WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_hdmi.c

Rev	Author	Line No.	Line
2330	Serge	1	/*
		2	* Copyright 2006 Dave Airlie
		3	* Copyright © 2006-2009 Intel Corporation
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice (including the next
		13	* paragraph) shall be included in all copies or substantial portions of the
		14	* Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		22	* DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors:
		25	* Eric Anholt
		26	* Jesse Barnes
		27	*/
		28
		29	#include
		30	#include
3031	serge	31	#include
4104	Serge	32	#include
3031	serge	33	#include
6084	serge	34	#include
3031	serge	35	#include
		36	#include
2330	Serge	37	#include "intel_drv.h"
3031	serge	38	#include
2330	Serge	39	#include "i915_drv.h"
		40
3243	Serge	41	static struct drm_device intel_hdmi_to_dev(struct intel_hdmi intel_hdmi)
		42	{
		43	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
		44	}
		45
3031	serge	46	static void
		47	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
		48	{
3243	Serge	49	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
3031	serge	50	struct drm_i915_private *dev_priv = dev->dev_private;
		51	uint32_t enabled_bits;
2330	Serge	52
3480	Serge	53	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
3031	serge	54
3746	Serge	55	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
3031	serge	56	"HDMI port enabled, expecting disabled\n");
		57	}
		58
		59	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
2330	Serge	60	{
3243	Serge	61	struct intel_digital_port *intel_dig_port =
		62	container_of(encoder, struct intel_digital_port, base.base);
		63	return &intel_dig_port->hdmi;
2330	Serge	64	}
		65
		66	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
		67	{
3243	Serge	68	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
2330	Serge	69	}
		70
4104	Serge	71	static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
2330	Serge	72	{
4104	Serge	73	switch (type) {
		74	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	75	return VIDEO_DIP_SELECT_AVI;
4104	Serge	76	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	77	return VIDEO_DIP_SELECT_SPD;
4104	Serge	78	case HDMI_INFOFRAME_TYPE_VENDOR:
		79	return VIDEO_DIP_SELECT_VENDOR;
3031	serge	80	default:
6937	serge	81	MISSING_CASE(type);
3031	serge	82	return 0;
		83	}
		84	}
2330	Serge	85
4104	Serge	86	static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
3031	serge	87	{
4104	Serge	88	switch (type) {
		89	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	90	return VIDEO_DIP_ENABLE_AVI;
4104	Serge	91	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	92	return VIDEO_DIP_ENABLE_SPD;
4104	Serge	93	case HDMI_INFOFRAME_TYPE_VENDOR:
		94	return VIDEO_DIP_ENABLE_VENDOR;
2330	Serge	95	default:
6937	serge	96	MISSING_CASE(type);
3031	serge	97	return 0;
2330	Serge	98	}
3031	serge	99	}
2330	Serge	100
4104	Serge	101	static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
3031	serge	102	{
4104	Serge	103	switch (type) {
		104	case HDMI_INFOFRAME_TYPE_AVI:
3031	serge	105	return VIDEO_DIP_ENABLE_AVI_HSW;
4104	Serge	106	case HDMI_INFOFRAME_TYPE_SPD:
3031	serge	107	return VIDEO_DIP_ENABLE_SPD_HSW;
4104	Serge	108	case HDMI_INFOFRAME_TYPE_VENDOR:
		109	return VIDEO_DIP_ENABLE_VS_HSW;
3031	serge	110	default:
6937	serge	111	MISSING_CASE(type);
3031	serge	112	return 0;
		113	}
2330	Serge	114	}
		115
6937	serge	116	static i915_reg_t
		117	hsw_dip_data_reg(struct drm_i915_private *dev_priv,
6084	serge	118	enum transcoder cpu_transcoder,
		119	enum hdmi_infoframe_type type,
		120	int i)
2330	Serge	121	{
4104	Serge	122	switch (type) {
		123	case HDMI_INFOFRAME_TYPE_AVI:
6084	serge	124	return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
4104	Serge	125	case HDMI_INFOFRAME_TYPE_SPD:
6084	serge	126	return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
4104	Serge	127	case HDMI_INFOFRAME_TYPE_VENDOR:
6084	serge	128	return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
2330	Serge	129	default:
6937	serge	130	MISSING_CASE(type);
		131	return INVALID_MMIO_REG;
2330	Serge	132	}
		133	}
		134
3031	serge	135	static void g4x_write_infoframe(struct drm_encoder *encoder,
4104	Serge	136	enum hdmi_infoframe_type type,
4560	Serge	137	const void *frame, ssize_t len)
2330	Serge	138	{
4560	Serge	139	const uint32_t *data = frame;
2330	Serge	140	struct drm_device *dev = encoder->dev;
		141	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	142	u32 val = I915_READ(VIDEO_DIP_CTL);
4104	Serge	143	int i;
2330	Serge	144
3031	serge	145	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
2330	Serge	146
3031	serge	147	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	148	val \|= g4x_infoframe_index(type);
2330	Serge	149
4104	Serge	150	val &= ~g4x_infoframe_enable(type);
2330	Serge	151
3031	serge	152	I915_WRITE(VIDEO_DIP_CTL, val);
2330	Serge	153
3031	serge	154	mmiowb();
2330	Serge	155	for (i = 0; i < len; i += 4) {
		156	I915_WRITE(VIDEO_DIP_DATA, *data);
		157	data++;
		158	}
3031	serge	159	/* Write every possible data byte to force correct ECC calculation. */
		160	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		161	I915_WRITE(VIDEO_DIP_DATA, 0);
		162	mmiowb();
2330	Serge	163
4104	Serge	164	val \|= g4x_infoframe_enable(type);
3031	serge	165	val &= ~VIDEO_DIP_FREQ_MASK;
		166	val \|= VIDEO_DIP_FREQ_VSYNC;
2330	Serge	167
3031	serge	168	I915_WRITE(VIDEO_DIP_CTL, val);
		169	POSTING_READ(VIDEO_DIP_CTL);
2330	Serge	170	}
		171
6937	serge	172	static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
		173	const struct intel_crtc_state *pipe_config)
5354	serge	174	{
6937	serge	175	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5354	serge	176	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		177	u32 val = I915_READ(VIDEO_DIP_CTL);
		178
6084	serge	179	if ((val & VIDEO_DIP_ENABLE) == 0)
		180	return false;
5354	serge	181
6084	serge	182	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		183	return false;
		184
		185	return val & (VIDEO_DIP_ENABLE_AVI \|
		186	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
5354	serge	187	}
		188
3031	serge	189	static void ibx_write_infoframe(struct drm_encoder *encoder,
4104	Serge	190	enum hdmi_infoframe_type type,
4560	Serge	191	const void *frame, ssize_t len)
2330	Serge	192	{
4560	Serge	193	const uint32_t *data = frame;
2330	Serge	194	struct drm_device *dev = encoder->dev;
		195	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	196	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	197	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	198	u32 val = I915_READ(reg);
6937	serge	199	int i;
2330	Serge	200
3031	serge	201	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
2330	Serge	202
3031	serge	203	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	204	val \|= g4x_infoframe_index(type);
2330	Serge	205
4104	Serge	206	val &= ~g4x_infoframe_enable(type);
3031	serge	207
		208	I915_WRITE(reg, val);
		209
		210	mmiowb();
		211	for (i = 0; i < len; i += 4) {
		212	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		213	data++;
		214	}
		215	/* Write every possible data byte to force correct ECC calculation. */
		216	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		217	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		218	mmiowb();
		219
4104	Serge	220	val \|= g4x_infoframe_enable(type);
3031	serge	221	val &= ~VIDEO_DIP_FREQ_MASK;
		222	val \|= VIDEO_DIP_FREQ_VSYNC;
		223
		224	I915_WRITE(reg, val);
		225	POSTING_READ(reg);
		226	}
		227
6937	serge	228	static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
		229	const struct intel_crtc_state *pipe_config)
5354	serge	230	{
6937	serge	231	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6084	serge	232	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
6937	serge	233	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		234	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
5354	serge	235	u32 val = I915_READ(reg);
		236
6084	serge	237	if ((val & VIDEO_DIP_ENABLE) == 0)
		238	return false;
		239
		240	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		241	return false;
		242
		243	return val & (VIDEO_DIP_ENABLE_AVI \|
		244	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		245	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	246	}
		247
3031	serge	248	static void cpt_write_infoframe(struct drm_encoder *encoder,
4104	Serge	249	enum hdmi_infoframe_type type,
4560	Serge	250	const void *frame, ssize_t len)
3031	serge	251	{
4560	Serge	252	const uint32_t *data = frame;
3031	serge	253	struct drm_device *dev = encoder->dev;
		254	struct drm_i915_private *dev_priv = dev->dev_private;
		255	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	256	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	257	u32 val = I915_READ(reg);
6937	serge	258	int i;
3031	serge	259
		260	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
		261
2342	Serge	262	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	263	val \|= g4x_infoframe_index(type);
2330	Serge	264
3031	serge	265	/* The DIP control register spec says that we need to update the AVI
		266	* infoframe without clearing its enable bit */
4104	Serge	267	if (type != HDMI_INFOFRAME_TYPE_AVI)
		268	val &= ~g4x_infoframe_enable(type);
2330	Serge	269
3031	serge	270	I915_WRITE(reg, val);
		271
		272	mmiowb();
2330	Serge	273	for (i = 0; i < len; i += 4) {
		274	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		275	data++;
		276	}
3031	serge	277	/* Write every possible data byte to force correct ECC calculation. */
		278	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		279	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		280	mmiowb();
2330	Serge	281
4104	Serge	282	val \|= g4x_infoframe_enable(type);
3031	serge	283	val &= ~VIDEO_DIP_FREQ_MASK;
		284	val \|= VIDEO_DIP_FREQ_VSYNC;
2330	Serge	285
3031	serge	286	I915_WRITE(reg, val);
		287	POSTING_READ(reg);
2330	Serge	288	}
3031	serge	289
6937	serge	290	static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
		291	const struct intel_crtc_state *pipe_config)
5354	serge	292	{
6937	serge	293	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
		294	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		295	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
5354	serge	296
6084	serge	297	if ((val & VIDEO_DIP_ENABLE) == 0)
		298	return false;
		299
		300	return val & (VIDEO_DIP_ENABLE_AVI \|
		301	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		302	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	303	}
		304
3031	serge	305	static void vlv_write_infoframe(struct drm_encoder *encoder,
4104	Serge	306	enum hdmi_infoframe_type type,
4560	Serge	307	const void *frame, ssize_t len)
3031	serge	308	{
4560	Serge	309	const uint32_t *data = frame;
3031	serge	310	struct drm_device *dev = encoder->dev;
		311	struct drm_i915_private *dev_priv = dev->dev_private;
		312	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6937	serge	313	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	314	u32 val = I915_READ(reg);
6937	serge	315	int i;
3031	serge	316
		317	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
		318
		319	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
4104	Serge	320	val \|= g4x_infoframe_index(type);
3031	serge	321
4104	Serge	322	val &= ~g4x_infoframe_enable(type);
3031	serge	323
		324	I915_WRITE(reg, val);
		325
		326	mmiowb();
		327	for (i = 0; i < len; i += 4) {
		328	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		329	data++;
		330	}
		331	/* Write every possible data byte to force correct ECC calculation. */
		332	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		333	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
		334	mmiowb();
		335
4104	Serge	336	val \|= g4x_infoframe_enable(type);
3031	serge	337	val &= ~VIDEO_DIP_FREQ_MASK;
		338	val \|= VIDEO_DIP_FREQ_VSYNC;
		339
		340	I915_WRITE(reg, val);
		341	POSTING_READ(reg);
		342	}
		343
6937	serge	344	static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
		345	const struct intel_crtc_state *pipe_config)
5354	serge	346	{
6937	serge	347	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6084	serge	348	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
6937	serge	349	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
		350	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
5354	serge	351
6084	serge	352	if ((val & VIDEO_DIP_ENABLE) == 0)
		353	return false;
		354
		355	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		356	return false;
		357
		358	return val & (VIDEO_DIP_ENABLE_AVI \|
		359	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		360	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
5354	serge	361	}
		362
3031	serge	363	static void hsw_write_infoframe(struct drm_encoder *encoder,
4104	Serge	364	enum hdmi_infoframe_type type,
4560	Serge	365	const void *frame, ssize_t len)
3031	serge	366	{
4560	Serge	367	const uint32_t *data = frame;
3031	serge	368	struct drm_device *dev = encoder->dev;
		369	struct drm_i915_private *dev_priv = dev->dev_private;
		370	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
6084	serge	371	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6937	serge	372	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
		373	i915_reg_t data_reg;
4104	Serge	374	int i;
3031	serge	375	u32 val = I915_READ(ctl_reg);
		376
6084	serge	377	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
3031	serge	378
4104	Serge	379	val &= ~hsw_infoframe_enable(type);
3031	serge	380	I915_WRITE(ctl_reg, val);
		381
		382	mmiowb();
		383	for (i = 0; i < len; i += 4) {
6084	serge	384	I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
		385	type, i >> 2), *data);
3031	serge	386	data++;
		387	}
		388	/* Write every possible data byte to force correct ECC calculation. */
		389	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
6084	serge	390	I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
		391	type, i >> 2), 0);
3031	serge	392	mmiowb();
		393
4104	Serge	394	val \|= hsw_infoframe_enable(type);
3031	serge	395	I915_WRITE(ctl_reg, val);
		396	POSTING_READ(ctl_reg);
		397	}
		398
6937	serge	399	static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
		400	const struct intel_crtc_state *pipe_config)
5354	serge	401	{
6937	serge	402	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
		403	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
5354	serge	404
6084	serge	405	return val & (VIDEO_DIP_ENABLE_VSC_HSW \| VIDEO_DIP_ENABLE_AVI_HSW \|
		406	VIDEO_DIP_ENABLE_GCP_HSW \| VIDEO_DIP_ENABLE_VS_HSW \|
		407	VIDEO_DIP_ENABLE_GMP_HSW \| VIDEO_DIP_ENABLE_SPD_HSW);
5354	serge	408	}
		409
4104	Serge	410	/*
		411	* The data we write to the DIP data buffer registers is 1 byte bigger than the
		412	* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
		413	* at 0). It's also a byte used by DisplayPort so the same DIP registers can be
		414	* used for both technologies.
		415	*
		416	* DW0: Reserved/ECC/DP \| HB2 \| HB1 \| HB0
		417	* DW1: DB3 \| DB2 \| DB1 \| DB0
		418	* DW2: DB7 \| DB6 \| DB5 \| DB4
		419	* DW3: ...
		420	*
		421	* (HB is Header Byte, DB is Data Byte)
		422	*
		423	* The hdmi pack() functions don't know about that hardware specific hole so we
		424	* trick them by giving an offset into the buffer and moving back the header
		425	* bytes by one.
		426	*/
		427	static void intel_write_infoframe(struct drm_encoder *encoder,
		428	union hdmi_infoframe *frame)
2330	Serge	429	{
		430	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
4104	Serge	431	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
		432	ssize_t len;
2330	Serge	433
4104	Serge	434	/* see comment above for the reason for this offset */
		435	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
		436	if (len < 0)
		437	return;
		438
		439	/* Insert the 'hole' (see big comment above) at position 3 */
		440	buffer[0] = buffer[1];
		441	buffer[1] = buffer[2];
		442	buffer[2] = buffer[3];
		443	buffer[3] = 0;
		444	len++;
		445
		446	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
2330	Serge	447	}
		448
3031	serge	449	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
6084	serge	450	const struct drm_display_mode *adjusted_mode)
2330	Serge	451	{
3480	Serge	452	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
3746	Serge	453	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
4104	Serge	454	union hdmi_infoframe frame;
		455	int ret;
2330	Serge	456
4104	Serge	457	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
		458	adjusted_mode);
		459	if (ret < 0) {
		460	DRM_ERROR("couldn't fill AVI infoframe\n");
		461	return;
		462	}
3031	serge	463
3480	Serge	464	if (intel_hdmi->rgb_quant_range_selectable) {
6084	serge	465	if (intel_crtc->config->limited_color_range)
4104	Serge	466	frame.avi.quantization_range =
		467	HDMI_QUANTIZATION_RANGE_LIMITED;
3480	Serge	468	else
4104	Serge	469	frame.avi.quantization_range =
		470	HDMI_QUANTIZATION_RANGE_FULL;
3480	Serge	471	}
3243	Serge	472
4104	Serge	473	intel_write_infoframe(encoder, &frame);
2330	Serge	474	}
		475
		476	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
		477	{
4104	Serge	478	union hdmi_infoframe frame;
		479	int ret;
2330	Serge	480
4104	Serge	481	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
		482	if (ret < 0) {
		483	DRM_ERROR("couldn't fill SPD infoframe\n");
		484	return;
		485	}
2330	Serge	486
4104	Serge	487	frame.spd.sdi = HDMI_SPD_SDI_PC;
		488
		489	intel_write_infoframe(encoder, &frame);
2330	Serge	490	}
		491
4104	Serge	492	static void
		493	intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
6084	serge	494	const struct drm_display_mode *adjusted_mode)
4104	Serge	495	{
		496	union hdmi_infoframe frame;
		497	int ret;
		498
		499	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
		500	adjusted_mode);
		501	if (ret < 0)
		502	return;
		503
		504	intel_write_infoframe(encoder, &frame);
		505	}
		506
3031	serge	507	static void g4x_set_infoframes(struct drm_encoder *encoder,
5060	serge	508	bool enable,
6084	serge	509	const struct drm_display_mode *adjusted_mode)
3031	serge	510	{
		511	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
3480	Serge	512	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		513	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
6937	serge	514	i915_reg_t reg = VIDEO_DIP_CTL;
3031	serge	515	u32 val = I915_READ(reg);
5060	serge	516	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	517
		518	assert_hdmi_port_disabled(intel_hdmi);
		519
		520	/* If the registers were not initialized yet, they might be zeroes,
		521	* which means we're selecting the AVI DIP and we're setting its
		522	* frequency to once. This seems to really confuse the HW and make
		523	* things stop working (the register spec says the AVI always needs to
		524	* be sent every VSync). So here we avoid writing to the register more
		525	* than we need and also explicitly select the AVI DIP and explicitly
		526	* set its frequency to every VSync. Avoiding to write it twice seems to
		527	* be enough to solve the problem, but being defensive shouldn't hurt us
		528	* either. */
		529	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		530
5060	serge	531	if (!enable) {
3031	serge	532	if (!(val & VIDEO_DIP_ENABLE))
		533	return;
6084	serge	534	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		535	DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
		536	(val & VIDEO_DIP_PORT_MASK) >> 29);
		537	return;
		538	}
		539	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		540	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
3031	serge	541	I915_WRITE(reg, val);
		542	POSTING_READ(reg);
		543	return;
		544	}
		545
		546	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		547	if (val & VIDEO_DIP_ENABLE) {
6084	serge	548	DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
		549	(val & VIDEO_DIP_PORT_MASK) >> 29);
		550	return;
3031	serge	551	}
		552	val &= ~VIDEO_DIP_PORT_MASK;
		553	val \|= port;
		554	}
		555
		556	val \|= VIDEO_DIP_ENABLE;
6084	serge	557	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		558	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_SPD);
3031	serge	559
		560	I915_WRITE(reg, val);
		561	POSTING_READ(reg);
		562
		563	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		564	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	565	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	566	}
		567
6084	serge	568	static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
		569	{
		570	struct drm_device *dev = encoder->dev;
		571	struct drm_connector *connector;
		572
		573	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
		574
		575	/*
		576	* HDMI cloning is only supported on g4x which doesn't
		577	* support deep color or GCP infoframes anyway so no
		578	* need to worry about multiple HDMI sinks here.
		579	*/
		580	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		581	if (connector->encoder == encoder)
		582	return connector->display_info.bpc > 8;
		583
		584	return false;
		585	}
		586
		587	/*
		588	* Determine if default_phase=1 can be indicated in the GCP infoframe.
		589	*
		590	* From HDMI specification 1.4a:
		591	* - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
		592	* - The first pixel following each Video Data Period shall have a pixel packing phase of 0
		593	* - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
		594	* - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
		595	* phase of 0
		596	*/
		597	static bool gcp_default_phase_possible(int pipe_bpp,
		598	const struct drm_display_mode *mode)
		599	{
		600	unsigned int pixels_per_group;
		601
		602	switch (pipe_bpp) {
		603	case 30:
		604	/* 4 pixels in 5 clocks */
		605	pixels_per_group = 4;
		606	break;
		607	case 36:
		608	/* 2 pixels in 3 clocks */
		609	pixels_per_group = 2;
		610	break;
		611	case 48:
		612	/* 1 pixel in 2 clocks */
		613	pixels_per_group = 1;
		614	break;
		615	default:
		616	/* phase information not relevant for 8bpc */
		617	return false;
		618	}
		619
		620	return mode->crtc_hdisplay % pixels_per_group == 0 &&
		621	mode->crtc_htotal % pixels_per_group == 0 &&
		622	mode->crtc_hblank_start % pixels_per_group == 0 &&
		623	mode->crtc_hblank_end % pixels_per_group == 0 &&
		624	mode->crtc_hsync_start % pixels_per_group == 0 &&
		625	mode->crtc_hsync_end % pixels_per_group == 0 &&
		626	((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 \|\|
		627	mode->crtc_htotal/2 % pixels_per_group == 0);
		628	}
		629
		630	static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
		631	{
		632	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		633	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6937	serge	634	i915_reg_t reg;
		635	u32 val = 0;
6084	serge	636
		637	if (HAS_DDI(dev_priv))
		638	reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
6937	serge	639	else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
6084	serge	640	reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
		641	else if (HAS_PCH_SPLIT(dev_priv->dev))
		642	reg = TVIDEO_DIP_GCP(crtc->pipe);
		643	else
		644	return false;
		645
		646	/* Indicate color depth whenever the sink supports deep color */
		647	if (hdmi_sink_is_deep_color(encoder))
		648	val \|= GCP_COLOR_INDICATION;
		649
		650	/* Enable default_phase whenever the display mode is suitably aligned */
		651	if (gcp_default_phase_possible(crtc->config->pipe_bpp,
		652	&crtc->config->base.adjusted_mode))
		653	val \|= GCP_DEFAULT_PHASE_ENABLE;
		654
		655	I915_WRITE(reg, val);
		656
		657	return val != 0;
		658	}
		659
3031	serge	660	static void ibx_set_infoframes(struct drm_encoder *encoder,
5060	serge	661	bool enable,
6084	serge	662	const struct drm_display_mode *adjusted_mode)
3031	serge	663	{
		664	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		665	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3480	Serge	666	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		667	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
6937	serge	668	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	669	u32 val = I915_READ(reg);
5060	serge	670	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	671
		672	assert_hdmi_port_disabled(intel_hdmi);
		673
		674	/* See the big comment in g4x_set_infoframes() */
		675	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		676
5060	serge	677	if (!enable) {
3031	serge	678	if (!(val & VIDEO_DIP_ENABLE))
		679	return;
6084	serge	680	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		681	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		682	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	683	I915_WRITE(reg, val);
		684	POSTING_READ(reg);
		685	return;
		686	}
		687
		688	if (port != (val & VIDEO_DIP_PORT_MASK)) {
6084	serge	689	WARN(val & VIDEO_DIP_ENABLE,
		690	"DIP already enabled on port %c\n",
		691	(val & VIDEO_DIP_PORT_MASK) >> 29);
3031	serge	692	val &= ~VIDEO_DIP_PORT_MASK;
		693	val \|= port;
		694	}
		695
		696	val \|= VIDEO_DIP_ENABLE;
6084	serge	697	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		698	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		699	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	700
6084	serge	701	if (intel_hdmi_set_gcp_infoframe(encoder))
		702	val \|= VIDEO_DIP_ENABLE_GCP;
		703
3031	serge	704	I915_WRITE(reg, val);
		705	POSTING_READ(reg);
		706
		707	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		708	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	709	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	710	}
		711
		712	static void cpt_set_infoframes(struct drm_encoder *encoder,
5060	serge	713	bool enable,
6084	serge	714	const struct drm_display_mode *adjusted_mode)
3031	serge	715	{
		716	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		717	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		718	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	719	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	720	u32 val = I915_READ(reg);
		721
		722	assert_hdmi_port_disabled(intel_hdmi);
		723
		724	/* See the big comment in g4x_set_infoframes() */
		725	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		726
5060	serge	727	if (!enable) {
3031	serge	728	if (!(val & VIDEO_DIP_ENABLE))
		729	return;
6084	serge	730	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		731	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		732	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	733	I915_WRITE(reg, val);
		734	POSTING_READ(reg);
		735	return;
		736	}
		737
		738	/* Set both together, unset both together: see the spec. */
		739	val \|= VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI;
		740	val &= ~(VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
6084	serge	741	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	742
6084	serge	743	if (intel_hdmi_set_gcp_infoframe(encoder))
		744	val \|= VIDEO_DIP_ENABLE_GCP;
		745
3031	serge	746	I915_WRITE(reg, val);
		747	POSTING_READ(reg);
		748
		749	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		750	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	751	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	752	}
		753
		754	static void vlv_set_infoframes(struct drm_encoder *encoder,
5060	serge	755	bool enable,
6084	serge	756	const struct drm_display_mode *adjusted_mode)
3031	serge	757	{
		758	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
5060	serge	759	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3031	serge	760	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		761	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	762	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
3031	serge	763	u32 val = I915_READ(reg);
5060	serge	764	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
3031	serge	765
		766	assert_hdmi_port_disabled(intel_hdmi);
		767
		768	/* See the big comment in g4x_set_infoframes() */
		769	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
		770
5060	serge	771	if (!enable) {
3031	serge	772	if (!(val & VIDEO_DIP_ENABLE))
		773	return;
6084	serge	774	val &= ~(VIDEO_DIP_ENABLE \| VIDEO_DIP_ENABLE_AVI \|
		775	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		776	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	777	I915_WRITE(reg, val);
		778	POSTING_READ(reg);
		779	return;
		780	}
		781
5060	serge	782	if (port != (val & VIDEO_DIP_PORT_MASK)) {
6084	serge	783	WARN(val & VIDEO_DIP_ENABLE,
		784	"DIP already enabled on port %c\n",
		785	(val & VIDEO_DIP_PORT_MASK) >> 29);
5060	serge	786	val &= ~VIDEO_DIP_PORT_MASK;
		787	val \|= port;
		788	}
		789
3031	serge	790	val \|= VIDEO_DIP_ENABLE;
6084	serge	791	val &= ~(VIDEO_DIP_ENABLE_AVI \|
		792	VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
		793	VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_ENABLE_GCP);
3031	serge	794
6084	serge	795	if (intel_hdmi_set_gcp_infoframe(encoder))
		796	val \|= VIDEO_DIP_ENABLE_GCP;
		797
3031	serge	798	I915_WRITE(reg, val);
		799	POSTING_READ(reg);
		800
		801	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		802	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	803	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	804	}
		805
		806	static void hsw_set_infoframes(struct drm_encoder *encoder,
5060	serge	807	bool enable,
6084	serge	808	const struct drm_display_mode *adjusted_mode)
3031	serge	809	{
		810	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		811	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
		812	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
6937	serge	813	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
3031	serge	814	u32 val = I915_READ(reg);
		815
		816	assert_hdmi_port_disabled(intel_hdmi);
		817
6084	serge	818	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW \| VIDEO_DIP_ENABLE_AVI_HSW \|
		819	VIDEO_DIP_ENABLE_GCP_HSW \| VIDEO_DIP_ENABLE_VS_HSW \|
		820	VIDEO_DIP_ENABLE_GMP_HSW \| VIDEO_DIP_ENABLE_SPD_HSW);
		821
5060	serge	822	if (!enable) {
6084	serge	823	I915_WRITE(reg, val);
3031	serge	824	POSTING_READ(reg);
		825	return;
		826	}
		827
6084	serge	828	if (intel_hdmi_set_gcp_infoframe(encoder))
		829	val \|= VIDEO_DIP_ENABLE_GCP_HSW;
3031	serge	830
		831	I915_WRITE(reg, val);
		832	POSTING_READ(reg);
		833
		834	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
		835	intel_hdmi_set_spd_infoframe(encoder);
4104	Serge	836	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
3031	serge	837	}
		838
5060	serge	839	static void intel_hdmi_prepare(struct intel_encoder *encoder)
2330	Serge	840	{
4104	Serge	841	struct drm_device *dev = encoder->base.dev;
2330	Serge	842	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	843	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		844	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
6084	serge	845	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
3746	Serge	846	u32 hdmi_val;
2330	Serge	847
3746	Serge	848	hdmi_val = SDVO_ENCODING_HDMI;
6084	serge	849	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
		850	hdmi_val \|= HDMI_COLOR_RANGE_16_235;
2330	Serge	851	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
3746	Serge	852	hdmi_val \|= SDVO_VSYNC_ACTIVE_HIGH;
2330	Serge	853	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
3746	Serge	854	hdmi_val \|= SDVO_HSYNC_ACTIVE_HIGH;
2330	Serge	855
6084	serge	856	if (crtc->config->pipe_bpp > 24)
3746	Serge	857	hdmi_val \|= HDMI_COLOR_FORMAT_12bpc;
2330	Serge	858	else
3746	Serge	859	hdmi_val \|= SDVO_COLOR_FORMAT_8bpc;
2330	Serge	860
6084	serge	861	if (crtc->config->has_hdmi_sink)
3746	Serge	862	hdmi_val \|= HDMI_MODE_SELECT_HDMI;
2330	Serge	863
6084	serge	864	if (HAS_PCH_CPT(dev))
4104	Serge	865	hdmi_val \|= SDVO_PIPE_SEL_CPT(crtc->pipe);
5060	serge	866	else if (IS_CHERRYVIEW(dev))
		867	hdmi_val \|= SDVO_PIPE_SEL_CHV(crtc->pipe);
3746	Serge	868	else
4104	Serge	869	hdmi_val \|= SDVO_PIPE_SEL(crtc->pipe);
2330	Serge	870
3746	Serge	871	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
		872	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	873	}
		874
3031	serge	875	static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
		876	enum pipe *pipe)
2330	Serge	877	{
3031	serge	878	struct drm_device *dev = encoder->base.dev;
2330	Serge	879	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	880	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5060	serge	881	enum intel_display_power_domain power_domain;
3031	serge	882	u32 tmp;
6937	serge	883	bool ret;
3031	serge	884
5060	serge	885	power_domain = intel_display_port_power_domain(encoder);
6937	serge	886	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
5060	serge	887	return false;
		888
6937	serge	889	ret = false;
		890
3746	Serge	891	tmp = I915_READ(intel_hdmi->hdmi_reg);
3031	serge	892
		893	if (!(tmp & SDVO_ENABLE))
6937	serge	894	goto out;
3031	serge	895
		896	if (HAS_PCH_CPT(dev))
		897	*pipe = PORT_TO_PIPE_CPT(tmp);
5060	serge	898	else if (IS_CHERRYVIEW(dev))
		899	*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
3031	serge	900	else
		901	*pipe = PORT_TO_PIPE(tmp);
		902
6937	serge	903	ret = true;
		904
		905	out:
		906	intel_display_power_put(dev_priv, power_domain);
		907
		908	return ret;
3031	serge	909	}
		910
4104	Serge	911	static void intel_hdmi_get_config(struct intel_encoder *encoder,
6084	serge	912	struct intel_crtc_state *pipe_config)
4104	Serge	913	{
		914	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5139	serge	915	struct drm_device *dev = encoder->base.dev;
		916	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	917	u32 tmp, flags = 0;
4560	Serge	918	int dotclock;
4104	Serge	919
		920	tmp = I915_READ(intel_hdmi->hdmi_reg);
		921
		922	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		923	flags \|= DRM_MODE_FLAG_PHSYNC;
		924	else
		925	flags \|= DRM_MODE_FLAG_NHSYNC;
		926
		927	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		928	flags \|= DRM_MODE_FLAG_PVSYNC;
		929	else
		930	flags \|= DRM_MODE_FLAG_NVSYNC;
		931
5060	serge	932	if (tmp & HDMI_MODE_SELECT_HDMI)
		933	pipe_config->has_hdmi_sink = true;
		934
6937	serge	935	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
5354	serge	936	pipe_config->has_infoframe = true;
		937
		938	if (tmp & SDVO_AUDIO_ENABLE)
5060	serge	939	pipe_config->has_audio = true;
		940
5139	serge	941	if (!HAS_PCH_SPLIT(dev) &&
		942	tmp & HDMI_COLOR_RANGE_16_235)
		943	pipe_config->limited_color_range = true;
		944
6084	serge	945	pipe_config->base.adjusted_mode.flags \|= flags;
4560	Serge	946
		947	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		948	dotclock = pipe_config->port_clock * 2 / 3;
		949	else
		950	dotclock = pipe_config->port_clock;
		951
6084	serge	952	if (pipe_config->pixel_multiplier)
		953	dotclock /= pipe_config->pixel_multiplier;
		954
4560	Serge	955	if (HAS_PCH_SPLIT(dev_priv->dev))
		956	ironlake_check_encoder_dotclock(pipe_config, dotclock);
		957
6084	serge	958	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
4104	Serge	959	}
		960
6084	serge	961	static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
3031	serge	962	{
6084	serge	963	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		964
		965	WARN_ON(!crtc->config->has_hdmi_sink);
		966	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
		967	pipe_name(crtc->pipe));
		968	intel_audio_codec_enable(encoder);
		969	}
		970
		971	static void g4x_enable_hdmi(struct intel_encoder *encoder)
		972	{
3031	serge	973	struct drm_device *dev = encoder->base.dev;
		974	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	975	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3031	serge	976	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2330	Serge	977	u32 temp;
		978
6084	serge	979	temp = I915_READ(intel_hdmi->hdmi_reg);
2342	Serge	980
6084	serge	981	temp \|= SDVO_ENABLE;
		982	if (crtc->config->has_audio)
		983	temp \|= SDVO_AUDIO_ENABLE;
		984
		985	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		986	POSTING_READ(intel_hdmi->hdmi_reg);
		987
		988	if (crtc->config->has_audio)
		989	intel_enable_hdmi_audio(encoder);
		990	}
		991
		992	static void ibx_enable_hdmi(struct intel_encoder *encoder)
		993	{
		994	struct drm_device *dev = encoder->base.dev;
		995	struct drm_i915_private *dev_priv = dev->dev_private;
		996	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		997	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		998	u32 temp;
		999
3746	Serge	1000	temp = I915_READ(intel_hdmi->hdmi_reg);
2330	Serge	1001
6084	serge	1002	temp \|= SDVO_ENABLE;
		1003	if (crtc->config->has_audio)
		1004	temp \|= SDVO_AUDIO_ENABLE;
3031	serge	1005
6084	serge	1006	/*
		1007	* HW workaround, need to write this twice for issue
		1008	* that may result in first write getting masked.
2330	Serge	1009	*/
6084	serge	1010	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1011	POSTING_READ(intel_hdmi->hdmi_reg);
		1012	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1013	POSTING_READ(intel_hdmi->hdmi_reg);
		1014
		1015	/*
		1016	* HW workaround, need to toggle enable bit off and on
		1017	* for 12bpc with pixel repeat.
		1018	*
		1019	* FIXME: BSpec says this should be done at the end of
		1020	* of the modeset sequence, so not sure if this isn't too soon.
		1021	*/
		1022	if (crtc->config->pipe_bpp > 24 &&
		1023	crtc->config->pixel_multiplier > 1) {
3746	Serge	1024	I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		1025	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1026
		1027	/*
		1028	* HW workaround, need to write this twice for issue
		1029	* that may result in first write getting masked.
		1030	*/
		1031	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1032	POSTING_READ(intel_hdmi->hdmi_reg);
		1033	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1034	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	1035	}
		1036
6084	serge	1037	if (crtc->config->has_audio)
		1038	intel_enable_hdmi_audio(encoder);
		1039	}
3031	serge	1040
6084	serge	1041	static void cpt_enable_hdmi(struct intel_encoder *encoder)
		1042	{
		1043	struct drm_device *dev = encoder->base.dev;
		1044	struct drm_i915_private *dev_priv = dev->dev_private;
		1045	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1046	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1047	enum pipe pipe = crtc->pipe;
		1048	u32 temp;
		1049
		1050	temp = I915_READ(intel_hdmi->hdmi_reg);
		1051
		1052	temp \|= SDVO_ENABLE;
		1053	if (crtc->config->has_audio)
		1054	temp \|= SDVO_AUDIO_ENABLE;
		1055
		1056	/*
		1057	* WaEnableHDMI8bpcBefore12bpc:snb,ivb
		1058	*
		1059	* The procedure for 12bpc is as follows:
		1060	* 1. disable HDMI clock gating
		1061	* 2. enable HDMI with 8bpc
		1062	* 3. enable HDMI with 12bpc
		1063	* 4. enable HDMI clock gating
		1064	*/
		1065
		1066	if (crtc->config->pipe_bpp > 24) {
		1067	I915_WRITE(TRANS_CHICKEN1(pipe),
		1068	I915_READ(TRANS_CHICKEN1(pipe)) \|
		1069	TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
		1070
		1071	temp &= ~SDVO_COLOR_FORMAT_MASK;
		1072	temp \|= SDVO_COLOR_FORMAT_8bpc;
		1073	}
		1074
3746	Serge	1075	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1076	POSTING_READ(intel_hdmi->hdmi_reg);
3031	serge	1077
6084	serge	1078	if (crtc->config->pipe_bpp > 24) {
		1079	temp &= ~SDVO_COLOR_FORMAT_MASK;
		1080	temp \|= HDMI_COLOR_FORMAT_12bpc;
		1081
3746	Serge	1082	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1083	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1084
		1085	I915_WRITE(TRANS_CHICKEN1(pipe),
		1086	I915_READ(TRANS_CHICKEN1(pipe)) &
		1087	~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2330	Serge	1088	}
5354	serge	1089
6084	serge	1090	if (crtc->config->has_audio)
		1091	intel_enable_hdmi_audio(encoder);
3031	serge	1092	}
2330	Serge	1093
4104	Serge	1094	static void vlv_enable_hdmi(struct intel_encoder *encoder)
		1095	{
		1096	}
		1097
3031	serge	1098	static void intel_disable_hdmi(struct intel_encoder *encoder)
		1099	{
		1100	struct drm_device *dev = encoder->base.dev;
		1101	struct drm_i915_private *dev_priv = dev->dev_private;
		1102	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
5354	serge	1103	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3031	serge	1104	u32 temp;
		1105
3746	Serge	1106	temp = I915_READ(intel_hdmi->hdmi_reg);
3031	serge	1107
6084	serge	1108	temp &= ~(SDVO_ENABLE \| SDVO_AUDIO_ENABLE);
3746	Serge	1109	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1110	POSTING_READ(intel_hdmi->hdmi_reg);
2330	Serge	1111
6084	serge	1112	/*
		1113	* HW workaround for IBX, we need to move the port
		1114	* to transcoder A after disabling it to allow the
		1115	* matching DP port to be enabled on transcoder A.
2330	Serge	1116	*/
6084	serge	1117	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
6937	serge	1118	/*
		1119	* We get CPU/PCH FIFO underruns on the other pipe when
		1120	* doing the workaround. Sweep them under the rug.
		1121	*/
		1122	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1123	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1124
6084	serge	1125	temp &= ~SDVO_PIPE_B_SELECT;
		1126	temp \|= SDVO_ENABLE;
		1127	/*
		1128	* HW workaround, need to write this twice for issue
		1129	* that may result in first write getting masked.
		1130	*/
3746	Serge	1131	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1132	POSTING_READ(intel_hdmi->hdmi_reg);
6084	serge	1133	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1134	POSTING_READ(intel_hdmi->hdmi_reg);
		1135
		1136	temp &= ~SDVO_ENABLE;
		1137	I915_WRITE(intel_hdmi->hdmi_reg, temp);
		1138	POSTING_READ(intel_hdmi->hdmi_reg);
6937	serge	1139
		1140	intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		1141	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		1142	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2330	Serge	1143	}
6084	serge	1144
		1145	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
2330	Serge	1146	}
		1147
6084	serge	1148	static void g4x_disable_hdmi(struct intel_encoder *encoder)
4104	Serge	1149	{
6084	serge	1150	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1151
		1152	if (crtc->config->has_audio)
		1153	intel_audio_codec_disable(encoder);
		1154
		1155	intel_disable_hdmi(encoder);
		1156	}
		1157
		1158	static void pch_disable_hdmi(struct intel_encoder *encoder)
		1159	{
		1160	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1161
		1162	if (crtc->config->has_audio)
		1163	intel_audio_codec_disable(encoder);
		1164	}
		1165
		1166	static void pch_post_disable_hdmi(struct intel_encoder *encoder)
		1167	{
		1168	intel_disable_hdmi(encoder);
		1169	}
		1170
		1171	static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
		1172	{
4104	Serge	1173	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1174
5060	serge	1175	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) \|\| IS_G4X(dev))
4104	Serge	1176	return 165000;
4560	Serge	1177	else if (IS_HASWELL(dev) \|\| INTEL_INFO(dev)->gen >= 8)
4104	Serge	1178	return 300000;
		1179	else
		1180	return 225000;
		1181	}
		1182
4560	Serge	1183	static enum drm_mode_status
6084	serge	1184	hdmi_port_clock_valid(struct intel_hdmi *hdmi,
		1185	int clock, bool respect_dvi_limit)
		1186	{
		1187	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1188
		1189	if (clock < 25000)
		1190	return MODE_CLOCK_LOW;
		1191	if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
		1192	return MODE_CLOCK_HIGH;
		1193
		1194	/* BXT DPLL can't generate 223-240 MHz */
		1195	if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
		1196	return MODE_CLOCK_RANGE;
		1197
		1198	/* CHV DPLL can't generate 216-240 MHz */
		1199	if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
		1200	return MODE_CLOCK_RANGE;
		1201
		1202	return MODE_OK;
		1203	}
		1204
		1205	static enum drm_mode_status
4560	Serge	1206	intel_hdmi_mode_valid(struct drm_connector *connector,
6084	serge	1207	struct drm_display_mode *mode)
2330	Serge	1208	{
6084	serge	1209	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
		1210	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
		1211	enum drm_mode_status status;
		1212	int clock;
5354	serge	1213
6084	serge	1214	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		1215	return MODE_NO_DBLESCAN;
		1216
		1217	clock = mode->clock;
5354	serge	1218	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		1219	clock *= 2;
		1220
6084	serge	1221	/* check if we can do 8bpc */
		1222	status = hdmi_port_clock_valid(hdmi, clock, true);
2330	Serge	1223
6084	serge	1224	/* if we can't do 8bpc we may still be able to do 12bpc */
		1225	if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
		1226	status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
2330	Serge	1227
6084	serge	1228	return status;
2330	Serge	1229	}
		1230
6084	serge	1231	static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
5060	serge	1232	{
6084	serge	1233	struct drm_device *dev = crtc_state->base.crtc->dev;
		1234	struct drm_atomic_state *state;
5060	serge	1235	struct intel_encoder *encoder;
6084	serge	1236	struct drm_connector *connector;
		1237	struct drm_connector_state *connector_state;
5060	serge	1238	int count = 0, count_hdmi = 0;
6084	serge	1239	int i;
5060	serge	1240
		1241	if (HAS_GMCH_DISPLAY(dev))
		1242	return false;
		1243
6084	serge	1244	state = crtc_state->base.state;
		1245
		1246	for_each_connector_in_state(state, connector, connector_state, i) {
		1247	if (connector_state->crtc != crtc_state->base.crtc)
5060	serge	1248	continue;
		1249
6084	serge	1250	encoder = to_intel_encoder(connector_state->best_encoder);
		1251
5060	serge	1252	count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
		1253	count++;
		1254	}
		1255
		1256	/*
		1257	* HDMI 12bpc affects the clocks, so it's only possible
		1258	* when not cloning with other encoder types.
		1259	*/
		1260	return count_hdmi > 0 && count_hdmi == count;
		1261	}
		1262
3746	Serge	1263	bool intel_hdmi_compute_config(struct intel_encoder *encoder,
6084	serge	1264	struct intel_crtc_state *pipe_config)
2330	Serge	1265	{
3746	Serge	1266	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1267	struct drm_device *dev = encoder->base.dev;
6084	serge	1268	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
		1269	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
		1270	int clock_12bpc = clock_8bpc * 3 / 2;
4104	Serge	1271	int desired_bpp;
2330	Serge	1272
5060	serge	1273	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
		1274
5354	serge	1275	if (pipe_config->has_hdmi_sink)
		1276	pipe_config->has_infoframe = true;
		1277
3480	Serge	1278	if (intel_hdmi->color_range_auto) {
		1279	/* See CEA-861-E - 5.1 Default Encoding Parameters */
6084	serge	1280	pipe_config->limited_color_range =
		1281	pipe_config->has_hdmi_sink &&
		1282	drm_match_cea_mode(adjusted_mode) > 1;
		1283	} else {
		1284	pipe_config->limited_color_range =
		1285	intel_hdmi->limited_color_range;
3031	serge	1286	}
		1287
5354	serge	1288	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
		1289	pipe_config->pixel_multiplier = 2;
6084	serge	1290	clock_8bpc *= 2;
		1291	clock_12bpc *= 2;
5354	serge	1292	}
		1293
3746	Serge	1294	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
		1295	pipe_config->has_pch_encoder = true;
		1296
5060	serge	1297	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
		1298	pipe_config->has_audio = true;
		1299
3746	Serge	1300	/*
		1301	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		1302	* through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
4104	Serge	1303	* outputs. We also need to check that the higher clock still fits
		1304	* within limits.
3746	Serge	1305	*/
5060	serge	1306	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
6084	serge	1307	hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
		1308	hdmi_12bpc_possible(pipe_config)) {
4104	Serge	1309	DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		1310	desired_bpp = 12*3;
		1311
		1312	/* Need to adjust the port link by 1.5x for 12bpc. */
		1313	pipe_config->port_clock = clock_12bpc;
3746	Serge	1314	} else {
4104	Serge	1315	DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		1316	desired_bpp = 8*3;
6084	serge	1317
		1318	pipe_config->port_clock = clock_8bpc;
3746	Serge	1319	}
		1320
4104	Serge	1321	if (!pipe_config->bw_constrained) {
		1322	DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		1323	pipe_config->pipe_bpp = desired_bpp;
		1324	}
		1325
6084	serge	1326	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
		1327	false) != MODE_OK) {
		1328	DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
4104	Serge	1329	return false;
		1330	}
		1331
6084	serge	1332	/* Set user selected PAR to incoming mode's member */
		1333	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
		1334
3480	Serge	1335	return true;
3031	serge	1336	}
		1337
5354	serge	1338	static void
		1339	intel_hdmi_unset_edid(struct drm_connector *connector)
2330	Serge	1340	{
		1341	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
5354	serge	1342
		1343	intel_hdmi->has_hdmi_sink = false;
		1344	intel_hdmi->has_audio = false;
		1345	intel_hdmi->rgb_quant_range_selectable = false;
		1346
		1347	kfree(to_intel_connector(connector)->detect_edid);
		1348	to_intel_connector(connector)->detect_edid = NULL;
		1349	}
		1350
		1351	static bool
6937	serge	1352	intel_hdmi_set_edid(struct drm_connector *connector, bool force)
5354	serge	1353	{
		1354	struct drm_i915_private *dev_priv = to_i915(connector->dev);
		1355	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
6937	serge	1356	struct edid *edid = NULL;
5354	serge	1357	bool connected = false;
2330	Serge	1358
6937	serge	1359	if (force) {
6084	serge	1360	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
5060	serge	1361
6084	serge	1362	edid = drm_get_edid(connector,
		1363	intel_gmbus_get_adapter(dev_priv,
		1364	intel_hdmi->ddc_bus));
2330	Serge	1365
6084	serge	1366	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
6937	serge	1367	}
5354	serge	1368
		1369	to_intel_connector(connector)->detect_edid = edid;
		1370	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6084	serge	1371	intel_hdmi->rgb_quant_range_selectable =
		1372	drm_rgb_quant_range_selectable(edid);
2330	Serge	1373
5354	serge	1374	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
3031	serge	1375	if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
		1376	intel_hdmi->has_audio =
5354	serge	1377	intel_hdmi->force_audio == HDMI_AUDIO_ON;
		1378
		1379	if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
		1380	intel_hdmi->has_hdmi_sink =
		1381	drm_detect_hdmi_monitor(edid);
		1382
		1383	connected = true;
2330	Serge	1384	}
		1385
5354	serge	1386	return connected;
		1387	}
5060	serge	1388
5354	serge	1389	static enum drm_connector_status
		1390	intel_hdmi_detect(struct drm_connector *connector, bool force)
		1391	{
		1392	enum drm_connector_status status;
6937	serge	1393	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
6084	serge	1394	struct drm_i915_private *dev_priv = to_i915(connector->dev);
6937	serge	1395	bool live_status = false;
		1396	unsigned int try;
5354	serge	1397
		1398	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		1399	connector->base.id, connector->name);
		1400
6084	serge	1401	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
		1402
6937	serge	1403	for (try = 0; !live_status && try < 9; try++) {
		1404	if (try)
		1405	msleep(10);
		1406	live_status = intel_digital_port_connected(dev_priv,
		1407	hdmi_to_dig_port(intel_hdmi));
		1408	}
		1409
		1410	if (!live_status) {
		1411	DRM_DEBUG_KMS("HDMI live status down\n");
		1412	/*
		1413	* Live status register is not reliable on all intel platforms.
		1414	* So consider live_status only for certain platforms, for
		1415	* others, read EDID to determine presence of sink.
		1416	*/
		1417	if (INTEL_INFO(dev_priv)->gen < 7 \|\| IS_IVYBRIDGE(dev_priv))
		1418	live_status = true;
		1419	}
		1420
5354	serge	1421	intel_hdmi_unset_edid(connector);
		1422
6937	serge	1423	if (intel_hdmi_set_edid(connector, live_status)) {
5354	serge	1424	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
		1425
		1426	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		1427	status = connector_status_connected;
		1428	} else
		1429	status = connector_status_disconnected;
		1430
6084	serge	1431	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
		1432
2330	Serge	1433	return status;
		1434	}
		1435
5354	serge	1436	static void
		1437	intel_hdmi_force(struct drm_connector *connector)
2330	Serge	1438	{
5354	serge	1439	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2330	Serge	1440
5354	serge	1441	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		1442	connector->base.id, connector->name);
2330	Serge	1443
5354	serge	1444	intel_hdmi_unset_edid(connector);
5060	serge	1445
5354	serge	1446	if (connector->status != connector_status_connected)
		1447	return;
5060	serge	1448
6937	serge	1449	intel_hdmi_set_edid(connector, true);
5354	serge	1450	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		1451	}
5060	serge	1452
5354	serge	1453	static int intel_hdmi_get_modes(struct drm_connector *connector)
		1454	{
		1455	struct edid *edid;
		1456
		1457	edid = to_intel_connector(connector)->detect_edid;
		1458	if (edid == NULL)
		1459	return 0;
		1460
		1461	return intel_connector_update_modes(connector, edid);
2330	Serge	1462	}
		1463
		1464	static bool
		1465	intel_hdmi_detect_audio(struct drm_connector *connector)
		1466	{
5354	serge	1467	bool has_audio = false;
2330	Serge	1468	struct edid *edid;
		1469
5354	serge	1470	edid = to_intel_connector(connector)->detect_edid;
		1471	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
6084	serge	1472	has_audio = drm_detect_monitor_audio(edid);
2330	Serge	1473
		1474	return has_audio;
		1475	}
		1476
		1477	static int
		1478	intel_hdmi_set_property(struct drm_connector *connector,
6084	serge	1479	struct drm_property *property,
		1480	uint64_t val)
2330	Serge	1481	{
		1482	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
3243	Serge	1483	struct intel_digital_port *intel_dig_port =
		1484	hdmi_to_dig_port(intel_hdmi);
2330	Serge	1485	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1486	int ret;
		1487
3243	Serge	1488	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	1489	if (ret)
		1490	return ret;
3480	Serge	1491
2330	Serge	1492	if (property == dev_priv->force_audio_property) {
3031	serge	1493	enum hdmi_force_audio i = val;
2330	Serge	1494	bool has_audio;
		1495
		1496	if (i == intel_hdmi->force_audio)
		1497	return 0;
		1498
		1499	intel_hdmi->force_audio = i;
		1500
3031	serge	1501	if (i == HDMI_AUDIO_AUTO)
2330	Serge	1502	has_audio = intel_hdmi_detect_audio(connector);
		1503	else
3031	serge	1504	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	1505
3031	serge	1506	if (i == HDMI_AUDIO_OFF_DVI)
		1507	intel_hdmi->has_hdmi_sink = 0;
2330	Serge	1508
		1509	intel_hdmi->has_audio = has_audio;
		1510	goto done;
		1511	}
		1512
		1513	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	1514	bool old_auto = intel_hdmi->color_range_auto;
6084	serge	1515	bool old_range = intel_hdmi->limited_color_range;
3746	Serge	1516
3480	Serge	1517	switch (val) {
		1518	case INTEL_BROADCAST_RGB_AUTO:
		1519	intel_hdmi->color_range_auto = true;
		1520	break;
		1521	case INTEL_BROADCAST_RGB_FULL:
		1522	intel_hdmi->color_range_auto = false;
6084	serge	1523	intel_hdmi->limited_color_range = false;
3480	Serge	1524	break;
		1525	case INTEL_BROADCAST_RGB_LIMITED:
		1526	intel_hdmi->color_range_auto = false;
6084	serge	1527	intel_hdmi->limited_color_range = true;
3480	Serge	1528	break;
		1529	default:
		1530	return -EINVAL;
		1531	}
3746	Serge	1532
		1533	if (old_auto == intel_hdmi->color_range_auto &&
6084	serge	1534	old_range == intel_hdmi->limited_color_range)
3746	Serge	1535	return 0;
		1536
2330	Serge	1537	goto done;
		1538	}
3031	serge	1539
5060	serge	1540	if (property == connector->dev->mode_config.aspect_ratio_property) {
		1541	switch (val) {
		1542	case DRM_MODE_PICTURE_ASPECT_NONE:
		1543	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
		1544	break;
		1545	case DRM_MODE_PICTURE_ASPECT_4_3:
		1546	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
		1547	break;
		1548	case DRM_MODE_PICTURE_ASPECT_16_9:
		1549	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
		1550	break;
		1551	default:
		1552	return -EINVAL;
		1553	}
		1554	goto done;
		1555	}
		1556
2330	Serge	1557	return -EINVAL;
		1558
		1559	done:
3480	Serge	1560	if (intel_dig_port->base.base.crtc)
		1561	intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
2330	Serge	1562
		1563	return 0;
		1564	}
		1565
5060	serge	1566	static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
		1567	{
		1568	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		1569	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
6084	serge	1570	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060	serge	1571
		1572	intel_hdmi_prepare(encoder);
		1573
		1574	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	1575	intel_crtc->config->has_hdmi_sink,
5060	serge	1576	adjusted_mode);
		1577	}
		1578
4560	Serge	1579	static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
4104	Serge	1580	{
		1581	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
5060	serge	1582	struct intel_hdmi *intel_hdmi = &dport->hdmi;
4104	Serge	1583	struct drm_device *dev = encoder->base.dev;
		1584	struct drm_i915_private *dev_priv = dev->dev_private;
		1585	struct intel_crtc *intel_crtc =
		1586	to_intel_crtc(encoder->base.crtc);
6084	serge	1587	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
4560	Serge	1588	enum dpio_channel port = vlv_dport_to_channel(dport);
4104	Serge	1589	int pipe = intel_crtc->pipe;
		1590	u32 val;
		1591
		1592	/* Enable clock channels for this port */
6084	serge	1593	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1594	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
4104	Serge	1595	val = 0;
		1596	if (pipe)
		1597	val \|= (1<<21);
		1598	else
		1599	val &= ~(1<<21);
		1600	val \|= 0x001000c4;
4560	Serge	1601	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
4104	Serge	1602
		1603	/* HDMI 1.0V-2dB */
4560	Serge	1604	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
		1605	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
		1606	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
		1607	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
		1608	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
		1609	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
		1610	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
		1611	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
4104	Serge	1612
		1613	/* Program lane clock */
4560	Serge	1614	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
		1615	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
6084	serge	1616	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1617
5060	serge	1618	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	1619	intel_crtc->config->has_hdmi_sink,
5060	serge	1620	adjusted_mode);
		1621
6084	serge	1622	g4x_enable_hdmi(encoder);
4104	Serge	1623
6084	serge	1624	vlv_wait_port_ready(dev_priv, dport, 0x0);
4104	Serge	1625	}
		1626
4560	Serge	1627	static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
4104	Serge	1628	{
		1629	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1630	struct drm_device *dev = encoder->base.dev;
		1631	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	1632	struct intel_crtc *intel_crtc =
		1633	to_intel_crtc(encoder->base.crtc);
		1634	enum dpio_channel port = vlv_dport_to_channel(dport);
		1635	int pipe = intel_crtc->pipe;
4104	Serge	1636
5060	serge	1637	intel_hdmi_prepare(encoder);
4104	Serge	1638
		1639	/* Program Tx lane resets to default */
6084	serge	1640	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1641	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
4104	Serge	1642	DPIO_PCS_TX_LANE2_RESET \|
		1643	DPIO_PCS_TX_LANE1_RESET);
4560	Serge	1644	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
4104	Serge	1645	DPIO_PCS_CLK_CRI_RXEB_EIOS_EN \|
		1646	DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN \|
		1647	(1<
		1648	DPIO_PCS_CLK_SOFT_RESET);
		1649
		1650	/* Fix up inter-pair skew failure */
4560	Serge	1651	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
		1652	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
		1653	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
4104	Serge	1654
4560	Serge	1655	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
		1656	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
6084	serge	1657	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1658	}
		1659
6084	serge	1660	static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
		1661	bool reset)
		1662	{
		1663	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		1664	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
		1665	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1666	enum pipe pipe = crtc->pipe;
		1667	uint32_t val;
		1668
		1669	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
		1670	if (reset)
		1671	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		1672	else
		1673	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
		1674	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
		1675
		1676	if (crtc->config->lane_count > 2) {
		1677	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		1678	if (reset)
		1679	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		1680	else
		1681	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
		1682	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
		1683	}
		1684
		1685	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
		1686	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		1687	if (reset)
		1688	val &= ~DPIO_PCS_CLK_SOFT_RESET;
		1689	else
		1690	val \|= DPIO_PCS_CLK_SOFT_RESET;
		1691	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
		1692
		1693	if (crtc->config->lane_count > 2) {
		1694	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		1695	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		1696	if (reset)
		1697	val &= ~DPIO_PCS_CLK_SOFT_RESET;
		1698	else
		1699	val \|= DPIO_PCS_CLK_SOFT_RESET;
		1700	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
		1701	}
		1702	}
		1703
5060	serge	1704	static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
		1705	{
		1706	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1707	struct drm_device *dev = encoder->base.dev;
		1708	struct drm_i915_private *dev_priv = dev->dev_private;
		1709	struct intel_crtc *intel_crtc =
		1710	to_intel_crtc(encoder->base.crtc);
		1711	enum dpio_channel ch = vlv_dport_to_channel(dport);
		1712	enum pipe pipe = intel_crtc->pipe;
		1713	u32 val;
		1714
5354	serge	1715	intel_hdmi_prepare(encoder);
		1716
6084	serge	1717	/*
		1718	* Must trick the second common lane into life.
		1719	* Otherwise we can't even access the PLL.
		1720	*/
		1721	if (ch == DPIO_CH0 && pipe == PIPE_B)
		1722	dport->release_cl2_override =
		1723	!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
5060	serge	1724
6084	serge	1725	chv_phy_powergate_lanes(encoder, true, 0x0);
		1726
		1727	mutex_lock(&dev_priv->sb_lock);
		1728
		1729	/* Assert data lane reset */
		1730	chv_data_lane_soft_reset(encoder, true);
		1731
5060	serge	1732	/* program left/right clock distribution */
		1733	if (pipe != PIPE_B) {
		1734	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		1735	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		1736	if (ch == DPIO_CH0)
		1737	val \|= CHV_BUFLEFTENA1_FORCE;
		1738	if (ch == DPIO_CH1)
		1739	val \|= CHV_BUFRIGHTENA1_FORCE;
		1740	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		1741	} else {
		1742	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		1743	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		1744	if (ch == DPIO_CH0)
		1745	val \|= CHV_BUFLEFTENA2_FORCE;
		1746	if (ch == DPIO_CH1)
		1747	val \|= CHV_BUFRIGHTENA2_FORCE;
		1748	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		1749	}
		1750
		1751	/* program clock channel usage */
		1752	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
		1753	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		1754	if (pipe != PIPE_B)
		1755	val &= ~CHV_PCS_USEDCLKCHANNEL;
		1756	else
		1757	val \|= CHV_PCS_USEDCLKCHANNEL;
		1758	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
		1759
		1760	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		1761	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		1762	if (pipe != PIPE_B)
		1763	val &= ~CHV_PCS_USEDCLKCHANNEL;
		1764	else
		1765	val \|= CHV_PCS_USEDCLKCHANNEL;
		1766	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
		1767
		1768	/*
		1769	* This a a bit weird since generally CL
		1770	* matches the pipe, but here we need to
		1771	* pick the CL based on the port.
		1772	*/
		1773	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
		1774	if (pipe != PIPE_B)
		1775	val &= ~CHV_CMN_USEDCLKCHANNEL;
		1776	else
		1777	val \|= CHV_CMN_USEDCLKCHANNEL;
		1778	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
		1779
6084	serge	1780	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1781	}
		1782
6084	serge	1783	static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
		1784	{
		1785	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		1786	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		1787	u32 val;
		1788
		1789	mutex_lock(&dev_priv->sb_lock);
		1790
		1791	/* disable left/right clock distribution */
		1792	if (pipe != PIPE_B) {
		1793	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		1794	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		1795	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		1796	} else {
		1797	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		1798	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		1799	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		1800	}
		1801
		1802	mutex_unlock(&dev_priv->sb_lock);
		1803
		1804	/*
		1805	* Leave the power down bit cleared for at least one
		1806	* lane so that chv_powergate_phy_ch() will power
		1807	* on something when the channel is otherwise unused.
		1808	* When the port is off and the override is removed
		1809	* the lanes power down anyway, so otherwise it doesn't
		1810	* really matter what the state of power down bits is
		1811	* after this.
		1812	*/
		1813	chv_phy_powergate_lanes(encoder, false, 0x0);
		1814	}
		1815
4560	Serge	1816	static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
4104	Serge	1817	{
		1818	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1819	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
4560	Serge	1820	struct intel_crtc *intel_crtc =
		1821	to_intel_crtc(encoder->base.crtc);
		1822	enum dpio_channel port = vlv_dport_to_channel(dport);
		1823	int pipe = intel_crtc->pipe;
4104	Serge	1824
		1825	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
6084	serge	1826	mutex_lock(&dev_priv->sb_lock);
4560	Serge	1827	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
		1828	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
6084	serge	1829	mutex_unlock(&dev_priv->sb_lock);
4104	Serge	1830	}
		1831
5060	serge	1832	static void chv_hdmi_post_disable(struct intel_encoder *encoder)
		1833	{
		1834	struct drm_device *dev = encoder->base.dev;
		1835	struct drm_i915_private *dev_priv = dev->dev_private;
		1836
6084	serge	1837	mutex_lock(&dev_priv->sb_lock);
5060	serge	1838
6084	serge	1839	/* Assert data lane reset */
		1840	chv_data_lane_soft_reset(encoder, true);
5060	serge	1841
6084	serge	1842	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1843	}
		1844
		1845	static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
		1846	{
		1847	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
5354	serge	1848	struct intel_hdmi *intel_hdmi = &dport->hdmi;
5060	serge	1849	struct drm_device *dev = encoder->base.dev;
		1850	struct drm_i915_private *dev_priv = dev->dev_private;
		1851	struct intel_crtc *intel_crtc =
		1852	to_intel_crtc(encoder->base.crtc);
6084	serge	1853	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
5060	serge	1854	enum dpio_channel ch = vlv_dport_to_channel(dport);
		1855	int pipe = intel_crtc->pipe;
6084	serge	1856	int data, i, stagger;
5060	serge	1857	u32 val;
		1858
6084	serge	1859	mutex_lock(&dev_priv->sb_lock);
5060	serge	1860
5354	serge	1861	/* allow hardware to manage TX FIFO reset source */
		1862	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
		1863	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		1864	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
		1865
		1866	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		1867	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		1868	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
		1869
5060	serge	1870	/* Program Tx latency optimal setting */
		1871	for (i = 0; i < 4; i++) {
		1872	/* Set the upar bit */
		1873	data = (i == 1) ? 0x0 : 0x1;
		1874	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
		1875	data << DPIO_UPAR_SHIFT);
		1876	}
		1877
		1878	/* Data lane stagger programming */
6084	serge	1879	if (intel_crtc->config->port_clock > 270000)
		1880	stagger = 0x18;
		1881	else if (intel_crtc->config->port_clock > 135000)
		1882	stagger = 0xd;
		1883	else if (intel_crtc->config->port_clock > 67500)
		1884	stagger = 0x7;
		1885	else if (intel_crtc->config->port_clock > 33750)
		1886	stagger = 0x4;
		1887	else
		1888	stagger = 0x2;
5060	serge	1889
6084	serge	1890	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
		1891	val \|= DPIO_TX2_STAGGER_MASK(0x1f);
		1892	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
		1893
		1894	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		1895	val \|= DPIO_TX2_STAGGER_MASK(0x1f);
		1896	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
		1897
		1898	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		1899	DPIO_LANESTAGGER_STRAP(stagger) \|
		1900	DPIO_LANESTAGGER_STRAP_OVRD \|
		1901	DPIO_TX1_STAGGER_MASK(0x1f) \|
		1902	DPIO_TX1_STAGGER_MULT(6) \|
		1903	DPIO_TX2_STAGGER_MULT(0));
		1904
		1905	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
		1906	DPIO_LANESTAGGER_STRAP(stagger) \|
		1907	DPIO_LANESTAGGER_STRAP_OVRD \|
		1908	DPIO_TX1_STAGGER_MASK(0x1f) \|
		1909	DPIO_TX1_STAGGER_MULT(7) \|
		1910	DPIO_TX2_STAGGER_MULT(5));
		1911
		1912	/* Deassert data lane reset */
		1913	chv_data_lane_soft_reset(encoder, false);
		1914
5060	serge	1915	/* Clear calc init */
		1916	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		1917	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
5354	serge	1918	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
		1919	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
5060	serge	1920	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		1921
		1922	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		1923	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
5354	serge	1924	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
		1925	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
5060	serge	1926	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		1927
5354	serge	1928	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
		1929	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
		1930	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
		1931	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
		1932
		1933	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		1934	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
		1935	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
		1936	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
		1937
5060	serge	1938	/* FIXME: Program the support xxx V-dB */
		1939	/* Use 800mV-0dB */
		1940	for (i = 0; i < 4; i++) {
		1941	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		1942	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		1943	val \|= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
		1944	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
		1945	}
		1946
		1947	for (i = 0; i < 4; i++) {
		1948	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
6084	serge	1949
5354	serge	1950	val &= ~DPIO_SWING_MARGIN000_MASK;
		1951	val \|= 102 << DPIO_SWING_MARGIN000_SHIFT;
6084	serge	1952
		1953	/*
		1954	* Supposedly this value shouldn't matter when unique transition
		1955	* scale is disabled, but in fact it does matter. Let's just
		1956	* always program the same value and hope it's OK.
		1957	*/
		1958	val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		1959	val \|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
		1960
5060	serge	1961	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		1962	}
		1963
6084	serge	1964	/*
		1965	* The document said it needs to set bit 27 for ch0 and bit 26
		1966	* for ch1. Might be a typo in the doc.
		1967	* For now, for this unique transition scale selection, set bit
		1968	* 27 for ch0 and ch1.
		1969	*/
5060	serge	1970	for (i = 0; i < 4; i++) {
		1971	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		1972	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		1973	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		1974	}
		1975
		1976	/* Start swing calculation */
		1977	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		1978	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		1979	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		1980
		1981	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		1982	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		1983	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		1984
6084	serge	1985	mutex_unlock(&dev_priv->sb_lock);
5060	serge	1986
5354	serge	1987	intel_hdmi->set_infoframes(&encoder->base,
6084	serge	1988	intel_crtc->config->has_hdmi_sink,
5354	serge	1989	adjusted_mode);
		1990
6084	serge	1991	g4x_enable_hdmi(encoder);
5060	serge	1992
6084	serge	1993	vlv_wait_port_ready(dev_priv, dport, 0x0);
		1994
		1995	/* Second common lane will stay alive on its own now */
		1996	if (dport->release_cl2_override) {
		1997	chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		1998	dport->release_cl2_override = false;
		1999	}
5060	serge	2000	}
		2001
2330	Serge	2002	static void intel_hdmi_destroy(struct drm_connector *connector)
		2003	{
5354	serge	2004	kfree(to_intel_connector(connector)->detect_edid);
2330	Serge	2005	drm_connector_cleanup(connector);
		2006	kfree(connector);
		2007	}
		2008
		2009	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
6084	serge	2010	.dpms = drm_atomic_helper_connector_dpms,
2330	Serge	2011	.detect = intel_hdmi_detect,
5354	serge	2012	.force = intel_hdmi_force,
2330	Serge	2013	.fill_modes = drm_helper_probe_single_connector_modes,
		2014	.set_property = intel_hdmi_set_property,
6084	serge	2015	.atomic_get_property = intel_connector_atomic_get_property,
2330	Serge	2016	.destroy = intel_hdmi_destroy,
6084	serge	2017	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
		2018	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2330	Serge	2019	};
		2020
		2021	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
		2022	.get_modes = intel_hdmi_get_modes,
		2023	.mode_valid = intel_hdmi_mode_valid,
		2024	.best_encoder = intel_best_encoder,
		2025	};
		2026
		2027	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
		2028	.destroy = intel_encoder_destroy,
		2029	};
		2030
		2031	static void
		2032	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
		2033	{
		2034	intel_attach_force_audio_property(connector);
		2035	intel_attach_broadcast_rgb_property(connector);
3480	Serge	2036	intel_hdmi->color_range_auto = true;
5060	serge	2037	intel_attach_aspect_ratio_property(connector);
		2038	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2330	Serge	2039	}
		2040
3243	Serge	2041	void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
		2042	struct intel_connector *intel_connector)
2330	Serge	2043	{
3243	Serge	2044	struct drm_connector *connector = &intel_connector->base;
		2045	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
		2046	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		2047	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	2048	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2049	enum port port = intel_dig_port->port;
6937	serge	2050	uint8_t alternate_ddc_pin;
2330	Serge	2051
		2052	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
		2053	DRM_MODE_CONNECTOR_HDMIA);
		2054	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
		2055
3031	serge	2056	connector->interlace_allowed = 1;
2330	Serge	2057	connector->doublescan_allowed = 0;
4560	Serge	2058	connector->stereo_allowed = 1;
2330	Serge	2059
3031	serge	2060	switch (port) {
		2061	case PORT_B:
6937	serge	2062	if (IS_BROXTON(dev_priv))
		2063	intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
		2064	else
		2065	intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
6084	serge	2066	/*
		2067	* On BXT A0/A1, sw needs to activate DDIA HPD logic and
		2068	* interrupts to check the external panel connection.
		2069	*/
6937	serge	2070	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
6084	serge	2071	intel_encoder->hpd_pin = HPD_PORT_A;
		2072	else
		2073	intel_encoder->hpd_pin = HPD_PORT_B;
3031	serge	2074	break;
		2075	case PORT_C:
6937	serge	2076	if (IS_BROXTON(dev_priv))
		2077	intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
		2078	else
		2079	intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
3746	Serge	2080	intel_encoder->hpd_pin = HPD_PORT_C;
3031	serge	2081	break;
		2082	case PORT_D:
6937	serge	2083	if (WARN_ON(IS_BROXTON(dev_priv)))
		2084	intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
		2085	else if (IS_CHERRYVIEW(dev_priv))
		2086	intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
		2087	else
		2088	intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
3746	Serge	2089	intel_encoder->hpd_pin = HPD_PORT_D;
3031	serge	2090	break;
6084	serge	2091	case PORT_E:
6937	serge	2092	/* On SKL PORT E doesn't have seperate GMBUS pin
		2093	* We rely on VBT to set a proper alternate GMBUS pin. */
		2094	alternate_ddc_pin =
		2095	dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
		2096	switch (alternate_ddc_pin) {
		2097	case DDC_PIN_B:
		2098	intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
		2099	break;
		2100	case DDC_PIN_C:
		2101	intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
		2102	break;
		2103	case DDC_PIN_D:
		2104	intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
		2105	break;
		2106	default:
		2107	MISSING_CASE(alternate_ddc_pin);
		2108	}
6084	serge	2109	intel_encoder->hpd_pin = HPD_PORT_E;
		2110	break;
6937	serge	2111	case PORT_A:
		2112	intel_encoder->hpd_pin = HPD_PORT_A;
		2113	/* Internal port only for eDP. */
3031	serge	2114	default:
6937	serge	2115	BUG();
2330	Serge	2116	}
		2117
6937	serge	2118	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev)) {
3746	Serge	2119	intel_hdmi->write_infoframe = vlv_write_infoframe;
		2120	intel_hdmi->set_infoframes = vlv_set_infoframes;
5354	serge	2121	intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
5060	serge	2122	} else if (IS_G4X(dev)) {
3031	serge	2123	intel_hdmi->write_infoframe = g4x_write_infoframe;
		2124	intel_hdmi->set_infoframes = g4x_set_infoframes;
5354	serge	2125	intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
3746	Serge	2126	} else if (HAS_DDI(dev)) {
3031	serge	2127	intel_hdmi->write_infoframe = hsw_write_infoframe;
		2128	intel_hdmi->set_infoframes = hsw_set_infoframes;
5354	serge	2129	intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
3031	serge	2130	} else if (HAS_PCH_IBX(dev)) {
		2131	intel_hdmi->write_infoframe = ibx_write_infoframe;
		2132	intel_hdmi->set_infoframes = ibx_set_infoframes;
5354	serge	2133	intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2342	Serge	2134	} else {
3031	serge	2135	intel_hdmi->write_infoframe = cpt_write_infoframe;
		2136	intel_hdmi->set_infoframes = cpt_set_infoframes;
5354	serge	2137	intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2342	Serge	2138	}
2330	Serge	2139
3480	Serge	2140	if (HAS_DDI(dev))
3243	Serge	2141	intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
		2142	else
6084	serge	2143	intel_connector->get_hw_state = intel_connector_get_hw_state;
5060	serge	2144	intel_connector->unregister = intel_connector_unregister;
2330	Serge	2145
		2146	intel_hdmi_add_properties(intel_hdmi, connector);
		2147
		2148	intel_connector_attach_encoder(intel_connector, intel_encoder);
5060	serge	2149	drm_connector_register(connector);
6084	serge	2150	intel_hdmi->attached_connector = intel_connector;
2330	Serge	2151
		2152	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		2153	* 0xd. Failure to do so will result in spurious interrupts being
		2154	* generated on the port when a cable is not attached.
		2155	*/
		2156	if (IS_G4X(dev) && !IS_GM45(dev)) {
		2157	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		2158	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		2159	}
		2160	}
3243	Serge	2161
6937	serge	2162	void intel_hdmi_init(struct drm_device *dev,
		2163	i915_reg_t hdmi_reg, enum port port)
3243	Serge	2164	{
		2165	struct intel_digital_port *intel_dig_port;
		2166	struct intel_encoder *intel_encoder;
		2167	struct intel_connector *intel_connector;
		2168
4560	Serge	2169	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	2170	if (!intel_dig_port)
		2171	return;
		2172
6084	serge	2173	intel_connector = intel_connector_alloc();
3243	Serge	2174	if (!intel_connector) {
		2175	kfree(intel_dig_port);
		2176	return;
		2177	}
		2178
		2179	intel_encoder = &intel_dig_port->base;
		2180
		2181	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
6937	serge	2182	DRM_MODE_ENCODER_TMDS, NULL);
3243	Serge	2183
3746	Serge	2184	intel_encoder->compute_config = intel_hdmi_compute_config;
6084	serge	2185	if (HAS_PCH_SPLIT(dev)) {
		2186	intel_encoder->disable = pch_disable_hdmi;
		2187	intel_encoder->post_disable = pch_post_disable_hdmi;
		2188	} else {
		2189	intel_encoder->disable = g4x_disable_hdmi;
		2190	}
3243	Serge	2191	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
4104	Serge	2192	intel_encoder->get_config = intel_hdmi_get_config;
5060	serge	2193	if (IS_CHERRYVIEW(dev)) {
		2194	intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
		2195	intel_encoder->pre_enable = chv_hdmi_pre_enable;
		2196	intel_encoder->enable = vlv_enable_hdmi;
		2197	intel_encoder->post_disable = chv_hdmi_post_disable;
6084	serge	2198	intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
5060	serge	2199	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	2200	intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		2201	intel_encoder->pre_enable = vlv_hdmi_pre_enable;
4104	Serge	2202	intel_encoder->enable = vlv_enable_hdmi;
4560	Serge	2203	intel_encoder->post_disable = vlv_hdmi_post_disable;
4104	Serge	2204	} else {
5060	serge	2205	intel_encoder->pre_enable = intel_hdmi_pre_enable;
6084	serge	2206	if (HAS_PCH_CPT(dev))
		2207	intel_encoder->enable = cpt_enable_hdmi;
		2208	else if (HAS_PCH_IBX(dev))
		2209	intel_encoder->enable = ibx_enable_hdmi;
		2210	else
		2211	intel_encoder->enable = g4x_enable_hdmi;
4104	Serge	2212	}
3243	Serge	2213
		2214	intel_encoder->type = INTEL_OUTPUT_HDMI;
5060	serge	2215	if (IS_CHERRYVIEW(dev)) {
		2216	if (port == PORT_D)
		2217	intel_encoder->crtc_mask = 1 << 2;
		2218	else
		2219	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
		2220	} else {
6084	serge	2221	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
5060	serge	2222	}
		2223	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
		2224	/*
		2225	* BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
		2226	* to work on real hardware. And since g4x can send infoframes to
		2227	* only one port anyway, nothing is lost by allowing it.
		2228	*/
		2229	if (IS_G4X(dev))
		2230	intel_encoder->cloneable \|= 1 << INTEL_OUTPUT_HDMI;
3243	Serge	2231
		2232	intel_dig_port->port = port;
3746	Serge	2233	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
6937	serge	2234	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3243	Serge	2235
		2236	intel_hdmi_init_connector(intel_dig_port, intel_connector);
		2237	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_hdmi.c – Rev 6937