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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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3031 | serge | 31 | #include |
4104 | Serge | 32 | #include |
3031 | serge | 33 | #include |
34 | #include |
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35 | #include |
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2330 | Serge | 36 | #include "intel_drv.h" |
3031 | serge | 37 | #include |
2330 | Serge | 38 | #include "i915_drv.h" |
39 | |||
3243 | Serge | 40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { |
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42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
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43 | } |
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44 | |||
3031 | serge | 45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
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47 | { |
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3243 | Serge | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
3031 | serge | 49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; |
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2330 | Serge | 51 | |
3480 | Serge | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
3031 | serge | 53 | |
3746 | Serge | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
3031 | serge | 55 | "HDMI port enabled, expecting disabled\n"); |
56 | } |
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57 | |||
58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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2330 | Serge | 59 | { |
3243 | Serge | 60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); |
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62 | return &intel_dig_port->hdmi; |
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2330 | Serge | 63 | } |
64 | |||
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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66 | { |
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3243 | Serge | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
2330 | Serge | 68 | } |
69 | |||
4104 | Serge | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
2330 | Serge | 71 | { |
4104 | Serge | 72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 74 | return VIDEO_DIP_SELECT_AVI; |
4104 | Serge | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 76 | return VIDEO_DIP_SELECT_SPD; |
4104 | Serge | 77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; |
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3031 | serge | 79 | default: |
4104 | Serge | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 81 | return 0; |
82 | } |
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83 | } |
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2330 | Serge | 84 | |
4104 | Serge | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
3031 | serge | 86 | { |
4104 | Serge | 87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 89 | return VIDEO_DIP_ENABLE_AVI; |
4104 | Serge | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 91 | return VIDEO_DIP_ENABLE_SPD; |
4104 | Serge | 92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; |
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2330 | Serge | 94 | default: |
4104 | Serge | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 96 | return 0; |
2330 | Serge | 97 | } |
3031 | serge | 98 | } |
2330 | Serge | 99 | |
4104 | Serge | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
3031 | serge | 101 | { |
4104 | Serge | 102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: |
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3031 | serge | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
4104 | Serge | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
3031 | serge | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
4104 | Serge | 107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; |
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3031 | serge | 109 | default: |
4104 | Serge | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 111 | return 0; |
112 | } |
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2330 | Serge | 113 | } |
114 | |||
4104 | Serge | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
3746 | Serge | 116 | enum transcoder cpu_transcoder) |
2330 | Serge | 117 | { |
4104 | Serge | 118 | switch (type) { |
119 | case HDMI_INFOFRAME_TYPE_AVI: |
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3746 | Serge | 120 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
4104 | Serge | 121 | case HDMI_INFOFRAME_TYPE_SPD: |
3746 | Serge | 122 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
4104 | Serge | 123 | case HDMI_INFOFRAME_TYPE_VENDOR: |
124 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); |
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2330 | Serge | 125 | default: |
4104 | Serge | 126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
3031 | serge | 127 | return 0; |
2330 | Serge | 128 | } |
129 | } |
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130 | |||
3031 | serge | 131 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 132 | enum hdmi_infoframe_type type, |
4560 | Serge | 133 | const void *frame, ssize_t len) |
2330 | Serge | 134 | { |
4560 | Serge | 135 | const uint32_t *data = frame; |
2330 | Serge | 136 | struct drm_device *dev = encoder->dev; |
137 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 138 | u32 val = I915_READ(VIDEO_DIP_CTL); |
4104 | Serge | 139 | int i; |
2330 | Serge | 140 | |
3031 | serge | 141 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 142 | |
3031 | serge | 143 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 144 | val |= g4x_infoframe_index(type); |
2330 | Serge | 145 | |
4104 | Serge | 146 | val &= ~g4x_infoframe_enable(type); |
2330 | Serge | 147 | |
3031 | serge | 148 | I915_WRITE(VIDEO_DIP_CTL, val); |
2330 | Serge | 149 | |
3031 | serge | 150 | mmiowb(); |
2330 | Serge | 151 | for (i = 0; i < len; i += 4) { |
152 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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153 | data++; |
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154 | } |
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3031 | serge | 155 | /* Write every possible data byte to force correct ECC calculation. */ |
156 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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157 | I915_WRITE(VIDEO_DIP_DATA, 0); |
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158 | mmiowb(); |
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2330 | Serge | 159 | |
4104 | Serge | 160 | val |= g4x_infoframe_enable(type); |
3031 | serge | 161 | val &= ~VIDEO_DIP_FREQ_MASK; |
162 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 163 | |
3031 | serge | 164 | I915_WRITE(VIDEO_DIP_CTL, val); |
165 | POSTING_READ(VIDEO_DIP_CTL); |
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2330 | Serge | 166 | } |
167 | |||
3031 | serge | 168 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
4104 | Serge | 169 | enum hdmi_infoframe_type type, |
4560 | Serge | 170 | const void *frame, ssize_t len) |
2330 | Serge | 171 | { |
4560 | Serge | 172 | const uint32_t *data = frame; |
2330 | Serge | 173 | struct drm_device *dev = encoder->dev; |
174 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3031 | serge | 175 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4104 | Serge | 176 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 177 | u32 val = I915_READ(reg); |
2330 | Serge | 178 | |
3031 | serge | 179 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
2330 | Serge | 180 | |
3031 | serge | 181 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 182 | val |= g4x_infoframe_index(type); |
2330 | Serge | 183 | |
4104 | Serge | 184 | val &= ~g4x_infoframe_enable(type); |
3031 | serge | 185 | |
186 | I915_WRITE(reg, val); |
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187 | |||
188 | mmiowb(); |
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189 | for (i = 0; i < len; i += 4) { |
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190 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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191 | data++; |
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192 | } |
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193 | /* Write every possible data byte to force correct ECC calculation. */ |
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194 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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195 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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196 | mmiowb(); |
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197 | |||
4104 | Serge | 198 | val |= g4x_infoframe_enable(type); |
3031 | serge | 199 | val &= ~VIDEO_DIP_FREQ_MASK; |
200 | val |= VIDEO_DIP_FREQ_VSYNC; |
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201 | |||
202 | I915_WRITE(reg, val); |
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203 | POSTING_READ(reg); |
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204 | } |
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205 | |||
206 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
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4104 | Serge | 207 | enum hdmi_infoframe_type type, |
4560 | Serge | 208 | const void *frame, ssize_t len) |
3031 | serge | 209 | { |
4560 | Serge | 210 | const uint32_t *data = frame; |
3031 | serge | 211 | struct drm_device *dev = encoder->dev; |
212 | struct drm_i915_private *dev_priv = dev->dev_private; |
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213 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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4104 | Serge | 214 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 215 | u32 val = I915_READ(reg); |
216 | |||
217 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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218 | |||
2342 | Serge | 219 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
4104 | Serge | 220 | val |= g4x_infoframe_index(type); |
2330 | Serge | 221 | |
3031 | serge | 222 | /* The DIP control register spec says that we need to update the AVI |
223 | * infoframe without clearing its enable bit */ |
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4104 | Serge | 224 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
225 | val &= ~g4x_infoframe_enable(type); |
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2330 | Serge | 226 | |
3031 | serge | 227 | I915_WRITE(reg, val); |
228 | |||
229 | mmiowb(); |
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2330 | Serge | 230 | for (i = 0; i < len; i += 4) { |
231 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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232 | data++; |
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233 | } |
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3031 | serge | 234 | /* Write every possible data byte to force correct ECC calculation. */ |
235 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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237 | mmiowb(); |
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2330 | Serge | 238 | |
4104 | Serge | 239 | val |= g4x_infoframe_enable(type); |
3031 | serge | 240 | val &= ~VIDEO_DIP_FREQ_MASK; |
241 | val |= VIDEO_DIP_FREQ_VSYNC; |
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2330 | Serge | 242 | |
3031 | serge | 243 | I915_WRITE(reg, val); |
244 | POSTING_READ(reg); |
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2330 | Serge | 245 | } |
3031 | serge | 246 | |
247 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
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4104 | Serge | 248 | enum hdmi_infoframe_type type, |
4560 | Serge | 249 | const void *frame, ssize_t len) |
3031 | serge | 250 | { |
4560 | Serge | 251 | const uint32_t *data = frame; |
3031 | serge | 252 | struct drm_device *dev = encoder->dev; |
253 | struct drm_i915_private *dev_priv = dev->dev_private; |
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254 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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4104 | Serge | 255 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
3031 | serge | 256 | u32 val = I915_READ(reg); |
257 | |||
258 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
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259 | |||
260 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
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4104 | Serge | 261 | val |= g4x_infoframe_index(type); |
3031 | serge | 262 | |
4104 | Serge | 263 | val &= ~g4x_infoframe_enable(type); |
3031 | serge | 264 | |
265 | I915_WRITE(reg, val); |
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266 | |||
267 | mmiowb(); |
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268 | for (i = 0; i < len; i += 4) { |
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269 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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270 | data++; |
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271 | } |
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272 | /* Write every possible data byte to force correct ECC calculation. */ |
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273 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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274 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
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275 | mmiowb(); |
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276 | |||
4104 | Serge | 277 | val |= g4x_infoframe_enable(type); |
3031 | serge | 278 | val &= ~VIDEO_DIP_FREQ_MASK; |
279 | val |= VIDEO_DIP_FREQ_VSYNC; |
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280 | |||
281 | I915_WRITE(reg, val); |
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282 | POSTING_READ(reg); |
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283 | } |
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284 | |||
285 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
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4104 | Serge | 286 | enum hdmi_infoframe_type type, |
4560 | Serge | 287 | const void *frame, ssize_t len) |
3031 | serge | 288 | { |
4560 | Serge | 289 | const uint32_t *data = frame; |
3031 | serge | 290 | struct drm_device *dev = encoder->dev; |
291 | struct drm_i915_private *dev_priv = dev->dev_private; |
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292 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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3746 | Serge | 293 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
4104 | Serge | 294 | u32 data_reg; |
295 | int i; |
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3031 | serge | 296 | u32 val = I915_READ(ctl_reg); |
297 | |||
4104 | Serge | 298 | data_reg = hsw_infoframe_data_reg(type, |
299 | intel_crtc->config.cpu_transcoder); |
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3031 | serge | 300 | if (data_reg == 0) |
301 | return; |
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302 | |||
4104 | Serge | 303 | val &= ~hsw_infoframe_enable(type); |
3031 | serge | 304 | I915_WRITE(ctl_reg, val); |
305 | |||
306 | mmiowb(); |
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307 | for (i = 0; i < len; i += 4) { |
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308 | I915_WRITE(data_reg + i, *data); |
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309 | data++; |
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310 | } |
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311 | /* Write every possible data byte to force correct ECC calculation. */ |
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312 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
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313 | I915_WRITE(data_reg + i, 0); |
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314 | mmiowb(); |
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315 | |||
4104 | Serge | 316 | val |= hsw_infoframe_enable(type); |
3031 | serge | 317 | I915_WRITE(ctl_reg, val); |
318 | POSTING_READ(ctl_reg); |
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319 | } |
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320 | |||
4104 | Serge | 321 | /* |
322 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
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323 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
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324 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
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325 | * used for both technologies. |
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326 | * |
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327 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 |
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328 | * DW1: DB3 | DB2 | DB1 | DB0 |
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329 | * DW2: DB7 | DB6 | DB5 | DB4 |
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330 | * DW3: ... |
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331 | * |
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332 | * (HB is Header Byte, DB is Data Byte) |
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333 | * |
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334 | * The hdmi pack() functions don't know about that hardware specific hole so we |
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335 | * trick them by giving an offset into the buffer and moving back the header |
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336 | * bytes by one. |
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337 | */ |
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338 | static void intel_write_infoframe(struct drm_encoder *encoder, |
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339 | union hdmi_infoframe *frame) |
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2330 | Serge | 340 | { |
341 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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4104 | Serge | 342 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
343 | ssize_t len; |
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2330 | Serge | 344 | |
4104 | Serge | 345 | /* see comment above for the reason for this offset */ |
346 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); |
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347 | if (len < 0) |
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348 | return; |
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349 | |||
350 | /* Insert the 'hole' (see big comment above) at position 3 */ |
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351 | buffer[0] = buffer[1]; |
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352 | buffer[1] = buffer[2]; |
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353 | buffer[2] = buffer[3]; |
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354 | buffer[3] = 0; |
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355 | len++; |
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356 | |||
357 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
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2330 | Serge | 358 | } |
359 | |||
3031 | serge | 360 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
361 | struct drm_display_mode *adjusted_mode) |
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2330 | Serge | 362 | { |
3480 | Serge | 363 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
3746 | Serge | 364 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4104 | Serge | 365 | union hdmi_infoframe frame; |
366 | int ret; |
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2330 | Serge | 367 | |
4104 | Serge | 368 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
369 | adjusted_mode); |
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370 | if (ret < 0) { |
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371 | DRM_ERROR("couldn't fill AVI infoframe\n"); |
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372 | return; |
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373 | } |
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3031 | serge | 374 | |
3480 | Serge | 375 | if (intel_hdmi->rgb_quant_range_selectable) { |
3746 | Serge | 376 | if (intel_crtc->config.limited_color_range) |
4104 | Serge | 377 | frame.avi.quantization_range = |
378 | HDMI_QUANTIZATION_RANGE_LIMITED; |
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3480 | Serge | 379 | else |
4104 | Serge | 380 | frame.avi.quantization_range = |
381 | HDMI_QUANTIZATION_RANGE_FULL; |
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3480 | Serge | 382 | } |
3243 | Serge | 383 | |
4104 | Serge | 384 | intel_write_infoframe(encoder, &frame); |
2330 | Serge | 385 | } |
386 | |||
387 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
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388 | { |
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4104 | Serge | 389 | union hdmi_infoframe frame; |
390 | int ret; |
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2330 | Serge | 391 | |
4104 | Serge | 392 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); |
393 | if (ret < 0) { |
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394 | DRM_ERROR("couldn't fill SPD infoframe\n"); |
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395 | return; |
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396 | } |
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2330 | Serge | 397 | |
4104 | Serge | 398 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
399 | |||
400 | intel_write_infoframe(encoder, &frame); |
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2330 | Serge | 401 | } |
402 | |||
4104 | Serge | 403 | static void |
404 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, |
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405 | struct drm_display_mode *adjusted_mode) |
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406 | { |
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407 | union hdmi_infoframe frame; |
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408 | int ret; |
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409 | |||
410 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, |
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411 | adjusted_mode); |
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412 | if (ret < 0) |
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413 | return; |
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414 | |||
415 | intel_write_infoframe(encoder, &frame); |
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416 | } |
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417 | |||
3031 | serge | 418 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
419 | struct drm_display_mode *adjusted_mode) |
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420 | { |
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421 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
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3480 | Serge | 422 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
423 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
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3031 | serge | 424 | u32 reg = VIDEO_DIP_CTL; |
425 | u32 val = I915_READ(reg); |
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426 | u32 port; |
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427 | |||
428 | assert_hdmi_port_disabled(intel_hdmi); |
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429 | |||
430 | /* If the registers were not initialized yet, they might be zeroes, |
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431 | * which means we're selecting the AVI DIP and we're setting its |
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432 | * frequency to once. This seems to really confuse the HW and make |
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433 | * things stop working (the register spec says the AVI always needs to |
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434 | * be sent every VSync). So here we avoid writing to the register more |
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435 | * than we need and also explicitly select the AVI DIP and explicitly |
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436 | * set its frequency to every VSync. Avoiding to write it twice seems to |
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437 | * be enough to solve the problem, but being defensive shouldn't hurt us |
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438 | * either. */ |
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439 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
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440 | |||
441 | if (!intel_hdmi->has_hdmi_sink) { |
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442 | if (!(val & VIDEO_DIP_ENABLE)) |
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443 | return; |
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444 | val &= ~VIDEO_DIP_ENABLE; |
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445 | I915_WRITE(reg, val); |
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446 | POSTING_READ(reg); |
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447 | return; |
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448 | } |
||
449 | |||
3480 | Serge | 450 | switch (intel_dig_port->port) { |
451 | case PORT_B: |
||
3031 | serge | 452 | port = VIDEO_DIP_PORT_B; |
453 | break; |
||
3480 | Serge | 454 | case PORT_C: |
3031 | serge | 455 | port = VIDEO_DIP_PORT_C; |
456 | break; |
||
457 | default: |
||
458 | BUG(); |
||
459 | return; |
||
460 | } |
||
461 | |||
462 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
||
463 | if (val & VIDEO_DIP_ENABLE) { |
||
464 | val &= ~VIDEO_DIP_ENABLE; |
||
465 | I915_WRITE(reg, val); |
||
466 | POSTING_READ(reg); |
||
467 | } |
||
468 | val &= ~VIDEO_DIP_PORT_MASK; |
||
469 | val |= port; |
||
470 | } |
||
471 | |||
472 | val |= VIDEO_DIP_ENABLE; |
||
473 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
||
474 | |||
475 | I915_WRITE(reg, val); |
||
476 | POSTING_READ(reg); |
||
477 | |||
478 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
479 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 480 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 481 | } |
482 | |||
483 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
||
484 | struct drm_display_mode *adjusted_mode) |
||
485 | { |
||
486 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
487 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
3480 | Serge | 488 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
489 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
3031 | serge | 490 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
491 | u32 val = I915_READ(reg); |
||
492 | u32 port; |
||
493 | |||
494 | assert_hdmi_port_disabled(intel_hdmi); |
||
495 | |||
496 | /* See the big comment in g4x_set_infoframes() */ |
||
497 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
498 | |||
499 | if (!intel_hdmi->has_hdmi_sink) { |
||
500 | if (!(val & VIDEO_DIP_ENABLE)) |
||
501 | return; |
||
502 | val &= ~VIDEO_DIP_ENABLE; |
||
503 | I915_WRITE(reg, val); |
||
504 | POSTING_READ(reg); |
||
505 | return; |
||
506 | } |
||
507 | |||
3480 | Serge | 508 | switch (intel_dig_port->port) { |
509 | case PORT_B: |
||
3031 | serge | 510 | port = VIDEO_DIP_PORT_B; |
511 | break; |
||
3480 | Serge | 512 | case PORT_C: |
3031 | serge | 513 | port = VIDEO_DIP_PORT_C; |
514 | break; |
||
3480 | Serge | 515 | case PORT_D: |
3031 | serge | 516 | port = VIDEO_DIP_PORT_D; |
517 | break; |
||
518 | default: |
||
519 | BUG(); |
||
520 | return; |
||
521 | } |
||
522 | |||
523 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
||
524 | if (val & VIDEO_DIP_ENABLE) { |
||
525 | val &= ~VIDEO_DIP_ENABLE; |
||
526 | I915_WRITE(reg, val); |
||
527 | POSTING_READ(reg); |
||
528 | } |
||
529 | val &= ~VIDEO_DIP_PORT_MASK; |
||
530 | val |= port; |
||
531 | } |
||
532 | |||
533 | val |= VIDEO_DIP_ENABLE; |
||
534 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
535 | VIDEO_DIP_ENABLE_GCP); |
||
536 | |||
537 | I915_WRITE(reg, val); |
||
538 | POSTING_READ(reg); |
||
539 | |||
540 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
541 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 542 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 543 | } |
544 | |||
545 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
||
546 | struct drm_display_mode *adjusted_mode) |
||
547 | { |
||
548 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
549 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
550 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
551 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
552 | u32 val = I915_READ(reg); |
||
553 | |||
554 | assert_hdmi_port_disabled(intel_hdmi); |
||
555 | |||
556 | /* See the big comment in g4x_set_infoframes() */ |
||
557 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
558 | |||
559 | if (!intel_hdmi->has_hdmi_sink) { |
||
560 | if (!(val & VIDEO_DIP_ENABLE)) |
||
561 | return; |
||
562 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); |
||
563 | I915_WRITE(reg, val); |
||
564 | POSTING_READ(reg); |
||
565 | return; |
||
566 | } |
||
567 | |||
568 | /* Set both together, unset both together: see the spec. */ |
||
569 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
||
570 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
571 | VIDEO_DIP_ENABLE_GCP); |
||
572 | |||
573 | I915_WRITE(reg, val); |
||
574 | POSTING_READ(reg); |
||
575 | |||
576 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
577 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 578 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 579 | } |
580 | |||
581 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
||
582 | struct drm_display_mode *adjusted_mode) |
||
583 | { |
||
584 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
585 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
586 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
587 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
||
588 | u32 val = I915_READ(reg); |
||
589 | |||
590 | assert_hdmi_port_disabled(intel_hdmi); |
||
591 | |||
592 | /* See the big comment in g4x_set_infoframes() */ |
||
593 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
||
594 | |||
595 | if (!intel_hdmi->has_hdmi_sink) { |
||
596 | if (!(val & VIDEO_DIP_ENABLE)) |
||
597 | return; |
||
598 | val &= ~VIDEO_DIP_ENABLE; |
||
599 | I915_WRITE(reg, val); |
||
600 | POSTING_READ(reg); |
||
601 | return; |
||
602 | } |
||
603 | |||
604 | val |= VIDEO_DIP_ENABLE; |
||
605 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
||
606 | VIDEO_DIP_ENABLE_GCP); |
||
607 | |||
608 | I915_WRITE(reg, val); |
||
609 | POSTING_READ(reg); |
||
610 | |||
611 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
612 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 613 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 614 | } |
615 | |||
616 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
||
617 | struct drm_display_mode *adjusted_mode) |
||
618 | { |
||
619 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
||
620 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
621 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
||
3746 | Serge | 622 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
3031 | serge | 623 | u32 val = I915_READ(reg); |
624 | |||
625 | assert_hdmi_port_disabled(intel_hdmi); |
||
626 | |||
627 | if (!intel_hdmi->has_hdmi_sink) { |
||
628 | I915_WRITE(reg, 0); |
||
629 | POSTING_READ(reg); |
||
630 | return; |
||
631 | } |
||
632 | |||
633 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
||
634 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); |
||
635 | |||
636 | I915_WRITE(reg, val); |
||
637 | POSTING_READ(reg); |
||
638 | |||
639 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
||
640 | intel_hdmi_set_spd_infoframe(encoder); |
||
4104 | Serge | 641 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
3031 | serge | 642 | } |
643 | |||
4104 | Serge | 644 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
2330 | Serge | 645 | { |
4104 | Serge | 646 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 647 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 648 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
649 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
650 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
||
3746 | Serge | 651 | u32 hdmi_val; |
2330 | Serge | 652 | |
3746 | Serge | 653 | hdmi_val = SDVO_ENCODING_HDMI; |
4104 | Serge | 654 | if (!HAS_PCH_SPLIT(dev)) |
3746 | Serge | 655 | hdmi_val |= intel_hdmi->color_range; |
2330 | Serge | 656 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
3746 | Serge | 657 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
2330 | Serge | 658 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
3746 | Serge | 659 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
2330 | Serge | 660 | |
4104 | Serge | 661 | if (crtc->config.pipe_bpp > 24) |
3746 | Serge | 662 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
2330 | Serge | 663 | else |
3746 | Serge | 664 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
2330 | Serge | 665 | |
666 | /* Required on CPT */ |
||
667 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
||
3746 | Serge | 668 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2330 | Serge | 669 | |
670 | if (intel_hdmi->has_audio) { |
||
2342 | Serge | 671 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
4104 | Serge | 672 | pipe_name(crtc->pipe)); |
3746 | Serge | 673 | hdmi_val |= SDVO_AUDIO_ENABLE; |
674 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
||
4104 | Serge | 675 | intel_write_eld(&encoder->base, adjusted_mode); |
2330 | Serge | 676 | } |
677 | |||
678 | if (HAS_PCH_CPT(dev)) |
||
4104 | Serge | 679 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
3746 | Serge | 680 | else |
4104 | Serge | 681 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
2330 | Serge | 682 | |
3746 | Serge | 683 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
684 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 685 | |
4104 | Serge | 686 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
2330 | Serge | 687 | } |
688 | |||
3031 | serge | 689 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
690 | enum pipe *pipe) |
||
2330 | Serge | 691 | { |
3031 | serge | 692 | struct drm_device *dev = encoder->base.dev; |
2330 | Serge | 693 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 694 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
695 | u32 tmp; |
||
696 | |||
3746 | Serge | 697 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
3031 | serge | 698 | |
699 | if (!(tmp & SDVO_ENABLE)) |
||
700 | return false; |
||
701 | |||
702 | if (HAS_PCH_CPT(dev)) |
||
703 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
704 | else |
||
705 | *pipe = PORT_TO_PIPE(tmp); |
||
706 | |||
707 | return true; |
||
708 | } |
||
709 | |||
4104 | Serge | 710 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
711 | struct intel_crtc_config *pipe_config) |
||
712 | { |
||
713 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
714 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
715 | u32 tmp, flags = 0; |
||
4560 | Serge | 716 | int dotclock; |
4104 | Serge | 717 | |
718 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
||
719 | |||
720 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) |
||
721 | flags |= DRM_MODE_FLAG_PHSYNC; |
||
722 | else |
||
723 | flags |= DRM_MODE_FLAG_NHSYNC; |
||
724 | |||
725 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) |
||
726 | flags |= DRM_MODE_FLAG_PVSYNC; |
||
727 | else |
||
728 | flags |= DRM_MODE_FLAG_NVSYNC; |
||
729 | |||
730 | pipe_config->adjusted_mode.flags |= flags; |
||
4560 | Serge | 731 | |
732 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) |
||
733 | dotclock = pipe_config->port_clock * 2 / 3; |
||
734 | else |
||
735 | dotclock = pipe_config->port_clock; |
||
736 | |||
737 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
||
738 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
||
739 | |||
740 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
||
4104 | Serge | 741 | } |
742 | |||
3031 | serge | 743 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
744 | { |
||
745 | struct drm_device *dev = encoder->base.dev; |
||
746 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3746 | Serge | 747 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
3031 | serge | 748 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2330 | Serge | 749 | u32 temp; |
2342 | Serge | 750 | u32 enable_bits = SDVO_ENABLE; |
2330 | Serge | 751 | |
2342 | Serge | 752 | if (intel_hdmi->has_audio) |
753 | enable_bits |= SDVO_AUDIO_ENABLE; |
||
754 | |||
3746 | Serge | 755 | temp = I915_READ(intel_hdmi->hdmi_reg); |
2330 | Serge | 756 | |
3031 | serge | 757 | /* HW workaround for IBX, we need to move the port to transcoder A |
3746 | Serge | 758 | * before disabling it, so restore the transcoder select bit here. */ |
759 | if (HAS_PCH_IBX(dev)) |
||
760 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); |
||
3031 | serge | 761 | |
2330 | Serge | 762 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
763 | * we do this anyway which shows more stable in testing. |
||
764 | */ |
||
765 | if (HAS_PCH_SPLIT(dev)) { |
||
3746 | Serge | 766 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
767 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 768 | } |
769 | |||
3031 | serge | 770 | temp |= enable_bits; |
771 | |||
3746 | Serge | 772 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
773 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
3031 | serge | 774 | |
775 | /* HW workaround, need to write this twice for issue that may result |
||
776 | * in first write getting masked. |
||
777 | */ |
||
778 | if (HAS_PCH_SPLIT(dev)) { |
||
3746 | Serge | 779 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
780 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 781 | } |
3031 | serge | 782 | } |
2330 | Serge | 783 | |
4104 | Serge | 784 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
785 | { |
||
786 | } |
||
787 | |||
3031 | serge | 788 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
789 | { |
||
790 | struct drm_device *dev = encoder->base.dev; |
||
791 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
792 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
||
793 | u32 temp; |
||
794 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
||
795 | |||
3746 | Serge | 796 | temp = I915_READ(intel_hdmi->hdmi_reg); |
3031 | serge | 797 | |
798 | /* HW workaround for IBX, we need to move the port to transcoder A |
||
799 | * before disabling it. */ |
||
800 | if (HAS_PCH_IBX(dev)) { |
||
801 | struct drm_crtc *crtc = encoder->base.crtc; |
||
802 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
803 | |||
804 | if (temp & SDVO_PIPE_B_SELECT) { |
||
805 | temp &= ~SDVO_PIPE_B_SELECT; |
||
3746 | Serge | 806 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
807 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
3031 | serge | 808 | |
809 | /* Again we need to write this twice. */ |
||
3746 | Serge | 810 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
811 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
3031 | serge | 812 | |
813 | /* Transcoder selection bits only update |
||
814 | * effectively on vblank. */ |
||
815 | if (crtc) |
||
816 | intel_wait_for_vblank(dev, pipe); |
||
817 | else |
||
818 | msleep(50); |
||
819 | } |
||
820 | } |
||
821 | |||
822 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
||
823 | * we do this anyway which shows more stable in testing. |
||
824 | */ |
||
825 | if (HAS_PCH_SPLIT(dev)) { |
||
3746 | Serge | 826 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
827 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
3031 | serge | 828 | } |
829 | |||
830 | temp &= ~enable_bits; |
||
831 | |||
3746 | Serge | 832 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
833 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 834 | |
835 | /* HW workaround, need to write this twice for issue that may result |
||
836 | * in first write getting masked. |
||
837 | */ |
||
838 | if (HAS_PCH_SPLIT(dev)) { |
||
3746 | Serge | 839 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
840 | POSTING_READ(intel_hdmi->hdmi_reg); |
||
2330 | Serge | 841 | } |
842 | } |
||
843 | |||
4104 | Serge | 844 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi) |
845 | { |
||
846 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
||
847 | |||
848 | if (IS_G4X(dev)) |
||
849 | return 165000; |
||
4560 | Serge | 850 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
4104 | Serge | 851 | return 300000; |
852 | else |
||
853 | return 225000; |
||
854 | } |
||
855 | |||
4560 | Serge | 856 | static enum drm_mode_status |
857 | intel_hdmi_mode_valid(struct drm_connector *connector, |
||
2330 | Serge | 858 | struct drm_display_mode *mode) |
859 | { |
||
4104 | Serge | 860 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) |
2330 | Serge | 861 | return MODE_CLOCK_HIGH; |
862 | if (mode->clock < 20000) |
||
863 | return MODE_CLOCK_LOW; |
||
864 | |||
865 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
866 | return MODE_NO_DBLESCAN; |
||
867 | |||
868 | return MODE_OK; |
||
869 | } |
||
870 | |||
3746 | Serge | 871 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
872 | struct intel_crtc_config *pipe_config) |
||
2330 | Serge | 873 | { |
3746 | Serge | 874 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
875 | struct drm_device *dev = encoder->base.dev; |
||
876 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
||
4560 | Serge | 877 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
4104 | Serge | 878 | int portclock_limit = hdmi_portclock_limit(intel_hdmi); |
879 | int desired_bpp; |
||
2330 | Serge | 880 | |
3480 | Serge | 881 | if (intel_hdmi->color_range_auto) { |
882 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
||
883 | if (intel_hdmi->has_hdmi_sink && |
||
884 | drm_match_cea_mode(adjusted_mode) > 1) |
||
3746 | Serge | 885 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
3480 | Serge | 886 | else |
887 | intel_hdmi->color_range = 0; |
||
3031 | serge | 888 | } |
889 | |||
3480 | Serge | 890 | if (intel_hdmi->color_range) |
3746 | Serge | 891 | pipe_config->limited_color_range = true; |
3480 | Serge | 892 | |
3746 | Serge | 893 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
894 | pipe_config->has_pch_encoder = true; |
||
895 | |||
896 | /* |
||
897 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
||
898 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi |
||
4104 | Serge | 899 | * outputs. We also need to check that the higher clock still fits |
900 | * within limits. |
||
3746 | Serge | 901 | */ |
4104 | Serge | 902 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit |
903 | && HAS_PCH_SPLIT(dev)) { |
||
904 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
||
905 | desired_bpp = 12*3; |
||
906 | |||
907 | /* Need to adjust the port link by 1.5x for 12bpc. */ |
||
908 | pipe_config->port_clock = clock_12bpc; |
||
3746 | Serge | 909 | } else { |
4104 | Serge | 910 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
911 | desired_bpp = 8*3; |
||
3746 | Serge | 912 | } |
913 | |||
4104 | Serge | 914 | if (!pipe_config->bw_constrained) { |
915 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); |
||
916 | pipe_config->pipe_bpp = desired_bpp; |
||
917 | } |
||
918 | |||
4560 | Serge | 919 | if (adjusted_mode->crtc_clock > portclock_limit) { |
4104 | Serge | 920 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
921 | return false; |
||
922 | } |
||
923 | |||
3480 | Serge | 924 | return true; |
3031 | serge | 925 | } |
926 | |||
2330 | Serge | 927 | static enum drm_connector_status |
928 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
||
929 | { |
||
3480 | Serge | 930 | struct drm_device *dev = connector->dev; |
2330 | Serge | 931 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
3243 | Serge | 932 | struct intel_digital_port *intel_dig_port = |
933 | hdmi_to_dig_port(intel_hdmi); |
||
934 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3480 | Serge | 935 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 936 | struct edid *edid; |
937 | enum drm_connector_status status = connector_status_disconnected; |
||
938 | |||
4104 | Serge | 939 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
940 | connector->base.id, drm_get_connector_name(connector)); |
||
941 | |||
2330 | Serge | 942 | intel_hdmi->has_hdmi_sink = false; |
943 | intel_hdmi->has_audio = false; |
||
3480 | Serge | 944 | intel_hdmi->rgb_quant_range_selectable = false; |
2330 | Serge | 945 | edid = drm_get_edid(connector, |
3031 | serge | 946 | intel_gmbus_get_adapter(dev_priv, |
947 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 948 | |
949 | if (edid) { |
||
950 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
||
951 | status = connector_status_connected; |
||
3031 | serge | 952 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
953 | intel_hdmi->has_hdmi_sink = |
||
954 | drm_detect_hdmi_monitor(edid); |
||
2330 | Serge | 955 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
3480 | Serge | 956 | intel_hdmi->rgb_quant_range_selectable = |
957 | drm_rgb_quant_range_selectable(edid); |
||
2330 | Serge | 958 | } |
959 | kfree(edid); |
||
960 | } |
||
961 | |||
962 | if (status == connector_status_connected) { |
||
3031 | serge | 963 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
964 | intel_hdmi->has_audio = |
||
965 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
||
3243 | Serge | 966 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
2330 | Serge | 967 | } |
968 | |||
969 | return status; |
||
970 | } |
||
971 | |||
972 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
||
973 | { |
||
974 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
975 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
976 | |||
977 | /* We should parse the EDID data and find out if it's an HDMI sink so |
||
978 | * we can send audio to it. |
||
979 | */ |
||
980 | |||
981 | return intel_ddc_get_modes(connector, |
||
3031 | serge | 982 | intel_gmbus_get_adapter(dev_priv, |
983 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 984 | } |
985 | |||
986 | static bool |
||
987 | intel_hdmi_detect_audio(struct drm_connector *connector) |
||
988 | { |
||
989 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
990 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
991 | struct edid *edid; |
||
992 | bool has_audio = false; |
||
993 | |||
994 | edid = drm_get_edid(connector, |
||
3031 | serge | 995 | intel_gmbus_get_adapter(dev_priv, |
996 | intel_hdmi->ddc_bus)); |
||
2330 | Serge | 997 | if (edid) { |
998 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
||
999 | has_audio = drm_detect_monitor_audio(edid); |
||
1000 | kfree(edid); |
||
1001 | } |
||
1002 | |||
1003 | return has_audio; |
||
1004 | } |
||
1005 | |||
1006 | static int |
||
1007 | intel_hdmi_set_property(struct drm_connector *connector, |
||
1008 | struct drm_property *property, |
||
1009 | uint64_t val) |
||
1010 | { |
||
1011 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
||
3243 | Serge | 1012 | struct intel_digital_port *intel_dig_port = |
1013 | hdmi_to_dig_port(intel_hdmi); |
||
2330 | Serge | 1014 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1015 | int ret; |
||
1016 | |||
3243 | Serge | 1017 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 1018 | if (ret) |
1019 | return ret; |
||
3480 | Serge | 1020 | |
2330 | Serge | 1021 | if (property == dev_priv->force_audio_property) { |
3031 | serge | 1022 | enum hdmi_force_audio i = val; |
2330 | Serge | 1023 | bool has_audio; |
1024 | |||
1025 | if (i == intel_hdmi->force_audio) |
||
1026 | return 0; |
||
1027 | |||
1028 | intel_hdmi->force_audio = i; |
||
1029 | |||
3031 | serge | 1030 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 1031 | has_audio = intel_hdmi_detect_audio(connector); |
1032 | else |
||
3031 | serge | 1033 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 1034 | |
3031 | serge | 1035 | if (i == HDMI_AUDIO_OFF_DVI) |
1036 | intel_hdmi->has_hdmi_sink = 0; |
||
2330 | Serge | 1037 | |
1038 | intel_hdmi->has_audio = has_audio; |
||
1039 | goto done; |
||
1040 | } |
||
1041 | |||
1042 | if (property == dev_priv->broadcast_rgb_property) { |
||
3746 | Serge | 1043 | bool old_auto = intel_hdmi->color_range_auto; |
1044 | uint32_t old_range = intel_hdmi->color_range; |
||
1045 | |||
3480 | Serge | 1046 | switch (val) { |
1047 | case INTEL_BROADCAST_RGB_AUTO: |
||
1048 | intel_hdmi->color_range_auto = true; |
||
1049 | break; |
||
1050 | case INTEL_BROADCAST_RGB_FULL: |
||
1051 | intel_hdmi->color_range_auto = false; |
||
1052 | intel_hdmi->color_range = 0; |
||
1053 | break; |
||
1054 | case INTEL_BROADCAST_RGB_LIMITED: |
||
1055 | intel_hdmi->color_range_auto = false; |
||
3746 | Serge | 1056 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
3480 | Serge | 1057 | break; |
1058 | default: |
||
1059 | return -EINVAL; |
||
1060 | } |
||
3746 | Serge | 1061 | |
1062 | if (old_auto == intel_hdmi->color_range_auto && |
||
1063 | old_range == intel_hdmi->color_range) |
||
1064 | return 0; |
||
1065 | |||
2330 | Serge | 1066 | goto done; |
1067 | } |
||
3031 | serge | 1068 | |
2330 | Serge | 1069 | return -EINVAL; |
1070 | |||
1071 | done: |
||
3480 | Serge | 1072 | if (intel_dig_port->base.base.crtc) |
1073 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); |
||
2330 | Serge | 1074 | |
1075 | return 0; |
||
1076 | } |
||
1077 | |||
4560 | Serge | 1078 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
4104 | Serge | 1079 | { |
1080 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1081 | struct drm_device *dev = encoder->base.dev; |
||
1082 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1083 | struct intel_crtc *intel_crtc = |
||
1084 | to_intel_crtc(encoder->base.crtc); |
||
4560 | Serge | 1085 | enum dpio_channel port = vlv_dport_to_channel(dport); |
4104 | Serge | 1086 | int pipe = intel_crtc->pipe; |
1087 | u32 val; |
||
1088 | |||
1089 | if (!IS_VALLEYVIEW(dev)) |
||
1090 | return; |
||
1091 | |||
1092 | /* Enable clock channels for this port */ |
||
1093 | mutex_lock(&dev_priv->dpio_lock); |
||
4560 | Serge | 1094 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
4104 | Serge | 1095 | val = 0; |
1096 | if (pipe) |
||
1097 | val |= (1<<21); |
||
1098 | else |
||
1099 | val &= ~(1<<21); |
||
1100 | val |= 0x001000c4; |
||
4560 | Serge | 1101 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
4104 | Serge | 1102 | |
1103 | /* HDMI 1.0V-2dB */ |
||
4560 | Serge | 1104 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1105 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); |
||
1106 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); |
||
1107 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); |
||
1108 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); |
||
1109 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
||
1110 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
||
1111 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
||
4104 | Serge | 1112 | |
1113 | /* Program lane clock */ |
||
4560 | Serge | 1114 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1115 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
||
4104 | Serge | 1116 | mutex_unlock(&dev_priv->dpio_lock); |
1117 | |||
1118 | intel_enable_hdmi(encoder); |
||
1119 | |||
4560 | Serge | 1120 | vlv_wait_port_ready(dev_priv, dport); |
4104 | Serge | 1121 | } |
1122 | |||
4560 | Serge | 1123 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
4104 | Serge | 1124 | { |
1125 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1126 | struct drm_device *dev = encoder->base.dev; |
||
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4560 | Serge | 1128 | struct intel_crtc *intel_crtc = |
1129 | to_intel_crtc(encoder->base.crtc); |
||
1130 | enum dpio_channel port = vlv_dport_to_channel(dport); |
||
1131 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 1132 | |
1133 | if (!IS_VALLEYVIEW(dev)) |
||
1134 | return; |
||
1135 | |||
1136 | /* Program Tx lane resets to default */ |
||
1137 | mutex_lock(&dev_priv->dpio_lock); |
||
4560 | Serge | 1138 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
4104 | Serge | 1139 | DPIO_PCS_TX_LANE2_RESET | |
1140 | DPIO_PCS_TX_LANE1_RESET); |
||
4560 | Serge | 1141 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
4104 | Serge | 1142 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1143 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
||
1144 | (1< |
||
1145 | DPIO_PCS_CLK_SOFT_RESET); |
||
1146 | |||
1147 | /* Fix up inter-pair skew failure */ |
||
4560 | Serge | 1148 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1149 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
||
1150 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
||
4104 | Serge | 1151 | |
4560 | Serge | 1152 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1153 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
||
4104 | Serge | 1154 | mutex_unlock(&dev_priv->dpio_lock); |
1155 | } |
||
1156 | |||
4560 | Serge | 1157 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
4104 | Serge | 1158 | { |
1159 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
1160 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
4560 | Serge | 1161 | struct intel_crtc *intel_crtc = |
1162 | to_intel_crtc(encoder->base.crtc); |
||
1163 | enum dpio_channel port = vlv_dport_to_channel(dport); |
||
1164 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 1165 | |
1166 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
||
1167 | mutex_lock(&dev_priv->dpio_lock); |
||
4560 | Serge | 1168 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1169 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); |
||
4104 | Serge | 1170 | mutex_unlock(&dev_priv->dpio_lock); |
1171 | } |
||
1172 | |||
2330 | Serge | 1173 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1174 | { |
||
1175 | drm_connector_cleanup(connector); |
||
1176 | kfree(connector); |
||
1177 | } |
||
1178 | |||
1179 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
||
3031 | serge | 1180 | .dpms = intel_connector_dpms, |
2330 | Serge | 1181 | .detect = intel_hdmi_detect, |
1182 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
1183 | .set_property = intel_hdmi_set_property, |
||
1184 | .destroy = intel_hdmi_destroy, |
||
1185 | }; |
||
1186 | |||
1187 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
||
1188 | .get_modes = intel_hdmi_get_modes, |
||
1189 | .mode_valid = intel_hdmi_mode_valid, |
||
1190 | .best_encoder = intel_best_encoder, |
||
1191 | }; |
||
1192 | |||
1193 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
||
1194 | .destroy = intel_encoder_destroy, |
||
1195 | }; |
||
1196 | |||
1197 | static void |
||
1198 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
||
1199 | { |
||
1200 | intel_attach_force_audio_property(connector); |
||
1201 | intel_attach_broadcast_rgb_property(connector); |
||
3480 | Serge | 1202 | intel_hdmi->color_range_auto = true; |
2330 | Serge | 1203 | } |
1204 | |||
3243 | Serge | 1205 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1206 | struct intel_connector *intel_connector) |
||
2330 | Serge | 1207 | { |
3243 | Serge | 1208 | struct drm_connector *connector = &intel_connector->base; |
1209 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
||
1210 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
1211 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 1212 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 1213 | enum port port = intel_dig_port->port; |
2330 | Serge | 1214 | |
1215 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
||
1216 | DRM_MODE_CONNECTOR_HDMIA); |
||
1217 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
||
1218 | |||
3031 | serge | 1219 | connector->interlace_allowed = 1; |
2330 | Serge | 1220 | connector->doublescan_allowed = 0; |
4560 | Serge | 1221 | connector->stereo_allowed = 1; |
2330 | Serge | 1222 | |
3031 | serge | 1223 | switch (port) { |
1224 | case PORT_B: |
||
2330 | Serge | 1225 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
3746 | Serge | 1226 | intel_encoder->hpd_pin = HPD_PORT_B; |
3031 | serge | 1227 | break; |
1228 | case PORT_C: |
||
2330 | Serge | 1229 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
3746 | Serge | 1230 | intel_encoder->hpd_pin = HPD_PORT_C; |
3031 | serge | 1231 | break; |
1232 | case PORT_D: |
||
2330 | Serge | 1233 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
3746 | Serge | 1234 | intel_encoder->hpd_pin = HPD_PORT_D; |
3031 | serge | 1235 | break; |
1236 | case PORT_A: |
||
3746 | Serge | 1237 | intel_encoder->hpd_pin = HPD_PORT_A; |
3031 | serge | 1238 | /* Internal port only for eDP. */ |
1239 | default: |
||
1240 | BUG(); |
||
2330 | Serge | 1241 | } |
1242 | |||
3746 | Serge | 1243 | if (IS_VALLEYVIEW(dev)) { |
1244 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
||
1245 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
||
1246 | } else if (!HAS_PCH_SPLIT(dev)) { |
||
3031 | serge | 1247 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1248 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
||
3746 | Serge | 1249 | } else if (HAS_DDI(dev)) { |
3031 | serge | 1250 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
1251 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
||
1252 | } else if (HAS_PCH_IBX(dev)) { |
||
1253 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
||
1254 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
||
2342 | Serge | 1255 | } else { |
3031 | serge | 1256 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
1257 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
||
2342 | Serge | 1258 | } |
2330 | Serge | 1259 | |
3480 | Serge | 1260 | if (HAS_DDI(dev)) |
3243 | Serge | 1261 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1262 | else |
||
3031 | serge | 1263 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2330 | Serge | 1264 | |
1265 | intel_hdmi_add_properties(intel_hdmi, connector); |
||
1266 | |||
1267 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
1268 | drm_sysfs_connector_add(connector); |
||
1269 | |||
1270 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
1271 | * 0xd. Failure to do so will result in spurious interrupts being |
||
1272 | * generated on the port when a cable is not attached. |
||
1273 | */ |
||
1274 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
1275 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
1276 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
1277 | } |
||
1278 | } |
||
3243 | Serge | 1279 | |
3746 | Serge | 1280 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
3243 | Serge | 1281 | { |
1282 | struct intel_digital_port *intel_dig_port; |
||
1283 | struct intel_encoder *intel_encoder; |
||
1284 | struct intel_connector *intel_connector; |
||
1285 | |||
4560 | Serge | 1286 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3243 | Serge | 1287 | if (!intel_dig_port) |
1288 | return; |
||
1289 | |||
4560 | Serge | 1290 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
3243 | Serge | 1291 | if (!intel_connector) { |
1292 | kfree(intel_dig_port); |
||
1293 | return; |
||
1294 | } |
||
1295 | |||
1296 | intel_encoder = &intel_dig_port->base; |
||
1297 | |||
1298 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
||
1299 | DRM_MODE_ENCODER_TMDS); |
||
1300 | |||
3746 | Serge | 1301 | intel_encoder->compute_config = intel_hdmi_compute_config; |
4104 | Serge | 1302 | intel_encoder->mode_set = intel_hdmi_mode_set; |
3243 | Serge | 1303 | intel_encoder->disable = intel_disable_hdmi; |
1304 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
||
4104 | Serge | 1305 | intel_encoder->get_config = intel_hdmi_get_config; |
1306 | if (IS_VALLEYVIEW(dev)) { |
||
4560 | Serge | 1307 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1308 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; |
||
4104 | Serge | 1309 | intel_encoder->enable = vlv_enable_hdmi; |
4560 | Serge | 1310 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
4104 | Serge | 1311 | } else { |
1312 | intel_encoder->enable = intel_enable_hdmi; |
||
1313 | } |
||
3243 | Serge | 1314 | |
1315 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
||
1316 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
1317 | intel_encoder->cloneable = false; |
||
1318 | |||
1319 | intel_dig_port->port = port; |
||
3746 | Serge | 1320 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
3243 | Serge | 1321 | intel_dig_port->dp.output_reg = 0; |
1322 | |||
1323 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
||
1324 | }><>><>><> |