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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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31 | //#include |
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32 | #include "drmP.h" |
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33 | #include "drm.h" |
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34 | #include "drm_crtc.h" |
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35 | #include "drm_edid.h" |
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36 | #include "intel_drv.h" |
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37 | #include "i915_drm.h" |
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38 | #include "i915_drv.h" |
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39 | |||
40 | struct intel_hdmi { |
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41 | struct intel_encoder base; |
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42 | u32 sdvox_reg; |
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43 | int ddc_bus; |
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44 | uint32_t color_range; |
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45 | bool has_hdmi_sink; |
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46 | bool has_audio; |
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47 | int force_audio; |
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48 | void (*write_infoframe)(struct drm_encoder *encoder, |
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49 | struct dip_infoframe *frame); |
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50 | }; |
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51 | |||
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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53 | { |
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54 | return container_of(encoder, struct intel_hdmi, base.base); |
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55 | } |
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56 | |||
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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58 | { |
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59 | return container_of(intel_attached_encoder(connector), |
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60 | struct intel_hdmi, base); |
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61 | } |
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62 | |||
63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
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64 | { |
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65 | uint8_t *data = (uint8_t *)frame; |
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66 | uint8_t sum = 0; |
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67 | unsigned i; |
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68 | |||
69 | frame->checksum = 0; |
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70 | frame->ecc = 0; |
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71 | |||
2342 | Serge | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
2330 | Serge | 73 | sum += data[i]; |
74 | |||
75 | frame->checksum = 0x100 - sum; |
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76 | } |
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77 | |||
78 | static u32 intel_infoframe_index(struct dip_infoframe *frame) |
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79 | { |
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80 | u32 flags = 0; |
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81 | |||
82 | switch (frame->type) { |
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83 | case DIP_TYPE_AVI: |
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84 | flags |= VIDEO_DIP_SELECT_AVI; |
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85 | break; |
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86 | case DIP_TYPE_SPD: |
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87 | flags |= VIDEO_DIP_SELECT_SPD; |
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88 | break; |
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89 | default: |
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90 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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91 | break; |
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92 | } |
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93 | |||
94 | return flags; |
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95 | } |
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96 | |||
97 | static u32 intel_infoframe_flags(struct dip_infoframe *frame) |
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98 | { |
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99 | u32 flags = 0; |
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100 | |||
101 | switch (frame->type) { |
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102 | case DIP_TYPE_AVI: |
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103 | flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; |
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104 | break; |
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105 | case DIP_TYPE_SPD: |
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2342 | Serge | 106 | flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; |
2330 | Serge | 107 | break; |
108 | default: |
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109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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110 | break; |
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111 | } |
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112 | |||
113 | return flags; |
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114 | } |
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115 | |||
116 | static void i9xx_write_infoframe(struct drm_encoder *encoder, |
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117 | struct dip_infoframe *frame) |
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118 | { |
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119 | uint32_t *data = (uint32_t *)frame; |
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120 | struct drm_device *dev = encoder->dev; |
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121 | struct drm_i915_private *dev_priv = dev->dev_private; |
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122 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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123 | u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); |
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124 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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125 | |||
126 | |||
127 | /* XXX first guess at handling video port, is this corrent? */ |
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128 | if (intel_hdmi->sdvox_reg == SDVOB) |
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129 | port = VIDEO_DIP_PORT_B; |
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130 | else if (intel_hdmi->sdvox_reg == SDVOC) |
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131 | port = VIDEO_DIP_PORT_C; |
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132 | else |
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133 | return; |
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134 | |||
135 | flags = intel_infoframe_index(frame); |
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136 | |||
137 | val &= ~VIDEO_DIP_SELECT_MASK; |
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138 | |||
139 | I915_WRITE(VIDEO_DIP_CTL, val | port | flags); |
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140 | |||
141 | for (i = 0; i < len; i += 4) { |
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142 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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143 | data++; |
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144 | } |
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145 | |||
146 | flags |= intel_infoframe_flags(frame); |
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147 | |||
148 | I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); |
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149 | } |
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150 | |||
151 | static void ironlake_write_infoframe(struct drm_encoder *encoder, |
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152 | struct dip_infoframe *frame) |
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153 | { |
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154 | uint32_t *data = (uint32_t *)frame; |
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155 | struct drm_device *dev = encoder->dev; |
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156 | struct drm_i915_private *dev_priv = dev->dev_private; |
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157 | struct drm_crtc *crtc = encoder->crtc; |
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158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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159 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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160 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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161 | u32 flags, val = I915_READ(reg); |
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162 | |||
163 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
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164 | |||
165 | flags = intel_infoframe_index(frame); |
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166 | |||
2342 | Serge | 167 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
2330 | Serge | 168 | |
2342 | Serge | 169 | I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); |
2330 | Serge | 170 | |
171 | for (i = 0; i < len; i += 4) { |
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172 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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173 | data++; |
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174 | } |
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175 | |||
176 | flags |= intel_infoframe_flags(frame); |
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177 | |||
178 | I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); |
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179 | } |
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180 | static void intel_set_infoframe(struct drm_encoder *encoder, |
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181 | struct dip_infoframe *frame) |
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182 | { |
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183 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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184 | |||
185 | if (!intel_hdmi->has_hdmi_sink) |
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186 | return; |
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187 | |||
188 | intel_dip_infoframe_csum(frame); |
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189 | intel_hdmi->write_infoframe(encoder, frame); |
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190 | } |
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191 | |||
192 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) |
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193 | { |
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194 | struct dip_infoframe avi_if = { |
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195 | .type = DIP_TYPE_AVI, |
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196 | .ver = DIP_VERSION_AVI, |
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197 | .len = DIP_LEN_AVI, |
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198 | }; |
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199 | |||
200 | intel_set_infoframe(encoder, &avi_if); |
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201 | } |
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202 | |||
203 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
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204 | { |
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205 | struct dip_infoframe spd_if; |
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206 | |||
207 | memset(&spd_if, 0, sizeof(spd_if)); |
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208 | spd_if.type = DIP_TYPE_SPD; |
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209 | spd_if.ver = DIP_VERSION_SPD; |
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210 | spd_if.len = DIP_LEN_SPD; |
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211 | strcpy(spd_if.body.spd.vn, "Intel"); |
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212 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
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213 | spd_if.body.spd.sdi = DIP_SPD_PC; |
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214 | |||
215 | intel_set_infoframe(encoder, &spd_if); |
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216 | } |
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217 | |||
218 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
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219 | struct drm_display_mode *mode, |
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220 | struct drm_display_mode *adjusted_mode) |
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221 | { |
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222 | struct drm_device *dev = encoder->dev; |
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223 | struct drm_i915_private *dev_priv = dev->dev_private; |
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224 | struct drm_crtc *crtc = encoder->crtc; |
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225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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226 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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227 | u32 sdvox; |
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228 | |||
229 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
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230 | if (!HAS_PCH_SPLIT(dev)) |
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231 | sdvox |= intel_hdmi->color_range; |
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232 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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233 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
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234 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
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235 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
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236 | |||
237 | if (intel_crtc->bpp > 24) |
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238 | sdvox |= COLOR_FORMAT_12bpc; |
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239 | else |
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240 | sdvox |= COLOR_FORMAT_8bpc; |
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241 | |||
242 | /* Required on CPT */ |
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243 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
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244 | sdvox |= HDMI_MODE_SELECT; |
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245 | |||
246 | if (intel_hdmi->has_audio) { |
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2342 | Serge | 247 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
248 | pipe_name(intel_crtc->pipe)); |
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2330 | Serge | 249 | sdvox |= SDVO_AUDIO_ENABLE; |
250 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
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2342 | Serge | 251 | intel_write_eld(encoder, adjusted_mode); |
2330 | Serge | 252 | } |
253 | |||
254 | if (HAS_PCH_CPT(dev)) |
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2342 | Serge | 255 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
256 | else if (intel_crtc->pipe == 1) |
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2330 | Serge | 257 | sdvox |= SDVO_PIPE_B_SELECT; |
258 | |||
259 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
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260 | POSTING_READ(intel_hdmi->sdvox_reg); |
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261 | |||
262 | intel_hdmi_set_avi_infoframe(encoder); |
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263 | intel_hdmi_set_spd_infoframe(encoder); |
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264 | } |
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265 | |||
266 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) |
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267 | { |
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268 | struct drm_device *dev = encoder->dev; |
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269 | struct drm_i915_private *dev_priv = dev->dev_private; |
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270 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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271 | u32 temp; |
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2342 | Serge | 272 | u32 enable_bits = SDVO_ENABLE; |
2330 | Serge | 273 | |
2342 | Serge | 274 | if (intel_hdmi->has_audio) |
275 | enable_bits |= SDVO_AUDIO_ENABLE; |
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276 | |||
2330 | Serge | 277 | temp = I915_READ(intel_hdmi->sdvox_reg); |
278 | |||
279 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
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280 | * we do this anyway which shows more stable in testing. |
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281 | */ |
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282 | if (HAS_PCH_SPLIT(dev)) { |
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283 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
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284 | POSTING_READ(intel_hdmi->sdvox_reg); |
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285 | } |
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286 | |||
287 | if (mode != DRM_MODE_DPMS_ON) { |
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2342 | Serge | 288 | temp &= ~enable_bits; |
2330 | Serge | 289 | } else { |
2342 | Serge | 290 | temp |= enable_bits; |
2330 | Serge | 291 | } |
292 | |||
293 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
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294 | POSTING_READ(intel_hdmi->sdvox_reg); |
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295 | |||
296 | /* HW workaround, need to write this twice for issue that may result |
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297 | * in first write getting masked. |
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298 | */ |
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299 | if (HAS_PCH_SPLIT(dev)) { |
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300 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
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301 | POSTING_READ(intel_hdmi->sdvox_reg); |
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302 | } |
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303 | } |
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304 | |||
305 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
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306 | struct drm_display_mode *mode) |
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307 | { |
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308 | if (mode->clock > 165000) |
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309 | return MODE_CLOCK_HIGH; |
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310 | if (mode->clock < 20000) |
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311 | return MODE_CLOCK_LOW; |
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312 | |||
313 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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314 | return MODE_NO_DBLESCAN; |
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315 | |||
316 | return MODE_OK; |
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317 | } |
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318 | |||
319 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
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320 | struct drm_display_mode *mode, |
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321 | struct drm_display_mode *adjusted_mode) |
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322 | { |
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323 | return true; |
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324 | } |
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325 | |||
326 | static enum drm_connector_status |
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327 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
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328 | { |
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329 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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330 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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331 | struct edid *edid; |
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332 | enum drm_connector_status status = connector_status_disconnected; |
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333 | |||
334 | intel_hdmi->has_hdmi_sink = false; |
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335 | intel_hdmi->has_audio = false; |
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336 | edid = drm_get_edid(connector, |
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337 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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338 | |||
339 | if (edid) { |
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340 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
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341 | status = connector_status_connected; |
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342 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
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343 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
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344 | } |
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345 | connector->display_info.raw_edid = NULL; |
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346 | kfree(edid); |
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347 | } |
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348 | |||
349 | if (status == connector_status_connected) { |
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350 | if (intel_hdmi->force_audio) |
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351 | intel_hdmi->has_audio = intel_hdmi->force_audio > 0; |
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352 | } |
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353 | |||
354 | return status; |
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355 | } |
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356 | |||
357 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
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358 | { |
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359 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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360 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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361 | |||
362 | /* We should parse the EDID data and find out if it's an HDMI sink so |
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363 | * we can send audio to it. |
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364 | */ |
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365 | |||
366 | return intel_ddc_get_modes(connector, |
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367 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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368 | } |
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369 | |||
370 | static bool |
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371 | intel_hdmi_detect_audio(struct drm_connector *connector) |
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372 | { |
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373 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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374 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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375 | struct edid *edid; |
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376 | bool has_audio = false; |
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377 | |||
378 | edid = drm_get_edid(connector, |
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379 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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380 | if (edid) { |
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381 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
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382 | has_audio = drm_detect_monitor_audio(edid); |
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383 | |||
384 | connector->display_info.raw_edid = NULL; |
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385 | kfree(edid); |
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386 | } |
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387 | |||
388 | return has_audio; |
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389 | } |
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390 | |||
391 | static int |
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392 | intel_hdmi_set_property(struct drm_connector *connector, |
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393 | struct drm_property *property, |
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394 | uint64_t val) |
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395 | { |
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396 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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397 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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398 | int ret; |
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399 | |||
400 | ret = drm_connector_property_set_value(connector, property, val); |
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401 | if (ret) |
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402 | return ret; |
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403 | #if 0 |
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404 | if (property == dev_priv->force_audio_property) { |
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405 | int i = val; |
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406 | bool has_audio; |
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407 | |||
408 | if (i == intel_hdmi->force_audio) |
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409 | return 0; |
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410 | |||
411 | intel_hdmi->force_audio = i; |
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412 | |||
413 | if (i == 0) |
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414 | has_audio = intel_hdmi_detect_audio(connector); |
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415 | else |
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416 | has_audio = i > 0; |
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417 | |||
418 | if (has_audio == intel_hdmi->has_audio) |
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419 | return 0; |
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420 | |||
421 | intel_hdmi->has_audio = has_audio; |
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422 | goto done; |
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423 | } |
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424 | |||
425 | if (property == dev_priv->broadcast_rgb_property) { |
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426 | if (val == !!intel_hdmi->color_range) |
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427 | return 0; |
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428 | |||
429 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
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430 | goto done; |
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431 | } |
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432 | #endif |
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433 | return -EINVAL; |
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434 | |||
435 | done: |
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436 | if (intel_hdmi->base.base.crtc) { |
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437 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
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438 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
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439 | crtc->x, crtc->y, |
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440 | crtc->fb); |
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441 | } |
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442 | |||
443 | return 0; |
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444 | } |
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445 | |||
446 | static void intel_hdmi_destroy(struct drm_connector *connector) |
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447 | { |
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448 | drm_sysfs_connector_remove(connector); |
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449 | drm_connector_cleanup(connector); |
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450 | kfree(connector); |
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451 | } |
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452 | |||
453 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
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454 | .dpms = intel_hdmi_dpms, |
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455 | .mode_fixup = intel_hdmi_mode_fixup, |
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456 | .prepare = intel_encoder_prepare, |
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457 | .mode_set = intel_hdmi_mode_set, |
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458 | .commit = intel_encoder_commit, |
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459 | }; |
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460 | |||
461 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
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462 | .dpms = drm_helper_connector_dpms, |
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463 | .detect = intel_hdmi_detect, |
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464 | .fill_modes = drm_helper_probe_single_connector_modes, |
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465 | .set_property = intel_hdmi_set_property, |
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466 | .destroy = intel_hdmi_destroy, |
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467 | }; |
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468 | |||
469 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
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470 | .get_modes = intel_hdmi_get_modes, |
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471 | .mode_valid = intel_hdmi_mode_valid, |
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472 | .best_encoder = intel_best_encoder, |
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473 | }; |
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474 | |||
475 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
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476 | .destroy = intel_encoder_destroy, |
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477 | }; |
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478 | |||
479 | static void |
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480 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
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481 | { |
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482 | intel_attach_force_audio_property(connector); |
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483 | intel_attach_broadcast_rgb_property(connector); |
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484 | } |
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485 | |||
486 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
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487 | { |
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488 | struct drm_i915_private *dev_priv = dev->dev_private; |
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489 | struct drm_connector *connector; |
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490 | struct intel_encoder *intel_encoder; |
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491 | struct intel_connector *intel_connector; |
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492 | struct intel_hdmi *intel_hdmi; |
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2342 | Serge | 493 | int i; |
2330 | Serge | 494 | |
495 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
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496 | if (!intel_hdmi) |
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497 | return; |
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498 | |||
499 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
500 | if (!intel_connector) { |
||
501 | kfree(intel_hdmi); |
||
502 | return; |
||
503 | } |
||
504 | |||
505 | intel_encoder = &intel_hdmi->base; |
||
506 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
||
507 | DRM_MODE_ENCODER_TMDS); |
||
508 | |||
509 | connector = &intel_connector->base; |
||
510 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
||
511 | DRM_MODE_CONNECTOR_HDMIA); |
||
512 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
||
513 | |||
514 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
||
515 | |||
516 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
||
517 | connector->interlace_allowed = 0; |
||
518 | connector->doublescan_allowed = 0; |
||
2342 | Serge | 519 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2330 | Serge | 520 | |
521 | /* Set up the DDC bus. */ |
||
522 | if (sdvox_reg == SDVOB) { |
||
523 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
||
524 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
||
525 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
||
526 | } else if (sdvox_reg == SDVOC) { |
||
527 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
||
528 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
||
529 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
||
530 | } else if (sdvox_reg == HDMIB) { |
||
531 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
||
532 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
||
533 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
||
534 | } else if (sdvox_reg == HDMIC) { |
||
535 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
||
536 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
||
537 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
||
538 | } else if (sdvox_reg == HDMID) { |
||
539 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
||
540 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
||
541 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
||
542 | } |
||
543 | |||
544 | intel_hdmi->sdvox_reg = sdvox_reg; |
||
545 | |||
2342 | Serge | 546 | if (!HAS_PCH_SPLIT(dev)) { |
2330 | Serge | 547 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
2342 | Serge | 548 | I915_WRITE(VIDEO_DIP_CTL, 0); |
549 | } else { |
||
2330 | Serge | 550 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
2342 | Serge | 551 | for_each_pipe(i) |
552 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
||
553 | } |
||
2330 | Serge | 554 | |
555 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
||
556 | |||
557 | intel_hdmi_add_properties(intel_hdmi, connector); |
||
558 | |||
559 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
560 | drm_sysfs_connector_add(connector); |
||
561 | |||
562 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
563 | * 0xd. Failure to do so will result in spurious interrupts being |
||
564 | * generated on the port when a cable is not attached. |
||
565 | */ |
||
566 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
567 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
568 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
569 | } |
||
570 | }><>><>><>><>><>><>><>><>>>>> |