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2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
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3 | * Copyright © 2006-2009 Intel Corporation |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Jesse Barnes |
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27 | */ |
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28 | |||
29 | #include |
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30 | #include |
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31 | //#include |
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32 | #include "drmP.h" |
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33 | #include "drm.h" |
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34 | #include "drm_crtc.h" |
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35 | #include "drm_edid.h" |
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36 | #include "intel_drv.h" |
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37 | #include "i915_drm.h" |
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38 | #include "i915_drv.h" |
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39 | |||
40 | struct intel_hdmi { |
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41 | struct intel_encoder base; |
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42 | u32 sdvox_reg; |
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43 | int ddc_bus; |
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44 | uint32_t color_range; |
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45 | bool has_hdmi_sink; |
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46 | bool has_audio; |
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47 | int force_audio; |
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48 | void (*write_infoframe)(struct drm_encoder *encoder, |
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49 | struct dip_infoframe *frame); |
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50 | }; |
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51 | |||
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
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53 | { |
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54 | return container_of(encoder, struct intel_hdmi, base.base); |
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55 | } |
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56 | |||
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
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58 | { |
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59 | return container_of(intel_attached_encoder(connector), |
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60 | struct intel_hdmi, base); |
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61 | } |
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62 | |||
63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
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64 | { |
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65 | uint8_t *data = (uint8_t *)frame; |
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66 | uint8_t sum = 0; |
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67 | unsigned i; |
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68 | |||
69 | frame->checksum = 0; |
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70 | frame->ecc = 0; |
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71 | |||
72 | /* Header isn't part of the checksum */ |
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73 | for (i = 5; i < frame->len; i++) |
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74 | sum += data[i]; |
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75 | |||
76 | frame->checksum = 0x100 - sum; |
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77 | } |
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78 | |||
79 | static u32 intel_infoframe_index(struct dip_infoframe *frame) |
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80 | { |
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81 | u32 flags = 0; |
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82 | |||
83 | switch (frame->type) { |
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84 | case DIP_TYPE_AVI: |
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85 | flags |= VIDEO_DIP_SELECT_AVI; |
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86 | break; |
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87 | case DIP_TYPE_SPD: |
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88 | flags |= VIDEO_DIP_SELECT_SPD; |
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89 | break; |
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90 | default: |
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91 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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92 | break; |
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93 | } |
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94 | |||
95 | return flags; |
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96 | } |
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97 | |||
98 | static u32 intel_infoframe_flags(struct dip_infoframe *frame) |
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99 | { |
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100 | u32 flags = 0; |
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101 | |||
102 | switch (frame->type) { |
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103 | case DIP_TYPE_AVI: |
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104 | flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; |
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105 | break; |
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106 | case DIP_TYPE_SPD: |
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107 | flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC; |
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108 | break; |
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109 | default: |
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110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
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111 | break; |
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112 | } |
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113 | |||
114 | return flags; |
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115 | } |
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116 | |||
117 | static void i9xx_write_infoframe(struct drm_encoder *encoder, |
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118 | struct dip_infoframe *frame) |
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119 | { |
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120 | uint32_t *data = (uint32_t *)frame; |
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121 | struct drm_device *dev = encoder->dev; |
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122 | struct drm_i915_private *dev_priv = dev->dev_private; |
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123 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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124 | u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); |
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125 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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126 | |||
127 | |||
128 | /* XXX first guess at handling video port, is this corrent? */ |
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129 | if (intel_hdmi->sdvox_reg == SDVOB) |
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130 | port = VIDEO_DIP_PORT_B; |
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131 | else if (intel_hdmi->sdvox_reg == SDVOC) |
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132 | port = VIDEO_DIP_PORT_C; |
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133 | else |
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134 | return; |
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135 | |||
136 | flags = intel_infoframe_index(frame); |
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137 | |||
138 | val &= ~VIDEO_DIP_SELECT_MASK; |
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139 | |||
140 | I915_WRITE(VIDEO_DIP_CTL, val | port | flags); |
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141 | |||
142 | for (i = 0; i < len; i += 4) { |
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143 | I915_WRITE(VIDEO_DIP_DATA, *data); |
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144 | data++; |
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145 | } |
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146 | |||
147 | flags |= intel_infoframe_flags(frame); |
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148 | |||
149 | I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); |
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150 | } |
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151 | |||
152 | static void ironlake_write_infoframe(struct drm_encoder *encoder, |
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153 | struct dip_infoframe *frame) |
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154 | { |
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155 | uint32_t *data = (uint32_t *)frame; |
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156 | struct drm_device *dev = encoder->dev; |
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157 | struct drm_i915_private *dev_priv = dev->dev_private; |
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158 | struct drm_crtc *crtc = encoder->crtc; |
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159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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160 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
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161 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
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162 | u32 flags, val = I915_READ(reg); |
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163 | |||
164 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
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165 | |||
166 | flags = intel_infoframe_index(frame); |
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167 | |||
168 | val &= ~VIDEO_DIP_SELECT_MASK; |
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169 | |||
170 | I915_WRITE(reg, val | flags); |
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171 | |||
172 | for (i = 0; i < len; i += 4) { |
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173 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
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174 | data++; |
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175 | } |
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176 | |||
177 | flags |= intel_infoframe_flags(frame); |
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178 | |||
179 | I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); |
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180 | } |
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181 | static void intel_set_infoframe(struct drm_encoder *encoder, |
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182 | struct dip_infoframe *frame) |
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183 | { |
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184 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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185 | |||
186 | if (!intel_hdmi->has_hdmi_sink) |
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187 | return; |
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188 | |||
189 | intel_dip_infoframe_csum(frame); |
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190 | intel_hdmi->write_infoframe(encoder, frame); |
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191 | } |
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192 | |||
193 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) |
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194 | { |
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195 | struct dip_infoframe avi_if = { |
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196 | .type = DIP_TYPE_AVI, |
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197 | .ver = DIP_VERSION_AVI, |
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198 | .len = DIP_LEN_AVI, |
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199 | }; |
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200 | |||
201 | intel_set_infoframe(encoder, &avi_if); |
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202 | } |
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203 | |||
204 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
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205 | { |
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206 | struct dip_infoframe spd_if; |
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207 | |||
208 | memset(&spd_if, 0, sizeof(spd_if)); |
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209 | spd_if.type = DIP_TYPE_SPD; |
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210 | spd_if.ver = DIP_VERSION_SPD; |
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211 | spd_if.len = DIP_LEN_SPD; |
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212 | strcpy(spd_if.body.spd.vn, "Intel"); |
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213 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
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214 | spd_if.body.spd.sdi = DIP_SPD_PC; |
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215 | |||
216 | intel_set_infoframe(encoder, &spd_if); |
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217 | } |
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218 | |||
219 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
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220 | struct drm_display_mode *mode, |
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221 | struct drm_display_mode *adjusted_mode) |
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222 | { |
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223 | struct drm_device *dev = encoder->dev; |
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224 | struct drm_i915_private *dev_priv = dev->dev_private; |
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225 | struct drm_crtc *crtc = encoder->crtc; |
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226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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227 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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228 | u32 sdvox; |
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229 | |||
230 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
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231 | if (!HAS_PCH_SPLIT(dev)) |
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232 | sdvox |= intel_hdmi->color_range; |
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233 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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234 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
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235 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
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236 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
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237 | |||
238 | if (intel_crtc->bpp > 24) |
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239 | sdvox |= COLOR_FORMAT_12bpc; |
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240 | else |
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241 | sdvox |= COLOR_FORMAT_8bpc; |
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242 | |||
243 | /* Required on CPT */ |
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244 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
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245 | sdvox |= HDMI_MODE_SELECT; |
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246 | |||
247 | if (intel_hdmi->has_audio) { |
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248 | sdvox |= SDVO_AUDIO_ENABLE; |
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249 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
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250 | } |
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251 | |||
252 | if (intel_crtc->pipe == 1) { |
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253 | if (HAS_PCH_CPT(dev)) |
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254 | sdvox |= PORT_TRANS_B_SEL_CPT; |
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255 | else |
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256 | sdvox |= SDVO_PIPE_B_SELECT; |
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257 | } |
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258 | |||
259 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
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260 | POSTING_READ(intel_hdmi->sdvox_reg); |
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261 | |||
262 | intel_hdmi_set_avi_infoframe(encoder); |
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263 | intel_hdmi_set_spd_infoframe(encoder); |
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264 | } |
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265 | |||
266 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) |
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267 | { |
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268 | struct drm_device *dev = encoder->dev; |
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269 | struct drm_i915_private *dev_priv = dev->dev_private; |
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270 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
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271 | u32 temp; |
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272 | |||
273 | temp = I915_READ(intel_hdmi->sdvox_reg); |
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274 | |||
275 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
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276 | * we do this anyway which shows more stable in testing. |
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277 | */ |
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278 | if (HAS_PCH_SPLIT(dev)) { |
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279 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
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280 | POSTING_READ(intel_hdmi->sdvox_reg); |
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281 | } |
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282 | |||
283 | if (mode != DRM_MODE_DPMS_ON) { |
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284 | temp &= ~SDVO_ENABLE; |
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285 | } else { |
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286 | temp |= SDVO_ENABLE; |
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287 | } |
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288 | |||
289 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
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290 | POSTING_READ(intel_hdmi->sdvox_reg); |
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291 | |||
292 | /* HW workaround, need to write this twice for issue that may result |
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293 | * in first write getting masked. |
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294 | */ |
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295 | if (HAS_PCH_SPLIT(dev)) { |
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296 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
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297 | POSTING_READ(intel_hdmi->sdvox_reg); |
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298 | } |
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299 | } |
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300 | |||
301 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
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302 | struct drm_display_mode *mode) |
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303 | { |
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304 | if (mode->clock > 165000) |
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305 | return MODE_CLOCK_HIGH; |
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306 | if (mode->clock < 20000) |
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307 | return MODE_CLOCK_LOW; |
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308 | |||
309 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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310 | return MODE_NO_DBLESCAN; |
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311 | |||
312 | return MODE_OK; |
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313 | } |
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314 | |||
315 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
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316 | struct drm_display_mode *mode, |
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317 | struct drm_display_mode *adjusted_mode) |
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318 | { |
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319 | return true; |
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320 | } |
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321 | |||
322 | static enum drm_connector_status |
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323 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
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324 | { |
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325 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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326 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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327 | struct edid *edid; |
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328 | enum drm_connector_status status = connector_status_disconnected; |
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329 | |||
330 | intel_hdmi->has_hdmi_sink = false; |
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331 | intel_hdmi->has_audio = false; |
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332 | edid = drm_get_edid(connector, |
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333 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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334 | |||
335 | if (edid) { |
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336 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
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337 | status = connector_status_connected; |
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338 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
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339 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
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340 | } |
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341 | connector->display_info.raw_edid = NULL; |
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342 | kfree(edid); |
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343 | } |
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344 | |||
345 | if (status == connector_status_connected) { |
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346 | if (intel_hdmi->force_audio) |
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347 | intel_hdmi->has_audio = intel_hdmi->force_audio > 0; |
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348 | } |
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349 | |||
350 | return status; |
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351 | } |
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352 | |||
353 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
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354 | { |
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355 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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356 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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357 | |||
358 | /* We should parse the EDID data and find out if it's an HDMI sink so |
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359 | * we can send audio to it. |
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360 | */ |
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361 | |||
362 | return intel_ddc_get_modes(connector, |
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363 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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364 | } |
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365 | |||
366 | static bool |
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367 | intel_hdmi_detect_audio(struct drm_connector *connector) |
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368 | { |
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369 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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370 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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371 | struct edid *edid; |
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372 | bool has_audio = false; |
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373 | |||
374 | edid = drm_get_edid(connector, |
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375 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
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376 | if (edid) { |
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377 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
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378 | has_audio = drm_detect_monitor_audio(edid); |
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379 | |||
380 | connector->display_info.raw_edid = NULL; |
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381 | kfree(edid); |
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382 | } |
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383 | |||
384 | return has_audio; |
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385 | } |
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386 | |||
387 | static int |
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388 | intel_hdmi_set_property(struct drm_connector *connector, |
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389 | struct drm_property *property, |
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390 | uint64_t val) |
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391 | { |
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392 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
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393 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
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394 | int ret; |
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395 | |||
396 | ret = drm_connector_property_set_value(connector, property, val); |
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397 | if (ret) |
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398 | return ret; |
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399 | #if 0 |
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400 | if (property == dev_priv->force_audio_property) { |
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401 | int i = val; |
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402 | bool has_audio; |
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403 | |||
404 | if (i == intel_hdmi->force_audio) |
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405 | return 0; |
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406 | |||
407 | intel_hdmi->force_audio = i; |
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408 | |||
409 | if (i == 0) |
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410 | has_audio = intel_hdmi_detect_audio(connector); |
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411 | else |
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412 | has_audio = i > 0; |
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413 | |||
414 | if (has_audio == intel_hdmi->has_audio) |
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415 | return 0; |
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416 | |||
417 | intel_hdmi->has_audio = has_audio; |
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418 | goto done; |
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419 | } |
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420 | |||
421 | if (property == dev_priv->broadcast_rgb_property) { |
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422 | if (val == !!intel_hdmi->color_range) |
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423 | return 0; |
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424 | |||
425 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
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426 | goto done; |
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427 | } |
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428 | #endif |
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429 | return -EINVAL; |
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430 | |||
431 | done: |
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432 | if (intel_hdmi->base.base.crtc) { |
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433 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
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434 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
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435 | crtc->x, crtc->y, |
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436 | crtc->fb); |
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437 | } |
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438 | |||
439 | return 0; |
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440 | } |
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441 | |||
442 | static void intel_hdmi_destroy(struct drm_connector *connector) |
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443 | { |
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444 | drm_sysfs_connector_remove(connector); |
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445 | drm_connector_cleanup(connector); |
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446 | kfree(connector); |
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447 | } |
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448 | |||
449 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
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450 | .dpms = intel_hdmi_dpms, |
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451 | .mode_fixup = intel_hdmi_mode_fixup, |
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452 | .prepare = intel_encoder_prepare, |
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453 | .mode_set = intel_hdmi_mode_set, |
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454 | .commit = intel_encoder_commit, |
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455 | }; |
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456 | |||
457 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
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458 | .dpms = drm_helper_connector_dpms, |
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459 | .detect = intel_hdmi_detect, |
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460 | .fill_modes = drm_helper_probe_single_connector_modes, |
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461 | .set_property = intel_hdmi_set_property, |
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462 | .destroy = intel_hdmi_destroy, |
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463 | }; |
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464 | |||
465 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
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466 | .get_modes = intel_hdmi_get_modes, |
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467 | .mode_valid = intel_hdmi_mode_valid, |
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468 | .best_encoder = intel_best_encoder, |
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469 | }; |
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470 | |||
471 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
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472 | .destroy = intel_encoder_destroy, |
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473 | }; |
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474 | |||
475 | static void |
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476 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
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477 | { |
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478 | intel_attach_force_audio_property(connector); |
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479 | intel_attach_broadcast_rgb_property(connector); |
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480 | } |
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481 | |||
482 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
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483 | { |
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484 | struct drm_i915_private *dev_priv = dev->dev_private; |
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485 | struct drm_connector *connector; |
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486 | struct intel_encoder *intel_encoder; |
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487 | struct intel_connector *intel_connector; |
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488 | struct intel_hdmi *intel_hdmi; |
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489 | |||
490 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
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491 | if (!intel_hdmi) |
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492 | return; |
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493 | |||
494 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
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495 | if (!intel_connector) { |
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496 | kfree(intel_hdmi); |
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497 | return; |
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498 | } |
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499 | |||
500 | intel_encoder = &intel_hdmi->base; |
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501 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
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502 | DRM_MODE_ENCODER_TMDS); |
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503 | |||
504 | connector = &intel_connector->base; |
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505 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
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506 | DRM_MODE_CONNECTOR_HDMIA); |
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507 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
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508 | |||
509 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
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510 | |||
511 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
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512 | connector->interlace_allowed = 0; |
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513 | connector->doublescan_allowed = 0; |
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514 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
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515 | |||
516 | /* Set up the DDC bus. */ |
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517 | if (sdvox_reg == SDVOB) { |
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518 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
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519 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
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520 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
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521 | } else if (sdvox_reg == SDVOC) { |
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522 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
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523 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
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524 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
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525 | } else if (sdvox_reg == HDMIB) { |
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526 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
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527 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
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528 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
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529 | } else if (sdvox_reg == HDMIC) { |
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530 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
||
531 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
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532 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
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533 | } else if (sdvox_reg == HDMID) { |
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534 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
||
535 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
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536 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
||
537 | } |
||
538 | |||
539 | intel_hdmi->sdvox_reg = sdvox_reg; |
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540 | |||
541 | if (!HAS_PCH_SPLIT(dev)) |
||
542 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
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543 | else |
||
544 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
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545 | |||
546 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
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547 | |||
548 | intel_hdmi_add_properties(intel_hdmi, connector); |
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549 | |||
550 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
551 | drm_sysfs_connector_add(connector); |
||
552 | |||
553 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
554 | * 0xd. Failure to do so will result in spurious interrupts being |
||
555 | * generated on the port when a cable is not attached. |
||
556 | */ |
||
557 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
558 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
559 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
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560 | } |
||
561 | }><>><>><>><>><>><>><>>>>> |