Rev 6937 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Vinit Azad |
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25 | * Ben Widawsky |
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26 | * Dave Gordon |
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27 | * Alex Dai |
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28 | */ |
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29 | #include |
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30 | #include "i915_drv.h" |
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31 | #include "intel_guc.h" |
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32 | |||
33 | /** |
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6937 | serge | 34 | * DOC: GuC-specific firmware loader |
6084 | serge | 35 | * |
36 | * intel_guc: |
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37 | * Top level structure of guc. It handles firmware loading and manages client |
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38 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy |
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39 | * ExecList submission. |
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40 | * |
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41 | * Firmware versioning: |
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42 | * The firmware build process will generate a version header file with major and |
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43 | * minor version defined. The versions are built into CSS header of firmware. |
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44 | * i915 kernel driver set the minimal firmware version required per platform. |
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45 | * The firmware installation package will install (symbolic link) proper version |
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46 | * of firmware. |
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47 | * |
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48 | * GuC address space: |
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49 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), |
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50 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is |
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51 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects |
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52 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. |
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53 | * |
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54 | * Firmware log: |
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55 | * Firmware log is enabled by setting i915.guc_log_level to non-negative level. |
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56 | * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from |
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57 | * i915_guc_load_status will print out firmware loading status and scratch |
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58 | * registers value. |
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59 | * |
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60 | */ |
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61 | |||
62 | #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin" |
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63 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
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64 | |||
65 | /* User-friendly representation of an enum */ |
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66 | const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) |
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67 | { |
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68 | switch (status) { |
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69 | case GUC_FIRMWARE_FAIL: |
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70 | return "FAIL"; |
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71 | case GUC_FIRMWARE_NONE: |
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72 | return "NONE"; |
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73 | case GUC_FIRMWARE_PENDING: |
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74 | return "PENDING"; |
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75 | case GUC_FIRMWARE_SUCCESS: |
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76 | return "SUCCESS"; |
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77 | default: |
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78 | return "UNKNOWN!"; |
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79 | } |
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80 | }; |
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81 | |||
82 | static void direct_interrupts_to_host(struct drm_i915_private *dev_priv) |
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83 | { |
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84 | struct intel_engine_cs *ring; |
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85 | int i, irqs; |
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86 | |||
87 | /* tell all command streamers NOT to forward interrupts and vblank to GuC */ |
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88 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); |
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89 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); |
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90 | for_each_ring(ring, dev_priv, i) |
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91 | I915_WRITE(RING_MODE_GEN7(ring), irqs); |
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92 | |||
93 | /* route all GT interrupts to the host */ |
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94 | I915_WRITE(GUC_BCS_RCS_IER, 0); |
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95 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); |
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96 | I915_WRITE(GUC_WD_VECS_IER, 0); |
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97 | } |
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98 | |||
99 | static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv) |
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100 | { |
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101 | struct intel_engine_cs *ring; |
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102 | int i, irqs; |
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103 | |||
104 | /* tell all command streamers to forward interrupts and vblank to GuC */ |
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105 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS); |
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106 | irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); |
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107 | for_each_ring(ring, dev_priv, i) |
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108 | I915_WRITE(RING_MODE_GEN7(ring), irqs); |
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109 | |||
110 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
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111 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
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112 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
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113 | /* These three registers have the same bit definitions */ |
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114 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); |
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115 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); |
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116 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); |
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117 | } |
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118 | |||
119 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
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120 | { |
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121 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ |
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122 | return 0; |
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123 | } |
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124 | |||
125 | static u32 get_core_family(struct drm_i915_private *dev_priv) |
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126 | { |
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127 | switch (INTEL_INFO(dev_priv)->gen) { |
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128 | case 9: |
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129 | return GFXCORE_FAMILY_GEN9; |
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130 | |||
131 | default: |
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132 | DRM_ERROR("GUC: unsupported core family\n"); |
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133 | return GFXCORE_FAMILY_UNKNOWN; |
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134 | } |
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135 | } |
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136 | |||
137 | static void set_guc_init_params(struct drm_i915_private *dev_priv) |
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138 | { |
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139 | struct intel_guc *guc = &dev_priv->guc; |
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140 | u32 params[GUC_CTL_MAX_DWORDS]; |
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141 | int i; |
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142 | |||
143 | memset(¶ms, 0, sizeof(params)); |
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144 | |||
145 | params[GUC_CTL_DEVICE_INFO] |= |
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146 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | |
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147 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); |
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148 | |||
149 | /* |
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150 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one |
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151 | * second. This ARAR is calculated by: |
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152 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 |
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153 | */ |
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154 | params[GUC_CTL_ARAT_HIGH] = 0; |
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155 | params[GUC_CTL_ARAT_LOW] = 100000000; |
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156 | |||
157 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; |
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158 | |||
159 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | |
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160 | GUC_CTL_VCS2_ENABLED; |
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161 | |||
162 | if (i915.guc_log_level >= 0) { |
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163 | params[GUC_CTL_LOG_PARAMS] = guc->log_flags; |
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164 | params[GUC_CTL_DEBUG] = |
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165 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; |
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166 | } |
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167 | |||
7144 | serge | 168 | if (guc->ads_obj) { |
169 | u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj) |
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170 | >> PAGE_SHIFT; |
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171 | params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT; |
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172 | params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED; |
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173 | } |
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174 | |||
6084 | serge | 175 | /* If GuC submission is enabled, set up additional parameters here */ |
176 | if (i915.enable_guc_submission) { |
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177 | u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); |
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178 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; |
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179 | |||
180 | pgs >>= PAGE_SHIFT; |
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181 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | |
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182 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); |
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183 | |||
184 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; |
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185 | |||
186 | /* Unmask this bit to enable the GuC's internal scheduler */ |
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187 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; |
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188 | } |
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189 | |||
190 | I915_WRITE(SOFT_SCRATCH(0), 0); |
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191 | |||
192 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) |
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193 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); |
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194 | } |
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195 | |||
196 | /* |
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197 | * Read the GuC status register (GUC_STATUS) and store it in the |
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198 | * specified location; then return a boolean indicating whether |
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199 | * the value matches either of two values representing completion |
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200 | * of the GuC boot process. |
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201 | * |
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7144 | serge | 202 | * This is used for polling the GuC status in a wait_for() |
6084 | serge | 203 | * loop below. |
204 | */ |
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205 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, |
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206 | u32 *status) |
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207 | { |
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208 | u32 val = I915_READ(GUC_STATUS); |
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209 | u32 uk_val = val & GS_UKERNEL_MASK; |
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210 | *status = val; |
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211 | return (uk_val == GS_UKERNEL_READY || |
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212 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); |
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213 | } |
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214 | |||
215 | /* |
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216 | * Transfer the firmware image to RAM for execution by the microcontroller. |
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217 | * |
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218 | * Architecturally, the DMA engine is bidirectional, and can potentially even |
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219 | * transfer between GTT locations. This functionality is left out of the API |
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220 | * for now as there is no need for it. |
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221 | * |
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222 | * Note that GuC needs the CSS header plus uKernel code to be copied by the |
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223 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. |
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224 | */ |
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225 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv) |
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226 | { |
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227 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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228 | struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj; |
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229 | unsigned long offset; |
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230 | struct sg_table *sg = fw_obj->pages; |
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6937 | serge | 231 | u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; |
6084 | serge | 232 | int i, ret = 0; |
233 | |||
6937 | serge | 234 | /* where RSA signature starts */ |
235 | offset = guc_fw->rsa_offset; |
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6084 | serge | 236 | |
237 | /* Copy RSA signature from the fw image to HW for verification */ |
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6937 | serge | 238 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset); |
239 | for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++) |
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6084 | serge | 240 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
241 | |||
6937 | serge | 242 | /* The header plus uCode will be copied to WOPCM via DMA, excluding any |
243 | * other components */ |
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244 | I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size); |
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245 | |||
6084 | serge | 246 | /* Set the source address for the new blob */ |
6937 | serge | 247 | offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset; |
6084 | serge | 248 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); |
249 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); |
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250 | |||
251 | /* |
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252 | * Set the DMA destination. Current uCode expects the code to be |
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253 | * loaded at 8k; locations below this are used for the stack. |
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254 | */ |
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255 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); |
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256 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); |
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257 | |||
258 | /* Finally start the DMA */ |
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259 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); |
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260 | |||
261 | /* |
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7144 | serge | 262 | * Wait for the DMA to complete & the GuC to start up. |
6084 | serge | 263 | * NB: Docs recommend not using the interrupt for completion. |
264 | * Measurements indicate this should take no more than 20ms, so a |
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265 | * timeout here indicates that the GuC has failed and is unusable. |
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266 | * (Higher levels of the driver will attempt to fall back to |
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267 | * execlist mode if this happens.) |
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268 | */ |
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7144 | serge | 269 | ret = wait_for(guc_ucode_response(dev_priv, &status), 100); |
6084 | serge | 270 | |
271 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", |
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272 | I915_READ(DMA_CTRL), status); |
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273 | |||
274 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { |
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275 | DRM_ERROR("GuC firmware signature verification failed\n"); |
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276 | ret = -ENOEXEC; |
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277 | } |
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278 | |||
279 | DRM_DEBUG_DRIVER("returning %d\n", ret); |
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280 | |||
281 | return ret; |
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282 | } |
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283 | |||
284 | /* |
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285 | * Load the GuC firmware blob into the MinuteIA. |
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286 | */ |
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287 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) |
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288 | { |
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289 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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290 | struct drm_device *dev = dev_priv->dev; |
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291 | int ret; |
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292 | |||
293 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); |
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294 | if (ret) { |
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295 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); |
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296 | return ret; |
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297 | } |
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298 | |||
299 | ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0); |
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300 | if (ret) { |
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301 | DRM_DEBUG_DRIVER("pin failed %d\n", ret); |
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302 | return ret; |
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303 | } |
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304 | |||
305 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ |
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306 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
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307 | |||
308 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
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309 | |||
310 | /* init WOPCM */ |
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311 | I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE); |
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312 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); |
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313 | |||
314 | /* Enable MIA caching. GuC clock gating is disabled. */ |
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315 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); |
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316 | |||
317 | /* WaDisableMinuteIaClockGating:skl,bxt */ |
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6937 | serge | 318 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
319 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
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6084 | serge | 320 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & |
321 | ~GUC_ENABLE_MIA_CLOCK_GATING)); |
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322 | } |
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323 | |||
324 | /* WaC6DisallowByGfxPause*/ |
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325 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); |
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326 | |||
327 | if (IS_BROXTON(dev)) |
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328 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
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329 | else |
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330 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
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331 | |||
332 | if (IS_GEN9(dev)) { |
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333 | /* DOP Clock Gating Enable for GuC clocks */ |
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334 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | |
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335 | I915_READ(GEN7_MISCCPCTL))); |
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336 | |||
337 | /* allows for 5us before GT can go to RC6 */ |
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338 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); |
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339 | } |
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340 | |||
341 | set_guc_init_params(dev_priv); |
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342 | |||
343 | ret = guc_ucode_xfer_dma(dev_priv); |
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344 | |||
345 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
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346 | |||
347 | /* |
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348 | * We keep the object pages for reuse during resume. But we can unpin it |
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349 | * now that DMA has completed, so it doesn't continue to take up space. |
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350 | */ |
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351 | i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj); |
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352 | |||
353 | return ret; |
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354 | } |
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355 | |||
356 | /** |
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357 | * intel_guc_ucode_load() - load GuC uCode into the device |
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358 | * @dev: drm device |
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359 | * |
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360 | * Called from gem_init_hw() during driver loading and also after a GPU reset. |
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361 | * |
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362 | * The firmware image should have already been fetched into memory by the |
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363 | * earlier call to intel_guc_ucode_init(), so here we need only check that |
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364 | * is succeeded, and then transfer the image to the h/w. |
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365 | * |
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366 | * Return: non-zero code on error |
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367 | */ |
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368 | int intel_guc_ucode_load(struct drm_device *dev) |
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369 | { |
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370 | struct drm_i915_private *dev_priv = dev->dev_private; |
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371 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
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372 | int err = 0; |
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373 | |||
6937 | serge | 374 | if (!i915.enable_guc_submission) |
375 | return 0; |
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376 | |||
6084 | serge | 377 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", |
378 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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379 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); |
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380 | |||
381 | direct_interrupts_to_host(dev_priv); |
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382 | |||
383 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE) |
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384 | return 0; |
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385 | |||
386 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS && |
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387 | guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) |
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388 | return -ENOEXEC; |
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389 | |||
390 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; |
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391 | |||
392 | DRM_DEBUG_DRIVER("GuC fw fetch status %s\n", |
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393 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); |
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394 | |||
395 | switch (guc_fw->guc_fw_fetch_status) { |
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396 | case GUC_FIRMWARE_FAIL: |
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397 | /* something went wrong :( */ |
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398 | err = -EIO; |
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399 | goto fail; |
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400 | |||
401 | case GUC_FIRMWARE_NONE: |
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402 | case GUC_FIRMWARE_PENDING: |
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403 | default: |
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404 | /* "can't happen" */ |
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405 | WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n", |
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406 | guc_fw->guc_fw_path, |
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407 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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408 | guc_fw->guc_fw_fetch_status); |
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409 | err = -ENXIO; |
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410 | goto fail; |
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411 | |||
412 | case GUC_FIRMWARE_SUCCESS: |
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413 | break; |
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414 | } |
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415 | |||
416 | err = i915_guc_submission_init(dev); |
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417 | if (err) |
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418 | goto fail; |
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419 | |||
420 | err = guc_ucode_xfer(dev_priv); |
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421 | if (err) |
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422 | goto fail; |
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423 | |||
424 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; |
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425 | |||
426 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", |
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427 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
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428 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); |
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429 | |||
430 | if (i915.enable_guc_submission) { |
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431 | /* The execbuf_client will be recreated. Release it first. */ |
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432 | i915_guc_submission_disable(dev); |
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433 | |||
434 | err = i915_guc_submission_enable(dev); |
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435 | if (err) |
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436 | goto fail; |
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437 | direct_interrupts_to_guc(dev_priv); |
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438 | } |
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439 | |||
440 | return 0; |
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441 | |||
442 | fail: |
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443 | if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) |
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444 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; |
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445 | |||
446 | direct_interrupts_to_host(dev_priv); |
||
447 | i915_guc_submission_disable(dev); |
||
7144 | serge | 448 | i915_guc_submission_fini(dev); |
6084 | serge | 449 | |
450 | return err; |
||
451 | } |
||
452 | |||
453 | static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) |
||
454 | { |
||
455 | struct drm_i915_gem_object *obj; |
||
456 | const struct firmware *fw; |
||
6937 | serge | 457 | struct guc_css_header *css; |
458 | size_t size; |
||
6084 | serge | 459 | int err; |
460 | |||
461 | DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", |
||
462 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); |
||
463 | |||
464 | err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev); |
||
465 | if (err) |
||
466 | goto fail; |
||
467 | if (!fw) |
||
468 | goto fail; |
||
469 | |||
470 | DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", |
||
471 | guc_fw->guc_fw_path, fw); |
||
472 | |||
6937 | serge | 473 | /* Check the size of the blob before examining buffer contents */ |
474 | if (fw->size < sizeof(struct guc_css_header)) { |
||
475 | DRM_ERROR("Firmware header is missing\n"); |
||
6084 | serge | 476 | goto fail; |
6937 | serge | 477 | } |
6084 | serge | 478 | |
6937 | serge | 479 | css = (struct guc_css_header *)fw->data; |
480 | |||
481 | /* Firmware bits always start from header */ |
||
482 | guc_fw->header_offset = 0; |
||
483 | guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - |
||
484 | css->key_size_dw - css->exponent_size_dw) * sizeof(u32); |
||
485 | |||
486 | if (guc_fw->header_size != sizeof(struct guc_css_header)) { |
||
487 | DRM_ERROR("CSS header definition mismatch\n"); |
||
488 | goto fail; |
||
489 | } |
||
490 | |||
491 | /* then, uCode */ |
||
492 | guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size; |
||
493 | guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); |
||
494 | |||
495 | /* now RSA */ |
||
496 | if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { |
||
497 | DRM_ERROR("RSA key size is bad\n"); |
||
498 | goto fail; |
||
499 | } |
||
500 | guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size; |
||
501 | guc_fw->rsa_size = css->key_size_dw * sizeof(u32); |
||
502 | |||
503 | /* At least, it should have header, uCode and RSA. Size of all three. */ |
||
504 | size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size; |
||
505 | if (fw->size < size) { |
||
506 | DRM_ERROR("Missing firmware components\n"); |
||
507 | goto fail; |
||
508 | } |
||
509 | |||
510 | /* Header and uCode will be loaded to WOPCM. Size of the two. */ |
||
511 | size = guc_fw->header_size + guc_fw->ucode_size; |
||
512 | |||
513 | /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ |
||
514 | if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) { |
||
515 | DRM_ERROR("Firmware is too large to fit in WOPCM\n"); |
||
516 | goto fail; |
||
517 | } |
||
518 | |||
6084 | serge | 519 | /* |
520 | * The GuC firmware image has the version number embedded at a well-known |
||
521 | * offset within the firmware blob; note that major / minor version are |
||
522 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined |
||
523 | * in terms of bytes (u8). |
||
524 | */ |
||
6937 | serge | 525 | guc_fw->guc_fw_major_found = css->guc_sw_version >> 16; |
526 | guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF; |
||
6084 | serge | 527 | |
528 | if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || |
||
529 | guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { |
||
530 | DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n", |
||
531 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, |
||
532 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); |
||
533 | err = -ENOEXEC; |
||
534 | goto fail; |
||
535 | } |
||
536 | |||
537 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", |
||
538 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, |
||
539 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); |
||
540 | |||
541 | mutex_lock(&dev->struct_mutex); |
||
542 | obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); |
||
543 | mutex_unlock(&dev->struct_mutex); |
||
544 | if (IS_ERR_OR_NULL(obj)) { |
||
545 | err = obj ? PTR_ERR(obj) : -ENOMEM; |
||
546 | goto fail; |
||
547 | } |
||
548 | |||
549 | guc_fw->guc_fw_obj = obj; |
||
550 | guc_fw->guc_fw_size = fw->size; |
||
551 | |||
552 | DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", |
||
553 | guc_fw->guc_fw_obj); |
||
554 | |||
555 | release_firmware(fw); |
||
556 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; |
||
557 | return; |
||
558 | |||
559 | fail: |
||
560 | DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", |
||
561 | err, fw, guc_fw->guc_fw_obj); |
||
562 | DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n", |
||
563 | guc_fw->guc_fw_path, err); |
||
564 | |||
7144 | serge | 565 | mutex_lock(&dev->struct_mutex); |
6084 | serge | 566 | obj = guc_fw->guc_fw_obj; |
567 | if (obj) |
||
568 | drm_gem_object_unreference(&obj->base); |
||
569 | guc_fw->guc_fw_obj = NULL; |
||
7144 | serge | 570 | mutex_unlock(&dev->struct_mutex); |
6084 | serge | 571 | |
572 | release_firmware(fw); /* OK even if fw is NULL */ |
||
573 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; |
||
574 | } |
||
575 | |||
576 | /** |
||
577 | * intel_guc_ucode_init() - define parameters and fetch firmware |
||
578 | * @dev: drm device |
||
579 | * |
||
580 | * Called early during driver load, but after GEM is initialised. |
||
581 | * |
||
582 | * The firmware will be transferred to the GuC's memory later, |
||
583 | * when intel_guc_ucode_load() is called. |
||
584 | */ |
||
585 | void intel_guc_ucode_init(struct drm_device *dev) |
||
586 | { |
||
587 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
588 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
||
589 | const char *fw_path; |
||
590 | |||
591 | if (!HAS_GUC_SCHED(dev)) |
||
592 | i915.enable_guc_submission = false; |
||
593 | |||
594 | if (!HAS_GUC_UCODE(dev)) { |
||
595 | fw_path = NULL; |
||
596 | } else if (IS_SKYLAKE(dev)) { |
||
597 | fw_path = I915_SKL_GUC_UCODE; |
||
598 | guc_fw->guc_fw_major_wanted = 4; |
||
599 | guc_fw->guc_fw_minor_wanted = 3; |
||
600 | } else { |
||
601 | i915.enable_guc_submission = false; |
||
602 | fw_path = ""; /* unknown device */ |
||
603 | } |
||
604 | |||
6937 | serge | 605 | if (!i915.enable_guc_submission) |
606 | return; |
||
607 | |||
6084 | serge | 608 | guc_fw->guc_dev = dev; |
609 | guc_fw->guc_fw_path = fw_path; |
||
610 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; |
||
611 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; |
||
612 | |||
613 | if (fw_path == NULL) |
||
614 | return; |
||
615 | |||
616 | if (*fw_path == '\0') { |
||
617 | DRM_ERROR("No GuC firmware known for this platform\n"); |
||
618 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; |
||
619 | return; |
||
620 | } |
||
621 | |||
622 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; |
||
623 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); |
||
624 | guc_fw_fetch(dev, guc_fw); |
||
625 | /* status must now be FAIL or SUCCESS */ |
||
626 | } |
||
627 | |||
628 | /** |
||
629 | * intel_guc_ucode_fini() - clean up all allocated resources |
||
630 | * @dev: drm device |
||
631 | */ |
||
632 | void intel_guc_ucode_fini(struct drm_device *dev) |
||
633 | { |
||
634 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
635 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
||
636 | |||
7144 | serge | 637 | mutex_lock(&dev->struct_mutex); |
6084 | serge | 638 | direct_interrupts_to_host(dev_priv); |
7144 | serge | 639 | i915_guc_submission_disable(dev); |
6084 | serge | 640 | i915_guc_submission_fini(dev); |
641 | |||
642 | if (guc_fw->guc_fw_obj) |
||
643 | drm_gem_object_unreference(&guc_fw->guc_fw_obj->base); |
||
644 | guc_fw->guc_fw_obj = NULL; |
||
645 | mutex_unlock(&dev->struct_mutex); |
||
646 | |||
647 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; |
||
648 | }>>>>>><>><>><>><>><>><>><>><> |