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6084 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | */ |
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23 | #ifndef _INTEL_GUC_FWIF_H |
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24 | #define _INTEL_GUC_FWIF_H |
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25 | |||
26 | /* |
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27 | * This file is partially autogenerated, although currently with some manual |
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28 | * fixups afterwards. In future, it should be entirely autogenerated, in order |
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29 | * to ensure that the definitions herein remain in sync with those used by the |
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30 | * GuC's own firmware. |
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31 | * |
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32 | * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. |
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33 | */ |
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34 | |||
35 | #define GFXCORE_FAMILY_GEN9 12 |
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36 | #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff |
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37 | |||
38 | #define GUC_CTX_PRIORITY_KMD_HIGH 0 |
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39 | #define GUC_CTX_PRIORITY_HIGH 1 |
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40 | #define GUC_CTX_PRIORITY_KMD_NORMAL 2 |
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41 | #define GUC_CTX_PRIORITY_NORMAL 3 |
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7144 | serge | 42 | #define GUC_CTX_PRIORITY_NUM 4 |
6084 | serge | 43 | |
44 | #define GUC_MAX_GPU_CONTEXTS 1024 |
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45 | #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS |
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46 | |||
7144 | serge | 47 | #define GUC_RENDER_ENGINE 0 |
48 | #define GUC_VIDEO_ENGINE 1 |
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49 | #define GUC_BLITTER_ENGINE 2 |
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50 | #define GUC_VIDEOENHANCE_ENGINE 3 |
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51 | #define GUC_VIDEO_ENGINE2 4 |
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52 | #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) |
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53 | |||
6084 | serge | 54 | /* Work queue item header definitions */ |
55 | #define WQ_STATUS_ACTIVE 1 |
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56 | #define WQ_STATUS_SUSPENDED 2 |
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57 | #define WQ_STATUS_CMD_ERROR 3 |
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58 | #define WQ_STATUS_ENGINE_ID_NOT_USED 4 |
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59 | #define WQ_STATUS_SUSPENDED_FROM_RESET 5 |
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60 | #define WQ_TYPE_SHIFT 0 |
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61 | #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) |
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62 | #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) |
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63 | #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) |
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64 | #define WQ_TARGET_SHIFT 10 |
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65 | #define WQ_LEN_SHIFT 16 |
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66 | #define WQ_NO_WCFLUSH_WAIT (1 << 27) |
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67 | #define WQ_PRESENT_WORKLOAD (1 << 28) |
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68 | #define WQ_WORKLOAD_SHIFT 29 |
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69 | #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) |
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70 | #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) |
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71 | #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) |
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72 | |||
73 | #define WQ_RING_TAIL_SHIFT 20 |
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74 | #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT) |
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75 | |||
76 | #define GUC_DOORBELL_ENABLED 1 |
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77 | #define GUC_DOORBELL_DISABLED 0 |
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78 | |||
79 | #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) |
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80 | #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) |
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81 | #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) |
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82 | #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) |
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83 | #define GUC_CTX_DESC_ATTR_RESET (1 << 4) |
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84 | #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) |
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85 | #define GUC_CTX_DESC_ATTR_PCH (1 << 6) |
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86 | #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7) |
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87 | |||
88 | /* The guc control data is 10 DWORDs */ |
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89 | #define GUC_CTL_CTXINFO 0 |
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90 | #define GUC_CTL_CTXNUM_IN16_SHIFT 0 |
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91 | #define GUC_CTL_BASE_ADDR_SHIFT 12 |
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7144 | serge | 92 | |
6084 | serge | 93 | #define GUC_CTL_ARAT_HIGH 1 |
94 | #define GUC_CTL_ARAT_LOW 2 |
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7144 | serge | 95 | |
6084 | serge | 96 | #define GUC_CTL_DEVICE_INFO 3 |
97 | #define GUC_CTL_GTTYPE_SHIFT 0 |
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98 | #define GUC_CTL_COREFAMILY_SHIFT 7 |
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7144 | serge | 99 | |
6084 | serge | 100 | #define GUC_CTL_LOG_PARAMS 4 |
101 | #define GUC_LOG_VALID (1 << 0) |
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102 | #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) |
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103 | #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) |
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104 | #define GUC_LOG_CRASH_PAGES 1 |
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105 | #define GUC_LOG_CRASH_SHIFT 4 |
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106 | #define GUC_LOG_DPC_PAGES 3 |
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107 | #define GUC_LOG_DPC_SHIFT 6 |
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108 | #define GUC_LOG_ISR_PAGES 3 |
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109 | #define GUC_LOG_ISR_SHIFT 9 |
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110 | #define GUC_LOG_BUF_ADDR_SHIFT 12 |
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7144 | serge | 111 | |
6084 | serge | 112 | #define GUC_CTL_PAGE_FAULT_CONTROL 5 |
7144 | serge | 113 | |
6084 | serge | 114 | #define GUC_CTL_WA 6 |
115 | #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) |
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7144 | serge | 116 | |
6084 | serge | 117 | #define GUC_CTL_FEATURE 7 |
118 | #define GUC_CTL_VCS2_ENABLED (1 << 0) |
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119 | #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) |
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120 | #define GUC_CTL_FEATURE2 (1 << 2) |
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121 | #define GUC_CTL_POWER_GATING (1 << 3) |
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122 | #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) |
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123 | #define GUC_CTL_PREEMPTION_LOG (1 << 5) |
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124 | #define GUC_CTL_ENABLE_SLPC (1 << 7) |
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125 | #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) |
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7144 | serge | 126 | |
6084 | serge | 127 | #define GUC_CTL_DEBUG 8 |
128 | #define GUC_LOG_VERBOSITY_SHIFT 0 |
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129 | #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) |
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130 | #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) |
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131 | #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) |
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132 | #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) |
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133 | /* Verbosity range-check limits, without the shift */ |
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134 | #define GUC_LOG_VERBOSITY_MIN 0 |
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135 | #define GUC_LOG_VERBOSITY_MAX 3 |
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7144 | serge | 136 | #define GUC_LOG_VERBOSITY_MASK 0x0000000f |
137 | #define GUC_LOG_DESTINATION_MASK (3 << 4) |
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138 | #define GUC_LOG_DISABLED (1 << 6) |
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139 | #define GUC_PROFILE_ENABLED (1 << 7) |
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140 | #define GUC_WQ_TRACK_ENABLED (1 << 8) |
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141 | #define GUC_ADS_ENABLED (1 << 9) |
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142 | #define GUC_DEBUG_RESERVED (1 << 10) |
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143 | #define GUC_ADS_ADDR_SHIFT 11 |
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144 | #define GUC_ADS_ADDR_MASK 0xfffff800 |
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145 | |||
6084 | serge | 146 | #define GUC_CTL_RSRVD 9 |
147 | |||
7144 | serge | 148 | #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ |
6084 | serge | 149 | |
6937 | serge | 150 | /** |
151 | * DOC: GuC Firmware Layout |
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152 | * |
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153 | * The GuC firmware layout looks like this: |
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154 | * |
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155 | * +-------------------------------+ |
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156 | * | guc_css_header | |
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157 | * | contains major/minor version | |
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158 | * +-------------------------------+ |
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159 | * | uCode | |
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160 | * +-------------------------------+ |
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161 | * | RSA signature | |
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162 | * +-------------------------------+ |
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163 | * | modulus key | |
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164 | * +-------------------------------+ |
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165 | * | exponent val | |
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166 | * +-------------------------------+ |
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167 | * |
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168 | * The firmware may or may not have modulus key and exponent data. The header, |
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169 | * uCode and RSA signature are must-have components that will be used by driver. |
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170 | * Length of each components, which is all in dwords, can be found in header. |
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171 | * In the case that modulus and exponent are not present in fw, a.k.a truncated |
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172 | * image, the length value still appears in header. |
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173 | * |
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174 | * Driver will do some basic fw size validation based on the following rules: |
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175 | * |
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176 | * 1. Header, uCode and RSA are must-have components. |
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177 | * 2. All firmware components, if they present, are in the sequence illustrated |
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178 | * in the layout table above. |
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179 | * 3. Length info of each component can be found in header, in dwords. |
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180 | * 4. Modulus and exponent key are not required by driver. They may not appear |
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181 | * in fw. So driver will load a truncated firmware in this case. |
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182 | */ |
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183 | |||
184 | struct guc_css_header { |
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185 | uint32_t module_type; |
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186 | /* header_size includes all non-uCode bits, including css_header, rsa |
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187 | * key, modulus key and exponent data. */ |
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188 | uint32_t header_size_dw; |
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189 | uint32_t header_version; |
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190 | uint32_t module_id; |
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191 | uint32_t module_vendor; |
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192 | union { |
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193 | struct { |
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194 | uint8_t day; |
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195 | uint8_t month; |
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196 | uint16_t year; |
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197 | }; |
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198 | uint32_t date; |
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199 | }; |
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200 | uint32_t size_dw; /* uCode plus header_size_dw */ |
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201 | uint32_t key_size_dw; |
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202 | uint32_t modulus_size_dw; |
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203 | uint32_t exponent_size_dw; |
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204 | union { |
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205 | struct { |
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206 | uint8_t hour; |
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207 | uint8_t min; |
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208 | uint16_t sec; |
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209 | }; |
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210 | uint32_t time; |
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211 | }; |
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212 | |||
213 | char username[8]; |
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214 | char buildnumber[12]; |
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215 | uint32_t device_id; |
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216 | uint32_t guc_sw_version; |
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217 | uint32_t prod_preprod_fw; |
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218 | uint32_t reserved[12]; |
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219 | uint32_t header_info; |
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220 | } __packed; |
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221 | |||
6084 | serge | 222 | struct guc_doorbell_info { |
223 | u32 db_status; |
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224 | u32 cookie; |
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225 | u32 reserved[14]; |
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226 | } __packed; |
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227 | |||
228 | union guc_doorbell_qw { |
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229 | struct { |
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230 | u32 db_status; |
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231 | u32 cookie; |
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232 | }; |
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233 | u64 value_qw; |
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234 | } __packed; |
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235 | |||
236 | #define GUC_MAX_DOORBELLS 256 |
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237 | #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) |
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238 | |||
239 | #define GUC_DB_SIZE (PAGE_SIZE) |
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240 | #define GUC_WQ_SIZE (PAGE_SIZE * 2) |
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241 | |||
242 | /* Work item for submitting workloads into work queue of GuC. */ |
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243 | struct guc_wq_item { |
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244 | u32 header; |
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245 | u32 context_desc; |
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246 | u32 ring_tail; |
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247 | u32 fence_id; |
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248 | } __packed; |
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249 | |||
250 | struct guc_process_desc { |
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251 | u32 context_id; |
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252 | u64 db_base_addr; |
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253 | u32 head; |
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254 | u32 tail; |
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255 | u32 error_offset; |
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256 | u64 wq_base_addr; |
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257 | u32 wq_size_bytes; |
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258 | u32 wq_status; |
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259 | u32 engine_presence; |
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260 | u32 priority; |
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261 | u32 reserved[30]; |
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262 | } __packed; |
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263 | |||
264 | /* engine id and context id is packed into guc_execlist_context.context_id*/ |
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265 | #define GUC_ELC_CTXID_OFFSET 0 |
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266 | #define GUC_ELC_ENGINE_OFFSET 29 |
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267 | |||
268 | /* The execlist context including software and HW information */ |
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269 | struct guc_execlist_context { |
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270 | u32 context_desc; |
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271 | u32 context_id; |
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272 | u32 ring_status; |
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273 | u32 ring_lcra; |
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274 | u32 ring_begin; |
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275 | u32 ring_end; |
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276 | u32 ring_next_free_location; |
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277 | u32 ring_current_tail_pointer_value; |
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278 | u8 engine_state_submit_value; |
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279 | u8 engine_state_wait_value; |
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280 | u16 pagefault_count; |
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281 | u16 engine_submit_queue_count; |
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282 | } __packed; |
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283 | |||
284 | /*Context descriptor for communicating between uKernel and Driver*/ |
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285 | struct guc_context_desc { |
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286 | u32 sched_common_area; |
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287 | u32 context_id; |
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288 | u32 pas_id; |
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289 | u8 engines_used; |
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290 | u64 db_trigger_cpu; |
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291 | u32 db_trigger_uk; |
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292 | u64 db_trigger_phy; |
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293 | u16 db_id; |
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294 | |||
7144 | serge | 295 | struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; |
6084 | serge | 296 | |
297 | u8 attribute; |
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298 | |||
299 | u32 priority; |
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300 | |||
301 | u32 wq_sampled_tail_offset; |
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302 | u32 wq_total_submit_enqueues; |
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303 | |||
304 | u32 process_desc; |
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305 | u32 wq_addr; |
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306 | u32 wq_size; |
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307 | |||
308 | u32 engine_presence; |
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309 | |||
310 | u8 engine_suspended; |
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311 | |||
312 | u8 reserved0[3]; |
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313 | u64 reserved1[1]; |
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314 | |||
315 | u64 desc_private; |
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316 | } __packed; |
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317 | |||
318 | #define GUC_FORCEWAKE_RENDER (1 << 0) |
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319 | #define GUC_FORCEWAKE_MEDIA (1 << 1) |
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320 | |||
321 | #define GUC_POWER_UNSPECIFIED 0 |
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322 | #define GUC_POWER_D0 1 |
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323 | #define GUC_POWER_D1 2 |
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324 | #define GUC_POWER_D2 3 |
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325 | #define GUC_POWER_D3 4 |
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326 | |||
7144 | serge | 327 | /* Scheduling policy settings */ |
328 | |||
329 | /* Reset engine upon preempt failure */ |
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330 | #define POLICY_RESET_ENGINE (1<<0) |
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331 | /* Preempt to idle on quantum expiry */ |
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332 | #define POLICY_PREEMPT_TO_IDLE (1<<1) |
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333 | |||
334 | #define POLICY_MAX_NUM_WI 15 |
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335 | |||
336 | struct guc_policy { |
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337 | /* Time for one workload to execute. (in micro seconds) */ |
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338 | u32 execution_quantum; |
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339 | u32 reserved1; |
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340 | |||
341 | /* Time to wait for a preemption request to completed before issuing a |
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342 | * reset. (in micro seconds). */ |
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343 | u32 preemption_time; |
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344 | |||
345 | /* How much time to allow to run after the first fault is observed. |
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346 | * Then preempt afterwards. (in micro seconds) */ |
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347 | u32 fault_time; |
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348 | |||
349 | u32 policy_flags; |
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350 | u32 reserved[2]; |
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351 | } __packed; |
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352 | |||
353 | struct guc_policies { |
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354 | struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; |
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355 | |||
356 | /* In micro seconds. How much time to allow before DPC processing is |
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357 | * called back via interrupt (to prevent DPC queue drain starving). |
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358 | * Typically 1000s of micro seconds (example only, not granularity). */ |
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359 | u32 dpc_promote_time; |
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360 | |||
361 | /* Must be set to take these new values. */ |
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362 | u32 is_valid; |
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363 | |||
364 | /* Max number of WIs to process per call. A large value may keep CS |
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365 | * idle. */ |
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366 | u32 max_num_work_items; |
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367 | |||
368 | u32 reserved[19]; |
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369 | } __packed; |
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370 | |||
371 | /* GuC MMIO reg state struct */ |
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372 | |||
373 | #define GUC_REGSET_FLAGS_NONE 0x0 |
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374 | #define GUC_REGSET_POWERCYCLE 0x1 |
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375 | #define GUC_REGSET_MASKED 0x2 |
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376 | #define GUC_REGSET_ENGINERESET 0x4 |
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377 | #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 |
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378 | #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 |
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379 | |||
380 | #define GUC_REGSET_MAX_REGISTERS 25 |
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381 | #define GUC_MMIO_WHITE_LIST_START 0x24d0 |
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382 | #define GUC_MMIO_WHITE_LIST_MAX 12 |
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383 | #define GUC_S3_SAVE_SPACE_PAGES 10 |
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384 | |||
385 | struct guc_mmio_regset { |
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386 | struct __packed { |
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387 | u32 offset; |
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388 | u32 value; |
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389 | u32 flags; |
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390 | } registers[GUC_REGSET_MAX_REGISTERS]; |
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391 | |||
392 | u32 values_valid; |
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393 | u32 number_of_registers; |
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394 | } __packed; |
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395 | |||
396 | struct guc_mmio_reg_state { |
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397 | struct guc_mmio_regset global_reg; |
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398 | struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; |
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399 | |||
400 | /* MMIO registers that are set as non privileged */ |
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401 | struct __packed { |
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402 | u32 mmio_start; |
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403 | u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; |
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404 | u32 count; |
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405 | } mmio_white_list[GUC_MAX_ENGINES_NUM]; |
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406 | } __packed; |
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407 | |||
408 | /* GuC Additional Data Struct */ |
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409 | |||
410 | struct guc_ads { |
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411 | u32 reg_state_addr; |
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412 | u32 reg_state_buffer; |
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413 | u32 golden_context_lrca; |
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414 | u32 scheduler_policies; |
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415 | u32 reserved0[3]; |
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416 | u32 eng_state_size[GUC_MAX_ENGINES_NUM]; |
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417 | u32 reserved2[4]; |
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418 | } __packed; |
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419 | |||
6084 | serge | 420 | /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ |
421 | enum host2guc_action { |
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422 | HOST2GUC_ACTION_DEFAULT = 0x0, |
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423 | HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, |
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424 | HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, |
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425 | HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, |
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426 | HOST2GUC_ACTION_ENTER_S_STATE = 0x501, |
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427 | HOST2GUC_ACTION_EXIT_S_STATE = 0x502, |
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428 | HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, |
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429 | HOST2GUC_ACTION_LIMIT |
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430 | }; |
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431 | |||
432 | /* |
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433 | * The GuC sends its response to a command by overwriting the |
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434 | * command in SS0. The response is distinguishable from a command |
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435 | * by the fact that all the MASK bits are set. The remaining bits |
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436 | * give more detail. |
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437 | */ |
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438 | #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) |
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439 | #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) |
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440 | #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) |
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441 | |||
442 | /* GUC will return status back to SOFT_SCRATCH_O_REG */ |
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443 | enum guc2host_status { |
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444 | GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), |
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445 | GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), |
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446 | GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), |
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447 | GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) |
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448 | }; |
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449 | |||
450 | #endif1) |