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5354 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Daniel Vetter |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "i915_drv.h" |
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29 | #include "intel_drv.h" |
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30 | |||
31 | /** |
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32 | * DOC: fifo underrun handling |
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33 | * |
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34 | * The i915 driver checks for display fifo underruns using the interrupt signals |
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35 | * provided by the hardware. This is enabled by default and fairly useful to |
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36 | * debug display issues, especially watermark settings. |
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37 | * |
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38 | * If an underrun is detected this is logged into dmesg. To avoid flooding logs |
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39 | * and occupying the cpu underrun interrupts are disabled after the first |
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40 | * occurrence until the next modeset on a given pipe. |
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41 | * |
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42 | * Note that underrun detection on gmch platforms is a bit more ugly since there |
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43 | * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe |
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44 | * interrupt register). Also on some other platforms underrun interrupts are |
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45 | * shared, which means that if we detect an underrun we need to disable underrun |
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46 | * reporting on all pipes. |
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47 | * |
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48 | * The code also supports underrun detection on the PCH transcoder. |
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49 | */ |
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50 | |||
51 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
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52 | { |
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53 | struct drm_i915_private *dev_priv = dev->dev_private; |
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54 | struct intel_crtc *crtc; |
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55 | enum pipe pipe; |
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56 | |||
57 | assert_spin_locked(&dev_priv->irq_lock); |
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58 | |||
59 | for_each_pipe(dev_priv, pipe) { |
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60 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
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61 | |||
62 | if (crtc->cpu_fifo_underrun_disabled) |
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63 | return false; |
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64 | } |
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65 | |||
66 | return true; |
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67 | } |
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68 | |||
69 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
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70 | { |
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71 | struct drm_i915_private *dev_priv = dev->dev_private; |
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72 | enum pipe pipe; |
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73 | struct intel_crtc *crtc; |
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74 | |||
75 | assert_spin_locked(&dev_priv->irq_lock); |
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76 | |||
77 | for_each_pipe(dev_priv, pipe) { |
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78 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
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79 | |||
80 | if (crtc->pch_fifo_underrun_disabled) |
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81 | return false; |
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82 | } |
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83 | |||
84 | return true; |
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85 | } |
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86 | |||
6937 | serge | 87 | static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) |
5354 | serge | 88 | { |
6937 | serge | 89 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
90 | i915_reg_t reg = PIPESTAT(crtc->pipe); |
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91 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
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5354 | serge | 92 | |
6937 | serge | 93 | assert_spin_locked(&dev_priv->irq_lock); |
5354 | serge | 94 | |
7144 | serge | 95 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) |
6937 | serge | 96 | return; |
5354 | serge | 97 | |
7144 | serge | 98 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
99 | POSTING_READ(reg); |
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5354 | serge | 100 | |
7144 | serge | 101 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); |
102 | } |
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5354 | serge | 103 | |
104 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
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105 | enum pipe pipe, |
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106 | bool enable, bool old) |
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107 | { |
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108 | struct drm_i915_private *dev_priv = dev->dev_private; |
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6937 | serge | 109 | i915_reg_t reg = PIPESTAT(pipe); |
5354 | serge | 110 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
111 | |||
112 | assert_spin_locked(&dev_priv->irq_lock); |
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113 | |||
114 | if (enable) { |
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115 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
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116 | POSTING_READ(reg); |
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117 | } else { |
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118 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) |
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119 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
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120 | } |
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121 | } |
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122 | |||
123 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
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124 | enum pipe pipe, bool enable) |
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125 | { |
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126 | struct drm_i915_private *dev_priv = dev->dev_private; |
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127 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
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128 | DE_PIPEB_FIFO_UNDERRUN; |
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129 | |||
130 | if (enable) |
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6937 | serge | 131 | ilk_enable_display_irq(dev_priv, bit); |
5354 | serge | 132 | else |
6937 | serge | 133 | ilk_disable_display_irq(dev_priv, bit); |
5354 | serge | 134 | } |
135 | |||
6937 | serge | 136 | static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) |
137 | { |
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138 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
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139 | enum pipe pipe = crtc->pipe; |
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140 | uint32_t err_int = I915_READ(GEN7_ERR_INT); |
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141 | |||
142 | assert_spin_locked(&dev_priv->irq_lock); |
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143 | |||
144 | if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) |
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145 | return; |
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146 | |||
147 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
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148 | POSTING_READ(GEN7_ERR_INT); |
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149 | |||
150 | DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); |
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151 | } |
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152 | |||
5354 | serge | 153 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
154 | enum pipe pipe, |
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155 | bool enable, bool old) |
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156 | { |
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157 | struct drm_i915_private *dev_priv = dev->dev_private; |
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158 | if (enable) { |
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159 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
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160 | |||
161 | if (!ivb_can_enable_err_int(dev)) |
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162 | return; |
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163 | |||
6937 | serge | 164 | ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
5354 | serge | 165 | } else { |
6937 | serge | 166 | ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
5354 | serge | 167 | |
168 | if (old && |
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169 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { |
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170 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
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171 | pipe_name(pipe)); |
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172 | } |
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173 | } |
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174 | } |
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175 | |||
176 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
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177 | enum pipe pipe, bool enable) |
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178 | { |
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179 | struct drm_i915_private *dev_priv = dev->dev_private; |
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180 | |||
181 | if (enable) |
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6937 | serge | 182 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); |
5354 | serge | 183 | else |
6937 | serge | 184 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); |
5354 | serge | 185 | } |
186 | |||
187 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
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188 | enum transcoder pch_transcoder, |
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189 | bool enable) |
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190 | { |
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191 | struct drm_i915_private *dev_priv = dev->dev_private; |
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192 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
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193 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
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194 | |||
195 | if (enable) |
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196 | ibx_enable_display_interrupt(dev_priv, bit); |
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197 | else |
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198 | ibx_disable_display_interrupt(dev_priv, bit); |
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199 | } |
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200 | |||
6937 | serge | 201 | static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) |
202 | { |
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203 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
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204 | enum transcoder pch_transcoder = (enum transcoder) crtc->pipe; |
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205 | uint32_t serr_int = I915_READ(SERR_INT); |
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206 | |||
207 | assert_spin_locked(&dev_priv->irq_lock); |
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208 | |||
209 | if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) |
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210 | return; |
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211 | |||
212 | I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
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213 | POSTING_READ(SERR_INT); |
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214 | |||
215 | DRM_ERROR("pch fifo underrun on pch transcoder %c\n", |
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216 | transcoder_name(pch_transcoder)); |
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217 | } |
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218 | |||
5354 | serge | 219 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
220 | enum transcoder pch_transcoder, |
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221 | bool enable, bool old) |
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222 | { |
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223 | struct drm_i915_private *dev_priv = dev->dev_private; |
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224 | |||
225 | if (enable) { |
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226 | I915_WRITE(SERR_INT, |
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227 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
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228 | |||
229 | if (!cpt_can_enable_serr_int(dev)) |
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230 | return; |
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231 | |||
232 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
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233 | } else { |
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234 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
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235 | |||
236 | if (old && I915_READ(SERR_INT) & |
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237 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { |
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238 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
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239 | transcoder_name(pch_transcoder)); |
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240 | } |
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241 | } |
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242 | } |
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243 | |||
244 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
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245 | enum pipe pipe, bool enable) |
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246 | { |
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247 | struct drm_i915_private *dev_priv = dev->dev_private; |
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248 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
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249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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250 | bool old; |
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251 | |||
252 | assert_spin_locked(&dev_priv->irq_lock); |
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253 | |||
254 | old = !intel_crtc->cpu_fifo_underrun_disabled; |
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255 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
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256 | |||
257 | if (HAS_GMCH_DISPLAY(dev)) |
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258 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
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259 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
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260 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
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261 | else if (IS_GEN7(dev)) |
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262 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
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263 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
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264 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
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265 | |||
266 | return old; |
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267 | } |
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268 | |||
269 | /** |
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270 | * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state |
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271 | * @dev_priv: i915 device instance |
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272 | * @pipe: (CPU) pipe to set state for |
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273 | * @enable: whether underruns should be reported or not |
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274 | * |
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275 | * This function sets the fifo underrun state for @pipe. It is used in the |
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276 | * modeset code to avoid false positives since on many platforms underruns are |
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277 | * expected when disabling or enabling the pipe. |
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278 | * |
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279 | * Notice that on some platforms disabling underrun reports for one pipe |
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280 | * disables for all due to shared interrupts. Actual reporting is still per-pipe |
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281 | * though. |
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282 | * |
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283 | * Returns the previous state of underrun reporting. |
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284 | */ |
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285 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
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286 | enum pipe pipe, bool enable) |
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287 | { |
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288 | unsigned long flags; |
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289 | bool ret; |
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290 | |||
291 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
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292 | ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe, |
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293 | enable); |
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294 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
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295 | |||
296 | return ret; |
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297 | } |
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298 | |||
299 | /** |
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300 | * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state |
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301 | * @dev_priv: i915 device instance |
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302 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
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303 | * @enable: whether underruns should be reported or not |
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304 | * |
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305 | * This function makes us disable or enable PCH fifo underruns for a specific |
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306 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
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307 | * underrun reporting for one transcoder may also disable all the other PCH |
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308 | * error interruts for the other transcoders, due to the fact that there's just |
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309 | * one interrupt mask/enable bit for all the transcoders. |
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310 | * |
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311 | * Returns the previous state of underrun reporting. |
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312 | */ |
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313 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
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314 | enum transcoder pch_transcoder, |
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315 | bool enable) |
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316 | { |
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317 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
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318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
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319 | unsigned long flags; |
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320 | bool old; |
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321 | |||
322 | /* |
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323 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
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324 | * has only one pch transcoder A that all pipes can use. To avoid racy |
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325 | * pch transcoder -> pipe lookups from interrupt code simply store the |
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326 | * underrun statistics in crtc A. Since we never expose this anywhere |
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327 | * nor use it outside of the fifo underrun code here using the "wrong" |
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328 | * crtc on LPT won't cause issues. |
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329 | */ |
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330 | |||
331 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
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332 | |||
333 | old = !intel_crtc->pch_fifo_underrun_disabled; |
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334 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
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335 | |||
336 | if (HAS_PCH_IBX(dev_priv->dev)) |
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337 | ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, |
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338 | enable); |
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339 | else |
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340 | cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, |
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341 | enable, old); |
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342 | |||
343 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
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344 | return old; |
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345 | } |
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346 | |||
347 | /** |
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6084 | serge | 348 | * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt |
5354 | serge | 349 | * @dev_priv: i915 device instance |
350 | * @pipe: (CPU) pipe to set state for |
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351 | * |
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352 | * This handles a CPU fifo underrun interrupt, generating an underrun warning |
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353 | * into dmesg if underrun reporting is enabled and then disables the underrun |
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354 | * interrupt to avoid an irq storm. |
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355 | */ |
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356 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
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357 | enum pipe pipe) |
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358 | { |
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6084 | serge | 359 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
360 | |||
361 | /* We may be called too early in init, thanks BIOS! */ |
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362 | if (crtc == NULL) |
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363 | return; |
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364 | |||
5354 | serge | 365 | /* GMCH can't disable fifo underruns, filter them. */ |
366 | if (HAS_GMCH_DISPLAY(dev_priv->dev) && |
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6084 | serge | 367 | to_intel_crtc(crtc)->cpu_fifo_underrun_disabled) |
5354 | serge | 368 | return; |
369 | |||
370 | if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) |
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371 | DRM_ERROR("CPU pipe %c FIFO underrun\n", |
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372 | pipe_name(pipe)); |
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373 | } |
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374 | |||
375 | /** |
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376 | * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt |
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377 | * @dev_priv: i915 device instance |
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378 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
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379 | * |
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380 | * This handles a PCH fifo underrun interrupt, generating an underrun warning |
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381 | * into dmesg if underrun reporting is enabled and then disables the underrun |
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382 | * interrupt to avoid an irq storm. |
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383 | */ |
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384 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
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385 | enum transcoder pch_transcoder) |
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386 | { |
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387 | if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, |
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388 | false)) |
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389 | DRM_ERROR("PCH transcoder %c FIFO underrun\n", |
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390 | transcoder_name(pch_transcoder)); |
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391 | } |
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6937 | serge | 392 | |
393 | /** |
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394 | * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately |
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395 | * @dev_priv: i915 device instance |
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396 | * |
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397 | * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared |
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398 | * error interrupt may have been disabled, and so CPU fifo underruns won't |
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399 | * necessarily raise an interrupt, and on GMCH platforms where underruns never |
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400 | * raise an interrupt. |
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401 | */ |
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402 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) |
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403 | { |
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404 | struct intel_crtc *crtc; |
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405 | |||
406 | spin_lock_irq(&dev_priv->irq_lock); |
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407 | |||
408 | for_each_intel_crtc(dev_priv->dev, crtc) { |
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409 | if (crtc->cpu_fifo_underrun_disabled) |
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410 | continue; |
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411 | |||
412 | if (HAS_GMCH_DISPLAY(dev_priv)) |
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413 | i9xx_check_fifo_underruns(crtc); |
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414 | else if (IS_GEN7(dev_priv)) |
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415 | ivybridge_check_fifo_underruns(crtc); |
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416 | } |
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417 | |||
418 | spin_unlock_irq(&dev_priv->irq_lock); |
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419 | } |
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420 | |||
421 | /** |
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422 | * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately |
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423 | * @dev_priv: i915 device instance |
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424 | * |
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425 | * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared |
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426 | * error interrupt may have been disabled, and so PCH fifo underruns won't |
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427 | * necessarily raise an interrupt. |
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428 | */ |
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429 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) |
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430 | { |
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431 | struct intel_crtc *crtc; |
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432 | |||
433 | spin_lock_irq(&dev_priv->irq_lock); |
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434 | |||
435 | for_each_intel_crtc(dev_priv->dev, crtc) { |
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436 | if (crtc->pch_fifo_underrun_disabled) |
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437 | continue; |
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438 | |||
439 | if (HAS_PCH_CPT(dev_priv)) |
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440 | cpt_check_pch_fifo_underruns(crtc); |
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441 | } |
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442 | |||
443 | spin_unlock_irq(&dev_priv->irq_lock); |
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444 | } |