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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Shobhit Kumar |
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25 | * Yogesh Mohan Marimuthu |
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26 | */ |
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27 | |||
28 | #include |
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29 | #include "intel_drv.h" |
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30 | #include "i915_drv.h" |
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31 | #include "intel_dsi.h" |
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32 | |||
33 | #define DSI_HSS_PACKET_SIZE 4 |
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34 | #define DSI_HSE_PACKET_SIZE 4 |
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35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 |
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36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 |
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37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 |
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38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 |
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39 | #define DSI_EOTP_PACKET_SIZE 4 |
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40 | |||
41 | struct dsi_mnp { |
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42 | u32 dsi_pll_ctrl; |
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43 | u32 dsi_pll_div; |
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44 | }; |
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45 | |||
46 | static const u32 lfsr_converts[] = { |
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47 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
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48 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
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49 | 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ |
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50 | 71, 35 /* 91 - 92 */ |
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51 | }; |
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52 | |||
53 | #ifdef DSI_CLK_FROM_RR |
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54 | |||
55 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
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56 | int pixel_format, int video_mode_format, |
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57 | int lane_count, bool eotp) |
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58 | { |
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59 | u32 bpp; |
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60 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; |
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61 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; |
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62 | u32 bytes_per_line, bytes_per_frame; |
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63 | u32 num_frames; |
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64 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; |
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65 | u32 dsi_bit_clock_hz; |
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66 | u32 dsi_clk; |
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67 | |||
68 | switch (pixel_format) { |
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69 | default: |
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70 | case VID_MODE_FORMAT_RGB888: |
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71 | case VID_MODE_FORMAT_RGB666_LOOSE: |
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72 | bpp = 24; |
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73 | break; |
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74 | case VID_MODE_FORMAT_RGB666: |
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75 | bpp = 18; |
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76 | break; |
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77 | case VID_MODE_FORMAT_RGB565: |
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78 | bpp = 16; |
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79 | break; |
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80 | } |
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81 | |||
82 | hactive = mode->hdisplay; |
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83 | vactive = mode->vdisplay; |
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84 | hfp = mode->hsync_start - mode->hdisplay; |
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85 | hsync = mode->hsync_end - mode->hsync_start; |
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86 | hbp = mode->htotal - mode->hsync_end; |
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87 | |||
88 | vfp = mode->vsync_start - mode->vdisplay; |
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89 | vsync = mode->vsync_end - mode->vsync_start; |
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90 | vbp = mode->vtotal - mode->vsync_end; |
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91 | |||
92 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); |
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93 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); |
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94 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); |
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95 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); |
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96 | |||
97 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + |
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98 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + |
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99 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + |
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100 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + |
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101 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; |
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102 | |||
103 | /* |
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104 | * XXX: Need to accurately calculate LP to HS transition timeout and add |
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105 | * it to bytes_per_line/bytes_per_frame. |
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106 | */ |
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107 | |||
108 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
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109 | bytes_per_line += DSI_EOTP_PACKET_SIZE; |
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110 | |||
111 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + |
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112 | vactive * bytes_per_line + vfp * bytes_per_line; |
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113 | |||
114 | if (eotp && |
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115 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || |
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116 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) |
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117 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; |
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118 | |||
119 | num_frames = drm_mode_vrefresh(mode); |
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120 | bytes_per_x_frames = num_frames * bytes_per_frame; |
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121 | |||
122 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; |
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123 | |||
124 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ |
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125 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; |
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126 | dsi_clk = dsi_bit_clock_hz / 1000; |
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127 | |||
128 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
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129 | dsi_clk *= 2; |
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130 | |||
131 | return dsi_clk; |
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132 | } |
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133 | |||
134 | #else |
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135 | |||
136 | /* Get DSI clock from pixel clock */ |
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137 | static u32 dsi_clk_from_pclk(const struct drm_display_mode *mode, |
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138 | int pixel_format, int lane_count) |
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139 | { |
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140 | u32 dsi_clk_khz; |
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141 | u32 bpp; |
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142 | |||
143 | switch (pixel_format) { |
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144 | default: |
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145 | case VID_MODE_FORMAT_RGB888: |
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146 | case VID_MODE_FORMAT_RGB666_LOOSE: |
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147 | bpp = 24; |
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148 | break; |
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149 | case VID_MODE_FORMAT_RGB666: |
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150 | bpp = 18; |
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151 | break; |
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152 | case VID_MODE_FORMAT_RGB565: |
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153 | bpp = 16; |
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154 | break; |
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155 | } |
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156 | |||
157 | /* DSI data rate = pixel clock * bits per pixel / lane count |
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158 | pixel clock is converted from KHz to Hz */ |
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159 | dsi_clk_khz = DIV_ROUND_CLOSEST(mode->clock * bpp, lane_count); |
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160 | |||
161 | return dsi_clk_khz; |
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162 | } |
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163 | |||
164 | #endif |
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165 | |||
166 | static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) |
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167 | { |
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168 | u32 m, n, p; |
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169 | u32 ref_clk; |
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170 | u32 error; |
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171 | u32 tmp_error; |
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172 | int target_dsi_clk; |
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173 | int calc_dsi_clk; |
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174 | u32 calc_m; |
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175 | u32 calc_p; |
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176 | u32 m_seed; |
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177 | |||
178 | /* dsi_clk is expected in KHZ */ |
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179 | if (dsi_clk < 300000 || dsi_clk > 1150000) { |
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180 | DRM_ERROR("DSI CLK Out of Range\n"); |
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181 | return -ECHRNG; |
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182 | } |
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183 | |||
184 | ref_clk = 25000; |
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185 | target_dsi_clk = dsi_clk; |
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186 | error = 0xFFFFFFFF; |
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187 | tmp_error = 0xFFFFFFFF; |
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188 | calc_m = 0; |
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189 | calc_p = 0; |
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190 | |||
191 | for (m = 62; m <= 92; m++) { |
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192 | for (p = 2; p <= 6; p++) { |
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193 | /* Find the optimal m and p divisors |
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194 | with minimal error +/- the required clock */ |
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195 | calc_dsi_clk = (m * ref_clk) / p; |
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196 | if (calc_dsi_clk == target_dsi_clk) { |
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197 | calc_m = m; |
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198 | calc_p = p; |
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199 | error = 0; |
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200 | break; |
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201 | } else |
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202 | tmp_error = abs(target_dsi_clk - calc_dsi_clk); |
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203 | |||
204 | if (tmp_error < error) { |
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205 | error = tmp_error; |
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206 | calc_m = m; |
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207 | calc_p = p; |
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208 | } |
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209 | } |
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210 | |||
211 | if (error == 0) |
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212 | break; |
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213 | } |
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214 | |||
215 | m_seed = lfsr_converts[calc_m - 62]; |
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216 | n = 1; |
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217 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
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218 | dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | |
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219 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
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220 | |||
221 | return 0; |
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222 | } |
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223 | |||
224 | /* |
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225 | * XXX: The muxing and gating is hard coded for now. Need to add support for |
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226 | * sharing PLLs with two DSI outputs. |
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227 | */ |
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228 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) |
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229 | { |
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230 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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231 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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232 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
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233 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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234 | int ret; |
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235 | struct dsi_mnp dsi_mnp; |
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236 | u32 dsi_clk; |
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237 | |||
238 | dsi_clk = dsi_clk_from_pclk(mode, intel_dsi->pixel_format, |
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239 | intel_dsi->lane_count); |
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240 | |||
241 | ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); |
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242 | if (ret) { |
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243 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); |
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244 | return; |
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245 | } |
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246 | |||
247 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; |
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248 | |||
249 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
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250 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); |
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251 | |||
252 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); |
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253 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); |
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254 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); |
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255 | } |
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256 | |||
257 | void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
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258 | { |
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259 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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260 | u32 tmp; |
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261 | |||
262 | DRM_DEBUG_KMS("\n"); |
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263 | |||
264 | mutex_lock(&dev_priv->dpio_lock); |
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265 | |||
266 | vlv_configure_dsi_pll(encoder); |
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267 | |||
268 | /* wait at least 0.5 us after ungating before enabling VCO */ |
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269 | usleep_range(1, 10); |
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270 | |||
271 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |