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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Author: Jani Nikula |
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24 | */ |
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25 | |||
26 | #include |
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27 | #include |
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28 | #include |
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5060 | serge | 29 | #include |
4560 | Serge | 30 | #include "i915_drv.h" |
31 | #include "intel_drv.h" |
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32 | #include "intel_dsi.h" |
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33 | #include "intel_dsi_cmd.h" |
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34 | |||
35 | /* |
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36 | * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and |
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37 | * MIPI_COMMAND_ADDRESS registers. |
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38 | * |
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39 | * Apparently these registers provide a MIPI adapter level way to send (lots of) |
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40 | * commands and data to the receiver, without having to write the commands and |
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41 | * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word. |
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42 | * |
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43 | * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and |
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44 | * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external |
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45 | * framebuffer in command mode displays) these are just an optimization that can |
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46 | * come later. |
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47 | * |
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48 | * For memory writes, these should probably be used for performance. |
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49 | */ |
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50 | |||
51 | static void print_stat(struct intel_dsi *intel_dsi) |
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52 | { |
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53 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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54 | struct drm_device *dev = encoder->dev; |
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55 | struct drm_i915_private *dev_priv = dev->dev_private; |
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56 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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57 | enum pipe pipe = intel_crtc->pipe; |
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58 | u32 val; |
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59 | |||
60 | val = I915_READ(MIPI_INTR_STAT(pipe)); |
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61 | |||
62 | #define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : "" |
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63 | DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x" |
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64 | "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" |
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65 | "\n", pipe, val, |
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66 | STAT_BIT(val, TEARING_EFFECT), |
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67 | STAT_BIT(val, SPL_PKT_SENT_INTERRUPT), |
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68 | STAT_BIT(val, GEN_READ_DATA_AVAIL), |
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69 | STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL), |
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70 | STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL), |
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71 | STAT_BIT(val, RX_PROT_VIOLATION), |
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72 | STAT_BIT(val, RX_INVALID_TX_LENGTH), |
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73 | STAT_BIT(val, ACK_WITH_NO_ERROR), |
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74 | STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT), |
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75 | STAT_BIT(val, LP_RX_TIMEOUT), |
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76 | STAT_BIT(val, HS_TX_TIMEOUT), |
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77 | STAT_BIT(val, DPI_FIFO_UNDERRUN), |
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78 | STAT_BIT(val, LOW_CONTENTION), |
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79 | STAT_BIT(val, HIGH_CONTENTION), |
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80 | STAT_BIT(val, TXDSI_VC_ID_INVALID), |
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81 | STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED), |
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82 | STAT_BIT(val, TXCHECKSUM_ERROR), |
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83 | STAT_BIT(val, TXECC_MULTIBIT_ERROR), |
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84 | STAT_BIT(val, TXECC_SINGLE_BIT_ERROR), |
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85 | STAT_BIT(val, TXFALSE_CONTROL_ERROR), |
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86 | STAT_BIT(val, RXDSI_VC_ID_INVALID), |
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87 | STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED), |
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88 | STAT_BIT(val, RXCHECKSUM_ERROR), |
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89 | STAT_BIT(val, RXECC_MULTIBIT_ERROR), |
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90 | STAT_BIT(val, RXECC_SINGLE_BIT_ERROR), |
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91 | STAT_BIT(val, RXFALSE_CONTROL_ERROR), |
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92 | STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR), |
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93 | STAT_BIT(val, RX_LP_TX_SYNC_ERROR), |
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94 | STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR), |
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95 | STAT_BIT(val, RXEOT_SYNC_ERROR), |
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96 | STAT_BIT(val, RXSOT_SYNC_ERROR), |
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97 | STAT_BIT(val, RXSOT_ERROR)); |
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98 | #undef STAT_BIT |
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99 | } |
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100 | |||
101 | enum dsi_type { |
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102 | DSI_DCS, |
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103 | DSI_GENERIC, |
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104 | }; |
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105 | |||
106 | /* enable or disable command mode hs transmissions */ |
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107 | void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable) |
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108 | { |
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109 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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110 | struct drm_device *dev = encoder->dev; |
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111 | struct drm_i915_private *dev_priv = dev->dev_private; |
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112 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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113 | enum pipe pipe = intel_crtc->pipe; |
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114 | u32 temp; |
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115 | u32 mask = DBI_FIFO_EMPTY; |
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116 | |||
117 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50)) |
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118 | DRM_ERROR("Timeout waiting for DBI FIFO empty\n"); |
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119 | |||
120 | temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe)); |
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121 | temp &= DBI_HS_LP_MODE_MASK; |
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122 | I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE); |
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123 | |||
124 | intel_dsi->hs = enable; |
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125 | } |
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126 | |||
127 | static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, |
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128 | u8 data_type, u16 data) |
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129 | { |
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130 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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131 | struct drm_device *dev = encoder->dev; |
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132 | struct drm_i915_private *dev_priv = dev->dev_private; |
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133 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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134 | enum pipe pipe = intel_crtc->pipe; |
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135 | u32 ctrl_reg; |
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136 | u32 ctrl; |
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137 | u32 mask; |
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138 | |||
139 | DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n", |
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140 | channel, data_type, data); |
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141 | |||
142 | if (intel_dsi->hs) { |
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143 | ctrl_reg = MIPI_HS_GEN_CTRL(pipe); |
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144 | mask = HS_CTRL_FIFO_FULL; |
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145 | } else { |
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146 | ctrl_reg = MIPI_LP_GEN_CTRL(pipe); |
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147 | mask = LP_CTRL_FIFO_FULL; |
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148 | } |
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149 | |||
150 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) { |
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151 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
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152 | print_stat(intel_dsi); |
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153 | } |
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154 | |||
155 | /* |
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156 | * Note: This function is also used for long packets, with length passed |
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157 | * as data, since SHORT_PACKET_PARAM_SHIFT == |
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158 | * LONG_PACKET_WORD_COUNT_SHIFT. |
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159 | */ |
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160 | ctrl = data << SHORT_PACKET_PARAM_SHIFT | |
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161 | channel << VIRTUAL_CHANNEL_SHIFT | |
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162 | data_type << DATA_TYPE_SHIFT; |
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163 | |||
164 | I915_WRITE(ctrl_reg, ctrl); |
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165 | |||
166 | return 0; |
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167 | } |
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168 | |||
169 | static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, |
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170 | u8 data_type, const u8 *data, int len) |
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171 | { |
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172 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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173 | struct drm_device *dev = encoder->dev; |
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174 | struct drm_i915_private *dev_priv = dev->dev_private; |
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175 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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176 | enum pipe pipe = intel_crtc->pipe; |
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177 | u32 data_reg; |
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178 | int i, j, n; |
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179 | u32 mask; |
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180 | |||
181 | DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n", |
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182 | channel, data_type, len); |
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183 | |||
184 | if (intel_dsi->hs) { |
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185 | data_reg = MIPI_HS_GEN_DATA(pipe); |
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186 | mask = HS_DATA_FIFO_FULL; |
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187 | } else { |
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188 | data_reg = MIPI_LP_GEN_DATA(pipe); |
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189 | mask = LP_DATA_FIFO_FULL; |
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190 | } |
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191 | |||
192 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) |
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193 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
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194 | |||
195 | for (i = 0; i < len; i += n) { |
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196 | u32 val = 0; |
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197 | n = min_t(int, len - i, 4); |
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198 | |||
199 | for (j = 0; j < n; j++) |
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200 | val |= *data++ << 8 * j; |
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201 | |||
202 | I915_WRITE(data_reg, val); |
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203 | /* XXX: check for data fifo full, once that is set, write 4 |
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204 | * dwords, then wait for not set, then continue. */ |
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205 | } |
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206 | |||
207 | return dsi_vc_send_short(intel_dsi, channel, data_type, len); |
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208 | } |
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209 | |||
210 | static int dsi_vc_write_common(struct intel_dsi *intel_dsi, |
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211 | int channel, const u8 *data, int len, |
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212 | enum dsi_type type) |
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213 | { |
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214 | int ret; |
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215 | |||
216 | if (len == 0) { |
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217 | BUG_ON(type == DSI_GENERIC); |
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218 | ret = dsi_vc_send_short(intel_dsi, channel, |
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219 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, |
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220 | 0); |
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221 | } else if (len == 1) { |
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222 | ret = dsi_vc_send_short(intel_dsi, channel, |
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223 | type == DSI_GENERIC ? |
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224 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : |
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225 | MIPI_DSI_DCS_SHORT_WRITE, data[0]); |
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226 | } else if (len == 2) { |
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227 | ret = dsi_vc_send_short(intel_dsi, channel, |
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228 | type == DSI_GENERIC ? |
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229 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : |
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230 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
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231 | (data[1] << 8) | data[0]); |
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232 | } else { |
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233 | ret = dsi_vc_send_long(intel_dsi, channel, |
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234 | type == DSI_GENERIC ? |
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235 | MIPI_DSI_GENERIC_LONG_WRITE : |
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236 | MIPI_DSI_DCS_LONG_WRITE, data, len); |
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237 | } |
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238 | |||
239 | return ret; |
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240 | } |
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241 | |||
242 | int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel, |
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243 | const u8 *data, int len) |
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244 | { |
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245 | return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS); |
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246 | } |
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247 | |||
248 | int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel, |
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249 | const u8 *data, int len) |
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250 | { |
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251 | return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC); |
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252 | } |
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253 | |||
254 | static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi, |
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255 | int channel, u8 dcs_cmd) |
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256 | { |
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257 | return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ, |
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258 | dcs_cmd); |
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259 | } |
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260 | |||
261 | static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi, |
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262 | int channel, u8 *reqdata, |
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263 | int reqlen) |
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264 | { |
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265 | u16 data; |
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266 | u8 data_type; |
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267 | |||
268 | switch (reqlen) { |
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269 | case 0: |
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270 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; |
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271 | data = 0; |
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272 | break; |
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273 | case 1: |
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274 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; |
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275 | data = reqdata[0]; |
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276 | break; |
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277 | case 2: |
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278 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; |
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279 | data = (reqdata[1] << 8) | reqdata[0]; |
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280 | break; |
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281 | default: |
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282 | BUG(); |
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283 | } |
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284 | |||
285 | return dsi_vc_send_short(intel_dsi, channel, data_type, data); |
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286 | } |
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287 | |||
288 | static int dsi_read_data_return(struct intel_dsi *intel_dsi, |
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289 | u8 *buf, int buflen) |
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290 | { |
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291 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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292 | struct drm_device *dev = encoder->dev; |
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293 | struct drm_i915_private *dev_priv = dev->dev_private; |
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294 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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295 | enum pipe pipe = intel_crtc->pipe; |
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296 | int i, len = 0; |
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297 | u32 data_reg, val; |
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298 | |||
299 | if (intel_dsi->hs) { |
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300 | data_reg = MIPI_HS_GEN_DATA(pipe); |
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301 | } else { |
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302 | data_reg = MIPI_LP_GEN_DATA(pipe); |
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303 | } |
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304 | |||
305 | while (len < buflen) { |
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306 | val = I915_READ(data_reg); |
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307 | for (i = 0; i < 4 && len < buflen; i++, len++) |
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308 | buf[len] = val >> 8 * i; |
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309 | } |
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310 | |||
311 | return len; |
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312 | } |
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313 | |||
314 | int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, |
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315 | u8 *buf, int buflen) |
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316 | { |
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317 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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318 | struct drm_device *dev = encoder->dev; |
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319 | struct drm_i915_private *dev_priv = dev->dev_private; |
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320 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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321 | enum pipe pipe = intel_crtc->pipe; |
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322 | u32 mask; |
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323 | int ret; |
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324 | |||
325 | /* |
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326 | * XXX: should issue multiple read requests and reads if request is |
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327 | * longer than MIPI_MAX_RETURN_PKT_SIZE |
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328 | */ |
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329 | |||
330 | I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); |
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331 | |||
332 | ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd); |
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333 | if (ret) |
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334 | return ret; |
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335 | |||
336 | mask = GEN_READ_DATA_AVAIL; |
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337 | if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) |
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338 | DRM_ERROR("Timeout waiting for read data.\n"); |
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339 | |||
340 | ret = dsi_read_data_return(intel_dsi, buf, buflen); |
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341 | if (ret < 0) |
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342 | return ret; |
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343 | |||
344 | if (ret != buflen) |
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345 | return -EIO; |
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346 | |||
347 | return 0; |
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348 | } |
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349 | |||
350 | int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, |
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351 | u8 *reqdata, int reqlen, u8 *buf, int buflen) |
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352 | { |
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353 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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354 | struct drm_device *dev = encoder->dev; |
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355 | struct drm_i915_private *dev_priv = dev->dev_private; |
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356 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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357 | enum pipe pipe = intel_crtc->pipe; |
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358 | u32 mask; |
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359 | int ret; |
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360 | |||
361 | /* |
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362 | * XXX: should issue multiple read requests and reads if request is |
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363 | * longer than MIPI_MAX_RETURN_PKT_SIZE |
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364 | */ |
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365 | |||
366 | I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); |
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367 | |||
368 | ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata, |
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369 | reqlen); |
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370 | if (ret) |
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371 | return ret; |
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372 | |||
373 | mask = GEN_READ_DATA_AVAIL; |
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374 | if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) |
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375 | DRM_ERROR("Timeout waiting for read data.\n"); |
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376 | |||
377 | ret = dsi_read_data_return(intel_dsi, buf, buflen); |
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378 | if (ret < 0) |
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379 | return ret; |
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380 | |||
381 | if (ret != buflen) |
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382 | return -EIO; |
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383 | |||
384 | return 0; |
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385 | } |
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386 | |||
387 | /* |
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388 | * send a video mode command |
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389 | * |
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390 | * XXX: commands with data in MIPI_DPI_DATA? |
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391 | */ |
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5060 | serge | 392 | int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) |
4560 | Serge | 393 | { |
394 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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395 | struct drm_device *dev = encoder->dev; |
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396 | struct drm_i915_private *dev_priv = dev->dev_private; |
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397 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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398 | enum pipe pipe = intel_crtc->pipe; |
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399 | u32 mask; |
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400 | |||
401 | /* XXX: pipe, hs */ |
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5060 | serge | 402 | if (hs) |
4560 | Serge | 403 | cmd &= ~DPI_LP_MODE; |
404 | else |
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405 | cmd |= DPI_LP_MODE; |
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406 | |||
407 | /* clear bit */ |
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408 | I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT); |
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409 | |||
410 | /* XXX: old code skips write if control unchanged */ |
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411 | if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe))) |
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412 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); |
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413 | |||
414 | I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd); |
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415 | |||
416 | mask = SPL_PKT_SENT_INTERRUPT; |
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417 | if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100)) |
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418 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
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419 | |||
420 | return 0; |
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421 | } |
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5060 | serge | 422 | |
423 | void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) |
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424 | { |
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425 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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426 | struct drm_device *dev = encoder->dev; |
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427 | struct drm_i915_private *dev_priv = dev->dev_private; |
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428 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
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429 | enum pipe pipe = intel_crtc->pipe; |
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430 | u32 mask; |
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431 | |||
432 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | |
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433 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; |
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434 | |||
435 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) |
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436 | DRM_ERROR("DPI FIFOs are not empty\n"); |
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437 | }>>>>>><>><>><>>>><>><>><> |