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4560 Serge 1
/*
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 * Copyright © 2013 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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 * DEALINGS IN THE SOFTWARE.
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 */
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#ifndef _INTEL_DSI_H
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#define _INTEL_DSI_H
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#include 
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#include 
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#include 
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#include "intel_drv.h"
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/* Dual Link support */
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#define DSI_DUAL_LINK_NONE		0
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#define DSI_DUAL_LINK_FRONT_BACK	1
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#define DSI_DUAL_LINK_PIXEL_ALT		2
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struct intel_dsi_host;
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struct intel_dsi {
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	struct intel_encoder base;
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	struct drm_panel *panel;
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	struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
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	/* GPIO Desc for CRC based Panel control */
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	struct gpio_desc *gpio_panel;
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	struct intel_connector *attached_connector;
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	/* bit mask of ports being driven */
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	u16 ports;
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	/* if true, use HS mode, otherwise LP */
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	bool hs;
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	/* virtual channel */
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	int channel;
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	/* Video mode or command mode */
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	u16 operation_mode;
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	/* number of DSI lanes */
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	unsigned int lane_count;
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	/* video mode pixel format for MIPI_DSI_FUNC_PRG register */
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	u32 pixel_format;
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	/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
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	u32 video_mode_format;
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	/* eot for MIPI_EOT_DISABLE register */
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	u8 eotp_pkt;
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	u8 clock_stop;
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	u8 escape_clk_div;
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	u8 dual_link;
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	u8 pixel_overlap;
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	u32 port_bits;
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	u32 bw_timer;
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	u32 dphy_reg;
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	u32 video_frmt_cfg_bits;
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	u16 lp_byte_clk;
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	/* timeouts in byte clocks */
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	u16 lp_rx_timeout;
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	u16 turn_arnd_val;
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	u16 rst_timer_val;
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	u16 hs_to_lp_count;
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	u16 clk_lp_to_hs_count;
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	u16 clk_hs_to_lp_count;
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	u16 init_count;
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	u32 pclk;
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	u16 burst_mode_ratio;
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	/* all delays in ms */
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	u16 backlight_off_delay;
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	u16 backlight_on_delay;
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	u16 panel_on_delay;
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	u16 panel_off_delay;
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	u16 panel_pwr_cycle_delay;
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};
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struct intel_dsi_host {
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	struct mipi_dsi_host base;
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	struct intel_dsi *intel_dsi;
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	enum port port;
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	/* our little hack */
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	struct mipi_dsi_device *device;
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};
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static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
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{
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	return container_of(h, struct intel_dsi_host, base);
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}
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#define for_each_dsi_port(__port, __ports_mask) \
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	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
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		if ((__ports_mask) & (1 << (__port)))
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static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
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{
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	return container_of(encoder, struct intel_dsi, base.base);
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}
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extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
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extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
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extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
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extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
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extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
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							enum port port);
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struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
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#endif /* _INTEL_DSI_H */