Subversion Repositories Kolibri OS

/*

 * Copyright (c) 2006 Dave Airlie 

 * Copyright (c) 2007-2008 Intel Corporation

 *   Jesse Barnes 

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 */

#ifndef __INTEL_DRV_H__

#define __INTEL_DRV_H__

#include 

#include 

#include 

#include 

#include "i915_drv.h"

#include 

#include 

#include 

#include 

#include 

#include 

#include 

/**

 * _wait_for - magic (register) wait macro

 *

 * Does the right thing for modeset paths when run under kdgb or similar atomic

 * contexts. Note that it's important that we check the condition again after

 * having timed out, since the timeout could be due to preemption or similar and

 * we've never had a chance to check the condition before the timeout.

 */

#define _wait_for(COND, MS, W) ({ \

	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;	\

	int ret__ = 0;							\

	while (!(COND)) {						\

		if (time_after(jiffies, timeout__)) {			\

			if (!(COND))					\

				ret__ = -ETIMEDOUT;			\

			break;						\

		}							\

		if (W )  {				\

         msleep(W); \

		} else {						\

			cpu_relax();					\

		}							\

	}								\

	ret__;								\

})

#define wait_for(COND, MS) _wait_for(COND, MS, 1)

#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)

#define wait_for_atomic_us(COND, US) _wait_for((COND), \

					       DIV_ROUND_UP((US), 1000), 0)

#define KHz(x) (1000 * (x))

#define MHz(x) KHz(1000 * (x))

/*

 * Display related stuff

 */

/* store information about an Ixxx DVO */

/* The i830->i865 use multiple DVOs with multiple i2cs */

/* the i915, i945 have a single sDVO i2c bus - which is different */

#define MAX_OUTPUTS 6

/* maximum connectors per crtcs in the mode set */

/* Maximum cursor sizes */

#define GEN2_CURSOR_WIDTH 64

#define GEN2_CURSOR_HEIGHT 64

#define MAX_CURSOR_WIDTH 256

#define MAX_CURSOR_HEIGHT 256

#define INTEL_I2C_BUS_DVO 1

#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only

   external chips are via DVO or SDVO output */

enum intel_output_type {

	INTEL_OUTPUT_UNUSED = 0,

	INTEL_OUTPUT_ANALOG = 1,

	INTEL_OUTPUT_DVO = 2,

	INTEL_OUTPUT_SDVO = 3,

	INTEL_OUTPUT_LVDS = 4,

	INTEL_OUTPUT_TVOUT = 5,

	INTEL_OUTPUT_HDMI = 6,

	INTEL_OUTPUT_DISPLAYPORT = 7,

	INTEL_OUTPUT_EDP = 8,

	INTEL_OUTPUT_DSI = 9,

	INTEL_OUTPUT_UNKNOWN = 10,

	INTEL_OUTPUT_DP_MST = 11,

};

#define INTEL_DVO_CHIP_NONE 0

#define INTEL_DVO_CHIP_LVDS 1

#define INTEL_DVO_CHIP_TMDS 2

#define INTEL_DVO_CHIP_TVOUT 4

#define INTEL_DSI_VIDEO_MODE	0

#define INTEL_DSI_COMMAND_MODE	1

struct intel_framebuffer {

	struct drm_framebuffer base;

	struct drm_i915_gem_object *obj;

	void   *private; /*Kolibri */

};

struct intel_fbdev {

	struct drm_fb_helper helper;

	struct intel_framebuffer *fb;

	int preferred_bpp;

};

struct intel_encoder {

	struct drm_encoder base;

	enum intel_output_type type;

	unsigned int cloneable;

	void (*hot_plug)(struct intel_encoder *);

	bool (*compute_config)(struct intel_encoder *,

			       struct intel_crtc_state *);

	void (*pre_pll_enable)(struct intel_encoder *);

	void (*pre_enable)(struct intel_encoder *);

	void (*enable)(struct intel_encoder *);

	void (*mode_set)(struct intel_encoder *intel_encoder);

	void (*disable)(struct intel_encoder *);

	void (*post_disable)(struct intel_encoder *);

	void (*post_pll_disable)(struct intel_encoder *);

	/* Read out the current hw state of this connector, returning true if

	 * the encoder is active. If the encoder is enabled it also set the pipe

	 * it is connected to in the pipe parameter. */

	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);

	/* Reconstructs the equivalent mode flags for the current hardware

	 * state. This must be called _after_ display->get_pipe_config has

	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must

	 * be set correctly before calling this function. */

	void (*get_config)(struct intel_encoder *,

			   struct intel_crtc_state *pipe_config);

	/*

	 * Called during system suspend after all pending requests for the

	 * encoder are flushed (for example for DP AUX transactions) and

	 * device interrupts are disabled.

	 */

	void (*suspend)(struct intel_encoder *);

	int crtc_mask;

	enum hpd_pin hpd_pin;

};

struct intel_panel {

	struct drm_display_mode *fixed_mode;

	struct drm_display_mode *downclock_mode;

	int fitting_mode;

	/* backlight */

	struct {

		bool present;

		u32 level;

		u32 min;

		u32 max;

		bool enabled;

		bool combination_mode;	/* gen 2/4 only */

		bool active_low_pwm;

		/* PWM chip */

		bool util_pin_active_low;	/* bxt+ */

		u8 controller;		/* bxt+ only */

		struct pwm_device *pwm;

		struct backlight_device *device;

		/* Connector and platform specific backlight functions */

		int (*setup)(struct intel_connector *connector, enum pipe pipe);

		uint32_t (*get)(struct intel_connector *connector);

		void (*set)(struct intel_connector *connector, uint32_t level);

		void (*disable)(struct intel_connector *connector);

		void (*enable)(struct intel_connector *connector);

		uint32_t (*hz_to_pwm)(struct intel_connector *connector,

				      uint32_t hz);

		void (*power)(struct intel_connector *, bool enable);

	} backlight;

};

struct intel_connector {

	struct drm_connector base;

	/*

	 * The fixed encoder this connector is connected to.

	 */

	struct intel_encoder *encoder;

	/* Reads out the current hw, returning true if the connector is enabled

	 * and active (i.e. dpms ON state). */

	bool (*get_hw_state)(struct intel_connector *);

	/*

	 * Removes all interfaces through which the connector is accessible

	 * - like sysfs, debugfs entries -, so that no new operations can be

	 * started on the connector. Also makes sure all currently pending

	 * operations finish before returing.

	 */

	void (*unregister)(struct intel_connector *);

	/* Panel info for eDP and LVDS */

	struct intel_panel panel;

	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */

	struct edid *edid;

	struct edid *detect_edid;

	/* since POLL and HPD connectors may use the same HPD line keep the native

	   state of connector->polled in case hotplug storm detection changes it */

	u8 polled;

	void *port; /* store this opaque as its illegal to dereference it */

	struct intel_dp *mst_port;

};

typedef struct dpll {

	/* given values */

	int n;

	int m1, m2;

	int p1, p2;

	/* derived values */

	int	dot;

	int	vco;

	int	m;

	int	p;

} intel_clock_t;

struct intel_atomic_state {

	struct drm_atomic_state base;

	unsigned int cdclk;

	/*

	 * Calculated device cdclk, can be different from cdclk

	 * only when all crtc's are DPMS off.

	 */

	unsigned int dev_cdclk;

	bool dpll_set, modeset;

	unsigned int active_crtcs;

	unsigned int min_pixclk[I915_MAX_PIPES];

	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];

	struct intel_wm_config wm_config;

};

struct intel_plane_state {

	struct drm_plane_state base;

	struct drm_rect src;

	struct drm_rect dst;

	struct drm_rect clip;

	bool visible;

	/*

	 * scaler_id

	 *    = -1 : not using a scaler

	 *    >=  0 : using a scalers

	 *

	 * plane requiring a scaler:

	 *   - During check_plane, its bit is set in

	 *     crtc_state->scaler_state.scaler_users by calling helper function

	 *     update_scaler_plane.

	 *   - scaler_id indicates the scaler it got assigned.

	 *

	 * plane doesn't require a scaler:

	 *   - this can happen when scaling is no more required or plane simply

	 *     got disabled.

	 *   - During check_plane, corresponding bit is reset in

	 *     crtc_state->scaler_state.scaler_users by calling helper function

	 *     update_scaler_plane.

	 */

	int scaler_id;

	struct drm_intel_sprite_colorkey ckey;

	/* async flip related structures */

	struct drm_i915_gem_request *wait_req;

};

struct intel_initial_plane_config {

	struct intel_framebuffer *fb;

	unsigned int tiling;

	int size;

	u32 base;

};

#define SKL_MIN_SRC_W 8

#define SKL_MAX_SRC_W 4096

#define SKL_MIN_SRC_H 8

#define SKL_MAX_SRC_H 4096

#define SKL_MIN_DST_W 8

#define SKL_MAX_DST_W 4096

#define SKL_MIN_DST_H 8

#define SKL_MAX_DST_H 4096

struct intel_scaler {

	int in_use;

	uint32_t mode;

};

struct intel_crtc_scaler_state {

#define SKL_NUM_SCALERS 2

	struct intel_scaler scalers[SKL_NUM_SCALERS];

	/*

	 * scaler_users: keeps track of users requesting scalers on this crtc.

	 *

	 *     If a bit is set, a user is using a scaler.

	 *     Here user can be a plane or crtc as defined below:

	 *       bits 0-30 - plane (bit position is index from drm_plane_index)

	 *       bit 31    - crtc

	 *

	 * Instead of creating a new index to cover planes and crtc, using

	 * existing drm_plane_index for planes which is well less than 31

	 * planes and bit 31 for crtc. This should be fine to cover all

	 * our platforms.

	 *

	 * intel_atomic_setup_scalers will setup available scalers to users

	 * requesting scalers. It will gracefully fail if request exceeds

	 * avilability.

	 */

#define SKL_CRTC_INDEX 31

	unsigned scaler_users;

	/* scaler used by crtc for panel fitting purpose */

	int scaler_id;

};

/* drm_mode->private_flags */

#define I915_MODE_FLAG_INHERITED 1

struct intel_pipe_wm {

	struct intel_wm_level wm[5];

	uint32_t linetime;

	bool fbc_wm_enabled;

	bool pipe_enabled;

	bool sprites_enabled;

	bool sprites_scaled;

};

struct skl_pipe_wm {

	struct skl_wm_level wm[8];

	struct skl_wm_level trans_wm;

	uint32_t linetime;

};

struct intel_crtc_state {

	struct drm_crtc_state base;

	/**

	 * quirks - bitfield with hw state readout quirks

	 *

	 * For various reasons the hw state readout code might not be able to

	 * completely faithfully read out the current state. These cases are

	 * tracked with quirk flags so that fastboot and state checker can act

	 * accordingly.

	 */

#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */

	unsigned long quirks;

	bool update_pipe; /* can a fast modeset be performed? */

	bool disable_cxsr;

	bool update_wm_pre, update_wm_post; /* watermarks are updated */

	bool fb_changed; /* fb on any of the planes is changed */

	/* Pipe source size (ie. panel fitter input size)

	 * All planes will be positioned inside this space,

	 * and get clipped at the edges. */

	int pipe_src_w, pipe_src_h;

	/* Whether to set up the PCH/FDI. Note that we never allow sharing

	 * between pch encoders and cpu encoders. */

	bool has_pch_encoder;

	/* Are we sending infoframes on the attached port */

	bool has_infoframe;

	/* CPU Transcoder for the pipe. Currently this can only differ from the

	 * pipe on Haswell (where we have a special eDP transcoder). */

	enum transcoder cpu_transcoder;

	/*

	 * Use reduced/limited/broadcast rbg range, compressing from the full

	 * range fed into the crtcs.

	 */

	bool limited_color_range;

	/* DP has a bunch of special case unfortunately, so mark the pipe

	 * accordingly. */

	bool has_dp_encoder;

	/* DSI has special cases */

	bool has_dsi_encoder;

	/* Whether we should send NULL infoframes. Required for audio. */

	bool has_hdmi_sink;

	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or

	 * has_dp_encoder is set. */

	bool has_audio;

	/*

	 * Enable dithering, used when the selected pipe bpp doesn't match the

	 * plane bpp.

	 */

	bool dither;

	/* Controls for the clock computation, to override various stages. */

	bool clock_set;

	/* SDVO TV has a bunch of special case. To make multifunction encoders

	 * work correctly, we need to track this at runtime.*/

	bool sdvo_tv_clock;

	/*

	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really

	 * required. This is set in the 2nd loop of calling encoder's

	 * ->compute_config if the first pick doesn't work out.

	 */

	bool bw_constrained;

	/* Settings for the intel dpll used on pretty much everything but

	 * haswell. */

	struct dpll dpll;

	/* Selected dpll when shared or DPLL_ID_PRIVATE. */

	enum intel_dpll_id shared_dpll;

	/*

	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.

	 * - enum skl_dpll on SKL

	 */

	uint32_t ddi_pll_sel;

	/* Actual register state of the dpll, for shared dpll cross-checking. */

	struct intel_dpll_hw_state dpll_hw_state;

	int pipe_bpp;

	struct intel_link_m_n dp_m_n;

	/* m2_n2 for eDP downclock */

	struct intel_link_m_n dp_m2_n2;

	bool has_drrs;

	/*

	 * Frequence the dpll for the port should run at. Differs from the

	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also

	 * already multiplied by pixel_multiplier.

	 */

	int port_clock;

	/* Used by SDVO (and if we ever fix it, HDMI). */

	unsigned pixel_multiplier;

	uint8_t lane_count;

	/* Panel fitter controls for gen2-gen4 + VLV */

	struct {

		u32 control;

		u32 pgm_ratios;

		u32 lvds_border_bits;

	} gmch_pfit;

	/* Panel fitter placement and size for Ironlake+ */

	struct {

		u32 pos;

		u32 size;

		bool enabled;

		bool force_thru;

	} pch_pfit;

	/* FDI configuration, only valid if has_pch_encoder is set. */

	int fdi_lanes;

	struct intel_link_m_n fdi_m_n;

	bool ips_enabled;

	bool enable_fbc;

	bool double_wide;

	bool dp_encoder_is_mst;

	int pbn;

	struct intel_crtc_scaler_state scaler_state;

	/* w/a for waiting 2 vblanks during crtc enable */

	enum pipe hsw_workaround_pipe;

	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */

	bool disable_lp_wm;

	struct {

		/*

		 * optimal watermarks, programmed post-vblank when this state

		 * is committed

		 */

		union {

			struct intel_pipe_wm ilk;

			struct skl_pipe_wm skl;

		} optimal;

	} wm;

};

struct vlv_wm_state {

	struct vlv_pipe_wm wm[3];

	struct vlv_sr_wm sr[3];

	uint8_t num_active_planes;

	uint8_t num_levels;

	uint8_t level;

	bool cxsr;

};

struct intel_mmio_flip {

	struct work_struct work;

	struct drm_i915_private *i915;

	struct drm_i915_gem_request *req;

	struct intel_crtc *crtc;

	unsigned int rotation;

};

/*

 * Tracking of operations that need to be performed at the beginning/end of an

 * atomic commit, outside the atomic section where interrupts are disabled.

 * These are generally operations that grab mutexes or might otherwise sleep

 * and thus can't be run with interrupts disabled.

 */

struct intel_crtc_atomic_commit {

	/* Sleepable operations to perform before commit */

	/* Sleepable operations to perform after commit */

	unsigned fb_bits;

	bool post_enable_primary;

	/* Sleepable operations to perform before and after commit */

	bool update_fbc;

};

struct intel_crtc {

	struct drm_crtc base;

	enum pipe pipe;

	enum plane plane;

	u8 lut_r[256], lut_g[256], lut_b[256];

	/*

	 * Whether the crtc and the connected output pipeline is active. Implies

	 * that crtc->enabled is set, i.e. the current mode configuration has

	 * some outputs connected to this crtc.

	 */

	bool active;

	unsigned long enabled_power_domains;

	bool lowfreq_avail;

	struct intel_overlay *overlay;

	struct intel_unpin_work *unpin_work;

	atomic_t unpin_work_count;

	/* Display surface base address adjustement for pageflips. Note that on

	 * gen4+ this only adjusts up to a tile, offsets within a tile are

	 * handled in the hw itself (with the TILEOFF register). */

	u32 dspaddr_offset;

	int adjusted_x;

	int adjusted_y;

	uint32_t cursor_addr;

	uint32_t cursor_cntl;

	uint32_t cursor_size;

	uint32_t cursor_base;

	struct intel_crtc_state *config;

	/* reset counter value when the last flip was submitted */

	unsigned int reset_counter;

	/* Access to these should be protected by dev_priv->irq_lock. */

	bool cpu_fifo_underrun_disabled;

	bool pch_fifo_underrun_disabled;

	/* per-pipe watermark state */

	struct {

		/* watermarks currently being used  */

		union {

			struct intel_pipe_wm ilk;

			struct skl_pipe_wm skl;

		} active;

		/* allow CxSR on this pipe */

		bool cxsr_allowed;

	} wm;

	int scanline_offset;

	struct {

		unsigned start_vbl_count;

		ktime_t start_vbl_time;

		int min_vbl, max_vbl;

		int scanline_start;

	} debug;

	struct intel_crtc_atomic_commit atomic;

	/* scalers available on this crtc */

	int num_scalers;

	struct vlv_wm_state wm_state;

};

struct intel_plane_wm_parameters {

	uint32_t horiz_pixels;

	uint32_t vert_pixels;

	/*

	 *   For packed pixel formats:

	 *     bytes_per_pixel - holds bytes per pixel

	 *   For planar pixel formats:

	 *     bytes_per_pixel - holds bytes per pixel for uv-plane

	 *     y_bytes_per_pixel - holds bytes per pixel for y-plane

	 */

	uint8_t bytes_per_pixel;

	uint8_t y_bytes_per_pixel;

	bool enabled;

	bool scaled;

	u64 tiling;

	unsigned int rotation;

	uint16_t fifo_size;

};

struct intel_plane {

	struct drm_plane base;

	int plane;

	enum pipe pipe;

	bool can_scale;

	int max_downscale;

	uint32_t frontbuffer_bit;

	/* Since we need to change the watermarks before/after

	 * enabling/disabling the planes, we need to store the parameters here

	 * as the other pieces of the struct may not reflect the values we want

	 * for the watermark calculations. Currently only Haswell uses this.

	 */

	struct intel_plane_wm_parameters wm;

	/*

	 * NOTE: Do not place new plane state fields here (e.g., when adding

	 * new plane properties).  New runtime state should now be placed in

	 * the intel_plane_state structure and accessed via plane_state.

	 */

	void (*update_plane)(struct drm_plane *plane,

			     const struct intel_crtc_state *crtc_state,

			     const struct intel_plane_state *plane_state);

	void (*disable_plane)(struct drm_plane *plane,

			      struct drm_crtc *crtc);

	int (*check_plane)(struct drm_plane *plane,

			   struct intel_crtc_state *crtc_state,

			   struct intel_plane_state *state);

};

struct intel_watermark_params {

	unsigned long fifo_size;

	unsigned long max_wm;

	unsigned long default_wm;

	unsigned long guard_size;

	unsigned long cacheline_size;

};

struct cxsr_latency {

	int is_desktop;

	int is_ddr3;

	unsigned long fsb_freq;

	unsigned long mem_freq;

	unsigned long display_sr;

	unsigned long display_hpll_disable;

	unsigned long cursor_sr;

	unsigned long cursor_hpll_disable;

};

#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)

#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)

#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)

#define to_intel_connector(x) container_of(x, struct intel_connector, base)

#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)

#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)

#define to_intel_plane(x) container_of(x, struct intel_plane, base)

#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)

#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)

struct intel_hdmi {

	i915_reg_t hdmi_reg;

	int ddc_bus;

	struct {

		enum drm_dp_dual_mode_type type;

		int max_tmds_clock;

	} dp_dual_mode;

	bool limited_color_range;

	bool color_range_auto;

	bool has_hdmi_sink;

	bool has_audio;

	enum hdmi_force_audio force_audio;

	bool rgb_quant_range_selectable;

	enum hdmi_picture_aspect aspect_ratio;

	struct intel_connector *attached_connector;

	void (*write_infoframe)(struct drm_encoder *encoder,

				enum hdmi_infoframe_type type,

				const void *frame, ssize_t len);

	void (*set_infoframes)(struct drm_encoder *encoder,

			       bool enable,

			       const struct drm_display_mode *adjusted_mode);

	bool (*infoframe_enabled)(struct drm_encoder *encoder,

				  const struct intel_crtc_state *pipe_config);

};

struct intel_dp_mst_encoder;

#define DP_MAX_DOWNSTREAM_PORTS		0x10

/*

 * enum link_m_n_set:

 *	When platform provides two set of M_N registers for dp, we can

 *	program them and switch between them incase of DRRS.

 *	But When only one such register is provided, we have to program the

 *	required divider value on that registers itself based on the DRRS state.

 *

 * M1_N1	: Program dp_m_n on M1_N1 registers

 *			  dp_m2_n2 on M2_N2 registers (If supported)

 *

 * M2_N2	: Program dp_m2_n2 on M1_N1 registers

 *			  M2_N2 registers are not supported

 */

enum link_m_n_set {

	/* Sets the m1_n1 and m2_n2 */

	M1_N1 = 0,

	M2_N2

};

struct intel_dp {

	i915_reg_t output_reg;

	i915_reg_t aux_ch_ctl_reg;

	i915_reg_t aux_ch_data_reg[5];

	uint32_t DP;

	int link_rate;

	uint8_t lane_count;

	bool has_audio;

	enum hdmi_force_audio force_audio;

	bool limited_color_range;

	bool color_range_auto;

	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */

	uint8_t num_sink_rates;

	int sink_rates[DP_MAX_SUPPORTED_RATES];

	struct drm_dp_aux aux;

	uint8_t train_set[4];

	int panel_power_up_delay;

	int panel_power_down_delay;

	int panel_power_cycle_delay;

	int backlight_on_delay;

	int backlight_off_delay;

	struct delayed_work panel_vdd_work;

	bool want_panel_vdd;

	unsigned long last_power_on;

	unsigned long last_backlight_off;

	ktime_t panel_power_off_time;

	struct notifier_block edp_notifier;

	/*

	 * Pipe whose power sequencer is currently locked into

	 * this port. Only relevant on VLV/CHV.

	 */

	enum pipe pps_pipe;

	struct edp_power_seq pps_delays;

	bool can_mst; /* this port supports mst */

	bool is_mst;

	int active_mst_links;

	/* connector directly attached - won't be use for modeset in mst world */

	struct intel_connector *attached_connector;

	/* mst connector list */

	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];

	struct drm_dp_mst_topology_mgr mst_mgr;

	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);

	/*

	 * This function returns the value we have to program the AUX_CTL

	 * register with to kick off an AUX transaction.

	 */

	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,

				     bool has_aux_irq,

				     int send_bytes,

				     uint32_t aux_clock_divider);

	/* This is called before a link training is starterd */

	void (*prepare_link_retrain)(struct intel_dp *intel_dp);

	/* Displayport compliance testing */

	unsigned long compliance_test_type;

	unsigned long compliance_test_data;

	bool compliance_test_active;

};

struct intel_digital_port {

	struct intel_encoder base;

	enum port port;

	u32 saved_port_bits;

	struct intel_dp dp;

	struct intel_hdmi hdmi;

	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);

	bool release_cl2_override;

	uint8_t max_lanes;

	/* for communication with audio component; protected by av_mutex */

	const struct drm_connector *audio_connector;

};

struct intel_dp_mst_encoder {

	struct intel_encoder base;

	enum pipe pipe;

	struct intel_digital_port *primary;

	void *port; /* store this opaque as its illegal to dereference it */

};

static inline enum dpio_channel

vlv_dport_to_channel(struct intel_digital_port *dport)

{

	switch (dport->port) {

	case PORT_B:

	case PORT_D:

		return DPIO_CH0;

	case PORT_C:

		return DPIO_CH1;

	default:

		BUG();

	}

}

static inline enum dpio_phy

vlv_dport_to_phy(struct intel_digital_port *dport)

{

	switch (dport->port) {

	case PORT_B:

	case PORT_C:

		return DPIO_PHY0;

	case PORT_D:

		return DPIO_PHY1;

	default:

		BUG();

	}

}

static inline enum dpio_channel

vlv_pipe_to_channel(enum pipe pipe)

{

	switch (pipe) {

	case PIPE_A:

	case PIPE_C:

		return DPIO_CH0;

	case PIPE_B:

		return DPIO_CH1;

	default:

		BUG();

	}

}

static inline struct drm_crtc *

intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->pipe_to_crtc_mapping[pipe];

}

static inline struct drm_crtc *

intel_get_crtc_for_plane(struct drm_device *dev, int plane)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->plane_to_crtc_mapping[plane];

}

struct intel_unpin_work {

	struct work_struct work;

	struct drm_crtc *crtc;

	struct drm_framebuffer *old_fb;

	struct drm_i915_gem_object *pending_flip_obj;

	struct drm_pending_vblank_event *event;

	atomic_t pending;

#define INTEL_FLIP_INACTIVE	0

#define INTEL_FLIP_PENDING	1

#define INTEL_FLIP_COMPLETE	2

	u32 flip_count;

	u32 gtt_offset;

	struct drm_i915_gem_request *flip_queued_req;

	u32 flip_queued_vblank;

	u32 flip_ready_vblank;

	bool enable_stall_check;

};

struct intel_load_detect_pipe {

	struct drm_atomic_state *restore_state;

};

static inline struct intel_encoder *

intel_attached_encoder(struct drm_connector *connector)

{

	return to_intel_connector(connector)->encoder;

}

static inline struct intel_digital_port *

enc_to_dig_port(struct drm_encoder *encoder)

{

	return container_of(encoder, struct intel_digital_port, base.base);

}

static inline struct intel_dp_mst_encoder *

enc_to_mst(struct drm_encoder *encoder)

{

	return container_of(encoder, struct intel_dp_mst_encoder, base.base);

}

static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)

{

	return &enc_to_dig_port(encoder)->dp;

}

static inline struct intel_digital_port *

dp_to_dig_port(struct intel_dp *intel_dp)

{

	return container_of(intel_dp, struct intel_digital_port, dp);

}

static inline struct intel_digital_port *

hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)

{

	return container_of(intel_hdmi, struct intel_digital_port, hdmi);

}

/*

 * Returns the number of planes for this pipe, ie the number of sprites + 1

 * (primary plane). This doesn't count the cursor plane then.

 */

static inline unsigned int intel_num_planes(struct intel_crtc *crtc)

{

	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;

}

/* intel_fifo_underrun.c */

bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum pipe pipe, bool enable);

bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

					   enum transcoder pch_transcoder,

					   bool enable);

void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum pipe pipe);

void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,

					 enum transcoder pch_transcoder);

void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);

void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);

/* i915_irq.c */

void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_reset_rps_interrupts(struct drm_device *dev);

void gen6_enable_rps_interrupts(struct drm_device *dev);

void gen6_disable_rps_interrupts(struct drm_device *dev);

u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);

void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);

void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);

static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)

{

	/*

	 * We only use drm_irq_uninstall() at unload and VT switch, so

	 * this is the only thing we need to check.

	 */

	return dev_priv->pm.irqs_enabled;

}

int intel_get_crtc_scanline(struct intel_crtc *crtc);

void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,

				     unsigned int pipe_mask);

void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,

				     unsigned int pipe_mask);

/* intel_crt.c */

void intel_crt_init(struct drm_device *dev);

/* intel_ddi.c */

void intel_ddi_clk_select(struct intel_encoder *encoder,

			  const struct intel_crtc_state *pipe_config);

void intel_prepare_ddi_buffer(struct intel_encoder *encoder);

void hsw_fdi_link_train(struct drm_crtc *crtc);

void intel_ddi_init(struct drm_device *dev, enum port port);

enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);

bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);

void intel_ddi_pll_init(struct drm_device *dev);

void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);

void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,

				       enum transcoder cpu_transcoder);

void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);

void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);

bool intel_ddi_pll_select(struct intel_crtc *crtc,

			  struct intel_crtc_state *crtc_state);

void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);

void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);

bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);

void intel_ddi_fdi_disable(struct drm_crtc *crtc);

void intel_ddi_get_config(struct intel_encoder *encoder,

			  struct intel_crtc_state *pipe_config);

struct intel_encoder *

intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);

void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);

void intel_ddi_clock_get(struct intel_encoder *encoder,

			 struct intel_crtc_state *pipe_config);

void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);

uint32_t ddi_signal_levels(struct intel_dp *intel_dp);

/* intel_frontbuffer.c */

void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,

			     enum fb_op_origin origin);

void intel_frontbuffer_flip_prepare(struct drm_device *dev,

				    unsigned frontbuffer_bits);

void intel_frontbuffer_flip_complete(struct drm_device *dev,

				     unsigned frontbuffer_bits);

void intel_frontbuffer_flip(struct drm_device *dev,

			    unsigned frontbuffer_bits);

unsigned int intel_fb_align_height(struct drm_device *dev,

				   unsigned int height,

				   uint32_t pixel_format,

				   uint64_t fb_format_modifier);

void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,

			enum fb_op_origin origin);

u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,

			      uint64_t fb_modifier, uint32_t pixel_format);

/* intel_audio.c */

void intel_init_audio(struct drm_device *dev);

void intel_audio_codec_enable(struct intel_encoder *encoder);

void intel_audio_codec_disable(struct intel_encoder *encoder);

void i915_audio_component_init(struct drm_i915_private *dev_priv);

void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);

/* intel_display.c */

extern const struct drm_plane_funcs intel_plane_funcs;

bool intel_has_pending_fb_unpin(struct drm_device *dev);

int intel_pch_rawclk(struct drm_device *dev);

int intel_hrawclk(struct drm_device *dev);

void intel_mark_busy(struct drm_device *dev);

void intel_mark_idle(struct drm_device *dev);

void intel_crtc_restore_mode(struct drm_crtc *crtc);

int intel_display_suspend(struct drm_device *dev);

void intel_encoder_destroy(struct drm_encoder *encoder);

int intel_connector_init(struct intel_connector *);

struct intel_connector *intel_connector_alloc(void);

bool intel_connector_get_hw_state(struct intel_connector *connector);

void intel_connector_attach_encoder(struct intel_connector *connector,

				    struct intel_encoder *encoder);

struct drm_encoder *intel_best_encoder(struct drm_connector *connector);

struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,