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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
28 | #include |
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3031 | serge | 29 | #include |
2326 | Serge | 30 | #include "i915_drv.h" |
3031 | serge | 31 | #include |
32 | #include |
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33 | #include |
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34 | #include |
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2326 | Serge | 35 | |
3482 | Serge | 36 | #define KBUILD_MODNAME "i915.dll" |
37 | |||
3031 | serge | 38 | #define cpu_relax() asm volatile("rep; nop") |
39 | |||
2326 | Serge | 40 | #define _wait_for(COND, MS, W) ({ \ |
3031 | serge | 41 | unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
2326 | Serge | 42 | int ret__ = 0; \ |
2342 | Serge | 43 | while (!(COND)) { \ |
3031 | serge | 44 | if (time_after(GetTimerTicks(), timeout__)) { \ |
2326 | Serge | 45 | ret__ = -ETIMEDOUT; \ |
46 | break; \ |
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47 | } \ |
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3031 | serge | 48 | if (W ) { \ |
49 | msleep(W); \ |
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50 | } else { \ |
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51 | cpu_relax(); \ |
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52 | } \ |
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2326 | Serge | 53 | } \ |
54 | ret__; \ |
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55 | }) |
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56 | |||
3031 | serge | 57 | #define wait_for_atomic_us(COND, US) ({ \ |
58 | unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US); \ |
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59 | int ret__ = 0; \ |
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60 | while (!(COND)) { \ |
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61 | if (time_after(GetTimerTicks(), timeout__)) { \ |
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62 | ret__ = -ETIMEDOUT; \ |
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63 | break; \ |
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64 | } \ |
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65 | cpu_relax(); \ |
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66 | } \ |
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67 | ret__; \ |
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68 | }) |
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69 | |||
2326 | Serge | 70 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
71 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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72 | |||
73 | #define MSLEEP(x) do { \ |
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74 | if (in_dbg_master()) \ |
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75 | mdelay(x); \ |
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76 | else \ |
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77 | msleep(x); \ |
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78 | } while(0) |
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79 | |||
80 | #define KHz(x) (1000*x) |
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81 | #define MHz(x) KHz(1000*x) |
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82 | |||
83 | /* |
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84 | * Display related stuff |
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85 | */ |
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86 | |||
87 | /* store information about an Ixxx DVO */ |
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88 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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89 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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90 | #define MAX_OUTPUTS 6 |
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91 | /* maximum connectors per crtcs in the mode set */ |
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92 | #define INTELFB_CONN_LIMIT 4 |
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93 | |||
94 | #define INTEL_I2C_BUS_DVO 1 |
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95 | #define INTEL_I2C_BUS_SDVO 2 |
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96 | |||
97 | /* these are outputs from the chip - integrated only |
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98 | external chips are via DVO or SDVO output */ |
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99 | #define INTEL_OUTPUT_UNUSED 0 |
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100 | #define INTEL_OUTPUT_ANALOG 1 |
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101 | #define INTEL_OUTPUT_DVO 2 |
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102 | #define INTEL_OUTPUT_SDVO 3 |
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103 | #define INTEL_OUTPUT_LVDS 4 |
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104 | #define INTEL_OUTPUT_TVOUT 5 |
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105 | #define INTEL_OUTPUT_HDMI 6 |
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106 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
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107 | #define INTEL_OUTPUT_EDP 8 |
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3243 | Serge | 108 | #define INTEL_OUTPUT_UNKNOWN 9 |
2326 | Serge | 109 | |
110 | #define INTEL_DVO_CHIP_NONE 0 |
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111 | #define INTEL_DVO_CHIP_LVDS 1 |
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112 | #define INTEL_DVO_CHIP_TMDS 2 |
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113 | #define INTEL_DVO_CHIP_TVOUT 4 |
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114 | |||
115 | /* drm_display_mode->private_flags */ |
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116 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) |
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117 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) |
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2342 | Serge | 118 | #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
3031 | serge | 119 | /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
120 | * timings in the mode to prevent the crtc fixup from overwriting them. |
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121 | * Currently only lvds needs that. */ |
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122 | #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) |
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3480 | Serge | 123 | /* |
124 | * Set when limited 16-235 (as opposed to full 0-255) RGB color range is |
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125 | * to be used. |
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126 | */ |
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127 | #define INTEL_MODE_LIMITED_COLOR_RANGE (0x40) |
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2326 | Serge | 128 | |
129 | static inline void |
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130 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, |
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131 | int multiplier) |
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132 | { |
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133 | mode->clock *= multiplier; |
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134 | mode->private_flags |= multiplier; |
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135 | } |
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136 | |||
137 | static inline int |
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138 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) |
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139 | { |
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140 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; |
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141 | } |
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142 | |||
143 | struct intel_framebuffer { |
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144 | struct drm_framebuffer base; |
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145 | struct drm_i915_gem_object *obj; |
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146 | }; |
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147 | |||
148 | struct intel_fbdev { |
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149 | struct drm_fb_helper helper; |
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150 | struct intel_framebuffer ifb; |
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151 | struct list_head fbdev_list; |
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152 | struct drm_display_mode *our_mode; |
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153 | }; |
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154 | |||
155 | struct intel_encoder { |
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156 | struct drm_encoder base; |
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3031 | serge | 157 | /* |
158 | * The new crtc this encoder will be driven from. Only differs from |
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159 | * base->crtc while a modeset is in progress. |
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160 | */ |
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161 | struct intel_crtc *new_crtc; |
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162 | |||
2326 | Serge | 163 | int type; |
164 | bool needs_tv_clock; |
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3031 | serge | 165 | /* |
166 | * Intel hw has only one MUX where encoders could be clone, hence a |
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167 | * simple flag is enough to compute the possible_clones mask. |
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168 | */ |
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169 | bool cloneable; |
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170 | bool connectors_active; |
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2326 | Serge | 171 | void (*hot_plug)(struct intel_encoder *); |
3480 | Serge | 172 | void (*pre_pll_enable)(struct intel_encoder *); |
3031 | serge | 173 | void (*pre_enable)(struct intel_encoder *); |
174 | void (*enable)(struct intel_encoder *); |
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175 | void (*disable)(struct intel_encoder *); |
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176 | void (*post_disable)(struct intel_encoder *); |
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177 | /* Read out the current hw state of this connector, returning true if |
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178 | * the encoder is active. If the encoder is enabled it also set the pipe |
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179 | * it is connected to in the pipe parameter. */ |
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180 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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2326 | Serge | 181 | int crtc_mask; |
182 | }; |
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183 | |||
3243 | Serge | 184 | struct intel_panel { |
185 | struct drm_display_mode *fixed_mode; |
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186 | int fitting_mode; |
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187 | }; |
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188 | |||
2326 | Serge | 189 | struct intel_connector { |
190 | struct drm_connector base; |
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3031 | serge | 191 | /* |
192 | * The fixed encoder this connector is connected to. |
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193 | */ |
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2326 | Serge | 194 | struct intel_encoder *encoder; |
3031 | serge | 195 | |
196 | /* |
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197 | * The new encoder this connector will be driven. Only differs from |
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198 | * encoder while a modeset is in progress. |
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199 | */ |
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200 | struct intel_encoder *new_encoder; |
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201 | |||
202 | /* Reads out the current hw, returning true if the connector is enabled |
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203 | * and active (i.e. dpms ON state). */ |
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204 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 205 | |
206 | /* Panel info for eDP and LVDS */ |
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207 | struct intel_panel panel; |
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208 | |||
209 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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210 | struct edid *edid; |
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2326 | Serge | 211 | }; |
212 | |||
213 | struct intel_crtc { |
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214 | struct drm_crtc base; |
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215 | enum pipe pipe; |
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216 | enum plane plane; |
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3243 | Serge | 217 | enum transcoder cpu_transcoder; |
2326 | Serge | 218 | u8 lut_r[256], lut_g[256], lut_b[256]; |
3031 | serge | 219 | /* |
220 | * Whether the crtc and the connected output pipeline is active. Implies |
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221 | * that crtc->enabled is set, i.e. the current mode configuration has |
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222 | * some outputs connected to this crtc. |
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223 | */ |
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224 | bool active; |
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3480 | Serge | 225 | bool eld_vld; |
3031 | serge | 226 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
2326 | Serge | 227 | bool lowfreq_avail; |
228 | struct intel_overlay *overlay; |
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229 | struct intel_unpin_work *unpin_work; |
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230 | int fdi_lanes; |
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231 | |||
3243 | Serge | 232 | atomic_t unpin_work_count; |
233 | |||
3031 | serge | 234 | /* Display surface base address adjustement for pageflips. Note that on |
235 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
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236 | * handled in the hw itself (with the TILEOFF register). */ |
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237 | unsigned long dspaddr_offset; |
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238 | |||
2326 | Serge | 239 | struct drm_i915_gem_object *cursor_bo; |
240 | uint32_t cursor_addr; |
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241 | int16_t cursor_x, cursor_y; |
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242 | int16_t cursor_width, cursor_height; |
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243 | bool cursor_visible; |
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244 | unsigned int bpp; |
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2342 | Serge | 245 | |
3031 | serge | 246 | /* We can share PLLs across outputs if the timings match */ |
247 | struct intel_pch_pll *pch_pll; |
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3243 | Serge | 248 | uint32_t ddi_pll_sel; |
3480 | Serge | 249 | |
250 | /* reset counter value when the last flip was submitted */ |
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251 | unsigned int reset_counter; |
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2326 | Serge | 252 | }; |
253 | |||
2342 | Serge | 254 | struct intel_plane { |
255 | struct drm_plane base; |
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256 | enum pipe pipe; |
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257 | struct drm_i915_gem_object *obj; |
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3243 | Serge | 258 | bool can_scale; |
2342 | Serge | 259 | int max_downscale; |
260 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
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261 | void (*update_plane)(struct drm_plane *plane, |
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262 | struct drm_framebuffer *fb, |
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263 | struct drm_i915_gem_object *obj, |
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264 | int crtc_x, int crtc_y, |
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265 | unsigned int crtc_w, unsigned int crtc_h, |
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266 | uint32_t x, uint32_t y, |
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267 | uint32_t src_w, uint32_t src_h); |
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268 | void (*disable_plane)(struct drm_plane *plane); |
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269 | int (*update_colorkey)(struct drm_plane *plane, |
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270 | struct drm_intel_sprite_colorkey *key); |
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271 | void (*get_colorkey)(struct drm_plane *plane, |
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272 | struct drm_intel_sprite_colorkey *key); |
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273 | }; |
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274 | |||
3031 | serge | 275 | struct intel_watermark_params { |
276 | unsigned long fifo_size; |
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277 | unsigned long max_wm; |
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278 | unsigned long default_wm; |
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279 | unsigned long guard_size; |
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280 | unsigned long cacheline_size; |
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281 | }; |
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282 | |||
283 | struct cxsr_latency { |
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284 | int is_desktop; |
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285 | int is_ddr3; |
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286 | unsigned long fsb_freq; |
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287 | unsigned long mem_freq; |
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288 | unsigned long display_sr; |
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289 | unsigned long display_hpll_disable; |
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290 | unsigned long cursor_sr; |
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291 | unsigned long cursor_hpll_disable; |
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292 | }; |
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293 | |||
2326 | Serge | 294 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
295 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
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296 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
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297 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
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2342 | Serge | 298 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
2326 | Serge | 299 | |
300 | #define DIP_HEADER_SIZE 5 |
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301 | |||
302 | #define DIP_TYPE_AVI 0x82 |
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303 | #define DIP_VERSION_AVI 0x2 |
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304 | #define DIP_LEN_AVI 13 |
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3031 | serge | 305 | #define DIP_AVI_PR_1 0 |
306 | #define DIP_AVI_PR_2 1 |
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3480 | Serge | 307 | #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
308 | #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) |
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309 | #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) |
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2326 | Serge | 310 | |
2342 | Serge | 311 | #define DIP_TYPE_SPD 0x83 |
2326 | Serge | 312 | #define DIP_VERSION_SPD 0x1 |
313 | #define DIP_LEN_SPD 25 |
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314 | #define DIP_SPD_UNKNOWN 0 |
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315 | #define DIP_SPD_DSTB 0x1 |
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316 | #define DIP_SPD_DVDP 0x2 |
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317 | #define DIP_SPD_DVHS 0x3 |
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318 | #define DIP_SPD_HDDVR 0x4 |
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319 | #define DIP_SPD_DVC 0x5 |
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320 | #define DIP_SPD_DSC 0x6 |
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321 | #define DIP_SPD_VCD 0x7 |
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322 | #define DIP_SPD_GAME 0x8 |
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323 | #define DIP_SPD_PC 0x9 |
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324 | #define DIP_SPD_BD 0xa |
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325 | #define DIP_SPD_SCD 0xb |
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326 | |||
327 | struct dip_infoframe { |
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328 | uint8_t type; /* HB0 */ |
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329 | uint8_t ver; /* HB1 */ |
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330 | uint8_t len; /* HB2 - body len, not including checksum */ |
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331 | uint8_t ecc; /* Header ECC */ |
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332 | uint8_t checksum; /* PB0 */ |
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333 | union { |
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334 | struct { |
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335 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
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336 | uint8_t Y_A_B_S; |
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337 | /* PB2 - C 7:6, M 5:4, R 3:0 */ |
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338 | uint8_t C_M_R; |
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339 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
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340 | uint8_t ITC_EC_Q_SC; |
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341 | /* PB4 - VIC 6:0 */ |
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342 | uint8_t VIC; |
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3031 | serge | 343 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
344 | uint8_t YQ_CN_PR; |
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2326 | Serge | 345 | /* PB6 to PB13 */ |
346 | uint16_t top_bar_end; |
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347 | uint16_t bottom_bar_start; |
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348 | uint16_t left_bar_end; |
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349 | uint16_t right_bar_start; |
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3031 | serge | 350 | } __attribute__ ((packed)) avi; |
2326 | Serge | 351 | struct { |
352 | uint8_t vn[8]; |
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353 | uint8_t pd[16]; |
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354 | uint8_t sdi; |
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3031 | serge | 355 | } __attribute__ ((packed)) spd; |
2326 | Serge | 356 | uint8_t payload[27]; |
357 | } __attribute__ ((packed)) body; |
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358 | } __attribute__((packed)); |
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359 | |||
3031 | serge | 360 | struct intel_hdmi { |
361 | u32 sdvox_reg; |
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362 | int ddc_bus; |
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363 | uint32_t color_range; |
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3480 | Serge | 364 | bool color_range_auto; |
3031 | serge | 365 | bool has_hdmi_sink; |
366 | bool has_audio; |
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367 | enum hdmi_force_audio force_audio; |
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3480 | Serge | 368 | bool rgb_quant_range_selectable; |
3031 | serge | 369 | void (*write_infoframe)(struct drm_encoder *encoder, |
370 | struct dip_infoframe *frame); |
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371 | void (*set_infoframes)(struct drm_encoder *encoder, |
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372 | struct drm_display_mode *adjusted_mode); |
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373 | }; |
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374 | |||
375 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
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376 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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377 | |||
378 | struct intel_dp { |
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379 | uint32_t output_reg; |
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380 | uint32_t DP; |
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381 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
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382 | bool has_audio; |
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383 | enum hdmi_force_audio force_audio; |
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384 | uint32_t color_range; |
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3480 | Serge | 385 | bool color_range_auto; |
3031 | serge | 386 | uint8_t link_bw; |
387 | uint8_t lane_count; |
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388 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
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389 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
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390 | struct i2c_adapter adapter; |
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391 | struct i2c_algo_dp_aux_data algo; |
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392 | bool is_pch_edp; |
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393 | uint8_t train_set[4]; |
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394 | int panel_power_up_delay; |
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395 | int panel_power_down_delay; |
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396 | int panel_power_cycle_delay; |
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397 | int backlight_on_delay; |
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398 | int backlight_off_delay; |
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399 | struct delayed_work panel_vdd_work; |
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400 | bool want_panel_vdd; |
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3243 | Serge | 401 | struct intel_connector *attached_connector; |
3031 | serge | 402 | }; |
403 | |||
3243 | Serge | 404 | struct intel_digital_port { |
405 | struct intel_encoder base; |
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406 | enum port port; |
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3480 | Serge | 407 | u32 port_reversal; |
3243 | Serge | 408 | struct intel_dp dp; |
409 | struct intel_hdmi hdmi; |
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410 | }; |
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411 | |||
2326 | Serge | 412 | static inline struct drm_crtc * |
413 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
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414 | { |
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415 | struct drm_i915_private *dev_priv = dev->dev_private; |
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416 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
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417 | } |
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418 | |||
419 | static inline struct drm_crtc * |
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420 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
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421 | { |
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422 | struct drm_i915_private *dev_priv = dev->dev_private; |
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423 | return dev_priv->plane_to_crtc_mapping[plane]; |
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424 | } |
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425 | |||
426 | struct intel_unpin_work { |
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2360 | Serge | 427 | struct work_struct work; |
3243 | Serge | 428 | struct drm_crtc *crtc; |
2326 | Serge | 429 | struct drm_i915_gem_object *old_fb_obj; |
430 | struct drm_i915_gem_object *pending_flip_obj; |
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431 | struct drm_pending_vblank_event *event; |
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3243 | Serge | 432 | atomic_t pending; |
433 | #define INTEL_FLIP_INACTIVE 0 |
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434 | #define INTEL_FLIP_PENDING 1 |
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435 | #define INTEL_FLIP_COMPLETE 2 |
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2326 | Serge | 436 | bool enable_stall_check; |
437 | }; |
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438 | |||
439 | struct intel_fbc_work { |
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2360 | Serge | 440 | struct delayed_work work; |
2326 | Serge | 441 | struct drm_crtc *crtc; |
442 | struct drm_framebuffer *fb; |
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443 | int interval; |
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444 | }; |
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445 | |||
3243 | Serge | 446 | int intel_pch_rawclk(struct drm_device *dev); |
447 | |||
3031 | serge | 448 | int intel_connector_update_modes(struct drm_connector *connector, |
449 | struct edid *edid); |
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2326 | Serge | 450 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
451 | |||
452 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
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453 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
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454 | |||
455 | extern void intel_crt_init(struct drm_device *dev); |
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3031 | serge | 456 | extern void intel_hdmi_init(struct drm_device *dev, |
457 | int sdvox_reg, enum port port); |
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3243 | Serge | 458 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
459 | struct intel_connector *intel_connector); |
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3031 | serge | 460 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
3243 | Serge | 461 | extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
462 | const struct drm_display_mode *mode, |
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463 | struct drm_display_mode *adjusted_mode); |
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3031 | serge | 464 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
465 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
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466 | bool is_sdvob); |
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2326 | Serge | 467 | extern void intel_dvo_init(struct drm_device *dev); |
468 | extern void intel_tv_init(struct drm_device *dev); |
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3031 | serge | 469 | extern void intel_mark_busy(struct drm_device *dev); |
3480 | Serge | 470 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
3031 | serge | 471 | extern void intel_mark_idle(struct drm_device *dev); |
2326 | Serge | 472 | extern bool intel_lvds_init(struct drm_device *dev); |
3480 | Serge | 473 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
3031 | serge | 474 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
475 | enum port port); |
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3243 | Serge | 476 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
477 | struct intel_connector *intel_connector); |
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2326 | Serge | 478 | void |
479 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
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480 | struct drm_display_mode *adjusted_mode); |
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3243 | Serge | 481 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
482 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
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483 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
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484 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
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485 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
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486 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
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487 | extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, |
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488 | const struct drm_display_mode *mode, |
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489 | struct drm_display_mode *adjusted_mode); |
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2326 | Serge | 490 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
3243 | Serge | 491 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
492 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
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493 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
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494 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
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495 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
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496 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
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2342 | Serge | 497 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
3031 | serge | 498 | extern int intel_edp_target_clock(struct intel_encoder *, |
499 | struct drm_display_mode *mode); |
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2326 | Serge | 500 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
2342 | Serge | 501 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
3031 | serge | 502 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
503 | enum plane plane); |
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2326 | Serge | 504 | |
505 | /* intel_panel.c */ |
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3243 | Serge | 506 | extern int intel_panel_init(struct intel_panel *panel, |
507 | struct drm_display_mode *fixed_mode); |
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508 | extern void intel_panel_fini(struct intel_panel *panel); |
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509 | |||
2326 | Serge | 510 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
511 | struct drm_display_mode *adjusted_mode); |
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512 | extern void intel_pch_panel_fitting(struct drm_device *dev, |
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513 | int fitting_mode, |
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3031 | serge | 514 | const struct drm_display_mode *mode, |
2326 | Serge | 515 | struct drm_display_mode *adjusted_mode); |
516 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
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517 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
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3243 | Serge | 518 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
3031 | serge | 519 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
520 | enum pipe pipe); |
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2326 | Serge | 521 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
522 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
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523 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
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524 | |||
3031 | serge | 525 | struct intel_set_config { |
526 | struct drm_encoder **save_connector_encoders; |
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527 | struct drm_crtc **save_encoder_crtcs; |
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528 | |||
529 | bool fb_changed; |
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530 | bool mode_changed; |
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531 | }; |
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532 | |||
3480 | Serge | 533 | extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
3031 | serge | 534 | int x, int y, struct drm_framebuffer *old_fb); |
535 | extern void intel_modeset_disable(struct drm_device *dev); |
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3480 | Serge | 536 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
2326 | Serge | 537 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
3031 | serge | 538 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
2326 | Serge | 539 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
3031 | serge | 540 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
541 | extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
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542 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
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543 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
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544 | extern void intel_modeset_check_state(struct drm_device *dev); |
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2326 | Serge | 545 | |
3031 | serge | 546 | |
2326 | Serge | 547 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
548 | { |
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549 | return to_intel_connector(connector)->encoder; |
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550 | } |
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551 | |||
3243 | Serge | 552 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
553 | { |
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554 | struct intel_digital_port *intel_dig_port = |
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555 | container_of(encoder, struct intel_digital_port, base.base); |
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556 | return &intel_dig_port->dp; |
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557 | } |
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558 | |||
559 | static inline struct intel_digital_port * |
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560 | enc_to_dig_port(struct drm_encoder *encoder) |
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561 | { |
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562 | return container_of(encoder, struct intel_digital_port, base.base); |
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563 | } |
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564 | |||
565 | static inline struct intel_digital_port * |
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566 | dp_to_dig_port(struct intel_dp *intel_dp) |
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567 | { |
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568 | return container_of(intel_dp, struct intel_digital_port, dp); |
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569 | } |
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570 | |||
571 | static inline struct intel_digital_port * |
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572 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
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573 | { |
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574 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
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575 | } |
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576 | |||
3480 | Serge | 577 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
578 | struct intel_digital_port *port); |
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579 | |||
2326 | Serge | 580 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
581 | struct intel_encoder *encoder); |
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582 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
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583 | |||
584 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
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585 | struct drm_crtc *crtc); |
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586 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
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587 | struct drm_file *file_priv); |
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3243 | Serge | 588 | extern enum transcoder |
589 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
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590 | enum pipe pipe); |
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2326 | Serge | 591 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
592 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
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3243 | Serge | 593 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
2326 | Serge | 594 | |
595 | struct intel_load_detect_pipe { |
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596 | struct drm_framebuffer *release_fb; |
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597 | bool load_detect_temp; |
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598 | int dpms_mode; |
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599 | }; |
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3031 | serge | 600 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 601 | struct drm_display_mode *mode, |
602 | struct intel_load_detect_pipe *old); |
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3031 | serge | 603 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 604 | struct intel_load_detect_pipe *old); |
605 | |||
606 | extern void intelfb_restore(void); |
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607 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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608 | u16 blue, int regno); |
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609 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
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610 | u16 *blue, int regno); |
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611 | extern void intel_enable_clock_gating(struct drm_device *dev); |
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612 | |||
613 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
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614 | struct drm_i915_gem_object *obj, |
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615 | struct intel_ring_buffer *pipelined); |
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3031 | serge | 616 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
2326 | Serge | 617 | |
618 | extern int intel_framebuffer_init(struct drm_device *dev, |
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619 | struct intel_framebuffer *ifb, |
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2342 | Serge | 620 | struct drm_mode_fb_cmd2 *mode_cmd, |
2326 | Serge | 621 | struct drm_i915_gem_object *obj); |
622 | extern int intel_fbdev_init(struct drm_device *dev); |
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3480 | Serge | 623 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
2326 | Serge | 624 | extern void intel_fbdev_fini(struct drm_device *dev); |
3031 | serge | 625 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
2326 | Serge | 626 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
627 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); |
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628 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
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629 | |||
630 | extern void intel_setup_overlay(struct drm_device *dev); |
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631 | extern void intel_cleanup_overlay(struct drm_device *dev); |
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632 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
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633 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
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634 | struct drm_file *file_priv); |
||
635 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, |
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636 | struct drm_file *file_priv); |
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637 | |||
638 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
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639 | extern void intel_fb_restore_mode(struct drm_device *dev); |
||
640 | |||
2342 | Serge | 641 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
642 | bool state); |
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643 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
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644 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
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645 | |||
2326 | Serge | 646 | extern void intel_init_clock_gating(struct drm_device *dev); |
2342 | Serge | 647 | extern void intel_write_eld(struct drm_encoder *encoder, |
648 | struct drm_display_mode *mode); |
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649 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
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3031 | serge | 650 | extern void intel_prepare_ddi(struct drm_device *dev); |
651 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
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652 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
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2342 | Serge | 653 | |
654 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
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3031 | serge | 655 | extern void intel_update_watermarks(struct drm_device *dev); |
2342 | Serge | 656 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
657 | uint32_t sprite_width, |
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658 | int pixel_size); |
||
3031 | serge | 659 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
660 | struct drm_display_mode *mode); |
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2342 | Serge | 661 | |
3480 | Serge | 662 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
663 | unsigned int tiling_mode, |
||
3243 | Serge | 664 | unsigned int bpp, |
665 | unsigned int pitch); |
||
666 | |||
2342 | Serge | 667 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
668 | struct drm_file *file_priv); |
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669 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
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670 | struct drm_file *file_priv); |
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671 | |||
3031 | serge | 672 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
673 | |||
674 | /* Power-related functions, located in intel_pm.c */ |
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675 | extern void intel_init_pm(struct drm_device *dev); |
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676 | /* FBC */ |
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677 | extern bool intel_fbc_enabled(struct drm_device *dev); |
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678 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
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679 | extern void intel_update_fbc(struct drm_device *dev); |
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680 | /* IPS */ |
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681 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
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682 | extern void intel_gpu_ips_teardown(void); |
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683 | |||
3480 | Serge | 684 | extern void intel_init_power_well(struct drm_device *dev); |
685 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
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3031 | serge | 686 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
687 | extern void intel_disable_gt_powersave(struct drm_device *dev); |
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688 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
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689 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
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690 | |||
691 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
||
692 | enum pipe *pipe); |
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3243 | Serge | 693 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
694 | extern void intel_ddi_pll_init(struct drm_device *dev); |
||
695 | extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); |
||
696 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
||
697 | enum transcoder cpu_transcoder); |
||
698 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
||
699 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
||
700 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
||
701 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
||
702 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
||
703 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
||
704 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
||
705 | extern bool |
||
706 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
||
707 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
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3031 | serge | 708 | |
2326 | Serge | 709 | #endif /* __INTEL_DRV_H__ */><>><>><>><> |