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2326 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright (c) 2007-2008 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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23 | * IN THE SOFTWARE. |
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24 | */ |
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25 | #ifndef __INTEL_DRV_H__ |
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26 | #define __INTEL_DRV_H__ |
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27 | |||
28 | #include |
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3031 | serge | 29 | #include |
2326 | Serge | 30 | #include "i915_drv.h" |
3031 | serge | 31 | #include |
32 | #include |
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33 | #include |
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34 | #include |
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2326 | Serge | 35 | |
3031 | serge | 36 | #define cpu_relax() asm volatile("rep; nop") |
37 | |||
2326 | Serge | 38 | #define _wait_for(COND, MS, W) ({ \ |
3031 | serge | 39 | unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
2326 | Serge | 40 | int ret__ = 0; \ |
2342 | Serge | 41 | while (!(COND)) { \ |
3031 | serge | 42 | if (time_after(GetTimerTicks(), timeout__)) { \ |
2326 | Serge | 43 | ret__ = -ETIMEDOUT; \ |
44 | break; \ |
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45 | } \ |
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3031 | serge | 46 | if (W ) { \ |
47 | msleep(W); \ |
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48 | } else { \ |
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49 | cpu_relax(); \ |
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50 | } \ |
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2326 | Serge | 51 | } \ |
52 | ret__; \ |
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53 | }) |
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54 | |||
3031 | serge | 55 | #define wait_for_atomic_us(COND, US) ({ \ |
56 | unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US); \ |
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57 | int ret__ = 0; \ |
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58 | while (!(COND)) { \ |
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59 | if (time_after(GetTimerTicks(), timeout__)) { \ |
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60 | ret__ = -ETIMEDOUT; \ |
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61 | break; \ |
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62 | } \ |
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63 | cpu_relax(); \ |
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64 | } \ |
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65 | ret__; \ |
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66 | }) |
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67 | |||
2326 | Serge | 68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
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70 | |||
71 | #define MSLEEP(x) do { \ |
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72 | if (in_dbg_master()) \ |
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73 | mdelay(x); \ |
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74 | else \ |
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75 | msleep(x); \ |
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76 | } while(0) |
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77 | |||
78 | #define KHz(x) (1000*x) |
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79 | #define MHz(x) KHz(1000*x) |
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80 | |||
81 | /* |
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82 | * Display related stuff |
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83 | */ |
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84 | |||
85 | /* store information about an Ixxx DVO */ |
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86 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
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87 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
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88 | #define MAX_OUTPUTS 6 |
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89 | /* maximum connectors per crtcs in the mode set */ |
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90 | #define INTELFB_CONN_LIMIT 4 |
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91 | |||
92 | #define INTEL_I2C_BUS_DVO 1 |
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93 | #define INTEL_I2C_BUS_SDVO 2 |
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94 | |||
95 | /* these are outputs from the chip - integrated only |
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96 | external chips are via DVO or SDVO output */ |
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97 | #define INTEL_OUTPUT_UNUSED 0 |
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98 | #define INTEL_OUTPUT_ANALOG 1 |
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99 | #define INTEL_OUTPUT_DVO 2 |
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100 | #define INTEL_OUTPUT_SDVO 3 |
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101 | #define INTEL_OUTPUT_LVDS 4 |
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102 | #define INTEL_OUTPUT_TVOUT 5 |
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103 | #define INTEL_OUTPUT_HDMI 6 |
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104 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
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105 | #define INTEL_OUTPUT_EDP 8 |
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3243 | Serge | 106 | #define INTEL_OUTPUT_UNKNOWN 9 |
2326 | Serge | 107 | |
108 | #define INTEL_DVO_CHIP_NONE 0 |
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109 | #define INTEL_DVO_CHIP_LVDS 1 |
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110 | #define INTEL_DVO_CHIP_TMDS 2 |
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111 | #define INTEL_DVO_CHIP_TVOUT 4 |
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112 | |||
113 | /* drm_display_mode->private_flags */ |
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114 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) |
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115 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) |
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2342 | Serge | 116 | #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
3031 | serge | 117 | /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
118 | * timings in the mode to prevent the crtc fixup from overwriting them. |
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119 | * Currently only lvds needs that. */ |
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120 | #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) |
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2326 | Serge | 121 | |
122 | static inline void |
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123 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, |
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124 | int multiplier) |
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125 | { |
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126 | mode->clock *= multiplier; |
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127 | mode->private_flags |= multiplier; |
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128 | } |
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129 | |||
130 | static inline int |
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131 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) |
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132 | { |
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133 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; |
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134 | } |
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135 | |||
136 | struct intel_framebuffer { |
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137 | struct drm_framebuffer base; |
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138 | struct drm_i915_gem_object *obj; |
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139 | }; |
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140 | |||
141 | struct intel_fbdev { |
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142 | struct drm_fb_helper helper; |
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143 | struct intel_framebuffer ifb; |
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144 | struct list_head fbdev_list; |
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145 | struct drm_display_mode *our_mode; |
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146 | }; |
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147 | |||
148 | struct intel_encoder { |
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149 | struct drm_encoder base; |
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3031 | serge | 150 | /* |
151 | * The new crtc this encoder will be driven from. Only differs from |
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152 | * base->crtc while a modeset is in progress. |
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153 | */ |
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154 | struct intel_crtc *new_crtc; |
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155 | |||
2326 | Serge | 156 | int type; |
157 | bool needs_tv_clock; |
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3031 | serge | 158 | /* |
159 | * Intel hw has only one MUX where encoders could be clone, hence a |
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160 | * simple flag is enough to compute the possible_clones mask. |
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161 | */ |
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162 | bool cloneable; |
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163 | bool connectors_active; |
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2326 | Serge | 164 | void (*hot_plug)(struct intel_encoder *); |
3031 | serge | 165 | void (*pre_enable)(struct intel_encoder *); |
166 | void (*enable)(struct intel_encoder *); |
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167 | void (*disable)(struct intel_encoder *); |
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168 | void (*post_disable)(struct intel_encoder *); |
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169 | /* Read out the current hw state of this connector, returning true if |
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170 | * the encoder is active. If the encoder is enabled it also set the pipe |
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171 | * it is connected to in the pipe parameter. */ |
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172 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
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2326 | Serge | 173 | int crtc_mask; |
174 | }; |
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175 | |||
3243 | Serge | 176 | struct intel_panel { |
177 | struct drm_display_mode *fixed_mode; |
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178 | int fitting_mode; |
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179 | }; |
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180 | |||
2326 | Serge | 181 | struct intel_connector { |
182 | struct drm_connector base; |
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3031 | serge | 183 | /* |
184 | * The fixed encoder this connector is connected to. |
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185 | */ |
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2326 | Serge | 186 | struct intel_encoder *encoder; |
3031 | serge | 187 | |
188 | /* |
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189 | * The new encoder this connector will be driven. Only differs from |
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190 | * encoder while a modeset is in progress. |
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191 | */ |
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192 | struct intel_encoder *new_encoder; |
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193 | |||
194 | /* Reads out the current hw, returning true if the connector is enabled |
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195 | * and active (i.e. dpms ON state). */ |
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196 | bool (*get_hw_state)(struct intel_connector *); |
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3243 | Serge | 197 | |
198 | /* Panel info for eDP and LVDS */ |
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199 | struct intel_panel panel; |
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200 | |||
201 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
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202 | struct edid *edid; |
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2326 | Serge | 203 | }; |
204 | |||
205 | struct intel_crtc { |
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206 | struct drm_crtc base; |
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207 | enum pipe pipe; |
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208 | enum plane plane; |
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3243 | Serge | 209 | enum transcoder cpu_transcoder; |
2326 | Serge | 210 | u8 lut_r[256], lut_g[256], lut_b[256]; |
3031 | serge | 211 | /* |
212 | * Whether the crtc and the connected output pipeline is active. Implies |
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213 | * that crtc->enabled is set, i.e. the current mode configuration has |
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214 | * some outputs connected to this crtc. |
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215 | */ |
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216 | bool active; |
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217 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
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2326 | Serge | 218 | bool lowfreq_avail; |
219 | struct intel_overlay *overlay; |
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220 | struct intel_unpin_work *unpin_work; |
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221 | int fdi_lanes; |
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222 | |||
3243 | Serge | 223 | atomic_t unpin_work_count; |
224 | |||
3031 | serge | 225 | /* Display surface base address adjustement for pageflips. Note that on |
226 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
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227 | * handled in the hw itself (with the TILEOFF register). */ |
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228 | unsigned long dspaddr_offset; |
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229 | |||
2326 | Serge | 230 | struct drm_i915_gem_object *cursor_bo; |
231 | uint32_t cursor_addr; |
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232 | int16_t cursor_x, cursor_y; |
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233 | int16_t cursor_width, cursor_height; |
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234 | bool cursor_visible; |
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235 | unsigned int bpp; |
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2342 | Serge | 236 | |
3031 | serge | 237 | /* We can share PLLs across outputs if the timings match */ |
238 | struct intel_pch_pll *pch_pll; |
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3243 | Serge | 239 | uint32_t ddi_pll_sel; |
2326 | Serge | 240 | }; |
241 | |||
2342 | Serge | 242 | struct intel_plane { |
243 | struct drm_plane base; |
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244 | enum pipe pipe; |
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245 | struct drm_i915_gem_object *obj; |
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3243 | Serge | 246 | bool can_scale; |
2342 | Serge | 247 | int max_downscale; |
248 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
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249 | void (*update_plane)(struct drm_plane *plane, |
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250 | struct drm_framebuffer *fb, |
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251 | struct drm_i915_gem_object *obj, |
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252 | int crtc_x, int crtc_y, |
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253 | unsigned int crtc_w, unsigned int crtc_h, |
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254 | uint32_t x, uint32_t y, |
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255 | uint32_t src_w, uint32_t src_h); |
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256 | void (*disable_plane)(struct drm_plane *plane); |
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257 | int (*update_colorkey)(struct drm_plane *plane, |
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258 | struct drm_intel_sprite_colorkey *key); |
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259 | void (*get_colorkey)(struct drm_plane *plane, |
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260 | struct drm_intel_sprite_colorkey *key); |
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261 | }; |
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262 | |||
3031 | serge | 263 | struct intel_watermark_params { |
264 | unsigned long fifo_size; |
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265 | unsigned long max_wm; |
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266 | unsigned long default_wm; |
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267 | unsigned long guard_size; |
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268 | unsigned long cacheline_size; |
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269 | }; |
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270 | |||
271 | struct cxsr_latency { |
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272 | int is_desktop; |
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273 | int is_ddr3; |
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274 | unsigned long fsb_freq; |
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275 | unsigned long mem_freq; |
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276 | unsigned long display_sr; |
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277 | unsigned long display_hpll_disable; |
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278 | unsigned long cursor_sr; |
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279 | unsigned long cursor_hpll_disable; |
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280 | }; |
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281 | |||
2326 | Serge | 282 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
283 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
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284 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
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285 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
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2342 | Serge | 286 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
2326 | Serge | 287 | |
288 | #define DIP_HEADER_SIZE 5 |
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289 | |||
290 | #define DIP_TYPE_AVI 0x82 |
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291 | #define DIP_VERSION_AVI 0x2 |
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292 | #define DIP_LEN_AVI 13 |
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3031 | serge | 293 | #define DIP_AVI_PR_1 0 |
294 | #define DIP_AVI_PR_2 1 |
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2326 | Serge | 295 | |
2342 | Serge | 296 | #define DIP_TYPE_SPD 0x83 |
2326 | Serge | 297 | #define DIP_VERSION_SPD 0x1 |
298 | #define DIP_LEN_SPD 25 |
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299 | #define DIP_SPD_UNKNOWN 0 |
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300 | #define DIP_SPD_DSTB 0x1 |
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301 | #define DIP_SPD_DVDP 0x2 |
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302 | #define DIP_SPD_DVHS 0x3 |
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303 | #define DIP_SPD_HDDVR 0x4 |
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304 | #define DIP_SPD_DVC 0x5 |
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305 | #define DIP_SPD_DSC 0x6 |
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306 | #define DIP_SPD_VCD 0x7 |
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307 | #define DIP_SPD_GAME 0x8 |
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308 | #define DIP_SPD_PC 0x9 |
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309 | #define DIP_SPD_BD 0xa |
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310 | #define DIP_SPD_SCD 0xb |
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311 | |||
312 | struct dip_infoframe { |
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313 | uint8_t type; /* HB0 */ |
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314 | uint8_t ver; /* HB1 */ |
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315 | uint8_t len; /* HB2 - body len, not including checksum */ |
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316 | uint8_t ecc; /* Header ECC */ |
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317 | uint8_t checksum; /* PB0 */ |
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318 | union { |
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319 | struct { |
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320 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
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321 | uint8_t Y_A_B_S; |
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322 | /* PB2 - C 7:6, M 5:4, R 3:0 */ |
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323 | uint8_t C_M_R; |
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324 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
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325 | uint8_t ITC_EC_Q_SC; |
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326 | /* PB4 - VIC 6:0 */ |
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327 | uint8_t VIC; |
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3031 | serge | 328 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
329 | uint8_t YQ_CN_PR; |
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2326 | Serge | 330 | /* PB6 to PB13 */ |
331 | uint16_t top_bar_end; |
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332 | uint16_t bottom_bar_start; |
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333 | uint16_t left_bar_end; |
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334 | uint16_t right_bar_start; |
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3031 | serge | 335 | } __attribute__ ((packed)) avi; |
2326 | Serge | 336 | struct { |
337 | uint8_t vn[8]; |
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338 | uint8_t pd[16]; |
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339 | uint8_t sdi; |
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3031 | serge | 340 | } __attribute__ ((packed)) spd; |
2326 | Serge | 341 | uint8_t payload[27]; |
342 | } __attribute__ ((packed)) body; |
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343 | } __attribute__((packed)); |
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344 | |||
3031 | serge | 345 | struct intel_hdmi { |
346 | u32 sdvox_reg; |
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347 | int ddc_bus; |
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348 | uint32_t color_range; |
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349 | bool has_hdmi_sink; |
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350 | bool has_audio; |
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351 | enum hdmi_force_audio force_audio; |
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352 | void (*write_infoframe)(struct drm_encoder *encoder, |
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353 | struct dip_infoframe *frame); |
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354 | void (*set_infoframes)(struct drm_encoder *encoder, |
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355 | struct drm_display_mode *adjusted_mode); |
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356 | }; |
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357 | |||
358 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
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359 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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360 | |||
361 | struct intel_dp { |
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362 | uint32_t output_reg; |
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363 | uint32_t DP; |
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364 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
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365 | bool has_audio; |
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366 | enum hdmi_force_audio force_audio; |
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367 | uint32_t color_range; |
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368 | uint8_t link_bw; |
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369 | uint8_t lane_count; |
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370 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
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371 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
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372 | struct i2c_adapter adapter; |
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373 | struct i2c_algo_dp_aux_data algo; |
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374 | bool is_pch_edp; |
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375 | uint8_t train_set[4]; |
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376 | int panel_power_up_delay; |
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377 | int panel_power_down_delay; |
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378 | int panel_power_cycle_delay; |
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379 | int backlight_on_delay; |
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380 | int backlight_off_delay; |
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381 | struct delayed_work panel_vdd_work; |
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382 | bool want_panel_vdd; |
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3243 | Serge | 383 | struct intel_connector *attached_connector; |
3031 | serge | 384 | }; |
385 | |||
3243 | Serge | 386 | struct intel_digital_port { |
387 | struct intel_encoder base; |
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388 | enum port port; |
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389 | struct intel_dp dp; |
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390 | struct intel_hdmi hdmi; |
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391 | }; |
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392 | |||
2326 | Serge | 393 | static inline struct drm_crtc * |
394 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
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395 | { |
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396 | struct drm_i915_private *dev_priv = dev->dev_private; |
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397 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
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398 | } |
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399 | |||
400 | static inline struct drm_crtc * |
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401 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
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402 | { |
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403 | struct drm_i915_private *dev_priv = dev->dev_private; |
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404 | return dev_priv->plane_to_crtc_mapping[plane]; |
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405 | } |
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406 | |||
407 | struct intel_unpin_work { |
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2360 | Serge | 408 | struct work_struct work; |
3243 | Serge | 409 | struct drm_crtc *crtc; |
2326 | Serge | 410 | struct drm_i915_gem_object *old_fb_obj; |
411 | struct drm_i915_gem_object *pending_flip_obj; |
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412 | struct drm_pending_vblank_event *event; |
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3243 | Serge | 413 | atomic_t pending; |
414 | #define INTEL_FLIP_INACTIVE 0 |
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415 | #define INTEL_FLIP_PENDING 1 |
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416 | #define INTEL_FLIP_COMPLETE 2 |
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2326 | Serge | 417 | bool enable_stall_check; |
418 | }; |
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419 | |||
420 | struct intel_fbc_work { |
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2360 | Serge | 421 | struct delayed_work work; |
2326 | Serge | 422 | struct drm_crtc *crtc; |
423 | struct drm_framebuffer *fb; |
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424 | int interval; |
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425 | }; |
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426 | |||
3243 | Serge | 427 | int intel_pch_rawclk(struct drm_device *dev); |
428 | |||
3031 | serge | 429 | int intel_connector_update_modes(struct drm_connector *connector, |
430 | struct edid *edid); |
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2326 | Serge | 431 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
432 | |||
433 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
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434 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
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435 | |||
436 | extern void intel_crt_init(struct drm_device *dev); |
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3031 | serge | 437 | extern void intel_hdmi_init(struct drm_device *dev, |
438 | int sdvox_reg, enum port port); |
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3243 | Serge | 439 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
440 | struct intel_connector *intel_connector); |
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3031 | serge | 441 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
3243 | Serge | 442 | extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
443 | const struct drm_display_mode *mode, |
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444 | struct drm_display_mode *adjusted_mode); |
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3031 | serge | 445 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
446 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
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447 | bool is_sdvob); |
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2326 | Serge | 448 | extern void intel_dvo_init(struct drm_device *dev); |
449 | extern void intel_tv_init(struct drm_device *dev); |
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3031 | serge | 450 | extern void intel_mark_busy(struct drm_device *dev); |
451 | extern void intel_mark_idle(struct drm_device *dev); |
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452 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
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453 | extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj); |
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2326 | Serge | 454 | extern bool intel_lvds_init(struct drm_device *dev); |
3031 | serge | 455 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
456 | enum port port); |
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3243 | Serge | 457 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
458 | struct intel_connector *intel_connector); |
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2326 | Serge | 459 | void |
460 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
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461 | struct drm_display_mode *adjusted_mode); |
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3243 | Serge | 462 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
463 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
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464 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
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465 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
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466 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
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467 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
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468 | extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, |
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469 | const struct drm_display_mode *mode, |
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470 | struct drm_display_mode *adjusted_mode); |
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2326 | Serge | 471 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
3243 | Serge | 472 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
473 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
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474 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
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475 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
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476 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
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477 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
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2342 | Serge | 478 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
3031 | serge | 479 | extern int intel_edp_target_clock(struct intel_encoder *, |
480 | struct drm_display_mode *mode); |
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2326 | Serge | 481 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
2342 | Serge | 482 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
3031 | serge | 483 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
484 | enum plane plane); |
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2326 | Serge | 485 | |
486 | /* intel_panel.c */ |
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3243 | Serge | 487 | extern int intel_panel_init(struct intel_panel *panel, |
488 | struct drm_display_mode *fixed_mode); |
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489 | extern void intel_panel_fini(struct intel_panel *panel); |
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490 | |||
2326 | Serge | 491 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
492 | struct drm_display_mode *adjusted_mode); |
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493 | extern void intel_pch_panel_fitting(struct drm_device *dev, |
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494 | int fitting_mode, |
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3031 | serge | 495 | const struct drm_display_mode *mode, |
2326 | Serge | 496 | struct drm_display_mode *adjusted_mode); |
497 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
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498 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
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3243 | Serge | 499 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
3031 | serge | 500 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
501 | enum pipe pipe); |
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2326 | Serge | 502 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
503 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
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504 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
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505 | |||
3031 | serge | 506 | struct intel_set_config { |
507 | struct drm_encoder **save_connector_encoders; |
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508 | struct drm_crtc **save_encoder_crtcs; |
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509 | |||
510 | bool fb_changed; |
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511 | bool mode_changed; |
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512 | }; |
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513 | |||
514 | extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
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515 | int x, int y, struct drm_framebuffer *old_fb); |
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516 | extern void intel_modeset_disable(struct drm_device *dev); |
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2326 | Serge | 517 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
3031 | serge | 518 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
519 | extern void intel_encoder_noop(struct drm_encoder *encoder); |
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2326 | Serge | 520 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
3031 | serge | 521 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
522 | extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
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523 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
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524 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
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525 | extern void intel_modeset_check_state(struct drm_device *dev); |
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2326 | Serge | 526 | |
3031 | serge | 527 | |
2326 | Serge | 528 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
529 | { |
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530 | return to_intel_connector(connector)->encoder; |
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531 | } |
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532 | |||
3243 | Serge | 533 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
534 | { |
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535 | struct intel_digital_port *intel_dig_port = |
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536 | container_of(encoder, struct intel_digital_port, base.base); |
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537 | return &intel_dig_port->dp; |
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538 | } |
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539 | |||
540 | static inline struct intel_digital_port * |
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541 | enc_to_dig_port(struct drm_encoder *encoder) |
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542 | { |
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543 | return container_of(encoder, struct intel_digital_port, base.base); |
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544 | } |
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545 | |||
546 | static inline struct intel_digital_port * |
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547 | dp_to_dig_port(struct intel_dp *intel_dp) |
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548 | { |
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549 | return container_of(intel_dp, struct intel_digital_port, dp); |
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550 | } |
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551 | |||
552 | static inline struct intel_digital_port * |
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553 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
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554 | { |
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555 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
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556 | } |
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557 | |||
2326 | Serge | 558 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
559 | struct intel_encoder *encoder); |
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560 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
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561 | |||
562 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
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563 | struct drm_crtc *crtc); |
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564 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
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565 | struct drm_file *file_priv); |
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3243 | Serge | 566 | extern enum transcoder |
567 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
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568 | enum pipe pipe); |
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2326 | Serge | 569 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
570 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
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3243 | Serge | 571 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
2326 | Serge | 572 | |
573 | struct intel_load_detect_pipe { |
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574 | struct drm_framebuffer *release_fb; |
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575 | bool load_detect_temp; |
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576 | int dpms_mode; |
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577 | }; |
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3031 | serge | 578 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 579 | struct drm_display_mode *mode, |
580 | struct intel_load_detect_pipe *old); |
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3031 | serge | 581 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
2326 | Serge | 582 | struct intel_load_detect_pipe *old); |
583 | |||
584 | extern void intelfb_restore(void); |
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585 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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586 | u16 blue, int regno); |
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587 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
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588 | u16 *blue, int regno); |
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589 | extern void intel_enable_clock_gating(struct drm_device *dev); |
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590 | |||
591 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
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592 | struct drm_i915_gem_object *obj, |
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593 | struct intel_ring_buffer *pipelined); |
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3031 | serge | 594 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
2326 | Serge | 595 | |
596 | extern int intel_framebuffer_init(struct drm_device *dev, |
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597 | struct intel_framebuffer *ifb, |
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2342 | Serge | 598 | struct drm_mode_fb_cmd2 *mode_cmd, |
2326 | Serge | 599 | struct drm_i915_gem_object *obj); |
600 | extern int intel_fbdev_init(struct drm_device *dev); |
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601 | extern void intel_fbdev_fini(struct drm_device *dev); |
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3031 | serge | 602 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
2326 | Serge | 603 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
604 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); |
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605 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
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606 | |||
607 | extern void intel_setup_overlay(struct drm_device *dev); |
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608 | extern void intel_cleanup_overlay(struct drm_device *dev); |
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609 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
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610 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
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611 | struct drm_file *file_priv); |
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612 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, |
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613 | struct drm_file *file_priv); |
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614 | |||
615 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
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616 | extern void intel_fb_restore_mode(struct drm_device *dev); |
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617 | |||
2342 | Serge | 618 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
619 | bool state); |
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620 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
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621 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
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622 | |||
2326 | Serge | 623 | extern void intel_init_clock_gating(struct drm_device *dev); |
2342 | Serge | 624 | extern void intel_write_eld(struct drm_encoder *encoder, |
625 | struct drm_display_mode *mode); |
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626 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
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3031 | serge | 627 | extern void intel_prepare_ddi(struct drm_device *dev); |
628 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
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629 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
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2342 | Serge | 630 | |
631 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
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3031 | serge | 632 | extern void intel_update_watermarks(struct drm_device *dev); |
2342 | Serge | 633 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
634 | uint32_t sprite_width, |
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635 | int pixel_size); |
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3031 | serge | 636 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
637 | struct drm_display_mode *mode); |
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2342 | Serge | 638 | |
3243 | Serge | 639 | extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, |
640 | unsigned int bpp, |
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641 | unsigned int pitch); |
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642 | |||
2342 | Serge | 643 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
644 | struct drm_file *file_priv); |
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645 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
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646 | struct drm_file *file_priv); |
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647 | |||
3031 | serge | 648 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
649 | |||
650 | /* Power-related functions, located in intel_pm.c */ |
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651 | extern void intel_init_pm(struct drm_device *dev); |
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652 | /* FBC */ |
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653 | extern bool intel_fbc_enabled(struct drm_device *dev); |
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654 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
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655 | extern void intel_update_fbc(struct drm_device *dev); |
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656 | /* IPS */ |
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657 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
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658 | extern void intel_gpu_ips_teardown(void); |
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659 | |||
660 | extern void intel_init_power_wells(struct drm_device *dev); |
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661 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
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662 | extern void intel_disable_gt_powersave(struct drm_device *dev); |
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663 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
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664 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
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665 | |||
666 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
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667 | enum pipe *pipe); |
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3243 | Serge | 668 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
669 | extern void intel_ddi_pll_init(struct drm_device *dev); |
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670 | extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); |
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671 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
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672 | enum transcoder cpu_transcoder); |
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673 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
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674 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
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675 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
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676 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
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677 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
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678 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
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679 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
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680 | extern bool |
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681 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
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682 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
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3031 | serge | 683 | |
2326 | Serge | 684 | #endif /* __INTEL_DRV_H__ */><> |