WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_dp.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Keith Packard
		25	*
		26	*/
		27
		28	#include
2330	Serge	29	#include
3031	serge	30	#include
		31	#include
		32	#include
		33	#include
		34	#include
2327	Serge	35	#include "intel_drv.h"
3031	serge	36	#include
2327	Serge	37	#include "i915_drv.h"
		38
5060	serge	39	#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
2327	Serge	40
4560	Serge	41	struct dp_link_dpll {
		42	int link_bw;
		43	struct dpll dpll;
		44	};
		45
		46	static const struct dp_link_dpll gen4_dpll[] = {
		47	{ DP_LINK_BW_1_62,
		48	{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
		49	{ DP_LINK_BW_2_7,
		50	{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
		51	};
		52
		53	static const struct dp_link_dpll pch_dpll[] = {
		54	{ DP_LINK_BW_1_62,
		55	{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
		56	{ DP_LINK_BW_2_7,
		57	{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
		58	};
		59
		60	static const struct dp_link_dpll vlv_dpll[] = {
		61	{ DP_LINK_BW_1_62,
		62	{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
		63	{ DP_LINK_BW_2_7,
		64	{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
		65	};
		66
5060	serge	67	/*
		68	* CHV supports eDP 1.4 that have more link rates.
		69	* Below only provides the fixed rate but exclude variable rate.
		70	*/
		71	static const struct dp_link_dpll chv_dpll[] = {
		72	/*
		73	* CHV requires to program fractional division for m2.
		74	* m2 is stored in fixed point format using formula below
		75	* (m2_int << 22) \| m2_fraction
		76	*/
		77	{ DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
		78	{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
		79	{ DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
		80	{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
		81	{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
		82	{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
		83	};
		84
2327	Serge	85	/**
		86	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
		87	* @intel_dp: DP struct
		88	*
		89	* If a CPU or PCH DP output is attached to an eDP panel, this function
		90	* will return true, and false otherwise.
		91	*/
		92	static bool is_edp(struct intel_dp *intel_dp)
		93	{
3243	Serge	94	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		95
		96	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
2327	Serge	97	}
		98
3243	Serge	99	static struct drm_device intel_dp_to_dev(struct intel_dp intel_dp)
2327	Serge	100	{
3243	Serge	101	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		102
		103	return intel_dig_port->base.base.dev;
2327	Serge	104	}
		105
2330	Serge	106	static struct intel_dp intel_attached_dp(struct drm_connector connector)
		107	{
3243	Serge	108	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
2330	Serge	109	}
2327	Serge	110
2330	Serge	111	static void intel_dp_link_down(struct intel_dp *intel_dp);
5060	serge	112	static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
		113	static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
2330	Serge	114
5060	serge	115	int
2330	Serge	116	intel_dp_max_link_bw(struct intel_dp *intel_dp)
		117	{
		118	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
5060	serge	119	struct drm_device *dev = intel_dp->attached_connector->base.dev;
2327	Serge	120
2330	Serge	121	switch (max_link_bw) {
		122	case DP_LINK_BW_1_62:
		123	case DP_LINK_BW_2_7:
		124	break;
4104	Serge	125	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
5060	serge	126	if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) \|\|
		127	INTEL_INFO(dev)->gen >= 8) &&
		128	intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
		129	max_link_bw = DP_LINK_BW_5_4;
		130	else
		131	max_link_bw = DP_LINK_BW_2_7;
4104	Serge	132	break;
2330	Serge	133	default:
4104	Serge	134	WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		135	max_link_bw);
2330	Serge	136	max_link_bw = DP_LINK_BW_1_62;
		137	break;
		138	}
		139	return max_link_bw;
		140	}
2327	Serge	141
5060	serge	142	static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
		143	{
		144	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		145	struct drm_device *dev = intel_dig_port->base.base.dev;
		146	u8 source_max, sink_max;
		147
		148	source_max = 4;
		149	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
		150	(intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		151	source_max = 2;
		152
		153	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
		154
		155	return min(source_max, sink_max);
		156	}
		157
2342	Serge	158	/*
		159	* The units on the numbers in the next two are... bizarre. Examples will
		160	* make it clearer; this one parallels an example in the eDP spec.
		161	*
		162	* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
		163	*
		164	* 270000 * 1 * 8 / 10 == 216000
		165	*
		166	* The actual data capacity of that configuration is 2.16Gbit/s, so the
		167	* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
		168	* or equivalently, kilopixels per second - so for 1680x1050R it'd be
		169	* 119000. At 18bpp that's 2142000 kilobits per second.
		170	*
		171	* Thus the strange-looking division by 10 in intel_dp_link_required, to
		172	* get the result in decakilobits instead of kilobits.
		173	*/
		174
2330	Serge	175	static int
2351	Serge	176	intel_dp_link_required(int pixel_clock, int bpp)
2330	Serge	177	{
2342	Serge	178	return (pixel_clock * bpp + 9) / 10;
2330	Serge	179	}
2327	Serge	180
2330	Serge	181	static int
		182	intel_dp_max_data_rate(int max_link_clock, int max_lanes)
		183	{
		184	return (max_link_clock * max_lanes * 8) / 10;
		185	}
2327	Serge	186
4560	Serge	187	static enum drm_mode_status
2330	Serge	188	intel_dp_mode_valid(struct drm_connector *connector,
		189	struct drm_display_mode *mode)
		190	{
		191	struct intel_dp *intel_dp = intel_attached_dp(connector);
3243	Serge	192	struct intel_connector *intel_connector = to_intel_connector(connector);
		193	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
3746	Serge	194	int target_clock = mode->clock;
		195	int max_rate, mode_rate, max_lanes, max_link_clock;
2327	Serge	196
3243	Serge	197	if (is_edp(intel_dp) && fixed_mode) {
		198	if (mode->hdisplay > fixed_mode->hdisplay)
2330	Serge	199	return MODE_PANEL;
2327	Serge	200
3243	Serge	201	if (mode->vdisplay > fixed_mode->vdisplay)
2330	Serge	202	return MODE_PANEL;
3746	Serge	203
		204	target_clock = fixed_mode->clock;
2330	Serge	205	}
2327	Serge	206
3746	Serge	207	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
5060	serge	208	max_lanes = intel_dp_max_lane_count(intel_dp);
3746	Serge	209
		210	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
		211	mode_rate = intel_dp_link_required(target_clock, 18);
		212
		213	if (mode_rate > max_rate)
2330	Serge	214	return MODE_CLOCK_HIGH;
2327	Serge	215
2330	Serge	216	if (mode->clock < 10000)
		217	return MODE_CLOCK_LOW;
		218
3031	serge	219	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		220	return MODE_H_ILLEGAL;
		221
2330	Serge	222	return MODE_OK;
		223	}
		224
		225	static uint32_t
		226	pack_aux(uint8_t *src, int src_bytes)
		227	{
		228	int i;
		229	uint32_t v = 0;
		230
		231	if (src_bytes > 4)
		232	src_bytes = 4;
		233	for (i = 0; i < src_bytes; i++)
		234	v \|= ((uint32_t) src[i]) << ((3-i) * 8);
		235	return v;
		236	}
		237
		238	static void
		239	unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
		240	{
		241	int i;
		242	if (dst_bytes > 4)
		243	dst_bytes = 4;
		244	for (i = 0; i < dst_bytes; i++)
		245	dst[i] = src >> ((3-i) * 8);
		246	}
		247
		248	/* hrawclock is 1/4 the FSB frequency */
		249	static int
		250	intel_hrawclk(struct drm_device *dev)
		251	{
		252	struct drm_i915_private *dev_priv = dev->dev_private;
		253	uint32_t clkcfg;
		254
3243	Serge	255	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
		256	if (IS_VALLEYVIEW(dev))
		257	return 200;
		258
2330	Serge	259	clkcfg = I915_READ(CLKCFG);
		260	switch (clkcfg & CLKCFG_FSB_MASK) {
		261	case CLKCFG_FSB_400:
		262	return 100;
		263	case CLKCFG_FSB_533:
		264	return 133;
		265	case CLKCFG_FSB_667:
		266	return 166;
		267	case CLKCFG_FSB_800:
		268	return 200;
		269	case CLKCFG_FSB_1067:
		270	return 266;
		271	case CLKCFG_FSB_1333:
		272	return 333;
		273	/* these two are just a guess; one of them might be right */
		274	case CLKCFG_FSB_1600:
		275	case CLKCFG_FSB_1600_ALT:
		276	return 400;
		277	default:
		278	return 133;
		279	}
		280	}
		281
4560	Serge	282	static void
		283	intel_dp_init_panel_power_sequencer(struct drm_device *dev,
		284	struct intel_dp *intel_dp,
		285	struct edp_power_seq *out);
		286	static void
		287	intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
		288	struct intel_dp *intel_dp,
		289	struct edp_power_seq *out);
		290
		291	static enum pipe
		292	vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
		293	{
		294	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		295	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		296	struct drm_device *dev = intel_dig_port->base.base.dev;
		297	struct drm_i915_private *dev_priv = dev->dev_private;
		298	enum port port = intel_dig_port->port;
		299	enum pipe pipe;
		300
		301	/* modeset should have pipe */
		302	if (crtc)
		303	return to_intel_crtc(crtc)->pipe;
		304
		305	/* init time, try to find a pipe with this port selected */
		306	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		307	u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
		308	PANEL_PORT_SELECT_MASK;
		309	if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
		310	return pipe;
		311	if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
		312	return pipe;
		313	}
		314
		315	/* shrug */
		316	return PIPE_A;
		317	}
		318
		319	static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
		320	{
		321	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		322
		323	if (HAS_PCH_SPLIT(dev))
		324	return PCH_PP_CONTROL;
		325	else
		326	return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
		327	}
		328
		329	static u32 _pp_stat_reg(struct intel_dp *intel_dp)
		330	{
		331	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		332
		333	if (HAS_PCH_SPLIT(dev))
		334	return PCH_PP_STATUS;
		335	else
		336	return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
		337	}
		338
5060	serge	339
		340	static bool edp_have_panel_power(struct intel_dp *intel_dp)
2342	Serge	341	{
3243	Serge	342	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	343	struct drm_i915_private *dev_priv = dev->dev_private;
		344
4560	Serge	345	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
2342	Serge	346	}
		347
5060	serge	348	static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
2342	Serge	349	{
3243	Serge	350	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	351	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	352	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		353	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		354	enum intel_display_power_domain power_domain;
2342	Serge	355
5060	serge	356	power_domain = intel_display_port_power_domain(intel_encoder);
		357	return intel_display_power_enabled(dev_priv, power_domain) &&
		358	(I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
2342	Serge	359	}
		360
		361	static void
		362	intel_dp_check_edp(struct intel_dp *intel_dp)
		363	{
3243	Serge	364	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	365	struct drm_i915_private *dev_priv = dev->dev_private;
		366
		367	if (!is_edp(intel_dp))
		368	return;
3746	Serge	369
5060	serge	370	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
2342	Serge	371	WARN(1, "eDP powered off while attempting aux channel communication.\n");
		372	DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
4560	Serge	373	I915_READ(_pp_stat_reg(intel_dp)),
		374	I915_READ(_pp_ctrl_reg(intel_dp)));
2342	Serge	375	}
		376	}
		377
3480	Serge	378	static uint32_t
		379	intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
		380	{
		381	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		382	struct drm_device *dev = intel_dig_port->base.base.dev;
		383	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	384	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
3480	Serge	385	uint32_t status;
		386	bool done;
		387
		388	#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		389	if (has_aux_irq)
		390	done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
4104	Serge	391	msecs_to_jiffies_timeout(10));
3480	Serge	392	else
		393	done = wait_for_atomic(C, 10) == 0;
		394	if (!done)
		395	DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
		396	has_aux_irq);
		397	#undef C
		398
		399	return status;
		400	}
		401
5060	serge	402	static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
4104	Serge	403	{
		404	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		405	struct drm_device *dev = intel_dig_port->base.base.dev;
		406
5060	serge	407	/*
		408	* The clock divider is based off the hrawclk, and would like to run at
		409	* 2MHz. So, take the hrawclk value and divide by 2 and use that
4104	Serge	410	*/
5060	serge	411	return index ? 0 : intel_hrawclk(dev) / 2;
		412	}
		413
		414	static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
		415	{
		416	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		417	struct drm_device *dev = intel_dig_port->base.base.dev;
		418
		419	if (index)
		420	return 0;
		421
		422	if (intel_dig_port->port == PORT_A) {
		423	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
4104	Serge	424	return 200; /* SNB & IVB eDP input clock at 400Mhz */
		425	else
		426	return 225; /* eDP input clock at 450Mhz */
5060	serge	427	} else {
		428	return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
		429	}
		430	}
		431
		432	static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
		433	{
		434	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		435	struct drm_device *dev = intel_dig_port->base.base.dev;
		436	struct drm_i915_private *dev_priv = dev->dev_private;
		437
		438	if (intel_dig_port->port == PORT_A) {
		439	if (index)
		440	return 0;
		441	return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
4104	Serge	442	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		443	/* Workaround for non-ULT HSW */
		444	switch (index) {
		445	case 0: return 63;
		446	case 1: return 72;
		447	default: return 0;
		448	}
5060	serge	449	} else {
4104	Serge	450	return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
		451	}
		452	}
		453
5060	serge	454	static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
		455	{
		456	return index ? 0 : 100;
		457	}
		458
		459	static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
		460	bool has_aux_irq,
		461	int send_bytes,
		462	uint32_t aux_clock_divider)
		463	{
		464	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		465	struct drm_device *dev = intel_dig_port->base.base.dev;
		466	uint32_t precharge, timeout;
		467
		468	if (IS_GEN6(dev))
		469	precharge = 3;
		470	else
		471	precharge = 5;
		472
		473	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		474	timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
		475	else
		476	timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
		477
		478	return DP_AUX_CH_CTL_SEND_BUSY \|
		479	DP_AUX_CH_CTL_DONE \|
		480	(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) \|
		481	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		482	timeout \|
		483	DP_AUX_CH_CTL_RECEIVE_ERROR \|
		484	(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		485	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		486	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
		487	}
		488
2330	Serge	489	static int
		490	intel_dp_aux_ch(struct intel_dp *intel_dp,
		491	uint8_t *send, int send_bytes,
		492	uint8_t *recv, int recv_size)
		493	{
3243	Serge	494	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		495	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	496	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	497	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
2330	Serge	498	uint32_t ch_data = ch_ctl + 4;
4104	Serge	499	uint32_t aux_clock_divider;
3480	Serge	500	int i, ret, recv_bytes;
2330	Serge	501	uint32_t status;
5060	serge	502	int try, clock = 0;
		503	bool has_aux_irq = HAS_AUX_IRQ(dev);
		504	bool vdd;
2330	Serge	505
5060	serge	506	vdd = _edp_panel_vdd_on(intel_dp);
		507
3480	Serge	508	/* dp aux is extremely sensitive to irq latency, hence request the
		509	* lowest possible wakeup latency and so prevent the cpu from going into
		510	* deep sleep states.
		511	*/
		512
2342	Serge	513	intel_dp_check_edp(intel_dp);
2330	Serge	514
4104	Serge	515	intel_aux_display_runtime_get(dev_priv);
		516
2330	Serge	517	/* Try to wait for any previous AUX channel activity */
		518	for (try = 0; try < 3; try++) {
3480	Serge	519	status = I915_READ_NOTRACE(ch_ctl);
2330	Serge	520	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		521	break;
		522	msleep(1);
		523	}
		524
		525	if (try == 3) {
		526	WARN(1, "dp_aux_ch not started status 0x%08x\n",
		527	I915_READ(ch_ctl));
3480	Serge	528	ret = -EBUSY;
		529	goto out;
2330	Serge	530	}
		531
4560	Serge	532	/* Only 5 data registers! */
		533	if (WARN_ON(send_bytes > 20 \|\| recv_size > 20)) {
		534	ret = -E2BIG;
		535	goto out;
		536	}
		537
5060	serge	538	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
		539	u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
		540	has_aux_irq,
		541	send_bytes,
		542	aux_clock_divider);
		543
2330	Serge	544	/* Must try at least 3 times according to DP spec */
		545	for (try = 0; try < 5; try++) {
		546	/* Load the send data into the aux channel data registers */
		547	for (i = 0; i < send_bytes; i += 4)
		548	I915_WRITE(ch_data + i,
		549	pack_aux(send + i, send_bytes - i));
		550
		551	/* Send the command and wait for it to complete */
5060	serge	552	I915_WRITE(ch_ctl, send_ctl);
2330	Serge	553
3480	Serge	554	status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
		555
2330	Serge	556	/* Clear done status and any errors */
		557	I915_WRITE(ch_ctl,
		558	status \|
		559	DP_AUX_CH_CTL_DONE \|
		560	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		561	DP_AUX_CH_CTL_RECEIVE_ERROR);
3031	serge	562
		563	if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		564	DP_AUX_CH_CTL_RECEIVE_ERROR))
		565	continue;
2330	Serge	566	if (status & DP_AUX_CH_CTL_DONE)
		567	break;
		568	}
4104	Serge	569	if (status & DP_AUX_CH_CTL_DONE)
		570	break;
		571	}
2330	Serge	572
		573	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		574	DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
3480	Serge	575	ret = -EBUSY;
		576	goto out;
2330	Serge	577	}
		578
		579	/* Check for timeout or receive error.
		580	* Timeouts occur when the sink is not connected
		581	*/
		582	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
		583	DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
3480	Serge	584	ret = -EIO;
		585	goto out;
2330	Serge	586	}
		587
		588	/* Timeouts occur when the device isn't connected, so they're
		589	* "normal" -- don't fill the kernel log with these */
		590	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
		591	DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
3480	Serge	592	ret = -ETIMEDOUT;
		593	goto out;
2330	Serge	594	}
		595
		596	/* Unload any bytes sent back from the other side */
		597	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		598	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
		599	if (recv_bytes > recv_size)
		600	recv_bytes = recv_size;
		601
		602	for (i = 0; i < recv_bytes; i += 4)
		603	unpack_aux(I915_READ(ch_data + i),
		604	recv + i, recv_bytes - i);
		605
3480	Serge	606	ret = recv_bytes;
		607	out:
		608	// pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
4104	Serge	609	intel_aux_display_runtime_put(dev_priv);
3480	Serge	610
5060	serge	611	if (vdd)
		612	edp_panel_vdd_off(intel_dp, false);
		613
3480	Serge	614	return ret;
2330	Serge	615	}
		616
5060	serge	617	#define BARE_ADDRESS_SIZE 3
		618	#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
		619	static ssize_t
		620	intel_dp_aux_transfer(struct drm_dp_aux aux, struct drm_dp_aux_msg msg)
2330	Serge	621	{
5060	serge	622	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
		623	uint8_t txbuf[20], rxbuf[20];
		624	size_t txsize, rxsize;
2330	Serge	625	int ret;
		626
5060	serge	627	txbuf[0] = msg->request << 4;
		628	txbuf[1] = msg->address >> 8;
		629	txbuf[2] = msg->address & 0xff;
		630	txbuf[3] = msg->size - 1;
		631
		632	switch (msg->request & ~DP_AUX_I2C_MOT) {
		633	case DP_AUX_NATIVE_WRITE:
		634	case DP_AUX_I2C_WRITE:
		635	txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
		636	rxsize = 1;
		637
		638	if (WARN_ON(txsize > 20))
4560	Serge	639	return -E2BIG;
		640
5060	serge	641	memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
		642
		643	ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		644	if (ret > 0) {
		645	msg->reply = rxbuf[0] >> 4;
		646
		647	/* Return payload size. */
		648	ret = msg->size;
		649	}
2330	Serge	650	break;
		651
5060	serge	652	case DP_AUX_NATIVE_READ:
		653	case DP_AUX_I2C_READ:
		654	txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
		655	rxsize = msg->size + 1;
2330	Serge	656
5060	serge	657	if (WARN_ON(rxsize > 20))
4560	Serge	658	return -E2BIG;
		659
5060	serge	660	ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		661	if (ret > 0) {
		662	msg->reply = rxbuf[0] >> 4;
		663	/*
		664	* Assume happy day, and copy the data. The caller is
		665	* expected to check msg->reply before touching it.
		666	*
		667	* Return payload size.
		668	*/
		669	ret--;
		670	memcpy(msg->buffer, rxbuf + 1, ret);
		671	}
		672	break;
2330	Serge	673
5060	serge	674	default:
		675	ret = -EINVAL;
		676	break;
		677	}
2330	Serge	678
		679	return ret;
		680	}
		681
5060	serge	682	static void
		683	intel_dp_aux_init(struct intel_dp intel_dp, struct intel_connector connector)
2330	Serge	684	{
5060	serge	685	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		686	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		687	enum port port = intel_dig_port->port;
		688	const char *name = NULL;
2330	Serge	689	int ret;
		690
5060	serge	691	switch (port) {
		692	case PORT_A:
		693	intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
		694	name = "DPDDC-A";
2330	Serge	695	break;
5060	serge	696	case PORT_B:
		697	intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
		698	name = "DPDDC-B";
2330	Serge	699	break;
5060	serge	700	case PORT_C:
		701	intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
		702	name = "DPDDC-C";
		703	break;
		704	case PORT_D:
		705	intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
		706	name = "DPDDC-D";
		707	break;
2330	Serge	708	default:
5060	serge	709	BUG();
2330	Serge	710	}
		711
5060	serge	712	if (!HAS_DDI(dev))
		713	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2330	Serge	714
5060	serge	715	intel_dp->aux.name = name;
		716	intel_dp->aux.dev = dev->dev;
		717	intel_dp->aux.transfer = intel_dp_aux_transfer;
2330	Serge	718
5060	serge	719
		720	ret = drm_dp_aux_register(&intel_dp->aux);
		721	if (ret < 0) {
		722	DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
		723	name, ret);
		724	return;
2330	Serge	725	}
5060	serge	726	}
2330	Serge	727
5060	serge	728	static void
		729	intel_dp_connector_unregister(struct intel_connector *intel_connector)
		730	{
		731	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
4560	Serge	732
5060	serge	733	intel_connector_unregister(intel_connector);
2330	Serge	734	}
		735
5060	serge	736	static void
		737	hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
2330	Serge	738	{
5060	serge	739	switch (link_bw) {
		740	case DP_LINK_BW_1_62:
		741	pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		742	break;
		743	case DP_LINK_BW_2_7:
		744	pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		745	break;
		746	case DP_LINK_BW_5_4:
		747	pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		748	break;
		749	}
2330	Serge	750	}
		751
4104	Serge	752	static void
		753	intel_dp_set_clock(struct intel_encoder *encoder,
		754	struct intel_crtc_config *pipe_config, int link_bw)
		755	{
		756	struct drm_device *dev = encoder->base.dev;
4560	Serge	757	const struct dp_link_dpll *divisor = NULL;
		758	int i, count = 0;
4104	Serge	759
		760	if (IS_G4X(dev)) {
4560	Serge	761	divisor = gen4_dpll;
		762	count = ARRAY_SIZE(gen4_dpll);
4104	Serge	763	} else if (HAS_PCH_SPLIT(dev)) {
4560	Serge	764	divisor = pch_dpll;
		765	count = ARRAY_SIZE(pch_dpll);
5060	serge	766	} else if (IS_CHERRYVIEW(dev)) {
		767	divisor = chv_dpll;
		768	count = ARRAY_SIZE(chv_dpll);
4560	Serge	769	} else if (IS_VALLEYVIEW(dev)) {
		770	divisor = vlv_dpll;
		771	count = ARRAY_SIZE(vlv_dpll);
5060	serge	772	}
4560	Serge	773
		774	if (divisor && count) {
		775	for (i = 0; i < count; i++) {
		776	if (link_bw == divisor[i].link_bw) {
		777	pipe_config->dpll = divisor[i].dpll;
5060	serge	778	pipe_config->clock_set = true;
4560	Serge	779	break;
		780	}
		781	}
4104	Serge	782	}
		783	}
		784
5060	serge	785	static void
		786	intel_dp_set_m2_n2(struct intel_crtc crtc, struct intel_link_m_n m_n)
		787	{
		788	struct drm_device *dev = crtc->base.dev;
		789	struct drm_i915_private *dev_priv = dev->dev_private;
		790	enum transcoder transcoder = crtc->config.cpu_transcoder;
		791
		792	I915_WRITE(PIPE_DATA_M2(transcoder),
		793	TU_SIZE(m_n->tu) \| m_n->gmch_m);
		794	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
		795	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
		796	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
		797	}
		798
3243	Serge	799	bool
3746	Serge	800	intel_dp_compute_config(struct intel_encoder *encoder,
		801	struct intel_crtc_config *pipe_config)
2330	Serge	802	{
3746	Serge	803	struct drm_device *dev = encoder->base.dev;
		804	struct drm_i915_private *dev_priv = dev->dev_private;
		805	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		806	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	807	enum port port = dp_to_dig_port(intel_dp)->port;
		808	struct intel_crtc *intel_crtc = encoder->new_crtc;
3243	Serge	809	struct intel_connector *intel_connector = intel_dp->attached_connector;
2330	Serge	810	int lane_count, clock;
5060	serge	811	int min_lane_count = 1;
		812	int max_lane_count = intel_dp_max_lane_count(intel_dp);
		813	/* Conveniently, the link BW constants become indices with a shift...*/
		814	int min_clock = 0;
		815	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
3031	serge	816	int bpp, mode_rate;
5060	serge	817	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
4104	Serge	818	int link_avail, link_clock;
2330	Serge	819
4104	Serge	820	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
3746	Serge	821	pipe_config->has_pch_encoder = true;
		822
		823	pipe_config->has_dp_encoder = true;
5060	serge	824	pipe_config->has_audio = intel_dp->has_audio;
3746	Serge	825
3243	Serge	826	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		827	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
		828	adjusted_mode);
4104	Serge	829	if (!HAS_PCH_SPLIT(dev))
		830	intel_gmch_panel_fitting(intel_crtc, pipe_config,
		831	intel_connector->panel.fitting_mode);
		832	else
		833	intel_pch_panel_fitting(intel_crtc, pipe_config,
		834	intel_connector->panel.fitting_mode);
2330	Serge	835	}
		836
3031	serge	837	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		838	return false;
		839
		840	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		841	"max bw %02x pixel clock %iKHz\n",
4560	Serge	842	max_lane_count, bws[max_clock],
		843	adjusted_mode->crtc_clock);
3031	serge	844
3746	Serge	845	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
		846	* bpc in between. */
4104	Serge	847	bpp = pipe_config->pipe_bpp;
5060	serge	848	if (is_edp(intel_dp)) {
		849	if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
4104	Serge	850	DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
		851	dev_priv->vbt.edp_bpp);
4560	Serge	852	bpp = dev_priv->vbt.edp_bpp;
4104	Serge	853	}
3746	Serge	854
5060	serge	855	if (IS_BROADWELL(dev)) {
		856	/* Yes, it's an ugly hack. */
		857	min_lane_count = max_lane_count;
		858	DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
		859	min_lane_count);
		860	} else if (dev_priv->vbt.edp_lanes) {
		861	min_lane_count = min(dev_priv->vbt.edp_lanes,
		862	max_lane_count);
		863	DRM_DEBUG_KMS("using min %u lanes per VBT\n",
		864	min_lane_count);
		865	}
		866
		867	if (dev_priv->vbt.edp_rate) {
		868	min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
		869	DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
		870	bws[min_clock]);
		871	}
		872	}
		873
3746	Serge	874	for (; bpp >= 63; bpp -= 23) {
4560	Serge	875	mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
		876	bpp);
3746	Serge	877
5060	serge	878	for (clock = min_clock; clock <= max_clock; clock++) {
		879	for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
3746	Serge	880	link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
		881	link_avail = intel_dp_max_data_rate(link_clock,
		882	lane_count);
		883
		884	if (mode_rate <= link_avail) {
		885	goto found;
		886	}
		887	}
		888	}
		889	}
		890
3031	serge	891	return false;
		892
3746	Serge	893	found:
3480	Serge	894	if (intel_dp->color_range_auto) {
		895	/*
		896	* See:
		897	* CEA-861-E - 5.1 Default Encoding Parameters
		898	* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		899	*/
		900	if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
		901	intel_dp->color_range = DP_COLOR_RANGE_16_235;
		902	else
		903	intel_dp->color_range = 0;
		904	}
		905
		906	if (intel_dp->color_range)
3746	Serge	907	pipe_config->limited_color_range = true;
3480	Serge	908
2330	Serge	909	intel_dp->link_bw = bws[clock];
		910	intel_dp->lane_count = lane_count;
3746	Serge	911	pipe_config->pipe_bpp = bpp;
4104	Serge	912	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
3746	Serge	913
		914	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
2330	Serge	915	intel_dp->link_bw, intel_dp->lane_count,
4104	Serge	916	pipe_config->port_clock, bpp);
3031	serge	917	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		918	mode_rate, link_avail);
2330	Serge	919
3746	Serge	920	intel_link_compute_m_n(bpp, lane_count,
4560	Serge	921	adjusted_mode->crtc_clock,
		922	pipe_config->port_clock,
3746	Serge	923	&pipe_config->dp_m_n);
2330	Serge	924
5060	serge	925	if (intel_connector->panel.downclock_mode != NULL &&
		926	intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
		927	intel_link_compute_m_n(bpp, lane_count,
		928	intel_connector->panel.downclock_mode->clock,
		929	pipe_config->port_clock,
		930	&pipe_config->dp_m2_n2);
		931	}
		932
		933	if (HAS_DDI(dev))
		934	hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
		935	else
4104	Serge	936	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
		937
3746	Serge	938	return true;
2327	Serge	939	}
		940
4104	Serge	941	static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
3480	Serge	942	{
4104	Serge	943	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		944	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
		945	struct drm_device *dev = crtc->base.dev;
3480	Serge	946	struct drm_i915_private *dev_priv = dev->dev_private;
		947	u32 dpa_ctl;
		948
4104	Serge	949	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
3480	Serge	950	dpa_ctl = I915_READ(DP_A);
		951	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		952
4104	Serge	953	if (crtc->config.port_clock == 162000) {
3480	Serge	954	/* For a long time we've carried around a ILK-DevA w/a for the
		955	* 160MHz clock. If we're really unlucky, it's still required.
		956	*/
		957	DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
		958	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
4104	Serge	959	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
3480	Serge	960	} else {
		961	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
4104	Serge	962	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
3480	Serge	963	}
		964
		965	I915_WRITE(DP_A, dpa_ctl);
		966
		967	POSTING_READ(DP_A);
		968	udelay(500);
		969	}
		970
5060	serge	971	static void intel_dp_prepare(struct intel_encoder *encoder)
2330	Serge	972	{
4104	Serge	973	struct drm_device *dev = encoder->base.dev;
2342	Serge	974	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	975	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		976	enum port port = dp_to_dig_port(intel_dp)->port;
		977	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		978	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
2327	Serge	979
2342	Serge	980	/*
		981	* There are four kinds of DP registers:
		982	*
		983	* IBX PCH
		984	* SNB CPU
		985	* IVB CPU
		986	* CPT PCH
		987	*
		988	* IBX PCH and CPU are the same for almost everything,
		989	* except that the CPU DP PLL is configured in this
		990	* register
		991	*
		992	* CPT PCH is quite different, having many bits moved
		993	* to the TRANS_DP_CTL register instead. That
		994	* configuration happens (oddly) in ironlake_pch_enable
		995	*/
2327	Serge	996
2342	Serge	997	/* Preserve the BIOS-computed detected bit. This is
		998	* supposed to be read-only.
		999	*/
		1000	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2327	Serge	1001
2342	Serge	1002	/* Handle DP bits in common between all three register formats */
		1003	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
4104	Serge	1004	intel_dp->DP \|= DP_PORT_WIDTH(intel_dp->lane_count);
2342	Serge	1005
5060	serge	1006	if (crtc->config.has_audio) {
2342	Serge	1007	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
4104	Serge	1008	pipe_name(crtc->pipe));
2330	Serge	1009	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
4104	Serge	1010	intel_write_eld(&encoder->base, adjusted_mode);
2342	Serge	1011	}
2327	Serge	1012
2342	Serge	1013	/* Split out the IBX/CPU vs CPT settings */
		1014
4104	Serge	1015	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
2342	Serge	1016	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		1017	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		1018	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		1019	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		1020	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		1021
4560	Serge	1022	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2342	Serge	1023	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		1024
4104	Serge	1025	intel_dp->DP \|= crtc->pipe << 29;
		1026	} else if (!HAS_PCH_CPT(dev) \|\| port == PORT_A) {
3746	Serge	1027	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
2342	Serge	1028	intel_dp->DP \|= intel_dp->color_range;
		1029
		1030	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		1031	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		1032	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		1033	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		1034	intel_dp->DP \|= DP_LINK_TRAIN_OFF;
		1035
4560	Serge	1036	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2342	Serge	1037	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		1038
5060	serge	1039	if (!IS_CHERRYVIEW(dev)) {
4104	Serge	1040	if (crtc->pipe == 1)
2330	Serge	1041	intel_dp->DP \|= DP_PIPEB_SELECT;
2342	Serge	1042	} else {
5060	serge	1043	intel_dp->DP \|= DP_PIPE_SELECT_CHV(crtc->pipe);
		1044	}
		1045	} else {
2342	Serge	1046	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		1047	}
2330	Serge	1048	}
2327	Serge	1049
5060	serge	1050	#define IDLE_ON_MASK (PP_ON \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		1051	#define IDLE_ON_VALUE (PP_ON \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_ON_IDLE)
2342	Serge	1052
5060	serge	1053	#define IDLE_OFF_MASK (PP_ON \| PP_SEQUENCE_MASK \| 0 \| 0)
		1054	#define IDLE_OFF_VALUE (0 \| PP_SEQUENCE_NONE \| 0 \| 0)
2342	Serge	1055
5060	serge	1056	#define IDLE_CYCLE_MASK (PP_ON \| PP_SEQUENCE_MASK \| PP_CYCLE_DELAY_ACTIVE \| PP_SEQUENCE_STATE_MASK)
		1057	#define IDLE_CYCLE_VALUE (0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
2342	Serge	1058
5060	serge	1059	static void wait_panel_status(struct intel_dp *intel_dp,
2342	Serge	1060	u32 mask,
		1061	u32 value)
		1062	{
3243	Serge	1063	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	1064	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	1065	u32 pp_stat_reg, pp_ctrl_reg;
2342	Serge	1066
4560	Serge	1067	pp_stat_reg = _pp_stat_reg(intel_dp);
		1068	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1069
2342	Serge	1070	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		1071	mask, value,
3746	Serge	1072	I915_READ(pp_stat_reg),
		1073	I915_READ(pp_ctrl_reg));
2342	Serge	1074
3746	Serge	1075	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
2342	Serge	1076	DRM_ERROR("Panel status timeout: status %08x control %08x\n",
3746	Serge	1077	I915_READ(pp_stat_reg),
		1078	I915_READ(pp_ctrl_reg));
2342	Serge	1079	}
4560	Serge	1080
		1081	DRM_DEBUG_KMS("Wait complete\n");
2342	Serge	1082	}
		1083
5060	serge	1084	static void wait_panel_on(struct intel_dp *intel_dp)
2342	Serge	1085	{
		1086	DRM_DEBUG_KMS("Wait for panel power on\n");
5060	serge	1087	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2342	Serge	1088	}
		1089
5060	serge	1090	static void wait_panel_off(struct intel_dp *intel_dp)
2342	Serge	1091	{
		1092	DRM_DEBUG_KMS("Wait for panel power off time\n");
5060	serge	1093	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2342	Serge	1094	}
		1095
5060	serge	1096	static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2342	Serge	1097	{
		1098	DRM_DEBUG_KMS("Wait for panel power cycle\n");
5060	serge	1099
		1100	/* When we disable the VDD override bit last we have to do the manual
		1101	* wait. */
		1102	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
		1103	intel_dp->panel_power_cycle_delay);
		1104
		1105	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2342	Serge	1106	}
		1107
5060	serge	1108	static void wait_backlight_on(struct intel_dp *intel_dp)
		1109	{
		1110	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
		1111	intel_dp->backlight_on_delay);
		1112	}
2342	Serge	1113
5060	serge	1114	static void edp_wait_backlight_off(struct intel_dp *intel_dp)
		1115	{
		1116	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
		1117	intel_dp->backlight_off_delay);
		1118	}
		1119
2342	Serge	1120	/* Read the current pp_control value, unlocking the register if it
		1121	* is locked
		1122	*/
		1123
3746	Serge	1124	static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2342	Serge	1125	{
3746	Serge	1126	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1127	struct drm_i915_private *dev_priv = dev->dev_private;
		1128	u32 control;
2342	Serge	1129
4560	Serge	1130	control = I915_READ(_pp_ctrl_reg(intel_dp));
2342	Serge	1131	control &= ~PANEL_UNLOCK_MASK;
		1132	control \|= PANEL_UNLOCK_REGS;
		1133	return control;
		1134	}
		1135
5060	serge	1136	static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
2330	Serge	1137	{
3243	Serge	1138	struct drm_device *dev = intel_dp_to_dev(intel_dp);
5060	serge	1139	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1140	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2330	Serge	1141	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	1142	enum intel_display_power_domain power_domain;
2330	Serge	1143	u32 pp;
3746	Serge	1144	u32 pp_stat_reg, pp_ctrl_reg;
5060	serge	1145	bool need_to_disable = !intel_dp->want_panel_vdd;
2327	Serge	1146
2342	Serge	1147	if (!is_edp(intel_dp))
5060	serge	1148	return false;
2327	Serge	1149
2342	Serge	1150	intel_dp->want_panel_vdd = true;
		1151
5060	serge	1152	if (edp_have_panel_vdd(intel_dp))
		1153	return need_to_disable;
2342	Serge	1154
5060	serge	1155	power_domain = intel_display_port_power_domain(intel_encoder);
		1156	intel_display_power_get(dev_priv, power_domain);
4560	Serge	1157
		1158	DRM_DEBUG_KMS("Turning eDP VDD on\n");
		1159
5060	serge	1160	if (!edp_have_panel_power(intel_dp))
		1161	wait_panel_power_cycle(intel_dp);
2342	Serge	1162
3746	Serge	1163	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1164	pp \|= EDP_FORCE_VDD;
2342	Serge	1165
4560	Serge	1166	pp_stat_reg = _pp_stat_reg(intel_dp);
		1167	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1168
		1169	I915_WRITE(pp_ctrl_reg, pp);
		1170	POSTING_READ(pp_ctrl_reg);
		1171	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		1172	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2342	Serge	1173	/*
		1174	* If the panel wasn't on, delay before accessing aux channel
		1175	*/
5060	serge	1176	if (!edp_have_panel_power(intel_dp)) {
2342	Serge	1177	DRM_DEBUG_KMS("eDP was not running\n");
		1178	msleep(intel_dp->panel_power_up_delay);
		1179	}
5060	serge	1180
		1181	return need_to_disable;
2330	Serge	1182	}
2327	Serge	1183
5060	serge	1184	void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2330	Serge	1185	{
5060	serge	1186	if (is_edp(intel_dp)) {
		1187	bool vdd = _edp_panel_vdd_on(intel_dp);
		1188
		1189	WARN(!vdd, "eDP VDD already requested on\n");
		1190	}
		1191	}
		1192
		1193	static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
		1194	{
3243	Serge	1195	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1196	struct drm_i915_private *dev_priv = dev->dev_private;
		1197	u32 pp;
3746	Serge	1198	u32 pp_stat_reg, pp_ctrl_reg;
2327	Serge	1199
5060	serge	1200	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3480	Serge	1201
5060	serge	1202	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
		1203	struct intel_digital_port *intel_dig_port =
		1204	dp_to_dig_port(intel_dp);
		1205	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		1206	enum intel_display_power_domain power_domain;
		1207
4560	Serge	1208	DRM_DEBUG_KMS("Turning eDP VDD off\n");
		1209
3746	Serge	1210	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1211	pp &= ~EDP_FORCE_VDD;
2327	Serge	1212
4560	Serge	1213	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		1214	pp_stat_reg = _pp_stat_reg(intel_dp);
3746	Serge	1215
		1216	I915_WRITE(pp_ctrl_reg, pp);
		1217	POSTING_READ(pp_ctrl_reg);
		1218
2330	Serge	1219	/* Make sure sequencer is idle before allowing subsequent activity */
3746	Serge	1220	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		1221	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
4560	Serge	1222
		1223	if ((pp & POWER_TARGET_ON) == 0)
5060	serge	1224	intel_dp->last_power_cycle = jiffies;
4560	Serge	1225
5060	serge	1226	power_domain = intel_display_port_power_domain(intel_encoder);
		1227	intel_display_power_put(dev_priv, power_domain);
2342	Serge	1228	}
2330	Serge	1229	}
2327	Serge	1230
5060	serge	1231	static void edp_panel_vdd_work(struct work_struct *__work)
3243	Serge	1232	{
3482	Serge	1233	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
		1234	struct intel_dp, panel_vdd_work);
		1235	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1236
5060	serge	1237	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
		1238	edp_panel_vdd_off_sync(intel_dp);
		1239	drm_modeset_unlock(&dev->mode_config.connection_mutex);
3243	Serge	1240	}
2342	Serge	1241
5060	serge	1242	static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2330	Serge	1243	{
5060	serge	1244	unsigned long delay;
		1245
		1246	/*
		1247	* Queue the timer to fire a long time from now (relative to the power
		1248	* down delay) to keep the panel power up across a sequence of
		1249	* operations.
		1250	*/
		1251	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
		1252	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
		1253	}
		1254
		1255	static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
		1256	{
2342	Serge	1257	if (!is_edp(intel_dp))
		1258	return;
		1259
		1260	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
		1261
		1262	intel_dp->want_panel_vdd = false;
		1263
5060	serge	1264	if (sync)
		1265	edp_panel_vdd_off_sync(intel_dp);
		1266	else
		1267	edp_panel_vdd_schedule_off(intel_dp);
2342	Serge	1268	}
		1269
5060	serge	1270	void intel_edp_panel_on(struct intel_dp *intel_dp)
2342	Serge	1271	{
3243	Serge	1272	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1273	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1274	u32 pp;
3746	Serge	1275	u32 pp_ctrl_reg;
2327	Serge	1276
2342	Serge	1277	if (!is_edp(intel_dp))
		1278	return;
2327	Serge	1279
2342	Serge	1280	DRM_DEBUG_KMS("Turn eDP power on\n");
2327	Serge	1281
5060	serge	1282	if (edp_have_panel_power(intel_dp)) {
2342	Serge	1283	DRM_DEBUG_KMS("eDP power already on\n");
		1284	return;
		1285	}
		1286
5060	serge	1287	wait_panel_power_cycle(intel_dp);
2342	Serge	1288
4560	Serge	1289	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1290	pp = ironlake_get_pp_control(intel_dp);
2342	Serge	1291	if (IS_GEN5(dev)) {
2330	Serge	1292	/* ILK workaround: disable reset around power sequence */
		1293	pp &= ~PANEL_POWER_RESET;
4560	Serge	1294	I915_WRITE(pp_ctrl_reg, pp);
		1295	POSTING_READ(pp_ctrl_reg);
2342	Serge	1296	}
2327	Serge	1297
2342	Serge	1298	pp \|= POWER_TARGET_ON;
		1299	if (!IS_GEN5(dev))
		1300	pp \|= PANEL_POWER_RESET;
		1301
3746	Serge	1302	I915_WRITE(pp_ctrl_reg, pp);
		1303	POSTING_READ(pp_ctrl_reg);
		1304
5060	serge	1305	wait_panel_on(intel_dp);
		1306	intel_dp->last_power_on = jiffies;
2327	Serge	1307
2342	Serge	1308	if (IS_GEN5(dev)) {
2330	Serge	1309	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
4560	Serge	1310	I915_WRITE(pp_ctrl_reg, pp);
		1311	POSTING_READ(pp_ctrl_reg);
2342	Serge	1312	}
2330	Serge	1313	}
2327	Serge	1314
5060	serge	1315	void intel_edp_panel_off(struct intel_dp *intel_dp)
2330	Serge	1316	{
5060	serge	1317	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1318	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3243	Serge	1319	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1320	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	1321	enum intel_display_power_domain power_domain;
2342	Serge	1322	u32 pp;
3746	Serge	1323	u32 pp_ctrl_reg;
2327	Serge	1324
2342	Serge	1325	if (!is_edp(intel_dp))
		1326	return;
2327	Serge	1327
2342	Serge	1328	DRM_DEBUG_KMS("Turn eDP power off\n");
2327	Serge	1329
5060	serge	1330	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
		1331
3746	Serge	1332	pp = ironlake_get_pp_control(intel_dp);
3031	serge	1333	/* We need to switch off panel power _and_ force vdd, for otherwise some
		1334	* panels get very unhappy and cease to work. */
5060	serge	1335	pp &= ~(POWER_TARGET_ON \| PANEL_POWER_RESET \| EDP_FORCE_VDD \|
		1336	EDP_BLC_ENABLE);
2327	Serge	1337
4560	Serge	1338	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1339
5060	serge	1340	intel_dp->want_panel_vdd = false;
		1341
3746	Serge	1342	I915_WRITE(pp_ctrl_reg, pp);
		1343	POSTING_READ(pp_ctrl_reg);
		1344
5060	serge	1345	intel_dp->last_power_cycle = jiffies;
		1346	wait_panel_off(intel_dp);
		1347
		1348	/* We got a reference when we enabled the VDD. */
		1349	power_domain = intel_display_port_power_domain(intel_encoder);
		1350	intel_display_power_put(dev_priv, power_domain);
2330	Serge	1351	}
2327	Serge	1352
5060	serge	1353	void intel_edp_backlight_on(struct intel_dp *intel_dp)
2330	Serge	1354	{
3243	Serge	1355	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1356	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	1357	struct drm_i915_private *dev_priv = dev->dev_private;
		1358	u32 pp;
3746	Serge	1359	u32 pp_ctrl_reg;
2327	Serge	1360
2342	Serge	1361	if (!is_edp(intel_dp))
		1362	return;
		1363
2330	Serge	1364	DRM_DEBUG_KMS("\n");
5060	serge	1365
		1366	intel_panel_enable_backlight(intel_dp->attached_connector);
		1367
2330	Serge	1368	/*
		1369	* If we enable the backlight right away following a panel power
		1370	* on, we may see slight flicker as the panel syncs with the eDP
		1371	* link. So delay a bit to make sure the image is solid before
		1372	* allowing it to appear.
		1373	*/
5060	serge	1374	wait_backlight_on(intel_dp);
3746	Serge	1375	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1376	pp \|= EDP_BLC_ENABLE;
3243	Serge	1377
4560	Serge	1378	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1379
		1380	I915_WRITE(pp_ctrl_reg, pp);
		1381	POSTING_READ(pp_ctrl_reg);
2330	Serge	1382	}
2327	Serge	1383
5060	serge	1384	void intel_edp_backlight_off(struct intel_dp *intel_dp)
2330	Serge	1385	{
3243	Serge	1386	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1387	struct drm_i915_private *dev_priv = dev->dev_private;
		1388	u32 pp;
3746	Serge	1389	u32 pp_ctrl_reg;
2327	Serge	1390
2342	Serge	1391	if (!is_edp(intel_dp))
		1392	return;
		1393
2330	Serge	1394	DRM_DEBUG_KMS("\n");
3746	Serge	1395	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1396	pp &= ~EDP_BLC_ENABLE;
3746	Serge	1397
4560	Serge	1398	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3746	Serge	1399
		1400	I915_WRITE(pp_ctrl_reg, pp);
		1401	POSTING_READ(pp_ctrl_reg);
5060	serge	1402	intel_dp->last_backlight_off = jiffies;
		1403
		1404	edp_wait_backlight_off(intel_dp);
		1405
		1406	intel_panel_disable_backlight(intel_dp->attached_connector);
2330	Serge	1407	}
2327	Serge	1408
3031	serge	1409	static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2330	Serge	1410	{
3243	Serge	1411	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1412	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		1413	struct drm_device *dev = crtc->dev;
2330	Serge	1414	struct drm_i915_private *dev_priv = dev->dev_private;
		1415	u32 dpa_ctl;
2327	Serge	1416
3031	serge	1417	assert_pipe_disabled(dev_priv,
		1418	to_intel_crtc(crtc)->pipe);
		1419
2330	Serge	1420	DRM_DEBUG_KMS("\n");
		1421	dpa_ctl = I915_READ(DP_A);
3031	serge	1422	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
		1423	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
		1424
		1425	/* We don't adjust intel_dp->DP while tearing down the link, to
		1426	* facilitate link retraining (e.g. after hotplug). Hence clear all
		1427	* enable bits here to ensure that we don't enable too much. */
		1428	intel_dp->DP &= ~(DP_PORT_EN \| DP_AUDIO_OUTPUT_ENABLE);
		1429	intel_dp->DP \|= DP_PLL_ENABLE;
		1430	I915_WRITE(DP_A, intel_dp->DP);
2330	Serge	1431	POSTING_READ(DP_A);
		1432	udelay(200);
		1433	}
2327	Serge	1434
3031	serge	1435	static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2330	Serge	1436	{
3243	Serge	1437	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1438	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		1439	struct drm_device *dev = crtc->dev;
2330	Serge	1440	struct drm_i915_private *dev_priv = dev->dev_private;
		1441	u32 dpa_ctl;
2327	Serge	1442
3031	serge	1443	assert_pipe_disabled(dev_priv,
		1444	to_intel_crtc(crtc)->pipe);
		1445
2330	Serge	1446	dpa_ctl = I915_READ(DP_A);
3031	serge	1447	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
		1448	"dp pll off, should be on\n");
		1449	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
		1450
		1451	/* We can't rely on the value tracked for the DP register in
		1452	* intel_dp->DP because link_down must not change that (otherwise link
		1453	* re-training will fail. */
2330	Serge	1454	dpa_ctl &= ~DP_PLL_ENABLE;
		1455	I915_WRITE(DP_A, dpa_ctl);
		1456	POSTING_READ(DP_A);
		1457	udelay(200);
		1458	}
2327	Serge	1459
2330	Serge	1460	/* If the sink supports it, try to set the power state appropriately */
3243	Serge	1461	void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2330	Serge	1462	{
		1463	int ret, i;
2327	Serge	1464
2330	Serge	1465	/* Should have a valid DPCD by this point */
		1466	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		1467	return;
2327	Serge	1468
2330	Serge	1469	if (mode != DRM_MODE_DPMS_ON) {
5060	serge	1470	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2330	Serge	1471	DP_SET_POWER_D3);
		1472	if (ret != 1)
		1473	DRM_DEBUG_DRIVER("failed to write sink power state\n");
		1474	} else {
		1475	/*
		1476	* When turning on, we need to retry for 1ms to give the sink
		1477	* time to wake up.
		1478	*/
		1479	for (i = 0; i < 3; i++) {
5060	serge	1480	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2330	Serge	1481	DP_SET_POWER_D0);
		1482	if (ret == 1)
		1483	break;
		1484	msleep(1);
		1485	}
		1486	}
		1487	}
2327	Serge	1488
3031	serge	1489	static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
		1490	enum pipe *pipe)
2330	Serge	1491	{
3031	serge	1492	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1493	enum port port = dp_to_dig_port(intel_dp)->port;
3031	serge	1494	struct drm_device *dev = encoder->base.dev;
		1495	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	1496	enum intel_display_power_domain power_domain;
		1497	u32 tmp;
2327	Serge	1498
5060	serge	1499	power_domain = intel_display_port_power_domain(encoder);
		1500	if (!intel_display_power_enabled(dev_priv, power_domain))
		1501	return false;
		1502
		1503	tmp = I915_READ(intel_dp->output_reg);
		1504
3031	serge	1505	if (!(tmp & DP_PORT_EN))
		1506	return false;
2342	Serge	1507
4104	Serge	1508	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
3031	serge	1509	*pipe = PORT_TO_PIPE_CPT(tmp);
5060	serge	1510	} else if (IS_CHERRYVIEW(dev)) {
		1511	*pipe = DP_PORT_TO_PIPE_CHV(tmp);
4104	Serge	1512	} else if (!HAS_PCH_CPT(dev) \|\| port == PORT_A) {
3031	serge	1513	*pipe = PORT_TO_PIPE(tmp);
		1514	} else {
		1515	u32 trans_sel;
		1516	u32 trans_dp;
		1517	int i;
2327	Serge	1518
3031	serge	1519	switch (intel_dp->output_reg) {
		1520	case PCH_DP_B:
		1521	trans_sel = TRANS_DP_PORT_SEL_B;
		1522	break;
		1523	case PCH_DP_C:
		1524	trans_sel = TRANS_DP_PORT_SEL_C;
		1525	break;
		1526	case PCH_DP_D:
		1527	trans_sel = TRANS_DP_PORT_SEL_D;
		1528	break;
		1529	default:
		1530	return true;
		1531	}
		1532
		1533	for_each_pipe(i) {
		1534	trans_dp = I915_READ(TRANS_DP_CTL(i));
		1535	if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
		1536	*pipe = i;
		1537	return true;
		1538	}
		1539	}
3243	Serge	1540
		1541	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
		1542	intel_dp->output_reg);
3031	serge	1543	}
		1544
		1545	return true;
2330	Serge	1546	}
2327	Serge	1547
4104	Serge	1548	static void intel_dp_get_config(struct intel_encoder *encoder,
		1549	struct intel_crtc_config *pipe_config)
		1550	{
		1551	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		1552	u32 tmp, flags = 0;
		1553	struct drm_device *dev = encoder->base.dev;
		1554	struct drm_i915_private *dev_priv = dev->dev_private;
		1555	enum port port = dp_to_dig_port(intel_dp)->port;
		1556	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4560	Serge	1557	int dotclock;
4104	Serge	1558
5060	serge	1559	tmp = I915_READ(intel_dp->output_reg);
		1560	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
		1561	pipe_config->has_audio = true;
		1562
4104	Serge	1563	if ((port == PORT_A) \|\| !HAS_PCH_CPT(dev)) {
		1564	if (tmp & DP_SYNC_HS_HIGH)
		1565	flags \|= DRM_MODE_FLAG_PHSYNC;
		1566	else
		1567	flags \|= DRM_MODE_FLAG_NHSYNC;
		1568
		1569	if (tmp & DP_SYNC_VS_HIGH)
		1570	flags \|= DRM_MODE_FLAG_PVSYNC;
		1571	else
		1572	flags \|= DRM_MODE_FLAG_NVSYNC;
		1573	} else {
		1574	tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		1575	if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
		1576	flags \|= DRM_MODE_FLAG_PHSYNC;
		1577	else
		1578	flags \|= DRM_MODE_FLAG_NHSYNC;
		1579
		1580	if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
		1581	flags \|= DRM_MODE_FLAG_PVSYNC;
		1582	else
		1583	flags \|= DRM_MODE_FLAG_NVSYNC;
		1584	}
		1585
		1586	pipe_config->adjusted_mode.flags \|= flags;
		1587
5139	serge	1588	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
		1589	tmp & DP_COLOR_RANGE_16_235)
		1590	pipe_config->limited_color_range = true;
		1591
4560	Serge	1592	pipe_config->has_dp_encoder = true;
		1593
		1594	intel_dp_get_m_n(crtc, pipe_config);
		1595
		1596	if (port == PORT_A) {
4104	Serge	1597	if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
		1598	pipe_config->port_clock = 162000;
		1599	else
		1600	pipe_config->port_clock = 270000;
		1601	}
4280	Serge	1602
4560	Serge	1603	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
		1604	&pipe_config->dp_m_n);
		1605
		1606	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		1607	ironlake_check_encoder_dotclock(pipe_config, dotclock);
		1608
		1609	pipe_config->adjusted_mode.crtc_clock = dotclock;
		1610
4280	Serge	1611	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
		1612	pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		1613	/*
		1614	* This is a big fat ugly hack.
		1615	*
		1616	* Some machines in UEFI boot mode provide us a VBT that has 18
		1617	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		1618	* unknown we fail to light up. Yet the same BIOS boots up with
		1619	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		1620	* max, not what it tells us to use.
		1621	*
		1622	* Note: This will still be broken if the eDP panel is not lit
		1623	* up by the BIOS, and thus we can't get the mode at module
		1624	* load.
		1625	*/
		1626	DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
		1627	pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		1628	dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
		1629	}
4104	Serge	1630	}
		1631
5060	serge	1632	static bool is_edp_psr(struct intel_dp *intel_dp)
4104	Serge	1633	{
5060	serge	1634	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
4104	Serge	1635	}
		1636
		1637	static bool intel_edp_is_psr_enabled(struct drm_device *dev)
		1638	{
		1639	struct drm_i915_private *dev_priv = dev->dev_private;
		1640
4560	Serge	1641	if (!HAS_PSR(dev))
4104	Serge	1642	return false;
		1643
4560	Serge	1644	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
4104	Serge	1645	}
		1646
		1647	static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
		1648	struct edp_vsc_psr *vsc_psr)
		1649	{
		1650	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1651	struct drm_device *dev = dig_port->base.base.dev;
		1652	struct drm_i915_private *dev_priv = dev->dev_private;
		1653	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
		1654	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
		1655	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
		1656	uint32_t data = (uint32_t ) vsc_psr;
		1657	unsigned int i;
		1658
		1659	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
		1660	the video DIP being updated before program video DIP data buffer
		1661	registers for DIP being updated. */
		1662	I915_WRITE(ctl_reg, 0);
		1663	POSTING_READ(ctl_reg);
		1664
		1665	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		1666	if (i < sizeof(struct edp_vsc_psr))
		1667	I915_WRITE(data_reg + i, *data++);
		1668	else
		1669	I915_WRITE(data_reg + i, 0);
		1670	}
		1671
		1672	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
		1673	POSTING_READ(ctl_reg);
		1674	}
		1675
		1676	static void intel_edp_psr_setup(struct intel_dp *intel_dp)
		1677	{
		1678	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1679	struct drm_i915_private *dev_priv = dev->dev_private;
		1680	struct edp_vsc_psr psr_vsc;
		1681
		1682	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
		1683	memset(&psr_vsc, 0, sizeof(psr_vsc));
		1684	psr_vsc.sdp_header.HB0 = 0;
		1685	psr_vsc.sdp_header.HB1 = 0x7;
		1686	psr_vsc.sdp_header.HB2 = 0x2;
		1687	psr_vsc.sdp_header.HB3 = 0x8;
		1688	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
		1689
		1690	/* Avoid continuous PSR exit by masking memup and hpd */
4560	Serge	1691	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP \|
4104	Serge	1692	EDP_PSR_DEBUG_MASK_HPD \| EDP_PSR_DEBUG_MASK_LPSP);
		1693	}
		1694
		1695	static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
		1696	{
5060	serge	1697	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1698	struct drm_device *dev = dig_port->base.base.dev;
4104	Serge	1699	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	1700	uint32_t aux_clock_divider;
4104	Serge	1701	int precharge = 0x3;
		1702	int msg_size = 5; /* Header(4) + Message(1) */
5060	serge	1703	bool only_standby = false;
4104	Serge	1704
5060	serge	1705	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
		1706
		1707	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		1708	only_standby = true;
		1709
4104	Serge	1710	/* Enable PSR in sink */
5060	serge	1711	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT \|\| only_standby)
		1712	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
		1713	DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
4104	Serge	1714	else
5060	serge	1715	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
		1716	DP_PSR_ENABLE \| DP_PSR_MAIN_LINK_ACTIVE);
4104	Serge	1717
		1718	/* Setup AUX registers */
4560	Serge	1719	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
		1720	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
		1721	I915_WRITE(EDP_PSR_AUX_CTL(dev),
4104	Serge	1722	DP_AUX_CH_CTL_TIME_OUT_400us \|
		1723	(msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		1724	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		1725	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
		1726	}
		1727
		1728	static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
		1729	{
5060	serge	1730	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1731	struct drm_device *dev = dig_port->base.base.dev;
4104	Serge	1732	struct drm_i915_private *dev_priv = dev->dev_private;
		1733	uint32_t max_sleep_time = 0x1f;
		1734	uint32_t idle_frames = 1;
		1735	uint32_t val = 0x0;
4560	Serge	1736	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
5060	serge	1737	bool only_standby = false;
4104	Serge	1738
5060	serge	1739	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		1740	only_standby = true;
		1741
		1742	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT \|\| only_standby) {
4104	Serge	1743	val \|= EDP_PSR_LINK_STANDBY;
		1744	val \|= EDP_PSR_TP2_TP3_TIME_0us;
		1745	val \|= EDP_PSR_TP1_TIME_0us;
		1746	val \|= EDP_PSR_SKIP_AUX_EXIT;
5060	serge	1747	val \|= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
4104	Serge	1748	} else
		1749	val \|= EDP_PSR_LINK_DISABLE;
		1750
4560	Serge	1751	I915_WRITE(EDP_PSR_CTL(dev), val \|
5060	serge	1752	(IS_BROADWELL(dev) ? 0 : link_entry_time) \|
4104	Serge	1753	max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT \|
		1754	idle_frames << EDP_PSR_IDLE_FRAME_SHIFT \|
		1755	EDP_PSR_ENABLE);
		1756	}
		1757
		1758	static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
		1759	{
		1760	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1761	struct drm_device *dev = dig_port->base.base.dev;
		1762	struct drm_i915_private *dev_priv = dev->dev_private;
		1763	struct drm_crtc *crtc = dig_port->base.base.crtc;
		1764	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1765
5060	serge	1766	lockdep_assert_held(&dev_priv->psr.lock);
		1767	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
		1768	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
		1769
4560	Serge	1770	dev_priv->psr.source_ok = false;
		1771
5060	serge	1772	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
4104	Serge	1773	DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		1774	return false;
		1775	}
		1776
5060	serge	1777	if (!i915.enable_psr) {
4104	Serge	1778	DRM_DEBUG_KMS("PSR disable by flag\n");
		1779	return false;
		1780	}
		1781
5060	serge	1782	/* Below limitations aren't valid for Broadwell */
		1783	if (IS_BROADWELL(dev))
		1784	goto out;
4104	Serge	1785
		1786	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
		1787	S3D_ENABLE) {
		1788	DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		1789	return false;
		1790	}
		1791
4560	Serge	1792	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
4104	Serge	1793	DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		1794	return false;
		1795	}
		1796
5060	serge	1797	out:
4560	Serge	1798	dev_priv->psr.source_ok = true;
4104	Serge	1799	return true;
		1800	}
		1801
		1802	static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
		1803	{
5060	serge	1804	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1805	struct drm_device *dev = intel_dig_port->base.base.dev;
		1806	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1807
5060	serge	1808	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
		1809	WARN_ON(dev_priv->psr.active);
		1810	lockdep_assert_held(&dev_priv->psr.lock);
4104	Serge	1811
		1812	/* Enable PSR on the panel */
		1813	intel_edp_psr_enable_sink(intel_dp);
		1814
		1815	/* Enable PSR on the host */
		1816	intel_edp_psr_enable_source(intel_dp);
5060	serge	1817
		1818	dev_priv->psr.active = true;
4104	Serge	1819	}
		1820
		1821	void intel_edp_psr_enable(struct intel_dp *intel_dp)
		1822	{
		1823	struct drm_device *dev = intel_dp_to_dev(intel_dp);
5060	serge	1824	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1825
5060	serge	1826	if (!HAS_PSR(dev)) {
		1827	DRM_DEBUG_KMS("PSR not supported on this platform\n");
		1828	return;
		1829	}
		1830
		1831	if (!is_edp_psr(intel_dp)) {
		1832	DRM_DEBUG_KMS("PSR not supported by this panel\n");
		1833	return;
		1834	}
		1835
		1836	mutex_lock(&dev_priv->psr.lock);
		1837	if (dev_priv->psr.enabled) {
		1838	DRM_DEBUG_KMS("PSR already in use\n");
		1839	mutex_unlock(&dev_priv->psr.lock);
		1840	return;
		1841	}
		1842
		1843	dev_priv->psr.busy_frontbuffer_bits = 0;
		1844
		1845	/* Setup PSR once */
		1846	intel_edp_psr_setup(intel_dp);
		1847
		1848	if (intel_edp_psr_match_conditions(intel_dp))
		1849	dev_priv->psr.enabled = intel_dp;
		1850	mutex_unlock(&dev_priv->psr.lock);
4104	Serge	1851	}
		1852
		1853	void intel_edp_psr_disable(struct intel_dp *intel_dp)
		1854	{
		1855	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1856	struct drm_i915_private *dev_priv = dev->dev_private;
		1857
5060	serge	1858	mutex_lock(&dev_priv->psr.lock);
		1859	if (!dev_priv->psr.enabled) {
		1860	mutex_unlock(&dev_priv->psr.lock);
4104	Serge	1861	return;
5060	serge	1862	}
4104	Serge	1863
5060	serge	1864	if (dev_priv->psr.active) {
4560	Serge	1865	I915_WRITE(EDP_PSR_CTL(dev),
		1866	I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
4104	Serge	1867
		1868	/* Wait till PSR is idle */
4560	Serge	1869	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
4104	Serge	1870	EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		1871	DRM_ERROR("Timed out waiting for PSR Idle State\n");
5060	serge	1872
		1873	dev_priv->psr.active = false;
		1874	} else {
		1875	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
		1876	}
		1877
		1878	dev_priv->psr.enabled = NULL;
		1879	mutex_unlock(&dev_priv->psr.lock);
		1880
		1881	cancel_delayed_work_sync(&dev_priv->psr.work);
4104	Serge	1882	}
		1883
5060	serge	1884	static void intel_edp_psr_work(struct work_struct *work)
4104	Serge	1885	{
5060	serge	1886	struct drm_i915_private *dev_priv =
		1887	container_of(work, typeof(*dev_priv), psr.work.work);
		1888	struct intel_dp *intel_dp = dev_priv->psr.enabled;
4104	Serge	1889
5060	serge	1890	mutex_lock(&dev_priv->psr.lock);
		1891	intel_dp = dev_priv->psr.enabled;
4104	Serge	1892
5060	serge	1893	if (!intel_dp)
		1894	goto unlock;
		1895
		1896	/*
		1897	* The delayed work can race with an invalidate hence we need to
		1898	* recheck. Since psr_flush first clears this and then reschedules we
		1899	* won't ever miss a flush when bailing out here.
		1900	*/
		1901	if (dev_priv->psr.busy_frontbuffer_bits)
		1902	goto unlock;
		1903
		1904	intel_edp_psr_do_enable(intel_dp);
		1905	unlock:
		1906	mutex_unlock(&dev_priv->psr.lock);
		1907	}
		1908
		1909	static void intel_edp_psr_do_exit(struct drm_device *dev)
		1910	{
		1911	struct drm_i915_private *dev_priv = dev->dev_private;
		1912
		1913	if (dev_priv->psr.active) {
		1914	u32 val = I915_READ(EDP_PSR_CTL(dev));
		1915
		1916	WARN_ON(!(val & EDP_PSR_ENABLE));
		1917
		1918	I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
		1919
		1920	dev_priv->psr.active = false;
		1921	}
		1922
		1923	}
		1924
		1925	void intel_edp_psr_invalidate(struct drm_device *dev,
		1926	unsigned frontbuffer_bits)
		1927	{
		1928	struct drm_i915_private *dev_priv = dev->dev_private;
		1929	struct drm_crtc *crtc;
		1930	enum pipe pipe;
		1931
		1932	mutex_lock(&dev_priv->psr.lock);
		1933	if (!dev_priv->psr.enabled) {
		1934	mutex_unlock(&dev_priv->psr.lock);
4104	Serge	1935	return;
5060	serge	1936	}
4104	Serge	1937
5060	serge	1938	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
		1939	pipe = to_intel_crtc(crtc)->pipe;
		1940
		1941	intel_edp_psr_do_exit(dev);
		1942
		1943	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
		1944
		1945	dev_priv->psr.busy_frontbuffer_bits \|= frontbuffer_bits;
		1946	mutex_unlock(&dev_priv->psr.lock);
		1947	}
		1948
		1949	void intel_edp_psr_flush(struct drm_device *dev,
		1950	unsigned frontbuffer_bits)
		1951	{
		1952	struct drm_i915_private *dev_priv = dev->dev_private;
		1953	struct drm_crtc *crtc;
		1954	enum pipe pipe;
		1955
		1956	mutex_lock(&dev_priv->psr.lock);
		1957	if (!dev_priv->psr.enabled) {
		1958	mutex_unlock(&dev_priv->psr.lock);
		1959	return;
4104	Serge	1960	}
5060	serge	1961
		1962	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
		1963	pipe = to_intel_crtc(crtc)->pipe;
		1964	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
		1965
		1966	/*
		1967	* On Haswell sprite plane updates don't result in a psr invalidating
		1968	* signal in the hardware. Which means we need to manually fake this in
		1969	* software for all flushes, not just when we've seen a preceding
		1970	* invalidation through frontbuffer rendering.
		1971	*/
		1972	if (IS_HASWELL(dev) &&
		1973	(frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
		1974	intel_edp_psr_do_exit(dev);
		1975
		1976	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
		1977	schedule_delayed_work(&dev_priv->psr.work,
		1978	msecs_to_jiffies(100));
		1979	mutex_unlock(&dev_priv->psr.lock);
4104	Serge	1980	}
		1981
5060	serge	1982	void intel_edp_psr_init(struct drm_device *dev)
		1983	{
		1984	struct drm_i915_private *dev_priv = dev->dev_private;
		1985
		1986	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
		1987	mutex_init(&dev_priv->psr.lock);
		1988	}
		1989
3031	serge	1990	static void intel_disable_dp(struct intel_encoder *encoder)
2330	Serge	1991	{
3031	serge	1992	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1993	enum port port = dp_to_dig_port(intel_dp)->port;
		1994	struct drm_device *dev = encoder->base.dev;
2327	Serge	1995
3031	serge	1996	/* Make sure the panel is off before trying to change the mode. But also
		1997	* ensure that we have vdd while we switch off the panel. */
5060	serge	1998	intel_edp_panel_vdd_on(intel_dp);
		1999	intel_edp_backlight_off(intel_dp);
4560	Serge	2000	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
5060	serge	2001	intel_edp_panel_off(intel_dp);
2330	Serge	2002
3031	serge	2003	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
4104	Serge	2004	if (!(port == PORT_A \|\| IS_VALLEYVIEW(dev)))
3031	serge	2005	intel_dp_link_down(intel_dp);
		2006	}
2330	Serge	2007
5060	serge	2008	static void g4x_post_disable_dp(struct intel_encoder *encoder)
3031	serge	2009	{
		2010	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	2011	enum port port = dp_to_dig_port(intel_dp)->port;
5060	serge	2012
		2013	if (port != PORT_A)
		2014	return;
		2015
		2016	intel_dp_link_down(intel_dp);
		2017	ironlake_edp_pll_off(intel_dp);
		2018	}
		2019
		2020	static void vlv_post_disable_dp(struct intel_encoder *encoder)
		2021	{
		2022	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2023
		2024	intel_dp_link_down(intel_dp);
		2025	}
		2026
		2027	static void chv_post_disable_dp(struct intel_encoder *encoder)
		2028	{
		2029	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2030	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3746	Serge	2031	struct drm_device *dev = encoder->base.dev;
5060	serge	2032	struct drm_i915_private *dev_priv = dev->dev_private;
		2033	struct intel_crtc *intel_crtc =
		2034	to_intel_crtc(encoder->base.crtc);
		2035	enum dpio_channel ch = vlv_dport_to_channel(dport);
		2036	enum pipe pipe = intel_crtc->pipe;
		2037	u32 val;
3031	serge	2038
		2039	intel_dp_link_down(intel_dp);
5060	serge	2040
		2041	mutex_lock(&dev_priv->dpio_lock);
		2042
		2043	/* Propagate soft reset to data lane reset */
		2044	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
		2045	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		2046	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
		2047
		2048	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		2049	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		2050	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
		2051
		2052	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
		2053	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		2054	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
		2055
		2056	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		2057	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		2058	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
		2059
		2060	mutex_unlock(&dev_priv->dpio_lock);
2330	Serge	2061	}
		2062
3031	serge	2063	static void intel_enable_dp(struct intel_encoder *encoder)
2330	Serge	2064	{
3031	serge	2065	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2066	struct drm_device *dev = encoder->base.dev;
2330	Serge	2067	struct drm_i915_private *dev_priv = dev->dev_private;
		2068	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		2069
3031	serge	2070	if (WARN_ON(dp_reg & DP_PORT_EN))
		2071	return;
2342	Serge	2072
5060	serge	2073	intel_edp_panel_vdd_on(intel_dp);
3031	serge	2074	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2330	Serge	2075	intel_dp_start_link_train(intel_dp);
5060	serge	2076	intel_edp_panel_on(intel_dp);
		2077	edp_panel_vdd_off(intel_dp, true);
2330	Serge	2078	intel_dp_complete_link_train(intel_dp);
3746	Serge	2079	intel_dp_stop_link_train(intel_dp);
4560	Serge	2080	}
		2081
		2082	static void g4x_enable_dp(struct intel_encoder *encoder)
		2083	{
		2084	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2085
		2086	intel_enable_dp(encoder);
5060	serge	2087	intel_edp_backlight_on(intel_dp);
2330	Serge	2088	}
		2089
4104	Serge	2090	static void vlv_enable_dp(struct intel_encoder *encoder)
		2091	{
4560	Serge	2092	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2093
5060	serge	2094	intel_edp_backlight_on(intel_dp);
4104	Serge	2095	}
		2096
4560	Serge	2097	static void g4x_pre_enable_dp(struct intel_encoder *encoder)
3031	serge	2098	{
		2099	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	2100	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3031	serge	2101
5060	serge	2102	intel_dp_prepare(encoder);
		2103
		2104	/* Only ilk+ has port A */
		2105	if (dport->port == PORT_A) {
		2106	ironlake_set_pll_cpu_edp(intel_dp);
3031	serge	2107	ironlake_edp_pll_on(intel_dp);
5060	serge	2108	}
3031	serge	2109	}
		2110
4104	Serge	2111	static void vlv_pre_enable_dp(struct intel_encoder *encoder)
		2112	{
		2113	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2114	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		2115	struct drm_device *dev = encoder->base.dev;
		2116	struct drm_i915_private *dev_priv = dev->dev_private;
		2117	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
4560	Serge	2118	enum dpio_channel port = vlv_dport_to_channel(dport);
4104	Serge	2119	int pipe = intel_crtc->pipe;
4560	Serge	2120	struct edp_power_seq power_seq;
4104	Serge	2121	u32 val;
		2122
		2123	mutex_lock(&dev_priv->dpio_lock);
		2124
4560	Serge	2125	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
4104	Serge	2126	val = 0;
		2127	if (pipe)
		2128	val \|= (1<<21);
		2129	else
		2130	val &= ~(1<<21);
		2131	val \|= 0x001000c4;
4560	Serge	2132	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
		2133	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
		2134	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
4104	Serge	2135
		2136	mutex_unlock(&dev_priv->dpio_lock);
		2137
5060	serge	2138	if (is_edp(intel_dp)) {
4560	Serge	2139	/* init power sequencer on this pipe and port */
		2140	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		2141	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
		2142	&power_seq);
5060	serge	2143	}
4560	Serge	2144
4104	Serge	2145	intel_enable_dp(encoder);
		2146
4560	Serge	2147	vlv_wait_port_ready(dev_priv, dport);
4539	Serge	2148	}
4104	Serge	2149
4560	Serge	2150	static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
4104	Serge	2151	{
		2152	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		2153	struct drm_device *dev = encoder->base.dev;
		2154	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	2155	struct intel_crtc *intel_crtc =
		2156	to_intel_crtc(encoder->base.crtc);
		2157	enum dpio_channel port = vlv_dport_to_channel(dport);
		2158	int pipe = intel_crtc->pipe;
4104	Serge	2159
5060	serge	2160	intel_dp_prepare(encoder);
		2161
4104	Serge	2162	/* Program Tx lane resets to default */
		2163	mutex_lock(&dev_priv->dpio_lock);
4560	Serge	2164	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
4104	Serge	2165	DPIO_PCS_TX_LANE2_RESET \|
		2166	DPIO_PCS_TX_LANE1_RESET);
4560	Serge	2167	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
4104	Serge	2168	DPIO_PCS_CLK_CRI_RXEB_EIOS_EN \|
		2169	DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN \|
		2170	(1<
		2171	DPIO_PCS_CLK_SOFT_RESET);
		2172
		2173	/* Fix up inter-pair skew failure */
4560	Serge	2174	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
		2175	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
		2176	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
4104	Serge	2177	mutex_unlock(&dev_priv->dpio_lock);
		2178	}
		2179
5060	serge	2180	static void chv_pre_enable_dp(struct intel_encoder *encoder)
		2181	{
		2182	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		2183	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		2184	struct drm_device *dev = encoder->base.dev;
		2185	struct drm_i915_private *dev_priv = dev->dev_private;
		2186	struct edp_power_seq power_seq;
		2187	struct intel_crtc *intel_crtc =
		2188	to_intel_crtc(encoder->base.crtc);
		2189	enum dpio_channel ch = vlv_dport_to_channel(dport);
		2190	int pipe = intel_crtc->pipe;
		2191	int data, i;
		2192	u32 val;
		2193
		2194	mutex_lock(&dev_priv->dpio_lock);
		2195
		2196	/* Deassert soft data lane reset*/
		2197	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
		2198	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		2199	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
		2200
		2201	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		2202	val \|= CHV_PCS_REQ_SOFTRESET_EN;
		2203	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
		2204
		2205	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
		2206	val \|= (DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		2207	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
		2208
		2209	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		2210	val \|= (DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
		2211	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
		2212
		2213	/* Program Tx lane latency optimal setting*/
		2214	for (i = 0; i < 4; i++) {
		2215	/* Set the latency optimal bit */
		2216	data = (i == 1) ? 0x0 : 0x6;
		2217	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
		2218	data << DPIO_FRC_LATENCY_SHFIT);
		2219
		2220	/* Set the upar bit */
		2221	data = (i == 1) ? 0x0 : 0x1;
		2222	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
		2223	data << DPIO_UPAR_SHIFT);
		2224	}
		2225
		2226	/* Data lane stagger programming */
		2227	/* FIXME: Fix up value only after power analysis */
		2228
		2229	mutex_unlock(&dev_priv->dpio_lock);
		2230
		2231	if (is_edp(intel_dp)) {
		2232	/* init power sequencer on this pipe and port */
		2233	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		2234	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
		2235	&power_seq);
		2236	}
		2237
		2238	intel_enable_dp(encoder);
		2239
		2240	vlv_wait_port_ready(dev_priv, dport);
		2241	}
		2242
		2243	static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
		2244	{
		2245	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		2246	struct drm_device *dev = encoder->base.dev;
		2247	struct drm_i915_private *dev_priv = dev->dev_private;
		2248	struct intel_crtc *intel_crtc =
		2249	to_intel_crtc(encoder->base.crtc);
		2250	enum dpio_channel ch = vlv_dport_to_channel(dport);
		2251	enum pipe pipe = intel_crtc->pipe;
		2252	u32 val;
		2253
		2254	mutex_lock(&dev_priv->dpio_lock);
		2255
		2256	/* program left/right clock distribution */
		2257	if (pipe != PIPE_B) {
		2258	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		2259	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
		2260	if (ch == DPIO_CH0)
		2261	val \|= CHV_BUFLEFTENA1_FORCE;
		2262	if (ch == DPIO_CH1)
		2263	val \|= CHV_BUFRIGHTENA1_FORCE;
		2264	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
		2265	} else {
		2266	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		2267	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
		2268	if (ch == DPIO_CH0)
		2269	val \|= CHV_BUFLEFTENA2_FORCE;
		2270	if (ch == DPIO_CH1)
		2271	val \|= CHV_BUFRIGHTENA2_FORCE;
		2272	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
		2273	}
		2274
		2275	/* program clock channel usage */
		2276	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
		2277	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		2278	if (pipe != PIPE_B)
		2279	val &= ~CHV_PCS_USEDCLKCHANNEL;
		2280	else
		2281	val \|= CHV_PCS_USEDCLKCHANNEL;
		2282	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
		2283
		2284	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		2285	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		2286	if (pipe != PIPE_B)
		2287	val &= ~CHV_PCS_USEDCLKCHANNEL;
		2288	else
		2289	val \|= CHV_PCS_USEDCLKCHANNEL;
		2290	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
		2291
		2292	/*
		2293	* This a a bit weird since generally CL
		2294	* matches the pipe, but here we need to
		2295	* pick the CL based on the port.
		2296	*/
		2297	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
		2298	if (pipe != PIPE_B)
		2299	val &= ~CHV_CMN_USEDCLKCHANNEL;
		2300	else
		2301	val \|= CHV_CMN_USEDCLKCHANNEL;
		2302	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
		2303
		2304	mutex_unlock(&dev_priv->dpio_lock);
		2305	}
		2306
2330	Serge	2307	/*
		2308	* Native read with retry for link status and receiver capability reads for
		2309	* cases where the sink may still be asleep.
5060	serge	2310	*
		2311	* Sinks are supposed to come up within 1ms from an off state, but we're also
		2312	* supposed to retry 3 times per the spec.
2330	Serge	2313	*/
5060	serge	2314	static ssize_t
		2315	intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
		2316	void *buffer, size_t size)
2330	Serge	2317	{
5060	serge	2318	ssize_t ret;
		2319	int i;
2330	Serge	2320
		2321	for (i = 0; i < 3; i++) {
5060	serge	2322	ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		2323	if (ret == size)
		2324	return ret;
2330	Serge	2325	msleep(1);
		2326	}
		2327
5060	serge	2328	return ret;
2330	Serge	2329	}
		2330
		2331	/*
		2332	* Fetch AUX CH registers 0x202 - 0x207 which contain
		2333	* link status information
		2334	*/
		2335	static bool
2342	Serge	2336	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	2337	{
5060	serge	2338	return intel_dp_dpcd_read_wake(&intel_dp->aux,
2330	Serge	2339	DP_LANE0_1_STATUS,
2342	Serge	2340	link_status,
5060	serge	2341	DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2330	Serge	2342	}
		2343
5060	serge	2344	/* These are source-specific values. */
2330	Serge	2345	static uint8_t
2342	Serge	2346	intel_dp_voltage_max(struct intel_dp *intel_dp)
2330	Serge	2347	{
3243	Serge	2348	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4104	Serge	2349	enum port port = dp_to_dig_port(intel_dp)->port;
2342	Serge	2350
5060	serge	2351	if (IS_VALLEYVIEW(dev))
4104	Serge	2352	return DP_TRAIN_VOLTAGE_SWING_1200;
		2353	else if (IS_GEN7(dev) && port == PORT_A)
2342	Serge	2354	return DP_TRAIN_VOLTAGE_SWING_800;
4104	Serge	2355	else if (HAS_PCH_CPT(dev) && port != PORT_A)
2342	Serge	2356	return DP_TRAIN_VOLTAGE_SWING_1200;
		2357	else
		2358	return DP_TRAIN_VOLTAGE_SWING_800;
		2359	}
		2360
		2361	static uint8_t
		2362	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
		2363	{
3243	Serge	2364	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4104	Serge	2365	enum port port = dp_to_dig_port(intel_dp)->port;
2342	Serge	2366
5060	serge	2367	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
2342	Serge	2368	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2369	case DP_TRAIN_VOLTAGE_SWING_400:
3243	Serge	2370	return DP_TRAIN_PRE_EMPHASIS_9_5;
		2371	case DP_TRAIN_VOLTAGE_SWING_600:
2342	Serge	2372	return DP_TRAIN_PRE_EMPHASIS_6;
3243	Serge	2373	case DP_TRAIN_VOLTAGE_SWING_800:
		2374	return DP_TRAIN_PRE_EMPHASIS_3_5;
		2375	case DP_TRAIN_VOLTAGE_SWING_1200:
		2376	default:
		2377	return DP_TRAIN_PRE_EMPHASIS_0;
		2378	}
4104	Serge	2379	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	2380	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2381	case DP_TRAIN_VOLTAGE_SWING_400:
4104	Serge	2382	return DP_TRAIN_PRE_EMPHASIS_9_5;
		2383	case DP_TRAIN_VOLTAGE_SWING_600:
3243	Serge	2384	return DP_TRAIN_PRE_EMPHASIS_6;
4104	Serge	2385	case DP_TRAIN_VOLTAGE_SWING_800:
		2386	return DP_TRAIN_PRE_EMPHASIS_3_5;
		2387	case DP_TRAIN_VOLTAGE_SWING_1200:
		2388	default:
		2389	return DP_TRAIN_PRE_EMPHASIS_0;
		2390	}
		2391	} else if (IS_GEN7(dev) && port == PORT_A) {
		2392	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2393	case DP_TRAIN_VOLTAGE_SWING_400:
		2394	return DP_TRAIN_PRE_EMPHASIS_6;
2342	Serge	2395	case DP_TRAIN_VOLTAGE_SWING_600:
		2396	case DP_TRAIN_VOLTAGE_SWING_800:
		2397	return DP_TRAIN_PRE_EMPHASIS_3_5;
		2398	default:
		2399	return DP_TRAIN_PRE_EMPHASIS_0;
		2400	}
		2401	} else {
2330	Serge	2402	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2403	case DP_TRAIN_VOLTAGE_SWING_400:
		2404	return DP_TRAIN_PRE_EMPHASIS_6;
		2405	case DP_TRAIN_VOLTAGE_SWING_600:
		2406	return DP_TRAIN_PRE_EMPHASIS_6;
		2407	case DP_TRAIN_VOLTAGE_SWING_800:
		2408	return DP_TRAIN_PRE_EMPHASIS_3_5;
		2409	case DP_TRAIN_VOLTAGE_SWING_1200:
		2410	default:
		2411	return DP_TRAIN_PRE_EMPHASIS_0;
		2412	}
2342	Serge	2413	}
2330	Serge	2414	}
		2415
4104	Serge	2416	static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
		2417	{
		2418	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		2419	struct drm_i915_private *dev_priv = dev->dev_private;
		2420	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
4560	Serge	2421	struct intel_crtc *intel_crtc =
		2422	to_intel_crtc(dport->base.base.crtc);
4104	Serge	2423	unsigned long demph_reg_value, preemph_reg_value,
		2424	uniqtranscale_reg_value;
		2425	uint8_t train_set = intel_dp->train_set[0];
4560	Serge	2426	enum dpio_channel port = vlv_dport_to_channel(dport);
		2427	int pipe = intel_crtc->pipe;
4104	Serge	2428
		2429	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		2430	case DP_TRAIN_PRE_EMPHASIS_0:
		2431	preemph_reg_value = 0x0004000;
		2432	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2433	case DP_TRAIN_VOLTAGE_SWING_400:
		2434	demph_reg_value = 0x2B405555;
		2435	uniqtranscale_reg_value = 0x552AB83A;
		2436	break;
		2437	case DP_TRAIN_VOLTAGE_SWING_600:
		2438	demph_reg_value = 0x2B404040;
		2439	uniqtranscale_reg_value = 0x5548B83A;
		2440	break;
		2441	case DP_TRAIN_VOLTAGE_SWING_800:
		2442	demph_reg_value = 0x2B245555;
		2443	uniqtranscale_reg_value = 0x5560B83A;
		2444	break;
		2445	case DP_TRAIN_VOLTAGE_SWING_1200:
		2446	demph_reg_value = 0x2B405555;
		2447	uniqtranscale_reg_value = 0x5598DA3A;
		2448	break;
		2449	default:
		2450	return 0;
		2451	}
		2452	break;
		2453	case DP_TRAIN_PRE_EMPHASIS_3_5:
		2454	preemph_reg_value = 0x0002000;
		2455	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2456	case DP_TRAIN_VOLTAGE_SWING_400:
		2457	demph_reg_value = 0x2B404040;
		2458	uniqtranscale_reg_value = 0x5552B83A;
		2459	break;
		2460	case DP_TRAIN_VOLTAGE_SWING_600:
		2461	demph_reg_value = 0x2B404848;
		2462	uniqtranscale_reg_value = 0x5580B83A;
		2463	break;
		2464	case DP_TRAIN_VOLTAGE_SWING_800:
		2465	demph_reg_value = 0x2B404040;
		2466	uniqtranscale_reg_value = 0x55ADDA3A;
		2467	break;
		2468	default:
		2469	return 0;
		2470	}
		2471	break;
		2472	case DP_TRAIN_PRE_EMPHASIS_6:
		2473	preemph_reg_value = 0x0000000;
		2474	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2475	case DP_TRAIN_VOLTAGE_SWING_400:
		2476	demph_reg_value = 0x2B305555;
		2477	uniqtranscale_reg_value = 0x5570B83A;
		2478	break;
		2479	case DP_TRAIN_VOLTAGE_SWING_600:
		2480	demph_reg_value = 0x2B2B4040;
		2481	uniqtranscale_reg_value = 0x55ADDA3A;
		2482	break;
		2483	default:
		2484	return 0;
		2485	}
		2486	break;
		2487	case DP_TRAIN_PRE_EMPHASIS_9_5:
		2488	preemph_reg_value = 0x0006000;
		2489	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2490	case DP_TRAIN_VOLTAGE_SWING_400:
		2491	demph_reg_value = 0x1B405555;
		2492	uniqtranscale_reg_value = 0x55ADDA3A;
		2493	break;
		2494	default:
		2495	return 0;
		2496	}
		2497	break;
		2498	default:
		2499	return 0;
		2500	}
		2501
		2502	mutex_lock(&dev_priv->dpio_lock);
4560	Serge	2503	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
		2504	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
		2505	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
4104	Serge	2506	uniqtranscale_reg_value);
4560	Serge	2507	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
		2508	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
		2509	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
		2510	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
4104	Serge	2511	mutex_unlock(&dev_priv->dpio_lock);
		2512
		2513	return 0;
		2514	}
		2515
5060	serge	2516	static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
		2517	{
		2518	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		2519	struct drm_i915_private *dev_priv = dev->dev_private;
		2520	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		2521	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
		2522	u32 deemph_reg_value, margin_reg_value, val;
		2523	uint8_t train_set = intel_dp->train_set[0];
		2524	enum dpio_channel ch = vlv_dport_to_channel(dport);
		2525	enum pipe pipe = intel_crtc->pipe;
		2526	int i;
		2527
		2528	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		2529	case DP_TRAIN_PRE_EMPHASIS_0:
		2530	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2531	case DP_TRAIN_VOLTAGE_SWING_400:
		2532	deemph_reg_value = 128;
		2533	margin_reg_value = 52;
		2534	break;
		2535	case DP_TRAIN_VOLTAGE_SWING_600:
		2536	deemph_reg_value = 128;
		2537	margin_reg_value = 77;
		2538	break;
		2539	case DP_TRAIN_VOLTAGE_SWING_800:
		2540	deemph_reg_value = 128;
		2541	margin_reg_value = 102;
		2542	break;
		2543	case DP_TRAIN_VOLTAGE_SWING_1200:
		2544	deemph_reg_value = 128;
		2545	margin_reg_value = 154;
		2546	/* FIXME extra to set for 1200 */
		2547	break;
		2548	default:
		2549	return 0;
		2550	}
		2551	break;
		2552	case DP_TRAIN_PRE_EMPHASIS_3_5:
		2553	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2554	case DP_TRAIN_VOLTAGE_SWING_400:
		2555	deemph_reg_value = 85;
		2556	margin_reg_value = 78;
		2557	break;
		2558	case DP_TRAIN_VOLTAGE_SWING_600:
		2559	deemph_reg_value = 85;
		2560	margin_reg_value = 116;
		2561	break;
		2562	case DP_TRAIN_VOLTAGE_SWING_800:
		2563	deemph_reg_value = 85;
		2564	margin_reg_value = 154;
		2565	break;
		2566	default:
		2567	return 0;
		2568	}
		2569	break;
		2570	case DP_TRAIN_PRE_EMPHASIS_6:
		2571	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2572	case DP_TRAIN_VOLTAGE_SWING_400:
		2573	deemph_reg_value = 64;
		2574	margin_reg_value = 104;
		2575	break;
		2576	case DP_TRAIN_VOLTAGE_SWING_600:
		2577	deemph_reg_value = 64;
		2578	margin_reg_value = 154;
		2579	break;
		2580	default:
		2581	return 0;
		2582	}
		2583	break;
		2584	case DP_TRAIN_PRE_EMPHASIS_9_5:
		2585	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2586	case DP_TRAIN_VOLTAGE_SWING_400:
		2587	deemph_reg_value = 43;
		2588	margin_reg_value = 154;
		2589	break;
		2590	default:
		2591	return 0;
		2592	}
		2593	break;
		2594	default:
		2595	return 0;
		2596	}
		2597
		2598	mutex_lock(&dev_priv->dpio_lock);
		2599
		2600	/* Clear calc init */
		2601	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		2602	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
		2603	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		2604
		2605	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		2606	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
		2607	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		2608
		2609	/* Program swing deemph */
		2610	for (i = 0; i < 4; i++) {
		2611	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		2612	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		2613	val \|= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		2614	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
		2615	}
		2616
		2617	/* Program swing margin */
		2618	for (i = 0; i < 4; i++) {
		2619	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
		2620	val &= ~DPIO_SWING_MARGIN_MASK;
		2621	val \|= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
		2622	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		2623	}
		2624
		2625	/* Disable unique transition scale */
		2626	for (i = 0; i < 4; i++) {
		2627	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		2628	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		2629	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		2630	}
		2631
		2632	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
		2633	== DP_TRAIN_PRE_EMPHASIS_0) &&
		2634	((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
		2635	== DP_TRAIN_VOLTAGE_SWING_1200)) {
		2636
		2637	/*
		2638	* The document said it needs to set bit 27 for ch0 and bit 26
		2639	* for ch1. Might be a typo in the doc.
		2640	* For now, for this unique transition scale selection, set bit
		2641	* 27 for ch0 and ch1.
		2642	*/
		2643	for (i = 0; i < 4; i++) {
		2644	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		2645	val \|= DPIO_TX_UNIQ_TRANS_SCALE_EN;
		2646	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		2647	}
		2648
		2649	for (i = 0; i < 4; i++) {
		2650	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
		2651	val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		2652	val \|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		2653	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		2654	}
		2655	}
		2656
		2657	/* Start swing calculation */
		2658	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
		2659	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		2660	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
		2661
		2662	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		2663	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
		2664	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
		2665
		2666	/* LRC Bypass */
		2667	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
		2668	val \|= DPIO_LRC_BYPASS;
		2669	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
		2670
		2671	mutex_unlock(&dev_priv->dpio_lock);
		2672
		2673	return 0;
		2674	}
		2675
2330	Serge	2676	static void
4560	Serge	2677	intel_get_adjust_train(struct intel_dp *intel_dp,
		2678	const uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	2679	{
		2680	uint8_t v = 0;
		2681	uint8_t p = 0;
		2682	int lane;
2342	Serge	2683	uint8_t voltage_max;
		2684	uint8_t preemph_max;
2330	Serge	2685
		2686	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3243	Serge	2687	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		2688	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2330	Serge	2689
		2690	if (this_v > v)
		2691	v = this_v;
		2692	if (this_p > p)
		2693	p = this_p;
		2694	}
		2695
2342	Serge	2696	voltage_max = intel_dp_voltage_max(intel_dp);
		2697	if (v >= voltage_max)
		2698	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
2330	Serge	2699
2342	Serge	2700	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
		2701	if (p >= preemph_max)
		2702	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2330	Serge	2703
		2704	for (lane = 0; lane < 4; lane++)
		2705	intel_dp->train_set[lane] = v \| p;
		2706	}
		2707
		2708	static uint32_t
3480	Serge	2709	intel_gen4_signal_levels(uint8_t train_set)
2330	Serge	2710	{
		2711	uint32_t signal_levels = 0;
		2712
		2713	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2714	case DP_TRAIN_VOLTAGE_SWING_400:
		2715	default:
		2716	signal_levels \|= DP_VOLTAGE_0_4;
		2717	break;
		2718	case DP_TRAIN_VOLTAGE_SWING_600:
		2719	signal_levels \|= DP_VOLTAGE_0_6;
		2720	break;
		2721	case DP_TRAIN_VOLTAGE_SWING_800:
		2722	signal_levels \|= DP_VOLTAGE_0_8;
		2723	break;
		2724	case DP_TRAIN_VOLTAGE_SWING_1200:
		2725	signal_levels \|= DP_VOLTAGE_1_2;
		2726	break;
		2727	}
		2728	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		2729	case DP_TRAIN_PRE_EMPHASIS_0:
		2730	default:
		2731	signal_levels \|= DP_PRE_EMPHASIS_0;
		2732	break;
		2733	case DP_TRAIN_PRE_EMPHASIS_3_5:
		2734	signal_levels \|= DP_PRE_EMPHASIS_3_5;
		2735	break;
		2736	case DP_TRAIN_PRE_EMPHASIS_6:
		2737	signal_levels \|= DP_PRE_EMPHASIS_6;
		2738	break;
		2739	case DP_TRAIN_PRE_EMPHASIS_9_5:
		2740	signal_levels \|= DP_PRE_EMPHASIS_9_5;
		2741	break;
		2742	}
		2743	return signal_levels;
		2744	}
		2745
		2746	/* Gen6's DP voltage swing and pre-emphasis control */
		2747	static uint32_t
		2748	intel_gen6_edp_signal_levels(uint8_t train_set)
		2749	{
		2750	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2751	DP_TRAIN_PRE_EMPHASIS_MASK);
		2752	switch (signal_levels) {
		2753	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2754	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2755	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		2756	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2757	return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
		2758	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2759	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		2760	return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
		2761	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2762	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2763	return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
		2764	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2765	case DP_TRAIN_VOLTAGE_SWING_1200 \| DP_TRAIN_PRE_EMPHASIS_0:
		2766	return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
		2767	default:
		2768	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2769	"0x%x\n", signal_levels);
		2770	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		2771	}
		2772	}
		2773
2342	Serge	2774	/* Gen7's DP voltage swing and pre-emphasis control */
		2775	static uint32_t
		2776	intel_gen7_edp_signal_levels(uint8_t train_set)
		2777	{
		2778	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2779	DP_TRAIN_PRE_EMPHASIS_MASK);
		2780	switch (signal_levels) {
		2781	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2782	return EDP_LINK_TRAIN_400MV_0DB_IVB;
		2783	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2784	return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
		2785	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2786	return EDP_LINK_TRAIN_400MV_6DB_IVB;
		2787
		2788	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2789	return EDP_LINK_TRAIN_600MV_0DB_IVB;
		2790	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2791	return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
		2792
		2793	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2794	return EDP_LINK_TRAIN_800MV_0DB_IVB;
		2795	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2796	return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
		2797
		2798	default:
		2799	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2800	"0x%x\n", signal_levels);
		2801	return EDP_LINK_TRAIN_500MV_0DB_IVB;
		2802	}
		2803	}
		2804
3243	Serge	2805	/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
		2806	static uint32_t
3480	Serge	2807	intel_hsw_signal_levels(uint8_t train_set)
2330	Serge	2808	{
3243	Serge	2809	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2810	DP_TRAIN_PRE_EMPHASIS_MASK);
		2811	switch (signal_levels) {
		2812	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2813	return DDI_BUF_EMP_400MV_0DB_HSW;
		2814	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2815	return DDI_BUF_EMP_400MV_3_5DB_HSW;
		2816	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2817	return DDI_BUF_EMP_400MV_6DB_HSW;
		2818	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_9_5:
		2819	return DDI_BUF_EMP_400MV_9_5DB_HSW;
2330	Serge	2820
3243	Serge	2821	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2822	return DDI_BUF_EMP_600MV_0DB_HSW;
		2823	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2824	return DDI_BUF_EMP_600MV_3_5DB_HSW;
		2825	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		2826	return DDI_BUF_EMP_600MV_6DB_HSW;
2330	Serge	2827
3243	Serge	2828	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2829	return DDI_BUF_EMP_800MV_0DB_HSW;
		2830	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2831	return DDI_BUF_EMP_800MV_3_5DB_HSW;
		2832	default:
		2833	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2834	"0x%x\n", signal_levels);
		2835	return DDI_BUF_EMP_400MV_0DB_HSW;
2330	Serge	2836	}
		2837	}
		2838
3480	Serge	2839	/* Properly updates "DP" with the correct signal levels. */
		2840	static void
		2841	intel_dp_set_signal_levels(struct intel_dp intel_dp, uint32_t DP)
		2842	{
		2843	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4104	Serge	2844	enum port port = intel_dig_port->port;
3480	Serge	2845	struct drm_device *dev = intel_dig_port->base.base.dev;
		2846	uint32_t signal_levels, mask;
		2847	uint8_t train_set = intel_dp->train_set[0];
		2848
5060	serge	2849	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
3480	Serge	2850	signal_levels = intel_hsw_signal_levels(train_set);
		2851	mask = DDI_BUF_EMP_MASK;
5060	serge	2852	} else if (IS_CHERRYVIEW(dev)) {
		2853	signal_levels = intel_chv_signal_levels(intel_dp);
		2854	mask = 0;
4104	Serge	2855	} else if (IS_VALLEYVIEW(dev)) {
		2856	signal_levels = intel_vlv_signal_levels(intel_dp);
		2857	mask = 0;
		2858	} else if (IS_GEN7(dev) && port == PORT_A) {
3480	Serge	2859	signal_levels = intel_gen7_edp_signal_levels(train_set);
		2860	mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4104	Serge	2861	} else if (IS_GEN6(dev) && port == PORT_A) {
3480	Serge	2862	signal_levels = intel_gen6_edp_signal_levels(train_set);
		2863	mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
		2864	} else {
		2865	signal_levels = intel_gen4_signal_levels(train_set);
		2866	mask = DP_VOLTAGE_MASK \| DP_PRE_EMPHASIS_MASK;
		2867	}
		2868
		2869	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
		2870
		2871	DP = (DP & ~mask) \| signal_levels;
		2872	}
		2873
2330	Serge	2874	static bool
		2875	intel_dp_set_link_train(struct intel_dp *intel_dp,
4560	Serge	2876	uint32_t *DP,
2330	Serge	2877	uint8_t dp_train_pat)
		2878	{
3243	Serge	2879	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		2880	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	2881	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2882	enum port port = intel_dig_port->port;
4560	Serge	2883	uint8_t buf[sizeof(intel_dp->train_set) + 1];
		2884	int ret, len;
2330	Serge	2885
3746	Serge	2886	if (HAS_DDI(dev)) {
		2887	uint32_t temp = I915_READ(DP_TP_CTL(port));
3243	Serge	2888
		2889	if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
		2890	temp \|= DP_TP_CTL_SCRAMBLE_DISABLE;
		2891	else
		2892	temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
		2893
		2894	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		2895	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2896	case DP_TRAINING_PATTERN_DISABLE:
		2897	temp \|= DP_TP_CTL_LINK_TRAIN_NORMAL;
		2898
		2899	break;
		2900	case DP_TRAINING_PATTERN_1:
		2901	temp \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		2902	break;
		2903	case DP_TRAINING_PATTERN_2:
		2904	temp \|= DP_TP_CTL_LINK_TRAIN_PAT2;
		2905	break;
		2906	case DP_TRAINING_PATTERN_3:
		2907	temp \|= DP_TP_CTL_LINK_TRAIN_PAT3;
		2908	break;
		2909	}
		2910	I915_WRITE(DP_TP_CTL(port), temp);
		2911
4104	Serge	2912	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| port != PORT_A)) {
4560	Serge	2913	*DP &= ~DP_LINK_TRAIN_MASK_CPT;
3031	serge	2914
		2915	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2916	case DP_TRAINING_PATTERN_DISABLE:
4560	Serge	2917	*DP \|= DP_LINK_TRAIN_OFF_CPT;
3031	serge	2918	break;
		2919	case DP_TRAINING_PATTERN_1:
4560	Serge	2920	*DP \|= DP_LINK_TRAIN_PAT_1_CPT;
3031	serge	2921	break;
		2922	case DP_TRAINING_PATTERN_2:
4560	Serge	2923	*DP \|= DP_LINK_TRAIN_PAT_2_CPT;
3031	serge	2924	break;
		2925	case DP_TRAINING_PATTERN_3:
		2926	DRM_ERROR("DP training pattern 3 not supported\n");
4560	Serge	2927	*DP \|= DP_LINK_TRAIN_PAT_2_CPT;
3031	serge	2928	break;
		2929	}
		2930
		2931	} else {
4560	Serge	2932	*DP &= ~DP_LINK_TRAIN_MASK;
3031	serge	2933
		2934	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2935	case DP_TRAINING_PATTERN_DISABLE:
4560	Serge	2936	*DP \|= DP_LINK_TRAIN_OFF;
3031	serge	2937	break;
		2938	case DP_TRAINING_PATTERN_1:
4560	Serge	2939	*DP \|= DP_LINK_TRAIN_PAT_1;
3031	serge	2940	break;
		2941	case DP_TRAINING_PATTERN_2:
4560	Serge	2942	*DP \|= DP_LINK_TRAIN_PAT_2;
3031	serge	2943	break;
		2944	case DP_TRAINING_PATTERN_3:
		2945	DRM_ERROR("DP training pattern 3 not supported\n");
4560	Serge	2946	*DP \|= DP_LINK_TRAIN_PAT_2;
3031	serge	2947	break;
		2948	}
		2949	}
		2950
4560	Serge	2951	I915_WRITE(intel_dp->output_reg, *DP);
2330	Serge	2952	POSTING_READ(intel_dp->output_reg);
		2953
4560	Serge	2954	buf[0] = dp_train_pat;
		2955	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
		2956	DP_TRAINING_PATTERN_DISABLE) {
		2957	/* don't write DP_TRAINING_LANEx_SET on disable */
		2958	len = 1;
		2959	} else {
		2960	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		2961	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		2962	len = intel_dp->lane_count + 1;
		2963	}
2330	Serge	2964
5060	serge	2965	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
4560	Serge	2966	buf, len);
		2967
		2968	return ret == len;
		2969	}
		2970
		2971	static bool
		2972	intel_dp_reset_link_train(struct intel_dp intel_dp, uint32_t DP,
		2973	uint8_t dp_train_pat)
		2974	{
		2975	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
		2976	intel_dp_set_signal_levels(intel_dp, DP);
		2977	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
		2978	}
		2979
		2980	static bool
		2981	intel_dp_update_link_train(struct intel_dp intel_dp, uint32_t DP,
		2982	const uint8_t link_status[DP_LINK_STATUS_SIZE])
		2983	{
		2984	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		2985	struct drm_device *dev = intel_dig_port->base.base.dev;
		2986	struct drm_i915_private *dev_priv = dev->dev_private;
		2987	int ret;
		2988
		2989	intel_get_adjust_train(intel_dp, link_status);
		2990	intel_dp_set_signal_levels(intel_dp, DP);
		2991
		2992	I915_WRITE(intel_dp->output_reg, *DP);
		2993	POSTING_READ(intel_dp->output_reg);
		2994
5060	serge	2995	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
		2996	intel_dp->train_set, intel_dp->lane_count);
2330	Serge	2997
4560	Serge	2998	return ret == intel_dp->lane_count;
2330	Serge	2999	}
		3000
3746	Serge	3001	static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
		3002	{
		3003	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3004	struct drm_device *dev = intel_dig_port->base.base.dev;
		3005	struct drm_i915_private *dev_priv = dev->dev_private;
		3006	enum port port = intel_dig_port->port;
		3007	uint32_t val;
		3008
		3009	if (!HAS_DDI(dev))
		3010	return;
		3011
		3012	val = I915_READ(DP_TP_CTL(port));
		3013	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		3014	val \|= DP_TP_CTL_LINK_TRAIN_IDLE;
		3015	I915_WRITE(DP_TP_CTL(port), val);
		3016
		3017	/*
		3018	* On PORT_A we can have only eDP in SST mode. There the only reason
		3019	* we need to set idle transmission mode is to work around a HW issue
		3020	* where we enable the pipe while not in idle link-training mode.
		3021	* In this case there is requirement to wait for a minimum number of
		3022	* idle patterns to be sent.
		3023	*/
		3024	if (port == PORT_A)
		3025	return;
		3026
		3027	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		3028	1))
		3029	DRM_ERROR("Timed out waiting for DP idle patterns\n");
		3030	}
		3031
2330	Serge	3032	/* Enable corresponding port and start training pattern 1 */
3243	Serge	3033	void
2330	Serge	3034	intel_dp_start_link_train(struct intel_dp *intel_dp)
		3035	{
3243	Serge	3036	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
		3037	struct drm_device *dev = encoder->dev;
2330	Serge	3038	int i;
		3039	uint8_t voltage;
2342	Serge	3040	int voltage_tries, loop_tries;
2330	Serge	3041	uint32_t DP = intel_dp->DP;
4560	Serge	3042	uint8_t link_config[2];
2330	Serge	3043
3480	Serge	3044	if (HAS_DDI(dev))
3243	Serge	3045	intel_ddi_prepare_link_retrain(encoder);
		3046
2330	Serge	3047	/* Write the link configuration data */
4560	Serge	3048	link_config[0] = intel_dp->link_bw;
		3049	link_config[1] = intel_dp->lane_count;
		3050	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		3051	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
5060	serge	3052	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2330	Serge	3053
4560	Serge	3054	link_config[0] = 0;
		3055	link_config[1] = DP_SET_ANSI_8B10B;
5060	serge	3056	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
4560	Serge	3057
2330	Serge	3058	DP \|= DP_PORT_EN;
2342	Serge	3059
4560	Serge	3060	/* clock recovery */
		3061	if (!intel_dp_reset_link_train(intel_dp, &DP,
		3062	DP_TRAINING_PATTERN_1 \|
		3063	DP_LINK_SCRAMBLING_DISABLE)) {
		3064	DRM_ERROR("failed to enable link training\n");
		3065	return;
		3066	}
		3067
2330	Serge	3068	voltage = 0xff;
2342	Serge	3069	voltage_tries = 0;
		3070	loop_tries = 0;
2330	Serge	3071	for (;;) {
2342	Serge	3072	uint8_t link_status[DP_LINK_STATUS_SIZE];
		3073
3243	Serge	3074	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2342	Serge	3075	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		3076	DRM_ERROR("failed to get link status\n");
2330	Serge	3077	break;
2342	Serge	3078	}
2330	Serge	3079
3243	Serge	3080	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2342	Serge	3081	DRM_DEBUG_KMS("clock recovery OK\n");
2330	Serge	3082	break;
		3083	}
		3084
		3085	/* Check to see if we've tried the max voltage */
		3086	for (i = 0; i < intel_dp->lane_count; i++)
		3087	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
		3088	break;
3480	Serge	3089	if (i == intel_dp->lane_count) {
2342	Serge	3090	++loop_tries;
		3091	if (loop_tries == 5) {
4560	Serge	3092	DRM_ERROR("too many full retries, give up\n");
2330	Serge	3093	break;
2342	Serge	3094	}
4560	Serge	3095	intel_dp_reset_link_train(intel_dp, &DP,
		3096	DP_TRAINING_PATTERN_1 \|
		3097	DP_LINK_SCRAMBLING_DISABLE);
2342	Serge	3098	voltage_tries = 0;
		3099	continue;
		3100	}
2330	Serge	3101
		3102	/* Check to see if we've tried the same voltage 5 times */
		3103	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2342	Serge	3104	++voltage_tries;
		3105	if (voltage_tries == 5) {
4560	Serge	3106	DRM_ERROR("too many voltage retries, give up\n");
2330	Serge	3107	break;
2342	Serge	3108	}
2330	Serge	3109	} else
2342	Serge	3110	voltage_tries = 0;
2330	Serge	3111	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
		3112
4560	Serge	3113	/* Update training set as requested by target */
		3114	if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
		3115	DRM_ERROR("failed to update link training\n");
		3116	break;
		3117	}
2330	Serge	3118	}
		3119
		3120	intel_dp->DP = DP;
		3121	}
		3122
3243	Serge	3123	void
2330	Serge	3124	intel_dp_complete_link_train(struct intel_dp *intel_dp)
		3125	{
		3126	bool channel_eq = false;
		3127	int tries, cr_tries;
		3128	uint32_t DP = intel_dp->DP;
5060	serge	3129	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2330	Serge	3130
5060	serge	3131	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
		3132	if (intel_dp->link_bw == DP_LINK_BW_5_4 \|\| intel_dp->use_tps3)
		3133	training_pattern = DP_TRAINING_PATTERN_3;
		3134
2330	Serge	3135	/* channel equalization */
4560	Serge	3136	if (!intel_dp_set_link_train(intel_dp, &DP,
5060	serge	3137	training_pattern \|
4560	Serge	3138	DP_LINK_SCRAMBLING_DISABLE)) {
		3139	DRM_ERROR("failed to start channel equalization\n");
		3140	return;
		3141	}
		3142
2330	Serge	3143	tries = 0;
		3144	cr_tries = 0;
		3145	channel_eq = false;
		3146	for (;;) {
2342	Serge	3147	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	3148
		3149	if (cr_tries > 5) {
		3150	DRM_ERROR("failed to train DP, aborting\n");
		3151	break;
		3152	}
		3153
3243	Serge	3154	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
4560	Serge	3155	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		3156	DRM_ERROR("failed to get link status\n");
2330	Serge	3157	break;
4560	Serge	3158	}
2330	Serge	3159
		3160	/* Make sure clock is still ok */
3243	Serge	3161	if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2330	Serge	3162	intel_dp_start_link_train(intel_dp);
4560	Serge	3163	intel_dp_set_link_train(intel_dp, &DP,
5060	serge	3164	training_pattern \|
4560	Serge	3165	DP_LINK_SCRAMBLING_DISABLE);
2330	Serge	3166	cr_tries++;
		3167	continue;
		3168	}
		3169
3243	Serge	3170	if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2330	Serge	3171	channel_eq = true;
		3172	break;
		3173	}
		3174
		3175	/* Try 5 times, then try clock recovery if that fails */
		3176	if (tries > 5) {
		3177	intel_dp_link_down(intel_dp);
		3178	intel_dp_start_link_train(intel_dp);
4560	Serge	3179	intel_dp_set_link_train(intel_dp, &DP,
5060	serge	3180	training_pattern \|
4560	Serge	3181	DP_LINK_SCRAMBLING_DISABLE);
2330	Serge	3182	tries = 0;
		3183	cr_tries++;
		3184	continue;
		3185	}
		3186
4560	Serge	3187	/* Update training set as requested by target */
		3188	if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
		3189	DRM_ERROR("failed to update link training\n");
		3190	break;
		3191	}
2330	Serge	3192	++tries;
		3193	}
		3194
3746	Serge	3195	intel_dp_set_idle_link_train(intel_dp);
		3196
		3197	intel_dp->DP = DP;
		3198
3243	Serge	3199	if (channel_eq)
3746	Serge	3200	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3243	Serge	3201
2330	Serge	3202	}
		3203
3746	Serge	3204	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
		3205	{
4560	Serge	3206	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3746	Serge	3207	DP_TRAINING_PATTERN_DISABLE);
		3208	}
		3209
2330	Serge	3210	static void
		3211	intel_dp_link_down(struct intel_dp *intel_dp)
		3212	{
3243	Serge	3213	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4104	Serge	3214	enum port port = intel_dig_port->port;
3243	Serge	3215	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	3216	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3217	struct intel_crtc *intel_crtc =
		3218	to_intel_crtc(intel_dig_port->base.base.crtc);
2330	Serge	3219	uint32_t DP = intel_dp->DP;
		3220
5060	serge	3221	if (WARN_ON(HAS_DDI(dev)))
3243	Serge	3222	return;
		3223
3031	serge	3224	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2330	Serge	3225	return;
		3226
		3227	DRM_DEBUG_KMS("\n");
		3228
4104	Serge	3229	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| port != PORT_A)) {
2330	Serge	3230	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		3231	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE_CPT);
		3232	} else {
		3233	DP &= ~DP_LINK_TRAIN_MASK;
		3234	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE);
		3235	}
		3236	POSTING_READ(intel_dp->output_reg);
		3237
3031	serge	3238	if (HAS_PCH_IBX(dev) &&
2330	Serge	3239	I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3243	Serge	3240	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2330	Serge	3241
		3242	/* Hardware workaround: leaving our transcoder select
		3243	* set to transcoder B while it's off will prevent the
		3244	* corresponding HDMI output on transcoder A.
		3245	*
		3246	* Combine this with another hardware workaround:
		3247	* transcoder select bit can only be cleared while the
		3248	* port is enabled.
		3249	*/
		3250	DP &= ~DP_PIPEB_SELECT;
		3251	I915_WRITE(intel_dp->output_reg, DP);
		3252
		3253	/* Changes to enable or select take place the vblank
		3254	* after being written.
		3255	*/
3480	Serge	3256	if (WARN_ON(crtc == NULL)) {
		3257	/* We should never try to disable a port without a crtc
		3258	* attached. For paranoia keep the code around for a
		3259	* bit. */
2330	Serge	3260	POSTING_READ(intel_dp->output_reg);
		3261	msleep(50);
		3262	} else
3480	Serge	3263	intel_wait_for_vblank(dev, intel_crtc->pipe);
2330	Serge	3264	}
		3265
2342	Serge	3266	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2330	Serge	3267	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
		3268	POSTING_READ(intel_dp->output_reg);
2342	Serge	3269	msleep(intel_dp->panel_power_down_delay);
2330	Serge	3270	}
		3271
		3272	static bool
		3273	intel_dp_get_dpcd(struct intel_dp *intel_dp)
		3274	{
4560	Serge	3275	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		3276	struct drm_device *dev = dig_port->base.base.dev;
		3277	struct drm_i915_private *dev_priv = dev->dev_private;
		3278
3480	Serge	3279	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
		3280
5060	serge	3281	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
		3282	sizeof(intel_dp->dpcd)) < 0)
3031	serge	3283	return false; /* aux transfer failed */
		3284
3480	Serge	3285	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
		3286	32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
		3287	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
		3288
3031	serge	3289	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		3290	return false; /* DPCD not present */
		3291
4104	Serge	3292	/* Check if the panel supports PSR */
		3293	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
4560	Serge	3294	if (is_edp(intel_dp)) {
5060	serge	3295	intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
4104	Serge	3296	intel_dp->psr_dpcd,
		3297	sizeof(intel_dp->psr_dpcd));
4560	Serge	3298	if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
		3299	dev_priv->psr.sink_support = true;
4104	Serge	3300	DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
4560	Serge	3301	}
		3302	}
		3303
5060	serge	3304	/* Training Pattern 3 support */
		3305	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
		3306	intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		3307	intel_dp->use_tps3 = true;
		3308	DRM_DEBUG_KMS("Displayport TPS3 supported");
		3309	} else
		3310	intel_dp->use_tps3 = false;
		3311
3031	serge	3312	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
		3313	DP_DWN_STRM_PORT_PRESENT))
		3314	return true; /* native DP sink */
		3315
		3316	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		3317	return true; /* no per-port downstream info */
		3318
5060	serge	3319	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3031	serge	3320	intel_dp->downstream_ports,
5060	serge	3321	DP_MAX_DOWNSTREAM_PORTS) < 0)
3031	serge	3322	return false; /* downstream port status fetch failed */
		3323
2330	Serge	3324	return true;
3031	serge	3325	}
2330	Serge	3326
3031	serge	3327	static void
		3328	intel_dp_probe_oui(struct intel_dp *intel_dp)
		3329	{
		3330	u8 buf[3];
		3331
		3332	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		3333	return;
		3334
5060	serge	3335	intel_edp_panel_vdd_on(intel_dp);
3031	serge	3336
5060	serge	3337	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3031	serge	3338	DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
		3339	buf[0], buf[1], buf[2]);
		3340
5060	serge	3341	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3031	serge	3342	DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
		3343	buf[0], buf[1], buf[2]);
		3344
5060	serge	3345	edp_panel_vdd_off(intel_dp, false);
2330	Serge	3346	}
		3347
2342	Serge	3348	static bool
5060	serge	3349	intel_dp_probe_mst(struct intel_dp *intel_dp)
		3350	{
		3351	u8 buf[1];
		3352
		3353	if (!intel_dp->can_mst)
		3354	return false;
		3355
		3356	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		3357	return false;
		3358
		3359	_edp_panel_vdd_on(intel_dp);
		3360	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		3361	if (buf[0] & DP_MST_CAP) {
		3362	DRM_DEBUG_KMS("Sink is MST capable\n");
		3363	intel_dp->is_mst = true;
		3364	} else {
		3365	DRM_DEBUG_KMS("Sink is not MST capable\n");
		3366	intel_dp->is_mst = false;
		3367	}
		3368	}
		3369	edp_panel_vdd_off(intel_dp, false);
		3370
		3371	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
		3372	return intel_dp->is_mst;
		3373	}
		3374
		3375	int intel_dp_sink_crc(struct intel_dp intel_dp, u8 crc)
		3376	{
		3377	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3378	struct drm_device *dev = intel_dig_port->base.base.dev;
		3379	struct intel_crtc *intel_crtc =
		3380	to_intel_crtc(intel_dig_port->base.base.crtc);
		3381	u8 buf[1];
		3382
		3383	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
		3384	return -EAGAIN;
		3385
		3386	if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
		3387	return -ENOTTY;
		3388
		3389	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
		3390	DP_TEST_SINK_START) < 0)
		3391	return -EAGAIN;
		3392
		3393	/* Wait 2 vblanks to be sure we will have the correct CRC value */
		3394	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3395	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3396
		3397	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
		3398	return -EAGAIN;
		3399
		3400	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
		3401	return 0;
		3402	}
		3403
		3404	static bool
2342	Serge	3405	intel_dp_get_sink_irq(struct intel_dp intel_dp, u8 sink_irq_vector)
		3406	{
5060	serge	3407	return intel_dp_dpcd_read_wake(&intel_dp->aux,
		3408	DP_DEVICE_SERVICE_IRQ_VECTOR,
		3409	sink_irq_vector, 1) == 1;
		3410	}
		3411
		3412	static bool
		3413	intel_dp_get_sink_irq_esi(struct intel_dp intel_dp, u8 sink_irq_vector)
		3414	{
2342	Serge	3415	int ret;
		3416
5060	serge	3417	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
		3418	DP_SINK_COUNT_ESI,
		3419	sink_irq_vector, 14);
		3420	if (ret != 14)
2342	Serge	3421	return false;
		3422
		3423	return true;
		3424	}
		3425
		3426	static void
		3427	intel_dp_handle_test_request(struct intel_dp *intel_dp)
		3428	{
		3429	/* NAK by default */
5060	serge	3430	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2342	Serge	3431	}
		3432
5060	serge	3433	static int
		3434	intel_dp_check_mst_status(struct intel_dp *intel_dp)
		3435	{
		3436	bool bret;
		3437
		3438	if (intel_dp->is_mst) {
		3439	u8 esi[16] = { 0 };
		3440	int ret = 0;
		3441	int retry;
		3442	bool handled;
		3443	bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
		3444	go_again:
		3445	if (bret == true) {
		3446
		3447	/* check link status - esi[10] = 0x200c */
		3448	if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
		3449	DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
		3450	intel_dp_start_link_train(intel_dp);
		3451	intel_dp_complete_link_train(intel_dp);
		3452	intel_dp_stop_link_train(intel_dp);
		3453	}
		3454
		3455	DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
		3456	ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
		3457
		3458	if (handled) {
		3459	for (retry = 0; retry < 3; retry++) {
		3460	int wret;
		3461	wret = drm_dp_dpcd_write(&intel_dp->aux,
		3462	DP_SINK_COUNT_ESI+1,
		3463	&esi[1], 3);
		3464	if (wret == 3) {
		3465	break;
		3466	}
		3467	}
		3468
		3469	bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
		3470	if (bret == true) {
		3471	DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
		3472	goto go_again;
		3473	}
		3474	} else
		3475	ret = 0;
		3476
		3477	return ret;
		3478	} else {
		3479	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3480	DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
		3481	intel_dp->is_mst = false;
		3482	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
		3483	/* send a hotplug event */
		3484	drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		3485	}
		3486	}
		3487	return -EINVAL;
		3488	}
		3489
2330	Serge	3490	/*
		3491	* According to DP spec
		3492	* 5.1.2:
		3493	* 1. Read DPCD
		3494	* 2. Configure link according to Receiver Capabilities
		3495	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
		3496	* 4. Check link status on receipt of hot-plug interrupt
		3497	*/
3243	Serge	3498	void
2330	Serge	3499	intel_dp_check_link_status(struct intel_dp *intel_dp)
		3500	{
5060	serge	3501	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3243	Serge	3502	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2342	Serge	3503	u8 sink_irq_vector;
		3504	u8 link_status[DP_LINK_STATUS_SIZE];
		3505
5060	serge	3506	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
		3507
3243	Serge	3508	if (!intel_encoder->connectors_active)
2330	Serge	3509	return;
		3510
3243	Serge	3511	if (WARN_ON(!intel_encoder->base.crtc))
2330	Serge	3512	return;
		3513
5060	serge	3514	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		3515	return;
		3516
2330	Serge	3517	/* Try to read receiver status if the link appears to be up */
2342	Serge	3518	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2330	Serge	3519	return;
		3520	}
		3521
		3522	/* Now read the DPCD to see if it's actually running */
		3523	if (!intel_dp_get_dpcd(intel_dp)) {
		3524	return;
		3525	}
		3526
2342	Serge	3527	/* Try to read the source of the interrupt */
		3528	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		3529	intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		3530	/* Clear interrupt source */
5060	serge	3531	drm_dp_dpcd_writeb(&intel_dp->aux,
2342	Serge	3532	DP_DEVICE_SERVICE_IRQ_VECTOR,
		3533	sink_irq_vector);
		3534
		3535	if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
		3536	intel_dp_handle_test_request(intel_dp);
		3537	if (sink_irq_vector & (DP_CP_IRQ \| DP_SINK_SPECIFIC_IRQ))
		3538	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
		3539	}
		3540
3243	Serge	3541	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2330	Serge	3542	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
5060	serge	3543	intel_encoder->base.name);
2330	Serge	3544	intel_dp_start_link_train(intel_dp);
		3545	intel_dp_complete_link_train(intel_dp);
3746	Serge	3546	intel_dp_stop_link_train(intel_dp);
2330	Serge	3547	}
		3548	}
		3549
3031	serge	3550	/* XXX this is probably wrong for multiple downstream ports */
2330	Serge	3551	static enum drm_connector_status
		3552	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
		3553	{
3031	serge	3554	uint8_t *dpcd = intel_dp->dpcd;
		3555	uint8_t type;
		3556
		3557	if (!intel_dp_get_dpcd(intel_dp))
		3558	return connector_status_disconnected;
		3559
		3560	/* if there's no downstream port, we're done */
		3561	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2330	Serge	3562	return connector_status_connected;
3031	serge	3563
		3564	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4560	Serge	3565	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		3566	intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3031	serge	3567	uint8_t reg;
5060	serge	3568
		3569	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
		3570	®, 1) < 0)
3031	serge	3571	return connector_status_unknown;
5060	serge	3572
3031	serge	3573	return DP_GET_SINK_COUNT(reg) ? connector_status_connected
		3574	: connector_status_disconnected;
		3575	}
		3576
		3577	/* If no HPD, poke DDC gently */
5060	serge	3578	if (drm_probe_ddc(&intel_dp->aux.ddc))
3031	serge	3579	return connector_status_connected;
		3580
		3581	/* Well we tried, say unknown for unreliable port types */
4560	Serge	3582	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3031	serge	3583	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4560	Serge	3584	if (type == DP_DS_PORT_TYPE_VGA \|\|
		3585	type == DP_DS_PORT_TYPE_NON_EDID)
3031	serge	3586	return connector_status_unknown;
4560	Serge	3587	} else {
		3588	type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
		3589	DP_DWN_STRM_PORT_TYPE_MASK;
		3590	if (type == DP_DWN_STRM_PORT_TYPE_ANALOG \|\|
		3591	type == DP_DWN_STRM_PORT_TYPE_OTHER)
5060	serge	3592	return connector_status_unknown;
4560	Serge	3593	}
3031	serge	3594
		3595	/* Anything else is out of spec, warn and ignore */
		3596	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2330	Serge	3597	return connector_status_disconnected;
		3598	}
		3599
		3600	static enum drm_connector_status
		3601	ironlake_dp_detect(struct intel_dp *intel_dp)
		3602	{
3243	Serge	3603	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3480	Serge	3604	struct drm_i915_private *dev_priv = dev->dev_private;
		3605	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2330	Serge	3606	enum drm_connector_status status;
		3607
		3608	/* Can't disconnect eDP, but you can close the lid... */
		3609	if (is_edp(intel_dp)) {
3243	Serge	3610	status = intel_panel_detect(dev);
2330	Serge	3611	if (status == connector_status_unknown)
		3612	status = connector_status_connected;
		3613	return status;
		3614	}
		3615
3480	Serge	3616	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		3617	return connector_status_disconnected;
		3618
2330	Serge	3619	return intel_dp_detect_dpcd(intel_dp);
		3620	}
		3621
5097	serge	3622	static int g4x_digital_port_connected(struct drm_device *dev,
		3623	struct intel_digital_port *intel_dig_port)
2330	Serge	3624	{
		3625	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	3626	uint32_t bit;
2330	Serge	3627
4560	Serge	3628	if (IS_VALLEYVIEW(dev)) {
		3629	switch (intel_dig_port->port) {
		3630	case PORT_B:
		3631	bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
		3632	break;
		3633	case PORT_C:
		3634	bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
		3635	break;
		3636	case PORT_D:
		3637	bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
		3638	break;
		3639	default:
5097	serge	3640	return -EINVAL;
4560	Serge	3641	}
		3642	} else {
3480	Serge	3643	switch (intel_dig_port->port) {
		3644	case PORT_B:
4560	Serge	3645	bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
2330	Serge	3646	break;
3480	Serge	3647	case PORT_C:
4560	Serge	3648	bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
2330	Serge	3649	break;
3480	Serge	3650	case PORT_D:
4560	Serge	3651	bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
2330	Serge	3652	break;
		3653	default:
5097	serge	3654	return -EINVAL;
2330	Serge	3655	}
4560	Serge	3656	}
2330	Serge	3657
3031	serge	3658	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
5097	serge	3659	return 0;
		3660	return 1;
		3661	}
		3662
		3663	static enum drm_connector_status
		3664	g4x_dp_detect(struct intel_dp *intel_dp)
		3665	{
		3666	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		3667	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3668	int ret;
		3669
		3670	/* Can't disconnect eDP, but you can close the lid... */
		3671	if (is_edp(intel_dp)) {
		3672	enum drm_connector_status status;
		3673
		3674	status = intel_panel_detect(dev);
		3675	if (status == connector_status_unknown)
		3676	status = connector_status_connected;
		3677	return status;
		3678	}
		3679
		3680	ret = g4x_digital_port_connected(dev, intel_dig_port);
		3681	if (ret == -EINVAL)
		3682	return connector_status_unknown;
		3683	else if (ret == 0)
2330	Serge	3684	return connector_status_disconnected;
		3685
		3686	return intel_dp_detect_dpcd(intel_dp);
		3687	}
		3688
2342	Serge	3689	static struct edid *
		3690	intel_dp_get_edid(struct drm_connector connector, struct i2c_adapter adapter)
		3691	{
3243	Serge	3692	struct intel_connector *intel_connector = to_intel_connector(connector);
		3693
		3694	/* use cached edid if we have one */
		3695	if (intel_connector->edid) {
		3696	/* invalid edid */
		3697	if (IS_ERR(intel_connector->edid))
3031	serge	3698	return NULL;
		3699
4560	Serge	3700	return drm_edid_duplicate(intel_connector->edid);
3031	serge	3701	}
		3702
3243	Serge	3703	return drm_get_edid(connector, adapter);
2342	Serge	3704	}
		3705
		3706	static int
		3707	intel_dp_get_edid_modes(struct drm_connector connector, struct i2c_adapter adapter)
		3708	{
3243	Serge	3709	struct intel_connector *intel_connector = to_intel_connector(connector);
2342	Serge	3710
3243	Serge	3711	/* use cached edid if we have one */
		3712	if (intel_connector->edid) {
		3713	/* invalid edid */
		3714	if (IS_ERR(intel_connector->edid))
		3715	return 0;
		3716
		3717	return intel_connector_update_modes(connector,
		3718	intel_connector->edid);
3031	serge	3719	}
		3720
3243	Serge	3721	return intel_ddc_get_modes(connector, adapter);
2342	Serge	3722	}
		3723
2330	Serge	3724	static enum drm_connector_status
		3725	intel_dp_detect(struct drm_connector *connector, bool force)
		3726	{
		3727	struct intel_dp *intel_dp = intel_attached_dp(connector);
3243	Serge	3728	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3729	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		3730	struct drm_device *dev = connector->dev;
4560	Serge	3731	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	3732	enum drm_connector_status status;
5060	serge	3733	enum intel_display_power_domain power_domain;
2330	Serge	3734	struct edid *edid = NULL;
5060	serge	3735	bool ret;
2330	Serge	3736
5060	serge	3737	power_domain = intel_display_port_power_domain(intel_encoder);
		3738	intel_display_power_get(dev_priv, power_domain);
4560	Serge	3739
4104	Serge	3740	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	3741	connector->base.id, connector->name);
4104	Serge	3742
5060	serge	3743	if (intel_dp->is_mst) {
		3744	/* MST devices are disconnected from a monitor POV */
		3745	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		3746	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		3747	status = connector_status_disconnected;
		3748	goto out;
		3749	}
		3750
2330	Serge	3751	intel_dp->has_audio = false;
		3752
		3753	if (HAS_PCH_SPLIT(dev))
		3754	status = ironlake_dp_detect(intel_dp);
		3755	else
		3756	status = g4x_dp_detect(intel_dp);
		3757
		3758	if (status != connector_status_connected)
4560	Serge	3759	goto out;
3031	serge	3760
		3761	intel_dp_probe_oui(intel_dp);
		3762
5060	serge	3763	ret = intel_dp_probe_mst(intel_dp);
		3764	if (ret) {
		3765	/* if we are in MST mode then this connector
		3766	won't appear connected or have anything with EDID on it */
		3767	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		3768	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		3769	status = connector_status_disconnected;
		3770	goto out;
		3771	}
		3772
3243	Serge	3773	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		3774	intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2330	Serge	3775	} else {
5060	serge	3776	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
2330	Serge	3777	if (edid) {
		3778	intel_dp->has_audio = drm_detect_monitor_audio(edid);
		3779	kfree(edid);
		3780	}
		3781	}
3243	Serge	3782
		3783	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		3784	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4560	Serge	3785	status = connector_status_connected;
		3786
		3787	out:
5060	serge	3788	intel_display_power_put(dev_priv, power_domain);
4560	Serge	3789	return status;
2330	Serge	3790	}
		3791
		3792	static int intel_dp_get_modes(struct drm_connector *connector)
		3793	{
		3794	struct intel_dp *intel_dp = intel_attached_dp(connector);
5060	serge	3795	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3796	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3243	Serge	3797	struct intel_connector *intel_connector = to_intel_connector(connector);
		3798	struct drm_device *dev = connector->dev;
5060	serge	3799	struct drm_i915_private *dev_priv = dev->dev_private;
		3800	enum intel_display_power_domain power_domain;
2330	Serge	3801	int ret;
		3802
		3803	/* We should parse the EDID data and find out if it has an audio sink
		3804	*/
		3805
5060	serge	3806	power_domain = intel_display_port_power_domain(intel_encoder);
		3807	intel_display_power_get(dev_priv, power_domain);
		3808
		3809	ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
		3810	intel_display_power_put(dev_priv, power_domain);
3243	Serge	3811	if (ret)
2330	Serge	3812	return ret;
		3813
3243	Serge	3814	/* if eDP has no EDID, fall back to fixed mode */
		3815	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2330	Serge	3816	struct drm_display_mode *mode;
3243	Serge	3817	mode = drm_mode_duplicate(dev,
		3818	intel_connector->panel.fixed_mode);
		3819	if (mode) {
2330	Serge	3820	drm_mode_probed_add(connector, mode);
		3821	return 1;
		3822	}
		3823	}
		3824	return 0;
		3825	}
		3826
3243	Serge	3827	static bool
		3828	intel_dp_detect_audio(struct drm_connector *connector)
		3829	{
		3830	struct intel_dp *intel_dp = intel_attached_dp(connector);
5060	serge	3831	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3832	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		3833	struct drm_device *dev = connector->dev;
		3834	struct drm_i915_private *dev_priv = dev->dev_private;
		3835	enum intel_display_power_domain power_domain;
3243	Serge	3836	struct edid *edid;
		3837	bool has_audio = false;
2330	Serge	3838
5060	serge	3839	power_domain = intel_display_port_power_domain(intel_encoder);
		3840	intel_display_power_get(dev_priv, power_domain);
		3841
		3842	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3243	Serge	3843	if (edid) {
		3844	has_audio = drm_detect_monitor_audio(edid);
		3845	kfree(edid);
		3846	}
2330	Serge	3847
5060	serge	3848	intel_display_power_put(dev_priv, power_domain);
		3849
3243	Serge	3850	return has_audio;
		3851	}
2330	Serge	3852
		3853	static int
		3854	intel_dp_set_property(struct drm_connector *connector,
		3855	struct drm_property *property,
		3856	uint64_t val)
		3857	{
		3858	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3243	Serge	3859	struct intel_connector *intel_connector = to_intel_connector(connector);
		3860	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
		3861	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2330	Serge	3862	int ret;
		3863
3243	Serge	3864	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	3865	if (ret)
		3866	return ret;
3480	Serge	3867
2330	Serge	3868	if (property == dev_priv->force_audio_property) {
		3869	int i = val;
		3870	bool has_audio;
		3871
		3872	if (i == intel_dp->force_audio)
		3873	return 0;
		3874
		3875	intel_dp->force_audio = i;
		3876
3031	serge	3877	if (i == HDMI_AUDIO_AUTO)
2330	Serge	3878	has_audio = intel_dp_detect_audio(connector);
		3879	else
3031	serge	3880	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	3881
		3882	if (has_audio == intel_dp->has_audio)
		3883	return 0;
		3884
		3885	intel_dp->has_audio = has_audio;
		3886	goto done;
		3887	}
		3888
		3889	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	3890	bool old_auto = intel_dp->color_range_auto;
		3891	uint32_t old_range = intel_dp->color_range;
		3892
3480	Serge	3893	switch (val) {
		3894	case INTEL_BROADCAST_RGB_AUTO:
		3895	intel_dp->color_range_auto = true;
		3896	break;
		3897	case INTEL_BROADCAST_RGB_FULL:
		3898	intel_dp->color_range_auto = false;
		3899	intel_dp->color_range = 0;
		3900	break;
		3901	case INTEL_BROADCAST_RGB_LIMITED:
		3902	intel_dp->color_range_auto = false;
		3903	intel_dp->color_range = DP_COLOR_RANGE_16_235;
		3904	break;
		3905	default:
		3906	return -EINVAL;
		3907	}
3746	Serge	3908
		3909	if (old_auto == intel_dp->color_range_auto &&
		3910	old_range == intel_dp->color_range)
		3911	return 0;
		3912
2330	Serge	3913	goto done;
		3914	}
		3915
3243	Serge	3916	if (is_edp(intel_dp) &&
		3917	property == connector->dev->mode_config.scaling_mode_property) {
		3918	if (val == DRM_MODE_SCALE_NONE) {
		3919	DRM_DEBUG_KMS("no scaling not supported\n");
		3920	return -EINVAL;
		3921	}
		3922
		3923	if (intel_connector->panel.fitting_mode == val) {
		3924	/* the eDP scaling property is not changed */
		3925	return 0;
		3926	}
		3927	intel_connector->panel.fitting_mode = val;
		3928
		3929	goto done;
		3930	}
		3931
2330	Serge	3932	return -EINVAL;
		3933
		3934	done:
3480	Serge	3935	if (intel_encoder->base.crtc)
		3936	intel_crtc_restore_mode(intel_encoder->base.crtc);
2330	Serge	3937
		3938	return 0;
		3939	}
		3940
		3941	static void
4104	Serge	3942	intel_dp_connector_destroy(struct drm_connector *connector)
2330	Serge	3943	{
3243	Serge	3944	struct intel_connector *intel_connector = to_intel_connector(connector);
2330	Serge	3945
3243	Serge	3946	if (!IS_ERR_OR_NULL(intel_connector->edid))
		3947	kfree(intel_connector->edid);
		3948
4104	Serge	3949	/* Can't call is_edp() since the encoder may have been destroyed
		3950	* already. */
		3951	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3243	Serge	3952	intel_panel_fini(&intel_connector->panel);
2330	Serge	3953
		3954	drm_connector_cleanup(connector);
		3955	kfree(connector);
		3956	}
		3957
3243	Serge	3958	void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3959	{
3243	Serge	3960	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		3961	struct intel_dp *intel_dp = &intel_dig_port->dp;
3480	Serge	3962	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	3963
5060	serge	3964	drm_dp_aux_unregister(&intel_dp->aux);
		3965	intel_dp_mst_encoder_cleanup(intel_dig_port);
2330	Serge	3966	drm_encoder_cleanup(encoder);
2342	Serge	3967	if (is_edp(intel_dp)) {
4293	Serge	3968	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5060	serge	3969	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
		3970	edp_panel_vdd_off_sync(intel_dp);
		3971	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2342	Serge	3972	}
3243	Serge	3973	kfree(intel_dig_port);
2330	Serge	3974	}
		3975
5060	serge	3976	static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
		3977	{
		3978	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
		3979
		3980	if (!is_edp(intel_dp))
		3981	return;
		3982
		3983	edp_panel_vdd_off_sync(intel_dp);
		3984	}
		3985
		3986	static void intel_dp_encoder_reset(struct drm_encoder *encoder)
		3987	{
		3988	intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
		3989	}
		3990
2330	Serge	3991	static const struct drm_connector_funcs intel_dp_connector_funcs = {
3031	serge	3992	.dpms = intel_connector_dpms,
2330	Serge	3993	.detect = intel_dp_detect,
		3994	.fill_modes = drm_helper_probe_single_connector_modes,
		3995	.set_property = intel_dp_set_property,
4104	Serge	3996	.destroy = intel_dp_connector_destroy,
2330	Serge	3997	};
		3998
		3999	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
		4000	.get_modes = intel_dp_get_modes,
		4001	.mode_valid = intel_dp_mode_valid,
		4002	.best_encoder = intel_best_encoder,
		4003	};
		4004
		4005	static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5060	serge	4006	.reset = intel_dp_encoder_reset,
2330	Serge	4007	.destroy = intel_dp_encoder_destroy,
		4008	};
		4009
5060	serge	4010	void
2330	Serge	4011	intel_dp_hot_plug(struct intel_encoder *intel_encoder)
		4012	{
5060	serge	4013	return;
		4014	}
2330	Serge	4015
5060	serge	4016	bool
		4017	intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
		4018	{
		4019	struct intel_dp *intel_dp = &intel_dig_port->dp;
		4020	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		4021	struct drm_device *dev = intel_dig_port->base.base.dev;
		4022	struct drm_i915_private *dev_priv = dev->dev_private;
		4023	enum intel_display_power_domain power_domain;
		4024	bool ret = true;
		4025
		4026	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		4027	intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
		4028
		4029	DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
		4030	long_hpd ? "long" : "short");
		4031
		4032	power_domain = intel_display_port_power_domain(intel_encoder);
		4033	intel_display_power_get(dev_priv, power_domain);
		4034
		4035	if (long_hpd) {
5097	serge	4036
		4037	if (HAS_PCH_SPLIT(dev)) {
5060	serge	4038	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		4039	goto mst_fail;
5097	serge	4040	} else {
		4041	if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
		4042	goto mst_fail;
		4043	}
5060	serge	4044
		4045	if (!intel_dp_get_dpcd(intel_dp)) {
		4046	goto mst_fail;
		4047	}
		4048
		4049	intel_dp_probe_oui(intel_dp);
		4050
		4051	if (!intel_dp_probe_mst(intel_dp))
		4052	goto mst_fail;
		4053
		4054	} else {
		4055	if (intel_dp->is_mst) {
		4056	if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
		4057	goto mst_fail;
		4058	}
		4059
		4060	if (!intel_dp->is_mst) {
		4061	/*
		4062	* we'll check the link status via the normal hot plug path later -
		4063	* but for short hpds we should check it now
		4064	*/
		4065	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
		4066	intel_dp_check_link_status(intel_dp);
		4067	drm_modeset_unlock(&dev->mode_config.connection_mutex);
		4068	}
		4069	}
		4070	ret = false;
		4071	goto put_power;
		4072	mst_fail:
		4073	/* if we were in MST mode, and device is not there get out of MST mode */
		4074	if (intel_dp->is_mst) {
		4075	DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		4076	intel_dp->is_mst = false;
		4077	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
		4078	}
		4079	put_power:
		4080	intel_display_power_put(dev_priv, power_domain);
		4081
		4082	return ret;
2330	Serge	4083	}
		4084
2327	Serge	4085	/* Return which DP Port should be selected for Transcoder DP control */
		4086	int
2342	Serge	4087	intel_trans_dp_port_sel(struct drm_crtc *crtc)
2327	Serge	4088	{
		4089	struct drm_device *dev = crtc->dev;
3243	Serge	4090	struct intel_encoder *intel_encoder;
		4091	struct intel_dp *intel_dp;
2327	Serge	4092
3243	Serge	4093	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		4094	intel_dp = enc_to_intel_dp(&intel_encoder->base);
2327	Serge	4095
3243	Serge	4096	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		4097	intel_encoder->type == INTEL_OUTPUT_EDP)
2327	Serge	4098	return intel_dp->output_reg;
		4099	}
		4100
		4101	return -1;
		4102	}
2330	Serge	4103
		4104	/* check the VBT to see whether the eDP is on DP-D port */
4560	Serge	4105	bool intel_dp_is_edp(struct drm_device *dev, enum port port)
2330	Serge	4106	{
		4107	struct drm_i915_private *dev_priv = dev->dev_private;
4560	Serge	4108	union child_device_config *p_child;
2330	Serge	4109	int i;
4560	Serge	4110	static const short port_mapping[] = {
		4111	[PORT_B] = PORT_IDPB,
		4112	[PORT_C] = PORT_IDPC,
		4113	[PORT_D] = PORT_IDPD,
		4114	};
2330	Serge	4115
4560	Serge	4116	if (port == PORT_A)
		4117	return true;
		4118
4104	Serge	4119	if (!dev_priv->vbt.child_dev_num)
2330	Serge	4120	return false;
		4121
4104	Serge	4122	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		4123	p_child = dev_priv->vbt.child_dev + i;
2330	Serge	4124
4560	Serge	4125	if (p_child->common.dvo_port == port_mapping[port] &&
		4126	(p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		4127	(DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
2330	Serge	4128	return true;
		4129	}
		4130	return false;
		4131	}
		4132
5060	serge	4133	void
2330	Serge	4134	intel_dp_add_properties(struct intel_dp intel_dp, struct drm_connector connector)
		4135	{
3243	Serge	4136	struct intel_connector *intel_connector = to_intel_connector(connector);
		4137
2330	Serge	4138	intel_attach_force_audio_property(connector);
		4139	intel_attach_broadcast_rgb_property(connector);
3480	Serge	4140	intel_dp->color_range_auto = true;
3243	Serge	4141
		4142	if (is_edp(intel_dp)) {
		4143	drm_mode_create_scaling_mode_property(connector->dev);
		4144	drm_object_attach_property(
		4145	&connector->base,
		4146	connector->dev->mode_config.scaling_mode_property,
		4147	DRM_MODE_SCALE_ASPECT);
		4148	intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
		4149	}
2330	Serge	4150	}
		4151
5060	serge	4152	static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
		4153	{
		4154	intel_dp->last_power_cycle = jiffies;
		4155	intel_dp->last_power_on = jiffies;
		4156	intel_dp->last_backlight_off = jiffies;
		4157	}
		4158
3243	Serge	4159	static void
		4160	intel_dp_init_panel_power_sequencer(struct drm_device *dev,
		4161	struct intel_dp *intel_dp,
		4162	struct edp_power_seq *out)
		4163	{
		4164	struct drm_i915_private *dev_priv = dev->dev_private;
		4165	struct edp_power_seq cur, vbt, spec, final;
		4166	u32 pp_on, pp_off, pp_div, pp;
4560	Serge	4167	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3243	Serge	4168
3746	Serge	4169	if (HAS_PCH_SPLIT(dev)) {
4560	Serge	4170	pp_ctrl_reg = PCH_PP_CONTROL;
3746	Serge	4171	pp_on_reg = PCH_PP_ON_DELAYS;
		4172	pp_off_reg = PCH_PP_OFF_DELAYS;
		4173	pp_div_reg = PCH_PP_DIVISOR;
		4174	} else {
4560	Serge	4175	enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
		4176
		4177	pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		4178	pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		4179	pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		4180	pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3746	Serge	4181	}
		4182
3243	Serge	4183	/* Workaround: Need to write PP_CONTROL with the unlock key as
		4184	* the very first thing. */
3746	Serge	4185	pp = ironlake_get_pp_control(intel_dp);
4560	Serge	4186	I915_WRITE(pp_ctrl_reg, pp);
3243	Serge	4187
3746	Serge	4188	pp_on = I915_READ(pp_on_reg);
		4189	pp_off = I915_READ(pp_off_reg);
		4190	pp_div = I915_READ(pp_div_reg);
3243	Serge	4191
		4192	/* Pull timing values out of registers */
		4193	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		4194	PANEL_POWER_UP_DELAY_SHIFT;
		4195
		4196	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		4197	PANEL_LIGHT_ON_DELAY_SHIFT;
		4198
		4199	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		4200	PANEL_LIGHT_OFF_DELAY_SHIFT;
		4201
		4202	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		4203	PANEL_POWER_DOWN_DELAY_SHIFT;
		4204
		4205	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		4206	PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
		4207
		4208	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		4209	cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
		4210
4104	Serge	4211	vbt = dev_priv->vbt.edp_pps;
3243	Serge	4212
		4213	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
		4214	* our hw here, which are all in 100usec. */
		4215	spec.t1_t3 = 210 * 10;
		4216	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
		4217	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
		4218	spec.t10 = 500 * 10;
		4219	/* This one is special and actually in units of 100ms, but zero
		4220	* based in the hw (so we need to add 100 ms). But the sw vbt
		4221	* table multiplies it with 1000 to make it in units of 100usec,
		4222	* too. */
		4223	spec.t11_t12 = (510 + 100) * 10;
		4224
		4225	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		4226	vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
		4227
		4228	/* Use the max of the register settings and vbt. If both are
		4229	* unset, fall back to the spec limits. */
		4230	#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
		4231	spec.field : \
		4232	max(cur.field, vbt.field))
		4233	assign_final(t1_t3);
		4234	assign_final(t8);
		4235	assign_final(t9);
		4236	assign_final(t10);
		4237	assign_final(t11_t12);
		4238	#undef assign_final
		4239
		4240	#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
		4241	intel_dp->panel_power_up_delay = get_delay(t1_t3);
		4242	intel_dp->backlight_on_delay = get_delay(t8);
		4243	intel_dp->backlight_off_delay = get_delay(t9);
		4244	intel_dp->panel_power_down_delay = get_delay(t10);
		4245	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
		4246	#undef get_delay
		4247
		4248	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		4249	intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		4250	intel_dp->panel_power_cycle_delay);
		4251
		4252	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		4253	intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
		4254
		4255	if (out)
		4256	*out = final;
		4257	}
		4258
		4259	static void
		4260	intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
		4261	struct intel_dp *intel_dp,
		4262	struct edp_power_seq *seq)
		4263	{
		4264	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4265	u32 pp_on, pp_off, pp_div, port_sel = 0;
		4266	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
		4267	int pp_on_reg, pp_off_reg, pp_div_reg;
3243	Serge	4268
3746	Serge	4269	if (HAS_PCH_SPLIT(dev)) {
		4270	pp_on_reg = PCH_PP_ON_DELAYS;
		4271	pp_off_reg = PCH_PP_OFF_DELAYS;
		4272	pp_div_reg = PCH_PP_DIVISOR;
		4273	} else {
4560	Serge	4274	enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
		4275
		4276	pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		4277	pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		4278	pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3746	Serge	4279	}
		4280
5060	serge	4281	/*
		4282	* And finally store the new values in the power sequencer. The
		4283	* backlight delays are set to 1 because we do manual waits on them. For
		4284	* T8, even BSpec recommends doing it. For T9, if we don't do this,
		4285	* we'll end up waiting for the backlight off delay twice: once when we
		4286	* do the manual sleep, and once when we disable the panel and wait for
		4287	* the PP_STATUS bit to become zero.
		4288	*/
3243	Serge	4289	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) \|
5060	serge	4290	(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
		4291	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) \|
3243	Serge	4292	(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
		4293	/* Compute the divisor for the pp clock, simply match the Bspec
		4294	* formula. */
3746	Serge	4295	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3243	Serge	4296	pp_div \|= (DIV_ROUND_UP(seq->t11_t12, 1000)
		4297	<< PANEL_POWER_CYCLE_DELAY_SHIFT);
		4298
		4299	/* Haswell doesn't have any port selection bits for the panel
		4300	* power sequencer any more. */
4104	Serge	4301	if (IS_VALLEYVIEW(dev)) {
4560	Serge	4302	if (dp_to_dig_port(intel_dp)->port == PORT_B)
		4303	port_sel = PANEL_PORT_SELECT_DPB_VLV;
		4304	else
		4305	port_sel = PANEL_PORT_SELECT_DPC_VLV;
4104	Serge	4306	} else if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)) {
		4307	if (dp_to_dig_port(intel_dp)->port == PORT_A)
4560	Serge	4308	port_sel = PANEL_PORT_SELECT_DPA;
3243	Serge	4309	else
4560	Serge	4310	port_sel = PANEL_PORT_SELECT_DPD;
3243	Serge	4311	}
		4312
3746	Serge	4313	pp_on \|= port_sel;
3243	Serge	4314
3746	Serge	4315	I915_WRITE(pp_on_reg, pp_on);
		4316	I915_WRITE(pp_off_reg, pp_off);
		4317	I915_WRITE(pp_div_reg, pp_div);
		4318
3243	Serge	4319	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3746	Serge	4320	I915_READ(pp_on_reg),
		4321	I915_READ(pp_off_reg),
		4322	I915_READ(pp_div_reg));
3243	Serge	4323	}
		4324
5060	serge	4325	void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
		4326	{
		4327	struct drm_i915_private *dev_priv = dev->dev_private;
		4328	struct intel_encoder *encoder;
		4329	struct intel_dp *intel_dp = NULL;
		4330	struct intel_crtc_config *config = NULL;
		4331	struct intel_crtc *intel_crtc = NULL;
		4332	struct intel_connector *intel_connector = dev_priv->drrs.connector;
		4333	u32 reg, val;
		4334	enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
		4335
		4336	if (refresh_rate <= 0) {
		4337	DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		4338	return;
		4339	}
		4340
		4341	if (intel_connector == NULL) {
		4342	DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
		4343	return;
		4344	}
		4345
		4346	/*
		4347	* FIXME: This needs proper synchronization with psr state. But really
		4348	* hard to tell without seeing the user of this function of this code.
		4349	* Check locking and ordering once that lands.
		4350	*/
		4351	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
		4352	DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
		4353	return;
		4354	}
		4355
		4356	encoder = intel_attached_encoder(&intel_connector->base);
		4357	intel_dp = enc_to_intel_dp(&encoder->base);
		4358	intel_crtc = encoder->new_crtc;
		4359
		4360	if (!intel_crtc) {
		4361	DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		4362	return;
		4363	}
		4364
		4365	config = &intel_crtc->config;
		4366
		4367	if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
		4368	DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		4369	return;
		4370	}
		4371
		4372	if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
		4373	index = DRRS_LOW_RR;
		4374
		4375	if (index == intel_dp->drrs_state.refresh_rate_type) {
		4376	DRM_DEBUG_KMS(
		4377	"DRRS requested for previously set RR...ignoring\n");
		4378	return;
		4379	}
		4380
		4381	if (!intel_crtc->active) {
		4382	DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		4383	return;
		4384	}
		4385
		4386	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		4387	reg = PIPECONF(intel_crtc->config.cpu_transcoder);
		4388	val = I915_READ(reg);
		4389	if (index > DRRS_HIGH_RR) {
		4390	val \|= PIPECONF_EDP_RR_MODE_SWITCH;
		4391	intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
		4392	} else {
		4393	val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		4394	}
		4395	I915_WRITE(reg, val);
		4396	}
		4397
		4398	/*
		4399	* mutex taken to ensure that there is no race between differnt
		4400	* drrs calls trying to update refresh rate. This scenario may occur
		4401	* in future when idleness detection based DRRS in kernel and
		4402	* possible calls from user space to set differnt RR are made.
		4403	*/
		4404
		4405	mutex_lock(&intel_dp->drrs_state.mutex);
		4406
		4407	intel_dp->drrs_state.refresh_rate_type = index;
		4408
		4409	mutex_unlock(&intel_dp->drrs_state.mutex);
		4410
		4411	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
		4412	}
		4413
		4414	static struct drm_display_mode *
		4415	intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
		4416	struct intel_connector *intel_connector,
		4417	struct drm_display_mode *fixed_mode)
		4418	{
		4419	struct drm_connector *connector = &intel_connector->base;
		4420	struct intel_dp *intel_dp = &intel_dig_port->dp;
		4421	struct drm_device *dev = intel_dig_port->base.base.dev;
		4422	struct drm_i915_private *dev_priv = dev->dev_private;
		4423	struct drm_display_mode *downclock_mode = NULL;
		4424
		4425	if (INTEL_INFO(dev)->gen <= 6) {
		4426	DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		4427	return NULL;
		4428	}
		4429
		4430	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
		4431	DRM_INFO("VBT doesn't support DRRS\n");
		4432	return NULL;
		4433	}
		4434
		4435	downclock_mode = intel_find_panel_downclock
		4436	(dev, fixed_mode, connector);
		4437
		4438	if (!downclock_mode) {
		4439	DRM_INFO("DRRS not supported\n");
		4440	return NULL;
		4441	}
		4442
		4443	dev_priv->drrs.connector = intel_connector;
		4444
		4445	mutex_init(&intel_dp->drrs_state.mutex);
		4446
		4447	intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
		4448
		4449	intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
		4450	DRM_INFO("seamless DRRS supported for eDP panel.\n");
		4451	return downclock_mode;
		4452	}
		4453
		4454	void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
		4455	{
		4456	struct drm_device *dev = intel_encoder->base.dev;
		4457	struct drm_i915_private *dev_priv = dev->dev_private;
		4458	struct intel_dp *intel_dp;
		4459	enum intel_display_power_domain power_domain;
		4460
		4461	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		4462	return;
		4463
		4464	intel_dp = enc_to_intel_dp(&intel_encoder->base);
		4465	if (!edp_have_panel_vdd(intel_dp))
		4466	return;
		4467	/*
		4468	* The VDD bit needs a power domain reference, so if the bit is
		4469	* already enabled when we boot or resume, grab this reference and
		4470	* schedule a vdd off, so we don't hold on to the reference
		4471	* indefinitely.
		4472	*/
		4473	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
		4474	power_domain = intel_display_port_power_domain(intel_encoder);
		4475	intel_display_power_get(dev_priv, power_domain);
		4476
		4477	edp_panel_vdd_schedule_off(intel_dp);
		4478	}
		4479
4104	Serge	4480	static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5060	serge	4481	struct intel_connector *intel_connector,
		4482	struct edp_power_seq *power_seq)
4104	Serge	4483	{
		4484	struct drm_connector *connector = &intel_connector->base;
		4485	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5060	serge	4486	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		4487	struct drm_device *dev = intel_encoder->base.dev;
4104	Serge	4488	struct drm_i915_private *dev_priv = dev->dev_private;
		4489	struct drm_display_mode *fixed_mode = NULL;
5060	serge	4490	struct drm_display_mode *downclock_mode = NULL;
4104	Serge	4491	bool has_dpcd;
		4492	struct drm_display_mode *scan;
		4493	struct edid *edid;
		4494
5060	serge	4495	intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
		4496
4104	Serge	4497	if (!is_edp(intel_dp))
		4498	return true;
		4499
5060	serge	4500	intel_edp_panel_vdd_sanitize(intel_encoder);
4104	Serge	4501
		4502	/* Cache DPCD and EDID for edp. */
5060	serge	4503	intel_edp_panel_vdd_on(intel_dp);
4104	Serge	4504	has_dpcd = intel_dp_get_dpcd(intel_dp);
5060	serge	4505	edp_panel_vdd_off(intel_dp, false);
4104	Serge	4506
		4507	if (has_dpcd) {
		4508	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		4509	dev_priv->no_aux_handshake =
		4510	intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
		4511	DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		4512	} else {
		4513	/* if this fails, presume the device is a ghost */
		4514	DRM_INFO("failed to retrieve link info, disabling eDP\n");
		4515	return false;
		4516	}
		4517
		4518	/* We now know it's not a ghost, init power sequence regs. */
5060	serge	4519	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4104	Serge	4520
5060	serge	4521	mutex_lock(&dev->mode_config.mutex);
		4522	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4104	Serge	4523	if (edid) {
		4524	if (drm_add_edid_modes(connector, edid)) {
		4525	drm_mode_connector_update_edid_property(connector,
		4526	edid);
		4527	drm_edid_to_eld(connector, edid);
		4528	} else {
		4529	kfree(edid);
		4530	edid = ERR_PTR(-EINVAL);
		4531	}
		4532	} else {
		4533	edid = ERR_PTR(-ENOENT);
		4534	}
		4535	intel_connector->edid = edid;
		4536
		4537	/* prefer fixed mode from EDID if available */
		4538	list_for_each_entry(scan, &connector->probed_modes, head) {
		4539	if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
		4540	fixed_mode = drm_mode_duplicate(dev, scan);
5060	serge	4541	downclock_mode = intel_dp_drrs_init(
		4542	intel_dig_port,
		4543	intel_connector, fixed_mode);
4104	Serge	4544	break;
		4545	}
		4546	}
		4547
		4548	/* fallback to VBT if available for eDP */
		4549	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		4550	fixed_mode = drm_mode_duplicate(dev,
		4551	dev_priv->vbt.lfp_lvds_vbt_mode);
		4552	if (fixed_mode)
		4553	fixed_mode->type \|= DRM_MODE_TYPE_PREFERRED;
		4554	}
5060	serge	4555	mutex_unlock(&dev->mode_config.mutex);
4104	Serge	4556
5060	serge	4557	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4104	Serge	4558	intel_panel_setup_backlight(connector);
		4559
		4560	return true;
		4561	}
		4562
		4563	bool
3243	Serge	4564	intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
		4565	struct intel_connector *intel_connector)
2330	Serge	4566	{
3243	Serge	4567	struct drm_connector *connector = &intel_connector->base;
		4568	struct intel_dp *intel_dp = &intel_dig_port->dp;
		4569	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		4570	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	4571	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	4572	enum port port = intel_dig_port->port;
5060	serge	4573	struct edp_power_seq power_seq = { 0 };
		4574	int type;
2330	Serge	4575
5060	serge	4576	/* intel_dp vfuncs */
		4577	if (IS_VALLEYVIEW(dev))
		4578	intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
		4579	else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
		4580	intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
		4581	else if (HAS_PCH_SPLIT(dev))
		4582	intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
		4583	else
		4584	intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
		4585
		4586	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
		4587
3031	serge	4588	/* Preserve the current hw state. */
		4589	intel_dp->DP = I915_READ(intel_dp->output_reg);
3243	Serge	4590	intel_dp->attached_connector = intel_connector;
2330	Serge	4591
4560	Serge	4592	if (intel_dp_is_edp(dev, port))
		4593	type = DRM_MODE_CONNECTOR_eDP;
		4594	else
4104	Serge	4595	type = DRM_MODE_CONNECTOR_DisplayPort;
2330	Serge	4596
4104	Serge	4597	/*
		4598	* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
		4599	* for DP the encoder type can be set by the caller to
		4600	* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
		4601	*/
		4602	if (type == DRM_MODE_CONNECTOR_eDP)
		4603	intel_encoder->type = INTEL_OUTPUT_EDP;
		4604
		4605	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
		4606	type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
		4607	port_name(port));
		4608
2330	Serge	4609	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
		4610	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
		4611
		4612	connector->interlace_allowed = true;
		4613	connector->doublescan_allowed = 0;
		4614
3243	Serge	4615	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5060	serge	4616	edp_panel_vdd_work);
2330	Serge	4617
		4618	intel_connector_attach_encoder(intel_connector, intel_encoder);
5060	serge	4619	drm_connector_register(connector);
2330	Serge	4620
3480	Serge	4621	if (HAS_DDI(dev))
3243	Serge	4622	intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
		4623	else
3031	serge	4624	intel_connector->get_hw_state = intel_connector_get_hw_state;
5060	serge	4625	intel_connector->unregister = intel_dp_connector_unregister;
3031	serge	4626
5060	serge	4627	/* Set up the hotplug pin. */
3031	serge	4628	switch (port) {
		4629	case PORT_A:
3746	Serge	4630	intel_encoder->hpd_pin = HPD_PORT_A;
2330	Serge	4631	break;
3031	serge	4632	case PORT_B:
3746	Serge	4633	intel_encoder->hpd_pin = HPD_PORT_B;
2330	Serge	4634	break;
3031	serge	4635	case PORT_C:
3746	Serge	4636	intel_encoder->hpd_pin = HPD_PORT_C;
2330	Serge	4637	break;
3031	serge	4638	case PORT_D:
3746	Serge	4639	intel_encoder->hpd_pin = HPD_PORT_D;
2330	Serge	4640	break;
3031	serge	4641	default:
3746	Serge	4642	BUG();
2330	Serge	4643	}
		4644
5060	serge	4645	if (is_edp(intel_dp)) {
		4646	intel_dp_init_panel_power_timestamps(intel_dp);
		4647	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		4648	}
2330	Serge	4649
5060	serge	4650	intel_dp_aux_init(intel_dp, intel_connector);
3031	serge	4651
5060	serge	4652	/* init MST on ports that can support it */
		4653	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
		4654	if (port == PORT_B \|\| port == PORT_C \|\| port == PORT_D) {
		4655	intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
		4656	}
		4657	}
		4658
		4659	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
		4660	drm_dp_aux_unregister(&intel_dp->aux);
3031	serge	4661	if (is_edp(intel_dp)) {
4293	Serge	4662	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5060	serge	4663	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
		4664	edp_panel_vdd_off_sync(intel_dp);
		4665	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2330	Serge	4666	}
5060	serge	4667	drm_connector_unregister(connector);
4104	Serge	4668	drm_connector_cleanup(connector);
		4669	return false;
2330	Serge	4670	}
		4671
		4672	intel_dp_add_properties(intel_dp, connector);
		4673
		4674	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		4675	* 0xd. Failure to do so will result in spurious interrupts being
		4676	* generated on the port when a cable is not attached.
		4677	*/
		4678	if (IS_G4X(dev) && !IS_GM45(dev)) {
		4679	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		4680	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		4681	}
4104	Serge	4682
		4683	return true;
2330	Serge	4684	}
3243	Serge	4685
		4686	void
		4687	intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
		4688	{
5060	serge	4689	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	4690	struct intel_digital_port *intel_dig_port;
		4691	struct intel_encoder *intel_encoder;
		4692	struct drm_encoder *encoder;
		4693	struct intel_connector *intel_connector;
		4694
4560	Serge	4695	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	4696	if (!intel_dig_port)
		4697	return;
		4698
4560	Serge	4699	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3243	Serge	4700	if (!intel_connector) {
		4701	kfree(intel_dig_port);
		4702	return;
		4703	}
		4704
		4705	intel_encoder = &intel_dig_port->base;
		4706	encoder = &intel_encoder->base;
		4707
		4708	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
		4709	DRM_MODE_ENCODER_TMDS);
		4710
3746	Serge	4711	intel_encoder->compute_config = intel_dp_compute_config;
3243	Serge	4712	intel_encoder->disable = intel_disable_dp;
		4713	intel_encoder->get_hw_state = intel_dp_get_hw_state;
4104	Serge	4714	intel_encoder->get_config = intel_dp_get_config;
5060	serge	4715	intel_encoder->suspend = intel_dp_encoder_suspend;
		4716	if (IS_CHERRYVIEW(dev)) {
		4717	intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
		4718	intel_encoder->pre_enable = chv_pre_enable_dp;
		4719	intel_encoder->enable = vlv_enable_dp;
		4720	intel_encoder->post_disable = chv_post_disable_dp;
		4721	} else if (IS_VALLEYVIEW(dev)) {
4560	Serge	4722	intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4104	Serge	4723	intel_encoder->pre_enable = vlv_pre_enable_dp;
		4724	intel_encoder->enable = vlv_enable_dp;
5060	serge	4725	intel_encoder->post_disable = vlv_post_disable_dp;
4104	Serge	4726	} else {
4560	Serge	4727	intel_encoder->pre_enable = g4x_pre_enable_dp;
		4728	intel_encoder->enable = g4x_enable_dp;
5060	serge	4729	intel_encoder->post_disable = g4x_post_disable_dp;
4104	Serge	4730	}
3243	Serge	4731
		4732	intel_dig_port->port = port;
		4733	intel_dig_port->dp.output_reg = output_reg;
		4734
		4735	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5060	serge	4736	if (IS_CHERRYVIEW(dev)) {
		4737	if (port == PORT_D)
		4738	intel_encoder->crtc_mask = 1 << 2;
		4739	else
		4740	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
		4741	} else {
3243	Serge	4742	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
5060	serge	4743	}
		4744	intel_encoder->cloneable = 0;
3243	Serge	4745	intel_encoder->hot_plug = intel_dp_hot_plug;
		4746
5060	serge	4747	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
		4748	dev_priv->hpd_irq_port[port] = intel_dig_port;
		4749
4104	Serge	4750	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		4751	drm_encoder_cleanup(encoder);
		4752	kfree(intel_dig_port);
		4753	kfree(intel_connector);
		4754	}
3243	Serge	4755	}
5060	serge	4756
		4757	void intel_dp_mst_suspend(struct drm_device *dev)
		4758	{
		4759	struct drm_i915_private *dev_priv = dev->dev_private;
		4760	int i;
		4761
		4762	/* disable MST */
		4763	for (i = 0; i < I915_MAX_PORTS; i++) {
		4764	struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		4765	if (!intel_dig_port)
		4766	continue;
		4767
		4768	if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
		4769	if (!intel_dig_port->dp.can_mst)
		4770	continue;
		4771	if (intel_dig_port->dp.is_mst)
		4772	drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		4773	}
		4774	}
		4775	}
		4776
		4777	void intel_dp_mst_resume(struct drm_device *dev)
		4778	{
		4779	struct drm_i915_private *dev_priv = dev->dev_private;
		4780	int i;
		4781
		4782	for (i = 0; i < I915_MAX_PORTS; i++) {
		4783	struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		4784	if (!intel_dig_port)
		4785	continue;
		4786	if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
		4787	int ret;
		4788
		4789	if (!intel_dig_port->dp.can_mst)
		4790	continue;
		4791
		4792	ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
		4793	if (ret != 0) {
		4794	intel_dp_check_mst_status(&intel_dig_port->dp);
		4795	}
		4796	}
		4797	}
		4798	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c – Rev 5139