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Rev | Author | Line No. | Line |
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2327 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Keith Packard |
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25 | * |
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26 | */ |
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27 | |||
28 | #include |
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2330 | Serge | 29 | #include |
3031 | serge | 30 | #include |
31 | #include |
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32 | #include |
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33 | #include |
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34 | #include |
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2327 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2327 | Serge | 37 | #include "i915_drv.h" |
38 | |||
5060 | serge | 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
2327 | Serge | 40 | |
4560 | Serge | 41 | struct dp_link_dpll { |
42 | int link_bw; |
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43 | struct dpll dpll; |
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44 | }; |
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45 | |||
46 | static const struct dp_link_dpll gen4_dpll[] = { |
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47 | { DP_LINK_BW_1_62, |
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48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
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49 | { DP_LINK_BW_2_7, |
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50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
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51 | }; |
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52 | |||
53 | static const struct dp_link_dpll pch_dpll[] = { |
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54 | { DP_LINK_BW_1_62, |
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55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
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56 | { DP_LINK_BW_2_7, |
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57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
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58 | }; |
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59 | |||
60 | static const struct dp_link_dpll vlv_dpll[] = { |
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61 | { DP_LINK_BW_1_62, |
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62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
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63 | { DP_LINK_BW_2_7, |
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64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
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65 | }; |
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66 | |||
5060 | serge | 67 | /* |
68 | * CHV supports eDP 1.4 that have more link rates. |
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69 | * Below only provides the fixed rate but exclude variable rate. |
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70 | */ |
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71 | static const struct dp_link_dpll chv_dpll[] = { |
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72 | /* |
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73 | * CHV requires to program fractional division for m2. |
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74 | * m2 is stored in fixed point format using formula below |
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75 | * (m2_int << 22) | m2_fraction |
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76 | */ |
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77 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ |
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78 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
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79 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ |
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80 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
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81 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ |
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82 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
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83 | }; |
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84 | |||
2327 | Serge | 85 | /** |
86 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
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87 | * @intel_dp: DP struct |
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88 | * |
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89 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
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90 | * will return true, and false otherwise. |
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91 | */ |
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92 | static bool is_edp(struct intel_dp *intel_dp) |
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93 | { |
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3243 | Serge | 94 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
95 | |||
96 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
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2327 | Serge | 97 | } |
98 | |||
3243 | Serge | 99 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
2327 | Serge | 100 | { |
3243 | Serge | 101 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
102 | |||
103 | return intel_dig_port->base.base.dev; |
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2327 | Serge | 104 | } |
105 | |||
2330 | Serge | 106 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
107 | { |
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3243 | Serge | 108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
2330 | Serge | 109 | } |
2327 | Serge | 110 | |
2330 | Serge | 111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
5060 | serge | 112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
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2330 | Serge | 114 | |
5060 | serge | 115 | int |
2330 | Serge | 116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
117 | { |
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118 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
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5060 | serge | 119 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
2327 | Serge | 120 | |
2330 | Serge | 121 | switch (max_link_bw) { |
122 | case DP_LINK_BW_1_62: |
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123 | case DP_LINK_BW_2_7: |
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124 | break; |
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4104 | Serge | 125 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
5060 | serge | 126 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
127 | INTEL_INFO(dev)->gen >= 8) && |
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128 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
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129 | max_link_bw = DP_LINK_BW_5_4; |
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130 | else |
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131 | max_link_bw = DP_LINK_BW_2_7; |
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4104 | Serge | 132 | break; |
2330 | Serge | 133 | default: |
4104 | Serge | 134 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
135 | max_link_bw); |
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2330 | Serge | 136 | max_link_bw = DP_LINK_BW_1_62; |
137 | break; |
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138 | } |
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139 | return max_link_bw; |
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140 | } |
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2327 | Serge | 141 | |
5060 | serge | 142 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
143 | { |
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144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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145 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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146 | u8 source_max, sink_max; |
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147 | |||
148 | source_max = 4; |
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149 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
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150 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
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151 | source_max = 2; |
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152 | |||
153 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
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154 | |||
155 | return min(source_max, sink_max); |
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156 | } |
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157 | |||
2342 | Serge | 158 | /* |
159 | * The units on the numbers in the next two are... bizarre. Examples will |
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160 | * make it clearer; this one parallels an example in the eDP spec. |
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161 | * |
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162 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
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163 | * |
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164 | * 270000 * 1 * 8 / 10 == 216000 |
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165 | * |
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166 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
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167 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
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168 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
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169 | * 119000. At 18bpp that's 2142000 kilobits per second. |
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170 | * |
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171 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
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172 | * get the result in decakilobits instead of kilobits. |
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173 | */ |
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174 | |||
2330 | Serge | 175 | static int |
2351 | Serge | 176 | intel_dp_link_required(int pixel_clock, int bpp) |
2330 | Serge | 177 | { |
2342 | Serge | 178 | return (pixel_clock * bpp + 9) / 10; |
2330 | Serge | 179 | } |
2327 | Serge | 180 | |
2330 | Serge | 181 | static int |
182 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
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183 | { |
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184 | return (max_link_clock * max_lanes * 8) / 10; |
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185 | } |
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2327 | Serge | 186 | |
4560 | Serge | 187 | static enum drm_mode_status |
2330 | Serge | 188 | intel_dp_mode_valid(struct drm_connector *connector, |
189 | struct drm_display_mode *mode) |
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190 | { |
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191 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
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3243 | Serge | 192 | struct intel_connector *intel_connector = to_intel_connector(connector); |
193 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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3746 | Serge | 194 | int target_clock = mode->clock; |
195 | int max_rate, mode_rate, max_lanes, max_link_clock; |
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2327 | Serge | 196 | |
3243 | Serge | 197 | if (is_edp(intel_dp) && fixed_mode) { |
198 | if (mode->hdisplay > fixed_mode->hdisplay) |
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2330 | Serge | 199 | return MODE_PANEL; |
2327 | Serge | 200 | |
3243 | Serge | 201 | if (mode->vdisplay > fixed_mode->vdisplay) |
2330 | Serge | 202 | return MODE_PANEL; |
3746 | Serge | 203 | |
204 | target_clock = fixed_mode->clock; |
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2330 | Serge | 205 | } |
2327 | Serge | 206 | |
3746 | Serge | 207 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
5060 | serge | 208 | max_lanes = intel_dp_max_lane_count(intel_dp); |
3746 | Serge | 209 | |
210 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
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211 | mode_rate = intel_dp_link_required(target_clock, 18); |
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212 | |||
213 | if (mode_rate > max_rate) |
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2330 | Serge | 214 | return MODE_CLOCK_HIGH; |
2327 | Serge | 215 | |
2330 | Serge | 216 | if (mode->clock < 10000) |
217 | return MODE_CLOCK_LOW; |
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218 | |||
3031 | serge | 219 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
220 | return MODE_H_ILLEGAL; |
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221 | |||
2330 | Serge | 222 | return MODE_OK; |
223 | } |
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224 | |||
225 | static uint32_t |
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226 | pack_aux(uint8_t *src, int src_bytes) |
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227 | { |
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228 | int i; |
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229 | uint32_t v = 0; |
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230 | |||
231 | if (src_bytes > 4) |
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232 | src_bytes = 4; |
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233 | for (i = 0; i < src_bytes; i++) |
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234 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
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235 | return v; |
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236 | } |
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237 | |||
238 | static void |
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239 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
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240 | { |
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241 | int i; |
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242 | if (dst_bytes > 4) |
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243 | dst_bytes = 4; |
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244 | for (i = 0; i < dst_bytes; i++) |
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245 | dst[i] = src >> ((3-i) * 8); |
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246 | } |
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247 | |||
248 | /* hrawclock is 1/4 the FSB frequency */ |
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249 | static int |
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250 | intel_hrawclk(struct drm_device *dev) |
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251 | { |
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252 | struct drm_i915_private *dev_priv = dev->dev_private; |
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253 | uint32_t clkcfg; |
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254 | |||
3243 | Serge | 255 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
256 | if (IS_VALLEYVIEW(dev)) |
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257 | return 200; |
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258 | |||
2330 | Serge | 259 | clkcfg = I915_READ(CLKCFG); |
260 | switch (clkcfg & CLKCFG_FSB_MASK) { |
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261 | case CLKCFG_FSB_400: |
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262 | return 100; |
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263 | case CLKCFG_FSB_533: |
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264 | return 133; |
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265 | case CLKCFG_FSB_667: |
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266 | return 166; |
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267 | case CLKCFG_FSB_800: |
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268 | return 200; |
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269 | case CLKCFG_FSB_1067: |
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270 | return 266; |
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271 | case CLKCFG_FSB_1333: |
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272 | return 333; |
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273 | /* these two are just a guess; one of them might be right */ |
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274 | case CLKCFG_FSB_1600: |
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275 | case CLKCFG_FSB_1600_ALT: |
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276 | return 400; |
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277 | default: |
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278 | return 133; |
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279 | } |
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280 | } |
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281 | |||
4560 | Serge | 282 | static void |
283 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
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284 | struct intel_dp *intel_dp, |
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285 | struct edp_power_seq *out); |
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286 | static void |
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287 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
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288 | struct intel_dp *intel_dp, |
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289 | struct edp_power_seq *out); |
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290 | |||
291 | static enum pipe |
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292 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
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293 | { |
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294 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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295 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
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296 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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297 | struct drm_i915_private *dev_priv = dev->dev_private; |
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298 | enum port port = intel_dig_port->port; |
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299 | enum pipe pipe; |
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300 | |||
301 | /* modeset should have pipe */ |
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302 | if (crtc) |
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303 | return to_intel_crtc(crtc)->pipe; |
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304 | |||
305 | /* init time, try to find a pipe with this port selected */ |
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306 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
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307 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
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308 | PANEL_PORT_SELECT_MASK; |
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309 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
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310 | return pipe; |
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311 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
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312 | return pipe; |
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313 | } |
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314 | |||
315 | /* shrug */ |
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316 | return PIPE_A; |
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317 | } |
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318 | |||
319 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
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320 | { |
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321 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
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322 | |||
323 | if (HAS_PCH_SPLIT(dev)) |
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324 | return PCH_PP_CONTROL; |
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325 | else |
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326 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
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327 | } |
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328 | |||
329 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
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330 | { |
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331 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
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332 | |||
333 | if (HAS_PCH_SPLIT(dev)) |
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334 | return PCH_PP_STATUS; |
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335 | else |
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336 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
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337 | } |
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338 | |||
5060 | serge | 339 | |
340 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
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2342 | Serge | 341 | { |
3243 | Serge | 342 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 343 | struct drm_i915_private *dev_priv = dev->dev_private; |
344 | |||
4560 | Serge | 345 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
2342 | Serge | 346 | } |
347 | |||
5060 | serge | 348 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
2342 | Serge | 349 | { |
3243 | Serge | 350 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 351 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 352 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
353 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
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354 | enum intel_display_power_domain power_domain; |
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2342 | Serge | 355 | |
5060 | serge | 356 | power_domain = intel_display_port_power_domain(intel_encoder); |
357 | return intel_display_power_enabled(dev_priv, power_domain) && |
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358 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
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2342 | Serge | 359 | } |
360 | |||
361 | static void |
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362 | intel_dp_check_edp(struct intel_dp *intel_dp) |
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363 | { |
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3243 | Serge | 364 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
366 | |||
367 | if (!is_edp(intel_dp)) |
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368 | return; |
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3746 | Serge | 369 | |
5060 | serge | 370 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
2342 | Serge | 371 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
372 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
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4560 | Serge | 373 | I915_READ(_pp_stat_reg(intel_dp)), |
374 | I915_READ(_pp_ctrl_reg(intel_dp))); |
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2342 | Serge | 375 | } |
376 | } |
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377 | |||
3480 | Serge | 378 | static uint32_t |
379 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
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380 | { |
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381 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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382 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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383 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3746 | Serge | 384 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
3480 | Serge | 385 | uint32_t status; |
386 | bool done; |
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387 | |||
388 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
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389 | if (has_aux_irq) |
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390 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
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4104 | Serge | 391 | msecs_to_jiffies_timeout(10)); |
3480 | Serge | 392 | else |
393 | done = wait_for_atomic(C, 10) == 0; |
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394 | if (!done) |
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395 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
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396 | has_aux_irq); |
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397 | #undef C |
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398 | |||
399 | return status; |
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400 | } |
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401 | |||
5060 | serge | 402 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
4104 | Serge | 403 | { |
404 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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405 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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406 | |||
5060 | serge | 407 | /* |
408 | * The clock divider is based off the hrawclk, and would like to run at |
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409 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
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4104 | Serge | 410 | */ |
5060 | serge | 411 | return index ? 0 : intel_hrawclk(dev) / 2; |
412 | } |
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413 | |||
414 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
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415 | { |
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416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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417 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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418 | |||
419 | if (index) |
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420 | return 0; |
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421 | |||
422 | if (intel_dig_port->port == PORT_A) { |
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423 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
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4104 | Serge | 424 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
425 | else |
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426 | return 225; /* eDP input clock at 450Mhz */ |
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5060 | serge | 427 | } else { |
428 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
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429 | } |
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430 | } |
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431 | |||
432 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
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433 | { |
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434 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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435 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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436 | struct drm_i915_private *dev_priv = dev->dev_private; |
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437 | |||
438 | if (intel_dig_port->port == PORT_A) { |
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439 | if (index) |
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440 | return 0; |
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441 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
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4104 | Serge | 442 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
443 | /* Workaround for non-ULT HSW */ |
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444 | switch (index) { |
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445 | case 0: return 63; |
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446 | case 1: return 72; |
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447 | default: return 0; |
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448 | } |
||
5060 | serge | 449 | } else { |
4104 | Serge | 450 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
451 | } |
||
452 | } |
||
453 | |||
5060 | serge | 454 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
455 | { |
||
456 | return index ? 0 : 100; |
||
457 | } |
||
458 | |||
459 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
||
460 | bool has_aux_irq, |
||
461 | int send_bytes, |
||
462 | uint32_t aux_clock_divider) |
||
463 | { |
||
464 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
465 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
466 | uint32_t precharge, timeout; |
||
467 | |||
468 | if (IS_GEN6(dev)) |
||
469 | precharge = 3; |
||
470 | else |
||
471 | precharge = 5; |
||
472 | |||
473 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
||
474 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
||
475 | else |
||
476 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
||
477 | |||
478 | return DP_AUX_CH_CTL_SEND_BUSY | |
||
479 | DP_AUX_CH_CTL_DONE | |
||
480 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
||
481 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
||
482 | timeout | |
||
483 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
||
484 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
||
485 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
||
486 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
||
487 | } |
||
488 | |||
2330 | Serge | 489 | static int |
490 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
||
491 | uint8_t *send, int send_bytes, |
||
492 | uint8_t *recv, int recv_size) |
||
493 | { |
||
3243 | Serge | 494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
495 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 496 | struct drm_i915_private *dev_priv = dev->dev_private; |
3746 | Serge | 497 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
2330 | Serge | 498 | uint32_t ch_data = ch_ctl + 4; |
4104 | Serge | 499 | uint32_t aux_clock_divider; |
3480 | Serge | 500 | int i, ret, recv_bytes; |
2330 | Serge | 501 | uint32_t status; |
5060 | serge | 502 | int try, clock = 0; |
503 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
||
504 | bool vdd; |
||
2330 | Serge | 505 | |
5060 | serge | 506 | vdd = _edp_panel_vdd_on(intel_dp); |
507 | |||
3480 | Serge | 508 | /* dp aux is extremely sensitive to irq latency, hence request the |
509 | * lowest possible wakeup latency and so prevent the cpu from going into |
||
510 | * deep sleep states. |
||
511 | */ |
||
512 | |||
2342 | Serge | 513 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 514 | |
4104 | Serge | 515 | intel_aux_display_runtime_get(dev_priv); |
516 | |||
2330 | Serge | 517 | /* Try to wait for any previous AUX channel activity */ |
518 | for (try = 0; try < 3; try++) { |
||
3480 | Serge | 519 | status = I915_READ_NOTRACE(ch_ctl); |
2330 | Serge | 520 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
521 | break; |
||
522 | msleep(1); |
||
523 | } |
||
524 | |||
525 | if (try == 3) { |
||
526 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
||
527 | I915_READ(ch_ctl)); |
||
3480 | Serge | 528 | ret = -EBUSY; |
529 | goto out; |
||
2330 | Serge | 530 | } |
531 | |||
4560 | Serge | 532 | /* Only 5 data registers! */ |
533 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
||
534 | ret = -E2BIG; |
||
535 | goto out; |
||
536 | } |
||
537 | |||
5060 | serge | 538 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
539 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
||
540 | has_aux_irq, |
||
541 | send_bytes, |
||
542 | aux_clock_divider); |
||
543 | |||
2330 | Serge | 544 | /* Must try at least 3 times according to DP spec */ |
545 | for (try = 0; try < 5; try++) { |
||
546 | /* Load the send data into the aux channel data registers */ |
||
547 | for (i = 0; i < send_bytes; i += 4) |
||
548 | I915_WRITE(ch_data + i, |
||
549 | pack_aux(send + i, send_bytes - i)); |
||
550 | |||
551 | /* Send the command and wait for it to complete */ |
||
5060 | serge | 552 | I915_WRITE(ch_ctl, send_ctl); |
2330 | Serge | 553 | |
3480 | Serge | 554 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
555 | |||
2330 | Serge | 556 | /* Clear done status and any errors */ |
557 | I915_WRITE(ch_ctl, |
||
558 | status | |
||
559 | DP_AUX_CH_CTL_DONE | |
||
560 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
||
561 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
||
3031 | serge | 562 | |
563 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
||
564 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
||
565 | continue; |
||
2330 | Serge | 566 | if (status & DP_AUX_CH_CTL_DONE) |
567 | break; |
||
568 | } |
||
4104 | Serge | 569 | if (status & DP_AUX_CH_CTL_DONE) |
570 | break; |
||
571 | } |
||
2330 | Serge | 572 | |
573 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
||
574 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
||
3480 | Serge | 575 | ret = -EBUSY; |
576 | goto out; |
||
2330 | Serge | 577 | } |
578 | |||
579 | /* Check for timeout or receive error. |
||
580 | * Timeouts occur when the sink is not connected |
||
581 | */ |
||
582 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
||
583 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
||
3480 | Serge | 584 | ret = -EIO; |
585 | goto out; |
||
2330 | Serge | 586 | } |
587 | |||
588 | /* Timeouts occur when the device isn't connected, so they're |
||
589 | * "normal" -- don't fill the kernel log with these */ |
||
590 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
||
591 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
||
3480 | Serge | 592 | ret = -ETIMEDOUT; |
593 | goto out; |
||
2330 | Serge | 594 | } |
595 | |||
596 | /* Unload any bytes sent back from the other side */ |
||
597 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
||
598 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
||
599 | if (recv_bytes > recv_size) |
||
600 | recv_bytes = recv_size; |
||
601 | |||
602 | for (i = 0; i < recv_bytes; i += 4) |
||
603 | unpack_aux(I915_READ(ch_data + i), |
||
604 | recv + i, recv_bytes - i); |
||
605 | |||
3480 | Serge | 606 | ret = recv_bytes; |
607 | out: |
||
608 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
||
4104 | Serge | 609 | intel_aux_display_runtime_put(dev_priv); |
3480 | Serge | 610 | |
5060 | serge | 611 | if (vdd) |
612 | edp_panel_vdd_off(intel_dp, false); |
||
613 | |||
3480 | Serge | 614 | return ret; |
2330 | Serge | 615 | } |
616 | |||
5060 | serge | 617 | #define BARE_ADDRESS_SIZE 3 |
618 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
||
619 | static ssize_t |
||
620 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
||
2330 | Serge | 621 | { |
5060 | serge | 622 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
623 | uint8_t txbuf[20], rxbuf[20]; |
||
624 | size_t txsize, rxsize; |
||
2330 | Serge | 625 | int ret; |
626 | |||
5060 | serge | 627 | txbuf[0] = msg->request << 4; |
628 | txbuf[1] = msg->address >> 8; |
||
629 | txbuf[2] = msg->address & 0xff; |
||
630 | txbuf[3] = msg->size - 1; |
||
631 | |||
632 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
||
633 | case DP_AUX_NATIVE_WRITE: |
||
634 | case DP_AUX_I2C_WRITE: |
||
635 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
||
636 | rxsize = 1; |
||
637 | |||
638 | if (WARN_ON(txsize > 20)) |
||
4560 | Serge | 639 | return -E2BIG; |
640 | |||
5060 | serge | 641 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
642 | |||
643 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
||
644 | if (ret > 0) { |
||
645 | msg->reply = rxbuf[0] >> 4; |
||
646 | |||
647 | /* Return payload size. */ |
||
648 | ret = msg->size; |
||
649 | } |
||
2330 | Serge | 650 | break; |
651 | |||
5060 | serge | 652 | case DP_AUX_NATIVE_READ: |
653 | case DP_AUX_I2C_READ: |
||
654 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
||
655 | rxsize = msg->size + 1; |
||
2330 | Serge | 656 | |
5060 | serge | 657 | if (WARN_ON(rxsize > 20)) |
4560 | Serge | 658 | return -E2BIG; |
659 | |||
5060 | serge | 660 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
661 | if (ret > 0) { |
||
662 | msg->reply = rxbuf[0] >> 4; |
||
663 | /* |
||
664 | * Assume happy day, and copy the data. The caller is |
||
665 | * expected to check msg->reply before touching it. |
||
666 | * |
||
667 | * Return payload size. |
||
668 | */ |
||
669 | ret--; |
||
670 | memcpy(msg->buffer, rxbuf + 1, ret); |
||
671 | } |
||
672 | break; |
||
2330 | Serge | 673 | |
5060 | serge | 674 | default: |
675 | ret = -EINVAL; |
||
676 | break; |
||
677 | } |
||
2330 | Serge | 678 | |
679 | return ret; |
||
680 | } |
||
681 | |||
5060 | serge | 682 | static void |
683 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
||
2330 | Serge | 684 | { |
5060 | serge | 685 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
686 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
687 | enum port port = intel_dig_port->port; |
||
688 | const char *name = NULL; |
||
2330 | Serge | 689 | int ret; |
690 | |||
5060 | serge | 691 | switch (port) { |
692 | case PORT_A: |
||
693 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
||
694 | name = "DPDDC-A"; |
||
2330 | Serge | 695 | break; |
5060 | serge | 696 | case PORT_B: |
697 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
||
698 | name = "DPDDC-B"; |
||
2330 | Serge | 699 | break; |
5060 | serge | 700 | case PORT_C: |
701 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
||
702 | name = "DPDDC-C"; |
||
703 | break; |
||
704 | case PORT_D: |
||
705 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
||
706 | name = "DPDDC-D"; |
||
707 | break; |
||
2330 | Serge | 708 | default: |
5060 | serge | 709 | BUG(); |
2330 | Serge | 710 | } |
711 | |||
5060 | serge | 712 | if (!HAS_DDI(dev)) |
713 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
||
2330 | Serge | 714 | |
5060 | serge | 715 | intel_dp->aux.name = name; |
716 | intel_dp->aux.dev = dev->dev; |
||
717 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
||
2330 | Serge | 718 | |
5060 | serge | 719 | |
720 | ret = drm_dp_aux_register(&intel_dp->aux); |
||
721 | if (ret < 0) { |
||
722 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
||
723 | name, ret); |
||
724 | return; |
||
2330 | Serge | 725 | } |
5060 | serge | 726 | } |
2330 | Serge | 727 | |
5060 | serge | 728 | static void |
729 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
||
730 | { |
||
731 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
||
4560 | Serge | 732 | |
5060 | serge | 733 | intel_connector_unregister(intel_connector); |
2330 | Serge | 734 | } |
735 | |||
5060 | serge | 736 | static void |
737 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) |
||
2330 | Serge | 738 | { |
5060 | serge | 739 | switch (link_bw) { |
740 | case DP_LINK_BW_1_62: |
||
741 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
||
742 | break; |
||
743 | case DP_LINK_BW_2_7: |
||
744 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
||
745 | break; |
||
746 | case DP_LINK_BW_5_4: |
||
747 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
||
748 | break; |
||
749 | } |
||
2330 | Serge | 750 | } |
751 | |||
4104 | Serge | 752 | static void |
753 | intel_dp_set_clock(struct intel_encoder *encoder, |
||
754 | struct intel_crtc_config *pipe_config, int link_bw) |
||
755 | { |
||
756 | struct drm_device *dev = encoder->base.dev; |
||
4560 | Serge | 757 | const struct dp_link_dpll *divisor = NULL; |
758 | int i, count = 0; |
||
4104 | Serge | 759 | |
760 | if (IS_G4X(dev)) { |
||
4560 | Serge | 761 | divisor = gen4_dpll; |
762 | count = ARRAY_SIZE(gen4_dpll); |
||
4104 | Serge | 763 | } else if (HAS_PCH_SPLIT(dev)) { |
4560 | Serge | 764 | divisor = pch_dpll; |
765 | count = ARRAY_SIZE(pch_dpll); |
||
5060 | serge | 766 | } else if (IS_CHERRYVIEW(dev)) { |
767 | divisor = chv_dpll; |
||
768 | count = ARRAY_SIZE(chv_dpll); |
||
4560 | Serge | 769 | } else if (IS_VALLEYVIEW(dev)) { |
770 | divisor = vlv_dpll; |
||
771 | count = ARRAY_SIZE(vlv_dpll); |
||
5060 | serge | 772 | } |
4560 | Serge | 773 | |
774 | if (divisor && count) { |
||
775 | for (i = 0; i < count; i++) { |
||
776 | if (link_bw == divisor[i].link_bw) { |
||
777 | pipe_config->dpll = divisor[i].dpll; |
||
5060 | serge | 778 | pipe_config->clock_set = true; |
4560 | Serge | 779 | break; |
780 | } |
||
781 | } |
||
4104 | Serge | 782 | } |
783 | } |
||
784 | |||
5060 | serge | 785 | static void |
786 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) |
||
787 | { |
||
788 | struct drm_device *dev = crtc->base.dev; |
||
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
790 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
||
791 | |||
792 | I915_WRITE(PIPE_DATA_M2(transcoder), |
||
793 | TU_SIZE(m_n->tu) | m_n->gmch_m); |
||
794 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); |
||
795 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); |
||
796 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); |
||
797 | } |
||
798 | |||
3243 | Serge | 799 | bool |
3746 | Serge | 800 | intel_dp_compute_config(struct intel_encoder *encoder, |
801 | struct intel_crtc_config *pipe_config) |
||
2330 | Serge | 802 | { |
3746 | Serge | 803 | struct drm_device *dev = encoder->base.dev; |
804 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
805 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
||
806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
4104 | Serge | 807 | enum port port = dp_to_dig_port(intel_dp)->port; |
808 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
||
3243 | Serge | 809 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2330 | Serge | 810 | int lane_count, clock; |
5060 | serge | 811 | int min_lane_count = 1; |
812 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
||
813 | /* Conveniently, the link BW constants become indices with a shift...*/ |
||
814 | int min_clock = 0; |
||
815 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
||
3031 | serge | 816 | int bpp, mode_rate; |
5060 | serge | 817 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
4104 | Serge | 818 | int link_avail, link_clock; |
2330 | Serge | 819 | |
4104 | Serge | 820 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
3746 | Serge | 821 | pipe_config->has_pch_encoder = true; |
822 | |||
823 | pipe_config->has_dp_encoder = true; |
||
5060 | serge | 824 | pipe_config->has_audio = intel_dp->has_audio; |
3746 | Serge | 825 | |
3243 | Serge | 826 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
827 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
||
828 | adjusted_mode); |
||
4104 | Serge | 829 | if (!HAS_PCH_SPLIT(dev)) |
830 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
||
831 | intel_connector->panel.fitting_mode); |
||
832 | else |
||
833 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
||
834 | intel_connector->panel.fitting_mode); |
||
2330 | Serge | 835 | } |
836 | |||
3031 | serge | 837 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
838 | return false; |
||
839 | |||
840 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
||
841 | "max bw %02x pixel clock %iKHz\n", |
||
4560 | Serge | 842 | max_lane_count, bws[max_clock], |
843 | adjusted_mode->crtc_clock); |
||
3031 | serge | 844 | |
3746 | Serge | 845 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
846 | * bpc in between. */ |
||
4104 | Serge | 847 | bpp = pipe_config->pipe_bpp; |
5060 | serge | 848 | if (is_edp(intel_dp)) { |
849 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { |
||
4104 | Serge | 850 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
851 | dev_priv->vbt.edp_bpp); |
||
4560 | Serge | 852 | bpp = dev_priv->vbt.edp_bpp; |
4104 | Serge | 853 | } |
3746 | Serge | 854 | |
5060 | serge | 855 | if (IS_BROADWELL(dev)) { |
856 | /* Yes, it's an ugly hack. */ |
||
857 | min_lane_count = max_lane_count; |
||
858 | DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", |
||
859 | min_lane_count); |
||
860 | } else if (dev_priv->vbt.edp_lanes) { |
||
861 | min_lane_count = min(dev_priv->vbt.edp_lanes, |
||
862 | max_lane_count); |
||
863 | DRM_DEBUG_KMS("using min %u lanes per VBT\n", |
||
864 | min_lane_count); |
||
865 | } |
||
866 | |||
867 | if (dev_priv->vbt.edp_rate) { |
||
868 | min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); |
||
869 | DRM_DEBUG_KMS("using min %02x link bw per VBT\n", |
||
870 | bws[min_clock]); |
||
871 | } |
||
872 | } |
||
873 | |||
3746 | Serge | 874 | for (; bpp >= 6*3; bpp -= 2*3) { |
4560 | Serge | 875 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
876 | bpp); |
||
3746 | Serge | 877 | |
5060 | serge | 878 | for (clock = min_clock; clock <= max_clock; clock++) { |
879 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { |
||
3746 | Serge | 880 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
881 | link_avail = intel_dp_max_data_rate(link_clock, |
||
882 | lane_count); |
||
883 | |||
884 | if (mode_rate <= link_avail) { |
||
885 | goto found; |
||
886 | } |
||
887 | } |
||
888 | } |
||
889 | } |
||
890 | |||
3031 | serge | 891 | return false; |
892 | |||
3746 | Serge | 893 | found: |
3480 | Serge | 894 | if (intel_dp->color_range_auto) { |
895 | /* |
||
896 | * See: |
||
897 | * CEA-861-E - 5.1 Default Encoding Parameters |
||
898 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
||
899 | */ |
||
900 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
||
901 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
||
902 | else |
||
903 | intel_dp->color_range = 0; |
||
904 | } |
||
905 | |||
906 | if (intel_dp->color_range) |
||
3746 | Serge | 907 | pipe_config->limited_color_range = true; |
3480 | Serge | 908 | |
2330 | Serge | 909 | intel_dp->link_bw = bws[clock]; |
910 | intel_dp->lane_count = lane_count; |
||
3746 | Serge | 911 | pipe_config->pipe_bpp = bpp; |
4104 | Serge | 912 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
3746 | Serge | 913 | |
914 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
||
2330 | Serge | 915 | intel_dp->link_bw, intel_dp->lane_count, |
4104 | Serge | 916 | pipe_config->port_clock, bpp); |
3031 | serge | 917 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
918 | mode_rate, link_avail); |
||
2330 | Serge | 919 | |
3746 | Serge | 920 | intel_link_compute_m_n(bpp, lane_count, |
4560 | Serge | 921 | adjusted_mode->crtc_clock, |
922 | pipe_config->port_clock, |
||
3746 | Serge | 923 | &pipe_config->dp_m_n); |
2330 | Serge | 924 | |
5060 | serge | 925 | if (intel_connector->panel.downclock_mode != NULL && |
926 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
||
927 | intel_link_compute_m_n(bpp, lane_count, |
||
928 | intel_connector->panel.downclock_mode->clock, |
||
929 | pipe_config->port_clock, |
||
930 | &pipe_config->dp_m2_n2); |
||
931 | } |
||
932 | |||
933 | if (HAS_DDI(dev)) |
||
934 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
||
935 | else |
||
4104 | Serge | 936 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
937 | |||
3746 | Serge | 938 | return true; |
2327 | Serge | 939 | } |
940 | |||
4104 | Serge | 941 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
3480 | Serge | 942 | { |
4104 | Serge | 943 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
944 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
||
945 | struct drm_device *dev = crtc->base.dev; |
||
3480 | Serge | 946 | struct drm_i915_private *dev_priv = dev->dev_private; |
947 | u32 dpa_ctl; |
||
948 | |||
4104 | Serge | 949 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
3480 | Serge | 950 | dpa_ctl = I915_READ(DP_A); |
951 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
||
952 | |||
4104 | Serge | 953 | if (crtc->config.port_clock == 162000) { |
3480 | Serge | 954 | /* For a long time we've carried around a ILK-DevA w/a for the |
955 | * 160MHz clock. If we're really unlucky, it's still required. |
||
956 | */ |
||
957 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
||
958 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
||
4104 | Serge | 959 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
3480 | Serge | 960 | } else { |
961 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
||
4104 | Serge | 962 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
3480 | Serge | 963 | } |
964 | |||
965 | I915_WRITE(DP_A, dpa_ctl); |
||
966 | |||
967 | POSTING_READ(DP_A); |
||
968 | udelay(500); |
||
969 | } |
||
970 | |||
5060 | serge | 971 | static void intel_dp_prepare(struct intel_encoder *encoder) |
2330 | Serge | 972 | { |
4104 | Serge | 973 | struct drm_device *dev = encoder->base.dev; |
2342 | Serge | 974 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 975 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
976 | enum port port = dp_to_dig_port(intel_dp)->port; |
||
977 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
978 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
||
2327 | Serge | 979 | |
2342 | Serge | 980 | /* |
981 | * There are four kinds of DP registers: |
||
982 | * |
||
983 | * IBX PCH |
||
984 | * SNB CPU |
||
985 | * IVB CPU |
||
986 | * CPT PCH |
||
987 | * |
||
988 | * IBX PCH and CPU are the same for almost everything, |
||
989 | * except that the CPU DP PLL is configured in this |
||
990 | * register |
||
991 | * |
||
992 | * CPT PCH is quite different, having many bits moved |
||
993 | * to the TRANS_DP_CTL register instead. That |
||
994 | * configuration happens (oddly) in ironlake_pch_enable |
||
995 | */ |
||
2327 | Serge | 996 | |
2342 | Serge | 997 | /* Preserve the BIOS-computed detected bit. This is |
998 | * supposed to be read-only. |
||
999 | */ |
||
1000 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
||
2327 | Serge | 1001 | |
2342 | Serge | 1002 | /* Handle DP bits in common between all three register formats */ |
1003 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
||
4104 | Serge | 1004 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
2342 | Serge | 1005 | |
5060 | serge | 1006 | if (crtc->config.has_audio) { |
2342 | Serge | 1007 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
4104 | Serge | 1008 | pipe_name(crtc->pipe)); |
2330 | Serge | 1009 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
4104 | Serge | 1010 | intel_write_eld(&encoder->base, adjusted_mode); |
2342 | Serge | 1011 | } |
2327 | Serge | 1012 | |
2342 | Serge | 1013 | /* Split out the IBX/CPU vs CPT settings */ |
1014 | |||
4104 | Serge | 1015 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
2342 | Serge | 1016 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1017 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
1018 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
1019 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
1020 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
||
1021 | |||
4560 | Serge | 1022 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2342 | Serge | 1023 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1024 | |||
4104 | Serge | 1025 | intel_dp->DP |= crtc->pipe << 29; |
1026 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
||
3746 | Serge | 1027 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
2342 | Serge | 1028 | intel_dp->DP |= intel_dp->color_range; |
1029 | |||
1030 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
||
1031 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
1032 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
1033 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
1034 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
||
1035 | |||
4560 | Serge | 1036 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2342 | Serge | 1037 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1038 | |||
5060 | serge | 1039 | if (!IS_CHERRYVIEW(dev)) { |
4104 | Serge | 1040 | if (crtc->pipe == 1) |
2330 | Serge | 1041 | intel_dp->DP |= DP_PIPEB_SELECT; |
2342 | Serge | 1042 | } else { |
5060 | serge | 1043 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1044 | } |
||
1045 | } else { |
||
2342 | Serge | 1046 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1047 | } |
||
2330 | Serge | 1048 | } |
2327 | Serge | 1049 | |
5060 | serge | 1050 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1051 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
||
2342 | Serge | 1052 | |
5060 | serge | 1053 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1054 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
||
2342 | Serge | 1055 | |
5060 | serge | 1056 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1057 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
||
2342 | Serge | 1058 | |
5060 | serge | 1059 | static void wait_panel_status(struct intel_dp *intel_dp, |
2342 | Serge | 1060 | u32 mask, |
1061 | u32 value) |
||
1062 | { |
||
3243 | Serge | 1063 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1064 | struct drm_i915_private *dev_priv = dev->dev_private; |
3746 | Serge | 1065 | u32 pp_stat_reg, pp_ctrl_reg; |
2342 | Serge | 1066 | |
4560 | Serge | 1067 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1068 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
||
3746 | Serge | 1069 | |
2342 | Serge | 1070 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1071 | mask, value, |
||
3746 | Serge | 1072 | I915_READ(pp_stat_reg), |
1073 | I915_READ(pp_ctrl_reg)); |
||
2342 | Serge | 1074 | |
3746 | Serge | 1075 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
2342 | Serge | 1076 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
3746 | Serge | 1077 | I915_READ(pp_stat_reg), |
1078 | I915_READ(pp_ctrl_reg)); |
||
2342 | Serge | 1079 | } |
4560 | Serge | 1080 | |
1081 | DRM_DEBUG_KMS("Wait complete\n"); |
||
2342 | Serge | 1082 | } |
1083 | |||
5060 | serge | 1084 | static void wait_panel_on(struct intel_dp *intel_dp) |
2342 | Serge | 1085 | { |
1086 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
||
5060 | serge | 1087 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
2342 | Serge | 1088 | } |
1089 | |||
5060 | serge | 1090 | static void wait_panel_off(struct intel_dp *intel_dp) |
2342 | Serge | 1091 | { |
1092 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
||
5060 | serge | 1093 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
2342 | Serge | 1094 | } |
1095 | |||
5060 | serge | 1096 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
2342 | Serge | 1097 | { |
1098 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
||
5060 | serge | 1099 | |
1100 | /* When we disable the VDD override bit last we have to do the manual |
||
1101 | * wait. */ |
||
1102 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
||
1103 | intel_dp->panel_power_cycle_delay); |
||
1104 | |||
1105 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
||
2342 | Serge | 1106 | } |
1107 | |||
5060 | serge | 1108 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1109 | { |
||
1110 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
||
1111 | intel_dp->backlight_on_delay); |
||
1112 | } |
||
2342 | Serge | 1113 | |
5060 | serge | 1114 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1115 | { |
||
1116 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
||
1117 | intel_dp->backlight_off_delay); |
||
1118 | } |
||
1119 | |||
2342 | Serge | 1120 | /* Read the current pp_control value, unlocking the register if it |
1121 | * is locked |
||
1122 | */ |
||
1123 | |||
3746 | Serge | 1124 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
2342 | Serge | 1125 | { |
3746 | Serge | 1126 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1128 | u32 control; |
||
2342 | Serge | 1129 | |
4560 | Serge | 1130 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
2342 | Serge | 1131 | control &= ~PANEL_UNLOCK_MASK; |
1132 | control |= PANEL_UNLOCK_REGS; |
||
1133 | return control; |
||
1134 | } |
||
1135 | |||
5060 | serge | 1136 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
2330 | Serge | 1137 | { |
3243 | Serge | 1138 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5060 | serge | 1139 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1140 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2330 | Serge | 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 1142 | enum intel_display_power_domain power_domain; |
2330 | Serge | 1143 | u32 pp; |
3746 | Serge | 1144 | u32 pp_stat_reg, pp_ctrl_reg; |
5060 | serge | 1145 | bool need_to_disable = !intel_dp->want_panel_vdd; |
2327 | Serge | 1146 | |
2342 | Serge | 1147 | if (!is_edp(intel_dp)) |
5060 | serge | 1148 | return false; |
2327 | Serge | 1149 | |
2342 | Serge | 1150 | intel_dp->want_panel_vdd = true; |
1151 | |||
5060 | serge | 1152 | if (edp_have_panel_vdd(intel_dp)) |
1153 | return need_to_disable; |
||
2342 | Serge | 1154 | |
5060 | serge | 1155 | power_domain = intel_display_port_power_domain(intel_encoder); |
1156 | intel_display_power_get(dev_priv, power_domain); |
||
4560 | Serge | 1157 | |
1158 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
||
1159 | |||
5060 | serge | 1160 | if (!edp_have_panel_power(intel_dp)) |
1161 | wait_panel_power_cycle(intel_dp); |
||
2342 | Serge | 1162 | |
3746 | Serge | 1163 | pp = ironlake_get_pp_control(intel_dp); |
2330 | Serge | 1164 | pp |= EDP_FORCE_VDD; |
2342 | Serge | 1165 | |
4560 | Serge | 1166 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1167 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
||
3746 | Serge | 1168 | |
1169 | I915_WRITE(pp_ctrl_reg, pp); |
||
1170 | POSTING_READ(pp_ctrl_reg); |
||
1171 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
||
1172 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
||
2342 | Serge | 1173 | /* |
1174 | * If the panel wasn't on, delay before accessing aux channel |
||
1175 | */ |
||
5060 | serge | 1176 | if (!edp_have_panel_power(intel_dp)) { |
2342 | Serge | 1177 | DRM_DEBUG_KMS("eDP was not running\n"); |
1178 | msleep(intel_dp->panel_power_up_delay); |
||
1179 | } |
||
5060 | serge | 1180 | |
1181 | return need_to_disable; |
||
2330 | Serge | 1182 | } |
2327 | Serge | 1183 | |
5060 | serge | 1184 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
2330 | Serge | 1185 | { |
5060 | serge | 1186 | if (is_edp(intel_dp)) { |
1187 | bool vdd = _edp_panel_vdd_on(intel_dp); |
||
1188 | |||
1189 | WARN(!vdd, "eDP VDD already requested on\n"); |
||
1190 | } |
||
1191 | } |
||
1192 | |||
1193 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
||
1194 | { |
||
3243 | Serge | 1195 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1196 | struct drm_i915_private *dev_priv = dev->dev_private; |
1197 | u32 pp; |
||
3746 | Serge | 1198 | u32 pp_stat_reg, pp_ctrl_reg; |
2327 | Serge | 1199 | |
5060 | serge | 1200 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
3480 | Serge | 1201 | |
5060 | serge | 1202 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
1203 | struct intel_digital_port *intel_dig_port = |
||
1204 | dp_to_dig_port(intel_dp); |
||
1205 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
1206 | enum intel_display_power_domain power_domain; |
||
1207 | |||
4560 | Serge | 1208 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1209 | |||
3746 | Serge | 1210 | pp = ironlake_get_pp_control(intel_dp); |
2330 | Serge | 1211 | pp &= ~EDP_FORCE_VDD; |
2327 | Serge | 1212 | |
4560 | Serge | 1213 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1214 | pp_stat_reg = _pp_stat_reg(intel_dp); |
||
3746 | Serge | 1215 | |
1216 | I915_WRITE(pp_ctrl_reg, pp); |
||
1217 | POSTING_READ(pp_ctrl_reg); |
||
1218 | |||
2330 | Serge | 1219 | /* Make sure sequencer is idle before allowing subsequent activity */ |
3746 | Serge | 1220 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1221 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
||
4560 | Serge | 1222 | |
1223 | if ((pp & POWER_TARGET_ON) == 0) |
||
5060 | serge | 1224 | intel_dp->last_power_cycle = jiffies; |
4560 | Serge | 1225 | |
5060 | serge | 1226 | power_domain = intel_display_port_power_domain(intel_encoder); |
1227 | intel_display_power_put(dev_priv, power_domain); |
||
2342 | Serge | 1228 | } |
2330 | Serge | 1229 | } |
2327 | Serge | 1230 | |
5060 | serge | 1231 | static void edp_panel_vdd_work(struct work_struct *__work) |
3243 | Serge | 1232 | { |
3482 | Serge | 1233 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1234 | struct intel_dp, panel_vdd_work); |
||
1235 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
1236 | |||
5060 | serge | 1237 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
1238 | edp_panel_vdd_off_sync(intel_dp); |
||
1239 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
||
3243 | Serge | 1240 | } |
2342 | Serge | 1241 | |
5060 | serge | 1242 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2330 | Serge | 1243 | { |
5060 | serge | 1244 | unsigned long delay; |
1245 | |||
1246 | /* |
||
1247 | * Queue the timer to fire a long time from now (relative to the power |
||
1248 | * down delay) to keep the panel power up across a sequence of |
||
1249 | * operations. |
||
1250 | */ |
||
1251 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
||
1252 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
||
1253 | } |
||
1254 | |||
1255 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
||
1256 | { |
||
2342 | Serge | 1257 | if (!is_edp(intel_dp)) |
1258 | return; |
||
1259 | |||
1260 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
||
1261 | |||
1262 | intel_dp->want_panel_vdd = false; |
||
1263 | |||
5060 | serge | 1264 | if (sync) |
1265 | edp_panel_vdd_off_sync(intel_dp); |
||
1266 | else |
||
1267 | edp_panel_vdd_schedule_off(intel_dp); |
||
2342 | Serge | 1268 | } |
1269 | |||
5060 | serge | 1270 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2342 | Serge | 1271 | { |
3243 | Serge | 1272 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1273 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | Serge | 1274 | u32 pp; |
3746 | Serge | 1275 | u32 pp_ctrl_reg; |
2327 | Serge | 1276 | |
2342 | Serge | 1277 | if (!is_edp(intel_dp)) |
1278 | return; |
||
2327 | Serge | 1279 | |
2342 | Serge | 1280 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
2327 | Serge | 1281 | |
5060 | serge | 1282 | if (edp_have_panel_power(intel_dp)) { |
2342 | Serge | 1283 | DRM_DEBUG_KMS("eDP power already on\n"); |
1284 | return; |
||
1285 | } |
||
1286 | |||
5060 | serge | 1287 | wait_panel_power_cycle(intel_dp); |
2342 | Serge | 1288 | |
4560 | Serge | 1289 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
3746 | Serge | 1290 | pp = ironlake_get_pp_control(intel_dp); |
2342 | Serge | 1291 | if (IS_GEN5(dev)) { |
2330 | Serge | 1292 | /* ILK workaround: disable reset around power sequence */ |
1293 | pp &= ~PANEL_POWER_RESET; |
||
4560 | Serge | 1294 | I915_WRITE(pp_ctrl_reg, pp); |
1295 | POSTING_READ(pp_ctrl_reg); |
||
2342 | Serge | 1296 | } |
2327 | Serge | 1297 | |
2342 | Serge | 1298 | pp |= POWER_TARGET_ON; |
1299 | if (!IS_GEN5(dev)) |
||
1300 | pp |= PANEL_POWER_RESET; |
||
1301 | |||
3746 | Serge | 1302 | I915_WRITE(pp_ctrl_reg, pp); |
1303 | POSTING_READ(pp_ctrl_reg); |
||
1304 | |||
5060 | serge | 1305 | wait_panel_on(intel_dp); |
1306 | intel_dp->last_power_on = jiffies; |
||
2327 | Serge | 1307 | |
2342 | Serge | 1308 | if (IS_GEN5(dev)) { |
2330 | Serge | 1309 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
4560 | Serge | 1310 | I915_WRITE(pp_ctrl_reg, pp); |
1311 | POSTING_READ(pp_ctrl_reg); |
||
2342 | Serge | 1312 | } |
2330 | Serge | 1313 | } |
2327 | Serge | 1314 | |
5060 | serge | 1315 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2330 | Serge | 1316 | { |
5060 | serge | 1317 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1318 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3243 | Serge | 1319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 1321 | enum intel_display_power_domain power_domain; |
2342 | Serge | 1322 | u32 pp; |
3746 | Serge | 1323 | u32 pp_ctrl_reg; |
2327 | Serge | 1324 | |
2342 | Serge | 1325 | if (!is_edp(intel_dp)) |
1326 | return; |
||
2327 | Serge | 1327 | |
2342 | Serge | 1328 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
2327 | Serge | 1329 | |
5060 | serge | 1330 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
1331 | |||
3746 | Serge | 1332 | pp = ironlake_get_pp_control(intel_dp); |
3031 | serge | 1333 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1334 | * panels get very unhappy and cease to work. */ |
||
5060 | serge | 1335 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
1336 | EDP_BLC_ENABLE); |
||
2327 | Serge | 1337 | |
4560 | Serge | 1338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
3746 | Serge | 1339 | |
5060 | serge | 1340 | intel_dp->want_panel_vdd = false; |
1341 | |||
3746 | Serge | 1342 | I915_WRITE(pp_ctrl_reg, pp); |
1343 | POSTING_READ(pp_ctrl_reg); |
||
1344 | |||
5060 | serge | 1345 | intel_dp->last_power_cycle = jiffies; |
1346 | wait_panel_off(intel_dp); |
||
1347 | |||
1348 | /* We got a reference when we enabled the VDD. */ |
||
1349 | power_domain = intel_display_port_power_domain(intel_encoder); |
||
1350 | intel_display_power_put(dev_priv, power_domain); |
||
2330 | Serge | 1351 | } |
2327 | Serge | 1352 | |
5060 | serge | 1353 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2330 | Serge | 1354 | { |
3243 | Serge | 1355 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1356 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
1358 | u32 pp; |
||
3746 | Serge | 1359 | u32 pp_ctrl_reg; |
2327 | Serge | 1360 | |
2342 | Serge | 1361 | if (!is_edp(intel_dp)) |
1362 | return; |
||
1363 | |||
2330 | Serge | 1364 | DRM_DEBUG_KMS("\n"); |
5060 | serge | 1365 | |
1366 | intel_panel_enable_backlight(intel_dp->attached_connector); |
||
1367 | |||
2330 | Serge | 1368 | /* |
1369 | * If we enable the backlight right away following a panel power |
||
1370 | * on, we may see slight flicker as the panel syncs with the eDP |
||
1371 | * link. So delay a bit to make sure the image is solid before |
||
1372 | * allowing it to appear. |
||
1373 | */ |
||
5060 | serge | 1374 | wait_backlight_on(intel_dp); |
3746 | Serge | 1375 | pp = ironlake_get_pp_control(intel_dp); |
2330 | Serge | 1376 | pp |= EDP_BLC_ENABLE; |
3243 | Serge | 1377 | |
4560 | Serge | 1378 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
3746 | Serge | 1379 | |
1380 | I915_WRITE(pp_ctrl_reg, pp); |
||
1381 | POSTING_READ(pp_ctrl_reg); |
||
2330 | Serge | 1382 | } |
2327 | Serge | 1383 | |
5060 | serge | 1384 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2330 | Serge | 1385 | { |
3243 | Serge | 1386 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
1388 | u32 pp; |
||
3746 | Serge | 1389 | u32 pp_ctrl_reg; |
2327 | Serge | 1390 | |
2342 | Serge | 1391 | if (!is_edp(intel_dp)) |
1392 | return; |
||
1393 | |||
2330 | Serge | 1394 | DRM_DEBUG_KMS("\n"); |
3746 | Serge | 1395 | pp = ironlake_get_pp_control(intel_dp); |
2330 | Serge | 1396 | pp &= ~EDP_BLC_ENABLE; |
3746 | Serge | 1397 | |
4560 | Serge | 1398 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
3746 | Serge | 1399 | |
1400 | I915_WRITE(pp_ctrl_reg, pp); |
||
1401 | POSTING_READ(pp_ctrl_reg); |
||
5060 | serge | 1402 | intel_dp->last_backlight_off = jiffies; |
1403 | |||
1404 | edp_wait_backlight_off(intel_dp); |
||
1405 | |||
1406 | intel_panel_disable_backlight(intel_dp->attached_connector); |
||
2330 | Serge | 1407 | } |
2327 | Serge | 1408 | |
3031 | serge | 1409 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2330 | Serge | 1410 | { |
3243 | Serge | 1411 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1412 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1413 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1414 | struct drm_i915_private *dev_priv = dev->dev_private; |
1415 | u32 dpa_ctl; |
||
2327 | Serge | 1416 | |
3031 | serge | 1417 | assert_pipe_disabled(dev_priv, |
1418 | to_intel_crtc(crtc)->pipe); |
||
1419 | |||
2330 | Serge | 1420 | DRM_DEBUG_KMS("\n"); |
1421 | dpa_ctl = I915_READ(DP_A); |
||
3031 | serge | 1422 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1423 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1424 | |||
1425 | /* We don't adjust intel_dp->DP while tearing down the link, to |
||
1426 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
||
1427 | * enable bits here to ensure that we don't enable too much. */ |
||
1428 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
||
1429 | intel_dp->DP |= DP_PLL_ENABLE; |
||
1430 | I915_WRITE(DP_A, intel_dp->DP); |
||
2330 | Serge | 1431 | POSTING_READ(DP_A); |
1432 | udelay(200); |
||
1433 | } |
||
2327 | Serge | 1434 | |
3031 | serge | 1435 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2330 | Serge | 1436 | { |
3243 | Serge | 1437 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1438 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1439 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1440 | struct drm_i915_private *dev_priv = dev->dev_private; |
1441 | u32 dpa_ctl; |
||
2327 | Serge | 1442 | |
3031 | serge | 1443 | assert_pipe_disabled(dev_priv, |
1444 | to_intel_crtc(crtc)->pipe); |
||
1445 | |||
2330 | Serge | 1446 | dpa_ctl = I915_READ(DP_A); |
3031 | serge | 1447 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1448 | "dp pll off, should be on\n"); |
||
1449 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1450 | |||
1451 | /* We can't rely on the value tracked for the DP register in |
||
1452 | * intel_dp->DP because link_down must not change that (otherwise link |
||
1453 | * re-training will fail. */ |
||
2330 | Serge | 1454 | dpa_ctl &= ~DP_PLL_ENABLE; |
1455 | I915_WRITE(DP_A, dpa_ctl); |
||
1456 | POSTING_READ(DP_A); |
||
1457 | udelay(200); |
||
1458 | } |
||
2327 | Serge | 1459 | |
2330 | Serge | 1460 | /* If the sink supports it, try to set the power state appropriately */ |
3243 | Serge | 1461 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2330 | Serge | 1462 | { |
1463 | int ret, i; |
||
2327 | Serge | 1464 | |
2330 | Serge | 1465 | /* Should have a valid DPCD by this point */ |
1466 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
||
1467 | return; |
||
2327 | Serge | 1468 | |
2330 | Serge | 1469 | if (mode != DRM_MODE_DPMS_ON) { |
5060 | serge | 1470 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2330 | Serge | 1471 | DP_SET_POWER_D3); |
1472 | if (ret != 1) |
||
1473 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
||
1474 | } else { |
||
1475 | /* |
||
1476 | * When turning on, we need to retry for 1ms to give the sink |
||
1477 | * time to wake up. |
||
1478 | */ |
||
1479 | for (i = 0; i < 3; i++) { |
||
5060 | serge | 1480 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2330 | Serge | 1481 | DP_SET_POWER_D0); |
1482 | if (ret == 1) |
||
1483 | break; |
||
1484 | msleep(1); |
||
1485 | } |
||
1486 | } |
||
1487 | } |
||
2327 | Serge | 1488 | |
3031 | serge | 1489 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1490 | enum pipe *pipe) |
||
2330 | Serge | 1491 | { |
3031 | serge | 1492 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
4104 | Serge | 1493 | enum port port = dp_to_dig_port(intel_dp)->port; |
3031 | serge | 1494 | struct drm_device *dev = encoder->base.dev; |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 1496 | enum intel_display_power_domain power_domain; |
1497 | u32 tmp; |
||
2327 | Serge | 1498 | |
5060 | serge | 1499 | power_domain = intel_display_port_power_domain(encoder); |
1500 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
||
1501 | return false; |
||
1502 | |||
1503 | tmp = I915_READ(intel_dp->output_reg); |
||
1504 | |||
3031 | serge | 1505 | if (!(tmp & DP_PORT_EN)) |
1506 | return false; |
||
2342 | Serge | 1507 | |
4104 | Serge | 1508 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
3031 | serge | 1509 | *pipe = PORT_TO_PIPE_CPT(tmp); |
5060 | serge | 1510 | } else if (IS_CHERRYVIEW(dev)) { |
1511 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
||
4104 | Serge | 1512 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
3031 | serge | 1513 | *pipe = PORT_TO_PIPE(tmp); |
1514 | } else { |
||
1515 | u32 trans_sel; |
||
1516 | u32 trans_dp; |
||
1517 | int i; |
||
2327 | Serge | 1518 | |
3031 | serge | 1519 | switch (intel_dp->output_reg) { |
1520 | case PCH_DP_B: |
||
1521 | trans_sel = TRANS_DP_PORT_SEL_B; |
||
1522 | break; |
||
1523 | case PCH_DP_C: |
||
1524 | trans_sel = TRANS_DP_PORT_SEL_C; |
||
1525 | break; |
||
1526 | case PCH_DP_D: |
||
1527 | trans_sel = TRANS_DP_PORT_SEL_D; |
||
1528 | break; |
||
1529 | default: |
||
1530 | return true; |
||
1531 | } |
||
1532 | |||
1533 | for_each_pipe(i) { |
||
1534 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
||
1535 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
||
1536 | *pipe = i; |
||
1537 | return true; |
||
1538 | } |
||
1539 | } |
||
3243 | Serge | 1540 | |
1541 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
||
1542 | intel_dp->output_reg); |
||
3031 | serge | 1543 | } |
1544 | |||
1545 | return true; |
||
2330 | Serge | 1546 | } |
2327 | Serge | 1547 | |
4104 | Serge | 1548 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1549 | struct intel_crtc_config *pipe_config) |
||
1550 | { |
||
1551 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
1552 | u32 tmp, flags = 0; |
||
1553 | struct drm_device *dev = encoder->base.dev; |
||
1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1555 | enum port port = dp_to_dig_port(intel_dp)->port; |
||
1556 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
||
4560 | Serge | 1557 | int dotclock; |
4104 | Serge | 1558 | |
5060 | serge | 1559 | tmp = I915_READ(intel_dp->output_reg); |
1560 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) |
||
1561 | pipe_config->has_audio = true; |
||
1562 | |||
4104 | Serge | 1563 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1564 | if (tmp & DP_SYNC_HS_HIGH) |
||
1565 | flags |= DRM_MODE_FLAG_PHSYNC; |
||
1566 | else |
||
1567 | flags |= DRM_MODE_FLAG_NHSYNC; |
||
1568 | |||
1569 | if (tmp & DP_SYNC_VS_HIGH) |
||
1570 | flags |= DRM_MODE_FLAG_PVSYNC; |
||
1571 | else |
||
1572 | flags |= DRM_MODE_FLAG_NVSYNC; |
||
1573 | } else { |
||
1574 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
||
1575 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
||
1576 | flags |= DRM_MODE_FLAG_PHSYNC; |
||
1577 | else |
||
1578 | flags |= DRM_MODE_FLAG_NHSYNC; |
||
1579 | |||
1580 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
||
1581 | flags |= DRM_MODE_FLAG_PVSYNC; |
||
1582 | else |
||
1583 | flags |= DRM_MODE_FLAG_NVSYNC; |
||
1584 | } |
||
1585 | |||
1586 | pipe_config->adjusted_mode.flags |= flags; |
||
1587 | |||
4560 | Serge | 1588 | pipe_config->has_dp_encoder = true; |
1589 | |||
1590 | intel_dp_get_m_n(crtc, pipe_config); |
||
1591 | |||
1592 | if (port == PORT_A) { |
||
4104 | Serge | 1593 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1594 | pipe_config->port_clock = 162000; |
||
1595 | else |
||
1596 | pipe_config->port_clock = 270000; |
||
1597 | } |
||
4280 | Serge | 1598 | |
4560 | Serge | 1599 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1600 | &pipe_config->dp_m_n); |
||
1601 | |||
1602 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
||
1603 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
||
1604 | |||
1605 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
||
1606 | |||
4280 | Serge | 1607 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1608 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
||
1609 | /* |
||
1610 | * This is a big fat ugly hack. |
||
1611 | * |
||
1612 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
||
1613 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
||
1614 | * unknown we fail to light up. Yet the same BIOS boots up with |
||
1615 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
||
1616 | * max, not what it tells us to use. |
||
1617 | * |
||
1618 | * Note: This will still be broken if the eDP panel is not lit |
||
1619 | * up by the BIOS, and thus we can't get the mode at module |
||
1620 | * load. |
||
1621 | */ |
||
1622 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
||
1623 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
||
1624 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
||
1625 | } |
||
4104 | Serge | 1626 | } |
1627 | |||
5060 | serge | 1628 | static bool is_edp_psr(struct intel_dp *intel_dp) |
4104 | Serge | 1629 | { |
5060 | serge | 1630 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
4104 | Serge | 1631 | } |
1632 | |||
1633 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
||
1634 | { |
||
1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1636 | |||
4560 | Serge | 1637 | if (!HAS_PSR(dev)) |
4104 | Serge | 1638 | return false; |
1639 | |||
4560 | Serge | 1640 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
4104 | Serge | 1641 | } |
1642 | |||
1643 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
||
1644 | struct edp_vsc_psr *vsc_psr) |
||
1645 | { |
||
1646 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
||
1647 | struct drm_device *dev = dig_port->base.base.dev; |
||
1648 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1649 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
||
1650 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
||
1651 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
||
1652 | uint32_t *data = (uint32_t *) vsc_psr; |
||
1653 | unsigned int i; |
||
1654 | |||
1655 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
||
1656 | the video DIP being updated before program video DIP data buffer |
||
1657 | registers for DIP being updated. */ |
||
1658 | I915_WRITE(ctl_reg, 0); |
||
1659 | POSTING_READ(ctl_reg); |
||
1660 | |||
1661 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
||
1662 | if (i < sizeof(struct edp_vsc_psr)) |
||
1663 | I915_WRITE(data_reg + i, *data++); |
||
1664 | else |
||
1665 | I915_WRITE(data_reg + i, 0); |
||
1666 | } |
||
1667 | |||
1668 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
||
1669 | POSTING_READ(ctl_reg); |
||
1670 | } |
||
1671 | |||
1672 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
||
1673 | { |
||
1674 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1676 | struct edp_vsc_psr psr_vsc; |
||
1677 | |||
1678 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
||
1679 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
||
1680 | psr_vsc.sdp_header.HB0 = 0; |
||
1681 | psr_vsc.sdp_header.HB1 = 0x7; |
||
1682 | psr_vsc.sdp_header.HB2 = 0x2; |
||
1683 | psr_vsc.sdp_header.HB3 = 0x8; |
||
1684 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
||
1685 | |||
1686 | /* Avoid continuous PSR exit by masking memup and hpd */ |
||
4560 | Serge | 1687 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
4104 | Serge | 1688 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
1689 | } |
||
1690 | |||
1691 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
||
1692 | { |
||
5060 | serge | 1693 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1694 | struct drm_device *dev = dig_port->base.base.dev; |
||
4104 | Serge | 1695 | struct drm_i915_private *dev_priv = dev->dev_private; |
5060 | serge | 1696 | uint32_t aux_clock_divider; |
4104 | Serge | 1697 | int precharge = 0x3; |
1698 | int msg_size = 5; /* Header(4) + Message(1) */ |
||
5060 | serge | 1699 | bool only_standby = false; |
4104 | Serge | 1700 | |
5060 | serge | 1701 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
1702 | |||
1703 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
||
1704 | only_standby = true; |
||
1705 | |||
4104 | Serge | 1706 | /* Enable PSR in sink */ |
5060 | serge | 1707 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
1708 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
||
1709 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
||
4104 | Serge | 1710 | else |
5060 | serge | 1711 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1712 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
||
4104 | Serge | 1713 | |
1714 | /* Setup AUX registers */ |
||
4560 | Serge | 1715 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1716 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
||
1717 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
||
4104 | Serge | 1718 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1719 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
||
1720 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
||
1721 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
||
1722 | } |
||
1723 | |||
1724 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
||
1725 | { |
||
5060 | serge | 1726 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1727 | struct drm_device *dev = dig_port->base.base.dev; |
||
4104 | Serge | 1728 | struct drm_i915_private *dev_priv = dev->dev_private; |
1729 | uint32_t max_sleep_time = 0x1f; |
||
1730 | uint32_t idle_frames = 1; |
||
1731 | uint32_t val = 0x0; |
||
4560 | Serge | 1732 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
5060 | serge | 1733 | bool only_standby = false; |
4104 | Serge | 1734 | |
5060 | serge | 1735 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
1736 | only_standby = true; |
||
1737 | |||
1738 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
||
4104 | Serge | 1739 | val |= EDP_PSR_LINK_STANDBY; |
1740 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
||
1741 | val |= EDP_PSR_TP1_TIME_0us; |
||
1742 | val |= EDP_PSR_SKIP_AUX_EXIT; |
||
5060 | serge | 1743 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
4104 | Serge | 1744 | } else |
1745 | val |= EDP_PSR_LINK_DISABLE; |
||
1746 | |||
4560 | Serge | 1747 | I915_WRITE(EDP_PSR_CTL(dev), val | |
5060 | serge | 1748 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
4104 | Serge | 1749 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1750 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
||
1751 | EDP_PSR_ENABLE); |
||
1752 | } |
||
1753 | |||
1754 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
||
1755 | { |
||
1756 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
||
1757 | struct drm_device *dev = dig_port->base.base.dev; |
||
1758 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1759 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
||
1760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
1761 | |||
5060 | serge | 1762 | lockdep_assert_held(&dev_priv->psr.lock); |
1763 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
||
1764 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
||
1765 | |||
4560 | Serge | 1766 | dev_priv->psr.source_ok = false; |
1767 | |||
5060 | serge | 1768 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
4104 | Serge | 1769 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
1770 | return false; |
||
1771 | } |
||
1772 | |||
5060 | serge | 1773 | if (!i915.enable_psr) { |
4104 | Serge | 1774 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
1775 | return false; |
||
1776 | } |
||
1777 | |||
5060 | serge | 1778 | /* Below limitations aren't valid for Broadwell */ |
1779 | if (IS_BROADWELL(dev)) |
||
1780 | goto out; |
||
4104 | Serge | 1781 | |
1782 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
||
1783 | S3D_ENABLE) { |
||
1784 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
||
1785 | return false; |
||
1786 | } |
||
1787 | |||
4560 | Serge | 1788 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
4104 | Serge | 1789 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
1790 | return false; |
||
1791 | } |
||
1792 | |||
5060 | serge | 1793 | out: |
4560 | Serge | 1794 | dev_priv->psr.source_ok = true; |
4104 | Serge | 1795 | return true; |
1796 | } |
||
1797 | |||
1798 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
||
1799 | { |
||
5060 | serge | 1800 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1801 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
1802 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4104 | Serge | 1803 | |
5060 | serge | 1804 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
1805 | WARN_ON(dev_priv->psr.active); |
||
1806 | lockdep_assert_held(&dev_priv->psr.lock); |
||
4104 | Serge | 1807 | |
1808 | /* Enable PSR on the panel */ |
||
1809 | intel_edp_psr_enable_sink(intel_dp); |
||
1810 | |||
1811 | /* Enable PSR on the host */ |
||
1812 | intel_edp_psr_enable_source(intel_dp); |
||
5060 | serge | 1813 | |
1814 | dev_priv->psr.active = true; |
||
4104 | Serge | 1815 | } |
1816 | |||
1817 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
||
1818 | { |
||
1819 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
5060 | serge | 1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 1821 | |
5060 | serge | 1822 | if (!HAS_PSR(dev)) { |
1823 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
||
1824 | return; |
||
1825 | } |
||
1826 | |||
1827 | if (!is_edp_psr(intel_dp)) { |
||
1828 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
||
1829 | return; |
||
1830 | } |
||
1831 | |||
1832 | mutex_lock(&dev_priv->psr.lock); |
||
1833 | if (dev_priv->psr.enabled) { |
||
1834 | DRM_DEBUG_KMS("PSR already in use\n"); |
||
1835 | mutex_unlock(&dev_priv->psr.lock); |
||
1836 | return; |
||
1837 | } |
||
1838 | |||
1839 | dev_priv->psr.busy_frontbuffer_bits = 0; |
||
1840 | |||
1841 | /* Setup PSR once */ |
||
1842 | intel_edp_psr_setup(intel_dp); |
||
1843 | |||
1844 | if (intel_edp_psr_match_conditions(intel_dp)) |
||
1845 | dev_priv->psr.enabled = intel_dp; |
||
1846 | mutex_unlock(&dev_priv->psr.lock); |
||
4104 | Serge | 1847 | } |
1848 | |||
1849 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
||
1850 | { |
||
1851 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1853 | |||
5060 | serge | 1854 | mutex_lock(&dev_priv->psr.lock); |
1855 | if (!dev_priv->psr.enabled) { |
||
1856 | mutex_unlock(&dev_priv->psr.lock); |
||
4104 | Serge | 1857 | return; |
5060 | serge | 1858 | } |
4104 | Serge | 1859 | |
5060 | serge | 1860 | if (dev_priv->psr.active) { |
4560 | Serge | 1861 | I915_WRITE(EDP_PSR_CTL(dev), |
1862 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
||
4104 | Serge | 1863 | |
1864 | /* Wait till PSR is idle */ |
||
4560 | Serge | 1865 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
4104 | Serge | 1866 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1867 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
||
5060 | serge | 1868 | |
1869 | dev_priv->psr.active = false; |
||
1870 | } else { |
||
1871 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
||
1872 | } |
||
1873 | |||
1874 | dev_priv->psr.enabled = NULL; |
||
1875 | mutex_unlock(&dev_priv->psr.lock); |
||
1876 | |||
1877 | cancel_delayed_work_sync(&dev_priv->psr.work); |
||
4104 | Serge | 1878 | } |
1879 | |||
5060 | serge | 1880 | static void intel_edp_psr_work(struct work_struct *work) |
4104 | Serge | 1881 | { |
5060 | serge | 1882 | struct drm_i915_private *dev_priv = |
1883 | container_of(work, typeof(*dev_priv), psr.work.work); |
||
1884 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
||
4104 | Serge | 1885 | |
5060 | serge | 1886 | mutex_lock(&dev_priv->psr.lock); |
1887 | intel_dp = dev_priv->psr.enabled; |
||
4104 | Serge | 1888 | |
5060 | serge | 1889 | if (!intel_dp) |
1890 | goto unlock; |
||
1891 | |||
1892 | /* |
||
1893 | * The delayed work can race with an invalidate hence we need to |
||
1894 | * recheck. Since psr_flush first clears this and then reschedules we |
||
1895 | * won't ever miss a flush when bailing out here. |
||
1896 | */ |
||
1897 | if (dev_priv->psr.busy_frontbuffer_bits) |
||
1898 | goto unlock; |
||
1899 | |||
1900 | intel_edp_psr_do_enable(intel_dp); |
||
1901 | unlock: |
||
1902 | mutex_unlock(&dev_priv->psr.lock); |
||
1903 | } |
||
1904 | |||
1905 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
||
1906 | { |
||
1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1908 | |||
1909 | if (dev_priv->psr.active) { |
||
1910 | u32 val = I915_READ(EDP_PSR_CTL(dev)); |
||
1911 | |||
1912 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
||
1913 | |||
1914 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); |
||
1915 | |||
1916 | dev_priv->psr.active = false; |
||
1917 | } |
||
1918 | |||
1919 | } |
||
1920 | |||
1921 | void intel_edp_psr_invalidate(struct drm_device *dev, |
||
1922 | unsigned frontbuffer_bits) |
||
1923 | { |
||
1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1925 | struct drm_crtc *crtc; |
||
1926 | enum pipe pipe; |
||
1927 | |||
1928 | mutex_lock(&dev_priv->psr.lock); |
||
1929 | if (!dev_priv->psr.enabled) { |
||
1930 | mutex_unlock(&dev_priv->psr.lock); |
||
4104 | Serge | 1931 | return; |
5060 | serge | 1932 | } |
4104 | Serge | 1933 | |
5060 | serge | 1934 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
1935 | pipe = to_intel_crtc(crtc)->pipe; |
||
1936 | |||
1937 | intel_edp_psr_do_exit(dev); |
||
1938 | |||
1939 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
||
1940 | |||
1941 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
||
1942 | mutex_unlock(&dev_priv->psr.lock); |
||
1943 | } |
||
1944 | |||
1945 | void intel_edp_psr_flush(struct drm_device *dev, |
||
1946 | unsigned frontbuffer_bits) |
||
1947 | { |
||
1948 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1949 | struct drm_crtc *crtc; |
||
1950 | enum pipe pipe; |
||
1951 | |||
1952 | mutex_lock(&dev_priv->psr.lock); |
||
1953 | if (!dev_priv->psr.enabled) { |
||
1954 | mutex_unlock(&dev_priv->psr.lock); |
||
1955 | return; |
||
4104 | Serge | 1956 | } |
5060 | serge | 1957 | |
1958 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
||
1959 | pipe = to_intel_crtc(crtc)->pipe; |
||
1960 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
||
1961 | |||
1962 | /* |
||
1963 | * On Haswell sprite plane updates don't result in a psr invalidating |
||
1964 | * signal in the hardware. Which means we need to manually fake this in |
||
1965 | * software for all flushes, not just when we've seen a preceding |
||
1966 | * invalidation through frontbuffer rendering. |
||
1967 | */ |
||
1968 | if (IS_HASWELL(dev) && |
||
1969 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) |
||
1970 | intel_edp_psr_do_exit(dev); |
||
1971 | |||
1972 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
||
1973 | schedule_delayed_work(&dev_priv->psr.work, |
||
1974 | msecs_to_jiffies(100)); |
||
1975 | mutex_unlock(&dev_priv->psr.lock); |
||
4104 | Serge | 1976 | } |
1977 | |||
5060 | serge | 1978 | void intel_edp_psr_init(struct drm_device *dev) |
1979 | { |
||
1980 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1981 | |||
1982 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
||
1983 | mutex_init(&dev_priv->psr.lock); |
||
1984 | } |
||
1985 | |||
3031 | serge | 1986 | static void intel_disable_dp(struct intel_encoder *encoder) |
2330 | Serge | 1987 | { |
3031 | serge | 1988 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
4104 | Serge | 1989 | enum port port = dp_to_dig_port(intel_dp)->port; |
1990 | struct drm_device *dev = encoder->base.dev; |
||
2327 | Serge | 1991 | |
3031 | serge | 1992 | /* Make sure the panel is off before trying to change the mode. But also |
1993 | * ensure that we have vdd while we switch off the panel. */ |
||
5060 | serge | 1994 | intel_edp_panel_vdd_on(intel_dp); |
1995 | intel_edp_backlight_off(intel_dp); |
||
4560 | Serge | 1996 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
5060 | serge | 1997 | intel_edp_panel_off(intel_dp); |
2330 | Serge | 1998 | |
3031 | serge | 1999 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
4104 | Serge | 2000 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3031 | serge | 2001 | intel_dp_link_down(intel_dp); |
2002 | } |
||
2330 | Serge | 2003 | |
5060 | serge | 2004 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
3031 | serge | 2005 | { |
2006 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
4104 | Serge | 2007 | enum port port = dp_to_dig_port(intel_dp)->port; |
5060 | serge | 2008 | |
2009 | if (port != PORT_A) |
||
2010 | return; |
||
2011 | |||
2012 | intel_dp_link_down(intel_dp); |
||
2013 | ironlake_edp_pll_off(intel_dp); |
||
2014 | } |
||
2015 | |||
2016 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
||
2017 | { |
||
2018 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
2019 | |||
2020 | intel_dp_link_down(intel_dp); |
||
2021 | } |
||
2022 | |||
2023 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
||
2024 | { |
||
2025 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
2026 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
||
3746 | Serge | 2027 | struct drm_device *dev = encoder->base.dev; |
5060 | serge | 2028 | struct drm_i915_private *dev_priv = dev->dev_private; |
2029 | struct intel_crtc *intel_crtc = |
||
2030 | to_intel_crtc(encoder->base.crtc); |
||
2031 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
||
2032 | enum pipe pipe = intel_crtc->pipe; |
||
2033 | u32 val; |
||
3031 | serge | 2034 | |
2035 | intel_dp_link_down(intel_dp); |
||
5060 | serge | 2036 | |
2037 | mutex_lock(&dev_priv->dpio_lock); |
||
2038 | |||
2039 | /* Propagate soft reset to data lane reset */ |
||
2040 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
||
2041 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
2042 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
||
2043 | |||
2044 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
||
2045 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
2046 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
||
2047 | |||
2048 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
||
2049 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
2050 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
||
2051 | |||
2052 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
||
2053 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
2054 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
||
2055 | |||
2056 | mutex_unlock(&dev_priv->dpio_lock); |
||
2330 | Serge | 2057 | } |
2058 | |||
3031 | serge | 2059 | static void intel_enable_dp(struct intel_encoder *encoder) |
2330 | Serge | 2060 | { |
3031 | serge | 2061 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2062 | struct drm_device *dev = encoder->base.dev; |
||
2330 | Serge | 2063 | struct drm_i915_private *dev_priv = dev->dev_private; |
2064 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
||
2065 | |||
3031 | serge | 2066 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2067 | return; |
||
2342 | Serge | 2068 | |
5060 | serge | 2069 | intel_edp_panel_vdd_on(intel_dp); |
3031 | serge | 2070 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2330 | Serge | 2071 | intel_dp_start_link_train(intel_dp); |
5060 | serge | 2072 | intel_edp_panel_on(intel_dp); |
2073 | edp_panel_vdd_off(intel_dp, true); |
||
2330 | Serge | 2074 | intel_dp_complete_link_train(intel_dp); |
3746 | Serge | 2075 | intel_dp_stop_link_train(intel_dp); |
4560 | Serge | 2076 | } |
2077 | |||
2078 | static void g4x_enable_dp(struct intel_encoder *encoder) |
||
2079 | { |
||
2080 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
2081 | |||
2082 | intel_enable_dp(encoder); |
||
5060 | serge | 2083 | intel_edp_backlight_on(intel_dp); |
2330 | Serge | 2084 | } |
2085 | |||
4104 | Serge | 2086 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2087 | { |
||
4560 | Serge | 2088 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2089 | |||
5060 | serge | 2090 | intel_edp_backlight_on(intel_dp); |
4104 | Serge | 2091 | } |
2092 | |||
4560 | Serge | 2093 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
3031 | serge | 2094 | { |
2095 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
4104 | Serge | 2096 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3031 | serge | 2097 | |
5060 | serge | 2098 | intel_dp_prepare(encoder); |
2099 | |||
2100 | /* Only ilk+ has port A */ |
||
2101 | if (dport->port == PORT_A) { |
||
2102 | ironlake_set_pll_cpu_edp(intel_dp); |
||
3031 | serge | 2103 | ironlake_edp_pll_on(intel_dp); |
5060 | serge | 2104 | } |
3031 | serge | 2105 | } |
2106 | |||
4104 | Serge | 2107 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2108 | { |
||
2109 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
2110 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
||
2111 | struct drm_device *dev = encoder->base.dev; |
||
2112 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2113 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
||
4560 | Serge | 2114 | enum dpio_channel port = vlv_dport_to_channel(dport); |
4104 | Serge | 2115 | int pipe = intel_crtc->pipe; |
4560 | Serge | 2116 | struct edp_power_seq power_seq; |
4104 | Serge | 2117 | u32 val; |
2118 | |||
2119 | mutex_lock(&dev_priv->dpio_lock); |
||
2120 | |||
4560 | Serge | 2121 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
4104 | Serge | 2122 | val = 0; |
2123 | if (pipe) |
||
2124 | val |= (1<<21); |
||
2125 | else |
||
2126 | val &= ~(1<<21); |
||
2127 | val |= 0x001000c4; |
||
4560 | Serge | 2128 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2129 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
||
2130 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
||
4104 | Serge | 2131 | |
2132 | mutex_unlock(&dev_priv->dpio_lock); |
||
2133 | |||
5060 | serge | 2134 | if (is_edp(intel_dp)) { |
4560 | Serge | 2135 | /* init power sequencer on this pipe and port */ |
2136 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
||
2137 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
||
2138 | &power_seq); |
||
5060 | serge | 2139 | } |
4560 | Serge | 2140 | |
4104 | Serge | 2141 | intel_enable_dp(encoder); |
2142 | |||
4560 | Serge | 2143 | vlv_wait_port_ready(dev_priv, dport); |
4539 | Serge | 2144 | } |
4104 | Serge | 2145 | |
4560 | Serge | 2146 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
4104 | Serge | 2147 | { |
2148 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
2149 | struct drm_device *dev = encoder->base.dev; |
||
2150 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4560 | Serge | 2151 | struct intel_crtc *intel_crtc = |
2152 | to_intel_crtc(encoder->base.crtc); |
||
2153 | enum dpio_channel port = vlv_dport_to_channel(dport); |
||
2154 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 2155 | |
5060 | serge | 2156 | intel_dp_prepare(encoder); |
2157 | |||
4104 | Serge | 2158 | /* Program Tx lane resets to default */ |
2159 | mutex_lock(&dev_priv->dpio_lock); |
||
4560 | Serge | 2160 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
4104 | Serge | 2161 | DPIO_PCS_TX_LANE2_RESET | |
2162 | DPIO_PCS_TX_LANE1_RESET); |
||
4560 | Serge | 2163 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
4104 | Serge | 2164 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2165 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
||
2166 | (1< |
||
2167 | DPIO_PCS_CLK_SOFT_RESET); |
||
2168 | |||
2169 | /* Fix up inter-pair skew failure */ |
||
4560 | Serge | 2170 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2171 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
||
2172 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
||
4104 | Serge | 2173 | mutex_unlock(&dev_priv->dpio_lock); |
2174 | } |
||
2175 | |||
5060 | serge | 2176 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2177 | { |
||
2178 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
2179 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
||
2180 | struct drm_device *dev = encoder->base.dev; |
||
2181 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2182 | struct edp_power_seq power_seq; |
||
2183 | struct intel_crtc *intel_crtc = |
||
2184 | to_intel_crtc(encoder->base.crtc); |
||
2185 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
||
2186 | int pipe = intel_crtc->pipe; |
||
2187 | int data, i; |
||
2188 | u32 val; |
||
2189 | |||
2190 | mutex_lock(&dev_priv->dpio_lock); |
||
2191 | |||
2192 | /* Deassert soft data lane reset*/ |
||
2193 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
||
2194 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
2195 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
||
2196 | |||
2197 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
||
2198 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
||
2199 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
||
2200 | |||
2201 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
||
2202 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
2203 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
||
2204 | |||
2205 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
||
2206 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
||
2207 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
||
2208 | |||
2209 | /* Program Tx lane latency optimal setting*/ |
||
2210 | for (i = 0; i < 4; i++) { |
||
2211 | /* Set the latency optimal bit */ |
||
2212 | data = (i == 1) ? 0x0 : 0x6; |
||
2213 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), |
||
2214 | data << DPIO_FRC_LATENCY_SHFIT); |
||
2215 | |||
2216 | /* Set the upar bit */ |
||
2217 | data = (i == 1) ? 0x0 : 0x1; |
||
2218 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
||
2219 | data << DPIO_UPAR_SHIFT); |
||
2220 | } |
||
2221 | |||
2222 | /* Data lane stagger programming */ |
||
2223 | /* FIXME: Fix up value only after power analysis */ |
||
2224 | |||
2225 | mutex_unlock(&dev_priv->dpio_lock); |
||
2226 | |||
2227 | if (is_edp(intel_dp)) { |
||
2228 | /* init power sequencer on this pipe and port */ |
||
2229 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
||
2230 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
||
2231 | &power_seq); |
||
2232 | } |
||
2233 | |||
2234 | intel_enable_dp(encoder); |
||
2235 | |||
2236 | vlv_wait_port_ready(dev_priv, dport); |
||
2237 | } |
||
2238 | |||
2239 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
||
2240 | { |
||
2241 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
||
2242 | struct drm_device *dev = encoder->base.dev; |
||
2243 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2244 | struct intel_crtc *intel_crtc = |
||
2245 | to_intel_crtc(encoder->base.crtc); |
||
2246 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
||
2247 | enum pipe pipe = intel_crtc->pipe; |
||
2248 | u32 val; |
||
2249 | |||
2250 | mutex_lock(&dev_priv->dpio_lock); |
||
2251 | |||
2252 | /* program left/right clock distribution */ |
||
2253 | if (pipe != PIPE_B) { |
||
2254 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
||
2255 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
||
2256 | if (ch == DPIO_CH0) |
||
2257 | val |= CHV_BUFLEFTENA1_FORCE; |
||
2258 | if (ch == DPIO_CH1) |
||
2259 | val |= CHV_BUFRIGHTENA1_FORCE; |
||
2260 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
||
2261 | } else { |
||
2262 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
||
2263 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
||
2264 | if (ch == DPIO_CH0) |
||
2265 | val |= CHV_BUFLEFTENA2_FORCE; |
||
2266 | if (ch == DPIO_CH1) |
||
2267 | val |= CHV_BUFRIGHTENA2_FORCE; |
||
2268 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
||
2269 | } |
||
2270 | |||
2271 | /* program clock channel usage */ |
||
2272 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
||
2273 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
||
2274 | if (pipe != PIPE_B) |
||
2275 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
||
2276 | else |
||
2277 | val |= CHV_PCS_USEDCLKCHANNEL; |
||
2278 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
||
2279 | |||
2280 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
||
2281 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
||
2282 | if (pipe != PIPE_B) |
||
2283 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
||
2284 | else |
||
2285 | val |= CHV_PCS_USEDCLKCHANNEL; |
||
2286 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
||
2287 | |||
2288 | /* |
||
2289 | * This a a bit weird since generally CL |
||
2290 | * matches the pipe, but here we need to |
||
2291 | * pick the CL based on the port. |
||
2292 | */ |
||
2293 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
||
2294 | if (pipe != PIPE_B) |
||
2295 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
||
2296 | else |
||
2297 | val |= CHV_CMN_USEDCLKCHANNEL; |
||
2298 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
||
2299 | |||
2300 | mutex_unlock(&dev_priv->dpio_lock); |
||
2301 | } |
||
2302 | |||
2330 | Serge | 2303 | /* |
2304 | * Native read with retry for link status and receiver capability reads for |
||
2305 | * cases where the sink may still be asleep. |
||
5060 | serge | 2306 | * |
2307 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
||
2308 | * supposed to retry 3 times per the spec. |
||
2330 | Serge | 2309 | */ |
5060 | serge | 2310 | static ssize_t |
2311 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
||
2312 | void *buffer, size_t size) |
||
2330 | Serge | 2313 | { |
5060 | serge | 2314 | ssize_t ret; |
2315 | int i; |
||
2330 | Serge | 2316 | |
2317 | for (i = 0; i < 3; i++) { |
||
5060 | serge | 2318 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2319 | if (ret == size) |
||
2320 | return ret; |
||
2330 | Serge | 2321 | msleep(1); |
2322 | } |
||
2323 | |||
5060 | serge | 2324 | return ret; |
2330 | Serge | 2325 | } |
2326 | |||
2327 | /* |
||
2328 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
||
2329 | * link status information |
||
2330 | */ |
||
2331 | static bool |
||
2342 | Serge | 2332 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2330 | Serge | 2333 | { |
5060 | serge | 2334 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2330 | Serge | 2335 | DP_LANE0_1_STATUS, |
2342 | Serge | 2336 | link_status, |
5060 | serge | 2337 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
2330 | Serge | 2338 | } |
2339 | |||
5060 | serge | 2340 | /* These are source-specific values. */ |
2330 | Serge | 2341 | static uint8_t |
2342 | Serge | 2342 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2330 | Serge | 2343 | { |
3243 | Serge | 2344 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4104 | Serge | 2345 | enum port port = dp_to_dig_port(intel_dp)->port; |
2342 | Serge | 2346 | |
5060 | serge | 2347 | if (IS_VALLEYVIEW(dev)) |
4104 | Serge | 2348 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2349 | else if (IS_GEN7(dev) && port == PORT_A) |
||
2342 | Serge | 2350 | return DP_TRAIN_VOLTAGE_SWING_800; |
4104 | Serge | 2351 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
2342 | Serge | 2352 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2353 | else |
||
2354 | return DP_TRAIN_VOLTAGE_SWING_800; |
||
2355 | } |
||
2356 | |||
2357 | static uint8_t |
||
2358 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
||
2359 | { |
||
3243 | Serge | 2360 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4104 | Serge | 2361 | enum port port = dp_to_dig_port(intel_dp)->port; |
2342 | Serge | 2362 | |
5060 | serge | 2363 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2342 | Serge | 2364 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2365 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
3243 | Serge | 2366 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2367 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2342 | Serge | 2368 | return DP_TRAIN_PRE_EMPHASIS_6; |
3243 | Serge | 2369 | case DP_TRAIN_VOLTAGE_SWING_800: |
2370 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
2371 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2372 | default: |
||
2373 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
2374 | } |
||
4104 | Serge | 2375 | } else if (IS_VALLEYVIEW(dev)) { |
3243 | Serge | 2376 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2377 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
4104 | Serge | 2378 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2379 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
3243 | Serge | 2380 | return DP_TRAIN_PRE_EMPHASIS_6; |
4104 | Serge | 2381 | case DP_TRAIN_VOLTAGE_SWING_800: |
2382 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
2383 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2384 | default: |
||
2385 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
2386 | } |
||
2387 | } else if (IS_GEN7(dev) && port == PORT_A) { |
||
2388 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2389 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2390 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
2342 | Serge | 2391 | case DP_TRAIN_VOLTAGE_SWING_600: |
2392 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2393 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
2394 | default: |
||
2395 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
2396 | } |
||
2397 | } else { |
||
2330 | Serge | 2398 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2399 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2400 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
2401 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2402 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
2403 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2404 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
2405 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2406 | default: |
||
2407 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
2408 | } |
||
2342 | Serge | 2409 | } |
2330 | Serge | 2410 | } |
2411 | |||
4104 | Serge | 2412 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2413 | { |
||
2414 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
2415 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2416 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
||
4560 | Serge | 2417 | struct intel_crtc *intel_crtc = |
2418 | to_intel_crtc(dport->base.base.crtc); |
||
4104 | Serge | 2419 | unsigned long demph_reg_value, preemph_reg_value, |
2420 | uniqtranscale_reg_value; |
||
2421 | uint8_t train_set = intel_dp->train_set[0]; |
||
4560 | Serge | 2422 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2423 | int pipe = intel_crtc->pipe; |
||
4104 | Serge | 2424 | |
2425 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
||
2426 | case DP_TRAIN_PRE_EMPHASIS_0: |
||
2427 | preemph_reg_value = 0x0004000; |
||
2428 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2429 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2430 | demph_reg_value = 0x2B405555; |
||
2431 | uniqtranscale_reg_value = 0x552AB83A; |
||
2432 | break; |
||
2433 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2434 | demph_reg_value = 0x2B404040; |
||
2435 | uniqtranscale_reg_value = 0x5548B83A; |
||
2436 | break; |
||
2437 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2438 | demph_reg_value = 0x2B245555; |
||
2439 | uniqtranscale_reg_value = 0x5560B83A; |
||
2440 | break; |
||
2441 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2442 | demph_reg_value = 0x2B405555; |
||
2443 | uniqtranscale_reg_value = 0x5598DA3A; |
||
2444 | break; |
||
2445 | default: |
||
2446 | return 0; |
||
2447 | } |
||
2448 | break; |
||
2449 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2450 | preemph_reg_value = 0x0002000; |
||
2451 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2452 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2453 | demph_reg_value = 0x2B404040; |
||
2454 | uniqtranscale_reg_value = 0x5552B83A; |
||
2455 | break; |
||
2456 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2457 | demph_reg_value = 0x2B404848; |
||
2458 | uniqtranscale_reg_value = 0x5580B83A; |
||
2459 | break; |
||
2460 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2461 | demph_reg_value = 0x2B404040; |
||
2462 | uniqtranscale_reg_value = 0x55ADDA3A; |
||
2463 | break; |
||
2464 | default: |
||
2465 | return 0; |
||
2466 | } |
||
2467 | break; |
||
2468 | case DP_TRAIN_PRE_EMPHASIS_6: |
||
2469 | preemph_reg_value = 0x0000000; |
||
2470 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2471 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2472 | demph_reg_value = 0x2B305555; |
||
2473 | uniqtranscale_reg_value = 0x5570B83A; |
||
2474 | break; |
||
2475 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2476 | demph_reg_value = 0x2B2B4040; |
||
2477 | uniqtranscale_reg_value = 0x55ADDA3A; |
||
2478 | break; |
||
2479 | default: |
||
2480 | return 0; |
||
2481 | } |
||
2482 | break; |
||
2483 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
||
2484 | preemph_reg_value = 0x0006000; |
||
2485 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2486 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2487 | demph_reg_value = 0x1B405555; |
||
2488 | uniqtranscale_reg_value = 0x55ADDA3A; |
||
2489 | break; |
||
2490 | default: |
||
2491 | return 0; |
||
2492 | } |
||
2493 | break; |
||
2494 | default: |
||
2495 | return 0; |
||
2496 | } |
||
2497 | |||
2498 | mutex_lock(&dev_priv->dpio_lock); |
||
4560 | Serge | 2499 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2500 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
||
2501 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
||
4104 | Serge | 2502 | uniqtranscale_reg_value); |
4560 | Serge | 2503 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2504 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
||
2505 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
||
2506 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
||
4104 | Serge | 2507 | mutex_unlock(&dev_priv->dpio_lock); |
2508 | |||
2509 | return 0; |
||
2510 | } |
||
2511 | |||
5060 | serge | 2512 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
2513 | { |
||
2514 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
2515 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2516 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
||
2517 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
||
2518 | u32 deemph_reg_value, margin_reg_value, val; |
||
2519 | uint8_t train_set = intel_dp->train_set[0]; |
||
2520 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
||
2521 | enum pipe pipe = intel_crtc->pipe; |
||
2522 | int i; |
||
2523 | |||
2524 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
||
2525 | case DP_TRAIN_PRE_EMPHASIS_0: |
||
2526 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2527 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2528 | deemph_reg_value = 128; |
||
2529 | margin_reg_value = 52; |
||
2530 | break; |
||
2531 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2532 | deemph_reg_value = 128; |
||
2533 | margin_reg_value = 77; |
||
2534 | break; |
||
2535 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2536 | deemph_reg_value = 128; |
||
2537 | margin_reg_value = 102; |
||
2538 | break; |
||
2539 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2540 | deemph_reg_value = 128; |
||
2541 | margin_reg_value = 154; |
||
2542 | /* FIXME extra to set for 1200 */ |
||
2543 | break; |
||
2544 | default: |
||
2545 | return 0; |
||
2546 | } |
||
2547 | break; |
||
2548 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2549 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2550 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2551 | deemph_reg_value = 85; |
||
2552 | margin_reg_value = 78; |
||
2553 | break; |
||
2554 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2555 | deemph_reg_value = 85; |
||
2556 | margin_reg_value = 116; |
||
2557 | break; |
||
2558 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2559 | deemph_reg_value = 85; |
||
2560 | margin_reg_value = 154; |
||
2561 | break; |
||
2562 | default: |
||
2563 | return 0; |
||
2564 | } |
||
2565 | break; |
||
2566 | case DP_TRAIN_PRE_EMPHASIS_6: |
||
2567 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2568 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2569 | deemph_reg_value = 64; |
||
2570 | margin_reg_value = 104; |
||
2571 | break; |
||
2572 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2573 | deemph_reg_value = 64; |
||
2574 | margin_reg_value = 154; |
||
2575 | break; |
||
2576 | default: |
||
2577 | return 0; |
||
2578 | } |
||
2579 | break; |
||
2580 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
||
2581 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2582 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2583 | deemph_reg_value = 43; |
||
2584 | margin_reg_value = 154; |
||
2585 | break; |
||
2586 | default: |
||
2587 | return 0; |
||
2588 | } |
||
2589 | break; |
||
2590 | default: |
||
2591 | return 0; |
||
2592 | } |
||
2593 | |||
2594 | mutex_lock(&dev_priv->dpio_lock); |
||
2595 | |||
2596 | /* Clear calc init */ |
||
2597 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
||
2598 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
||
2599 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
||
2600 | |||
2601 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
||
2602 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
||
2603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
||
2604 | |||
2605 | /* Program swing deemph */ |
||
2606 | for (i = 0; i < 4; i++) { |
||
2607 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
||
2608 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
||
2609 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
||
2610 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
||
2611 | } |
||
2612 | |||
2613 | /* Program swing margin */ |
||
2614 | for (i = 0; i < 4; i++) { |
||
2615 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
||
2616 | val &= ~DPIO_SWING_MARGIN_MASK; |
||
2617 | val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; |
||
2618 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
||
2619 | } |
||
2620 | |||
2621 | /* Disable unique transition scale */ |
||
2622 | for (i = 0; i < 4; i++) { |
||
2623 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
||
2624 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
||
2625 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
||
2626 | } |
||
2627 | |||
2628 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
2629 | == DP_TRAIN_PRE_EMPHASIS_0) && |
||
2630 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
||
2631 | == DP_TRAIN_VOLTAGE_SWING_1200)) { |
||
2632 | |||
2633 | /* |
||
2634 | * The document said it needs to set bit 27 for ch0 and bit 26 |
||
2635 | * for ch1. Might be a typo in the doc. |
||
2636 | * For now, for this unique transition scale selection, set bit |
||
2637 | * 27 for ch0 and ch1. |
||
2638 | */ |
||
2639 | for (i = 0; i < 4; i++) { |
||
2640 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
||
2641 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
||
2642 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
||
2643 | } |
||
2644 | |||
2645 | for (i = 0; i < 4; i++) { |
||
2646 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
||
2647 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
||
2648 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
||
2649 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
||
2650 | } |
||
2651 | } |
||
2652 | |||
2653 | /* Start swing calculation */ |
||
2654 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
||
2655 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
||
2656 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
||
2657 | |||
2658 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
||
2659 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
||
2660 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
||
2661 | |||
2662 | /* LRC Bypass */ |
||
2663 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
||
2664 | val |= DPIO_LRC_BYPASS; |
||
2665 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
||
2666 | |||
2667 | mutex_unlock(&dev_priv->dpio_lock); |
||
2668 | |||
2669 | return 0; |
||
2670 | } |
||
2671 | |||
2330 | Serge | 2672 | static void |
4560 | Serge | 2673 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2674 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
||
2330 | Serge | 2675 | { |
2676 | uint8_t v = 0; |
||
2677 | uint8_t p = 0; |
||
2678 | int lane; |
||
2342 | Serge | 2679 | uint8_t voltage_max; |
2680 | uint8_t preemph_max; |
||
2330 | Serge | 2681 | |
2682 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
||
3243 | Serge | 2683 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2684 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
||
2330 | Serge | 2685 | |
2686 | if (this_v > v) |
||
2687 | v = this_v; |
||
2688 | if (this_p > p) |
||
2689 | p = this_p; |
||
2690 | } |
||
2691 | |||
2342 | Serge | 2692 | voltage_max = intel_dp_voltage_max(intel_dp); |
2693 | if (v >= voltage_max) |
||
2694 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
||
2330 | Serge | 2695 | |
2342 | Serge | 2696 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2697 | if (p >= preemph_max) |
||
2698 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
||
2330 | Serge | 2699 | |
2700 | for (lane = 0; lane < 4; lane++) |
||
2701 | intel_dp->train_set[lane] = v | p; |
||
2702 | } |
||
2703 | |||
2704 | static uint32_t |
||
3480 | Serge | 2705 | intel_gen4_signal_levels(uint8_t train_set) |
2330 | Serge | 2706 | { |
2707 | uint32_t signal_levels = 0; |
||
2708 | |||
2709 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
2710 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
2711 | default: |
||
2712 | signal_levels |= DP_VOLTAGE_0_4; |
||
2713 | break; |
||
2714 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2715 | signal_levels |= DP_VOLTAGE_0_6; |
||
2716 | break; |
||
2717 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
2718 | signal_levels |= DP_VOLTAGE_0_8; |
||
2719 | break; |
||
2720 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
2721 | signal_levels |= DP_VOLTAGE_1_2; |
||
2722 | break; |
||
2723 | } |
||
2724 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
||
2725 | case DP_TRAIN_PRE_EMPHASIS_0: |
||
2726 | default: |
||
2727 | signal_levels |= DP_PRE_EMPHASIS_0; |
||
2728 | break; |
||
2729 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2730 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
||
2731 | break; |
||
2732 | case DP_TRAIN_PRE_EMPHASIS_6: |
||
2733 | signal_levels |= DP_PRE_EMPHASIS_6; |
||
2734 | break; |
||
2735 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
||
2736 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
||
2737 | break; |
||
2738 | } |
||
2739 | return signal_levels; |
||
2740 | } |
||
2741 | |||
2742 | /* Gen6's DP voltage swing and pre-emphasis control */ |
||
2743 | static uint32_t |
||
2744 | intel_gen6_edp_signal_levels(uint8_t train_set) |
||
2745 | { |
||
2746 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
2747 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
2748 | switch (signal_levels) { |
||
2749 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2750 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2751 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
2752 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2753 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
||
2754 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
2755 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
2756 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
||
2757 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2758 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2759 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
||
2760 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2761 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2762 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
||
2763 | default: |
||
2764 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
2765 | "0x%x\n", signal_levels); |
||
2766 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
2767 | } |
||
2768 | } |
||
2769 | |||
2342 | Serge | 2770 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2771 | static uint32_t |
||
2772 | intel_gen7_edp_signal_levels(uint8_t train_set) |
||
2773 | { |
||
2774 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
2775 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
2776 | switch (signal_levels) { |
||
2777 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2778 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
||
2779 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2780 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
||
2781 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
2782 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
||
2783 | |||
2784 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2785 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
||
2786 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2787 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
||
2788 | |||
2789 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2790 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
||
2791 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2792 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
||
2793 | |||
2794 | default: |
||
2795 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
2796 | "0x%x\n", signal_levels); |
||
2797 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
||
2798 | } |
||
2799 | } |
||
2800 | |||
3243 | Serge | 2801 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2802 | static uint32_t |
||
3480 | Serge | 2803 | intel_hsw_signal_levels(uint8_t train_set) |
2330 | Serge | 2804 | { |
3243 | Serge | 2805 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2806 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
2807 | switch (signal_levels) { |
||
2808 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
2809 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
2810 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2811 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
||
2812 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
2813 | return DDI_BUF_EMP_400MV_6DB_HSW; |
||
2814 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
||
2815 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
||
2330 | Serge | 2816 | |
3243 | Serge | 2817 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2818 | return DDI_BUF_EMP_600MV_0DB_HSW; |
||
2819 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2820 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
||
2821 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
2822 | return DDI_BUF_EMP_600MV_6DB_HSW; |
||
2330 | Serge | 2823 | |
3243 | Serge | 2824 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2825 | return DDI_BUF_EMP_800MV_0DB_HSW; |
||
2826 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
2827 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
||
2828 | default: |
||
2829 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
2830 | "0x%x\n", signal_levels); |
||
2831 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
2330 | Serge | 2832 | } |
2833 | } |
||
2834 | |||
3480 | Serge | 2835 | /* Properly updates "DP" with the correct signal levels. */ |
2836 | static void |
||
2837 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
||
2838 | { |
||
2839 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
4104 | Serge | 2840 | enum port port = intel_dig_port->port; |
3480 | Serge | 2841 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2842 | uint32_t signal_levels, mask; |
||
2843 | uint8_t train_set = intel_dp->train_set[0]; |
||
2844 | |||
5060 | serge | 2845 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3480 | Serge | 2846 | signal_levels = intel_hsw_signal_levels(train_set); |
2847 | mask = DDI_BUF_EMP_MASK; |
||
5060 | serge | 2848 | } else if (IS_CHERRYVIEW(dev)) { |
2849 | signal_levels = intel_chv_signal_levels(intel_dp); |
||
2850 | mask = 0; |
||
4104 | Serge | 2851 | } else if (IS_VALLEYVIEW(dev)) { |
2852 | signal_levels = intel_vlv_signal_levels(intel_dp); |
||
2853 | mask = 0; |
||
2854 | } else if (IS_GEN7(dev) && port == PORT_A) { |
||
3480 | Serge | 2855 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2856 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
||
4104 | Serge | 2857 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3480 | Serge | 2858 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2859 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
||
2860 | } else { |
||
2861 | signal_levels = intel_gen4_signal_levels(train_set); |
||
2862 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
||
2863 | } |
||
2864 | |||
2865 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
||
2866 | |||
2867 | *DP = (*DP & ~mask) | signal_levels; |
||
2868 | } |
||
2869 | |||
2330 | Serge | 2870 | static bool |
2871 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
||
4560 | Serge | 2872 | uint32_t *DP, |
2330 | Serge | 2873 | uint8_t dp_train_pat) |
2874 | { |
||
3243 | Serge | 2875 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2876 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 2877 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 2878 | enum port port = intel_dig_port->port; |
4560 | Serge | 2879 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2880 | int ret, len; |
||
2330 | Serge | 2881 | |
3746 | Serge | 2882 | if (HAS_DDI(dev)) { |
2883 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
||
3243 | Serge | 2884 | |
2885 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
||
2886 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
||
2887 | else |
||
2888 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
||
2889 | |||
2890 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
2891 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
2892 | case DP_TRAINING_PATTERN_DISABLE: |
||
2893 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
||
2894 | |||
2895 | break; |
||
2896 | case DP_TRAINING_PATTERN_1: |
||
2897 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
||
2898 | break; |
||
2899 | case DP_TRAINING_PATTERN_2: |
||
2900 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
||
2901 | break; |
||
2902 | case DP_TRAINING_PATTERN_3: |
||
2903 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
||
2904 | break; |
||
2905 | } |
||
2906 | I915_WRITE(DP_TP_CTL(port), temp); |
||
2907 | |||
4104 | Serge | 2908 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
4560 | Serge | 2909 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3031 | serge | 2910 | |
2911 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
2912 | case DP_TRAINING_PATTERN_DISABLE: |
||
4560 | Serge | 2913 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
3031 | serge | 2914 | break; |
2915 | case DP_TRAINING_PATTERN_1: |
||
4560 | Serge | 2916 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
3031 | serge | 2917 | break; |
2918 | case DP_TRAINING_PATTERN_2: |
||
4560 | Serge | 2919 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
3031 | serge | 2920 | break; |
2921 | case DP_TRAINING_PATTERN_3: |
||
2922 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
4560 | Serge | 2923 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
3031 | serge | 2924 | break; |
2925 | } |
||
2926 | |||
2927 | } else { |
||
4560 | Serge | 2928 | *DP &= ~DP_LINK_TRAIN_MASK; |
3031 | serge | 2929 | |
2930 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
2931 | case DP_TRAINING_PATTERN_DISABLE: |
||
4560 | Serge | 2932 | *DP |= DP_LINK_TRAIN_OFF; |
3031 | serge | 2933 | break; |
2934 | case DP_TRAINING_PATTERN_1: |
||
4560 | Serge | 2935 | *DP |= DP_LINK_TRAIN_PAT_1; |
3031 | serge | 2936 | break; |
2937 | case DP_TRAINING_PATTERN_2: |
||
4560 | Serge | 2938 | *DP |= DP_LINK_TRAIN_PAT_2; |
3031 | serge | 2939 | break; |
2940 | case DP_TRAINING_PATTERN_3: |
||
2941 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
4560 | Serge | 2942 | *DP |= DP_LINK_TRAIN_PAT_2; |
3031 | serge | 2943 | break; |
2944 | } |
||
2945 | } |
||
2946 | |||
4560 | Serge | 2947 | I915_WRITE(intel_dp->output_reg, *DP); |
2330 | Serge | 2948 | POSTING_READ(intel_dp->output_reg); |
2949 | |||
4560 | Serge | 2950 | buf[0] = dp_train_pat; |
2951 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
||
2952 | DP_TRAINING_PATTERN_DISABLE) { |
||
2953 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
||
2954 | len = 1; |
||
2955 | } else { |
||
2956 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
||
2957 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
||
2958 | len = intel_dp->lane_count + 1; |
||
2959 | } |
||
2330 | Serge | 2960 | |
5060 | serge | 2961 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
4560 | Serge | 2962 | buf, len); |
2963 | |||
2964 | return ret == len; |
||
2965 | } |
||
2966 | |||
2967 | static bool |
||
2968 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
||
2969 | uint8_t dp_train_pat) |
||
2970 | { |
||
2971 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
||
2972 | intel_dp_set_signal_levels(intel_dp, DP); |
||
2973 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
||
2974 | } |
||
2975 | |||
2976 | static bool |
||
2977 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
||
2978 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
||
2979 | { |
||
2980 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
2981 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2982 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2983 | int ret; |
||
2984 | |||
2985 | intel_get_adjust_train(intel_dp, link_status); |
||
2986 | intel_dp_set_signal_levels(intel_dp, DP); |
||
2987 | |||
2988 | I915_WRITE(intel_dp->output_reg, *DP); |
||
2989 | POSTING_READ(intel_dp->output_reg); |
||
2990 | |||
5060 | serge | 2991 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2992 | intel_dp->train_set, intel_dp->lane_count); |
||
2330 | Serge | 2993 | |
4560 | Serge | 2994 | return ret == intel_dp->lane_count; |
2330 | Serge | 2995 | } |
2996 | |||
3746 | Serge | 2997 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2998 | { |
||
2999 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
3000 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
3001 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3002 | enum port port = intel_dig_port->port; |
||
3003 | uint32_t val; |
||
3004 | |||
3005 | if (!HAS_DDI(dev)) |
||
3006 | return; |
||
3007 | |||
3008 | val = I915_READ(DP_TP_CTL(port)); |
||
3009 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
3010 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
||
3011 | I915_WRITE(DP_TP_CTL(port), val); |
||
3012 | |||
3013 | /* |
||
3014 | * On PORT_A we can have only eDP in SST mode. There the only reason |
||
3015 | * we need to set idle transmission mode is to work around a HW issue |
||
3016 | * where we enable the pipe while not in idle link-training mode. |
||
3017 | * In this case there is requirement to wait for a minimum number of |
||
3018 | * idle patterns to be sent. |
||
3019 | */ |
||
3020 | if (port == PORT_A) |
||
3021 | return; |
||
3022 | |||
3023 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
||
3024 | 1)) |
||
3025 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
||
3026 | } |
||
3027 | |||
2330 | Serge | 3028 | /* Enable corresponding port and start training pattern 1 */ |
3243 | Serge | 3029 | void |
2330 | Serge | 3030 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
3031 | { |
||
3243 | Serge | 3032 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
3033 | struct drm_device *dev = encoder->dev; |
||
2330 | Serge | 3034 | int i; |
3035 | uint8_t voltage; |
||
2342 | Serge | 3036 | int voltage_tries, loop_tries; |
2330 | Serge | 3037 | uint32_t DP = intel_dp->DP; |
4560 | Serge | 3038 | uint8_t link_config[2]; |
2330 | Serge | 3039 | |
3480 | Serge | 3040 | if (HAS_DDI(dev)) |
3243 | Serge | 3041 | intel_ddi_prepare_link_retrain(encoder); |
3042 | |||
2330 | Serge | 3043 | /* Write the link configuration data */ |
4560 | Serge | 3044 | link_config[0] = intel_dp->link_bw; |
3045 | link_config[1] = intel_dp->lane_count; |
||
3046 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
||
3047 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
||
5060 | serge | 3048 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
2330 | Serge | 3049 | |
4560 | Serge | 3050 | link_config[0] = 0; |
3051 | link_config[1] = DP_SET_ANSI_8B10B; |
||
5060 | serge | 3052 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
4560 | Serge | 3053 | |
2330 | Serge | 3054 | DP |= DP_PORT_EN; |
2342 | Serge | 3055 | |
4560 | Serge | 3056 | /* clock recovery */ |
3057 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
||
3058 | DP_TRAINING_PATTERN_1 | |
||
3059 | DP_LINK_SCRAMBLING_DISABLE)) { |
||
3060 | DRM_ERROR("failed to enable link training\n"); |
||
3061 | return; |
||
3062 | } |
||
3063 | |||
2330 | Serge | 3064 | voltage = 0xff; |
2342 | Serge | 3065 | voltage_tries = 0; |
3066 | loop_tries = 0; |
||
2330 | Serge | 3067 | for (;;) { |
2342 | Serge | 3068 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3069 | |||
3243 | Serge | 3070 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
2342 | Serge | 3071 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3072 | DRM_ERROR("failed to get link status\n"); |
||
2330 | Serge | 3073 | break; |
2342 | Serge | 3074 | } |
2330 | Serge | 3075 | |
3243 | Serge | 3076 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2342 | Serge | 3077 | DRM_DEBUG_KMS("clock recovery OK\n"); |
2330 | Serge | 3078 | break; |
3079 | } |
||
3080 | |||
3081 | /* Check to see if we've tried the max voltage */ |
||
3082 | for (i = 0; i < intel_dp->lane_count; i++) |
||
3083 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
3084 | break; |
||
3480 | Serge | 3085 | if (i == intel_dp->lane_count) { |
2342 | Serge | 3086 | ++loop_tries; |
3087 | if (loop_tries == 5) { |
||
4560 | Serge | 3088 | DRM_ERROR("too many full retries, give up\n"); |
2330 | Serge | 3089 | break; |
2342 | Serge | 3090 | } |
4560 | Serge | 3091 | intel_dp_reset_link_train(intel_dp, &DP, |
3092 | DP_TRAINING_PATTERN_1 | |
||
3093 | DP_LINK_SCRAMBLING_DISABLE); |
||
2342 | Serge | 3094 | voltage_tries = 0; |
3095 | continue; |
||
3096 | } |
||
2330 | Serge | 3097 | |
3098 | /* Check to see if we've tried the same voltage 5 times */ |
||
3099 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
||
2342 | Serge | 3100 | ++voltage_tries; |
3101 | if (voltage_tries == 5) { |
||
4560 | Serge | 3102 | DRM_ERROR("too many voltage retries, give up\n"); |
2330 | Serge | 3103 | break; |
2342 | Serge | 3104 | } |
2330 | Serge | 3105 | } else |
2342 | Serge | 3106 | voltage_tries = 0; |
2330 | Serge | 3107 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
3108 | |||
4560 | Serge | 3109 | /* Update training set as requested by target */ |
3110 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
||
3111 | DRM_ERROR("failed to update link training\n"); |
||
3112 | break; |
||
3113 | } |
||
2330 | Serge | 3114 | } |
3115 | |||
3116 | intel_dp->DP = DP; |
||
3117 | } |
||
3118 | |||
3243 | Serge | 3119 | void |
2330 | Serge | 3120 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
3121 | { |
||
3122 | bool channel_eq = false; |
||
3123 | int tries, cr_tries; |
||
3124 | uint32_t DP = intel_dp->DP; |
||
5060 | serge | 3125 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
2330 | Serge | 3126 | |
5060 | serge | 3127 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
3128 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
||
3129 | training_pattern = DP_TRAINING_PATTERN_3; |
||
3130 | |||
2330 | Serge | 3131 | /* channel equalization */ |
4560 | Serge | 3132 | if (!intel_dp_set_link_train(intel_dp, &DP, |
5060 | serge | 3133 | training_pattern | |
4560 | Serge | 3134 | DP_LINK_SCRAMBLING_DISABLE)) { |
3135 | DRM_ERROR("failed to start channel equalization\n"); |
||
3136 | return; |
||
3137 | } |
||
3138 | |||
2330 | Serge | 3139 | tries = 0; |
3140 | cr_tries = 0; |
||
3141 | channel_eq = false; |
||
3142 | for (;;) { |
||
2342 | Serge | 3143 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2330 | Serge | 3144 | |
3145 | if (cr_tries > 5) { |
||
3146 | DRM_ERROR("failed to train DP, aborting\n"); |
||
3147 | break; |
||
3148 | } |
||
3149 | |||
3243 | Serge | 3150 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
4560 | Serge | 3151 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3152 | DRM_ERROR("failed to get link status\n"); |
||
2330 | Serge | 3153 | break; |
4560 | Serge | 3154 | } |
2330 | Serge | 3155 | |
3156 | /* Make sure clock is still ok */ |
||
3243 | Serge | 3157 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 3158 | intel_dp_start_link_train(intel_dp); |
4560 | Serge | 3159 | intel_dp_set_link_train(intel_dp, &DP, |
5060 | serge | 3160 | training_pattern | |
4560 | Serge | 3161 | DP_LINK_SCRAMBLING_DISABLE); |
2330 | Serge | 3162 | cr_tries++; |
3163 | continue; |
||
3164 | } |
||
3165 | |||
3243 | Serge | 3166 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 3167 | channel_eq = true; |
3168 | break; |
||
3169 | } |
||
3170 | |||
3171 | /* Try 5 times, then try clock recovery if that fails */ |
||
3172 | if (tries > 5) { |
||
3173 | intel_dp_link_down(intel_dp); |
||
3174 | intel_dp_start_link_train(intel_dp); |
||
4560 | Serge | 3175 | intel_dp_set_link_train(intel_dp, &DP, |
5060 | serge | 3176 | training_pattern | |
4560 | Serge | 3177 | DP_LINK_SCRAMBLING_DISABLE); |
2330 | Serge | 3178 | tries = 0; |
3179 | cr_tries++; |
||
3180 | continue; |
||
3181 | } |
||
3182 | |||
4560 | Serge | 3183 | /* Update training set as requested by target */ |
3184 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
||
3185 | DRM_ERROR("failed to update link training\n"); |
||
3186 | break; |
||
3187 | } |
||
2330 | Serge | 3188 | ++tries; |
3189 | } |
||
3190 | |||
3746 | Serge | 3191 | intel_dp_set_idle_link_train(intel_dp); |
3192 | |||
3193 | intel_dp->DP = DP; |
||
3194 | |||
3243 | Serge | 3195 | if (channel_eq) |
3746 | Serge | 3196 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
3243 | Serge | 3197 | |
2330 | Serge | 3198 | } |
3199 | |||
3746 | Serge | 3200 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
3201 | { |
||
4560 | Serge | 3202 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3746 | Serge | 3203 | DP_TRAINING_PATTERN_DISABLE); |
3204 | } |
||
3205 | |||
2330 | Serge | 3206 | static void |
3207 | intel_dp_link_down(struct intel_dp *intel_dp) |
||
3208 | { |
||
3243 | Serge | 3209 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4104 | Serge | 3210 | enum port port = intel_dig_port->port; |
3243 | Serge | 3211 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2330 | Serge | 3212 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 3213 | struct intel_crtc *intel_crtc = |
3214 | to_intel_crtc(intel_dig_port->base.base.crtc); |
||
2330 | Serge | 3215 | uint32_t DP = intel_dp->DP; |
3216 | |||
5060 | serge | 3217 | if (WARN_ON(HAS_DDI(dev))) |
3243 | Serge | 3218 | return; |
3219 | |||
3031 | serge | 3220 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2330 | Serge | 3221 | return; |
3222 | |||
3223 | DRM_DEBUG_KMS("\n"); |
||
3224 | |||
4104 | Serge | 3225 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
2330 | Serge | 3226 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3227 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
||
3228 | } else { |
||
3229 | DP &= ~DP_LINK_TRAIN_MASK; |
||
3230 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
||
3231 | } |
||
3232 | POSTING_READ(intel_dp->output_reg); |
||
3233 | |||
3031 | serge | 3234 | if (HAS_PCH_IBX(dev) && |
2330 | Serge | 3235 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
3243 | Serge | 3236 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2330 | Serge | 3237 | |
3238 | /* Hardware workaround: leaving our transcoder select |
||
3239 | * set to transcoder B while it's off will prevent the |
||
3240 | * corresponding HDMI output on transcoder A. |
||
3241 | * |
||
3242 | * Combine this with another hardware workaround: |
||
3243 | * transcoder select bit can only be cleared while the |
||
3244 | * port is enabled. |
||
3245 | */ |
||
3246 | DP &= ~DP_PIPEB_SELECT; |
||
3247 | I915_WRITE(intel_dp->output_reg, DP); |
||
3248 | |||
3249 | /* Changes to enable or select take place the vblank |
||
3250 | * after being written. |
||
3251 | */ |
||
3480 | Serge | 3252 | if (WARN_ON(crtc == NULL)) { |
3253 | /* We should never try to disable a port without a crtc |
||
3254 | * attached. For paranoia keep the code around for a |
||
3255 | * bit. */ |
||
2330 | Serge | 3256 | POSTING_READ(intel_dp->output_reg); |
3257 | msleep(50); |
||
3258 | } else |
||
3480 | Serge | 3259 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2330 | Serge | 3260 | } |
3261 | |||
2342 | Serge | 3262 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
2330 | Serge | 3263 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
3264 | POSTING_READ(intel_dp->output_reg); |
||
2342 | Serge | 3265 | msleep(intel_dp->panel_power_down_delay); |
2330 | Serge | 3266 | } |
3267 | |||
3268 | static bool |
||
3269 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
||
3270 | { |
||
4560 | Serge | 3271 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3272 | struct drm_device *dev = dig_port->base.base.dev; |
||
3273 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3274 | |||
3480 | Serge | 3275 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
3276 | |||
5060 | serge | 3277 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3278 | sizeof(intel_dp->dpcd)) < 0) |
||
3031 | serge | 3279 | return false; /* aux transfer failed */ |
3280 | |||
3480 | Serge | 3281 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
3282 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
||
3283 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
||
3284 | |||
3031 | serge | 3285 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3286 | return false; /* DPCD not present */ |
||
3287 | |||
4104 | Serge | 3288 | /* Check if the panel supports PSR */ |
3289 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
||
4560 | Serge | 3290 | if (is_edp(intel_dp)) { |
5060 | serge | 3291 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
4104 | Serge | 3292 | intel_dp->psr_dpcd, |
3293 | sizeof(intel_dp->psr_dpcd)); |
||
4560 | Serge | 3294 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3295 | dev_priv->psr.sink_support = true; |
||
4104 | Serge | 3296 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
4560 | Serge | 3297 | } |
3298 | } |
||
3299 | |||
5060 | serge | 3300 | /* Training Pattern 3 support */ |
3301 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
||
3302 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
||
3303 | intel_dp->use_tps3 = true; |
||
3304 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
||
3305 | } else |
||
3306 | intel_dp->use_tps3 = false; |
||
3307 | |||
3031 | serge | 3308 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3309 | DP_DWN_STRM_PORT_PRESENT)) |
||
3310 | return true; /* native DP sink */ |
||
3311 | |||
3312 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
||
3313 | return true; /* no per-port downstream info */ |
||
3314 | |||
5060 | serge | 3315 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3031 | serge | 3316 | intel_dp->downstream_ports, |
5060 | serge | 3317 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
3031 | serge | 3318 | return false; /* downstream port status fetch failed */ |
3319 | |||
2330 | Serge | 3320 | return true; |
3031 | serge | 3321 | } |
2330 | Serge | 3322 | |
3031 | serge | 3323 | static void |
3324 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
||
3325 | { |
||
3326 | u8 buf[3]; |
||
3327 | |||
3328 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
||
3329 | return; |
||
3330 | |||
5060 | serge | 3331 | intel_edp_panel_vdd_on(intel_dp); |
3031 | serge | 3332 | |
5060 | serge | 3333 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
3031 | serge | 3334 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3335 | buf[0], buf[1], buf[2]); |
||
3336 | |||
5060 | serge | 3337 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
3031 | serge | 3338 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3339 | buf[0], buf[1], buf[2]); |
||
3340 | |||
5060 | serge | 3341 | edp_panel_vdd_off(intel_dp, false); |
2330 | Serge | 3342 | } |
3343 | |||
2342 | Serge | 3344 | static bool |
5060 | serge | 3345 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
3346 | { |
||
3347 | u8 buf[1]; |
||
3348 | |||
3349 | if (!intel_dp->can_mst) |
||
3350 | return false; |
||
3351 | |||
3352 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
||
3353 | return false; |
||
3354 | |||
3355 | _edp_panel_vdd_on(intel_dp); |
||
3356 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
||
3357 | if (buf[0] & DP_MST_CAP) { |
||
3358 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
||
3359 | intel_dp->is_mst = true; |
||
3360 | } else { |
||
3361 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
||
3362 | intel_dp->is_mst = false; |
||
3363 | } |
||
3364 | } |
||
3365 | edp_panel_vdd_off(intel_dp, false); |
||
3366 | |||
3367 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
||
3368 | return intel_dp->is_mst; |
||
3369 | } |
||
3370 | |||
3371 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
||
3372 | { |
||
3373 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
3374 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
3375 | struct intel_crtc *intel_crtc = |
||
3376 | to_intel_crtc(intel_dig_port->base.base.crtc); |
||
3377 | u8 buf[1]; |
||
3378 | |||
3379 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
||
3380 | return -EAGAIN; |
||
3381 | |||
3382 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
||
3383 | return -ENOTTY; |
||
3384 | |||
3385 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
||
3386 | DP_TEST_SINK_START) < 0) |
||
3387 | return -EAGAIN; |
||
3388 | |||
3389 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
||
3390 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
3391 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
3392 | |||
3393 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
||
3394 | return -EAGAIN; |
||
3395 | |||
3396 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
||
3397 | return 0; |
||
3398 | } |
||
3399 | |||
3400 | static bool |
||
2342 | Serge | 3401 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
3402 | { |
||
5060 | serge | 3403 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3404 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
||
3405 | sink_irq_vector, 1) == 1; |
||
3406 | } |
||
3407 | |||
3408 | static bool |
||
3409 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
||
3410 | { |
||
2342 | Serge | 3411 | int ret; |
3412 | |||
5060 | serge | 3413 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
3414 | DP_SINK_COUNT_ESI, |
||
3415 | sink_irq_vector, 14); |
||
3416 | if (ret != 14) |
||
2342 | Serge | 3417 | return false; |
3418 | |||
3419 | return true; |
||
3420 | } |
||
3421 | |||
3422 | static void |
||
3423 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
||
3424 | { |
||
3425 | /* NAK by default */ |
||
5060 | serge | 3426 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
2342 | Serge | 3427 | } |
3428 | |||
5060 | serge | 3429 | static int |
3430 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
||
3431 | { |
||
3432 | bool bret; |
||
3433 | |||
3434 | if (intel_dp->is_mst) { |
||
3435 | u8 esi[16] = { 0 }; |
||
3436 | int ret = 0; |
||
3437 | int retry; |
||
3438 | bool handled; |
||
3439 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
||
3440 | go_again: |
||
3441 | if (bret == true) { |
||
3442 | |||
3443 | /* check link status - esi[10] = 0x200c */ |
||
3444 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
||
3445 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
||
3446 | intel_dp_start_link_train(intel_dp); |
||
3447 | intel_dp_complete_link_train(intel_dp); |
||
3448 | intel_dp_stop_link_train(intel_dp); |
||
3449 | } |
||
3450 | |||
3451 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
3452 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
||
3453 | |||
3454 | if (handled) { |
||
3455 | for (retry = 0; retry < 3; retry++) { |
||
3456 | int wret; |
||
3457 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
||
3458 | DP_SINK_COUNT_ESI+1, |
||
3459 | &esi[1], 3); |
||
3460 | if (wret == 3) { |
||
3461 | break; |
||
3462 | } |
||
3463 | } |
||
3464 | |||
3465 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
||
3466 | if (bret == true) { |
||
3467 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
3468 | goto go_again; |
||
3469 | } |
||
3470 | } else |
||
3471 | ret = 0; |
||
3472 | |||
3473 | return ret; |
||
3474 | } else { |
||
3475 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
3476 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
||
3477 | intel_dp->is_mst = false; |
||
3478 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
||
3479 | /* send a hotplug event */ |
||
3480 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
||
3481 | } |
||
3482 | } |
||
3483 | return -EINVAL; |
||
3484 | } |
||
3485 | |||
2330 | Serge | 3486 | /* |
3487 | * According to DP spec |
||
3488 | * 5.1.2: |
||
3489 | * 1. Read DPCD |
||
3490 | * 2. Configure link according to Receiver Capabilities |
||
3491 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
||
3492 | * 4. Check link status on receipt of hot-plug interrupt |
||
3493 | */ |
||
3243 | Serge | 3494 | void |
2330 | Serge | 3495 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
3496 | { |
||
5060 | serge | 3497 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3243 | Serge | 3498 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
2342 | Serge | 3499 | u8 sink_irq_vector; |
3500 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
3501 | |||
5060 | serge | 3502 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
3503 | |||
3243 | Serge | 3504 | if (!intel_encoder->connectors_active) |
2330 | Serge | 3505 | return; |
3506 | |||
3243 | Serge | 3507 | if (WARN_ON(!intel_encoder->base.crtc)) |
2330 | Serge | 3508 | return; |
3509 | |||
5060 | serge | 3510 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
3511 | return; |
||
3512 | |||
2330 | Serge | 3513 | /* Try to read receiver status if the link appears to be up */ |
2342 | Serge | 3514 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2330 | Serge | 3515 | return; |
3516 | } |
||
3517 | |||
3518 | /* Now read the DPCD to see if it's actually running */ |
||
3519 | if (!intel_dp_get_dpcd(intel_dp)) { |
||
3520 | return; |
||
3521 | } |
||
3522 | |||
2342 | Serge | 3523 | /* Try to read the source of the interrupt */ |
3524 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
||
3525 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
||
3526 | /* Clear interrupt source */ |
||
5060 | serge | 3527 | drm_dp_dpcd_writeb(&intel_dp->aux, |
2342 | Serge | 3528 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3529 | sink_irq_vector); |
||
3530 | |||
3531 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
||
3532 | intel_dp_handle_test_request(intel_dp); |
||
3533 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
||
3534 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
||
3535 | } |
||
3536 | |||
3243 | Serge | 3537 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 3538 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
5060 | serge | 3539 | intel_encoder->base.name); |
2330 | Serge | 3540 | intel_dp_start_link_train(intel_dp); |
3541 | intel_dp_complete_link_train(intel_dp); |
||
3746 | Serge | 3542 | intel_dp_stop_link_train(intel_dp); |
2330 | Serge | 3543 | } |
3544 | } |
||
3545 | |||
3031 | serge | 3546 | /* XXX this is probably wrong for multiple downstream ports */ |
2330 | Serge | 3547 | static enum drm_connector_status |
3548 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
||
3549 | { |
||
3031 | serge | 3550 | uint8_t *dpcd = intel_dp->dpcd; |
3551 | uint8_t type; |
||
3552 | |||
3553 | if (!intel_dp_get_dpcd(intel_dp)) |
||
3554 | return connector_status_disconnected; |
||
3555 | |||
3556 | /* if there's no downstream port, we're done */ |
||
3557 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
||
2330 | Serge | 3558 | return connector_status_connected; |
3031 | serge | 3559 | |
3560 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
||
4560 | Serge | 3561 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3562 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
||
3031 | serge | 3563 | uint8_t reg; |
5060 | serge | 3564 | |
3565 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
||
3566 | ®, 1) < 0) |
||
3031 | serge | 3567 | return connector_status_unknown; |
5060 | serge | 3568 | |
3031 | serge | 3569 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3570 | : connector_status_disconnected; |
||
3571 | } |
||
3572 | |||
3573 | /* If no HPD, poke DDC gently */ |
||
5060 | serge | 3574 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
3031 | serge | 3575 | return connector_status_connected; |
3576 | |||
3577 | /* Well we tried, say unknown for unreliable port types */ |
||
4560 | Serge | 3578 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3031 | serge | 3579 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4560 | Serge | 3580 | if (type == DP_DS_PORT_TYPE_VGA || |
3581 | type == DP_DS_PORT_TYPE_NON_EDID) |
||
3031 | serge | 3582 | return connector_status_unknown; |
4560 | Serge | 3583 | } else { |
3584 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
||
3585 | DP_DWN_STRM_PORT_TYPE_MASK; |
||
3586 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
||
3587 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
||
5060 | serge | 3588 | return connector_status_unknown; |
4560 | Serge | 3589 | } |
3031 | serge | 3590 | |
3591 | /* Anything else is out of spec, warn and ignore */ |
||
3592 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
||
2330 | Serge | 3593 | return connector_status_disconnected; |
3594 | } |
||
3595 | |||
3596 | static enum drm_connector_status |
||
3597 | ironlake_dp_detect(struct intel_dp *intel_dp) |
||
3598 | { |
||
3243 | Serge | 3599 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3480 | Serge | 3600 | struct drm_i915_private *dev_priv = dev->dev_private; |
3601 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
2330 | Serge | 3602 | enum drm_connector_status status; |
3603 | |||
3604 | /* Can't disconnect eDP, but you can close the lid... */ |
||
3605 | if (is_edp(intel_dp)) { |
||
3243 | Serge | 3606 | status = intel_panel_detect(dev); |
2330 | Serge | 3607 | if (status == connector_status_unknown) |
3608 | status = connector_status_connected; |
||
3609 | return status; |
||
3610 | } |
||
3611 | |||
3480 | Serge | 3612 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3613 | return connector_status_disconnected; |
||
3614 | |||
2330 | Serge | 3615 | return intel_dp_detect_dpcd(intel_dp); |
3616 | } |
||
3617 | |||
5097 | serge | 3618 | static int g4x_digital_port_connected(struct drm_device *dev, |
3619 | struct intel_digital_port *intel_dig_port) |
||
2330 | Serge | 3620 | { |
3621 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3031 | serge | 3622 | uint32_t bit; |
2330 | Serge | 3623 | |
4560 | Serge | 3624 | if (IS_VALLEYVIEW(dev)) { |
3625 | switch (intel_dig_port->port) { |
||
3626 | case PORT_B: |
||
3627 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
||
3628 | break; |
||
3629 | case PORT_C: |
||
3630 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
||
3631 | break; |
||
3632 | case PORT_D: |
||
3633 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
||
3634 | break; |
||
3635 | default: |
||
5097 | serge | 3636 | return -EINVAL; |
4560 | Serge | 3637 | } |
3638 | } else { |
||
3480 | Serge | 3639 | switch (intel_dig_port->port) { |
3640 | case PORT_B: |
||
4560 | Serge | 3641 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
2330 | Serge | 3642 | break; |
3480 | Serge | 3643 | case PORT_C: |
4560 | Serge | 3644 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
2330 | Serge | 3645 | break; |
3480 | Serge | 3646 | case PORT_D: |
4560 | Serge | 3647 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
2330 | Serge | 3648 | break; |
3649 | default: |
||
5097 | serge | 3650 | return -EINVAL; |
2330 | Serge | 3651 | } |
4560 | Serge | 3652 | } |
2330 | Serge | 3653 | |
3031 | serge | 3654 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
5097 | serge | 3655 | return 0; |
3656 | return 1; |
||
3657 | } |
||
3658 | |||
3659 | static enum drm_connector_status |
||
3660 | g4x_dp_detect(struct intel_dp *intel_dp) |
||
3661 | { |
||
3662 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
3663 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
3664 | int ret; |
||
3665 | |||
3666 | /* Can't disconnect eDP, but you can close the lid... */ |
||
3667 | if (is_edp(intel_dp)) { |
||
3668 | enum drm_connector_status status; |
||
3669 | |||
3670 | status = intel_panel_detect(dev); |
||
3671 | if (status == connector_status_unknown) |
||
3672 | status = connector_status_connected; |
||
3673 | return status; |
||
3674 | } |
||
3675 | |||
3676 | ret = g4x_digital_port_connected(dev, intel_dig_port); |
||
3677 | if (ret == -EINVAL) |
||
3678 | return connector_status_unknown; |
||
3679 | else if (ret == 0) |
||
2330 | Serge | 3680 | return connector_status_disconnected; |
3681 | |||
3682 | return intel_dp_detect_dpcd(intel_dp); |
||
3683 | } |
||
3684 | |||
2342 | Serge | 3685 | static struct edid * |
3686 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
3687 | { |
||
3243 | Serge | 3688 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3689 | |||
3690 | /* use cached edid if we have one */ |
||
3691 | if (intel_connector->edid) { |
||
3692 | /* invalid edid */ |
||
3693 | if (IS_ERR(intel_connector->edid)) |
||
3031 | serge | 3694 | return NULL; |
3695 | |||
4560 | Serge | 3696 | return drm_edid_duplicate(intel_connector->edid); |
3031 | serge | 3697 | } |
3698 | |||
3243 | Serge | 3699 | return drm_get_edid(connector, adapter); |
2342 | Serge | 3700 | } |
3701 | |||
3702 | static int |
||
3703 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
3704 | { |
||
3243 | Serge | 3705 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2342 | Serge | 3706 | |
3243 | Serge | 3707 | /* use cached edid if we have one */ |
3708 | if (intel_connector->edid) { |
||
3709 | /* invalid edid */ |
||
3710 | if (IS_ERR(intel_connector->edid)) |
||
3711 | return 0; |
||
3712 | |||
3713 | return intel_connector_update_modes(connector, |
||
3714 | intel_connector->edid); |
||
3031 | serge | 3715 | } |
3716 | |||
3243 | Serge | 3717 | return intel_ddc_get_modes(connector, adapter); |
2342 | Serge | 3718 | } |
3719 | |||
2330 | Serge | 3720 | static enum drm_connector_status |
3721 | intel_dp_detect(struct drm_connector *connector, bool force) |
||
3722 | { |
||
3723 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
3243 | Serge | 3724 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3725 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3726 | struct drm_device *dev = connector->dev; |
||
4560 | Serge | 3727 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 3728 | enum drm_connector_status status; |
5060 | serge | 3729 | enum intel_display_power_domain power_domain; |
2330 | Serge | 3730 | struct edid *edid = NULL; |
5060 | serge | 3731 | bool ret; |
2330 | Serge | 3732 | |
5060 | serge | 3733 | power_domain = intel_display_port_power_domain(intel_encoder); |
3734 | intel_display_power_get(dev_priv, power_domain); |
||
4560 | Serge | 3735 | |
4104 | Serge | 3736 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5060 | serge | 3737 | connector->base.id, connector->name); |
4104 | Serge | 3738 | |
5060 | serge | 3739 | if (intel_dp->is_mst) { |
3740 | /* MST devices are disconnected from a monitor POV */ |
||
3741 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
3742 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
3743 | status = connector_status_disconnected; |
||
3744 | goto out; |
||
3745 | } |
||
3746 | |||
2330 | Serge | 3747 | intel_dp->has_audio = false; |
3748 | |||
3749 | if (HAS_PCH_SPLIT(dev)) |
||
3750 | status = ironlake_dp_detect(intel_dp); |
||
3751 | else |
||
3752 | status = g4x_dp_detect(intel_dp); |
||
3753 | |||
3754 | if (status != connector_status_connected) |
||
4560 | Serge | 3755 | goto out; |
3031 | serge | 3756 | |
3757 | intel_dp_probe_oui(intel_dp); |
||
3758 | |||
5060 | serge | 3759 | ret = intel_dp_probe_mst(intel_dp); |
3760 | if (ret) { |
||
3761 | /* if we are in MST mode then this connector |
||
3762 | won't appear connected or have anything with EDID on it */ |
||
3763 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
3764 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
3765 | status = connector_status_disconnected; |
||
3766 | goto out; |
||
3767 | } |
||
3768 | |||
3243 | Serge | 3769 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3770 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
||
2330 | Serge | 3771 | } else { |
5060 | serge | 3772 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
2330 | Serge | 3773 | if (edid) { |
3774 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
||
3775 | kfree(edid); |
||
3776 | } |
||
3777 | } |
||
3243 | Serge | 3778 | |
3779 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
3780 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
4560 | Serge | 3781 | status = connector_status_connected; |
3782 | |||
3783 | out: |
||
5060 | serge | 3784 | intel_display_power_put(dev_priv, power_domain); |
4560 | Serge | 3785 | return status; |
2330 | Serge | 3786 | } |
3787 | |||
3788 | static int intel_dp_get_modes(struct drm_connector *connector) |
||
3789 | { |
||
3790 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
5060 | serge | 3791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3792 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3243 | Serge | 3793 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3794 | struct drm_device *dev = connector->dev; |
||
5060 | serge | 3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
3796 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 3797 | int ret; |
3798 | |||
3799 | /* We should parse the EDID data and find out if it has an audio sink |
||
3800 | */ |
||
3801 | |||
5060 | serge | 3802 | power_domain = intel_display_port_power_domain(intel_encoder); |
3803 | intel_display_power_get(dev_priv, power_domain); |
||
3804 | |||
3805 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
||
3806 | intel_display_power_put(dev_priv, power_domain); |
||
3243 | Serge | 3807 | if (ret) |
2330 | Serge | 3808 | return ret; |
3809 | |||
3243 | Serge | 3810 | /* if eDP has no EDID, fall back to fixed mode */ |
3811 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
||
2330 | Serge | 3812 | struct drm_display_mode *mode; |
3243 | Serge | 3813 | mode = drm_mode_duplicate(dev, |
3814 | intel_connector->panel.fixed_mode); |
||
3815 | if (mode) { |
||
2330 | Serge | 3816 | drm_mode_probed_add(connector, mode); |
3817 | return 1; |
||
3818 | } |
||
3819 | } |
||
3820 | return 0; |
||
3821 | } |
||
3822 | |||
3243 | Serge | 3823 | static bool |
3824 | intel_dp_detect_audio(struct drm_connector *connector) |
||
3825 | { |
||
3826 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
5060 | serge | 3827 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3828 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
3829 | struct drm_device *dev = connector->dev; |
||
3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3831 | enum intel_display_power_domain power_domain; |
||
3243 | Serge | 3832 | struct edid *edid; |
3833 | bool has_audio = false; |
||
2330 | Serge | 3834 | |
5060 | serge | 3835 | power_domain = intel_display_port_power_domain(intel_encoder); |
3836 | intel_display_power_get(dev_priv, power_domain); |
||
3837 | |||
3838 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
||
3243 | Serge | 3839 | if (edid) { |
3840 | has_audio = drm_detect_monitor_audio(edid); |
||
3841 | kfree(edid); |
||
3842 | } |
||
2330 | Serge | 3843 | |
5060 | serge | 3844 | intel_display_power_put(dev_priv, power_domain); |
3845 | |||
3243 | Serge | 3846 | return has_audio; |
3847 | } |
||
2330 | Serge | 3848 | |
3849 | static int |
||
3850 | intel_dp_set_property(struct drm_connector *connector, |
||
3851 | struct drm_property *property, |
||
3852 | uint64_t val) |
||
3853 | { |
||
3854 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
3243 | Serge | 3855 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3856 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
||
3857 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2330 | Serge | 3858 | int ret; |
3859 | |||
3243 | Serge | 3860 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 3861 | if (ret) |
3862 | return ret; |
||
3480 | Serge | 3863 | |
2330 | Serge | 3864 | if (property == dev_priv->force_audio_property) { |
3865 | int i = val; |
||
3866 | bool has_audio; |
||
3867 | |||
3868 | if (i == intel_dp->force_audio) |
||
3869 | return 0; |
||
3870 | |||
3871 | intel_dp->force_audio = i; |
||
3872 | |||
3031 | serge | 3873 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 3874 | has_audio = intel_dp_detect_audio(connector); |
3875 | else |
||
3031 | serge | 3876 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 3877 | |
3878 | if (has_audio == intel_dp->has_audio) |
||
3879 | return 0; |
||
3880 | |||
3881 | intel_dp->has_audio = has_audio; |
||
3882 | goto done; |
||
3883 | } |
||
3884 | |||
3885 | if (property == dev_priv->broadcast_rgb_property) { |
||
3746 | Serge | 3886 | bool old_auto = intel_dp->color_range_auto; |
3887 | uint32_t old_range = intel_dp->color_range; |
||
3888 | |||
3480 | Serge | 3889 | switch (val) { |
3890 | case INTEL_BROADCAST_RGB_AUTO: |
||
3891 | intel_dp->color_range_auto = true; |
||
3892 | break; |
||
3893 | case INTEL_BROADCAST_RGB_FULL: |
||
3894 | intel_dp->color_range_auto = false; |
||
3895 | intel_dp->color_range = 0; |
||
3896 | break; |
||
3897 | case INTEL_BROADCAST_RGB_LIMITED: |
||
3898 | intel_dp->color_range_auto = false; |
||
3899 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
||
3900 | break; |
||
3901 | default: |
||
3902 | return -EINVAL; |
||
3903 | } |
||
3746 | Serge | 3904 | |
3905 | if (old_auto == intel_dp->color_range_auto && |
||
3906 | old_range == intel_dp->color_range) |
||
3907 | return 0; |
||
3908 | |||
2330 | Serge | 3909 | goto done; |
3910 | } |
||
3911 | |||
3243 | Serge | 3912 | if (is_edp(intel_dp) && |
3913 | property == connector->dev->mode_config.scaling_mode_property) { |
||
3914 | if (val == DRM_MODE_SCALE_NONE) { |
||
3915 | DRM_DEBUG_KMS("no scaling not supported\n"); |
||
3916 | return -EINVAL; |
||
3917 | } |
||
3918 | |||
3919 | if (intel_connector->panel.fitting_mode == val) { |
||
3920 | /* the eDP scaling property is not changed */ |
||
3921 | return 0; |
||
3922 | } |
||
3923 | intel_connector->panel.fitting_mode = val; |
||
3924 | |||
3925 | goto done; |
||
3926 | } |
||
3927 | |||
2330 | Serge | 3928 | return -EINVAL; |
3929 | |||
3930 | done: |
||
3480 | Serge | 3931 | if (intel_encoder->base.crtc) |
3932 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
||
2330 | Serge | 3933 | |
3934 | return 0; |
||
3935 | } |
||
3936 | |||
3937 | static void |
||
4104 | Serge | 3938 | intel_dp_connector_destroy(struct drm_connector *connector) |
2330 | Serge | 3939 | { |
3243 | Serge | 3940 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2330 | Serge | 3941 | |
3243 | Serge | 3942 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3943 | kfree(intel_connector->edid); |
||
3944 | |||
4104 | Serge | 3945 | /* Can't call is_edp() since the encoder may have been destroyed |
3946 | * already. */ |
||
3947 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
||
3243 | Serge | 3948 | intel_panel_fini(&intel_connector->panel); |
2330 | Serge | 3949 | |
3950 | drm_connector_cleanup(connector); |
||
3951 | kfree(connector); |
||
3952 | } |
||
3953 | |||
3243 | Serge | 3954 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2330 | Serge | 3955 | { |
3243 | Serge | 3956 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3957 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
3480 | Serge | 3958 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 3959 | |
5060 | serge | 3960 | drm_dp_aux_unregister(&intel_dp->aux); |
3961 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
||
2330 | Serge | 3962 | drm_encoder_cleanup(encoder); |
2342 | Serge | 3963 | if (is_edp(intel_dp)) { |
4293 | Serge | 3964 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5060 | serge | 3965 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3966 | edp_panel_vdd_off_sync(intel_dp); |
||
3967 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
||
2342 | Serge | 3968 | } |
3243 | Serge | 3969 | kfree(intel_dig_port); |
2330 | Serge | 3970 | } |
3971 | |||
5060 | serge | 3972 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
3973 | { |
||
3974 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
3975 | |||
3976 | if (!is_edp(intel_dp)) |
||
3977 | return; |
||
3978 | |||
3979 | edp_panel_vdd_off_sync(intel_dp); |
||
3980 | } |
||
3981 | |||
3982 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
||
3983 | { |
||
3984 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
||
3985 | } |
||
3986 | |||
2330 | Serge | 3987 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3031 | serge | 3988 | .dpms = intel_connector_dpms, |
2330 | Serge | 3989 | .detect = intel_dp_detect, |
3990 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
3991 | .set_property = intel_dp_set_property, |
||
4104 | Serge | 3992 | .destroy = intel_dp_connector_destroy, |
2330 | Serge | 3993 | }; |
3994 | |||
3995 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
||
3996 | .get_modes = intel_dp_get_modes, |
||
3997 | .mode_valid = intel_dp_mode_valid, |
||
3998 | .best_encoder = intel_best_encoder, |
||
3999 | }; |
||
4000 | |||
4001 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
||
5060 | serge | 4002 | .reset = intel_dp_encoder_reset, |
2330 | Serge | 4003 | .destroy = intel_dp_encoder_destroy, |
4004 | }; |
||
4005 | |||
5060 | serge | 4006 | void |
2330 | Serge | 4007 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
4008 | { |
||
5060 | serge | 4009 | return; |
4010 | } |
||
2330 | Serge | 4011 | |
5060 | serge | 4012 | bool |
4013 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
||
4014 | { |
||
4015 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
4016 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
4017 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
4018 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4019 | enum intel_display_power_domain power_domain; |
||
4020 | bool ret = true; |
||
4021 | |||
4022 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
||
4023 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
||
4024 | |||
4025 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
||
4026 | long_hpd ? "long" : "short"); |
||
4027 | |||
4028 | power_domain = intel_display_port_power_domain(intel_encoder); |
||
4029 | intel_display_power_get(dev_priv, power_domain); |
||
4030 | |||
4031 | if (long_hpd) { |
||
5097 | serge | 4032 | |
4033 | if (HAS_PCH_SPLIT(dev)) { |
||
5060 | serge | 4034 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
4035 | goto mst_fail; |
||
5097 | serge | 4036 | } else { |
4037 | if (g4x_digital_port_connected(dev, intel_dig_port) != 1) |
||
4038 | goto mst_fail; |
||
4039 | } |
||
5060 | serge | 4040 | |
4041 | if (!intel_dp_get_dpcd(intel_dp)) { |
||
4042 | goto mst_fail; |
||
4043 | } |
||
4044 | |||
4045 | intel_dp_probe_oui(intel_dp); |
||
4046 | |||
4047 | if (!intel_dp_probe_mst(intel_dp)) |
||
4048 | goto mst_fail; |
||
4049 | |||
4050 | } else { |
||
4051 | if (intel_dp->is_mst) { |
||
4052 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
||
4053 | goto mst_fail; |
||
4054 | } |
||
4055 | |||
4056 | if (!intel_dp->is_mst) { |
||
4057 | /* |
||
4058 | * we'll check the link status via the normal hot plug path later - |
||
4059 | * but for short hpds we should check it now |
||
4060 | */ |
||
4061 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
||
4062 | intel_dp_check_link_status(intel_dp); |
||
4063 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
||
4064 | } |
||
4065 | } |
||
4066 | ret = false; |
||
4067 | goto put_power; |
||
4068 | mst_fail: |
||
4069 | /* if we were in MST mode, and device is not there get out of MST mode */ |
||
4070 | if (intel_dp->is_mst) { |
||
4071 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
||
4072 | intel_dp->is_mst = false; |
||
4073 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
||
4074 | } |
||
4075 | put_power: |
||
4076 | intel_display_power_put(dev_priv, power_domain); |
||
4077 | |||
4078 | return ret; |
||
2330 | Serge | 4079 | } |
4080 | |||
2327 | Serge | 4081 | /* Return which DP Port should be selected for Transcoder DP control */ |
4082 | int |
||
2342 | Serge | 4083 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
2327 | Serge | 4084 | { |
4085 | struct drm_device *dev = crtc->dev; |
||
3243 | Serge | 4086 | struct intel_encoder *intel_encoder; |
4087 | struct intel_dp *intel_dp; |
||
2327 | Serge | 4088 | |
3243 | Serge | 4089 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4090 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2327 | Serge | 4091 | |
3243 | Serge | 4092 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
4093 | intel_encoder->type == INTEL_OUTPUT_EDP) |
||
2327 | Serge | 4094 | return intel_dp->output_reg; |
4095 | } |
||
4096 | |||
4097 | return -1; |
||
4098 | } |
||
2330 | Serge | 4099 | |
4100 | /* check the VBT to see whether the eDP is on DP-D port */ |
||
4560 | Serge | 4101 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
2330 | Serge | 4102 | { |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4560 | Serge | 4104 | union child_device_config *p_child; |
2330 | Serge | 4105 | int i; |
4560 | Serge | 4106 | static const short port_mapping[] = { |
4107 | [PORT_B] = PORT_IDPB, |
||
4108 | [PORT_C] = PORT_IDPC, |
||
4109 | [PORT_D] = PORT_IDPD, |
||
4110 | }; |
||
2330 | Serge | 4111 | |
4560 | Serge | 4112 | if (port == PORT_A) |
4113 | return true; |
||
4114 | |||
4104 | Serge | 4115 | if (!dev_priv->vbt.child_dev_num) |
2330 | Serge | 4116 | return false; |
4117 | |||
4104 | Serge | 4118 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
4119 | p_child = dev_priv->vbt.child_dev + i; |
||
2330 | Serge | 4120 | |
4560 | Serge | 4121 | if (p_child->common.dvo_port == port_mapping[port] && |
4122 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
||
4123 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
||
2330 | Serge | 4124 | return true; |
4125 | } |
||
4126 | return false; |
||
4127 | } |
||
4128 | |||
5060 | serge | 4129 | void |
2330 | Serge | 4130 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4131 | { |
||
3243 | Serge | 4132 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4133 | |||
2330 | Serge | 4134 | intel_attach_force_audio_property(connector); |
4135 | intel_attach_broadcast_rgb_property(connector); |
||
3480 | Serge | 4136 | intel_dp->color_range_auto = true; |
3243 | Serge | 4137 | |
4138 | if (is_edp(intel_dp)) { |
||
4139 | drm_mode_create_scaling_mode_property(connector->dev); |
||
4140 | drm_object_attach_property( |
||
4141 | &connector->base, |
||
4142 | connector->dev->mode_config.scaling_mode_property, |
||
4143 | DRM_MODE_SCALE_ASPECT); |
||
4144 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
||
4145 | } |
||
2330 | Serge | 4146 | } |
4147 | |||
5060 | serge | 4148 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4149 | { |
||
4150 | intel_dp->last_power_cycle = jiffies; |
||
4151 | intel_dp->last_power_on = jiffies; |
||
4152 | intel_dp->last_backlight_off = jiffies; |
||
4153 | } |
||
4154 | |||
3243 | Serge | 4155 | static void |
4156 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
||
4157 | struct intel_dp *intel_dp, |
||
4158 | struct edp_power_seq *out) |
||
4159 | { |
||
4160 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4161 | struct edp_power_seq cur, vbt, spec, final; |
||
4162 | u32 pp_on, pp_off, pp_div, pp; |
||
4560 | Serge | 4163 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
3243 | Serge | 4164 | |
3746 | Serge | 4165 | if (HAS_PCH_SPLIT(dev)) { |
4560 | Serge | 4166 | pp_ctrl_reg = PCH_PP_CONTROL; |
3746 | Serge | 4167 | pp_on_reg = PCH_PP_ON_DELAYS; |
4168 | pp_off_reg = PCH_PP_OFF_DELAYS; |
||
4169 | pp_div_reg = PCH_PP_DIVISOR; |
||
4170 | } else { |
||
4560 | Serge | 4171 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4172 | |||
4173 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
||
4174 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
||
4175 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
||
4176 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
||
3746 | Serge | 4177 | } |
4178 | |||
3243 | Serge | 4179 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
4180 | * the very first thing. */ |
||
3746 | Serge | 4181 | pp = ironlake_get_pp_control(intel_dp); |
4560 | Serge | 4182 | I915_WRITE(pp_ctrl_reg, pp); |
3243 | Serge | 4183 | |
3746 | Serge | 4184 | pp_on = I915_READ(pp_on_reg); |
4185 | pp_off = I915_READ(pp_off_reg); |
||
4186 | pp_div = I915_READ(pp_div_reg); |
||
3243 | Serge | 4187 | |
4188 | /* Pull timing values out of registers */ |
||
4189 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
||
4190 | PANEL_POWER_UP_DELAY_SHIFT; |
||
4191 | |||
4192 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
||
4193 | PANEL_LIGHT_ON_DELAY_SHIFT; |
||
4194 | |||
4195 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
||
4196 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
||
4197 | |||
4198 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
||
4199 | PANEL_POWER_DOWN_DELAY_SHIFT; |
||
4200 | |||
4201 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
||
4202 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
||
4203 | |||
4204 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
4205 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
||
4206 | |||
4104 | Serge | 4207 | vbt = dev_priv->vbt.edp_pps; |
3243 | Serge | 4208 | |
4209 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
||
4210 | * our hw here, which are all in 100usec. */ |
||
4211 | spec.t1_t3 = 210 * 10; |
||
4212 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
||
4213 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
||
4214 | spec.t10 = 500 * 10; |
||
4215 | /* This one is special and actually in units of 100ms, but zero |
||
4216 | * based in the hw (so we need to add 100 ms). But the sw vbt |
||
4217 | * table multiplies it with 1000 to make it in units of 100usec, |
||
4218 | * too. */ |
||
4219 | spec.t11_t12 = (510 + 100) * 10; |
||
4220 | |||
4221 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
4222 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
||
4223 | |||
4224 | /* Use the max of the register settings and vbt. If both are |
||
4225 | * unset, fall back to the spec limits. */ |
||
4226 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
||
4227 | spec.field : \ |
||
4228 | max(cur.field, vbt.field)) |
||
4229 | assign_final(t1_t3); |
||
4230 | assign_final(t8); |
||
4231 | assign_final(t9); |
||
4232 | assign_final(t10); |
||
4233 | assign_final(t11_t12); |
||
4234 | #undef assign_final |
||
4235 | |||
4236 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
||
4237 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
||
4238 | intel_dp->backlight_on_delay = get_delay(t8); |
||
4239 | intel_dp->backlight_off_delay = get_delay(t9); |
||
4240 | intel_dp->panel_power_down_delay = get_delay(t10); |
||
4241 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
||
4242 | #undef get_delay |
||
4243 | |||
4244 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
||
4245 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
||
4246 | intel_dp->panel_power_cycle_delay); |
||
4247 | |||
4248 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
||
4249 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
||
4250 | |||
4251 | if (out) |
||
4252 | *out = final; |
||
4253 | } |
||
4254 | |||
4255 | static void |
||
4256 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
||
4257 | struct intel_dp *intel_dp, |
||
4258 | struct edp_power_seq *seq) |
||
4259 | { |
||
4260 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3746 | Serge | 4261 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
4262 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
||
4263 | int pp_on_reg, pp_off_reg, pp_div_reg; |
||
3243 | Serge | 4264 | |
3746 | Serge | 4265 | if (HAS_PCH_SPLIT(dev)) { |
4266 | pp_on_reg = PCH_PP_ON_DELAYS; |
||
4267 | pp_off_reg = PCH_PP_OFF_DELAYS; |
||
4268 | pp_div_reg = PCH_PP_DIVISOR; |
||
4269 | } else { |
||
4560 | Serge | 4270 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4271 | |||
4272 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
||
4273 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
||
4274 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
||
3746 | Serge | 4275 | } |
4276 | |||
5060 | serge | 4277 | /* |
4278 | * And finally store the new values in the power sequencer. The |
||
4279 | * backlight delays are set to 1 because we do manual waits on them. For |
||
4280 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
||
4281 | * we'll end up waiting for the backlight off delay twice: once when we |
||
4282 | * do the manual sleep, and once when we disable the panel and wait for |
||
4283 | * the PP_STATUS bit to become zero. |
||
4284 | */ |
||
3243 | Serge | 4285 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5060 | serge | 4286 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4287 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
||
3243 | Serge | 4288 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
4289 | /* Compute the divisor for the pp clock, simply match the Bspec |
||
4290 | * formula. */ |
||
3746 | Serge | 4291 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
3243 | Serge | 4292 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
4293 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
||
4294 | |||
4295 | /* Haswell doesn't have any port selection bits for the panel |
||
4296 | * power sequencer any more. */ |
||
4104 | Serge | 4297 | if (IS_VALLEYVIEW(dev)) { |
4560 | Serge | 4298 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
4299 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
||
4300 | else |
||
4301 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
||
4104 | Serge | 4302 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
4303 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
||
4560 | Serge | 4304 | port_sel = PANEL_PORT_SELECT_DPA; |
3243 | Serge | 4305 | else |
4560 | Serge | 4306 | port_sel = PANEL_PORT_SELECT_DPD; |
3243 | Serge | 4307 | } |
4308 | |||
3746 | Serge | 4309 | pp_on |= port_sel; |
3243 | Serge | 4310 | |
3746 | Serge | 4311 | I915_WRITE(pp_on_reg, pp_on); |
4312 | I915_WRITE(pp_off_reg, pp_off); |
||
4313 | I915_WRITE(pp_div_reg, pp_div); |
||
4314 | |||
3243 | Serge | 4315 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
3746 | Serge | 4316 | I915_READ(pp_on_reg), |
4317 | I915_READ(pp_off_reg), |
||
4318 | I915_READ(pp_div_reg)); |
||
3243 | Serge | 4319 | } |
4320 | |||
5060 | serge | 4321 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
4322 | { |
||
4323 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4324 | struct intel_encoder *encoder; |
||
4325 | struct intel_dp *intel_dp = NULL; |
||
4326 | struct intel_crtc_config *config = NULL; |
||
4327 | struct intel_crtc *intel_crtc = NULL; |
||
4328 | struct intel_connector *intel_connector = dev_priv->drrs.connector; |
||
4329 | u32 reg, val; |
||
4330 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; |
||
4331 | |||
4332 | if (refresh_rate <= 0) { |
||
4333 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
||
4334 | return; |
||
4335 | } |
||
4336 | |||
4337 | if (intel_connector == NULL) { |
||
4338 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); |
||
4339 | return; |
||
4340 | } |
||
4341 | |||
4342 | /* |
||
4343 | * FIXME: This needs proper synchronization with psr state. But really |
||
4344 | * hard to tell without seeing the user of this function of this code. |
||
4345 | * Check locking and ordering once that lands. |
||
4346 | */ |
||
4347 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
||
4348 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
||
4349 | return; |
||
4350 | } |
||
4351 | |||
4352 | encoder = intel_attached_encoder(&intel_connector->base); |
||
4353 | intel_dp = enc_to_intel_dp(&encoder->base); |
||
4354 | intel_crtc = encoder->new_crtc; |
||
4355 | |||
4356 | if (!intel_crtc) { |
||
4357 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
||
4358 | return; |
||
4359 | } |
||
4360 | |||
4361 | config = &intel_crtc->config; |
||
4362 | |||
4363 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { |
||
4364 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
||
4365 | return; |
||
4366 | } |
||
4367 | |||
4368 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) |
||
4369 | index = DRRS_LOW_RR; |
||
4370 | |||
4371 | if (index == intel_dp->drrs_state.refresh_rate_type) { |
||
4372 | DRM_DEBUG_KMS( |
||
4373 | "DRRS requested for previously set RR...ignoring\n"); |
||
4374 | return; |
||
4375 | } |
||
4376 | |||
4377 | if (!intel_crtc->active) { |
||
4378 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
||
4379 | return; |
||
4380 | } |
||
4381 | |||
4382 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
||
4383 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
||
4384 | val = I915_READ(reg); |
||
4385 | if (index > DRRS_HIGH_RR) { |
||
4386 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
||
4387 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); |
||
4388 | } else { |
||
4389 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
||
4390 | } |
||
4391 | I915_WRITE(reg, val); |
||
4392 | } |
||
4393 | |||
4394 | /* |
||
4395 | * mutex taken to ensure that there is no race between differnt |
||
4396 | * drrs calls trying to update refresh rate. This scenario may occur |
||
4397 | * in future when idleness detection based DRRS in kernel and |
||
4398 | * possible calls from user space to set differnt RR are made. |
||
4399 | */ |
||
4400 | |||
4401 | mutex_lock(&intel_dp->drrs_state.mutex); |
||
4402 | |||
4403 | intel_dp->drrs_state.refresh_rate_type = index; |
||
4404 | |||
4405 | mutex_unlock(&intel_dp->drrs_state.mutex); |
||
4406 | |||
4407 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
||
4408 | } |
||
4409 | |||
4410 | static struct drm_display_mode * |
||
4411 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, |
||
4412 | struct intel_connector *intel_connector, |
||
4413 | struct drm_display_mode *fixed_mode) |
||
4414 | { |
||
4415 | struct drm_connector *connector = &intel_connector->base; |
||
4416 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
4417 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
4418 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4419 | struct drm_display_mode *downclock_mode = NULL; |
||
4420 | |||
4421 | if (INTEL_INFO(dev)->gen <= 6) { |
||
4422 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
||
4423 | return NULL; |
||
4424 | } |
||
4425 | |||
4426 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
||
4427 | DRM_INFO("VBT doesn't support DRRS\n"); |
||
4428 | return NULL; |
||
4429 | } |
||
4430 | |||
4431 | downclock_mode = intel_find_panel_downclock |
||
4432 | (dev, fixed_mode, connector); |
||
4433 | |||
4434 | if (!downclock_mode) { |
||
4435 | DRM_INFO("DRRS not supported\n"); |
||
4436 | return NULL; |
||
4437 | } |
||
4438 | |||
4439 | dev_priv->drrs.connector = intel_connector; |
||
4440 | |||
4441 | mutex_init(&intel_dp->drrs_state.mutex); |
||
4442 | |||
4443 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
||
4444 | |||
4445 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
||
4446 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); |
||
4447 | return downclock_mode; |
||
4448 | } |
||
4449 | |||
4450 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) |
||
4451 | { |
||
4452 | struct drm_device *dev = intel_encoder->base.dev; |
||
4453 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4454 | struct intel_dp *intel_dp; |
||
4455 | enum intel_display_power_domain power_domain; |
||
4456 | |||
4457 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
4458 | return; |
||
4459 | |||
4460 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
4461 | if (!edp_have_panel_vdd(intel_dp)) |
||
4462 | return; |
||
4463 | /* |
||
4464 | * The VDD bit needs a power domain reference, so if the bit is |
||
4465 | * already enabled when we boot or resume, grab this reference and |
||
4466 | * schedule a vdd off, so we don't hold on to the reference |
||
4467 | * indefinitely. |
||
4468 | */ |
||
4469 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
||
4470 | power_domain = intel_display_port_power_domain(intel_encoder); |
||
4471 | intel_display_power_get(dev_priv, power_domain); |
||
4472 | |||
4473 | edp_panel_vdd_schedule_off(intel_dp); |
||
4474 | } |
||
4475 | |||
4104 | Serge | 4476 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5060 | serge | 4477 | struct intel_connector *intel_connector, |
4478 | struct edp_power_seq *power_seq) |
||
4104 | Serge | 4479 | { |
4480 | struct drm_connector *connector = &intel_connector->base; |
||
4481 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
5060 | serge | 4482 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4483 | struct drm_device *dev = intel_encoder->base.dev; |
||
4104 | Serge | 4484 | struct drm_i915_private *dev_priv = dev->dev_private; |
4485 | struct drm_display_mode *fixed_mode = NULL; |
||
5060 | serge | 4486 | struct drm_display_mode *downclock_mode = NULL; |
4104 | Serge | 4487 | bool has_dpcd; |
4488 | struct drm_display_mode *scan; |
||
4489 | struct edid *edid; |
||
4490 | |||
5060 | serge | 4491 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
4492 | |||
4104 | Serge | 4493 | if (!is_edp(intel_dp)) |
4494 | return true; |
||
4495 | |||
5060 | serge | 4496 | intel_edp_panel_vdd_sanitize(intel_encoder); |
4104 | Serge | 4497 | |
4498 | /* Cache DPCD and EDID for edp. */ |
||
5060 | serge | 4499 | intel_edp_panel_vdd_on(intel_dp); |
4104 | Serge | 4500 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5060 | serge | 4501 | edp_panel_vdd_off(intel_dp, false); |
4104 | Serge | 4502 | |
4503 | if (has_dpcd) { |
||
4504 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
||
4505 | dev_priv->no_aux_handshake = |
||
4506 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
||
4507 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
||
4508 | } else { |
||
4509 | /* if this fails, presume the device is a ghost */ |
||
4510 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
||
4511 | return false; |
||
4512 | } |
||
4513 | |||
4514 | /* We now know it's not a ghost, init power sequence regs. */ |
||
5060 | serge | 4515 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
4104 | Serge | 4516 | |
5060 | serge | 4517 | mutex_lock(&dev->mode_config.mutex); |
4518 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
||
4104 | Serge | 4519 | if (edid) { |
4520 | if (drm_add_edid_modes(connector, edid)) { |
||
4521 | drm_mode_connector_update_edid_property(connector, |
||
4522 | edid); |
||
4523 | drm_edid_to_eld(connector, edid); |
||
4524 | } else { |
||
4525 | kfree(edid); |
||
4526 | edid = ERR_PTR(-EINVAL); |
||
4527 | } |
||
4528 | } else { |
||
4529 | edid = ERR_PTR(-ENOENT); |
||
4530 | } |
||
4531 | intel_connector->edid = edid; |
||
4532 | |||
4533 | /* prefer fixed mode from EDID if available */ |
||
4534 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
4535 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
||
4536 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
5060 | serge | 4537 | downclock_mode = intel_dp_drrs_init( |
4538 | intel_dig_port, |
||
4539 | intel_connector, fixed_mode); |
||
4104 | Serge | 4540 | break; |
4541 | } |
||
4542 | } |
||
4543 | |||
4544 | /* fallback to VBT if available for eDP */ |
||
4545 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
||
4546 | fixed_mode = drm_mode_duplicate(dev, |
||
4547 | dev_priv->vbt.lfp_lvds_vbt_mode); |
||
4548 | if (fixed_mode) |
||
4549 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
4550 | } |
||
5060 | serge | 4551 | mutex_unlock(&dev->mode_config.mutex); |
4104 | Serge | 4552 | |
5060 | serge | 4553 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
4104 | Serge | 4554 | intel_panel_setup_backlight(connector); |
4555 | |||
4556 | return true; |
||
4557 | } |
||
4558 | |||
4559 | bool |
||
3243 | Serge | 4560 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
4561 | struct intel_connector *intel_connector) |
||
2330 | Serge | 4562 | { |
3243 | Serge | 4563 | struct drm_connector *connector = &intel_connector->base; |
4564 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
4565 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
4566 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 4567 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 4568 | enum port port = intel_dig_port->port; |
5060 | serge | 4569 | struct edp_power_seq power_seq = { 0 }; |
4570 | int type; |
||
2330 | Serge | 4571 | |
5060 | serge | 4572 | /* intel_dp vfuncs */ |
4573 | if (IS_VALLEYVIEW(dev)) |
||
4574 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
||
4575 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
||
4576 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
||
4577 | else if (HAS_PCH_SPLIT(dev)) |
||
4578 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
||
4579 | else |
||
4580 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
||
4581 | |||
4582 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
||
4583 | |||
3031 | serge | 4584 | /* Preserve the current hw state. */ |
4585 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
||
3243 | Serge | 4586 | intel_dp->attached_connector = intel_connector; |
2330 | Serge | 4587 | |
4560 | Serge | 4588 | if (intel_dp_is_edp(dev, port)) |
4589 | type = DRM_MODE_CONNECTOR_eDP; |
||
4590 | else |
||
4104 | Serge | 4591 | type = DRM_MODE_CONNECTOR_DisplayPort; |
2330 | Serge | 4592 | |
4104 | Serge | 4593 | /* |
4594 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
||
4595 | * for DP the encoder type can be set by the caller to |
||
4596 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
||
4597 | */ |
||
4598 | if (type == DRM_MODE_CONNECTOR_eDP) |
||
4599 | intel_encoder->type = INTEL_OUTPUT_EDP; |
||
4600 | |||
4601 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
||
4602 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
||
4603 | port_name(port)); |
||
4604 | |||
2330 | Serge | 4605 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
4606 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
||
4607 | |||
4608 | connector->interlace_allowed = true; |
||
4609 | connector->doublescan_allowed = 0; |
||
4610 | |||
3243 | Serge | 4611 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
5060 | serge | 4612 | edp_panel_vdd_work); |
2330 | Serge | 4613 | |
4614 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
5060 | serge | 4615 | drm_connector_register(connector); |
2330 | Serge | 4616 | |
3480 | Serge | 4617 | if (HAS_DDI(dev)) |
3243 | Serge | 4618 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
4619 | else |
||
3031 | serge | 4620 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 4621 | intel_connector->unregister = intel_dp_connector_unregister; |
3031 | serge | 4622 | |
5060 | serge | 4623 | /* Set up the hotplug pin. */ |
3031 | serge | 4624 | switch (port) { |
4625 | case PORT_A: |
||
3746 | Serge | 4626 | intel_encoder->hpd_pin = HPD_PORT_A; |
2330 | Serge | 4627 | break; |
3031 | serge | 4628 | case PORT_B: |
3746 | Serge | 4629 | intel_encoder->hpd_pin = HPD_PORT_B; |
2330 | Serge | 4630 | break; |
3031 | serge | 4631 | case PORT_C: |
3746 | Serge | 4632 | intel_encoder->hpd_pin = HPD_PORT_C; |
2330 | Serge | 4633 | break; |
3031 | serge | 4634 | case PORT_D: |
3746 | Serge | 4635 | intel_encoder->hpd_pin = HPD_PORT_D; |
2330 | Serge | 4636 | break; |
3031 | serge | 4637 | default: |
3746 | Serge | 4638 | BUG(); |
2330 | Serge | 4639 | } |
4640 | |||
5060 | serge | 4641 | if (is_edp(intel_dp)) { |
4642 | intel_dp_init_panel_power_timestamps(intel_dp); |
||
4643 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
||
4644 | } |
||
2330 | Serge | 4645 | |
5060 | serge | 4646 | intel_dp_aux_init(intel_dp, intel_connector); |
3031 | serge | 4647 | |
5060 | serge | 4648 | /* init MST on ports that can support it */ |
4649 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
||
4650 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
||
4651 | intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); |
||
4652 | } |
||
4653 | } |
||
4654 | |||
4655 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
||
4656 | drm_dp_aux_unregister(&intel_dp->aux); |
||
3031 | serge | 4657 | if (is_edp(intel_dp)) { |
4293 | Serge | 4658 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5060 | serge | 4659 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4660 | edp_panel_vdd_off_sync(intel_dp); |
||
4661 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
||
2330 | Serge | 4662 | } |
5060 | serge | 4663 | drm_connector_unregister(connector); |
4104 | Serge | 4664 | drm_connector_cleanup(connector); |
4665 | return false; |
||
2330 | Serge | 4666 | } |
4667 | |||
4668 | intel_dp_add_properties(intel_dp, connector); |
||
4669 | |||
4670 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
4671 | * 0xd. Failure to do so will result in spurious interrupts being |
||
4672 | * generated on the port when a cable is not attached. |
||
4673 | */ |
||
4674 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
4675 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
4676 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
4677 | } |
||
4104 | Serge | 4678 | |
4679 | return true; |
||
2330 | Serge | 4680 | } |
3243 | Serge | 4681 | |
4682 | void |
||
4683 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
||
4684 | { |
||
5060 | serge | 4685 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 4686 | struct intel_digital_port *intel_dig_port; |
4687 | struct intel_encoder *intel_encoder; |
||
4688 | struct drm_encoder *encoder; |
||
4689 | struct intel_connector *intel_connector; |
||
4690 | |||
4560 | Serge | 4691 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3243 | Serge | 4692 | if (!intel_dig_port) |
4693 | return; |
||
4694 | |||
4560 | Serge | 4695 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
3243 | Serge | 4696 | if (!intel_connector) { |
4697 | kfree(intel_dig_port); |
||
4698 | return; |
||
4699 | } |
||
4700 | |||
4701 | intel_encoder = &intel_dig_port->base; |
||
4702 | encoder = &intel_encoder->base; |
||
4703 | |||
4704 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
||
4705 | DRM_MODE_ENCODER_TMDS); |
||
4706 | |||
3746 | Serge | 4707 | intel_encoder->compute_config = intel_dp_compute_config; |
3243 | Serge | 4708 | intel_encoder->disable = intel_disable_dp; |
4709 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
||
4104 | Serge | 4710 | intel_encoder->get_config = intel_dp_get_config; |
5060 | serge | 4711 | intel_encoder->suspend = intel_dp_encoder_suspend; |
4712 | if (IS_CHERRYVIEW(dev)) { |
||
4713 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
||
4714 | intel_encoder->pre_enable = chv_pre_enable_dp; |
||
4715 | intel_encoder->enable = vlv_enable_dp; |
||
4716 | intel_encoder->post_disable = chv_post_disable_dp; |
||
4717 | } else if (IS_VALLEYVIEW(dev)) { |
||
4560 | Serge | 4718 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
4104 | Serge | 4719 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
4720 | intel_encoder->enable = vlv_enable_dp; |
||
5060 | serge | 4721 | intel_encoder->post_disable = vlv_post_disable_dp; |
4104 | Serge | 4722 | } else { |
4560 | Serge | 4723 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
4724 | intel_encoder->enable = g4x_enable_dp; |
||
5060 | serge | 4725 | intel_encoder->post_disable = g4x_post_disable_dp; |
4104 | Serge | 4726 | } |
3243 | Serge | 4727 | |
4728 | intel_dig_port->port = port; |
||
4729 | intel_dig_port->dp.output_reg = output_reg; |
||
4730 | |||
4731 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
5060 | serge | 4732 | if (IS_CHERRYVIEW(dev)) { |
4733 | if (port == PORT_D) |
||
4734 | intel_encoder->crtc_mask = 1 << 2; |
||
4735 | else |
||
4736 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
4737 | } else { |
||
3243 | Serge | 4738 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
5060 | serge | 4739 | } |
4740 | intel_encoder->cloneable = 0; |
||
3243 | Serge | 4741 | intel_encoder->hot_plug = intel_dp_hot_plug; |
4742 | |||
5060 | serge | 4743 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
4744 | dev_priv->hpd_irq_port[port] = intel_dig_port; |
||
4745 | |||
4104 | Serge | 4746 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
4747 | drm_encoder_cleanup(encoder); |
||
4748 | kfree(intel_dig_port); |
||
4749 | kfree(intel_connector); |
||
4750 | } |
||
3243 | Serge | 4751 | } |
5060 | serge | 4752 | |
4753 | void intel_dp_mst_suspend(struct drm_device *dev) |
||
4754 | { |
||
4755 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4756 | int i; |
||
4757 | |||
4758 | /* disable MST */ |
||
4759 | for (i = 0; i < I915_MAX_PORTS; i++) { |
||
4760 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
||
4761 | if (!intel_dig_port) |
||
4762 | continue; |
||
4763 | |||
4764 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
||
4765 | if (!intel_dig_port->dp.can_mst) |
||
4766 | continue; |
||
4767 | if (intel_dig_port->dp.is_mst) |
||
4768 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
||
4769 | } |
||
4770 | } |
||
4771 | } |
||
4772 | |||
4773 | void intel_dp_mst_resume(struct drm_device *dev) |
||
4774 | { |
||
4775 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
4776 | int i; |
||
4777 | |||
4778 | for (i = 0; i < I915_MAX_PORTS; i++) { |
||
4779 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
||
4780 | if (!intel_dig_port) |
||
4781 | continue; |
||
4782 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
||
4783 | int ret; |
||
4784 | |||
4785 | if (!intel_dig_port->dp.can_mst) |
||
4786 | continue; |
||
4787 | |||
4788 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
||
4789 | if (ret != 0) { |
||
4790 | intel_dp_check_mst_status(&intel_dig_port->dp); |
||
4791 | } |
||
4792 | } |
||
4793 | } |
||
4794 | }>>><>><>><>><>><>><>=>>>>=>><>><>><>><>><>><>>>>>>>>>>>>>><>><>>>>><>>><>>>><>><>> |