WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_dp.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Keith Packard
		25	*
		26	*/
		27
		28	#include
2330	Serge	29	#include
3031	serge	30	#include
		31	#include
		32	#include
		33	#include
		34	#include
2327	Serge	35	#include "intel_drv.h"
3031	serge	36	#include
2327	Serge	37	#include "i915_drv.h"
		38
		39	#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
		40
		41	/**
		42	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
		43	* @intel_dp: DP struct
		44	*
		45	* If a CPU or PCH DP output is attached to an eDP panel, this function
		46	* will return true, and false otherwise.
		47	*/
		48	static bool is_edp(struct intel_dp *intel_dp)
		49	{
3243	Serge	50	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		51
		52	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
2327	Serge	53	}
		54
3243	Serge	55	static struct drm_device intel_dp_to_dev(struct intel_dp intel_dp)
2327	Serge	56	{
3243	Serge	57	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		58
		59	return intel_dig_port->base.base.dev;
2327	Serge	60	}
		61
2330	Serge	62	static struct intel_dp intel_attached_dp(struct drm_connector connector)
		63	{
3243	Serge	64	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
2330	Serge	65	}
2327	Serge	66
2330	Serge	67	static void intel_dp_link_down(struct intel_dp *intel_dp);
		68
		69	static int
		70	intel_dp_max_link_bw(struct intel_dp *intel_dp)
		71	{
		72	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
2327	Serge	73
2330	Serge	74	switch (max_link_bw) {
		75	case DP_LINK_BW_1_62:
		76	case DP_LINK_BW_2_7:
		77	break;
4104	Serge	78	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
		79	max_link_bw = DP_LINK_BW_2_7;
		80	break;
2330	Serge	81	default:
4104	Serge	82	WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		83	max_link_bw);
2330	Serge	84	max_link_bw = DP_LINK_BW_1_62;
		85	break;
		86	}
		87	return max_link_bw;
		88	}
2327	Serge	89
2342	Serge	90	/*
		91	* The units on the numbers in the next two are... bizarre. Examples will
		92	* make it clearer; this one parallels an example in the eDP spec.
		93	*
		94	* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
		95	*
		96	* 270000 * 1 * 8 / 10 == 216000
		97	*
		98	* The actual data capacity of that configuration is 2.16Gbit/s, so the
		99	* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
		100	* or equivalently, kilopixels per second - so for 1680x1050R it'd be
		101	* 119000. At 18bpp that's 2142000 kilobits per second.
		102	*
		103	* Thus the strange-looking division by 10 in intel_dp_link_required, to
		104	* get the result in decakilobits instead of kilobits.
		105	*/
		106
2330	Serge	107	static int
2351	Serge	108	intel_dp_link_required(int pixel_clock, int bpp)
2330	Serge	109	{
2342	Serge	110	return (pixel_clock * bpp + 9) / 10;
2330	Serge	111	}
2327	Serge	112
2330	Serge	113	static int
		114	intel_dp_max_data_rate(int max_link_clock, int max_lanes)
		115	{
		116	return (max_link_clock * max_lanes * 8) / 10;
		117	}
2327	Serge	118
2330	Serge	119	static int
		120	intel_dp_mode_valid(struct drm_connector *connector,
		121	struct drm_display_mode *mode)
		122	{
		123	struct intel_dp *intel_dp = intel_attached_dp(connector);
3243	Serge	124	struct intel_connector *intel_connector = to_intel_connector(connector);
		125	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
3746	Serge	126	int target_clock = mode->clock;
		127	int max_rate, mode_rate, max_lanes, max_link_clock;
2327	Serge	128
3243	Serge	129	if (is_edp(intel_dp) && fixed_mode) {
		130	if (mode->hdisplay > fixed_mode->hdisplay)
2330	Serge	131	return MODE_PANEL;
2327	Serge	132
3243	Serge	133	if (mode->vdisplay > fixed_mode->vdisplay)
2330	Serge	134	return MODE_PANEL;
3746	Serge	135
		136	target_clock = fixed_mode->clock;
2330	Serge	137	}
2327	Serge	138
3746	Serge	139	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
		140	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
		141
		142	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
		143	mode_rate = intel_dp_link_required(target_clock, 18);
		144
		145	if (mode_rate > max_rate)
2330	Serge	146	return MODE_CLOCK_HIGH;
2327	Serge	147
2330	Serge	148	if (mode->clock < 10000)
		149	return MODE_CLOCK_LOW;
		150
3031	serge	151	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		152	return MODE_H_ILLEGAL;
		153
2330	Serge	154	return MODE_OK;
		155	}
		156
		157	static uint32_t
		158	pack_aux(uint8_t *src, int src_bytes)
		159	{
		160	int i;
		161	uint32_t v = 0;
		162
		163	if (src_bytes > 4)
		164	src_bytes = 4;
		165	for (i = 0; i < src_bytes; i++)
		166	v \|= ((uint32_t) src[i]) << ((3-i) * 8);
		167	return v;
		168	}
		169
		170	static void
		171	unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
		172	{
		173	int i;
		174	if (dst_bytes > 4)
		175	dst_bytes = 4;
		176	for (i = 0; i < dst_bytes; i++)
		177	dst[i] = src >> ((3-i) * 8);
		178	}
		179
		180	/* hrawclock is 1/4 the FSB frequency */
		181	static int
		182	intel_hrawclk(struct drm_device *dev)
		183	{
		184	struct drm_i915_private *dev_priv = dev->dev_private;
		185	uint32_t clkcfg;
		186
3243	Serge	187	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
		188	if (IS_VALLEYVIEW(dev))
		189	return 200;
		190
2330	Serge	191	clkcfg = I915_READ(CLKCFG);
		192	switch (clkcfg & CLKCFG_FSB_MASK) {
		193	case CLKCFG_FSB_400:
		194	return 100;
		195	case CLKCFG_FSB_533:
		196	return 133;
		197	case CLKCFG_FSB_667:
		198	return 166;
		199	case CLKCFG_FSB_800:
		200	return 200;
		201	case CLKCFG_FSB_1067:
		202	return 266;
		203	case CLKCFG_FSB_1333:
		204	return 333;
		205	/* these two are just a guess; one of them might be right */
		206	case CLKCFG_FSB_1600:
		207	case CLKCFG_FSB_1600_ALT:
		208	return 400;
		209	default:
		210	return 133;
		211	}
		212	}
		213
2342	Serge	214	static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
		215	{
3243	Serge	216	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	217	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	218	u32 pp_stat_reg;
2342	Serge	219
3746	Serge	220	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		221	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
2342	Serge	222	}
		223
		224	static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
		225	{
3243	Serge	226	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	227	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	228	u32 pp_ctrl_reg;
2342	Serge	229
3746	Serge	230	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		231	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
2342	Serge	232	}
		233
		234	static void
		235	intel_dp_check_edp(struct intel_dp *intel_dp)
		236	{
3243	Serge	237	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	238	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	239	u32 pp_stat_reg, pp_ctrl_reg;
2342	Serge	240
		241	if (!is_edp(intel_dp))
		242	return;
3746	Serge	243
		244	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		245	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		246
2342	Serge	247	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
		248	WARN(1, "eDP powered off while attempting aux channel communication.\n");
		249	DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
3746	Serge	250	I915_READ(pp_stat_reg),
		251	I915_READ(pp_ctrl_reg));
2342	Serge	252	}
		253	}
		254
3480	Serge	255	static uint32_t
		256	intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
		257	{
		258	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		259	struct drm_device *dev = intel_dig_port->base.base.dev;
		260	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	261	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
3480	Serge	262	uint32_t status;
		263	bool done;
		264
		265	#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		266	if (has_aux_irq)
		267	done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
4104	Serge	268	msecs_to_jiffies_timeout(10));
3480	Serge	269	else
		270	done = wait_for_atomic(C, 10) == 0;
		271	if (!done)
		272	DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
		273	has_aux_irq);
		274	#undef C
		275
		276	return status;
		277	}
		278
4104	Serge	279	static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
		280	int index)
		281	{
		282	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		283	struct drm_device *dev = intel_dig_port->base.base.dev;
		284	struct drm_i915_private *dev_priv = dev->dev_private;
		285
		286	/* The clock divider is based off the hrawclk,
		287	* and would like to run at 2MHz. So, take the
		288	* hrawclk value and divide by 2 and use that
		289	*
		290	* Note that PCH attached eDP panels should use a 125MHz input
		291	* clock divider.
		292	*/
		293	if (IS_VALLEYVIEW(dev)) {
		294	return index ? 0 : 100;
		295	} else if (intel_dig_port->port == PORT_A) {
		296	if (index)
		297	return 0;
		298	if (HAS_DDI(dev))
		299	return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
		300	else if (IS_GEN6(dev) \|\| IS_GEN7(dev))
		301	return 200; /* SNB & IVB eDP input clock at 400Mhz */
		302	else
		303	return 225; /* eDP input clock at 450Mhz */
		304	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		305	/* Workaround for non-ULT HSW */
		306	switch (index) {
		307	case 0: return 63;
		308	case 1: return 72;
		309	default: return 0;
		310	}
		311	} else if (HAS_PCH_SPLIT(dev)) {
		312	return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
		313	} else {
		314	return index ? 0 :intel_hrawclk(dev) / 2;
		315	}
		316	}
		317
2330	Serge	318	static int
		319	intel_dp_aux_ch(struct intel_dp *intel_dp,
		320	uint8_t *send, int send_bytes,
		321	uint8_t *recv, int recv_size)
		322	{
3243	Serge	323	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		324	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	325	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	326	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
2330	Serge	327	uint32_t ch_data = ch_ctl + 4;
4104	Serge	328	uint32_t aux_clock_divider;
3480	Serge	329	int i, ret, recv_bytes;
2330	Serge	330	uint32_t status;
4104	Serge	331	int try, precharge, clock = 0;
3480	Serge	332	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
2330	Serge	333
3480	Serge	334	/* dp aux is extremely sensitive to irq latency, hence request the
		335	* lowest possible wakeup latency and so prevent the cpu from going into
		336	* deep sleep states.
		337	*/
		338	// pm_qos_update_request(&dev_priv->pm_qos, 0);
		339
2342	Serge	340	intel_dp_check_edp(intel_dp);
2330	Serge	341
		342	if (IS_GEN6(dev))
		343	precharge = 3;
		344	else
		345	precharge = 5;
		346
4104	Serge	347	intel_aux_display_runtime_get(dev_priv);
		348
2330	Serge	349	/* Try to wait for any previous AUX channel activity */
		350	for (try = 0; try < 3; try++) {
3480	Serge	351	status = I915_READ_NOTRACE(ch_ctl);
2330	Serge	352	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		353	break;
		354	msleep(1);
		355	}
		356
		357	if (try == 3) {
		358	WARN(1, "dp_aux_ch not started status 0x%08x\n",
		359	I915_READ(ch_ctl));
3480	Serge	360	ret = -EBUSY;
		361	goto out;
2330	Serge	362	}
		363
4104	Serge	364	while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
2330	Serge	365	/* Must try at least 3 times according to DP spec */
		366	for (try = 0; try < 5; try++) {
		367	/* Load the send data into the aux channel data registers */
		368	for (i = 0; i < send_bytes; i += 4)
		369	I915_WRITE(ch_data + i,
		370	pack_aux(send + i, send_bytes - i));
		371
		372	/* Send the command and wait for it to complete */
		373	I915_WRITE(ch_ctl,
		374	DP_AUX_CH_CTL_SEND_BUSY \|
3480	Serge	375	(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) \|
2330	Serge	376	DP_AUX_CH_CTL_TIME_OUT_400us \|
		377	(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		378	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		379	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) \|
		380	DP_AUX_CH_CTL_DONE \|
		381	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		382	DP_AUX_CH_CTL_RECEIVE_ERROR);
		383
3480	Serge	384	status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
		385
2330	Serge	386	/* Clear done status and any errors */
		387	I915_WRITE(ch_ctl,
		388	status \|
		389	DP_AUX_CH_CTL_DONE \|
		390	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		391	DP_AUX_CH_CTL_RECEIVE_ERROR);
3031	serge	392
		393	if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		394	DP_AUX_CH_CTL_RECEIVE_ERROR))
		395	continue;
2330	Serge	396	if (status & DP_AUX_CH_CTL_DONE)
		397	break;
		398	}
4104	Serge	399	if (status & DP_AUX_CH_CTL_DONE)
		400	break;
		401	}
2330	Serge	402
		403	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		404	DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
3480	Serge	405	ret = -EBUSY;
		406	goto out;
2330	Serge	407	}
		408
		409	/* Check for timeout or receive error.
		410	* Timeouts occur when the sink is not connected
		411	*/
		412	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
		413	DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
3480	Serge	414	ret = -EIO;
		415	goto out;
2330	Serge	416	}
		417
		418	/* Timeouts occur when the device isn't connected, so they're
		419	* "normal" -- don't fill the kernel log with these */
		420	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
		421	DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
3480	Serge	422	ret = -ETIMEDOUT;
		423	goto out;
2330	Serge	424	}
		425
		426	/* Unload any bytes sent back from the other side */
		427	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		428	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
		429	if (recv_bytes > recv_size)
		430	recv_bytes = recv_size;
		431
		432	for (i = 0; i < recv_bytes; i += 4)
		433	unpack_aux(I915_READ(ch_data + i),
		434	recv + i, recv_bytes - i);
		435
3480	Serge	436	ret = recv_bytes;
		437	out:
		438	// pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
4104	Serge	439	intel_aux_display_runtime_put(dev_priv);
3480	Serge	440
		441	return ret;
2330	Serge	442	}
		443
		444	/* Write data to the aux channel in native mode */
		445	static int
		446	intel_dp_aux_native_write(struct intel_dp *intel_dp,
		447	uint16_t address, uint8_t *send, int send_bytes)
		448	{
		449	int ret;
		450	uint8_t msg[20];
		451	int msg_bytes;
		452	uint8_t ack;
		453
2342	Serge	454	intel_dp_check_edp(intel_dp);
2330	Serge	455	if (send_bytes > 16)
		456	return -1;
		457	msg[0] = AUX_NATIVE_WRITE << 4;
		458	msg[1] = address >> 8;
		459	msg[2] = address & 0xff;
		460	msg[3] = send_bytes - 1;
		461	memcpy(&msg[4], send, send_bytes);
		462	msg_bytes = send_bytes + 4;
		463	for (;;) {
		464	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
		465	if (ret < 0)
		466	return ret;
		467	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		468	break;
		469	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		470	udelay(100);
		471	else
		472	return -EIO;
		473	}
		474	return send_bytes;
		475	}
		476
		477	/* Write a single byte to the aux channel in native mode */
		478	static int
		479	intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
		480	uint16_t address, uint8_t byte)
		481	{
		482	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
		483	}
		484
		485	/* read bytes from a native aux channel */
		486	static int
		487	intel_dp_aux_native_read(struct intel_dp *intel_dp,
		488	uint16_t address, uint8_t *recv, int recv_bytes)
		489	{
		490	uint8_t msg[4];
		491	int msg_bytes;
		492	uint8_t reply[20];
		493	int reply_bytes;
		494	uint8_t ack;
		495	int ret;
		496
2342	Serge	497	intel_dp_check_edp(intel_dp);
2330	Serge	498	msg[0] = AUX_NATIVE_READ << 4;
		499	msg[1] = address >> 8;
		500	msg[2] = address & 0xff;
		501	msg[3] = recv_bytes - 1;
		502
		503	msg_bytes = 4;
		504	reply_bytes = recv_bytes + 1;
		505
		506	for (;;) {
		507	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
		508	reply, reply_bytes);
		509	if (ret == 0)
		510	return -EPROTO;
		511	if (ret < 0)
		512	return ret;
		513	ack = reply[0];
		514	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
		515	memcpy(recv, reply + 1, ret - 1);
		516	return ret - 1;
		517	}
		518	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		519	udelay(100);
		520	else
		521	return -EIO;
		522	}
		523	}
		524
		525	static int
		526	intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		527	uint8_t write_byte, uint8_t *read_byte)
		528	{
		529	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
		530	struct intel_dp *intel_dp = container_of(adapter,
		531	struct intel_dp,
		532	adapter);
		533	uint16_t address = algo_data->address;
		534	uint8_t msg[5];
		535	uint8_t reply[2];
		536	unsigned retry;
		537	int msg_bytes;
		538	int reply_bytes;
		539	int ret;
		540
2342	Serge	541	intel_dp_check_edp(intel_dp);
2330	Serge	542	/* Set up the command byte */
		543	if (mode & MODE_I2C_READ)
		544	msg[0] = AUX_I2C_READ << 4;
		545	else
		546	msg[0] = AUX_I2C_WRITE << 4;
		547
		548	if (!(mode & MODE_I2C_STOP))
		549	msg[0] \|= AUX_I2C_MOT << 4;
		550
		551	msg[1] = address >> 8;
		552	msg[2] = address;
		553
		554	switch (mode) {
		555	case MODE_I2C_WRITE:
		556	msg[3] = 0;
		557	msg[4] = write_byte;
		558	msg_bytes = 5;
		559	reply_bytes = 1;
		560	break;
		561	case MODE_I2C_READ:
		562	msg[3] = 0;
		563	msg_bytes = 4;
		564	reply_bytes = 2;
		565	break;
		566	default:
		567	msg_bytes = 3;
		568	reply_bytes = 1;
		569	break;
		570	}
		571
		572	for (retry = 0; retry < 5; retry++) {
		573	ret = intel_dp_aux_ch(intel_dp,
		574	msg, msg_bytes,
		575	reply, reply_bytes);
		576	if (ret < 0) {
		577	DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
		578	return ret;
		579	}
		580
		581	switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		582	case AUX_NATIVE_REPLY_ACK:
		583	/* I2C-over-AUX Reply field is only valid
		584	* when paired with AUX ACK.
		585	*/
		586	break;
		587	case AUX_NATIVE_REPLY_NACK:
		588	DRM_DEBUG_KMS("aux_ch native nack\n");
		589	return -EREMOTEIO;
		590	case AUX_NATIVE_REPLY_DEFER:
4104	Serge	591	udelay(500);
2330	Serge	592	continue;
		593	default:
		594	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
		595	reply[0]);
		596	return -EREMOTEIO;
		597	}
		598
		599	switch (reply[0] & AUX_I2C_REPLY_MASK) {
		600	case AUX_I2C_REPLY_ACK:
		601	if (mode == MODE_I2C_READ) {
		602	*read_byte = reply[1];
		603	}
		604	return reply_bytes - 1;
		605	case AUX_I2C_REPLY_NACK:
		606	DRM_DEBUG_KMS("aux_i2c nack\n");
		607	return -EREMOTEIO;
		608	case AUX_I2C_REPLY_DEFER:
		609	DRM_DEBUG_KMS("aux_i2c defer\n");
		610	udelay(100);
		611	break;
		612	default:
		613	DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
		614	return -EREMOTEIO;
		615	}
		616	}
		617
		618	DRM_ERROR("too many retries, giving up\n");
		619	return -EREMOTEIO;
		620	}
		621
		622	static int
		623	intel_dp_i2c_init(struct intel_dp *intel_dp,
		624	struct intel_connector intel_connector, const char name)
		625	{
2342	Serge	626	int ret;
		627
2330	Serge	628	DRM_DEBUG_KMS("i2c_init %s\n", name);
		629	intel_dp->algo.running = false;
		630	intel_dp->algo.address = 0;
		631	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
		632
2342	Serge	633	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
3031	serge	634	intel_dp->adapter.owner = THIS_MODULE;
2330	Serge	635	intel_dp->adapter.class = I2C_CLASS_DDC;
2342	Serge	636	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
2330	Serge	637	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
		638	intel_dp->adapter.algo_data = &intel_dp->algo;
		639	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
		640
2342	Serge	641	ironlake_edp_panel_vdd_on(intel_dp);
		642	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
		643	ironlake_edp_panel_vdd_off(intel_dp, false);
		644	return ret;
2330	Serge	645	}
		646
4104	Serge	647	static void
		648	intel_dp_set_clock(struct intel_encoder *encoder,
		649	struct intel_crtc_config *pipe_config, int link_bw)
		650	{
		651	struct drm_device *dev = encoder->base.dev;
		652
		653	if (IS_G4X(dev)) {
		654	if (link_bw == DP_LINK_BW_1_62) {
		655	pipe_config->dpll.p1 = 2;
		656	pipe_config->dpll.p2 = 10;
		657	pipe_config->dpll.n = 2;
		658	pipe_config->dpll.m1 = 23;
		659	pipe_config->dpll.m2 = 8;
		660	} else {
		661	pipe_config->dpll.p1 = 1;
		662	pipe_config->dpll.p2 = 10;
		663	pipe_config->dpll.n = 1;
		664	pipe_config->dpll.m1 = 14;
		665	pipe_config->dpll.m2 = 2;
		666	}
		667	pipe_config->clock_set = true;
		668	} else if (IS_HASWELL(dev)) {
		669	/* Haswell has special-purpose DP DDI clocks. */
		670	} else if (HAS_PCH_SPLIT(dev)) {
		671	if (link_bw == DP_LINK_BW_1_62) {
		672	pipe_config->dpll.n = 1;
		673	pipe_config->dpll.p1 = 2;
		674	pipe_config->dpll.p2 = 10;
		675	pipe_config->dpll.m1 = 12;
		676	pipe_config->dpll.m2 = 9;
		677	} else {
		678	pipe_config->dpll.n = 2;
		679	pipe_config->dpll.p1 = 1;
		680	pipe_config->dpll.p2 = 10;
		681	pipe_config->dpll.m1 = 14;
		682	pipe_config->dpll.m2 = 8;
		683	}
		684	pipe_config->clock_set = true;
		685	} else if (IS_VALLEYVIEW(dev)) {
		686	/* FIXME: Need to figure out optimized DP clocks for vlv. */
		687	}
		688	}
		689
3243	Serge	690	bool
3746	Serge	691	intel_dp_compute_config(struct intel_encoder *encoder,
		692	struct intel_crtc_config *pipe_config)
2330	Serge	693	{
3746	Serge	694	struct drm_device *dev = encoder->base.dev;
		695	struct drm_i915_private *dev_priv = dev->dev_private;
		696	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		697	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	698	enum port port = dp_to_dig_port(intel_dp)->port;
		699	struct intel_crtc *intel_crtc = encoder->new_crtc;
3243	Serge	700	struct intel_connector *intel_connector = intel_dp->attached_connector;
2330	Serge	701	int lane_count, clock;
3243	Serge	702	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
2330	Serge	703	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
3031	serge	704	int bpp, mode_rate;
2330	Serge	705	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
4104	Serge	706	int link_avail, link_clock;
2330	Serge	707
4104	Serge	708	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
3746	Serge	709	pipe_config->has_pch_encoder = true;
		710
		711	pipe_config->has_dp_encoder = true;
		712
3243	Serge	713	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		714	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
		715	adjusted_mode);
4104	Serge	716	if (!HAS_PCH_SPLIT(dev))
		717	intel_gmch_panel_fitting(intel_crtc, pipe_config,
		718	intel_connector->panel.fitting_mode);
		719	else
		720	intel_pch_panel_fitting(intel_crtc, pipe_config,
		721	intel_connector->panel.fitting_mode);
2330	Serge	722	}
		723
3031	serge	724	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		725	return false;
		726
		727	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		728	"max bw %02x pixel clock %iKHz\n",
		729	max_lane_count, bws[max_clock], adjusted_mode->clock);
		730
3746	Serge	731	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
		732	* bpc in between. */
4104	Serge	733	bpp = pipe_config->pipe_bpp;
		734	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
		735	DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
		736	dev_priv->vbt.edp_bpp);
		737	bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
		738	}
3746	Serge	739
		740	for (; bpp >= 63; bpp -= 23) {
4104	Serge	741	mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
3746	Serge	742
		743	for (clock = 0; clock <= max_clock; clock++) {
		744	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		745	link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
		746	link_avail = intel_dp_max_data_rate(link_clock,
		747	lane_count);
		748
		749	if (mode_rate <= link_avail) {
		750	goto found;
		751	}
		752	}
		753	}
		754	}
		755
3031	serge	756	return false;
		757
3746	Serge	758	found:
3480	Serge	759	if (intel_dp->color_range_auto) {
		760	/*
		761	* See:
		762	* CEA-861-E - 5.1 Default Encoding Parameters
		763	* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		764	*/
		765	if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
		766	intel_dp->color_range = DP_COLOR_RANGE_16_235;
		767	else
		768	intel_dp->color_range = 0;
		769	}
		770
		771	if (intel_dp->color_range)
3746	Serge	772	pipe_config->limited_color_range = true;
3480	Serge	773
2330	Serge	774	intel_dp->link_bw = bws[clock];
		775	intel_dp->lane_count = lane_count;
3746	Serge	776	pipe_config->pipe_bpp = bpp;
4104	Serge	777	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
3746	Serge	778
		779	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
2330	Serge	780	intel_dp->link_bw, intel_dp->lane_count,
4104	Serge	781	pipe_config->port_clock, bpp);
3031	serge	782	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		783	mode_rate, link_avail);
2330	Serge	784
3746	Serge	785	intel_link_compute_m_n(bpp, lane_count,
4104	Serge	786	adjusted_mode->clock, pipe_config->port_clock,
3746	Serge	787	&pipe_config->dp_m_n);
2330	Serge	788
4104	Serge	789	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
		790
3746	Serge	791	return true;
2327	Serge	792	}
		793
3243	Serge	794	void intel_dp_init_link_config(struct intel_dp *intel_dp)
		795	{
		796	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
		797	intel_dp->link_configuration[0] = intel_dp->link_bw;
		798	intel_dp->link_configuration[1] = intel_dp->lane_count;
		799	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
		800	/*
		801	* Check for DPCD version > 1.1 and enhanced framing support
		802	*/
		803	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		804	(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		805	intel_dp->link_configuration[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
		806	}
		807	}
		808
4104	Serge	809	static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
3480	Serge	810	{
4104	Serge	811	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		812	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
		813	struct drm_device *dev = crtc->base.dev;
3480	Serge	814	struct drm_i915_private *dev_priv = dev->dev_private;
		815	u32 dpa_ctl;
		816
4104	Serge	817	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
3480	Serge	818	dpa_ctl = I915_READ(DP_A);
		819	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		820
4104	Serge	821	if (crtc->config.port_clock == 162000) {
3480	Serge	822	/* For a long time we've carried around a ILK-DevA w/a for the
		823	* 160MHz clock. If we're really unlucky, it's still required.
		824	*/
		825	DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
		826	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
4104	Serge	827	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
3480	Serge	828	} else {
		829	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
4104	Serge	830	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
3480	Serge	831	}
		832
		833	I915_WRITE(DP_A, dpa_ctl);
		834
		835	POSTING_READ(DP_A);
		836	udelay(500);
		837	}
		838
4104	Serge	839	static void intel_dp_mode_set(struct intel_encoder *encoder)
2330	Serge	840	{
4104	Serge	841	struct drm_device *dev = encoder->base.dev;
2342	Serge	842	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	843	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		844	enum port port = dp_to_dig_port(intel_dp)->port;
		845	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		846	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
2327	Serge	847
2342	Serge	848	/*
		849	* There are four kinds of DP registers:
		850	*
		851	* IBX PCH
		852	* SNB CPU
		853	* IVB CPU
		854	* CPT PCH
		855	*
		856	* IBX PCH and CPU are the same for almost everything,
		857	* except that the CPU DP PLL is configured in this
		858	* register
		859	*
		860	* CPT PCH is quite different, having many bits moved
		861	* to the TRANS_DP_CTL register instead. That
		862	* configuration happens (oddly) in ironlake_pch_enable
		863	*/
2327	Serge	864
2342	Serge	865	/* Preserve the BIOS-computed detected bit. This is
		866	* supposed to be read-only.
		867	*/
		868	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2327	Serge	869
2342	Serge	870	/* Handle DP bits in common between all three register formats */
		871	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
4104	Serge	872	intel_dp->DP \|= DP_PORT_WIDTH(intel_dp->lane_count);
2342	Serge	873
		874	if (intel_dp->has_audio) {
		875	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
4104	Serge	876	pipe_name(crtc->pipe));
2330	Serge	877	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
4104	Serge	878	intel_write_eld(&encoder->base, adjusted_mode);
2342	Serge	879	}
2327	Serge	880
3243	Serge	881	intel_dp_init_link_config(intel_dp);
		882
2342	Serge	883	/* Split out the IBX/CPU vs CPT settings */
		884
4104	Serge	885	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
2342	Serge	886	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		887	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		888	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		889	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		890	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		891
		892	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		893	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		894
4104	Serge	895	intel_dp->DP \|= crtc->pipe << 29;
		896	} else if (!HAS_PCH_CPT(dev) \|\| port == PORT_A) {
3746	Serge	897	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
2342	Serge	898	intel_dp->DP \|= intel_dp->color_range;
		899
		900	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		901	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		902	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		903	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		904	intel_dp->DP \|= DP_LINK_TRAIN_OFF;
		905
		906	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		907	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		908
4104	Serge	909	if (crtc->pipe == 1)
2330	Serge	910	intel_dp->DP \|= DP_PIPEB_SELECT;
2342	Serge	911	} else {
		912	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		913	}
3480	Serge	914
4104	Serge	915	if (port == PORT_A && !IS_VALLEYVIEW(dev))
		916	ironlake_set_pll_cpu_edp(intel_dp);
2330	Serge	917	}
2327	Serge	918
2342	Serge	919	#define IDLE_ON_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		920	#define IDLE_ON_VALUE (PP_ON \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_ON_IDLE)
		921
		922	#define IDLE_OFF_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		923	#define IDLE_OFF_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		924
		925	#define IDLE_CYCLE_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| PP_CYCLE_DELAY_ACTIVE \| PP_SEQUENCE_STATE_MASK)
		926	#define IDLE_CYCLE_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		927
		928	static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
		929	u32 mask,
		930	u32 value)
		931	{
3243	Serge	932	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2342	Serge	933	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	934	u32 pp_stat_reg, pp_ctrl_reg;
2342	Serge	935
3746	Serge	936	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		937	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		938
2342	Serge	939	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		940	mask, value,
3746	Serge	941	I915_READ(pp_stat_reg),
		942	I915_READ(pp_ctrl_reg));
2342	Serge	943
3746	Serge	944	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
2342	Serge	945	DRM_ERROR("Panel status timeout: status %08x control %08x\n",
3746	Serge	946	I915_READ(pp_stat_reg),
		947	I915_READ(pp_ctrl_reg));
2342	Serge	948	}
		949	}
		950
		951	static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
		952	{
		953	DRM_DEBUG_KMS("Wait for panel power on\n");
		954	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
		955	}
		956
		957	static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
		958	{
		959	DRM_DEBUG_KMS("Wait for panel power off time\n");
		960	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
		961	}
		962
		963	static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
		964	{
		965	DRM_DEBUG_KMS("Wait for panel power cycle\n");
		966	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
		967	}
		968
		969
		970	/* Read the current pp_control value, unlocking the register if it
		971	* is locked
		972	*/
		973
3746	Serge	974	static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2342	Serge	975	{
3746	Serge	976	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		977	struct drm_i915_private *dev_priv = dev->dev_private;
		978	u32 control;
		979	u32 pp_ctrl_reg;
2342	Serge	980
3746	Serge	981	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		982	control = I915_READ(pp_ctrl_reg);
		983
2342	Serge	984	control &= ~PANEL_UNLOCK_MASK;
		985	control \|= PANEL_UNLOCK_REGS;
		986	return control;
		987	}
		988
3243	Serge	989	void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
2330	Serge	990	{
3243	Serge	991	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	992	struct drm_i915_private *dev_priv = dev->dev_private;
		993	u32 pp;
3746	Serge	994	u32 pp_stat_reg, pp_ctrl_reg;
2327	Serge	995
2342	Serge	996	if (!is_edp(intel_dp))
		997	return;
		998	DRM_DEBUG_KMS("Turn eDP VDD on\n");
2327	Serge	999
2342	Serge	1000	WARN(intel_dp->want_panel_vdd,
		1001	"eDP VDD already requested on\n");
		1002
		1003	intel_dp->want_panel_vdd = true;
		1004
		1005	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		1006	DRM_DEBUG_KMS("eDP VDD already on\n");
		1007	return;
		1008	}
		1009
		1010	if (!ironlake_edp_have_panel_power(intel_dp))
		1011	ironlake_wait_panel_power_cycle(intel_dp);
		1012
3746	Serge	1013	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1014	pp \|= EDP_FORCE_VDD;
2342	Serge	1015
3746	Serge	1016	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		1017	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		1018
		1019	I915_WRITE(pp_ctrl_reg, pp);
		1020	POSTING_READ(pp_ctrl_reg);
		1021	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		1022	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2342	Serge	1023	/*
		1024	* If the panel wasn't on, delay before accessing aux channel
		1025	*/
		1026	if (!ironlake_edp_have_panel_power(intel_dp)) {
		1027	DRM_DEBUG_KMS("eDP was not running\n");
		1028	msleep(intel_dp->panel_power_up_delay);
		1029	}
2330	Serge	1030	}
2327	Serge	1031
2342	Serge	1032	static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
2330	Serge	1033	{
3243	Serge	1034	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1035	struct drm_i915_private *dev_priv = dev->dev_private;
		1036	u32 pp;
3746	Serge	1037	u32 pp_stat_reg, pp_ctrl_reg;
2327	Serge	1038
3480	Serge	1039	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
		1040
2342	Serge	1041	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
3746	Serge	1042	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1043	pp &= ~EDP_FORCE_VDD;
2327	Serge	1044
3746	Serge	1045	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		1046	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		1047
		1048	I915_WRITE(pp_ctrl_reg, pp);
		1049	POSTING_READ(pp_ctrl_reg);
		1050
2330	Serge	1051	/* Make sure sequencer is idle before allowing subsequent activity */
3746	Serge	1052	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		1053	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2342	Serge	1054	msleep(intel_dp->panel_power_down_delay);
		1055	}
2330	Serge	1056	}
2327	Serge	1057
3243	Serge	1058	static void ironlake_panel_vdd_work(struct work_struct *__work)
		1059	{
3482	Serge	1060	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
		1061	struct intel_dp, panel_vdd_work);
		1062	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1063
		1064	mutex_lock(&dev->mode_config.mutex);
		1065	ironlake_panel_vdd_off_sync(intel_dp);
		1066	mutex_unlock(&dev->mode_config.mutex);
3243	Serge	1067	}
2342	Serge	1068
3243	Serge	1069	void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2330	Serge	1070	{
2342	Serge	1071	if (!is_edp(intel_dp))
		1072	return;
		1073
		1074	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
		1075	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
		1076
		1077	intel_dp->want_panel_vdd = false;
		1078
		1079	if (sync) {
		1080	ironlake_panel_vdd_off_sync(intel_dp);
		1081	} else {
		1082	/*
		1083	* Queue the timer to fire a long
		1084	* time from now (relative to the power down delay)
		1085	* to keep the panel power up across a sequence of operations
		1086	*/
4126	Serge	1087	schedule_delayed_work(&intel_dp->panel_vdd_work,
		1088	msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
2342	Serge	1089	}
		1090	}
		1091
3243	Serge	1092	void ironlake_edp_panel_on(struct intel_dp *intel_dp)
2342	Serge	1093	{
3243	Serge	1094	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1095	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1096	u32 pp;
3746	Serge	1097	u32 pp_ctrl_reg;
2327	Serge	1098
2342	Serge	1099	if (!is_edp(intel_dp))
		1100	return;
2327	Serge	1101
2342	Serge	1102	DRM_DEBUG_KMS("Turn eDP power on\n");
2327	Serge	1103
2342	Serge	1104	if (ironlake_edp_have_panel_power(intel_dp)) {
		1105	DRM_DEBUG_KMS("eDP power already on\n");
		1106	return;
		1107	}
		1108
		1109	ironlake_wait_panel_power_cycle(intel_dp);
		1110
3746	Serge	1111	pp = ironlake_get_pp_control(intel_dp);
2342	Serge	1112	if (IS_GEN5(dev)) {
2330	Serge	1113	/* ILK workaround: disable reset around power sequence */
		1114	pp &= ~PANEL_POWER_RESET;
		1115	I915_WRITE(PCH_PP_CONTROL, pp);
		1116	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1117	}
2327	Serge	1118
2342	Serge	1119	pp \|= POWER_TARGET_ON;
		1120	if (!IS_GEN5(dev))
		1121	pp \|= PANEL_POWER_RESET;
		1122
3746	Serge	1123	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
2327	Serge	1124
3746	Serge	1125	I915_WRITE(pp_ctrl_reg, pp);
		1126	POSTING_READ(pp_ctrl_reg);
		1127
2342	Serge	1128	ironlake_wait_panel_on(intel_dp);
2327	Serge	1129
2342	Serge	1130	if (IS_GEN5(dev)) {
2330	Serge	1131	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
		1132	I915_WRITE(PCH_PP_CONTROL, pp);
		1133	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1134	}
2330	Serge	1135	}
2327	Serge	1136
3243	Serge	1137	void ironlake_edp_panel_off(struct intel_dp *intel_dp)
2330	Serge	1138	{
3243	Serge	1139	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1140	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1141	u32 pp;
3746	Serge	1142	u32 pp_ctrl_reg;
2327	Serge	1143
2342	Serge	1144	if (!is_edp(intel_dp))
		1145	return;
2327	Serge	1146
2342	Serge	1147	DRM_DEBUG_KMS("Turn eDP power off\n");
2327	Serge	1148
3031	serge	1149	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
2342	Serge	1150
3746	Serge	1151	pp = ironlake_get_pp_control(intel_dp);
3031	serge	1152	/* We need to switch off panel power _and_ force vdd, for otherwise some
		1153	* panels get very unhappy and cease to work. */
2342	Serge	1154	pp &= ~(POWER_TARGET_ON \| EDP_FORCE_VDD \| PANEL_POWER_RESET \| EDP_BLC_ENABLE);
2327	Serge	1155
3746	Serge	1156	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		1157
		1158	I915_WRITE(pp_ctrl_reg, pp);
		1159	POSTING_READ(pp_ctrl_reg);
		1160
3031	serge	1161	intel_dp->want_panel_vdd = false;
		1162
2342	Serge	1163	ironlake_wait_panel_off(intel_dp);
2330	Serge	1164	}
2327	Serge	1165
3243	Serge	1166	void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
2330	Serge	1167	{
3243	Serge	1168	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1169	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	1170	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1171	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
2330	Serge	1172	u32 pp;
3746	Serge	1173	u32 pp_ctrl_reg;
2327	Serge	1174
2342	Serge	1175	if (!is_edp(intel_dp))
		1176	return;
		1177
2330	Serge	1178	DRM_DEBUG_KMS("\n");
		1179	/*
		1180	* If we enable the backlight right away following a panel power
		1181	* on, we may see slight flicker as the panel syncs with the eDP
		1182	* link. So delay a bit to make sure the image is solid before
		1183	* allowing it to appear.
		1184	*/
2342	Serge	1185	msleep(intel_dp->backlight_on_delay);
3746	Serge	1186	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1187	pp \|= EDP_BLC_ENABLE;
3243	Serge	1188
3746	Serge	1189	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		1190
		1191	I915_WRITE(pp_ctrl_reg, pp);
		1192	POSTING_READ(pp_ctrl_reg);
		1193
3243	Serge	1194	intel_panel_enable_backlight(dev, pipe);
2330	Serge	1195	}
2327	Serge	1196
3243	Serge	1197	void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
2330	Serge	1198	{
3243	Serge	1199	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	1200	struct drm_i915_private *dev_priv = dev->dev_private;
		1201	u32 pp;
3746	Serge	1202	u32 pp_ctrl_reg;
2327	Serge	1203
2342	Serge	1204	if (!is_edp(intel_dp))
		1205	return;
		1206
3243	Serge	1207	intel_panel_disable_backlight(dev);
		1208
2330	Serge	1209	DRM_DEBUG_KMS("\n");
3746	Serge	1210	pp = ironlake_get_pp_control(intel_dp);
2330	Serge	1211	pp &= ~EDP_BLC_ENABLE;
3746	Serge	1212
		1213	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
		1214
		1215	I915_WRITE(pp_ctrl_reg, pp);
		1216	POSTING_READ(pp_ctrl_reg);
2342	Serge	1217	msleep(intel_dp->backlight_off_delay);
2330	Serge	1218	}
2327	Serge	1219
3031	serge	1220	static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2330	Serge	1221	{
3243	Serge	1222	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1223	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		1224	struct drm_device *dev = crtc->dev;
2330	Serge	1225	struct drm_i915_private *dev_priv = dev->dev_private;
		1226	u32 dpa_ctl;
2327	Serge	1227
3031	serge	1228	assert_pipe_disabled(dev_priv,
		1229	to_intel_crtc(crtc)->pipe);
		1230
2330	Serge	1231	DRM_DEBUG_KMS("\n");
		1232	dpa_ctl = I915_READ(DP_A);
3031	serge	1233	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
		1234	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
		1235
		1236	/* We don't adjust intel_dp->DP while tearing down the link, to
		1237	* facilitate link retraining (e.g. after hotplug). Hence clear all
		1238	* enable bits here to ensure that we don't enable too much. */
		1239	intel_dp->DP &= ~(DP_PORT_EN \| DP_AUDIO_OUTPUT_ENABLE);
		1240	intel_dp->DP \|= DP_PLL_ENABLE;
		1241	I915_WRITE(DP_A, intel_dp->DP);
2330	Serge	1242	POSTING_READ(DP_A);
		1243	udelay(200);
		1244	}
2327	Serge	1245
3031	serge	1246	static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2330	Serge	1247	{
3243	Serge	1248	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1249	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		1250	struct drm_device *dev = crtc->dev;
2330	Serge	1251	struct drm_i915_private *dev_priv = dev->dev_private;
		1252	u32 dpa_ctl;
2327	Serge	1253
3031	serge	1254	assert_pipe_disabled(dev_priv,
		1255	to_intel_crtc(crtc)->pipe);
		1256
2330	Serge	1257	dpa_ctl = I915_READ(DP_A);
3031	serge	1258	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
		1259	"dp pll off, should be on\n");
		1260	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
		1261
		1262	/* We can't rely on the value tracked for the DP register in
		1263	* intel_dp->DP because link_down must not change that (otherwise link
		1264	* re-training will fail. */
2330	Serge	1265	dpa_ctl &= ~DP_PLL_ENABLE;
		1266	I915_WRITE(DP_A, dpa_ctl);
		1267	POSTING_READ(DP_A);
		1268	udelay(200);
		1269	}
2327	Serge	1270
2330	Serge	1271	/* If the sink supports it, try to set the power state appropriately */
3243	Serge	1272	void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2330	Serge	1273	{
		1274	int ret, i;
2327	Serge	1275
2330	Serge	1276	/* Should have a valid DPCD by this point */
		1277	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		1278	return;
2327	Serge	1279
2330	Serge	1280	if (mode != DRM_MODE_DPMS_ON) {
		1281	ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
		1282	DP_SET_POWER_D3);
		1283	if (ret != 1)
		1284	DRM_DEBUG_DRIVER("failed to write sink power state\n");
		1285	} else {
		1286	/*
		1287	* When turning on, we need to retry for 1ms to give the sink
		1288	* time to wake up.
		1289	*/
		1290	for (i = 0; i < 3; i++) {
		1291	ret = intel_dp_aux_native_write_1(intel_dp,
		1292	DP_SET_POWER,
		1293	DP_SET_POWER_D0);
		1294	if (ret == 1)
		1295	break;
		1296	msleep(1);
		1297	}
		1298	}
		1299	}
2327	Serge	1300
3031	serge	1301	static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
		1302	enum pipe *pipe)
2330	Serge	1303	{
3031	serge	1304	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1305	enum port port = dp_to_dig_port(intel_dp)->port;
3031	serge	1306	struct drm_device *dev = encoder->base.dev;
		1307	struct drm_i915_private *dev_priv = dev->dev_private;
		1308	u32 tmp = I915_READ(intel_dp->output_reg);
2327	Serge	1309
3031	serge	1310	if (!(tmp & DP_PORT_EN))
		1311	return false;
2342	Serge	1312
4104	Serge	1313	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
3031	serge	1314	*pipe = PORT_TO_PIPE_CPT(tmp);
4104	Serge	1315	} else if (!HAS_PCH_CPT(dev) \|\| port == PORT_A) {
3031	serge	1316	*pipe = PORT_TO_PIPE(tmp);
		1317	} else {
		1318	u32 trans_sel;
		1319	u32 trans_dp;
		1320	int i;
2327	Serge	1321
3031	serge	1322	switch (intel_dp->output_reg) {
		1323	case PCH_DP_B:
		1324	trans_sel = TRANS_DP_PORT_SEL_B;
		1325	break;
		1326	case PCH_DP_C:
		1327	trans_sel = TRANS_DP_PORT_SEL_C;
		1328	break;
		1329	case PCH_DP_D:
		1330	trans_sel = TRANS_DP_PORT_SEL_D;
		1331	break;
		1332	default:
		1333	return true;
		1334	}
		1335
		1336	for_each_pipe(i) {
		1337	trans_dp = I915_READ(TRANS_DP_CTL(i));
		1338	if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
		1339	*pipe = i;
		1340	return true;
		1341	}
		1342	}
3243	Serge	1343
		1344	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
		1345	intel_dp->output_reg);
3031	serge	1346	}
		1347
		1348	return true;
2330	Serge	1349	}
2327	Serge	1350
4104	Serge	1351	static void intel_dp_get_config(struct intel_encoder *encoder,
		1352	struct intel_crtc_config *pipe_config)
		1353	{
		1354	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		1355	u32 tmp, flags = 0;
		1356	struct drm_device *dev = encoder->base.dev;
		1357	struct drm_i915_private *dev_priv = dev->dev_private;
		1358	enum port port = dp_to_dig_port(intel_dp)->port;
		1359	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
		1360
		1361	if ((port == PORT_A) \|\| !HAS_PCH_CPT(dev)) {
		1362	tmp = I915_READ(intel_dp->output_reg);
		1363	if (tmp & DP_SYNC_HS_HIGH)
		1364	flags \|= DRM_MODE_FLAG_PHSYNC;
		1365	else
		1366	flags \|= DRM_MODE_FLAG_NHSYNC;
		1367
		1368	if (tmp & DP_SYNC_VS_HIGH)
		1369	flags \|= DRM_MODE_FLAG_PVSYNC;
		1370	else
		1371	flags \|= DRM_MODE_FLAG_NVSYNC;
		1372	} else {
		1373	tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		1374	if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
		1375	flags \|= DRM_MODE_FLAG_PHSYNC;
		1376	else
		1377	flags \|= DRM_MODE_FLAG_NHSYNC;
		1378
		1379	if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
		1380	flags \|= DRM_MODE_FLAG_PVSYNC;
		1381	else
		1382	flags \|= DRM_MODE_FLAG_NVSYNC;
		1383	}
		1384
		1385	pipe_config->adjusted_mode.flags \|= flags;
		1386
		1387	if (dp_to_dig_port(intel_dp)->port == PORT_A) {
		1388	if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
		1389	pipe_config->port_clock = 162000;
		1390	else
		1391	pipe_config->port_clock = 270000;
		1392	}
4280	Serge	1393
		1394	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
		1395	pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		1396	/*
		1397	* This is a big fat ugly hack.
		1398	*
		1399	* Some machines in UEFI boot mode provide us a VBT that has 18
		1400	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		1401	* unknown we fail to light up. Yet the same BIOS boots up with
		1402	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		1403	* max, not what it tells us to use.
		1404	*
		1405	* Note: This will still be broken if the eDP panel is not lit
		1406	* up by the BIOS, and thus we can't get the mode at module
		1407	* load.
		1408	*/
		1409	DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
		1410	pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		1411	dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
		1412	}
4104	Serge	1413	}
		1414
		1415	static bool is_edp_psr(struct intel_dp *intel_dp)
		1416	{
		1417	return is_edp(intel_dp) &&
		1418	intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
		1419	}
		1420
		1421	static bool intel_edp_is_psr_enabled(struct drm_device *dev)
		1422	{
		1423	struct drm_i915_private *dev_priv = dev->dev_private;
		1424
		1425	if (!IS_HASWELL(dev))
		1426	return false;
		1427
		1428	return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
		1429	}
		1430
		1431	static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
		1432	struct edp_vsc_psr *vsc_psr)
		1433	{
		1434	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1435	struct drm_device *dev = dig_port->base.base.dev;
		1436	struct drm_i915_private *dev_priv = dev->dev_private;
		1437	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
		1438	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
		1439	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
		1440	uint32_t data = (uint32_t ) vsc_psr;
		1441	unsigned int i;
		1442
		1443	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
		1444	the video DIP being updated before program video DIP data buffer
		1445	registers for DIP being updated. */
		1446	I915_WRITE(ctl_reg, 0);
		1447	POSTING_READ(ctl_reg);
		1448
		1449	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		1450	if (i < sizeof(struct edp_vsc_psr))
		1451	I915_WRITE(data_reg + i, *data++);
		1452	else
		1453	I915_WRITE(data_reg + i, 0);
		1454	}
		1455
		1456	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
		1457	POSTING_READ(ctl_reg);
		1458	}
		1459
		1460	static void intel_edp_psr_setup(struct intel_dp *intel_dp)
		1461	{
		1462	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1463	struct drm_i915_private *dev_priv = dev->dev_private;
		1464	struct edp_vsc_psr psr_vsc;
		1465
		1466	if (intel_dp->psr_setup_done)
		1467	return;
		1468
		1469	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
		1470	memset(&psr_vsc, 0, sizeof(psr_vsc));
		1471	psr_vsc.sdp_header.HB0 = 0;
		1472	psr_vsc.sdp_header.HB1 = 0x7;
		1473	psr_vsc.sdp_header.HB2 = 0x2;
		1474	psr_vsc.sdp_header.HB3 = 0x8;
		1475	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
		1476
		1477	/* Avoid continuous PSR exit by masking memup and hpd */
		1478	I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP \|
		1479	EDP_PSR_DEBUG_MASK_HPD \| EDP_PSR_DEBUG_MASK_LPSP);
		1480
		1481	intel_dp->psr_setup_done = true;
		1482	}
		1483
		1484	static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
		1485	{
		1486	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1487	struct drm_i915_private *dev_priv = dev->dev_private;
		1488	uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
		1489	int precharge = 0x3;
		1490	int msg_size = 5; /* Header(4) + Message(1) */
		1491
		1492	/* Enable PSR in sink */
		1493	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
		1494	intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
		1495	DP_PSR_ENABLE &
		1496	~DP_PSR_MAIN_LINK_ACTIVE);
		1497	else
		1498	intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
		1499	DP_PSR_ENABLE \|
		1500	DP_PSR_MAIN_LINK_ACTIVE);
		1501
		1502	/* Setup AUX registers */
		1503	I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
		1504	I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
		1505	I915_WRITE(EDP_PSR_AUX_CTL,
		1506	DP_AUX_CH_CTL_TIME_OUT_400us \|
		1507	(msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		1508	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		1509	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
		1510	}
		1511
		1512	static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
		1513	{
		1514	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1515	struct drm_i915_private *dev_priv = dev->dev_private;
		1516	uint32_t max_sleep_time = 0x1f;
		1517	uint32_t idle_frames = 1;
		1518	uint32_t val = 0x0;
		1519
		1520	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
		1521	val \|= EDP_PSR_LINK_STANDBY;
		1522	val \|= EDP_PSR_TP2_TP3_TIME_0us;
		1523	val \|= EDP_PSR_TP1_TIME_0us;
		1524	val \|= EDP_PSR_SKIP_AUX_EXIT;
		1525	} else
		1526	val \|= EDP_PSR_LINK_DISABLE;
		1527
		1528	I915_WRITE(EDP_PSR_CTL, val \|
		1529	EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES \|
		1530	max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT \|
		1531	idle_frames << EDP_PSR_IDLE_FRAME_SHIFT \|
		1532	EDP_PSR_ENABLE);
		1533	}
		1534
		1535	static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
		1536	{
		1537	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1538	struct drm_device *dev = dig_port->base.base.dev;
		1539	struct drm_i915_private *dev_priv = dev->dev_private;
		1540	struct drm_crtc *crtc = dig_port->base.base.crtc;
		1541	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1542	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
		1543	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
		1544
		1545	if (!IS_HASWELL(dev)) {
		1546	DRM_DEBUG_KMS("PSR not supported on this platform\n");
		1547	dev_priv->no_psr_reason = PSR_NO_SOURCE;
		1548	return false;
		1549	}
		1550
		1551	if ((intel_encoder->type != INTEL_OUTPUT_EDP) \|\|
		1552	(dig_port->port != PORT_A)) {
		1553	DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		1554	dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
		1555	return false;
		1556	}
		1557
		1558	if (!is_edp_psr(intel_dp)) {
		1559	DRM_DEBUG_KMS("PSR not supported by this panel\n");
		1560	dev_priv->no_psr_reason = PSR_NO_SINK;
		1561	return false;
		1562	}
		1563
		1564	if (!i915_enable_psr) {
		1565	DRM_DEBUG_KMS("PSR disable by flag\n");
		1566	dev_priv->no_psr_reason = PSR_MODULE_PARAM;
		1567	return false;
		1568	}
		1569
		1570	crtc = dig_port->base.base.crtc;
		1571	if (crtc == NULL) {
		1572	DRM_DEBUG_KMS("crtc not active for PSR\n");
		1573	dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
		1574	return false;
		1575	}
		1576
		1577	intel_crtc = to_intel_crtc(crtc);
		1578	if (!intel_crtc->active \|\| !crtc->fb \|\| !crtc->mode.clock) {
		1579	DRM_DEBUG_KMS("crtc not active for PSR\n");
		1580	dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
		1581	return false;
		1582	}
		1583
		1584	obj = to_intel_framebuffer(crtc->fb)->obj;
		1585	if (obj->tiling_mode != I915_TILING_X \|\|
		1586	obj->fence_reg == I915_FENCE_REG_NONE) {
		1587	DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		1588	dev_priv->no_psr_reason = PSR_NOT_TILED;
		1589	return false;
		1590	}
		1591
		1592	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		1593	DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		1594	dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
		1595	return false;
		1596	}
		1597
		1598	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
		1599	S3D_ENABLE) {
		1600	DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		1601	dev_priv->no_psr_reason = PSR_S3D_ENABLED;
		1602	return false;
		1603	}
		1604
		1605	if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
		1606	DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		1607	dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
		1608	return false;
		1609	}
		1610
		1611	return true;
		1612	}
		1613
		1614	static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
		1615	{
		1616	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1617
		1618	if (!intel_edp_psr_match_conditions(intel_dp) \|\|
		1619	intel_edp_is_psr_enabled(dev))
		1620	return;
		1621
		1622	/* Setup PSR once */
		1623	intel_edp_psr_setup(intel_dp);
		1624
		1625	/* Enable PSR on the panel */
		1626	intel_edp_psr_enable_sink(intel_dp);
		1627
		1628	/* Enable PSR on the host */
		1629	intel_edp_psr_enable_source(intel_dp);
		1630	}
		1631
		1632	void intel_edp_psr_enable(struct intel_dp *intel_dp)
		1633	{
		1634	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1635
		1636	if (intel_edp_psr_match_conditions(intel_dp) &&
		1637	!intel_edp_is_psr_enabled(dev))
		1638	intel_edp_psr_do_enable(intel_dp);
		1639	}
		1640
		1641	void intel_edp_psr_disable(struct intel_dp *intel_dp)
		1642	{
		1643	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1644	struct drm_i915_private *dev_priv = dev->dev_private;
		1645
		1646	if (!intel_edp_is_psr_enabled(dev))
		1647	return;
		1648
		1649	I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
		1650
		1651	/* Wait till PSR is idle */
		1652	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
		1653	EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		1654	DRM_ERROR("Timed out waiting for PSR Idle State\n");
		1655	}
		1656
		1657	void intel_edp_psr_update(struct drm_device *dev)
		1658	{
		1659	struct intel_encoder *encoder;
		1660	struct intel_dp *intel_dp = NULL;
		1661
		1662	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		1663	if (encoder->type == INTEL_OUTPUT_EDP) {
		1664	intel_dp = enc_to_intel_dp(&encoder->base);
		1665
		1666	if (!is_edp_psr(intel_dp))
		1667	return;
		1668
		1669	if (!intel_edp_psr_match_conditions(intel_dp))
		1670	intel_edp_psr_disable(intel_dp);
		1671	else
		1672	if (!intel_edp_is_psr_enabled(dev))
		1673	intel_edp_psr_do_enable(intel_dp);
		1674	}
		1675	}
		1676
3031	serge	1677	static void intel_disable_dp(struct intel_encoder *encoder)
2330	Serge	1678	{
3031	serge	1679	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1680	enum port port = dp_to_dig_port(intel_dp)->port;
		1681	struct drm_device *dev = encoder->base.dev;
2327	Serge	1682
3031	serge	1683	/* Make sure the panel is off before trying to change the mode. But also
		1684	* ensure that we have vdd while we switch off the panel. */
2330	Serge	1685	ironlake_edp_panel_vdd_on(intel_dp);
3031	serge	1686	ironlake_edp_backlight_off(intel_dp);
2342	Serge	1687	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3031	serge	1688	ironlake_edp_panel_off(intel_dp);
2330	Serge	1689
3031	serge	1690	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
4104	Serge	1691	if (!(port == PORT_A \|\| IS_VALLEYVIEW(dev)))
3031	serge	1692	intel_dp_link_down(intel_dp);
		1693	}
2330	Serge	1694
3031	serge	1695	static void intel_post_disable_dp(struct intel_encoder *encoder)
		1696	{
		1697	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1698	enum port port = dp_to_dig_port(intel_dp)->port;
3746	Serge	1699	struct drm_device *dev = encoder->base.dev;
3031	serge	1700
4104	Serge	1701	if (port == PORT_A \|\| IS_VALLEYVIEW(dev)) {
3031	serge	1702	intel_dp_link_down(intel_dp);
3746	Serge	1703	if (!IS_VALLEYVIEW(dev))
3031	serge	1704	ironlake_edp_pll_off(intel_dp);
		1705	}
2330	Serge	1706	}
		1707
3031	serge	1708	static void intel_enable_dp(struct intel_encoder *encoder)
2330	Serge	1709	{
3031	serge	1710	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		1711	struct drm_device *dev = encoder->base.dev;
2330	Serge	1712	struct drm_i915_private *dev_priv = dev->dev_private;
		1713	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		1714
3031	serge	1715	if (WARN_ON(dp_reg & DP_PORT_EN))
		1716	return;
2342	Serge	1717
		1718	ironlake_edp_panel_vdd_on(intel_dp);
3031	serge	1719	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2330	Serge	1720	intel_dp_start_link_train(intel_dp);
		1721	ironlake_edp_panel_on(intel_dp);
2342	Serge	1722	ironlake_edp_panel_vdd_off(intel_dp, true);
2330	Serge	1723	intel_dp_complete_link_train(intel_dp);
3746	Serge	1724	intel_dp_stop_link_train(intel_dp);
2342	Serge	1725	ironlake_edp_backlight_on(intel_dp);
2330	Serge	1726	}
		1727
4104	Serge	1728	static void vlv_enable_dp(struct intel_encoder *encoder)
		1729	{
		1730	}
		1731
3031	serge	1732	static void intel_pre_enable_dp(struct intel_encoder *encoder)
		1733	{
		1734	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4104	Serge	1735	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3031	serge	1736
4104	Serge	1737	if (dport->port == PORT_A)
3031	serge	1738	ironlake_edp_pll_on(intel_dp);
		1739	}
		1740
4104	Serge	1741	static void vlv_pre_enable_dp(struct intel_encoder *encoder)
		1742	{
		1743	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		1744	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		1745	struct drm_device *dev = encoder->base.dev;
		1746	struct drm_i915_private *dev_priv = dev->dev_private;
		1747	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
		1748	int port = vlv_dport_to_channel(dport);
		1749	int pipe = intel_crtc->pipe;
		1750	u32 val;
		1751
		1752	mutex_lock(&dev_priv->dpio_lock);
		1753
		1754	val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
		1755	val = 0;
		1756	if (pipe)
		1757	val \|= (1<<21);
		1758	else
		1759	val &= ~(1<<21);
		1760	val \|= 0x001000c4;
		1761	vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
		1762	vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
		1763	vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
		1764
		1765	mutex_unlock(&dev_priv->dpio_lock);
		1766
		1767	intel_enable_dp(encoder);
		1768
		1769	vlv_wait_port_ready(dev_priv, port);
		1770	}
		1771
		1772	static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
		1773	{
		1774	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		1775	struct drm_device *dev = encoder->base.dev;
		1776	struct drm_i915_private *dev_priv = dev->dev_private;
		1777	int port = vlv_dport_to_channel(dport);
		1778
		1779	if (!IS_VALLEYVIEW(dev))
		1780	return;
		1781
		1782	/* Program Tx lane resets to default */
		1783	mutex_lock(&dev_priv->dpio_lock);
		1784	vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
		1785	DPIO_PCS_TX_LANE2_RESET \|
		1786	DPIO_PCS_TX_LANE1_RESET);
		1787	vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
		1788	DPIO_PCS_CLK_CRI_RXEB_EIOS_EN \|
		1789	DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN \|
		1790	(1<
		1791	DPIO_PCS_CLK_SOFT_RESET);
		1792
		1793	/* Fix up inter-pair skew failure */
		1794	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
		1795	vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
		1796	vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
		1797	mutex_unlock(&dev_priv->dpio_lock);
		1798	}
		1799
2330	Serge	1800	/*
		1801	* Native read with retry for link status and receiver capability reads for
		1802	* cases where the sink may still be asleep.
		1803	*/
		1804	static bool
		1805	intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
		1806	uint8_t *recv, int recv_bytes)
		1807	{
		1808	int ret, i;
		1809
		1810	/*
		1811	* Sinks are supposed to come up within 1ms from an off state,
		1812	* but we're also supposed to retry 3 times per the spec.
		1813	*/
		1814	for (i = 0; i < 3; i++) {
		1815	ret = intel_dp_aux_native_read(intel_dp, address, recv,
		1816	recv_bytes);
		1817	if (ret == recv_bytes)
		1818	return true;
		1819	msleep(1);
		1820	}
		1821
		1822	return false;
		1823	}
		1824
		1825	/*
		1826	* Fetch AUX CH registers 0x202 - 0x207 which contain
		1827	* link status information
		1828	*/
		1829	static bool
2342	Serge	1830	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1831	{
		1832	return intel_dp_aux_native_read_retry(intel_dp,
		1833	DP_LANE0_1_STATUS,
2342	Serge	1834	link_status,
2330	Serge	1835	DP_LINK_STATUS_SIZE);
		1836	}
		1837
		1838	#if 0
		1839	static char *voltage_names[] = {
		1840	"0.4V", "0.6V", "0.8V", "1.2V"
		1841	};
		1842	static char *pre_emph_names[] = {
		1843	"0dB", "3.5dB", "6dB", "9.5dB"
		1844	};
		1845	static char *link_train_names[] = {
		1846	"pattern 1", "pattern 2", "idle", "off"
		1847	};
		1848	#endif
		1849
		1850	/*
		1851	* These are source-specific values; current Intel hardware supports
		1852	* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
		1853	*/
		1854
		1855	static uint8_t
2342	Serge	1856	intel_dp_voltage_max(struct intel_dp *intel_dp)
2330	Serge	1857	{
3243	Serge	1858	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4104	Serge	1859	enum port port = dp_to_dig_port(intel_dp)->port;
2342	Serge	1860
4104	Serge	1861	if (IS_VALLEYVIEW(dev))
		1862	return DP_TRAIN_VOLTAGE_SWING_1200;
		1863	else if (IS_GEN7(dev) && port == PORT_A)
2342	Serge	1864	return DP_TRAIN_VOLTAGE_SWING_800;
4104	Serge	1865	else if (HAS_PCH_CPT(dev) && port != PORT_A)
2342	Serge	1866	return DP_TRAIN_VOLTAGE_SWING_1200;
		1867	else
		1868	return DP_TRAIN_VOLTAGE_SWING_800;
		1869	}
		1870
		1871	static uint8_t
		1872	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
		1873	{
3243	Serge	1874	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4104	Serge	1875	enum port port = dp_to_dig_port(intel_dp)->port;
2342	Serge	1876
3746	Serge	1877	if (HAS_DDI(dev)) {
2342	Serge	1878	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1879	case DP_TRAIN_VOLTAGE_SWING_400:
3243	Serge	1880	return DP_TRAIN_PRE_EMPHASIS_9_5;
		1881	case DP_TRAIN_VOLTAGE_SWING_600:
2342	Serge	1882	return DP_TRAIN_PRE_EMPHASIS_6;
3243	Serge	1883	case DP_TRAIN_VOLTAGE_SWING_800:
		1884	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1885	case DP_TRAIN_VOLTAGE_SWING_1200:
		1886	default:
		1887	return DP_TRAIN_PRE_EMPHASIS_0;
		1888	}
4104	Serge	1889	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	1890	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1891	case DP_TRAIN_VOLTAGE_SWING_400:
4104	Serge	1892	return DP_TRAIN_PRE_EMPHASIS_9_5;
		1893	case DP_TRAIN_VOLTAGE_SWING_600:
3243	Serge	1894	return DP_TRAIN_PRE_EMPHASIS_6;
4104	Serge	1895	case DP_TRAIN_VOLTAGE_SWING_800:
		1896	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1897	case DP_TRAIN_VOLTAGE_SWING_1200:
		1898	default:
		1899	return DP_TRAIN_PRE_EMPHASIS_0;
		1900	}
		1901	} else if (IS_GEN7(dev) && port == PORT_A) {
		1902	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1903	case DP_TRAIN_VOLTAGE_SWING_400:
		1904	return DP_TRAIN_PRE_EMPHASIS_6;
2342	Serge	1905	case DP_TRAIN_VOLTAGE_SWING_600:
		1906	case DP_TRAIN_VOLTAGE_SWING_800:
		1907	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1908	default:
		1909	return DP_TRAIN_PRE_EMPHASIS_0;
		1910	}
		1911	} else {
2330	Serge	1912	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1913	case DP_TRAIN_VOLTAGE_SWING_400:
		1914	return DP_TRAIN_PRE_EMPHASIS_6;
		1915	case DP_TRAIN_VOLTAGE_SWING_600:
		1916	return DP_TRAIN_PRE_EMPHASIS_6;
		1917	case DP_TRAIN_VOLTAGE_SWING_800:
		1918	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1919	case DP_TRAIN_VOLTAGE_SWING_1200:
		1920	default:
		1921	return DP_TRAIN_PRE_EMPHASIS_0;
		1922	}
2342	Serge	1923	}
2330	Serge	1924	}
		1925
4104	Serge	1926	static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
		1927	{
		1928	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1929	struct drm_i915_private *dev_priv = dev->dev_private;
		1930	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		1931	unsigned long demph_reg_value, preemph_reg_value,
		1932	uniqtranscale_reg_value;
		1933	uint8_t train_set = intel_dp->train_set[0];
		1934	int port = vlv_dport_to_channel(dport);
		1935
		1936	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		1937	case DP_TRAIN_PRE_EMPHASIS_0:
		1938	preemph_reg_value = 0x0004000;
		1939	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1940	case DP_TRAIN_VOLTAGE_SWING_400:
		1941	demph_reg_value = 0x2B405555;
		1942	uniqtranscale_reg_value = 0x552AB83A;
		1943	break;
		1944	case DP_TRAIN_VOLTAGE_SWING_600:
		1945	demph_reg_value = 0x2B404040;
		1946	uniqtranscale_reg_value = 0x5548B83A;
		1947	break;
		1948	case DP_TRAIN_VOLTAGE_SWING_800:
		1949	demph_reg_value = 0x2B245555;
		1950	uniqtranscale_reg_value = 0x5560B83A;
		1951	break;
		1952	case DP_TRAIN_VOLTAGE_SWING_1200:
		1953	demph_reg_value = 0x2B405555;
		1954	uniqtranscale_reg_value = 0x5598DA3A;
		1955	break;
		1956	default:
		1957	return 0;
		1958	}
		1959	break;
		1960	case DP_TRAIN_PRE_EMPHASIS_3_5:
		1961	preemph_reg_value = 0x0002000;
		1962	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1963	case DP_TRAIN_VOLTAGE_SWING_400:
		1964	demph_reg_value = 0x2B404040;
		1965	uniqtranscale_reg_value = 0x5552B83A;
		1966	break;
		1967	case DP_TRAIN_VOLTAGE_SWING_600:
		1968	demph_reg_value = 0x2B404848;
		1969	uniqtranscale_reg_value = 0x5580B83A;
		1970	break;
		1971	case DP_TRAIN_VOLTAGE_SWING_800:
		1972	demph_reg_value = 0x2B404040;
		1973	uniqtranscale_reg_value = 0x55ADDA3A;
		1974	break;
		1975	default:
		1976	return 0;
		1977	}
		1978	break;
		1979	case DP_TRAIN_PRE_EMPHASIS_6:
		1980	preemph_reg_value = 0x0000000;
		1981	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1982	case DP_TRAIN_VOLTAGE_SWING_400:
		1983	demph_reg_value = 0x2B305555;
		1984	uniqtranscale_reg_value = 0x5570B83A;
		1985	break;
		1986	case DP_TRAIN_VOLTAGE_SWING_600:
		1987	demph_reg_value = 0x2B2B4040;
		1988	uniqtranscale_reg_value = 0x55ADDA3A;
		1989	break;
		1990	default:
		1991	return 0;
		1992	}
		1993	break;
		1994	case DP_TRAIN_PRE_EMPHASIS_9_5:
		1995	preemph_reg_value = 0x0006000;
		1996	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1997	case DP_TRAIN_VOLTAGE_SWING_400:
		1998	demph_reg_value = 0x1B405555;
		1999	uniqtranscale_reg_value = 0x55ADDA3A;
		2000	break;
		2001	default:
		2002	return 0;
		2003	}
		2004	break;
		2005	default:
		2006	return 0;
		2007	}
		2008
		2009	mutex_lock(&dev_priv->dpio_lock);
		2010	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
		2011	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
		2012	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
		2013	uniqtranscale_reg_value);
		2014	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
		2015	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
		2016	vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
		2017	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
		2018	mutex_unlock(&dev_priv->dpio_lock);
		2019
		2020	return 0;
		2021	}
		2022
2330	Serge	2023	static void
2342	Serge	2024	intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	2025	{
		2026	uint8_t v = 0;
		2027	uint8_t p = 0;
		2028	int lane;
2342	Serge	2029	uint8_t voltage_max;
		2030	uint8_t preemph_max;
2330	Serge	2031
		2032	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3243	Serge	2033	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		2034	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2330	Serge	2035
		2036	if (this_v > v)
		2037	v = this_v;
		2038	if (this_p > p)
		2039	p = this_p;
		2040	}
		2041
2342	Serge	2042	voltage_max = intel_dp_voltage_max(intel_dp);
		2043	if (v >= voltage_max)
		2044	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
2330	Serge	2045
2342	Serge	2046	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
		2047	if (p >= preemph_max)
		2048	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2330	Serge	2049
		2050	for (lane = 0; lane < 4; lane++)
		2051	intel_dp->train_set[lane] = v \| p;
		2052	}
		2053
		2054	static uint32_t
3480	Serge	2055	intel_gen4_signal_levels(uint8_t train_set)
2330	Serge	2056	{
		2057	uint32_t signal_levels = 0;
		2058
		2059	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		2060	case DP_TRAIN_VOLTAGE_SWING_400:
		2061	default:
		2062	signal_levels \|= DP_VOLTAGE_0_4;
		2063	break;
		2064	case DP_TRAIN_VOLTAGE_SWING_600:
		2065	signal_levels \|= DP_VOLTAGE_0_6;
		2066	break;
		2067	case DP_TRAIN_VOLTAGE_SWING_800:
		2068	signal_levels \|= DP_VOLTAGE_0_8;
		2069	break;
		2070	case DP_TRAIN_VOLTAGE_SWING_1200:
		2071	signal_levels \|= DP_VOLTAGE_1_2;
		2072	break;
		2073	}
		2074	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		2075	case DP_TRAIN_PRE_EMPHASIS_0:
		2076	default:
		2077	signal_levels \|= DP_PRE_EMPHASIS_0;
		2078	break;
		2079	case DP_TRAIN_PRE_EMPHASIS_3_5:
		2080	signal_levels \|= DP_PRE_EMPHASIS_3_5;
		2081	break;
		2082	case DP_TRAIN_PRE_EMPHASIS_6:
		2083	signal_levels \|= DP_PRE_EMPHASIS_6;
		2084	break;
		2085	case DP_TRAIN_PRE_EMPHASIS_9_5:
		2086	signal_levels \|= DP_PRE_EMPHASIS_9_5;
		2087	break;
		2088	}
		2089	return signal_levels;
		2090	}
		2091
		2092	/* Gen6's DP voltage swing and pre-emphasis control */
		2093	static uint32_t
		2094	intel_gen6_edp_signal_levels(uint8_t train_set)
		2095	{
		2096	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2097	DP_TRAIN_PRE_EMPHASIS_MASK);
		2098	switch (signal_levels) {
		2099	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2100	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2101	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		2102	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2103	return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
		2104	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2105	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		2106	return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
		2107	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2108	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2109	return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
		2110	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2111	case DP_TRAIN_VOLTAGE_SWING_1200 \| DP_TRAIN_PRE_EMPHASIS_0:
		2112	return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
		2113	default:
		2114	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2115	"0x%x\n", signal_levels);
		2116	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		2117	}
		2118	}
		2119
2342	Serge	2120	/* Gen7's DP voltage swing and pre-emphasis control */
		2121	static uint32_t
		2122	intel_gen7_edp_signal_levels(uint8_t train_set)
		2123	{
		2124	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2125	DP_TRAIN_PRE_EMPHASIS_MASK);
		2126	switch (signal_levels) {
		2127	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2128	return EDP_LINK_TRAIN_400MV_0DB_IVB;
		2129	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2130	return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
		2131	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2132	return EDP_LINK_TRAIN_400MV_6DB_IVB;
		2133
		2134	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2135	return EDP_LINK_TRAIN_600MV_0DB_IVB;
		2136	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2137	return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
		2138
		2139	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2140	return EDP_LINK_TRAIN_800MV_0DB_IVB;
		2141	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2142	return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
		2143
		2144	default:
		2145	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2146	"0x%x\n", signal_levels);
		2147	return EDP_LINK_TRAIN_500MV_0DB_IVB;
		2148	}
		2149	}
		2150
3243	Serge	2151	/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
		2152	static uint32_t
3480	Serge	2153	intel_hsw_signal_levels(uint8_t train_set)
2330	Serge	2154	{
3243	Serge	2155	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2156	DP_TRAIN_PRE_EMPHASIS_MASK);
		2157	switch (signal_levels) {
		2158	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		2159	return DDI_BUF_EMP_400MV_0DB_HSW;
		2160	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2161	return DDI_BUF_EMP_400MV_3_5DB_HSW;
		2162	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		2163	return DDI_BUF_EMP_400MV_6DB_HSW;
		2164	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_9_5:
		2165	return DDI_BUF_EMP_400MV_9_5DB_HSW;
2330	Serge	2166
3243	Serge	2167	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		2168	return DDI_BUF_EMP_600MV_0DB_HSW;
		2169	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2170	return DDI_BUF_EMP_600MV_3_5DB_HSW;
		2171	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		2172	return DDI_BUF_EMP_600MV_6DB_HSW;
2330	Serge	2173
3243	Serge	2174	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		2175	return DDI_BUF_EMP_800MV_0DB_HSW;
		2176	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		2177	return DDI_BUF_EMP_800MV_3_5DB_HSW;
		2178	default:
		2179	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		2180	"0x%x\n", signal_levels);
		2181	return DDI_BUF_EMP_400MV_0DB_HSW;
2330	Serge	2182	}
		2183	}
		2184
3480	Serge	2185	/* Properly updates "DP" with the correct signal levels. */
		2186	static void
		2187	intel_dp_set_signal_levels(struct intel_dp intel_dp, uint32_t DP)
		2188	{
		2189	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4104	Serge	2190	enum port port = intel_dig_port->port;
3480	Serge	2191	struct drm_device *dev = intel_dig_port->base.base.dev;
		2192	uint32_t signal_levels, mask;
		2193	uint8_t train_set = intel_dp->train_set[0];
		2194
3746	Serge	2195	if (HAS_DDI(dev)) {
3480	Serge	2196	signal_levels = intel_hsw_signal_levels(train_set);
		2197	mask = DDI_BUF_EMP_MASK;
4104	Serge	2198	} else if (IS_VALLEYVIEW(dev)) {
		2199	signal_levels = intel_vlv_signal_levels(intel_dp);
		2200	mask = 0;
		2201	} else if (IS_GEN7(dev) && port == PORT_A) {
3480	Serge	2202	signal_levels = intel_gen7_edp_signal_levels(train_set);
		2203	mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4104	Serge	2204	} else if (IS_GEN6(dev) && port == PORT_A) {
3480	Serge	2205	signal_levels = intel_gen6_edp_signal_levels(train_set);
		2206	mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
		2207	} else {
		2208	signal_levels = intel_gen4_signal_levels(train_set);
		2209	mask = DP_VOLTAGE_MASK \| DP_PRE_EMPHASIS_MASK;
		2210	}
		2211
		2212	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
		2213
		2214	DP = (DP & ~mask) \| signal_levels;
		2215	}
		2216
2330	Serge	2217	static bool
		2218	intel_dp_set_link_train(struct intel_dp *intel_dp,
		2219	uint32_t dp_reg_value,
		2220	uint8_t dp_train_pat)
		2221	{
3243	Serge	2222	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		2223	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	2224	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2225	enum port port = intel_dig_port->port;
2330	Serge	2226	int ret;
		2227
3746	Serge	2228	if (HAS_DDI(dev)) {
		2229	uint32_t temp = I915_READ(DP_TP_CTL(port));
3243	Serge	2230
		2231	if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
		2232	temp \|= DP_TP_CTL_SCRAMBLE_DISABLE;
		2233	else
		2234	temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
		2235
		2236	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		2237	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2238	case DP_TRAINING_PATTERN_DISABLE:
		2239	temp \|= DP_TP_CTL_LINK_TRAIN_NORMAL;
		2240
		2241	break;
		2242	case DP_TRAINING_PATTERN_1:
		2243	temp \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		2244	break;
		2245	case DP_TRAINING_PATTERN_2:
		2246	temp \|= DP_TP_CTL_LINK_TRAIN_PAT2;
		2247	break;
		2248	case DP_TRAINING_PATTERN_3:
		2249	temp \|= DP_TP_CTL_LINK_TRAIN_PAT3;
		2250	break;
		2251	}
		2252	I915_WRITE(DP_TP_CTL(port), temp);
		2253
4104	Serge	2254	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| port != PORT_A)) {
3031	serge	2255	dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
		2256
		2257	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2258	case DP_TRAINING_PATTERN_DISABLE:
		2259	dp_reg_value \|= DP_LINK_TRAIN_OFF_CPT;
		2260	break;
		2261	case DP_TRAINING_PATTERN_1:
		2262	dp_reg_value \|= DP_LINK_TRAIN_PAT_1_CPT;
		2263	break;
		2264	case DP_TRAINING_PATTERN_2:
		2265	dp_reg_value \|= DP_LINK_TRAIN_PAT_2_CPT;
		2266	break;
		2267	case DP_TRAINING_PATTERN_3:
		2268	DRM_ERROR("DP training pattern 3 not supported\n");
		2269	dp_reg_value \|= DP_LINK_TRAIN_PAT_2_CPT;
		2270	break;
		2271	}
		2272
		2273	} else {
		2274	dp_reg_value &= ~DP_LINK_TRAIN_MASK;
		2275
		2276	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		2277	case DP_TRAINING_PATTERN_DISABLE:
		2278	dp_reg_value \|= DP_LINK_TRAIN_OFF;
		2279	break;
		2280	case DP_TRAINING_PATTERN_1:
		2281	dp_reg_value \|= DP_LINK_TRAIN_PAT_1;
		2282	break;
		2283	case DP_TRAINING_PATTERN_2:
		2284	dp_reg_value \|= DP_LINK_TRAIN_PAT_2;
		2285	break;
		2286	case DP_TRAINING_PATTERN_3:
		2287	DRM_ERROR("DP training pattern 3 not supported\n");
		2288	dp_reg_value \|= DP_LINK_TRAIN_PAT_2;
		2289	break;
		2290	}
		2291	}
		2292
2330	Serge	2293	I915_WRITE(intel_dp->output_reg, dp_reg_value);
		2294	POSTING_READ(intel_dp->output_reg);
		2295
		2296	intel_dp_aux_native_write_1(intel_dp,
		2297	DP_TRAINING_PATTERN_SET,
		2298	dp_train_pat);
		2299
3031	serge	2300	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
		2301	DP_TRAINING_PATTERN_DISABLE) {
2330	Serge	2302	ret = intel_dp_aux_native_write(intel_dp,
		2303	DP_TRAINING_LANE0_SET,
2342	Serge	2304	intel_dp->train_set,
		2305	intel_dp->lane_count);
		2306	if (ret != intel_dp->lane_count)
2330	Serge	2307	return false;
3031	serge	2308	}
2330	Serge	2309
		2310	return true;
		2311	}
		2312
3746	Serge	2313	static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
		2314	{
		2315	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		2316	struct drm_device *dev = intel_dig_port->base.base.dev;
		2317	struct drm_i915_private *dev_priv = dev->dev_private;
		2318	enum port port = intel_dig_port->port;
		2319	uint32_t val;
		2320
		2321	if (!HAS_DDI(dev))
		2322	return;
		2323
		2324	val = I915_READ(DP_TP_CTL(port));
		2325	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		2326	val \|= DP_TP_CTL_LINK_TRAIN_IDLE;
		2327	I915_WRITE(DP_TP_CTL(port), val);
		2328
		2329	/*
		2330	* On PORT_A we can have only eDP in SST mode. There the only reason
		2331	* we need to set idle transmission mode is to work around a HW issue
		2332	* where we enable the pipe while not in idle link-training mode.
		2333	* In this case there is requirement to wait for a minimum number of
		2334	* idle patterns to be sent.
		2335	*/
		2336	if (port == PORT_A)
		2337	return;
		2338
		2339	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		2340	1))
		2341	DRM_ERROR("Timed out waiting for DP idle patterns\n");
		2342	}
		2343
2330	Serge	2344	/* Enable corresponding port and start training pattern 1 */
3243	Serge	2345	void
2330	Serge	2346	intel_dp_start_link_train(struct intel_dp *intel_dp)
		2347	{
3243	Serge	2348	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
		2349	struct drm_device *dev = encoder->dev;
2330	Serge	2350	int i;
		2351	uint8_t voltage;
2342	Serge	2352	int voltage_tries, loop_tries;
2330	Serge	2353	uint32_t DP = intel_dp->DP;
		2354
3480	Serge	2355	if (HAS_DDI(dev))
3243	Serge	2356	intel_ddi_prepare_link_retrain(encoder);
		2357
2330	Serge	2358	/* Write the link configuration data */
		2359	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
		2360	intel_dp->link_configuration,
		2361	DP_LINK_CONFIGURATION_SIZE);
		2362
		2363	DP \|= DP_PORT_EN;
2342	Serge	2364
2330	Serge	2365	memset(intel_dp->train_set, 0, 4);
		2366	voltage = 0xff;
2342	Serge	2367	voltage_tries = 0;
		2368	loop_tries = 0;
2330	Serge	2369	for (;;) {
		2370	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2342	Serge	2371	uint8_t link_status[DP_LINK_STATUS_SIZE];
		2372
3480	Serge	2373	intel_dp_set_signal_levels(intel_dp, &DP);
2330	Serge	2374
3243	Serge	2375	/* Set training pattern 1 */
3031	serge	2376	if (!intel_dp_set_link_train(intel_dp, DP,
2330	Serge	2377	DP_TRAINING_PATTERN_1 \|
		2378	DP_LINK_SCRAMBLING_DISABLE))
		2379	break;
		2380
3243	Serge	2381	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2342	Serge	2382	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		2383	DRM_ERROR("failed to get link status\n");
2330	Serge	2384	break;
2342	Serge	2385	}
2330	Serge	2386
3243	Serge	2387	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2342	Serge	2388	DRM_DEBUG_KMS("clock recovery OK\n");
2330	Serge	2389	break;
		2390	}
		2391
		2392	/* Check to see if we've tried the max voltage */
		2393	for (i = 0; i < intel_dp->lane_count; i++)
		2394	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
		2395	break;
3480	Serge	2396	if (i == intel_dp->lane_count) {
2342	Serge	2397	++loop_tries;
		2398	if (loop_tries == 5) {
		2399	DRM_DEBUG_KMS("too many full retries, give up\n");
2330	Serge	2400	break;
2342	Serge	2401	}
		2402	memset(intel_dp->train_set, 0, 4);
		2403	voltage_tries = 0;
		2404	continue;
		2405	}
2330	Serge	2406
		2407	/* Check to see if we've tried the same voltage 5 times */
		2408	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2342	Serge	2409	++voltage_tries;
		2410	if (voltage_tries == 5) {
		2411	DRM_DEBUG_KMS("too many voltage retries, give up\n");
2330	Serge	2412	break;
2342	Serge	2413	}
2330	Serge	2414	} else
2342	Serge	2415	voltage_tries = 0;
2330	Serge	2416	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
		2417
		2418	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	2419	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	2420	}
		2421
		2422	intel_dp->DP = DP;
		2423	}
		2424
3243	Serge	2425	void
2330	Serge	2426	intel_dp_complete_link_train(struct intel_dp *intel_dp)
		2427	{
		2428	bool channel_eq = false;
		2429	int tries, cr_tries;
		2430	uint32_t DP = intel_dp->DP;
		2431
		2432	/* channel equalization */
		2433	tries = 0;
		2434	cr_tries = 0;
		2435	channel_eq = false;
		2436	for (;;) {
2342	Serge	2437	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	2438
		2439	if (cr_tries > 5) {
		2440	DRM_ERROR("failed to train DP, aborting\n");
		2441	intel_dp_link_down(intel_dp);
		2442	break;
		2443	}
		2444
3480	Serge	2445	intel_dp_set_signal_levels(intel_dp, &DP);
2330	Serge	2446
		2447	/* channel eq pattern */
3031	serge	2448	if (!intel_dp_set_link_train(intel_dp, DP,
2330	Serge	2449	DP_TRAINING_PATTERN_2 \|
		2450	DP_LINK_SCRAMBLING_DISABLE))
		2451	break;
		2452
3243	Serge	2453	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2342	Serge	2454	if (!intel_dp_get_link_status(intel_dp, link_status))
2330	Serge	2455	break;
		2456
		2457	/* Make sure clock is still ok */
3243	Serge	2458	if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2330	Serge	2459	intel_dp_start_link_train(intel_dp);
		2460	cr_tries++;
		2461	continue;
		2462	}
		2463
3243	Serge	2464	if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2330	Serge	2465	channel_eq = true;
		2466	break;
		2467	}
		2468
		2469	/* Try 5 times, then try clock recovery if that fails */
		2470	if (tries > 5) {
		2471	intel_dp_link_down(intel_dp);
		2472	intel_dp_start_link_train(intel_dp);
		2473	tries = 0;
		2474	cr_tries++;
		2475	continue;
		2476	}
		2477
		2478	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	2479	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	2480	++tries;
		2481	}
		2482
3746	Serge	2483	intel_dp_set_idle_link_train(intel_dp);
		2484
		2485	intel_dp->DP = DP;
		2486
3243	Serge	2487	if (channel_eq)
3746	Serge	2488	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3243	Serge	2489
2330	Serge	2490	}
		2491
3746	Serge	2492	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
		2493	{
		2494	intel_dp_set_link_train(intel_dp, intel_dp->DP,
		2495	DP_TRAINING_PATTERN_DISABLE);
		2496	}
		2497
2330	Serge	2498	static void
		2499	intel_dp_link_down(struct intel_dp *intel_dp)
		2500	{
3243	Serge	2501	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4104	Serge	2502	enum port port = intel_dig_port->port;
3243	Serge	2503	struct drm_device *dev = intel_dig_port->base.base.dev;
2330	Serge	2504	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2505	struct intel_crtc *intel_crtc =
		2506	to_intel_crtc(intel_dig_port->base.base.crtc);
2330	Serge	2507	uint32_t DP = intel_dp->DP;
		2508
3243	Serge	2509	/*
		2510	* DDI code has a strict mode set sequence and we should try to respect
		2511	* it, otherwise we might hang the machine in many different ways. So we
		2512	* really should be disabling the port only on a complete crtc_disable
		2513	* sequence. This function is just called under two conditions on DDI
		2514	* code:
		2515	* - Link train failed while doing crtc_enable, and on this case we
		2516	* really should respect the mode set sequence and wait for a
		2517	* crtc_disable.
		2518	* - Someone turned the monitor off and intel_dp_check_link_status
		2519	* called us. We don't need to disable the whole port on this case, so
		2520	* when someone turns the monitor on again,
		2521	* intel_ddi_prepare_link_retrain will take care of redoing the link
		2522	* train.
		2523	*/
3480	Serge	2524	if (HAS_DDI(dev))
3243	Serge	2525	return;
		2526
3031	serge	2527	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2330	Serge	2528	return;
		2529
		2530	DRM_DEBUG_KMS("\n");
		2531
4104	Serge	2532	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| port != PORT_A)) {
2330	Serge	2533	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		2534	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE_CPT);
		2535	} else {
		2536	DP &= ~DP_LINK_TRAIN_MASK;
		2537	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE);
		2538	}
		2539	POSTING_READ(intel_dp->output_reg);
		2540
3480	Serge	2541	/* We don't really know why we're doing this */
		2542	intel_wait_for_vblank(dev, intel_crtc->pipe);
2330	Serge	2543
3031	serge	2544	if (HAS_PCH_IBX(dev) &&
2330	Serge	2545	I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3243	Serge	2546	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2330	Serge	2547
		2548	/* Hardware workaround: leaving our transcoder select
		2549	* set to transcoder B while it's off will prevent the
		2550	* corresponding HDMI output on transcoder A.
		2551	*
		2552	* Combine this with another hardware workaround:
		2553	* transcoder select bit can only be cleared while the
		2554	* port is enabled.
		2555	*/
		2556	DP &= ~DP_PIPEB_SELECT;
		2557	I915_WRITE(intel_dp->output_reg, DP);
		2558
		2559	/* Changes to enable or select take place the vblank
		2560	* after being written.
		2561	*/
3480	Serge	2562	if (WARN_ON(crtc == NULL)) {
		2563	/* We should never try to disable a port without a crtc
		2564	* attached. For paranoia keep the code around for a
		2565	* bit. */
2330	Serge	2566	POSTING_READ(intel_dp->output_reg);
		2567	msleep(50);
		2568	} else
3480	Serge	2569	intel_wait_for_vblank(dev, intel_crtc->pipe);
2330	Serge	2570	}
		2571
2342	Serge	2572	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2330	Serge	2573	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
		2574	POSTING_READ(intel_dp->output_reg);
2342	Serge	2575	msleep(intel_dp->panel_power_down_delay);
2330	Serge	2576	}
		2577
		2578	static bool
		2579	intel_dp_get_dpcd(struct intel_dp *intel_dp)
		2580	{
3480	Serge	2581	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
		2582
2330	Serge	2583	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
3031	serge	2584	sizeof(intel_dp->dpcd)) == 0)
		2585	return false; /* aux transfer failed */
		2586
3480	Serge	2587	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
		2588	32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
		2589	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
		2590
3031	serge	2591	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		2592	return false; /* DPCD not present */
		2593
4104	Serge	2594	/* Check if the panel supports PSR */
		2595	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
		2596	intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
		2597	intel_dp->psr_dpcd,
		2598	sizeof(intel_dp->psr_dpcd));
		2599	if (is_edp_psr(intel_dp))
		2600	DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3031	serge	2601	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
		2602	DP_DWN_STRM_PORT_PRESENT))
		2603	return true; /* native DP sink */
		2604
		2605	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		2606	return true; /* no per-port downstream info */
		2607
		2608	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
		2609	intel_dp->downstream_ports,
		2610	DP_MAX_DOWNSTREAM_PORTS) == 0)
		2611	return false; /* downstream port status fetch failed */
		2612
2330	Serge	2613	return true;
3031	serge	2614	}
2330	Serge	2615
3031	serge	2616	static void
		2617	intel_dp_probe_oui(struct intel_dp *intel_dp)
		2618	{
		2619	u8 buf[3];
		2620
		2621	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		2622	return;
		2623
		2624	ironlake_edp_panel_vdd_on(intel_dp);
		2625
		2626	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		2627	DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
		2628	buf[0], buf[1], buf[2]);
		2629
		2630	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		2631	DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
		2632	buf[0], buf[1], buf[2]);
		2633
		2634	ironlake_edp_panel_vdd_off(intel_dp, false);
2330	Serge	2635	}
		2636
2342	Serge	2637	static bool
		2638	intel_dp_get_sink_irq(struct intel_dp intel_dp, u8 sink_irq_vector)
		2639	{
		2640	int ret;
		2641
		2642	ret = intel_dp_aux_native_read_retry(intel_dp,
		2643	DP_DEVICE_SERVICE_IRQ_VECTOR,
		2644	sink_irq_vector, 1);
		2645	if (!ret)
		2646	return false;
		2647
		2648	return true;
		2649	}
		2650
		2651	static void
		2652	intel_dp_handle_test_request(struct intel_dp *intel_dp)
		2653	{
		2654	/* NAK by default */
3243	Serge	2655	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2342	Serge	2656	}
		2657
2330	Serge	2658	/*
		2659	* According to DP spec
		2660	* 5.1.2:
		2661	* 1. Read DPCD
		2662	* 2. Configure link according to Receiver Capabilities
		2663	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
		2664	* 4. Check link status on receipt of hot-plug interrupt
		2665	*/
		2666
3243	Serge	2667	void
2330	Serge	2668	intel_dp_check_link_status(struct intel_dp *intel_dp)
		2669	{
3243	Serge	2670	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2342	Serge	2671	u8 sink_irq_vector;
		2672	u8 link_status[DP_LINK_STATUS_SIZE];
		2673
3243	Serge	2674	if (!intel_encoder->connectors_active)
2330	Serge	2675	return;
		2676
3243	Serge	2677	if (WARN_ON(!intel_encoder->base.crtc))
2330	Serge	2678	return;
		2679
		2680	/* Try to read receiver status if the link appears to be up */
2342	Serge	2681	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2330	Serge	2682	intel_dp_link_down(intel_dp);
		2683	return;
		2684	}
		2685
		2686	/* Now read the DPCD to see if it's actually running */
		2687	if (!intel_dp_get_dpcd(intel_dp)) {
		2688	intel_dp_link_down(intel_dp);
		2689	return;
		2690	}
		2691
2342	Serge	2692	/* Try to read the source of the interrupt */
		2693	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		2694	intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		2695	/* Clear interrupt source */
		2696	intel_dp_aux_native_write_1(intel_dp,
		2697	DP_DEVICE_SERVICE_IRQ_VECTOR,
		2698	sink_irq_vector);
		2699
		2700	if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
		2701	intel_dp_handle_test_request(intel_dp);
		2702	if (sink_irq_vector & (DP_CP_IRQ \| DP_SINK_SPECIFIC_IRQ))
		2703	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
		2704	}
		2705
3243	Serge	2706	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2330	Serge	2707	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3243	Serge	2708	drm_get_encoder_name(&intel_encoder->base));
2330	Serge	2709	intel_dp_start_link_train(intel_dp);
		2710	intel_dp_complete_link_train(intel_dp);
3746	Serge	2711	intel_dp_stop_link_train(intel_dp);
2330	Serge	2712	}
		2713	}
		2714
3031	serge	2715	/* XXX this is probably wrong for multiple downstream ports */
2330	Serge	2716	static enum drm_connector_status
		2717	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
		2718	{
3031	serge	2719	uint8_t *dpcd = intel_dp->dpcd;
		2720	bool hpd;
		2721	uint8_t type;
		2722
		2723	if (!intel_dp_get_dpcd(intel_dp))
		2724	return connector_status_disconnected;
		2725
		2726	/* if there's no downstream port, we're done */
		2727	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2330	Serge	2728	return connector_status_connected;
3031	serge	2729
		2730	/* If we're HPD-aware, SINK_COUNT changes dynamically */
		2731	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
		2732	if (hpd) {
		2733	uint8_t reg;
		2734	if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
		2735	®, 1))
		2736	return connector_status_unknown;
		2737	return DP_GET_SINK_COUNT(reg) ? connector_status_connected
		2738	: connector_status_disconnected;
		2739	}
		2740
		2741	/* If no HPD, poke DDC gently */
		2742	if (drm_probe_ddc(&intel_dp->adapter))
		2743	return connector_status_connected;
		2744
		2745	/* Well we tried, say unknown for unreliable port types */
		2746	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		2747	if (type == DP_DS_PORT_TYPE_VGA \|\| type == DP_DS_PORT_TYPE_NON_EDID)
		2748	return connector_status_unknown;
		2749
		2750	/* Anything else is out of spec, warn and ignore */
		2751	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2330	Serge	2752	return connector_status_disconnected;
		2753	}
		2754
		2755	static enum drm_connector_status
		2756	ironlake_dp_detect(struct intel_dp *intel_dp)
		2757	{
3243	Serge	2758	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3480	Serge	2759	struct drm_i915_private *dev_priv = dev->dev_private;
		2760	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2330	Serge	2761	enum drm_connector_status status;
		2762
		2763	/* Can't disconnect eDP, but you can close the lid... */
		2764	if (is_edp(intel_dp)) {
3243	Serge	2765	status = intel_panel_detect(dev);
2330	Serge	2766	if (status == connector_status_unknown)
		2767	status = connector_status_connected;
		2768	return status;
		2769	}
		2770
3480	Serge	2771	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		2772	return connector_status_disconnected;
		2773
2330	Serge	2774	return intel_dp_detect_dpcd(intel_dp);
		2775	}
		2776
		2777	static enum drm_connector_status
		2778	g4x_dp_detect(struct intel_dp *intel_dp)
		2779	{
3243	Serge	2780	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	2781	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2782	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3031	serge	2783	uint32_t bit;
2330	Serge	2784
3746	Serge	2785	/* Can't disconnect eDP, but you can close the lid... */
		2786	if (is_edp(intel_dp)) {
		2787	enum drm_connector_status status;
		2788
		2789	status = intel_panel_detect(dev);
		2790	if (status == connector_status_unknown)
		2791	status = connector_status_connected;
		2792	return status;
		2793	}
		2794
3480	Serge	2795	switch (intel_dig_port->port) {
		2796	case PORT_B:
		2797	bit = PORTB_HOTPLUG_LIVE_STATUS;
2330	Serge	2798	break;
3480	Serge	2799	case PORT_C:
		2800	bit = PORTC_HOTPLUG_LIVE_STATUS;
2330	Serge	2801	break;
3480	Serge	2802	case PORT_D:
		2803	bit = PORTD_HOTPLUG_LIVE_STATUS;
2330	Serge	2804	break;
		2805	default:
		2806	return connector_status_unknown;
		2807	}
		2808
3031	serge	2809	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2330	Serge	2810	return connector_status_disconnected;
		2811
		2812	return intel_dp_detect_dpcd(intel_dp);
		2813	}
		2814
2342	Serge	2815	static struct edid *
		2816	intel_dp_get_edid(struct drm_connector connector, struct i2c_adapter adapter)
		2817	{
3243	Serge	2818	struct intel_connector *intel_connector = to_intel_connector(connector);
		2819
		2820	/* use cached edid if we have one */
		2821	if (intel_connector->edid) {
2342	Serge	2822	struct edid *edid;
3031	serge	2823	int size;
2342	Serge	2824
3243	Serge	2825	/* invalid edid */
		2826	if (IS_ERR(intel_connector->edid))
3031	serge	2827	return NULL;
		2828
3243	Serge	2829	size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
4104	Serge	2830	edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
3031	serge	2831	if (!edid)
		2832	return NULL;
		2833
		2834	return edid;
		2835	}
		2836
3243	Serge	2837	return drm_get_edid(connector, adapter);
2342	Serge	2838	}
		2839
		2840	static int
		2841	intel_dp_get_edid_modes(struct drm_connector connector, struct i2c_adapter adapter)
		2842	{
3243	Serge	2843	struct intel_connector *intel_connector = to_intel_connector(connector);
2342	Serge	2844
3243	Serge	2845	/* use cached edid if we have one */
		2846	if (intel_connector->edid) {
		2847	/* invalid edid */
		2848	if (IS_ERR(intel_connector->edid))
		2849	return 0;
		2850
		2851	return intel_connector_update_modes(connector,
		2852	intel_connector->edid);
3031	serge	2853	}
		2854
3243	Serge	2855	return intel_ddc_get_modes(connector, adapter);
2342	Serge	2856	}
		2857
2330	Serge	2858	static enum drm_connector_status
		2859	intel_dp_detect(struct drm_connector *connector, bool force)
		2860	{
		2861	struct intel_dp *intel_dp = intel_attached_dp(connector);
3243	Serge	2862	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		2863	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		2864	struct drm_device *dev = connector->dev;
2330	Serge	2865	enum drm_connector_status status;
		2866	struct edid *edid = NULL;
		2867
4104	Serge	2868	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		2869	connector->base.id, drm_get_connector_name(connector));
		2870
2330	Serge	2871	intel_dp->has_audio = false;
		2872
		2873	if (HAS_PCH_SPLIT(dev))
		2874	status = ironlake_dp_detect(intel_dp);
		2875	else
		2876	status = g4x_dp_detect(intel_dp);
		2877
		2878	if (status != connector_status_connected)
		2879	return status;
3031	serge	2880
		2881	intel_dp_probe_oui(intel_dp);
		2882
3243	Serge	2883	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		2884	intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2330	Serge	2885	} else {
3031	serge	2886	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2330	Serge	2887	if (edid) {
		2888	intel_dp->has_audio = drm_detect_monitor_audio(edid);
		2889	kfree(edid);
		2890	}
		2891	}
3243	Serge	2892
		2893	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		2894	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2330	Serge	2895	return connector_status_connected;
		2896	}
		2897
		2898	static int intel_dp_get_modes(struct drm_connector *connector)
		2899	{
		2900	struct intel_dp *intel_dp = intel_attached_dp(connector);
3243	Serge	2901	struct intel_connector *intel_connector = to_intel_connector(connector);
		2902	struct drm_device *dev = connector->dev;
2330	Serge	2903	int ret;
		2904
		2905	/* We should parse the EDID data and find out if it has an audio sink
		2906	*/
		2907
2342	Serge	2908	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3243	Serge	2909	if (ret)
2330	Serge	2910	return ret;
		2911
3243	Serge	2912	/* if eDP has no EDID, fall back to fixed mode */
		2913	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2330	Serge	2914	struct drm_display_mode *mode;
3243	Serge	2915	mode = drm_mode_duplicate(dev,
		2916	intel_connector->panel.fixed_mode);
		2917	if (mode) {
2330	Serge	2918	drm_mode_probed_add(connector, mode);
		2919	return 1;
		2920	}
		2921	}
		2922	return 0;
		2923	}
		2924
3243	Serge	2925	static bool
		2926	intel_dp_detect_audio(struct drm_connector *connector)
		2927	{
		2928	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2929	struct edid *edid;
		2930	bool has_audio = false;
2330	Serge	2931
3243	Serge	2932	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
		2933	if (edid) {
		2934	has_audio = drm_detect_monitor_audio(edid);
		2935	kfree(edid);
		2936	}
2330	Serge	2937
3243	Serge	2938	return has_audio;
		2939	}
2330	Serge	2940
		2941	static int
		2942	intel_dp_set_property(struct drm_connector *connector,
		2943	struct drm_property *property,
		2944	uint64_t val)
		2945	{
		2946	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3243	Serge	2947	struct intel_connector *intel_connector = to_intel_connector(connector);
		2948	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
		2949	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2330	Serge	2950	int ret;
		2951
3243	Serge	2952	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	2953	if (ret)
		2954	return ret;
3480	Serge	2955
2330	Serge	2956	if (property == dev_priv->force_audio_property) {
		2957	int i = val;
		2958	bool has_audio;
		2959
		2960	if (i == intel_dp->force_audio)
		2961	return 0;
		2962
		2963	intel_dp->force_audio = i;
		2964
3031	serge	2965	if (i == HDMI_AUDIO_AUTO)
2330	Serge	2966	has_audio = intel_dp_detect_audio(connector);
		2967	else
3031	serge	2968	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	2969
		2970	if (has_audio == intel_dp->has_audio)
		2971	return 0;
		2972
		2973	intel_dp->has_audio = has_audio;
		2974	goto done;
		2975	}
		2976
		2977	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	2978	bool old_auto = intel_dp->color_range_auto;
		2979	uint32_t old_range = intel_dp->color_range;
		2980
3480	Serge	2981	switch (val) {
		2982	case INTEL_BROADCAST_RGB_AUTO:
		2983	intel_dp->color_range_auto = true;
		2984	break;
		2985	case INTEL_BROADCAST_RGB_FULL:
		2986	intel_dp->color_range_auto = false;
		2987	intel_dp->color_range = 0;
		2988	break;
		2989	case INTEL_BROADCAST_RGB_LIMITED:
		2990	intel_dp->color_range_auto = false;
		2991	intel_dp->color_range = DP_COLOR_RANGE_16_235;
		2992	break;
		2993	default:
		2994	return -EINVAL;
		2995	}
3746	Serge	2996
		2997	if (old_auto == intel_dp->color_range_auto &&
		2998	old_range == intel_dp->color_range)
		2999	return 0;
		3000
2330	Serge	3001	goto done;
		3002	}
		3003
3243	Serge	3004	if (is_edp(intel_dp) &&
		3005	property == connector->dev->mode_config.scaling_mode_property) {
		3006	if (val == DRM_MODE_SCALE_NONE) {
		3007	DRM_DEBUG_KMS("no scaling not supported\n");
		3008	return -EINVAL;
		3009	}
		3010
		3011	if (intel_connector->panel.fitting_mode == val) {
		3012	/* the eDP scaling property is not changed */
		3013	return 0;
		3014	}
		3015	intel_connector->panel.fitting_mode = val;
		3016
		3017	goto done;
		3018	}
		3019
2330	Serge	3020	return -EINVAL;
		3021
		3022	done:
3480	Serge	3023	if (intel_encoder->base.crtc)
		3024	intel_crtc_restore_mode(intel_encoder->base.crtc);
2330	Serge	3025
		3026	return 0;
		3027	}
		3028
		3029	static void
4104	Serge	3030	intel_dp_connector_destroy(struct drm_connector *connector)
2330	Serge	3031	{
3243	Serge	3032	struct intel_connector *intel_connector = to_intel_connector(connector);
2330	Serge	3033
3243	Serge	3034	if (!IS_ERR_OR_NULL(intel_connector->edid))
		3035	kfree(intel_connector->edid);
		3036
4104	Serge	3037	/* Can't call is_edp() since the encoder may have been destroyed
		3038	* already. */
		3039	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3243	Serge	3040	intel_panel_fini(&intel_connector->panel);
2330	Serge	3041
		3042	drm_sysfs_connector_remove(connector);
		3043	drm_connector_cleanup(connector);
		3044	kfree(connector);
		3045	}
		3046
3243	Serge	3047	void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3048	{
3243	Serge	3049	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		3050	struct intel_dp *intel_dp = &intel_dig_port->dp;
3480	Serge	3051	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2330	Serge	3052
3243	Serge	3053	i2c_del_adapter(&intel_dp->adapter);
2330	Serge	3054	drm_encoder_cleanup(encoder);
2342	Serge	3055	if (is_edp(intel_dp)) {
		3056	// cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3480	Serge	3057	mutex_lock(&dev->mode_config.mutex);
2342	Serge	3058	ironlake_panel_vdd_off_sync(intel_dp);
3480	Serge	3059	mutex_unlock(&dev->mode_config.mutex);
2342	Serge	3060	}
3243	Serge	3061	kfree(intel_dig_port);
2330	Serge	3062	}
		3063
		3064	static const struct drm_connector_funcs intel_dp_connector_funcs = {
3031	serge	3065	.dpms = intel_connector_dpms,
2330	Serge	3066	.detect = intel_dp_detect,
		3067	.fill_modes = drm_helper_probe_single_connector_modes,
		3068	.set_property = intel_dp_set_property,
4104	Serge	3069	.destroy = intel_dp_connector_destroy,
2330	Serge	3070	};
		3071
		3072	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
		3073	.get_modes = intel_dp_get_modes,
		3074	.mode_valid = intel_dp_mode_valid,
		3075	.best_encoder = intel_best_encoder,
		3076	};
		3077
		3078	static const struct drm_encoder_funcs intel_dp_enc_funcs = {
		3079	.destroy = intel_dp_encoder_destroy,
		3080	};
		3081
		3082	static void
		3083	intel_dp_hot_plug(struct intel_encoder *intel_encoder)
		3084	{
3243	Serge	3085	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2330	Serge	3086
		3087	intel_dp_check_link_status(intel_dp);
		3088	}
		3089
2327	Serge	3090	/* Return which DP Port should be selected for Transcoder DP control */
		3091	int
2342	Serge	3092	intel_trans_dp_port_sel(struct drm_crtc *crtc)
2327	Serge	3093	{
		3094	struct drm_device *dev = crtc->dev;
3243	Serge	3095	struct intel_encoder *intel_encoder;
		3096	struct intel_dp *intel_dp;
2327	Serge	3097
3243	Serge	3098	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		3099	intel_dp = enc_to_intel_dp(&intel_encoder->base);
2327	Serge	3100
3243	Serge	3101	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		3102	intel_encoder->type == INTEL_OUTPUT_EDP)
2327	Serge	3103	return intel_dp->output_reg;
		3104	}
		3105
		3106	return -1;
		3107	}
2330	Serge	3108
		3109	/* check the VBT to see whether the eDP is on DP-D port */
		3110	bool intel_dpd_is_edp(struct drm_device *dev)
		3111	{
		3112	struct drm_i915_private *dev_priv = dev->dev_private;
		3113	struct child_device_config *p_child;
		3114	int i;
		3115
4104	Serge	3116	if (!dev_priv->vbt.child_dev_num)
2330	Serge	3117	return false;
		3118
4104	Serge	3119	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		3120	p_child = dev_priv->vbt.child_dev + i;
2330	Serge	3121
		3122	if (p_child->dvo_port == PORT_IDPD &&
		3123	p_child->device_type == DEVICE_TYPE_eDP)
		3124	return true;
		3125	}
		3126	return false;
		3127	}
		3128
		3129	static void
		3130	intel_dp_add_properties(struct intel_dp intel_dp, struct drm_connector connector)
		3131	{
3243	Serge	3132	struct intel_connector *intel_connector = to_intel_connector(connector);
		3133
2330	Serge	3134	intel_attach_force_audio_property(connector);
		3135	intel_attach_broadcast_rgb_property(connector);
3480	Serge	3136	intel_dp->color_range_auto = true;
3243	Serge	3137
		3138	if (is_edp(intel_dp)) {
		3139	drm_mode_create_scaling_mode_property(connector->dev);
		3140	drm_object_attach_property(
		3141	&connector->base,
		3142	connector->dev->mode_config.scaling_mode_property,
		3143	DRM_MODE_SCALE_ASPECT);
		3144	intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
		3145	}
2330	Serge	3146	}
		3147
3243	Serge	3148	static void
		3149	intel_dp_init_panel_power_sequencer(struct drm_device *dev,
		3150	struct intel_dp *intel_dp,
		3151	struct edp_power_seq *out)
		3152	{
		3153	struct drm_i915_private *dev_priv = dev->dev_private;
		3154	struct edp_power_seq cur, vbt, spec, final;
		3155	u32 pp_on, pp_off, pp_div, pp;
3746	Serge	3156	int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3243	Serge	3157
3746	Serge	3158	if (HAS_PCH_SPLIT(dev)) {
		3159	pp_control_reg = PCH_PP_CONTROL;
		3160	pp_on_reg = PCH_PP_ON_DELAYS;
		3161	pp_off_reg = PCH_PP_OFF_DELAYS;
		3162	pp_div_reg = PCH_PP_DIVISOR;
		3163	} else {
		3164	pp_control_reg = PIPEA_PP_CONTROL;
		3165	pp_on_reg = PIPEA_PP_ON_DELAYS;
		3166	pp_off_reg = PIPEA_PP_OFF_DELAYS;
		3167	pp_div_reg = PIPEA_PP_DIVISOR;
		3168	}
		3169
3243	Serge	3170	/* Workaround: Need to write PP_CONTROL with the unlock key as
		3171	* the very first thing. */
3746	Serge	3172	pp = ironlake_get_pp_control(intel_dp);
		3173	I915_WRITE(pp_control_reg, pp);
3243	Serge	3174
3746	Serge	3175	pp_on = I915_READ(pp_on_reg);
		3176	pp_off = I915_READ(pp_off_reg);
		3177	pp_div = I915_READ(pp_div_reg);
3243	Serge	3178
		3179	/* Pull timing values out of registers */
		3180	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		3181	PANEL_POWER_UP_DELAY_SHIFT;
		3182
		3183	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		3184	PANEL_LIGHT_ON_DELAY_SHIFT;
		3185
		3186	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		3187	PANEL_LIGHT_OFF_DELAY_SHIFT;
		3188
		3189	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		3190	PANEL_POWER_DOWN_DELAY_SHIFT;
		3191
		3192	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		3193	PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
		3194
		3195	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		3196	cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
		3197
4104	Serge	3198	vbt = dev_priv->vbt.edp_pps;
3243	Serge	3199
		3200	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
		3201	* our hw here, which are all in 100usec. */
		3202	spec.t1_t3 = 210 * 10;
		3203	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
		3204	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
		3205	spec.t10 = 500 * 10;
		3206	/* This one is special and actually in units of 100ms, but zero
		3207	* based in the hw (so we need to add 100 ms). But the sw vbt
		3208	* table multiplies it with 1000 to make it in units of 100usec,
		3209	* too. */
		3210	spec.t11_t12 = (510 + 100) * 10;
		3211
		3212	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		3213	vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
		3214
		3215	/* Use the max of the register settings and vbt. If both are
		3216	* unset, fall back to the spec limits. */
		3217	#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
		3218	spec.field : \
		3219	max(cur.field, vbt.field))
		3220	assign_final(t1_t3);
		3221	assign_final(t8);
		3222	assign_final(t9);
		3223	assign_final(t10);
		3224	assign_final(t11_t12);
		3225	#undef assign_final
		3226
		3227	#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
		3228	intel_dp->panel_power_up_delay = get_delay(t1_t3);
		3229	intel_dp->backlight_on_delay = get_delay(t8);
		3230	intel_dp->backlight_off_delay = get_delay(t9);
		3231	intel_dp->panel_power_down_delay = get_delay(t10);
		3232	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
		3233	#undef get_delay
		3234
		3235	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		3236	intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		3237	intel_dp->panel_power_cycle_delay);
		3238
		3239	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		3240	intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
		3241
		3242	if (out)
		3243	*out = final;
		3244	}
		3245
		3246	static void
		3247	intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
		3248	struct intel_dp *intel_dp,
		3249	struct edp_power_seq *seq)
		3250	{
		3251	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	3252	u32 pp_on, pp_off, pp_div, port_sel = 0;
		3253	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
		3254	int pp_on_reg, pp_off_reg, pp_div_reg;
3243	Serge	3255
3746	Serge	3256	if (HAS_PCH_SPLIT(dev)) {
		3257	pp_on_reg = PCH_PP_ON_DELAYS;
		3258	pp_off_reg = PCH_PP_OFF_DELAYS;
		3259	pp_div_reg = PCH_PP_DIVISOR;
		3260	} else {
		3261	pp_on_reg = PIPEA_PP_ON_DELAYS;
		3262	pp_off_reg = PIPEA_PP_OFF_DELAYS;
		3263	pp_div_reg = PIPEA_PP_DIVISOR;
		3264	}
		3265
3243	Serge	3266	/* And finally store the new values in the power sequencer. */
		3267	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) \|
		3268	(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
		3269	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) \|
		3270	(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
		3271	/* Compute the divisor for the pp clock, simply match the Bspec
		3272	* formula. */
3746	Serge	3273	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3243	Serge	3274	pp_div \|= (DIV_ROUND_UP(seq->t11_t12, 1000)
		3275	<< PANEL_POWER_CYCLE_DELAY_SHIFT);
		3276
		3277	/* Haswell doesn't have any port selection bits for the panel
		3278	* power sequencer any more. */
4104	Serge	3279	if (IS_VALLEYVIEW(dev)) {
		3280	port_sel = I915_READ(pp_on_reg) & 0xc0000000;
		3281	} else if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)) {
		3282	if (dp_to_dig_port(intel_dp)->port == PORT_A)
3746	Serge	3283	port_sel = PANEL_POWER_PORT_DP_A;
3243	Serge	3284	else
3746	Serge	3285	port_sel = PANEL_POWER_PORT_DP_D;
3243	Serge	3286	}
		3287
3746	Serge	3288	pp_on \|= port_sel;
3243	Serge	3289
3746	Serge	3290	I915_WRITE(pp_on_reg, pp_on);
		3291	I915_WRITE(pp_off_reg, pp_off);
		3292	I915_WRITE(pp_div_reg, pp_div);
		3293
3243	Serge	3294	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3746	Serge	3295	I915_READ(pp_on_reg),
		3296	I915_READ(pp_off_reg),
		3297	I915_READ(pp_div_reg));
3243	Serge	3298	}
		3299
4104	Serge	3300	static bool intel_edp_init_connector(struct intel_dp *intel_dp,
		3301	struct intel_connector *intel_connector)
		3302	{
		3303	struct drm_connector *connector = &intel_connector->base;
		3304	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3305	struct drm_device *dev = intel_dig_port->base.base.dev;
		3306	struct drm_i915_private *dev_priv = dev->dev_private;
		3307	struct drm_display_mode *fixed_mode = NULL;
		3308	struct edp_power_seq power_seq = { 0 };
		3309	bool has_dpcd;
		3310	struct drm_display_mode *scan;
		3311	struct edid *edid;
		3312
		3313	if (!is_edp(intel_dp))
		3314	return true;
		3315
		3316	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		3317
		3318	/* Cache DPCD and EDID for edp. */
		3319	ironlake_edp_panel_vdd_on(intel_dp);
		3320	has_dpcd = intel_dp_get_dpcd(intel_dp);
		3321	ironlake_edp_panel_vdd_off(intel_dp, false);
		3322
		3323	if (has_dpcd) {
		3324	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		3325	dev_priv->no_aux_handshake =
		3326	intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
		3327	DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		3328	} else {
		3329	/* if this fails, presume the device is a ghost */
		3330	DRM_INFO("failed to retrieve link info, disabling eDP\n");
		3331	return false;
		3332	}
		3333
		3334	/* We now know it's not a ghost, init power sequence regs. */
		3335	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
		3336	&power_seq);
		3337
		3338	ironlake_edp_panel_vdd_on(intel_dp);
		3339	edid = drm_get_edid(connector, &intel_dp->adapter);
		3340	if (edid) {
		3341	if (drm_add_edid_modes(connector, edid)) {
		3342	drm_mode_connector_update_edid_property(connector,
		3343	edid);
		3344	drm_edid_to_eld(connector, edid);
		3345	} else {
		3346	kfree(edid);
		3347	edid = ERR_PTR(-EINVAL);
		3348	}
		3349	} else {
		3350	edid = ERR_PTR(-ENOENT);
		3351	}
		3352	intel_connector->edid = edid;
		3353
		3354	/* prefer fixed mode from EDID if available */
		3355	list_for_each_entry(scan, &connector->probed_modes, head) {
		3356	if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
		3357	fixed_mode = drm_mode_duplicate(dev, scan);
		3358	break;
		3359	}
		3360	}
		3361
		3362	/* fallback to VBT if available for eDP */
		3363	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		3364	fixed_mode = drm_mode_duplicate(dev,
		3365	dev_priv->vbt.lfp_lvds_vbt_mode);
		3366	if (fixed_mode)
		3367	fixed_mode->type \|= DRM_MODE_TYPE_PREFERRED;
		3368	}
		3369
		3370	ironlake_edp_panel_vdd_off(intel_dp, false);
		3371
		3372	intel_panel_init(&intel_connector->panel, fixed_mode);
		3373	intel_panel_setup_backlight(connector);
		3374
		3375	return true;
		3376	}
		3377
		3378	bool
3243	Serge	3379	intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
		3380	struct intel_connector *intel_connector)
2330	Serge	3381	{
3243	Serge	3382	struct drm_connector *connector = &intel_connector->base;
		3383	struct intel_dp *intel_dp = &intel_dig_port->dp;
		3384	struct intel_encoder *intel_encoder = &intel_dig_port->base;
		3385	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	3386	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3387	enum port port = intel_dig_port->port;
2330	Serge	3388	const char *name = NULL;
4104	Serge	3389	int type, error;
2330	Serge	3390
3031	serge	3391	/* Preserve the current hw state. */
		3392	intel_dp->DP = I915_READ(intel_dp->output_reg);
3243	Serge	3393	intel_dp->attached_connector = intel_connector;
2330	Serge	3394
4104	Serge	3395	type = DRM_MODE_CONNECTOR_DisplayPort;
3243	Serge	3396	/*
		3397	* FIXME : We need to initialize built-in panels before external panels.
		3398	* For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
		3399	*/
4104	Serge	3400	switch (port) {
		3401	case PORT_A:
2330	Serge	3402	type = DRM_MODE_CONNECTOR_eDP;
4104	Serge	3403	break;
		3404	case PORT_C:
		3405	if (IS_VALLEYVIEW(dev))
3243	Serge	3406	type = DRM_MODE_CONNECTOR_eDP;
4104	Serge	3407	break;
		3408	case PORT_D:
		3409	if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
		3410	type = DRM_MODE_CONNECTOR_eDP;
		3411	break;
		3412	default: /* silence GCC warning */
		3413	break;
2330	Serge	3414	}
		3415
4104	Serge	3416	/*
		3417	* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
		3418	* for DP the encoder type can be set by the caller to
		3419	* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
		3420	*/
		3421	if (type == DRM_MODE_CONNECTOR_eDP)
		3422	intel_encoder->type = INTEL_OUTPUT_EDP;
		3423
		3424	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
		3425	type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
		3426	port_name(port));
		3427
2330	Serge	3428	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
		3429	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
		3430
		3431	connector->interlace_allowed = true;
		3432	connector->doublescan_allowed = 0;
		3433
3243	Serge	3434	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
		3435	ironlake_panel_vdd_work);
2330	Serge	3436
		3437	intel_connector_attach_encoder(intel_connector, intel_encoder);
		3438	drm_sysfs_connector_add(connector);
		3439
3480	Serge	3440	if (HAS_DDI(dev))
3243	Serge	3441	intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
		3442	else
3031	serge	3443	intel_connector->get_hw_state = intel_connector_get_hw_state;
		3444
3746	Serge	3445	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
		3446	if (HAS_DDI(dev)) {
		3447	switch (intel_dig_port->port) {
		3448	case PORT_A:
		3449	intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
		3450	break;
		3451	case PORT_B:
		3452	intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
		3453	break;
		3454	case PORT_C:
		3455	intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
		3456	break;
		3457	case PORT_D:
		3458	intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
		3459	break;
		3460	default:
		3461	BUG();
		3462	}
		3463	}
3243	Serge	3464
2330	Serge	3465	/* Set up the DDC bus. */
3031	serge	3466	switch (port) {
		3467	case PORT_A:
3746	Serge	3468	intel_encoder->hpd_pin = HPD_PORT_A;
2330	Serge	3469	name = "DPDDC-A";
		3470	break;
3031	serge	3471	case PORT_B:
3746	Serge	3472	intel_encoder->hpd_pin = HPD_PORT_B;
2330	Serge	3473	name = "DPDDC-B";
		3474	break;
3031	serge	3475	case PORT_C:
3746	Serge	3476	intel_encoder->hpd_pin = HPD_PORT_C;
2330	Serge	3477	name = "DPDDC-C";
		3478	break;
3031	serge	3479	case PORT_D:
3746	Serge	3480	intel_encoder->hpd_pin = HPD_PORT_D;
2330	Serge	3481	name = "DPDDC-D";
		3482	break;
3031	serge	3483	default:
3746	Serge	3484	BUG();
2330	Serge	3485	}
		3486
4104	Serge	3487	error = intel_dp_i2c_init(intel_dp, intel_connector, name);
		3488	WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
		3489	error, port_name(port));
2330	Serge	3490
4104	Serge	3491	intel_dp->psr_setup_done = false;
3031	serge	3492
4104	Serge	3493	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
		3494	i2c_del_adapter(&intel_dp->adapter);
3031	serge	3495	if (is_edp(intel_dp)) {
4104	Serge	3496	// cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		3497	mutex_lock(&dev->mode_config.mutex);
		3498	ironlake_panel_vdd_off_sync(intel_dp);
		3499	mutex_unlock(&dev->mode_config.mutex);
2330	Serge	3500	}
4104	Serge	3501	drm_sysfs_connector_remove(connector);
		3502	drm_connector_cleanup(connector);
		3503	return false;
2330	Serge	3504	}
		3505
		3506	intel_dp_add_properties(intel_dp, connector);
		3507
		3508	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		3509	* 0xd. Failure to do so will result in spurious interrupts being
		3510	* generated on the port when a cable is not attached.
		3511	*/
		3512	if (IS_G4X(dev) && !IS_GM45(dev)) {
		3513	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		3514	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		3515	}
4104	Serge	3516
		3517	return true;
2330	Serge	3518	}
3243	Serge	3519
		3520	void
		3521	intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
		3522	{
		3523	struct intel_digital_port *intel_dig_port;
		3524	struct intel_encoder *intel_encoder;
		3525	struct drm_encoder *encoder;
		3526	struct intel_connector *intel_connector;
		3527
		3528	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
		3529	if (!intel_dig_port)
		3530	return;
		3531
		3532	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
		3533	if (!intel_connector) {
		3534	kfree(intel_dig_port);
		3535	return;
		3536	}
		3537
		3538	intel_encoder = &intel_dig_port->base;
		3539	encoder = &intel_encoder->base;
		3540
		3541	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
		3542	DRM_MODE_ENCODER_TMDS);
		3543
3746	Serge	3544	intel_encoder->compute_config = intel_dp_compute_config;
4104	Serge	3545	intel_encoder->mode_set = intel_dp_mode_set;
3243	Serge	3546	intel_encoder->disable = intel_disable_dp;
		3547	intel_encoder->post_disable = intel_post_disable_dp;
		3548	intel_encoder->get_hw_state = intel_dp_get_hw_state;
4104	Serge	3549	intel_encoder->get_config = intel_dp_get_config;
		3550	if (IS_VALLEYVIEW(dev)) {
		3551	intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
		3552	intel_encoder->pre_enable = vlv_pre_enable_dp;
		3553	intel_encoder->enable = vlv_enable_dp;
		3554	} else {
		3555	intel_encoder->pre_enable = intel_pre_enable_dp;
		3556	intel_encoder->enable = intel_enable_dp;
		3557	}
3243	Serge	3558
		3559	intel_dig_port->port = port;
		3560	intel_dig_port->dp.output_reg = output_reg;
		3561
		3562	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		3563	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
		3564	intel_encoder->cloneable = false;
		3565	intel_encoder->hot_plug = intel_dp_hot_plug;
		3566
4104	Serge	3567	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		3568	drm_encoder_cleanup(encoder);
		3569	kfree(intel_dig_port);
		3570	kfree(intel_connector);
		3571	}
3243	Serge	3572	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c – Rev 4280