WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_dp.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Keith Packard
		25	*
		26	*/
		27
		28	#include
2330	Serge	29	#include
2327	Serge	30	#include "drmP.h"
		31	#include "drm.h"
		32	#include "drm_crtc.h"
		33	#include "drm_crtc_helper.h"
		34	#include "intel_drv.h"
2330	Serge	35	#include "i915_drm.h"
2327	Serge	36	#include "i915_drv.h"
		37	#include "drm_dp_helper.h"
		38
2342	Serge	39	#define DP_RECEIVER_CAP_SIZE 0xf
2327	Serge	40	#define DP_LINK_STATUS_SIZE 6
		41	#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
		42
		43	#define DP_LINK_CONFIGURATION_SIZE 9
		44
		45	struct intel_dp {
		46	struct intel_encoder base;
		47	uint32_t output_reg;
		48	uint32_t DP;
		49	uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
		50	bool has_audio;
		51	int force_audio;
		52	uint32_t color_range;
		53	int dpms_mode;
		54	uint8_t link_bw;
		55	uint8_t lane_count;
2342	Serge	56	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
2327	Serge	57	struct i2c_adapter adapter;
		58	struct i2c_algo_dp_aux_data algo;
		59	bool is_pch_edp;
		60	uint8_t train_set[4];
2342	Serge	61	int panel_power_up_delay;
		62	int panel_power_down_delay;
		63	int panel_power_cycle_delay;
		64	int backlight_on_delay;
		65	int backlight_off_delay;
		66	struct drm_display_mode panel_fixed_mode; / for eDP */
		67	bool want_panel_vdd;
2327	Serge	68	};
		69
		70	/**
		71	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
		72	* @intel_dp: DP struct
		73	*
		74	* If a CPU or PCH DP output is attached to an eDP panel, this function
		75	* will return true, and false otherwise.
		76	*/
		77	static bool is_edp(struct intel_dp *intel_dp)
		78	{
		79	return intel_dp->base.type == INTEL_OUTPUT_EDP;
		80	}
		81
		82	/**
		83	* is_pch_edp - is the port on the PCH and attached to an eDP panel?
		84	* @intel_dp: DP struct
		85	*
		86	* Returns true if the given DP struct corresponds to a PCH DP port attached
		87	* to an eDP panel, false otherwise. Helpful for determining whether we
		88	* may need FDI resources for a given DP output or not.
		89	*/
		90	static bool is_pch_edp(struct intel_dp *intel_dp)
		91	{
		92	return intel_dp->is_pch_edp;
		93	}
		94
2342	Serge	95	/**
		96	* is_cpu_edp - is the port on the CPU and attached to an eDP panel?
		97	* @intel_dp: DP struct
		98	*
		99	* Returns true if the given DP struct corresponds to a CPU eDP port.
		100	*/
		101	static bool is_cpu_edp(struct intel_dp *intel_dp)
		102	{
		103	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
		104	}
		105
2327	Serge	106	static struct intel_dp enc_to_intel_dp(struct drm_encoder encoder)
		107	{
		108	return container_of(encoder, struct intel_dp, base.base);
		109	}
		110
2330	Serge	111	static struct intel_dp intel_attached_dp(struct drm_connector connector)
		112	{
		113	return container_of(intel_attached_encoder(connector),
		114	struct intel_dp, base);
		115	}
2327	Serge	116
		117	/**
		118	* intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
		119	* @encoder: DRM encoder
		120	*
		121	* Return true if @encoder corresponds to a PCH attached eDP panel. Needed
		122	* by intel_display.c.
		123	*/
		124	bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
		125	{
		126	struct intel_dp *intel_dp;
		127
		128	if (!encoder)
		129	return false;
		130
		131	intel_dp = enc_to_intel_dp(encoder);
		132
		133	return is_pch_edp(intel_dp);
		134	}
		135
2330	Serge	136	static void intel_dp_start_link_train(struct intel_dp *intel_dp);
		137	static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
		138	static void intel_dp_link_down(struct intel_dp *intel_dp);
		139
2327	Serge	140	void
2342	Serge	141	intel_edp_link_config(struct intel_encoder *intel_encoder,
2327	Serge	142	int lane_num, int link_bw)
		143	{
		144	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		145
		146	*lane_num = intel_dp->lane_count;
		147	if (intel_dp->link_bw == DP_LINK_BW_1_62)
		148	*link_bw = 162000;
		149	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
		150	*link_bw = 270000;
		151	}
		152
2330	Serge	153	static int
		154	intel_dp_max_lane_count(struct intel_dp *intel_dp)
		155	{
2342	Serge	156	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
2330	Serge	157	switch (max_lane_count) {
		158	case 1: case 2: case 4:
		159	break;
		160	default:
		161	max_lane_count = 4;
		162	}
		163	return max_lane_count;
		164	}
2327	Serge	165
2330	Serge	166	static int
		167	intel_dp_max_link_bw(struct intel_dp *intel_dp)
		168	{
		169	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
2327	Serge	170
2330	Serge	171	switch (max_link_bw) {
		172	case DP_LINK_BW_1_62:
		173	case DP_LINK_BW_2_7:
		174	break;
		175	default:
		176	max_link_bw = DP_LINK_BW_1_62;
		177	break;
		178	}
		179	return max_link_bw;
		180	}
2327	Serge	181
2330	Serge	182	static int
		183	intel_dp_link_clock(uint8_t link_bw)
		184	{
		185	if (link_bw == DP_LINK_BW_2_7)
		186	return 270000;
		187	else
		188	return 162000;
		189	}
2327	Serge	190
2342	Serge	191	/*
		192	* The units on the numbers in the next two are... bizarre. Examples will
		193	* make it clearer; this one parallels an example in the eDP spec.
		194	*
		195	* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
		196	*
		197	* 270000 * 1 * 8 / 10 == 216000
		198	*
		199	* The actual data capacity of that configuration is 2.16Gbit/s, so the
		200	* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
		201	* or equivalently, kilopixels per second - so for 1680x1050R it'd be
		202	* 119000. At 18bpp that's 2142000 kilobits per second.
		203	*
		204	* Thus the strange-looking division by 10 in intel_dp_link_required, to
		205	* get the result in decakilobits instead of kilobits.
		206	*/
		207
2330	Serge	208	static int
2351	Serge	209	intel_dp_link_required(int pixel_clock, int bpp)
2330	Serge	210	{
2342	Serge	211	return (pixel_clock * bpp + 9) / 10;
2330	Serge	212	}
2327	Serge	213
2330	Serge	214	static int
		215	intel_dp_max_data_rate(int max_link_clock, int max_lanes)
		216	{
		217	return (max_link_clock * max_lanes * 8) / 10;
		218	}
2327	Serge	219
2330	Serge	220	static int
		221	intel_dp_mode_valid(struct drm_connector *connector,
		222	struct drm_display_mode *mode)
		223	{
		224	struct intel_dp *intel_dp = intel_attached_dp(connector);
		225	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
		226	int max_lanes = intel_dp_max_lane_count(intel_dp);
2342	Serge	227	int max_rate, mode_rate;
2327	Serge	228
2342	Serge	229	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		230	if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
2330	Serge	231	return MODE_PANEL;
2327	Serge	232
2342	Serge	233	if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
2330	Serge	234	return MODE_PANEL;
		235	}
2327	Serge	236
2351	Serge	237	mode_rate = intel_dp_link_required(mode->clock, 24);
2342	Serge	238	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
		239
		240	if (mode_rate > max_rate) {
2351	Serge	241	mode_rate = intel_dp_link_required(mode->clock, 18);
2342	Serge	242	if (mode_rate > max_rate)
2330	Serge	243	return MODE_CLOCK_HIGH;
2342	Serge	244	else
		245	mode->private_flags \|= INTEL_MODE_DP_FORCE_6BPC;
		246	}
2327	Serge	247
2330	Serge	248	if (mode->clock < 10000)
		249	return MODE_CLOCK_LOW;
		250
		251	return MODE_OK;
		252	}
		253
		254	static uint32_t
		255	pack_aux(uint8_t *src, int src_bytes)
		256	{
		257	int i;
		258	uint32_t v = 0;
		259
		260	if (src_bytes > 4)
		261	src_bytes = 4;
		262	for (i = 0; i < src_bytes; i++)
		263	v \|= ((uint32_t) src[i]) << ((3-i) * 8);
		264	return v;
		265	}
		266
		267	static void
		268	unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
		269	{
		270	int i;
		271	if (dst_bytes > 4)
		272	dst_bytes = 4;
		273	for (i = 0; i < dst_bytes; i++)
		274	dst[i] = src >> ((3-i) * 8);
		275	}
		276
		277	/* hrawclock is 1/4 the FSB frequency */
		278	static int
		279	intel_hrawclk(struct drm_device *dev)
		280	{
		281	struct drm_i915_private *dev_priv = dev->dev_private;
		282	uint32_t clkcfg;
		283
		284	clkcfg = I915_READ(CLKCFG);
		285	switch (clkcfg & CLKCFG_FSB_MASK) {
		286	case CLKCFG_FSB_400:
		287	return 100;
		288	case CLKCFG_FSB_533:
		289	return 133;
		290	case CLKCFG_FSB_667:
		291	return 166;
		292	case CLKCFG_FSB_800:
		293	return 200;
		294	case CLKCFG_FSB_1067:
		295	return 266;
		296	case CLKCFG_FSB_1333:
		297	return 333;
		298	/* these two are just a guess; one of them might be right */
		299	case CLKCFG_FSB_1600:
		300	case CLKCFG_FSB_1600_ALT:
		301	return 400;
		302	default:
		303	return 133;
		304	}
		305	}
		306
2342	Serge	307	static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
		308	{
		309	struct drm_device *dev = intel_dp->base.base.dev;
		310	struct drm_i915_private *dev_priv = dev->dev_private;
		311
		312	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
		313	}
		314
		315	static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
		316	{
		317	struct drm_device *dev = intel_dp->base.base.dev;
		318	struct drm_i915_private *dev_priv = dev->dev_private;
		319
		320	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
		321	}
		322
		323	static void
		324	intel_dp_check_edp(struct intel_dp *intel_dp)
		325	{
		326	struct drm_device *dev = intel_dp->base.base.dev;
		327	struct drm_i915_private *dev_priv = dev->dev_private;
		328
		329	if (!is_edp(intel_dp))
		330	return;
		331	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
		332	WARN(1, "eDP powered off while attempting aux channel communication.\n");
		333	DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
		334	I915_READ(PCH_PP_STATUS),
		335	I915_READ(PCH_PP_CONTROL));
		336	}
		337	}
		338
2330	Serge	339	static int
		340	intel_dp_aux_ch(struct intel_dp *intel_dp,
		341	uint8_t *send, int send_bytes,
		342	uint8_t *recv, int recv_size)
		343	{
		344	uint32_t output_reg = intel_dp->output_reg;
		345	struct drm_device *dev = intel_dp->base.base.dev;
		346	struct drm_i915_private *dev_priv = dev->dev_private;
		347	uint32_t ch_ctl = output_reg + 0x10;
		348	uint32_t ch_data = ch_ctl + 4;
		349	int i;
		350	int recv_bytes;
		351	uint32_t status;
		352	uint32_t aux_clock_divider;
		353	int try, precharge;
		354
2342	Serge	355	intel_dp_check_edp(intel_dp);
2330	Serge	356	/* The clock divider is based off the hrawclk,
		357	* and would like to run at 2MHz. So, take the
		358	* hrawclk value and divide by 2 and use that
		359	*
		360	* Note that PCH attached eDP panels should use a 125MHz input
		361	* clock divider.
		362	*/
2342	Serge	363	if (is_cpu_edp(intel_dp)) {
		364	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
		365	aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
2330	Serge	366	else
		367	aux_clock_divider = 225; /* eDP input clock at 450Mhz */
		368	} else if (HAS_PCH_SPLIT(dev))
		369	aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
		370	else
		371	aux_clock_divider = intel_hrawclk(dev) / 2;
		372
		373	if (IS_GEN6(dev))
		374	precharge = 3;
		375	else
		376	precharge = 5;
		377
		378	/* Try to wait for any previous AUX channel activity */
		379	for (try = 0; try < 3; try++) {
		380	status = I915_READ(ch_ctl);
		381	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		382	break;
		383	msleep(1);
		384	}
		385
		386	if (try == 3) {
		387	WARN(1, "dp_aux_ch not started status 0x%08x\n",
		388	I915_READ(ch_ctl));
		389	return -EBUSY;
		390	}
		391
		392	/* Must try at least 3 times according to DP spec */
		393	for (try = 0; try < 5; try++) {
		394	/* Load the send data into the aux channel data registers */
		395	for (i = 0; i < send_bytes; i += 4)
		396	I915_WRITE(ch_data + i,
		397	pack_aux(send + i, send_bytes - i));
		398
		399	/* Send the command and wait for it to complete */
		400	I915_WRITE(ch_ctl,
		401	DP_AUX_CH_CTL_SEND_BUSY \|
		402	DP_AUX_CH_CTL_TIME_OUT_400us \|
		403	(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		404	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		405	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) \|
		406	DP_AUX_CH_CTL_DONE \|
		407	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		408	DP_AUX_CH_CTL_RECEIVE_ERROR);
		409	for (;;) {
		410	status = I915_READ(ch_ctl);
		411	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		412	break;
		413	udelay(100);
		414	}
		415
		416	/* Clear done status and any errors */
		417	I915_WRITE(ch_ctl,
		418	status \|
		419	DP_AUX_CH_CTL_DONE \|
		420	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		421	DP_AUX_CH_CTL_RECEIVE_ERROR);
		422	if (status & DP_AUX_CH_CTL_DONE)
		423	break;
		424	}
		425
		426	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		427	DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
		428	return -EBUSY;
		429	}
		430
		431	/* Check for timeout or receive error.
		432	* Timeouts occur when the sink is not connected
		433	*/
		434	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
		435	DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
		436	return -EIO;
		437	}
		438
		439	/* Timeouts occur when the device isn't connected, so they're
		440	* "normal" -- don't fill the kernel log with these */
		441	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
		442	DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
		443	return -ETIMEDOUT;
		444	}
		445
		446	/* Unload any bytes sent back from the other side */
		447	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		448	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
		449	if (recv_bytes > recv_size)
		450	recv_bytes = recv_size;
		451
		452	for (i = 0; i < recv_bytes; i += 4)
		453	unpack_aux(I915_READ(ch_data + i),
		454	recv + i, recv_bytes - i);
		455
		456	return recv_bytes;
		457	}
		458
		459	/* Write data to the aux channel in native mode */
		460	static int
		461	intel_dp_aux_native_write(struct intel_dp *intel_dp,
		462	uint16_t address, uint8_t *send, int send_bytes)
		463	{
		464	int ret;
		465	uint8_t msg[20];
		466	int msg_bytes;
		467	uint8_t ack;
		468
2342	Serge	469	intel_dp_check_edp(intel_dp);
2330	Serge	470	if (send_bytes > 16)
		471	return -1;
		472	msg[0] = AUX_NATIVE_WRITE << 4;
		473	msg[1] = address >> 8;
		474	msg[2] = address & 0xff;
		475	msg[3] = send_bytes - 1;
		476	memcpy(&msg[4], send, send_bytes);
		477	msg_bytes = send_bytes + 4;
		478	for (;;) {
		479	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
		480	if (ret < 0)
		481	return ret;
		482	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		483	break;
		484	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		485	udelay(100);
		486	else
		487	return -EIO;
		488	}
		489	return send_bytes;
		490	}
		491
		492	/* Write a single byte to the aux channel in native mode */
		493	static int
		494	intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
		495	uint16_t address, uint8_t byte)
		496	{
		497	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
		498	}
		499
		500	/* read bytes from a native aux channel */
		501	static int
		502	intel_dp_aux_native_read(struct intel_dp *intel_dp,
		503	uint16_t address, uint8_t *recv, int recv_bytes)
		504	{
		505	uint8_t msg[4];
		506	int msg_bytes;
		507	uint8_t reply[20];
		508	int reply_bytes;
		509	uint8_t ack;
		510	int ret;
		511
2342	Serge	512	intel_dp_check_edp(intel_dp);
2330	Serge	513	msg[0] = AUX_NATIVE_READ << 4;
		514	msg[1] = address >> 8;
		515	msg[2] = address & 0xff;
		516	msg[3] = recv_bytes - 1;
		517
		518	msg_bytes = 4;
		519	reply_bytes = recv_bytes + 1;
		520
		521	for (;;) {
		522	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
		523	reply, reply_bytes);
		524	if (ret == 0)
		525	return -EPROTO;
		526	if (ret < 0)
		527	return ret;
		528	ack = reply[0];
		529	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
		530	memcpy(recv, reply + 1, ret - 1);
		531	return ret - 1;
		532	}
		533	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		534	udelay(100);
		535	else
		536	return -EIO;
		537	}
		538	}
		539
		540	static int
		541	intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		542	uint8_t write_byte, uint8_t *read_byte)
		543	{
		544	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
		545	struct intel_dp *intel_dp = container_of(adapter,
		546	struct intel_dp,
		547	adapter);
		548	uint16_t address = algo_data->address;
		549	uint8_t msg[5];
		550	uint8_t reply[2];
		551	unsigned retry;
		552	int msg_bytes;
		553	int reply_bytes;
		554	int ret;
		555
2342	Serge	556	intel_dp_check_edp(intel_dp);
2330	Serge	557	/* Set up the command byte */
		558	if (mode & MODE_I2C_READ)
		559	msg[0] = AUX_I2C_READ << 4;
		560	else
		561	msg[0] = AUX_I2C_WRITE << 4;
		562
		563	if (!(mode & MODE_I2C_STOP))
		564	msg[0] \|= AUX_I2C_MOT << 4;
		565
		566	msg[1] = address >> 8;
		567	msg[2] = address;
		568
		569	switch (mode) {
		570	case MODE_I2C_WRITE:
		571	msg[3] = 0;
		572	msg[4] = write_byte;
		573	msg_bytes = 5;
		574	reply_bytes = 1;
		575	break;
		576	case MODE_I2C_READ:
		577	msg[3] = 0;
		578	msg_bytes = 4;
		579	reply_bytes = 2;
		580	break;
		581	default:
		582	msg_bytes = 3;
		583	reply_bytes = 1;
		584	break;
		585	}
		586
		587	for (retry = 0; retry < 5; retry++) {
		588	ret = intel_dp_aux_ch(intel_dp,
		589	msg, msg_bytes,
		590	reply, reply_bytes);
		591	if (ret < 0) {
		592	DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
		593	return ret;
		594	}
		595
		596	switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		597	case AUX_NATIVE_REPLY_ACK:
		598	/* I2C-over-AUX Reply field is only valid
		599	* when paired with AUX ACK.
		600	*/
		601	break;
		602	case AUX_NATIVE_REPLY_NACK:
		603	DRM_DEBUG_KMS("aux_ch native nack\n");
		604	return -EREMOTEIO;
		605	case AUX_NATIVE_REPLY_DEFER:
		606	udelay(100);
		607	continue;
		608	default:
		609	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
		610	reply[0]);
		611	return -EREMOTEIO;
		612	}
		613
		614	switch (reply[0] & AUX_I2C_REPLY_MASK) {
		615	case AUX_I2C_REPLY_ACK:
		616	if (mode == MODE_I2C_READ) {
		617	*read_byte = reply[1];
		618	}
		619	return reply_bytes - 1;
		620	case AUX_I2C_REPLY_NACK:
		621	DRM_DEBUG_KMS("aux_i2c nack\n");
		622	return -EREMOTEIO;
		623	case AUX_I2C_REPLY_DEFER:
		624	DRM_DEBUG_KMS("aux_i2c defer\n");
		625	udelay(100);
		626	break;
		627	default:
		628	DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
		629	return -EREMOTEIO;
		630	}
		631	}
		632
		633	DRM_ERROR("too many retries, giving up\n");
		634	return -EREMOTEIO;
		635	}
		636
2342	Serge	637	static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
		638	static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
		639
2330	Serge	640	static int
		641	intel_dp_i2c_init(struct intel_dp *intel_dp,
		642	struct intel_connector intel_connector, const char name)
		643	{
2342	Serge	644	int ret;
		645
2330	Serge	646	DRM_DEBUG_KMS("i2c_init %s\n", name);
		647	intel_dp->algo.running = false;
		648	intel_dp->algo.address = 0;
		649	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
		650
2342	Serge	651	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
2330	Serge	652	// intel_dp->adapter.owner = THIS_MODULE;
		653	intel_dp->adapter.class = I2C_CLASS_DDC;
2342	Serge	654	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
2330	Serge	655	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
		656	intel_dp->adapter.algo_data = &intel_dp->algo;
		657	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
		658
2342	Serge	659	ironlake_edp_panel_vdd_on(intel_dp);
		660	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
		661	ironlake_edp_panel_vdd_off(intel_dp, false);
		662	return ret;
2330	Serge	663	}
		664
		665	static bool
		666	intel_dp_mode_fixup(struct drm_encoder encoder, struct drm_display_mode mode,
		667	struct drm_display_mode *adjusted_mode)
		668	{
		669	struct drm_device *dev = encoder->dev;
		670	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		671	int lane_count, clock;
		672	int max_lane_count = intel_dp_max_lane_count(intel_dp);
		673	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
2351	Serge	674	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
2330	Serge	675	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
		676
2342	Serge	677	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		678	intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
2330	Serge	679	intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
		680	mode, adjusted_mode);
		681	/*
		682	* the mode->clock is used to calculate the Data&Link M/N
		683	* of the pipe. For the eDP the fixed clock should be used.
		684	*/
2342	Serge	685	mode->clock = intel_dp->panel_fixed_mode->clock;
2330	Serge	686	}
		687
		688	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		689	for (clock = 0; clock <= max_clock; clock++) {
		690	int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
		691
2351	Serge	692	if (intel_dp_link_required(mode->clock, bpp)
2330	Serge	693	<= link_avail) {
		694	intel_dp->link_bw = bws[clock];
		695	intel_dp->lane_count = lane_count;
		696	adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
		697	DRM_DEBUG_KMS("Display port link bw %02x lane "
		698	"count %d clock %d\n",
		699	intel_dp->link_bw, intel_dp->lane_count,
		700	adjusted_mode->clock);
		701	return true;
		702	}
		703	}
		704	}
		705
		706	return false;
		707	}
		708
2327	Serge	709	struct intel_dp_m_n {
		710	uint32_t tu;
		711	uint32_t gmch_m;
		712	uint32_t gmch_n;
		713	uint32_t link_m;
		714	uint32_t link_n;
		715	};
		716
		717	static void
		718	intel_reduce_ratio(uint32_t num, uint32_t den)
		719	{
		720	while (num > 0xffffff \|\| den > 0xffffff) {
		721	*num >>= 1;
		722	*den >>= 1;
		723	}
		724	}
		725
		726	static void
		727	intel_dp_compute_m_n(int bpp,
		728	int nlanes,
		729	int pixel_clock,
		730	int link_clock,
		731	struct intel_dp_m_n *m_n)
		732	{
		733	m_n->tu = 64;
		734	m_n->gmch_m = (pixel_clock * bpp) >> 3;
		735	m_n->gmch_n = link_clock * nlanes;
		736	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		737	m_n->link_m = pixel_clock;
		738	m_n->link_n = link_clock;
		739	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
		740	}
		741
		742	void
		743	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
		744	struct drm_display_mode *adjusted_mode)
		745	{
		746	struct drm_device *dev = crtc->dev;
		747	struct drm_mode_config *mode_config = &dev->mode_config;
		748	struct drm_encoder *encoder;
		749	struct drm_i915_private *dev_priv = dev->dev_private;
		750	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		751	int lane_count = 4;
		752	struct intel_dp_m_n m_n;
		753	int pipe = intel_crtc->pipe;
		754
		755	/*
		756	* Find the lane count in the intel_encoder private
		757	*/
		758	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		759	struct intel_dp *intel_dp;
		760
		761	if (encoder->crtc != crtc)
		762	continue;
		763
		764	intel_dp = enc_to_intel_dp(encoder);
2342	Serge	765	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT \|\|
		766	intel_dp->base.type == INTEL_OUTPUT_EDP)
		767	{
2327	Serge	768	lane_count = intel_dp->lane_count;
		769	break;
		770	}
		771	}
		772
		773	/*
		774	* Compute the GMCH and Link ratios. The '3' here is
		775	* the number of bytes_per_pixel post-LUT, which we always
		776	* set up for 8-bits of R/G/B, or 3 bytes total.
		777	*/
		778	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
		779	mode->clock, adjusted_mode->clock, &m_n);
		780
		781	if (HAS_PCH_SPLIT(dev)) {
		782	I915_WRITE(TRANSDATA_M1(pipe),
		783	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		784	m_n.gmch_m);
		785	I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		786	I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		787	I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
		788	} else {
		789	I915_WRITE(PIPE_GMCH_DATA_M(pipe),
		790	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		791	m_n.gmch_m);
		792	I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		793	I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		794	I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
		795	}
		796	}
		797
2342	Serge	798	static void ironlake_edp_pll_on(struct drm_encoder *encoder);
		799	static void ironlake_edp_pll_off(struct drm_encoder *encoder);
		800
2330	Serge	801	static void
		802	intel_dp_mode_set(struct drm_encoder encoder, struct drm_display_mode mode,
		803	struct drm_display_mode *adjusted_mode)
		804	{
		805	struct drm_device *dev = encoder->dev;
2342	Serge	806	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	807	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		808	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		809	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	810
2342	Serge	811	/* Turn on the eDP PLL if needed */
		812	if (is_edp(intel_dp)) {
		813	if (!is_pch_edp(intel_dp))
		814	ironlake_edp_pll_on(encoder);
		815	else
		816	ironlake_edp_pll_off(encoder);
		817	}
2327	Serge	818
2342	Serge	819	/*
		820	* There are four kinds of DP registers:
		821	*
		822	* IBX PCH
		823	* SNB CPU
		824	* IVB CPU
		825	* CPT PCH
		826	*
		827	* IBX PCH and CPU are the same for almost everything,
		828	* except that the CPU DP PLL is configured in this
		829	* register
		830	*
		831	* CPT PCH is quite different, having many bits moved
		832	* to the TRANS_DP_CTL register instead. That
		833	* configuration happens (oddly) in ironlake_pch_enable
		834	*/
2327	Serge	835
2342	Serge	836	/* Preserve the BIOS-computed detected bit. This is
		837	* supposed to be read-only.
		838	*/
		839	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
		840	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
2327	Serge	841
2342	Serge	842	/* Handle DP bits in common between all three register formats */
		843
		844	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
		845
2330	Serge	846	switch (intel_dp->lane_count) {
		847	case 1:
		848	intel_dp->DP \|= DP_PORT_WIDTH_1;
		849	break;
		850	case 2:
		851	intel_dp->DP \|= DP_PORT_WIDTH_2;
		852	break;
		853	case 4:
		854	intel_dp->DP \|= DP_PORT_WIDTH_4;
		855	break;
		856	}
2342	Serge	857	if (intel_dp->has_audio) {
		858	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
		859	pipe_name(intel_crtc->pipe));
2330	Serge	860	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
2342	Serge	861	intel_write_eld(encoder, adjusted_mode);
		862	}
2330	Serge	863	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
		864	intel_dp->link_configuration[0] = intel_dp->link_bw;
		865	intel_dp->link_configuration[1] = intel_dp->lane_count;
		866	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
		867	/*
		868	* Check for DPCD version > 1.1 and enhanced framing support
		869	*/
		870	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		871	(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		872	intel_dp->link_configuration[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
		873	}
2327	Serge	874
2342	Serge	875	/* Split out the IBX/CPU vs CPT settings */
		876
		877	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		878	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		879	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		880	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		881	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		882	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		883
		884	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		885	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		886
		887	intel_dp->DP \|= intel_crtc->pipe << 29;
		888
		889	/* don't miss out required setting for eDP */
		890	intel_dp->DP \|= DP_PLL_ENABLE;
		891	if (adjusted_mode->clock < 200000)
		892	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
		893	else
		894	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		895	} else if (!HAS_PCH_CPT(dev) \|\| is_cpu_edp(intel_dp)) {
		896	intel_dp->DP \|= intel_dp->color_range;
		897
		898	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		899	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		900	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		901	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		902	intel_dp->DP \|= DP_LINK_TRAIN_OFF;
		903
		904	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		905	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		906
		907	if (intel_crtc->pipe == 1)
2330	Serge	908	intel_dp->DP \|= DP_PIPEB_SELECT;
2327	Serge	909
2342	Serge	910	if (is_cpu_edp(intel_dp)) {
2330	Serge	911	/* don't miss out required setting for eDP */
		912	intel_dp->DP \|= DP_PLL_ENABLE;
		913	if (adjusted_mode->clock < 200000)
		914	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
		915	else
		916	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		917	}
2342	Serge	918	} else {
		919	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		920	}
2330	Serge	921	}
2327	Serge	922
2342	Serge	923	#define IDLE_ON_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		924	#define IDLE_ON_VALUE (PP_ON \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_ON_IDLE)
		925
		926	#define IDLE_OFF_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		927	#define IDLE_OFF_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		928
		929	#define IDLE_CYCLE_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| PP_CYCLE_DELAY_ACTIVE \| PP_SEQUENCE_STATE_MASK)
		930	#define IDLE_CYCLE_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		931
		932	static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
		933	u32 mask,
		934	u32 value)
		935	{
		936	struct drm_device *dev = intel_dp->base.base.dev;
		937	struct drm_i915_private *dev_priv = dev->dev_private;
		938
		939	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		940	mask, value,
		941	I915_READ(PCH_PP_STATUS),
		942	I915_READ(PCH_PP_CONTROL));
		943
		944	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
		945	DRM_ERROR("Panel status timeout: status %08x control %08x\n",
		946	I915_READ(PCH_PP_STATUS),
		947	I915_READ(PCH_PP_CONTROL));
		948	}
		949	}
		950
		951	static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
		952	{
		953	DRM_DEBUG_KMS("Wait for panel power on\n");
		954	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
		955	}
		956
		957	static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
		958	{
		959	DRM_DEBUG_KMS("Wait for panel power off time\n");
		960	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
		961	}
		962
		963	static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
		964	{
		965	DRM_DEBUG_KMS("Wait for panel power cycle\n");
		966	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
		967	}
		968
		969
		970	/* Read the current pp_control value, unlocking the register if it
		971	* is locked
		972	*/
		973
		974	static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
		975	{
		976	u32 control = I915_READ(PCH_PP_CONTROL);
		977
		978	control &= ~PANEL_UNLOCK_MASK;
		979	control \|= PANEL_UNLOCK_REGS;
		980	return control;
		981	}
		982
2330	Serge	983	static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
		984	{
		985	struct drm_device *dev = intel_dp->base.base.dev;
		986	struct drm_i915_private *dev_priv = dev->dev_private;
		987	u32 pp;
2327	Serge	988
2342	Serge	989	if (!is_edp(intel_dp))
		990	return;
		991	DRM_DEBUG_KMS("Turn eDP VDD on\n");
2327	Serge	992
2342	Serge	993	WARN(intel_dp->want_panel_vdd,
		994	"eDP VDD already requested on\n");
		995
		996	intel_dp->want_panel_vdd = true;
		997
		998	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		999	DRM_DEBUG_KMS("eDP VDD already on\n");
		1000	return;
		1001	}
		1002
		1003	if (!ironlake_edp_have_panel_power(intel_dp))
		1004	ironlake_wait_panel_power_cycle(intel_dp);
		1005
		1006	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1007	pp \|= EDP_FORCE_VDD;
		1008	I915_WRITE(PCH_PP_CONTROL, pp);
		1009	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1010	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		1011	I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
		1012
		1013	/*
		1014	* If the panel wasn't on, delay before accessing aux channel
		1015	*/
		1016	if (!ironlake_edp_have_panel_power(intel_dp)) {
		1017	DRM_DEBUG_KMS("eDP was not running\n");
		1018	msleep(intel_dp->panel_power_up_delay);
		1019	}
2330	Serge	1020	}
2327	Serge	1021
2342	Serge	1022	static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
2330	Serge	1023	{
		1024	struct drm_device *dev = intel_dp->base.base.dev;
		1025	struct drm_i915_private *dev_priv = dev->dev_private;
		1026	u32 pp;
2327	Serge	1027
2342	Serge	1028	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
		1029	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1030	pp &= ~EDP_FORCE_VDD;
		1031	I915_WRITE(PCH_PP_CONTROL, pp);
		1032	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1033
2330	Serge	1034	/* Make sure sequencer is idle before allowing subsequent activity */
2342	Serge	1035	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		1036	I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
		1037
		1038	msleep(intel_dp->panel_power_down_delay);
		1039	}
2330	Serge	1040	}
2327	Serge	1041
2342	Serge	1042
		1043	static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2330	Serge	1044	{
2342	Serge	1045	if (!is_edp(intel_dp))
		1046	return;
		1047
		1048	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
		1049	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
		1050
		1051	intel_dp->want_panel_vdd = false;
		1052
		1053	if (sync) {
		1054	ironlake_panel_vdd_off_sync(intel_dp);
		1055	} else {
		1056	/*
		1057	* Queue the timer to fire a long
		1058	* time from now (relative to the power down delay)
		1059	* to keep the panel power up across a sequence of operations
		1060	*/
		1061	// schedule_delayed_work(&intel_dp->panel_vdd_work,
		1062	// msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
		1063	}
		1064	}
		1065
		1066	static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
		1067	{
2330	Serge	1068	struct drm_device *dev = intel_dp->base.base.dev;
		1069	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1070	u32 pp;
2327	Serge	1071
2342	Serge	1072	if (!is_edp(intel_dp))
		1073	return;
2327	Serge	1074
2342	Serge	1075	DRM_DEBUG_KMS("Turn eDP power on\n");
2327	Serge	1076
2342	Serge	1077	if (ironlake_edp_have_panel_power(intel_dp)) {
		1078	DRM_DEBUG_KMS("eDP power already on\n");
		1079	return;
		1080	}
		1081
		1082	ironlake_wait_panel_power_cycle(intel_dp);
		1083
		1084	pp = ironlake_get_pp_control(dev_priv);
		1085	if (IS_GEN5(dev)) {
2330	Serge	1086	/* ILK workaround: disable reset around power sequence */
		1087	pp &= ~PANEL_POWER_RESET;
		1088	I915_WRITE(PCH_PP_CONTROL, pp);
		1089	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1090	}
2327	Serge	1091
2342	Serge	1092	pp \|= POWER_TARGET_ON;
		1093	if (!IS_GEN5(dev))
		1094	pp \|= PANEL_POWER_RESET;
		1095
2330	Serge	1096	I915_WRITE(PCH_PP_CONTROL, pp);
		1097	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1098
2342	Serge	1099	ironlake_wait_panel_on(intel_dp);
2327	Serge	1100
2342	Serge	1101	if (IS_GEN5(dev)) {
2330	Serge	1102	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
		1103	I915_WRITE(PCH_PP_CONTROL, pp);
		1104	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1105	}
2330	Serge	1106	}
2327	Serge	1107
2342	Serge	1108	static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
2330	Serge	1109	{
2342	Serge	1110	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1111	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1112	u32 pp;
2327	Serge	1113
2342	Serge	1114	if (!is_edp(intel_dp))
		1115	return;
2327	Serge	1116
2342	Serge	1117	DRM_DEBUG_KMS("Turn eDP power off\n");
2327	Serge	1118
2342	Serge	1119	WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
		1120
		1121	pp = ironlake_get_pp_control(dev_priv);
		1122	pp &= ~(POWER_TARGET_ON \| EDP_FORCE_VDD \| PANEL_POWER_RESET \| EDP_BLC_ENABLE);
2330	Serge	1123	I915_WRITE(PCH_PP_CONTROL, pp);
		1124	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1125
2342	Serge	1126	ironlake_wait_panel_off(intel_dp);
2330	Serge	1127	}
2327	Serge	1128
2342	Serge	1129	static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
2330	Serge	1130	{
2342	Serge	1131	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1132	struct drm_i915_private *dev_priv = dev->dev_private;
		1133	u32 pp;
2327	Serge	1134
2342	Serge	1135	if (!is_edp(intel_dp))
		1136	return;
		1137
2330	Serge	1138	DRM_DEBUG_KMS("\n");
		1139	/*
		1140	* If we enable the backlight right away following a panel power
		1141	* on, we may see slight flicker as the panel syncs with the eDP
		1142	* link. So delay a bit to make sure the image is solid before
		1143	* allowing it to appear.
		1144	*/
2342	Serge	1145	msleep(intel_dp->backlight_on_delay);
		1146	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1147	pp \|= EDP_BLC_ENABLE;
		1148	I915_WRITE(PCH_PP_CONTROL, pp);
2342	Serge	1149	POSTING_READ(PCH_PP_CONTROL);
2330	Serge	1150	}
2327	Serge	1151
2342	Serge	1152	static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
2330	Serge	1153	{
2342	Serge	1154	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1155	struct drm_i915_private *dev_priv = dev->dev_private;
		1156	u32 pp;
2327	Serge	1157
2342	Serge	1158	if (!is_edp(intel_dp))
		1159	return;
		1160
2330	Serge	1161	DRM_DEBUG_KMS("\n");
2342	Serge	1162	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1163	pp &= ~EDP_BLC_ENABLE;
		1164	I915_WRITE(PCH_PP_CONTROL, pp);
2342	Serge	1165	POSTING_READ(PCH_PP_CONTROL);
		1166	msleep(intel_dp->backlight_off_delay);
2330	Serge	1167	}
2327	Serge	1168
2330	Serge	1169	static void ironlake_edp_pll_on(struct drm_encoder *encoder)
		1170	{
		1171	struct drm_device *dev = encoder->dev;
		1172	struct drm_i915_private *dev_priv = dev->dev_private;
		1173	u32 dpa_ctl;
2327	Serge	1174
2330	Serge	1175	DRM_DEBUG_KMS("\n");
		1176	dpa_ctl = I915_READ(DP_A);
		1177	dpa_ctl \|= DP_PLL_ENABLE;
		1178	I915_WRITE(DP_A, dpa_ctl);
		1179	POSTING_READ(DP_A);
		1180	udelay(200);
		1181	}
2327	Serge	1182
2330	Serge	1183	static void ironlake_edp_pll_off(struct drm_encoder *encoder)
		1184	{
		1185	struct drm_device *dev = encoder->dev;
		1186	struct drm_i915_private *dev_priv = dev->dev_private;
		1187	u32 dpa_ctl;
2327	Serge	1188
2330	Serge	1189	dpa_ctl = I915_READ(DP_A);
		1190	dpa_ctl &= ~DP_PLL_ENABLE;
		1191	I915_WRITE(DP_A, dpa_ctl);
		1192	POSTING_READ(DP_A);
		1193	udelay(200);
		1194	}
2327	Serge	1195
2330	Serge	1196	/* If the sink supports it, try to set the power state appropriately */
		1197	static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
		1198	{
		1199	int ret, i;
2327	Serge	1200
2330	Serge	1201	/* Should have a valid DPCD by this point */
		1202	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		1203	return;
2327	Serge	1204
2330	Serge	1205	if (mode != DRM_MODE_DPMS_ON) {
		1206	ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
		1207	DP_SET_POWER_D3);
		1208	if (ret != 1)
		1209	DRM_DEBUG_DRIVER("failed to write sink power state\n");
		1210	} else {
		1211	/*
		1212	* When turning on, we need to retry for 1ms to give the sink
		1213	* time to wake up.
		1214	*/
		1215	for (i = 0; i < 3; i++) {
		1216	ret = intel_dp_aux_native_write_1(intel_dp,
		1217	DP_SET_POWER,
		1218	DP_SET_POWER_D0);
		1219	if (ret == 1)
		1220	break;
		1221	msleep(1);
		1222	}
		1223	}
		1224	}
2327	Serge	1225
2330	Serge	1226	static void intel_dp_prepare(struct drm_encoder *encoder)
		1227	{
		1228	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2327	Serge	1229
2342	Serge	1230	ironlake_edp_backlight_off(intel_dp);
		1231	ironlake_edp_panel_off(intel_dp);
		1232
2330	Serge	1233	/* Wake up the sink first */
2342	Serge	1234	ironlake_edp_panel_vdd_on(intel_dp);
2330	Serge	1235	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2342	Serge	1236	intel_dp_link_down(intel_dp);
		1237	ironlake_edp_panel_vdd_off(intel_dp, false);
2327	Serge	1238
2342	Serge	1239	/* Make sure the panel is off before trying to
		1240	* change the mode
		1241	*/
2330	Serge	1242	}
2327	Serge	1243
2330	Serge	1244	static void intel_dp_commit(struct drm_encoder *encoder)
		1245	{
		1246	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1247	struct drm_device *dev = encoder->dev;
2342	Serge	1248	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
2327	Serge	1249
2330	Serge	1250	ironlake_edp_panel_vdd_on(intel_dp);
2342	Serge	1251	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2330	Serge	1252	intel_dp_start_link_train(intel_dp);
		1253	ironlake_edp_panel_on(intel_dp);
2342	Serge	1254	ironlake_edp_panel_vdd_off(intel_dp, true);
2330	Serge	1255	intel_dp_complete_link_train(intel_dp);
2342	Serge	1256	ironlake_edp_backlight_on(intel_dp);
2330	Serge	1257
2342	Serge	1258	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
2330	Serge	1259
2342	Serge	1260	if (HAS_PCH_CPT(dev))
		1261	intel_cpt_verify_modeset(dev, intel_crtc->pipe);
2330	Serge	1262	}
		1263
		1264	static void
		1265	intel_dp_dpms(struct drm_encoder *encoder, int mode)
		1266	{
		1267	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1268	struct drm_device *dev = encoder->dev;
		1269	struct drm_i915_private *dev_priv = dev->dev_private;
		1270	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		1271
		1272	if (mode != DRM_MODE_DPMS_ON) {
2342	Serge	1273	ironlake_edp_backlight_off(intel_dp);
		1274	ironlake_edp_panel_off(intel_dp);
		1275
		1276	ironlake_edp_panel_vdd_on(intel_dp);
2330	Serge	1277	intel_dp_sink_dpms(intel_dp, mode);
		1278	intel_dp_link_down(intel_dp);
2342	Serge	1279	ironlake_edp_panel_vdd_off(intel_dp, false);
		1280
		1281	if (is_cpu_edp(intel_dp))
2330	Serge	1282	ironlake_edp_pll_off(encoder);
		1283	} else {
2342	Serge	1284	if (is_cpu_edp(intel_dp))
		1285	ironlake_edp_pll_on(encoder);
		1286
2330	Serge	1287	ironlake_edp_panel_vdd_on(intel_dp);
		1288	intel_dp_sink_dpms(intel_dp, mode);
		1289	if (!(dp_reg & DP_PORT_EN)) {
		1290	intel_dp_start_link_train(intel_dp);
		1291	ironlake_edp_panel_on(intel_dp);
2342	Serge	1292	ironlake_edp_panel_vdd_off(intel_dp, true);
2330	Serge	1293	intel_dp_complete_link_train(intel_dp);
2342	Serge	1294	} else
		1295	ironlake_edp_panel_vdd_off(intel_dp, false);
		1296	ironlake_edp_backlight_on(intel_dp);
2330	Serge	1297	}
		1298	intel_dp->dpms_mode = mode;
		1299	}
		1300
		1301	/*
		1302	* Native read with retry for link status and receiver capability reads for
		1303	* cases where the sink may still be asleep.
		1304	*/
		1305	static bool
		1306	intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
		1307	uint8_t *recv, int recv_bytes)
		1308	{
		1309	int ret, i;
		1310
		1311	/*
		1312	* Sinks are supposed to come up within 1ms from an off state,
		1313	* but we're also supposed to retry 3 times per the spec.
		1314	*/
		1315	for (i = 0; i < 3; i++) {
		1316	ret = intel_dp_aux_native_read(intel_dp, address, recv,
		1317	recv_bytes);
		1318	if (ret == recv_bytes)
		1319	return true;
		1320	msleep(1);
		1321	}
		1322
		1323	return false;
		1324	}
		1325
		1326	/*
		1327	* Fetch AUX CH registers 0x202 - 0x207 which contain
		1328	* link status information
		1329	*/
		1330	static bool
2342	Serge	1331	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1332	{
		1333	return intel_dp_aux_native_read_retry(intel_dp,
		1334	DP_LANE0_1_STATUS,
2342	Serge	1335	link_status,
2330	Serge	1336	DP_LINK_STATUS_SIZE);
		1337	}
		1338
		1339	static uint8_t
		1340	intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1341	int r)
		1342	{
		1343	return link_status[r - DP_LANE0_1_STATUS];
		1344	}
		1345
		1346	static uint8_t
2342	Serge	1347	intel_get_adjust_request_voltage(uint8_t adjust_request[2],
2330	Serge	1348	int lane)
		1349	{
		1350	int s = ((lane & 1) ?
		1351	DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
		1352	DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
2342	Serge	1353	uint8_t l = adjust_request[lane>>1];
2330	Serge	1354
		1355	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
		1356	}
		1357
		1358	static uint8_t
2342	Serge	1359	intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
2330	Serge	1360	int lane)
		1361	{
		1362	int s = ((lane & 1) ?
		1363	DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
		1364	DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
2342	Serge	1365	uint8_t l = adjust_request[lane>>1];
2330	Serge	1366
		1367	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
		1368	}
		1369
		1370
		1371	#if 0
		1372	static char *voltage_names[] = {
		1373	"0.4V", "0.6V", "0.8V", "1.2V"
		1374	};
		1375	static char *pre_emph_names[] = {
		1376	"0dB", "3.5dB", "6dB", "9.5dB"
		1377	};
		1378	static char *link_train_names[] = {
		1379	"pattern 1", "pattern 2", "idle", "off"
		1380	};
		1381	#endif
		1382
		1383	/*
		1384	* These are source-specific values; current Intel hardware supports
		1385	* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
		1386	*/
		1387
		1388	static uint8_t
2342	Serge	1389	intel_dp_voltage_max(struct intel_dp *intel_dp)
2330	Serge	1390	{
2342	Serge	1391	struct drm_device *dev = intel_dp->base.base.dev;
		1392
		1393	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		1394	return DP_TRAIN_VOLTAGE_SWING_800;
		1395	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		1396	return DP_TRAIN_VOLTAGE_SWING_1200;
		1397	else
		1398	return DP_TRAIN_VOLTAGE_SWING_800;
		1399	}
		1400
		1401	static uint8_t
		1402	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
		1403	{
		1404	struct drm_device *dev = intel_dp->base.base.dev;
		1405
		1406	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1407	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1408	case DP_TRAIN_VOLTAGE_SWING_400:
		1409	return DP_TRAIN_PRE_EMPHASIS_6;
		1410	case DP_TRAIN_VOLTAGE_SWING_600:
		1411	case DP_TRAIN_VOLTAGE_SWING_800:
		1412	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1413	default:
		1414	return DP_TRAIN_PRE_EMPHASIS_0;
		1415	}
		1416	} else {
2330	Serge	1417	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1418	case DP_TRAIN_VOLTAGE_SWING_400:
		1419	return DP_TRAIN_PRE_EMPHASIS_6;
		1420	case DP_TRAIN_VOLTAGE_SWING_600:
		1421	return DP_TRAIN_PRE_EMPHASIS_6;
		1422	case DP_TRAIN_VOLTAGE_SWING_800:
		1423	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1424	case DP_TRAIN_VOLTAGE_SWING_1200:
		1425	default:
		1426	return DP_TRAIN_PRE_EMPHASIS_0;
		1427	}
2342	Serge	1428	}
2330	Serge	1429	}
		1430
		1431	static void
2342	Serge	1432	intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1433	{
		1434	uint8_t v = 0;
		1435	uint8_t p = 0;
		1436	int lane;
2342	Serge	1437	uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
		1438	uint8_t voltage_max;
		1439	uint8_t preemph_max;
2330	Serge	1440
		1441	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2342	Serge	1442	uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
		1443	uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
2330	Serge	1444
		1445	if (this_v > v)
		1446	v = this_v;
		1447	if (this_p > p)
		1448	p = this_p;
		1449	}
		1450
2342	Serge	1451	voltage_max = intel_dp_voltage_max(intel_dp);
		1452	if (v >= voltage_max)
		1453	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
2330	Serge	1454
2342	Serge	1455	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
		1456	if (p >= preemph_max)
		1457	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2330	Serge	1458
		1459	for (lane = 0; lane < 4; lane++)
		1460	intel_dp->train_set[lane] = v \| p;
		1461	}
		1462
		1463	static uint32_t
2342	Serge	1464	intel_dp_signal_levels(uint8_t train_set)
2330	Serge	1465	{
		1466	uint32_t signal_levels = 0;
		1467
		1468	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1469	case DP_TRAIN_VOLTAGE_SWING_400:
		1470	default:
		1471	signal_levels \|= DP_VOLTAGE_0_4;
		1472	break;
		1473	case DP_TRAIN_VOLTAGE_SWING_600:
		1474	signal_levels \|= DP_VOLTAGE_0_6;
		1475	break;
		1476	case DP_TRAIN_VOLTAGE_SWING_800:
		1477	signal_levels \|= DP_VOLTAGE_0_8;
		1478	break;
		1479	case DP_TRAIN_VOLTAGE_SWING_1200:
		1480	signal_levels \|= DP_VOLTAGE_1_2;
		1481	break;
		1482	}
		1483	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		1484	case DP_TRAIN_PRE_EMPHASIS_0:
		1485	default:
		1486	signal_levels \|= DP_PRE_EMPHASIS_0;
		1487	break;
		1488	case DP_TRAIN_PRE_EMPHASIS_3_5:
		1489	signal_levels \|= DP_PRE_EMPHASIS_3_5;
		1490	break;
		1491	case DP_TRAIN_PRE_EMPHASIS_6:
		1492	signal_levels \|= DP_PRE_EMPHASIS_6;
		1493	break;
		1494	case DP_TRAIN_PRE_EMPHASIS_9_5:
		1495	signal_levels \|= DP_PRE_EMPHASIS_9_5;
		1496	break;
		1497	}
		1498	return signal_levels;
		1499	}
		1500
		1501	/* Gen6's DP voltage swing and pre-emphasis control */
		1502	static uint32_t
		1503	intel_gen6_edp_signal_levels(uint8_t train_set)
		1504	{
		1505	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		1506	DP_TRAIN_PRE_EMPHASIS_MASK);
		1507	switch (signal_levels) {
		1508	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		1509	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		1510	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1511	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1512	return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
		1513	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		1514	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		1515	return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
		1516	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1517	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1518	return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
		1519	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		1520	case DP_TRAIN_VOLTAGE_SWING_1200 \| DP_TRAIN_PRE_EMPHASIS_0:
		1521	return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
		1522	default:
		1523	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		1524	"0x%x\n", signal_levels);
		1525	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1526	}
		1527	}
		1528
2342	Serge	1529	/* Gen7's DP voltage swing and pre-emphasis control */
		1530	static uint32_t
		1531	intel_gen7_edp_signal_levels(uint8_t train_set)
		1532	{
		1533	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		1534	DP_TRAIN_PRE_EMPHASIS_MASK);
		1535	switch (signal_levels) {
		1536	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		1537	return EDP_LINK_TRAIN_400MV_0DB_IVB;
		1538	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1539	return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
		1540	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		1541	return EDP_LINK_TRAIN_400MV_6DB_IVB;
		1542
		1543	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		1544	return EDP_LINK_TRAIN_600MV_0DB_IVB;
		1545	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1546	return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
		1547
		1548	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		1549	return EDP_LINK_TRAIN_800MV_0DB_IVB;
		1550	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1551	return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
		1552
		1553	default:
		1554	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		1555	"0x%x\n", signal_levels);
		1556	return EDP_LINK_TRAIN_500MV_0DB_IVB;
		1557	}
		1558	}
		1559
2330	Serge	1560	static uint8_t
		1561	intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1562	int lane)
		1563	{
		1564	int s = (lane & 1) * 4;
2342	Serge	1565	uint8_t l = link_status[lane>>1];
2330	Serge	1566
		1567	return (l >> s) & 0xf;
		1568	}
		1569
		1570	/* Check for clock recovery is done on all channels */
		1571	static bool
		1572	intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
		1573	{
		1574	int lane;
		1575	uint8_t lane_status;
		1576
		1577	for (lane = 0; lane < lane_count; lane++) {
		1578	lane_status = intel_get_lane_status(link_status, lane);
		1579	if ((lane_status & DP_LANE_CR_DONE) == 0)
		1580	return false;
		1581	}
		1582	return true;
		1583	}
		1584
		1585	/* Check to see if channel eq is done on all channels */
		1586	#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE\|\
		1587	DP_LANE_CHANNEL_EQ_DONE\|\
		1588	DP_LANE_SYMBOL_LOCKED)
		1589	static bool
2342	Serge	1590	intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1591	{
		1592	uint8_t lane_align;
		1593	uint8_t lane_status;
		1594	int lane;
		1595
2342	Serge	1596	lane_align = intel_dp_link_status(link_status,
2330	Serge	1597	DP_LANE_ALIGN_STATUS_UPDATED);
		1598	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		1599	return false;
		1600	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2342	Serge	1601	lane_status = intel_get_lane_status(link_status, lane);
2330	Serge	1602	if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
		1603	return false;
		1604	}
		1605	return true;
		1606	}
		1607
		1608	static bool
		1609	intel_dp_set_link_train(struct intel_dp *intel_dp,
		1610	uint32_t dp_reg_value,
		1611	uint8_t dp_train_pat)
		1612	{
		1613	struct drm_device *dev = intel_dp->base.base.dev;
		1614	struct drm_i915_private *dev_priv = dev->dev_private;
		1615	int ret;
		1616
		1617	I915_WRITE(intel_dp->output_reg, dp_reg_value);
		1618	POSTING_READ(intel_dp->output_reg);
		1619
		1620	intel_dp_aux_native_write_1(intel_dp,
		1621	DP_TRAINING_PATTERN_SET,
		1622	dp_train_pat);
		1623
		1624	ret = intel_dp_aux_native_write(intel_dp,
		1625	DP_TRAINING_LANE0_SET,
2342	Serge	1626	intel_dp->train_set,
		1627	intel_dp->lane_count);
		1628	if (ret != intel_dp->lane_count)
2330	Serge	1629	return false;
		1630
		1631	return true;
		1632	}
		1633
		1634	/* Enable corresponding port and start training pattern 1 */
		1635	static void
		1636	intel_dp_start_link_train(struct intel_dp *intel_dp)
		1637	{
		1638	struct drm_device *dev = intel_dp->base.base.dev;
		1639	struct drm_i915_private *dev_priv = dev->dev_private;
		1640	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
		1641	int i;
		1642	uint8_t voltage;
		1643	bool clock_recovery = false;
2342	Serge	1644	int voltage_tries, loop_tries;
2330	Serge	1645	u32 reg;
		1646	uint32_t DP = intel_dp->DP;
		1647
		1648	/*
		1649	* On CPT we have to enable the port in training pattern 1, which
		1650	* will happen below in intel_dp_set_link_train. Otherwise, enable
		1651	* the port and wait for it to become active.
		1652	*/
		1653	if (!HAS_PCH_CPT(dev)) {
		1654	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
		1655	POSTING_READ(intel_dp->output_reg);
		1656	intel_wait_for_vblank(dev, intel_crtc->pipe);
		1657	}
		1658
		1659	/* Write the link configuration data */
		1660	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
		1661	intel_dp->link_configuration,
		1662	DP_LINK_CONFIGURATION_SIZE);
		1663
		1664	DP \|= DP_PORT_EN;
2342	Serge	1665
		1666	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1667	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1668	else
		1669	DP &= ~DP_LINK_TRAIN_MASK;
		1670	memset(intel_dp->train_set, 0, 4);
		1671	voltage = 0xff;
2342	Serge	1672	voltage_tries = 0;
		1673	loop_tries = 0;
2330	Serge	1674	clock_recovery = false;
		1675	for (;;) {
		1676	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2342	Serge	1677	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	1678	uint32_t signal_levels;
2342	Serge	1679
		1680
		1681	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1682	signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
		1683	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) \| signal_levels;
		1684	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
2330	Serge	1685	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1686	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1687	} else {
2342	Serge	1688	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
		1689	DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
2330	Serge	1690	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1691	}
		1692
2342	Serge	1693	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1694	reg = DP \| DP_LINK_TRAIN_PAT_1_CPT;
		1695	else
		1696	reg = DP \| DP_LINK_TRAIN_PAT_1;
		1697
		1698	if (!intel_dp_set_link_train(intel_dp, reg,
		1699	DP_TRAINING_PATTERN_1 \|
		1700	DP_LINK_SCRAMBLING_DISABLE))
		1701	break;
		1702	/* Set training pattern 1 */
		1703
		1704	udelay(100);
2342	Serge	1705	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		1706	DRM_ERROR("failed to get link status\n");
2330	Serge	1707	break;
2342	Serge	1708	}
2330	Serge	1709
2342	Serge	1710	if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
		1711	DRM_DEBUG_KMS("clock recovery OK\n");
2330	Serge	1712	clock_recovery = true;
		1713	break;
		1714	}
		1715
		1716	/* Check to see if we've tried the max voltage */
		1717	for (i = 0; i < intel_dp->lane_count; i++)
		1718	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
		1719	break;
2342	Serge	1720	if (i == intel_dp->lane_count) {
		1721	++loop_tries;
		1722	if (loop_tries == 5) {
		1723	DRM_DEBUG_KMS("too many full retries, give up\n");
2330	Serge	1724	break;
2342	Serge	1725	}
		1726	memset(intel_dp->train_set, 0, 4);
		1727	voltage_tries = 0;
		1728	continue;
		1729	}
2330	Serge	1730
		1731	/* Check to see if we've tried the same voltage 5 times */
		1732	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2342	Serge	1733	++voltage_tries;
		1734	if (voltage_tries == 5) {
		1735	DRM_DEBUG_KMS("too many voltage retries, give up\n");
2330	Serge	1736	break;
2342	Serge	1737	}
2330	Serge	1738	} else
2342	Serge	1739	voltage_tries = 0;
2330	Serge	1740	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
		1741
		1742	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	1743	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	1744	}
		1745
		1746	intel_dp->DP = DP;
		1747	}
		1748
		1749	static void
		1750	intel_dp_complete_link_train(struct intel_dp *intel_dp)
		1751	{
		1752	struct drm_device *dev = intel_dp->base.base.dev;
		1753	struct drm_i915_private *dev_priv = dev->dev_private;
		1754	bool channel_eq = false;
		1755	int tries, cr_tries;
		1756	u32 reg;
		1757	uint32_t DP = intel_dp->DP;
		1758
		1759	/* channel equalization */
		1760	tries = 0;
		1761	cr_tries = 0;
		1762	channel_eq = false;
		1763	for (;;) {
		1764	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
		1765	uint32_t signal_levels;
2342	Serge	1766	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	1767
		1768	if (cr_tries > 5) {
		1769	DRM_ERROR("failed to train DP, aborting\n");
		1770	intel_dp_link_down(intel_dp);
		1771	break;
		1772	}
		1773
2342	Serge	1774	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1775	signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
		1776	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) \| signal_levels;
		1777	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
2330	Serge	1778	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1779	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1780	} else {
2342	Serge	1781	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
2330	Serge	1782	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1783	}
		1784
2342	Serge	1785	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1786	reg = DP \| DP_LINK_TRAIN_PAT_2_CPT;
		1787	else
		1788	reg = DP \| DP_LINK_TRAIN_PAT_2;
		1789
		1790	/* channel eq pattern */
		1791	if (!intel_dp_set_link_train(intel_dp, reg,
		1792	DP_TRAINING_PATTERN_2 \|
		1793	DP_LINK_SCRAMBLING_DISABLE))
		1794	break;
		1795
		1796	udelay(400);
2342	Serge	1797	if (!intel_dp_get_link_status(intel_dp, link_status))
2330	Serge	1798	break;
		1799
		1800	/* Make sure clock is still ok */
2342	Serge	1801	if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2330	Serge	1802	intel_dp_start_link_train(intel_dp);
		1803	cr_tries++;
		1804	continue;
		1805	}
		1806
2342	Serge	1807	if (intel_channel_eq_ok(intel_dp, link_status)) {
2330	Serge	1808	channel_eq = true;
		1809	break;
		1810	}
		1811
		1812	/* Try 5 times, then try clock recovery if that fails */
		1813	if (tries > 5) {
		1814	intel_dp_link_down(intel_dp);
		1815	intel_dp_start_link_train(intel_dp);
		1816	tries = 0;
		1817	cr_tries++;
		1818	continue;
		1819	}
		1820
		1821	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	1822	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	1823	++tries;
		1824	}
		1825
2342	Serge	1826	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1827	reg = DP \| DP_LINK_TRAIN_OFF_CPT;
		1828	else
		1829	reg = DP \| DP_LINK_TRAIN_OFF;
		1830
		1831	I915_WRITE(intel_dp->output_reg, reg);
		1832	POSTING_READ(intel_dp->output_reg);
		1833	intel_dp_aux_native_write_1(intel_dp,
		1834	DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
		1835	}
		1836
		1837	static void
		1838	intel_dp_link_down(struct intel_dp *intel_dp)
		1839	{
		1840	struct drm_device *dev = intel_dp->base.base.dev;
		1841	struct drm_i915_private *dev_priv = dev->dev_private;
		1842	uint32_t DP = intel_dp->DP;
		1843
		1844	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
		1845	return;
		1846
		1847	DRM_DEBUG_KMS("\n");
		1848
		1849	if (is_edp(intel_dp)) {
		1850	DP &= ~DP_PLL_ENABLE;
		1851	I915_WRITE(intel_dp->output_reg, DP);
		1852	POSTING_READ(intel_dp->output_reg);
		1853	udelay(100);
		1854	}
		1855
2342	Serge	1856	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp))) {
2330	Serge	1857	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1858	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE_CPT);
		1859	} else {
		1860	DP &= ~DP_LINK_TRAIN_MASK;
		1861	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE);
		1862	}
		1863	POSTING_READ(intel_dp->output_reg);
		1864
		1865	msleep(17);
		1866
2342	Serge	1867	if (is_edp(intel_dp)) {
		1868	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
		1869	DP \|= DP_LINK_TRAIN_OFF_CPT;
		1870	else
2330	Serge	1871	DP \|= DP_LINK_TRAIN_OFF;
2342	Serge	1872	}
2330	Serge	1873
		1874	if (!HAS_PCH_CPT(dev) &&
		1875	I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
		1876	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		1877
		1878	/* Hardware workaround: leaving our transcoder select
		1879	* set to transcoder B while it's off will prevent the
		1880	* corresponding HDMI output on transcoder A.
		1881	*
		1882	* Combine this with another hardware workaround:
		1883	* transcoder select bit can only be cleared while the
		1884	* port is enabled.
		1885	*/
		1886	DP &= ~DP_PIPEB_SELECT;
		1887	I915_WRITE(intel_dp->output_reg, DP);
		1888
		1889	/* Changes to enable or select take place the vblank
		1890	* after being written.
		1891	*/
		1892	if (crtc == NULL) {
		1893	/* We can arrive here never having been attached
		1894	* to a CRTC, for instance, due to inheriting
		1895	* random state from the BIOS.
		1896	*
		1897	* If the pipe is not running, play safe and
		1898	* wait for the clocks to stabilise before
		1899	* continuing.
		1900	*/
		1901	POSTING_READ(intel_dp->output_reg);
		1902	msleep(50);
		1903	} else
		1904	intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
		1905	}
		1906
2342	Serge	1907	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2330	Serge	1908	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
		1909	POSTING_READ(intel_dp->output_reg);
2342	Serge	1910	msleep(intel_dp->panel_power_down_delay);
2330	Serge	1911	}
		1912
		1913	static bool
		1914	intel_dp_get_dpcd(struct intel_dp *intel_dp)
		1915	{
		1916	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2342	Serge	1917	sizeof(intel_dp->dpcd)) &&
2330	Serge	1918	(intel_dp->dpcd[DP_DPCD_REV] != 0)) {
		1919	return true;
		1920	}
		1921
		1922	return false;
		1923	}
		1924
2342	Serge	1925	static bool
		1926	intel_dp_get_sink_irq(struct intel_dp intel_dp, u8 sink_irq_vector)
		1927	{
		1928	int ret;
		1929
		1930	ret = intel_dp_aux_native_read_retry(intel_dp,
		1931	DP_DEVICE_SERVICE_IRQ_VECTOR,
		1932	sink_irq_vector, 1);
		1933	if (!ret)
		1934	return false;
		1935
		1936	return true;
		1937	}
		1938
		1939	static void
		1940	intel_dp_handle_test_request(struct intel_dp *intel_dp)
		1941	{
		1942	/* NAK by default */
		1943	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
		1944	}
		1945
2330	Serge	1946	/*
		1947	* According to DP spec
		1948	* 5.1.2:
		1949	* 1. Read DPCD
		1950	* 2. Configure link according to Receiver Capabilities
		1951	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
		1952	* 4. Check link status on receipt of hot-plug interrupt
		1953	*/
		1954
		1955	static void
		1956	intel_dp_check_link_status(struct intel_dp *intel_dp)
		1957	{
2342	Serge	1958	u8 sink_irq_vector;
		1959	u8 link_status[DP_LINK_STATUS_SIZE];
		1960
2330	Serge	1961	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
		1962	return;
		1963
		1964	if (!intel_dp->base.base.crtc)
		1965	return;
		1966
		1967	/* Try to read receiver status if the link appears to be up */
2342	Serge	1968	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2330	Serge	1969	intel_dp_link_down(intel_dp);
		1970	return;
		1971	}
		1972
		1973	/* Now read the DPCD to see if it's actually running */
		1974	if (!intel_dp_get_dpcd(intel_dp)) {
		1975	intel_dp_link_down(intel_dp);
		1976	return;
		1977	}
		1978
2342	Serge	1979	/* Try to read the source of the interrupt */
		1980	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		1981	intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		1982	/* Clear interrupt source */
		1983	intel_dp_aux_native_write_1(intel_dp,
		1984	DP_DEVICE_SERVICE_IRQ_VECTOR,
		1985	sink_irq_vector);
		1986
		1987	if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
		1988	intel_dp_handle_test_request(intel_dp);
		1989	if (sink_irq_vector & (DP_CP_IRQ \| DP_SINK_SPECIFIC_IRQ))
		1990	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
		1991	}
		1992
		1993	if (!intel_channel_eq_ok(intel_dp, link_status)) {
2330	Serge	1994	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
		1995	drm_get_encoder_name(&intel_dp->base.base));
		1996	intel_dp_start_link_train(intel_dp);
		1997	intel_dp_complete_link_train(intel_dp);
		1998	}
		1999	}
		2000
		2001	static enum drm_connector_status
		2002	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
		2003	{
		2004	if (intel_dp_get_dpcd(intel_dp))
		2005	return connector_status_connected;
		2006	return connector_status_disconnected;
		2007	}
		2008
		2009	static enum drm_connector_status
		2010	ironlake_dp_detect(struct intel_dp *intel_dp)
		2011	{
		2012	enum drm_connector_status status;
		2013
		2014	/* Can't disconnect eDP, but you can close the lid... */
		2015	if (is_edp(intel_dp)) {
		2016	status = intel_panel_detect(intel_dp->base.base.dev);
		2017	if (status == connector_status_unknown)
		2018	status = connector_status_connected;
		2019	return status;
		2020	}
		2021
		2022	return intel_dp_detect_dpcd(intel_dp);
		2023	}
		2024
		2025	static enum drm_connector_status
		2026	g4x_dp_detect(struct intel_dp *intel_dp)
		2027	{
		2028	struct drm_device *dev = intel_dp->base.base.dev;
		2029	struct drm_i915_private *dev_priv = dev->dev_private;
		2030	uint32_t temp, bit;
		2031
		2032	switch (intel_dp->output_reg) {
		2033	case DP_B:
		2034	bit = DPB_HOTPLUG_INT_STATUS;
		2035	break;
		2036	case DP_C:
		2037	bit = DPC_HOTPLUG_INT_STATUS;
		2038	break;
		2039	case DP_D:
		2040	bit = DPD_HOTPLUG_INT_STATUS;
		2041	break;
		2042	default:
		2043	return connector_status_unknown;
		2044	}
		2045
		2046	temp = I915_READ(PORT_HOTPLUG_STAT);
		2047
		2048	if ((temp & bit) == 0)
		2049	return connector_status_disconnected;
		2050
		2051	return intel_dp_detect_dpcd(intel_dp);
		2052	}
		2053
2342	Serge	2054	static struct edid *
		2055	intel_dp_get_edid(struct drm_connector connector, struct i2c_adapter adapter)
		2056	{
		2057	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2058	struct edid *edid;
		2059
		2060	ironlake_edp_panel_vdd_on(intel_dp);
		2061	edid = drm_get_edid(connector, adapter);
		2062	ironlake_edp_panel_vdd_off(intel_dp, false);
		2063	return edid;
		2064	}
		2065
		2066	static int
		2067	intel_dp_get_edid_modes(struct drm_connector connector, struct i2c_adapter adapter)
		2068	{
		2069	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2070	int ret;
		2071
		2072	ironlake_edp_panel_vdd_on(intel_dp);
		2073	ret = intel_ddc_get_modes(connector, adapter);
		2074	ironlake_edp_panel_vdd_off(intel_dp, false);
		2075	return ret;
		2076	}
		2077
		2078
2330	Serge	2079	/**
		2080	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
		2081	*
		2082	* \return true if DP port is connected.
		2083	* \return false if DP port is disconnected.
		2084	*/
		2085	static enum drm_connector_status
		2086	intel_dp_detect(struct drm_connector *connector, bool force)
		2087	{
		2088	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2089	struct drm_device *dev = intel_dp->base.base.dev;
		2090	enum drm_connector_status status;
		2091	struct edid *edid = NULL;
		2092
		2093	intel_dp->has_audio = false;
		2094
		2095	if (HAS_PCH_SPLIT(dev))
		2096	status = ironlake_dp_detect(intel_dp);
		2097	else
		2098	status = g4x_dp_detect(intel_dp);
		2099
		2100	DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
		2101	intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
		2102	intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
		2103	intel_dp->dpcd[6], intel_dp->dpcd[7]);
		2104
		2105	if (status != connector_status_connected)
		2106	return status;
		2107	/*
		2108	if (intel_dp->force_audio) {
		2109	intel_dp->has_audio = intel_dp->force_audio > 0;
		2110	} else {
		2111	edid = drm_get_edid(connector, &intel_dp->adapter);
		2112	if (edid) {
		2113	intel_dp->has_audio = drm_detect_monitor_audio(edid);
		2114	connector->display_info.raw_edid = NULL;
		2115	kfree(edid);
		2116	}
		2117	}
		2118	*/
		2119	return connector_status_connected;
		2120	}
		2121
		2122	static int intel_dp_get_modes(struct drm_connector *connector)
		2123	{
		2124	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2125	struct drm_device *dev = intel_dp->base.base.dev;
		2126	struct drm_i915_private *dev_priv = dev->dev_private;
		2127	int ret;
		2128
		2129	/* We should parse the EDID data and find out if it has an audio sink
		2130	*/
		2131
2342	Serge	2132	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2330	Serge	2133	if (ret) {
2342	Serge	2134	if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2330	Serge	2135	struct drm_display_mode *newmode;
		2136	list_for_each_entry(newmode, &connector->probed_modes,
		2137	head) {
2342	Serge	2138	if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
		2139	intel_dp->panel_fixed_mode =
2330	Serge	2140	drm_mode_duplicate(dev, newmode);
		2141	break;
		2142	}
		2143	}
		2144	}
		2145	return ret;
		2146	}
		2147
		2148	/* if eDP has no EDID, try to use fixed panel mode from VBT */
		2149	if (is_edp(intel_dp)) {
2342	Serge	2150	/* initialize panel mode from VBT if available for eDP */
		2151	if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
		2152	intel_dp->panel_fixed_mode =
		2153	drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
		2154	if (intel_dp->panel_fixed_mode) {
		2155	intel_dp->panel_fixed_mode->type \|=
		2156	DRM_MODE_TYPE_PREFERRED;
		2157	}
		2158	}
		2159	if (intel_dp->panel_fixed_mode) {
2330	Serge	2160	struct drm_display_mode *mode;
2342	Serge	2161	mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2330	Serge	2162	drm_mode_probed_add(connector, mode);
		2163	return 1;
		2164	}
		2165	}
		2166	return 0;
		2167	}
		2168
		2169
		2170
		2171
		2172
		2173	static int
		2174	intel_dp_set_property(struct drm_connector *connector,
		2175	struct drm_property *property,
		2176	uint64_t val)
		2177	{
		2178	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		2179	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2180	int ret;
		2181
		2182	ret = drm_connector_property_set_value(connector, property, val);
		2183	if (ret)
		2184	return ret;
		2185	#if 0
		2186	if (property == dev_priv->force_audio_property) {
		2187	int i = val;
		2188	bool has_audio;
		2189
		2190	if (i == intel_dp->force_audio)
		2191	return 0;
		2192
		2193	intel_dp->force_audio = i;
		2194
		2195	if (i == 0)
		2196	has_audio = intel_dp_detect_audio(connector);
		2197	else
		2198	has_audio = i > 0;
		2199
		2200	if (has_audio == intel_dp->has_audio)
		2201	return 0;
		2202
		2203	intel_dp->has_audio = has_audio;
		2204	goto done;
		2205	}
		2206
		2207	if (property == dev_priv->broadcast_rgb_property) {
		2208	if (val == !!intel_dp->color_range)
		2209	return 0;
		2210
		2211	intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
		2212	goto done;
		2213	}
		2214	#endif
		2215
		2216	return -EINVAL;
		2217
		2218	done:
		2219	if (intel_dp->base.base.crtc) {
		2220	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		2221	drm_crtc_helper_set_mode(crtc, &crtc->mode,
		2222	crtc->x, crtc->y,
		2223	crtc->fb);
		2224	}
		2225
		2226	return 0;
		2227	}
		2228
		2229	static void
2342	Serge	2230	intel_dp_destroy(struct drm_connector *connector)
2330	Serge	2231	{
		2232	struct drm_device *dev = connector->dev;
		2233
		2234	if (intel_dpd_is_edp(dev))
		2235	intel_panel_destroy_backlight(dev);
		2236
		2237	drm_sysfs_connector_remove(connector);
		2238	drm_connector_cleanup(connector);
		2239	kfree(connector);
		2240	}
		2241
		2242	static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
		2243	{
		2244	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2245
		2246	// i2c_del_adapter(&intel_dp->adapter);
		2247	drm_encoder_cleanup(encoder);
2342	Serge	2248	if (is_edp(intel_dp)) {
		2249	// cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		2250	ironlake_panel_vdd_off_sync(intel_dp);
		2251	}
2330	Serge	2252	kfree(intel_dp);
		2253	}
		2254
		2255	static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
		2256	.dpms = intel_dp_dpms,
		2257	.mode_fixup = intel_dp_mode_fixup,
		2258	.prepare = intel_dp_prepare,
		2259	.mode_set = intel_dp_mode_set,
		2260	.commit = intel_dp_commit,
		2261	};
		2262
		2263	static const struct drm_connector_funcs intel_dp_connector_funcs = {
		2264	.dpms = drm_helper_connector_dpms,
		2265	.detect = intel_dp_detect,
		2266	.fill_modes = drm_helper_probe_single_connector_modes,
		2267	.set_property = intel_dp_set_property,
		2268	.destroy = intel_dp_destroy,
		2269	};
		2270
		2271	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
		2272	.get_modes = intel_dp_get_modes,
		2273	.mode_valid = intel_dp_mode_valid,
		2274	.best_encoder = intel_best_encoder,
		2275	};
		2276
		2277	static const struct drm_encoder_funcs intel_dp_enc_funcs = {
		2278	.destroy = intel_dp_encoder_destroy,
		2279	};
		2280
		2281	static void
		2282	intel_dp_hot_plug(struct intel_encoder *intel_encoder)
		2283	{
		2284	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		2285
		2286	intel_dp_check_link_status(intel_dp);
		2287	}
		2288
2327	Serge	2289	/* Return which DP Port should be selected for Transcoder DP control */
		2290	int
2342	Serge	2291	intel_trans_dp_port_sel(struct drm_crtc *crtc)
2327	Serge	2292	{
		2293	struct drm_device *dev = crtc->dev;
		2294	struct drm_mode_config *mode_config = &dev->mode_config;
		2295	struct drm_encoder *encoder;
		2296
		2297	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		2298	struct intel_dp *intel_dp;
		2299
		2300	if (encoder->crtc != crtc)
		2301	continue;
		2302
		2303	intel_dp = enc_to_intel_dp(encoder);
2342	Serge	2304	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT \|\|
		2305	intel_dp->base.type == INTEL_OUTPUT_EDP)
2327	Serge	2306	return intel_dp->output_reg;
		2307	}
		2308
		2309	return -1;
		2310	}
2330	Serge	2311
		2312	/* check the VBT to see whether the eDP is on DP-D port */
		2313	bool intel_dpd_is_edp(struct drm_device *dev)
		2314	{
		2315	struct drm_i915_private *dev_priv = dev->dev_private;
		2316	struct child_device_config *p_child;
		2317	int i;
		2318
		2319	if (!dev_priv->child_dev_num)
		2320	return false;
		2321
		2322	for (i = 0; i < dev_priv->child_dev_num; i++) {
		2323	p_child = dev_priv->child_dev + i;
		2324
		2325	if (p_child->dvo_port == PORT_IDPD &&
		2326	p_child->device_type == DEVICE_TYPE_eDP)
		2327	return true;
		2328	}
		2329	return false;
		2330	}
		2331
		2332	static void
		2333	intel_dp_add_properties(struct intel_dp intel_dp, struct drm_connector connector)
		2334	{
		2335	intel_attach_force_audio_property(connector);
		2336	intel_attach_broadcast_rgb_property(connector);
		2337	}
		2338
		2339	void
		2340	intel_dp_init(struct drm_device *dev, int output_reg)
		2341	{
		2342	struct drm_i915_private *dev_priv = dev->dev_private;
		2343	struct drm_connector *connector;
		2344	struct intel_dp *intel_dp;
		2345	struct intel_encoder *intel_encoder;
		2346	struct intel_connector *intel_connector;
		2347	const char *name = NULL;
		2348	int type;
		2349
		2350	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
		2351	if (!intel_dp)
		2352	return;
		2353
		2354	intel_dp->output_reg = output_reg;
		2355	intel_dp->dpms_mode = -1;
		2356
		2357	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
		2358	if (!intel_connector) {
		2359	kfree(intel_dp);
		2360	return;
		2361	}
		2362	intel_encoder = &intel_dp->base;
		2363
		2364	if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
		2365	if (intel_dpd_is_edp(dev))
		2366	intel_dp->is_pch_edp = true;
		2367
		2368	if (output_reg == DP_A \|\| is_pch_edp(intel_dp)) {
		2369	type = DRM_MODE_CONNECTOR_eDP;
		2370	intel_encoder->type = INTEL_OUTPUT_EDP;
		2371	} else {
		2372	type = DRM_MODE_CONNECTOR_DisplayPort;
		2373	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		2374	}
		2375
		2376	connector = &intel_connector->base;
		2377	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
		2378	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
		2379
		2380	connector->polled = DRM_CONNECTOR_POLL_HPD;
		2381
		2382	if (output_reg == DP_B \|\| output_reg == PCH_DP_B)
		2383	intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
		2384	else if (output_reg == DP_C \|\| output_reg == PCH_DP_C)
		2385	intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
		2386	else if (output_reg == DP_D \|\| output_reg == PCH_DP_D)
		2387	intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
		2388
2342	Serge	2389	if (is_edp(intel_dp)) {
2330	Serge	2390	intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2342	Serge	2391	// INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
		2392	// ironlake_panel_vdd_work);
		2393	}
2330	Serge	2394
2342	Serge	2395	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
2330	Serge	2396	connector->interlace_allowed = true;
		2397	connector->doublescan_allowed = 0;
		2398
		2399	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
		2400	DRM_MODE_ENCODER_TMDS);
		2401	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
		2402
		2403	intel_connector_attach_encoder(intel_connector, intel_encoder);
		2404	drm_sysfs_connector_add(connector);
		2405
		2406	/* Set up the DDC bus. */
		2407	switch (output_reg) {
		2408	case DP_A:
		2409	name = "DPDDC-A";
		2410	break;
		2411	case DP_B:
		2412	case PCH_DP_B:
		2413	dev_priv->hotplug_supported_mask \|=
		2414	HDMIB_HOTPLUG_INT_STATUS;
		2415	name = "DPDDC-B";
		2416	break;
		2417	case DP_C:
		2418	case PCH_DP_C:
		2419	dev_priv->hotplug_supported_mask \|=
		2420	HDMIC_HOTPLUG_INT_STATUS;
		2421	name = "DPDDC-C";
		2422	break;
		2423	case DP_D:
		2424	case PCH_DP_D:
		2425	dev_priv->hotplug_supported_mask \|=
		2426	HDMID_HOTPLUG_INT_STATUS;
		2427	name = "DPDDC-D";
		2428	break;
		2429	}
		2430
		2431	/* Cache some DPCD data in the eDP case */
		2432	if (is_edp(intel_dp)) {
		2433	bool ret;
2342	Serge	2434	struct edp_power_seq cur, vbt;
		2435	u32 pp_on, pp_off, pp_div;
2330	Serge	2436
		2437	pp_on = I915_READ(PCH_PP_ON_DELAYS);
2342	Serge	2438	pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2330	Serge	2439	pp_div = I915_READ(PCH_PP_DIVISOR);
		2440
2342	Serge	2441	/* Pull timing values out of registers */
		2442	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		2443	PANEL_POWER_UP_DELAY_SHIFT;
2330	Serge	2444
2342	Serge	2445	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		2446	PANEL_LIGHT_ON_DELAY_SHIFT;
		2447
		2448	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		2449	PANEL_LIGHT_OFF_DELAY_SHIFT;
		2450
		2451	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		2452	PANEL_POWER_DOWN_DELAY_SHIFT;
		2453
		2454	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		2455	PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
		2456
		2457	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		2458	cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
		2459
		2460	vbt = dev_priv->edp.pps;
		2461
		2462	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		2463	vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
		2464
		2465	#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
		2466
		2467	intel_dp->panel_power_up_delay = get_delay(t1_t3);
		2468	intel_dp->backlight_on_delay = get_delay(t8);
		2469	intel_dp->backlight_off_delay = get_delay(t9);
		2470	intel_dp->panel_power_down_delay = get_delay(t10);
		2471	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
		2472
		2473	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		2474	intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		2475	intel_dp->panel_power_cycle_delay);
		2476
		2477	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		2478	intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
		2479
2330	Serge	2480	ironlake_edp_panel_vdd_on(intel_dp);
		2481	ret = intel_dp_get_dpcd(intel_dp);
2342	Serge	2482	ironlake_edp_panel_vdd_off(intel_dp, false);
		2483
2330	Serge	2484	if (ret) {
		2485	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		2486	dev_priv->no_aux_handshake =
		2487	intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
		2488	DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		2489	} else {
		2490	/* if this fails, presume the device is a ghost */
		2491	DRM_INFO("failed to retrieve link info, disabling eDP\n");
		2492	intel_dp_encoder_destroy(&intel_dp->base.base);
		2493	intel_dp_destroy(&intel_connector->base);
		2494	return;
		2495	}
		2496	}
		2497
2342	Serge	2498	intel_dp_i2c_init(intel_dp, intel_connector, name);
		2499
2330	Serge	2500	intel_encoder->hot_plug = intel_dp_hot_plug;
		2501
		2502	if (is_edp(intel_dp)) {
		2503	dev_priv->int_edp_connector = connector;
		2504	intel_panel_setup_backlight(dev);
		2505	}
		2506
		2507	intel_dp_add_properties(intel_dp, connector);
		2508
		2509	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		2510	* 0xd. Failure to do so will result in spurious interrupts being
		2511	* generated on the port when a cable is not attached.
		2512	*/
		2513	if (IS_G4X(dev) && !IS_GM45(dev)) {
		2514	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		2515	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		2516	}
		2517	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c @ 2360 – Rev 2351