WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_dp.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Keith Packard
		25	*
		26	*/
		27
		28	#include
2330	Serge	29	#include
2327	Serge	30	#include "drmP.h"
		31	#include "drm.h"
		32	#include "drm_crtc.h"
		33	#include "drm_crtc_helper.h"
		34	#include "intel_drv.h"
2330	Serge	35	#include "i915_drm.h"
2327	Serge	36	#include "i915_drv.h"
		37	#include "drm_dp_helper.h"
		38
2342	Serge	39	#define DP_RECEIVER_CAP_SIZE 0xf
2327	Serge	40	#define DP_LINK_STATUS_SIZE 6
		41	#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
		42
		43	#define DP_LINK_CONFIGURATION_SIZE 9
		44
		45	struct intel_dp {
		46	struct intel_encoder base;
		47	uint32_t output_reg;
		48	uint32_t DP;
		49	uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
		50	bool has_audio;
		51	int force_audio;
		52	uint32_t color_range;
		53	int dpms_mode;
		54	uint8_t link_bw;
		55	uint8_t lane_count;
2342	Serge	56	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
2327	Serge	57	struct i2c_adapter adapter;
		58	struct i2c_algo_dp_aux_data algo;
		59	bool is_pch_edp;
		60	uint8_t train_set[4];
2342	Serge	61	int panel_power_up_delay;
		62	int panel_power_down_delay;
		63	int panel_power_cycle_delay;
		64	int backlight_on_delay;
		65	int backlight_off_delay;
		66	struct drm_display_mode panel_fixed_mode; / for eDP */
		67	bool want_panel_vdd;
2327	Serge	68	};
		69
		70	/**
		71	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
		72	* @intel_dp: DP struct
		73	*
		74	* If a CPU or PCH DP output is attached to an eDP panel, this function
		75	* will return true, and false otherwise.
		76	*/
		77	static bool is_edp(struct intel_dp *intel_dp)
		78	{
		79	return intel_dp->base.type == INTEL_OUTPUT_EDP;
		80	}
		81
		82	/**
		83	* is_pch_edp - is the port on the PCH and attached to an eDP panel?
		84	* @intel_dp: DP struct
		85	*
		86	* Returns true if the given DP struct corresponds to a PCH DP port attached
		87	* to an eDP panel, false otherwise. Helpful for determining whether we
		88	* may need FDI resources for a given DP output or not.
		89	*/
		90	static bool is_pch_edp(struct intel_dp *intel_dp)
		91	{
		92	return intel_dp->is_pch_edp;
		93	}
		94
2342	Serge	95	/**
		96	* is_cpu_edp - is the port on the CPU and attached to an eDP panel?
		97	* @intel_dp: DP struct
		98	*
		99	* Returns true if the given DP struct corresponds to a CPU eDP port.
		100	*/
		101	static bool is_cpu_edp(struct intel_dp *intel_dp)
		102	{
		103	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
		104	}
		105
2327	Serge	106	static struct intel_dp enc_to_intel_dp(struct drm_encoder encoder)
		107	{
		108	return container_of(encoder, struct intel_dp, base.base);
		109	}
		110
2330	Serge	111	static struct intel_dp intel_attached_dp(struct drm_connector connector)
		112	{
		113	return container_of(intel_attached_encoder(connector),
		114	struct intel_dp, base);
		115	}
2327	Serge	116
		117	/**
		118	* intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
		119	* @encoder: DRM encoder
		120	*
		121	* Return true if @encoder corresponds to a PCH attached eDP panel. Needed
		122	* by intel_display.c.
		123	*/
		124	bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
		125	{
		126	struct intel_dp *intel_dp;
		127
		128	if (!encoder)
		129	return false;
		130
		131	intel_dp = enc_to_intel_dp(encoder);
		132
		133	return is_pch_edp(intel_dp);
		134	}
		135
2330	Serge	136	static void intel_dp_start_link_train(struct intel_dp *intel_dp);
		137	static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
		138	static void intel_dp_link_down(struct intel_dp *intel_dp);
		139
2327	Serge	140	void
2342	Serge	141	intel_edp_link_config(struct intel_encoder *intel_encoder,
2327	Serge	142	int lane_num, int link_bw)
		143	{
		144	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		145
		146	*lane_num = intel_dp->lane_count;
		147	if (intel_dp->link_bw == DP_LINK_BW_1_62)
		148	*link_bw = 162000;
		149	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
		150	*link_bw = 270000;
		151	}
		152
2330	Serge	153	static int
		154	intel_dp_max_lane_count(struct intel_dp *intel_dp)
		155	{
2342	Serge	156	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
2330	Serge	157	switch (max_lane_count) {
		158	case 1: case 2: case 4:
		159	break;
		160	default:
		161	max_lane_count = 4;
		162	}
		163	return max_lane_count;
		164	}
2327	Serge	165
2330	Serge	166	static int
		167	intel_dp_max_link_bw(struct intel_dp *intel_dp)
		168	{
		169	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
2327	Serge	170
2330	Serge	171	switch (max_link_bw) {
		172	case DP_LINK_BW_1_62:
		173	case DP_LINK_BW_2_7:
		174	break;
		175	default:
		176	max_link_bw = DP_LINK_BW_1_62;
		177	break;
		178	}
		179	return max_link_bw;
		180	}
2327	Serge	181
2330	Serge	182	static int
		183	intel_dp_link_clock(uint8_t link_bw)
		184	{
		185	if (link_bw == DP_LINK_BW_2_7)
		186	return 270000;
		187	else
		188	return 162000;
		189	}
2327	Serge	190
2342	Serge	191	/*
		192	* The units on the numbers in the next two are... bizarre. Examples will
		193	* make it clearer; this one parallels an example in the eDP spec.
		194	*
		195	* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
		196	*
		197	* 270000 * 1 * 8 / 10 == 216000
		198	*
		199	* The actual data capacity of that configuration is 2.16Gbit/s, so the
		200	* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
		201	* or equivalently, kilopixels per second - so for 1680x1050R it'd be
		202	* 119000. At 18bpp that's 2142000 kilobits per second.
		203	*
		204	* Thus the strange-looking division by 10 in intel_dp_link_required, to
		205	* get the result in decakilobits instead of kilobits.
		206	*/
		207
2330	Serge	208	static int
2342	Serge	209	intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
2330	Serge	210	{
		211	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		212	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		213	int bpp = 24;
2327	Serge	214
2342	Serge	215	if (check_bpp)
		216	bpp = check_bpp;
		217	else if (intel_crtc)
2330	Serge	218	bpp = intel_crtc->bpp;
2327	Serge	219
2342	Serge	220	return (pixel_clock * bpp + 9) / 10;
2330	Serge	221	}
2327	Serge	222
2330	Serge	223	static int
		224	intel_dp_max_data_rate(int max_link_clock, int max_lanes)
		225	{
		226	return (max_link_clock * max_lanes * 8) / 10;
		227	}
2327	Serge	228
2330	Serge	229	static int
		230	intel_dp_mode_valid(struct drm_connector *connector,
		231	struct drm_display_mode *mode)
		232	{
		233	struct intel_dp *intel_dp = intel_attached_dp(connector);
		234	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
		235	int max_lanes = intel_dp_max_lane_count(intel_dp);
2342	Serge	236	int max_rate, mode_rate;
2327	Serge	237
2342	Serge	238	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		239	if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
2330	Serge	240	return MODE_PANEL;
2327	Serge	241
2342	Serge	242	if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
2330	Serge	243	return MODE_PANEL;
		244	}
2327	Serge	245
2342	Serge	246	mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
		247	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
		248
		249	if (mode_rate > max_rate) {
		250	mode_rate = intel_dp_link_required(intel_dp,
		251	mode->clock, 18);
		252	if (mode_rate > max_rate)
2330	Serge	253	return MODE_CLOCK_HIGH;
2342	Serge	254	else
		255	mode->private_flags \|= INTEL_MODE_DP_FORCE_6BPC;
		256	}
2327	Serge	257
2330	Serge	258	if (mode->clock < 10000)
		259	return MODE_CLOCK_LOW;
		260
		261	return MODE_OK;
		262	}
		263
		264	static uint32_t
		265	pack_aux(uint8_t *src, int src_bytes)
		266	{
		267	int i;
		268	uint32_t v = 0;
		269
		270	if (src_bytes > 4)
		271	src_bytes = 4;
		272	for (i = 0; i < src_bytes; i++)
		273	v \|= ((uint32_t) src[i]) << ((3-i) * 8);
		274	return v;
		275	}
		276
		277	static void
		278	unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
		279	{
		280	int i;
		281	if (dst_bytes > 4)
		282	dst_bytes = 4;
		283	for (i = 0; i < dst_bytes; i++)
		284	dst[i] = src >> ((3-i) * 8);
		285	}
		286
		287	/* hrawclock is 1/4 the FSB frequency */
		288	static int
		289	intel_hrawclk(struct drm_device *dev)
		290	{
		291	struct drm_i915_private *dev_priv = dev->dev_private;
		292	uint32_t clkcfg;
		293
		294	clkcfg = I915_READ(CLKCFG);
		295	switch (clkcfg & CLKCFG_FSB_MASK) {
		296	case CLKCFG_FSB_400:
		297	return 100;
		298	case CLKCFG_FSB_533:
		299	return 133;
		300	case CLKCFG_FSB_667:
		301	return 166;
		302	case CLKCFG_FSB_800:
		303	return 200;
		304	case CLKCFG_FSB_1067:
		305	return 266;
		306	case CLKCFG_FSB_1333:
		307	return 333;
		308	/* these two are just a guess; one of them might be right */
		309	case CLKCFG_FSB_1600:
		310	case CLKCFG_FSB_1600_ALT:
		311	return 400;
		312	default:
		313	return 133;
		314	}
		315	}
		316
2342	Serge	317	static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
		318	{
		319	struct drm_device *dev = intel_dp->base.base.dev;
		320	struct drm_i915_private *dev_priv = dev->dev_private;
		321
		322	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
		323	}
		324
		325	static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
		326	{
		327	struct drm_device *dev = intel_dp->base.base.dev;
		328	struct drm_i915_private *dev_priv = dev->dev_private;
		329
		330	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
		331	}
		332
		333	static void
		334	intel_dp_check_edp(struct intel_dp *intel_dp)
		335	{
		336	struct drm_device *dev = intel_dp->base.base.dev;
		337	struct drm_i915_private *dev_priv = dev->dev_private;
		338
		339	if (!is_edp(intel_dp))
		340	return;
		341	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
		342	WARN(1, "eDP powered off while attempting aux channel communication.\n");
		343	DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
		344	I915_READ(PCH_PP_STATUS),
		345	I915_READ(PCH_PP_CONTROL));
		346	}
		347	}
		348
2330	Serge	349	static int
		350	intel_dp_aux_ch(struct intel_dp *intel_dp,
		351	uint8_t *send, int send_bytes,
		352	uint8_t *recv, int recv_size)
		353	{
		354	uint32_t output_reg = intel_dp->output_reg;
		355	struct drm_device *dev = intel_dp->base.base.dev;
		356	struct drm_i915_private *dev_priv = dev->dev_private;
		357	uint32_t ch_ctl = output_reg + 0x10;
		358	uint32_t ch_data = ch_ctl + 4;
		359	int i;
		360	int recv_bytes;
		361	uint32_t status;
		362	uint32_t aux_clock_divider;
		363	int try, precharge;
		364
2342	Serge	365	intel_dp_check_edp(intel_dp);
2330	Serge	366	/* The clock divider is based off the hrawclk,
		367	* and would like to run at 2MHz. So, take the
		368	* hrawclk value and divide by 2 and use that
		369	*
		370	* Note that PCH attached eDP panels should use a 125MHz input
		371	* clock divider.
		372	*/
2342	Serge	373	if (is_cpu_edp(intel_dp)) {
		374	if (IS_GEN6(dev) \|\| IS_GEN7(dev))
		375	aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
2330	Serge	376	else
		377	aux_clock_divider = 225; /* eDP input clock at 450Mhz */
		378	} else if (HAS_PCH_SPLIT(dev))
		379	aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
		380	else
		381	aux_clock_divider = intel_hrawclk(dev) / 2;
		382
		383	if (IS_GEN6(dev))
		384	precharge = 3;
		385	else
		386	precharge = 5;
		387
		388	/* Try to wait for any previous AUX channel activity */
		389	for (try = 0; try < 3; try++) {
		390	status = I915_READ(ch_ctl);
		391	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		392	break;
		393	msleep(1);
		394	}
		395
		396	if (try == 3) {
		397	WARN(1, "dp_aux_ch not started status 0x%08x\n",
		398	I915_READ(ch_ctl));
		399	return -EBUSY;
		400	}
		401
		402	/* Must try at least 3 times according to DP spec */
		403	for (try = 0; try < 5; try++) {
		404	/* Load the send data into the aux channel data registers */
		405	for (i = 0; i < send_bytes; i += 4)
		406	I915_WRITE(ch_data + i,
		407	pack_aux(send + i, send_bytes - i));
		408
		409	/* Send the command and wait for it to complete */
		410	I915_WRITE(ch_ctl,
		411	DP_AUX_CH_CTL_SEND_BUSY \|
		412	DP_AUX_CH_CTL_TIME_OUT_400us \|
		413	(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		414	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		415	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) \|
		416	DP_AUX_CH_CTL_DONE \|
		417	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		418	DP_AUX_CH_CTL_RECEIVE_ERROR);
		419	for (;;) {
		420	status = I915_READ(ch_ctl);
		421	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		422	break;
		423	udelay(100);
		424	}
		425
		426	/* Clear done status and any errors */
		427	I915_WRITE(ch_ctl,
		428	status \|
		429	DP_AUX_CH_CTL_DONE \|
		430	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		431	DP_AUX_CH_CTL_RECEIVE_ERROR);
		432	if (status & DP_AUX_CH_CTL_DONE)
		433	break;
		434	}
		435
		436	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		437	DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
		438	return -EBUSY;
		439	}
		440
		441	/* Check for timeout or receive error.
		442	* Timeouts occur when the sink is not connected
		443	*/
		444	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
		445	DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
		446	return -EIO;
		447	}
		448
		449	/* Timeouts occur when the device isn't connected, so they're
		450	* "normal" -- don't fill the kernel log with these */
		451	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
		452	DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
		453	return -ETIMEDOUT;
		454	}
		455
		456	/* Unload any bytes sent back from the other side */
		457	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		458	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
		459	if (recv_bytes > recv_size)
		460	recv_bytes = recv_size;
		461
		462	for (i = 0; i < recv_bytes; i += 4)
		463	unpack_aux(I915_READ(ch_data + i),
		464	recv + i, recv_bytes - i);
		465
		466	return recv_bytes;
		467	}
		468
		469	/* Write data to the aux channel in native mode */
		470	static int
		471	intel_dp_aux_native_write(struct intel_dp *intel_dp,
		472	uint16_t address, uint8_t *send, int send_bytes)
		473	{
		474	int ret;
		475	uint8_t msg[20];
		476	int msg_bytes;
		477	uint8_t ack;
		478
2342	Serge	479	intel_dp_check_edp(intel_dp);
2330	Serge	480	if (send_bytes > 16)
		481	return -1;
		482	msg[0] = AUX_NATIVE_WRITE << 4;
		483	msg[1] = address >> 8;
		484	msg[2] = address & 0xff;
		485	msg[3] = send_bytes - 1;
		486	memcpy(&msg[4], send, send_bytes);
		487	msg_bytes = send_bytes + 4;
		488	for (;;) {
		489	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
		490	if (ret < 0)
		491	return ret;
		492	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		493	break;
		494	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		495	udelay(100);
		496	else
		497	return -EIO;
		498	}
		499	return send_bytes;
		500	}
		501
		502	/* Write a single byte to the aux channel in native mode */
		503	static int
		504	intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
		505	uint16_t address, uint8_t byte)
		506	{
		507	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
		508	}
		509
		510	/* read bytes from a native aux channel */
		511	static int
		512	intel_dp_aux_native_read(struct intel_dp *intel_dp,
		513	uint16_t address, uint8_t *recv, int recv_bytes)
		514	{
		515	uint8_t msg[4];
		516	int msg_bytes;
		517	uint8_t reply[20];
		518	int reply_bytes;
		519	uint8_t ack;
		520	int ret;
		521
2342	Serge	522	intel_dp_check_edp(intel_dp);
2330	Serge	523	msg[0] = AUX_NATIVE_READ << 4;
		524	msg[1] = address >> 8;
		525	msg[2] = address & 0xff;
		526	msg[3] = recv_bytes - 1;
		527
		528	msg_bytes = 4;
		529	reply_bytes = recv_bytes + 1;
		530
		531	for (;;) {
		532	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
		533	reply, reply_bytes);
		534	if (ret == 0)
		535	return -EPROTO;
		536	if (ret < 0)
		537	return ret;
		538	ack = reply[0];
		539	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
		540	memcpy(recv, reply + 1, ret - 1);
		541	return ret - 1;
		542	}
		543	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		544	udelay(100);
		545	else
		546	return -EIO;
		547	}
		548	}
		549
		550	static int
		551	intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		552	uint8_t write_byte, uint8_t *read_byte)
		553	{
		554	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
		555	struct intel_dp *intel_dp = container_of(adapter,
		556	struct intel_dp,
		557	adapter);
		558	uint16_t address = algo_data->address;
		559	uint8_t msg[5];
		560	uint8_t reply[2];
		561	unsigned retry;
		562	int msg_bytes;
		563	int reply_bytes;
		564	int ret;
		565
2342	Serge	566	intel_dp_check_edp(intel_dp);
2330	Serge	567	/* Set up the command byte */
		568	if (mode & MODE_I2C_READ)
		569	msg[0] = AUX_I2C_READ << 4;
		570	else
		571	msg[0] = AUX_I2C_WRITE << 4;
		572
		573	if (!(mode & MODE_I2C_STOP))
		574	msg[0] \|= AUX_I2C_MOT << 4;
		575
		576	msg[1] = address >> 8;
		577	msg[2] = address;
		578
		579	switch (mode) {
		580	case MODE_I2C_WRITE:
		581	msg[3] = 0;
		582	msg[4] = write_byte;
		583	msg_bytes = 5;
		584	reply_bytes = 1;
		585	break;
		586	case MODE_I2C_READ:
		587	msg[3] = 0;
		588	msg_bytes = 4;
		589	reply_bytes = 2;
		590	break;
		591	default:
		592	msg_bytes = 3;
		593	reply_bytes = 1;
		594	break;
		595	}
		596
		597	for (retry = 0; retry < 5; retry++) {
		598	ret = intel_dp_aux_ch(intel_dp,
		599	msg, msg_bytes,
		600	reply, reply_bytes);
		601	if (ret < 0) {
		602	DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
		603	return ret;
		604	}
		605
		606	switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		607	case AUX_NATIVE_REPLY_ACK:
		608	/* I2C-over-AUX Reply field is only valid
		609	* when paired with AUX ACK.
		610	*/
		611	break;
		612	case AUX_NATIVE_REPLY_NACK:
		613	DRM_DEBUG_KMS("aux_ch native nack\n");
		614	return -EREMOTEIO;
		615	case AUX_NATIVE_REPLY_DEFER:
		616	udelay(100);
		617	continue;
		618	default:
		619	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
		620	reply[0]);
		621	return -EREMOTEIO;
		622	}
		623
		624	switch (reply[0] & AUX_I2C_REPLY_MASK) {
		625	case AUX_I2C_REPLY_ACK:
		626	if (mode == MODE_I2C_READ) {
		627	*read_byte = reply[1];
		628	}
		629	return reply_bytes - 1;
		630	case AUX_I2C_REPLY_NACK:
		631	DRM_DEBUG_KMS("aux_i2c nack\n");
		632	return -EREMOTEIO;
		633	case AUX_I2C_REPLY_DEFER:
		634	DRM_DEBUG_KMS("aux_i2c defer\n");
		635	udelay(100);
		636	break;
		637	default:
		638	DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
		639	return -EREMOTEIO;
		640	}
		641	}
		642
		643	DRM_ERROR("too many retries, giving up\n");
		644	return -EREMOTEIO;
		645	}
		646
2342	Serge	647	static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
		648	static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
		649
2330	Serge	650	static int
		651	intel_dp_i2c_init(struct intel_dp *intel_dp,
		652	struct intel_connector intel_connector, const char name)
		653	{
2342	Serge	654	int ret;
		655
2330	Serge	656	DRM_DEBUG_KMS("i2c_init %s\n", name);
		657	intel_dp->algo.running = false;
		658	intel_dp->algo.address = 0;
		659	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
		660
2342	Serge	661	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
2330	Serge	662	// intel_dp->adapter.owner = THIS_MODULE;
		663	intel_dp->adapter.class = I2C_CLASS_DDC;
2342	Serge	664	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
2330	Serge	665	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
		666	intel_dp->adapter.algo_data = &intel_dp->algo;
		667	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
		668
2342	Serge	669	ironlake_edp_panel_vdd_on(intel_dp);
		670	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
		671	ironlake_edp_panel_vdd_off(intel_dp, false);
		672	return ret;
2330	Serge	673	}
		674
		675	static bool
		676	intel_dp_mode_fixup(struct drm_encoder encoder, struct drm_display_mode mode,
		677	struct drm_display_mode *adjusted_mode)
		678	{
		679	struct drm_device *dev = encoder->dev;
		680	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		681	int lane_count, clock;
		682	int max_lane_count = intel_dp_max_lane_count(intel_dp);
		683	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
2342	Serge	684	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
2330	Serge	685	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
		686
2342	Serge	687	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		688	intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
2330	Serge	689	intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
		690	mode, adjusted_mode);
		691	/*
		692	* the mode->clock is used to calculate the Data&Link M/N
		693	* of the pipe. For the eDP the fixed clock should be used.
		694	*/
2342	Serge	695	mode->clock = intel_dp->panel_fixed_mode->clock;
2330	Serge	696	}
		697
		698	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		699	for (clock = 0; clock <= max_clock; clock++) {
		700	int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
		701
2342	Serge	702	if (intel_dp_link_required(intel_dp, mode->clock, bpp)
2330	Serge	703	<= link_avail) {
		704	intel_dp->link_bw = bws[clock];
		705	intel_dp->lane_count = lane_count;
		706	adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
		707	DRM_DEBUG_KMS("Display port link bw %02x lane "
		708	"count %d clock %d\n",
		709	intel_dp->link_bw, intel_dp->lane_count,
		710	adjusted_mode->clock);
		711	return true;
		712	}
		713	}
		714	}
		715
		716	return false;
		717	}
		718
2327	Serge	719	struct intel_dp_m_n {
		720	uint32_t tu;
		721	uint32_t gmch_m;
		722	uint32_t gmch_n;
		723	uint32_t link_m;
		724	uint32_t link_n;
		725	};
		726
		727	static void
		728	intel_reduce_ratio(uint32_t num, uint32_t den)
		729	{
		730	while (num > 0xffffff \|\| den > 0xffffff) {
		731	*num >>= 1;
		732	*den >>= 1;
		733	}
		734	}
		735
		736	static void
		737	intel_dp_compute_m_n(int bpp,
		738	int nlanes,
		739	int pixel_clock,
		740	int link_clock,
		741	struct intel_dp_m_n *m_n)
		742	{
		743	m_n->tu = 64;
		744	m_n->gmch_m = (pixel_clock * bpp) >> 3;
		745	m_n->gmch_n = link_clock * nlanes;
		746	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		747	m_n->link_m = pixel_clock;
		748	m_n->link_n = link_clock;
		749	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
		750	}
		751
		752	void
		753	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
		754	struct drm_display_mode *adjusted_mode)
		755	{
		756	struct drm_device *dev = crtc->dev;
		757	struct drm_mode_config *mode_config = &dev->mode_config;
		758	struct drm_encoder *encoder;
		759	struct drm_i915_private *dev_priv = dev->dev_private;
		760	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		761	int lane_count = 4;
		762	struct intel_dp_m_n m_n;
		763	int pipe = intel_crtc->pipe;
		764
		765	/*
		766	* Find the lane count in the intel_encoder private
		767	*/
		768	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		769	struct intel_dp *intel_dp;
		770
		771	if (encoder->crtc != crtc)
		772	continue;
		773
		774	intel_dp = enc_to_intel_dp(encoder);
2342	Serge	775	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT \|\|
		776	intel_dp->base.type == INTEL_OUTPUT_EDP)
		777	{
2327	Serge	778	lane_count = intel_dp->lane_count;
		779	break;
		780	}
		781	}
		782
		783	/*
		784	* Compute the GMCH and Link ratios. The '3' here is
		785	* the number of bytes_per_pixel post-LUT, which we always
		786	* set up for 8-bits of R/G/B, or 3 bytes total.
		787	*/
		788	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
		789	mode->clock, adjusted_mode->clock, &m_n);
		790
		791	if (HAS_PCH_SPLIT(dev)) {
		792	I915_WRITE(TRANSDATA_M1(pipe),
		793	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		794	m_n.gmch_m);
		795	I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		796	I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		797	I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
		798	} else {
		799	I915_WRITE(PIPE_GMCH_DATA_M(pipe),
		800	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		801	m_n.gmch_m);
		802	I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		803	I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		804	I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
		805	}
		806	}
		807
2342	Serge	808	static void ironlake_edp_pll_on(struct drm_encoder *encoder);
		809	static void ironlake_edp_pll_off(struct drm_encoder *encoder);
		810
2330	Serge	811	static void
		812	intel_dp_mode_set(struct drm_encoder encoder, struct drm_display_mode mode,
		813	struct drm_display_mode *adjusted_mode)
		814	{
		815	struct drm_device *dev = encoder->dev;
2342	Serge	816	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	817	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		818	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		819	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	820
2342	Serge	821	/* Turn on the eDP PLL if needed */
		822	if (is_edp(intel_dp)) {
		823	if (!is_pch_edp(intel_dp))
		824	ironlake_edp_pll_on(encoder);
		825	else
		826	ironlake_edp_pll_off(encoder);
		827	}
2327	Serge	828
2342	Serge	829	/*
		830	* There are four kinds of DP registers:
		831	*
		832	* IBX PCH
		833	* SNB CPU
		834	* IVB CPU
		835	* CPT PCH
		836	*
		837	* IBX PCH and CPU are the same for almost everything,
		838	* except that the CPU DP PLL is configured in this
		839	* register
		840	*
		841	* CPT PCH is quite different, having many bits moved
		842	* to the TRANS_DP_CTL register instead. That
		843	* configuration happens (oddly) in ironlake_pch_enable
		844	*/
2327	Serge	845
2342	Serge	846	/* Preserve the BIOS-computed detected bit. This is
		847	* supposed to be read-only.
		848	*/
		849	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
		850	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
2327	Serge	851
2342	Serge	852	/* Handle DP bits in common between all three register formats */
		853
		854	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
		855
2330	Serge	856	switch (intel_dp->lane_count) {
		857	case 1:
		858	intel_dp->DP \|= DP_PORT_WIDTH_1;
		859	break;
		860	case 2:
		861	intel_dp->DP \|= DP_PORT_WIDTH_2;
		862	break;
		863	case 4:
		864	intel_dp->DP \|= DP_PORT_WIDTH_4;
		865	break;
		866	}
2342	Serge	867	if (intel_dp->has_audio) {
		868	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
		869	pipe_name(intel_crtc->pipe));
2330	Serge	870	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
2342	Serge	871	intel_write_eld(encoder, adjusted_mode);
		872	}
2330	Serge	873	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
		874	intel_dp->link_configuration[0] = intel_dp->link_bw;
		875	intel_dp->link_configuration[1] = intel_dp->lane_count;
		876	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
		877	/*
		878	* Check for DPCD version > 1.1 and enhanced framing support
		879	*/
		880	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		881	(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		882	intel_dp->link_configuration[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
		883	}
2327	Serge	884
2342	Serge	885	/* Split out the IBX/CPU vs CPT settings */
		886
		887	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		888	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		889	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		890	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		891	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		892	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		893
		894	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		895	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		896
		897	intel_dp->DP \|= intel_crtc->pipe << 29;
		898
		899	/* don't miss out required setting for eDP */
		900	intel_dp->DP \|= DP_PLL_ENABLE;
		901	if (adjusted_mode->clock < 200000)
		902	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
		903	else
		904	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		905	} else if (!HAS_PCH_CPT(dev) \|\| is_cpu_edp(intel_dp)) {
		906	intel_dp->DP \|= intel_dp->color_range;
		907
		908	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		909	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		910	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		911	intel_dp->DP \|= DP_SYNC_VS_HIGH;
		912	intel_dp->DP \|= DP_LINK_TRAIN_OFF;
		913
		914	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
		915	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		916
		917	if (intel_crtc->pipe == 1)
2330	Serge	918	intel_dp->DP \|= DP_PIPEB_SELECT;
2327	Serge	919
2342	Serge	920	if (is_cpu_edp(intel_dp)) {
2330	Serge	921	/* don't miss out required setting for eDP */
		922	intel_dp->DP \|= DP_PLL_ENABLE;
		923	if (adjusted_mode->clock < 200000)
		924	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
		925	else
		926	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		927	}
2342	Serge	928	} else {
		929	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		930	}
2330	Serge	931	}
2327	Serge	932
2342	Serge	933	#define IDLE_ON_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		934	#define IDLE_ON_VALUE (PP_ON \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_ON_IDLE)
		935
		936	#define IDLE_OFF_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| 0 \| PP_SEQUENCE_STATE_MASK)
		937	#define IDLE_OFF_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		938
		939	#define IDLE_CYCLE_MASK (PP_ON \| 0 \| PP_SEQUENCE_MASK \| PP_CYCLE_DELAY_ACTIVE \| PP_SEQUENCE_STATE_MASK)
		940	#define IDLE_CYCLE_VALUE (0 \| 0 \| PP_SEQUENCE_NONE \| 0 \| PP_SEQUENCE_STATE_OFF_IDLE)
		941
		942	static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
		943	u32 mask,
		944	u32 value)
		945	{
		946	struct drm_device *dev = intel_dp->base.base.dev;
		947	struct drm_i915_private *dev_priv = dev->dev_private;
		948
		949	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		950	mask, value,
		951	I915_READ(PCH_PP_STATUS),
		952	I915_READ(PCH_PP_CONTROL));
		953
		954	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
		955	DRM_ERROR("Panel status timeout: status %08x control %08x\n",
		956	I915_READ(PCH_PP_STATUS),
		957	I915_READ(PCH_PP_CONTROL));
		958	}
		959	}
		960
		961	static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
		962	{
		963	DRM_DEBUG_KMS("Wait for panel power on\n");
		964	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
		965	}
		966
		967	static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
		968	{
		969	DRM_DEBUG_KMS("Wait for panel power off time\n");
		970	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
		971	}
		972
		973	static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
		974	{
		975	DRM_DEBUG_KMS("Wait for panel power cycle\n");
		976	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
		977	}
		978
		979
		980	/* Read the current pp_control value, unlocking the register if it
		981	* is locked
		982	*/
		983
		984	static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
		985	{
		986	u32 control = I915_READ(PCH_PP_CONTROL);
		987
		988	control &= ~PANEL_UNLOCK_MASK;
		989	control \|= PANEL_UNLOCK_REGS;
		990	return control;
		991	}
		992
2330	Serge	993	static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
		994	{
		995	struct drm_device *dev = intel_dp->base.base.dev;
		996	struct drm_i915_private *dev_priv = dev->dev_private;
		997	u32 pp;
2327	Serge	998
2342	Serge	999	if (!is_edp(intel_dp))
		1000	return;
		1001	DRM_DEBUG_KMS("Turn eDP VDD on\n");
2327	Serge	1002
2342	Serge	1003	WARN(intel_dp->want_panel_vdd,
		1004	"eDP VDD already requested on\n");
		1005
		1006	intel_dp->want_panel_vdd = true;
		1007
		1008	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		1009	DRM_DEBUG_KMS("eDP VDD already on\n");
		1010	return;
		1011	}
		1012
		1013	if (!ironlake_edp_have_panel_power(intel_dp))
		1014	ironlake_wait_panel_power_cycle(intel_dp);
		1015
		1016	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1017	pp \|= EDP_FORCE_VDD;
		1018	I915_WRITE(PCH_PP_CONTROL, pp);
		1019	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1020	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		1021	I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
		1022
		1023	/*
		1024	* If the panel wasn't on, delay before accessing aux channel
		1025	*/
		1026	if (!ironlake_edp_have_panel_power(intel_dp)) {
		1027	DRM_DEBUG_KMS("eDP was not running\n");
		1028	msleep(intel_dp->panel_power_up_delay);
		1029	}
2330	Serge	1030	}
2327	Serge	1031
2342	Serge	1032	static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
2330	Serge	1033	{
		1034	struct drm_device *dev = intel_dp->base.base.dev;
		1035	struct drm_i915_private *dev_priv = dev->dev_private;
		1036	u32 pp;
2327	Serge	1037
2342	Serge	1038	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
		1039	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1040	pp &= ~EDP_FORCE_VDD;
		1041	I915_WRITE(PCH_PP_CONTROL, pp);
		1042	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1043
2330	Serge	1044	/* Make sure sequencer is idle before allowing subsequent activity */
2342	Serge	1045	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		1046	I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
		1047
		1048	msleep(intel_dp->panel_power_down_delay);
		1049	}
2330	Serge	1050	}
2327	Serge	1051
2342	Serge	1052
		1053	static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2330	Serge	1054	{
2342	Serge	1055	if (!is_edp(intel_dp))
		1056	return;
		1057
		1058	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
		1059	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
		1060
		1061	intel_dp->want_panel_vdd = false;
		1062
		1063	if (sync) {
		1064	ironlake_panel_vdd_off_sync(intel_dp);
		1065	} else {
		1066	/*
		1067	* Queue the timer to fire a long
		1068	* time from now (relative to the power down delay)
		1069	* to keep the panel power up across a sequence of operations
		1070	*/
		1071	// schedule_delayed_work(&intel_dp->panel_vdd_work,
		1072	// msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
		1073	}
		1074	}
		1075
		1076	static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
		1077	{
2330	Serge	1078	struct drm_device *dev = intel_dp->base.base.dev;
		1079	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1080	u32 pp;
2327	Serge	1081
2342	Serge	1082	if (!is_edp(intel_dp))
		1083	return;
2327	Serge	1084
2342	Serge	1085	DRM_DEBUG_KMS("Turn eDP power on\n");
2327	Serge	1086
2342	Serge	1087	if (ironlake_edp_have_panel_power(intel_dp)) {
		1088	DRM_DEBUG_KMS("eDP power already on\n");
		1089	return;
		1090	}
		1091
		1092	ironlake_wait_panel_power_cycle(intel_dp);
		1093
		1094	pp = ironlake_get_pp_control(dev_priv);
		1095	if (IS_GEN5(dev)) {
2330	Serge	1096	/* ILK workaround: disable reset around power sequence */
		1097	pp &= ~PANEL_POWER_RESET;
		1098	I915_WRITE(PCH_PP_CONTROL, pp);
		1099	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1100	}
2327	Serge	1101
2342	Serge	1102	pp \|= POWER_TARGET_ON;
		1103	if (!IS_GEN5(dev))
		1104	pp \|= PANEL_POWER_RESET;
		1105
2330	Serge	1106	I915_WRITE(PCH_PP_CONTROL, pp);
		1107	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1108
2342	Serge	1109	ironlake_wait_panel_on(intel_dp);
2327	Serge	1110
2342	Serge	1111	if (IS_GEN5(dev)) {
2330	Serge	1112	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
		1113	I915_WRITE(PCH_PP_CONTROL, pp);
		1114	POSTING_READ(PCH_PP_CONTROL);
2342	Serge	1115	}
2330	Serge	1116	}
2327	Serge	1117
2342	Serge	1118	static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
2330	Serge	1119	{
2342	Serge	1120	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1121	struct drm_i915_private *dev_priv = dev->dev_private;
2342	Serge	1122	u32 pp;
2327	Serge	1123
2342	Serge	1124	if (!is_edp(intel_dp))
		1125	return;
2327	Serge	1126
2342	Serge	1127	DRM_DEBUG_KMS("Turn eDP power off\n");
2327	Serge	1128
2342	Serge	1129	WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
		1130
		1131	pp = ironlake_get_pp_control(dev_priv);
		1132	pp &= ~(POWER_TARGET_ON \| EDP_FORCE_VDD \| PANEL_POWER_RESET \| EDP_BLC_ENABLE);
2330	Serge	1133	I915_WRITE(PCH_PP_CONTROL, pp);
		1134	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	1135
2342	Serge	1136	ironlake_wait_panel_off(intel_dp);
2330	Serge	1137	}
2327	Serge	1138
2342	Serge	1139	static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
2330	Serge	1140	{
2342	Serge	1141	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1142	struct drm_i915_private *dev_priv = dev->dev_private;
		1143	u32 pp;
2327	Serge	1144
2342	Serge	1145	if (!is_edp(intel_dp))
		1146	return;
		1147
2330	Serge	1148	DRM_DEBUG_KMS("\n");
		1149	/*
		1150	* If we enable the backlight right away following a panel power
		1151	* on, we may see slight flicker as the panel syncs with the eDP
		1152	* link. So delay a bit to make sure the image is solid before
		1153	* allowing it to appear.
		1154	*/
2342	Serge	1155	msleep(intel_dp->backlight_on_delay);
		1156	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1157	pp \|= EDP_BLC_ENABLE;
		1158	I915_WRITE(PCH_PP_CONTROL, pp);
2342	Serge	1159	POSTING_READ(PCH_PP_CONTROL);
2330	Serge	1160	}
2327	Serge	1161
2342	Serge	1162	static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
2330	Serge	1163	{
2342	Serge	1164	struct drm_device *dev = intel_dp->base.base.dev;
2330	Serge	1165	struct drm_i915_private *dev_priv = dev->dev_private;
		1166	u32 pp;
2327	Serge	1167
2342	Serge	1168	if (!is_edp(intel_dp))
		1169	return;
		1170
2330	Serge	1171	DRM_DEBUG_KMS("\n");
2342	Serge	1172	pp = ironlake_get_pp_control(dev_priv);
2330	Serge	1173	pp &= ~EDP_BLC_ENABLE;
		1174	I915_WRITE(PCH_PP_CONTROL, pp);
2342	Serge	1175	POSTING_READ(PCH_PP_CONTROL);
		1176	msleep(intel_dp->backlight_off_delay);
2330	Serge	1177	}
2327	Serge	1178
2330	Serge	1179	static void ironlake_edp_pll_on(struct drm_encoder *encoder)
		1180	{
		1181	struct drm_device *dev = encoder->dev;
		1182	struct drm_i915_private *dev_priv = dev->dev_private;
		1183	u32 dpa_ctl;
2327	Serge	1184
2330	Serge	1185	DRM_DEBUG_KMS("\n");
		1186	dpa_ctl = I915_READ(DP_A);
		1187	dpa_ctl \|= DP_PLL_ENABLE;
		1188	I915_WRITE(DP_A, dpa_ctl);
		1189	POSTING_READ(DP_A);
		1190	udelay(200);
		1191	}
2327	Serge	1192
2330	Serge	1193	static void ironlake_edp_pll_off(struct drm_encoder *encoder)
		1194	{
		1195	struct drm_device *dev = encoder->dev;
		1196	struct drm_i915_private *dev_priv = dev->dev_private;
		1197	u32 dpa_ctl;
2327	Serge	1198
2330	Serge	1199	dpa_ctl = I915_READ(DP_A);
		1200	dpa_ctl &= ~DP_PLL_ENABLE;
		1201	I915_WRITE(DP_A, dpa_ctl);
		1202	POSTING_READ(DP_A);
		1203	udelay(200);
		1204	}
2327	Serge	1205
2330	Serge	1206	/* If the sink supports it, try to set the power state appropriately */
		1207	static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
		1208	{
		1209	int ret, i;
2327	Serge	1210
2330	Serge	1211	/* Should have a valid DPCD by this point */
		1212	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		1213	return;
2327	Serge	1214
2330	Serge	1215	if (mode != DRM_MODE_DPMS_ON) {
		1216	ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
		1217	DP_SET_POWER_D3);
		1218	if (ret != 1)
		1219	DRM_DEBUG_DRIVER("failed to write sink power state\n");
		1220	} else {
		1221	/*
		1222	* When turning on, we need to retry for 1ms to give the sink
		1223	* time to wake up.
		1224	*/
		1225	for (i = 0; i < 3; i++) {
		1226	ret = intel_dp_aux_native_write_1(intel_dp,
		1227	DP_SET_POWER,
		1228	DP_SET_POWER_D0);
		1229	if (ret == 1)
		1230	break;
		1231	msleep(1);
		1232	}
		1233	}
		1234	}
2327	Serge	1235
2330	Serge	1236	static void intel_dp_prepare(struct drm_encoder *encoder)
		1237	{
		1238	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2327	Serge	1239
2342	Serge	1240	ironlake_edp_backlight_off(intel_dp);
		1241	ironlake_edp_panel_off(intel_dp);
		1242
2330	Serge	1243	/* Wake up the sink first */
2342	Serge	1244	ironlake_edp_panel_vdd_on(intel_dp);
2330	Serge	1245	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2342	Serge	1246	intel_dp_link_down(intel_dp);
		1247	ironlake_edp_panel_vdd_off(intel_dp, false);
2327	Serge	1248
2342	Serge	1249	/* Make sure the panel is off before trying to
		1250	* change the mode
		1251	*/
2330	Serge	1252	}
2327	Serge	1253
2330	Serge	1254	static void intel_dp_commit(struct drm_encoder *encoder)
		1255	{
		1256	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1257	struct drm_device *dev = encoder->dev;
2342	Serge	1258	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
2327	Serge	1259
2330	Serge	1260	ironlake_edp_panel_vdd_on(intel_dp);
2342	Serge	1261	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2330	Serge	1262	intel_dp_start_link_train(intel_dp);
		1263	ironlake_edp_panel_on(intel_dp);
2342	Serge	1264	ironlake_edp_panel_vdd_off(intel_dp, true);
2330	Serge	1265	intel_dp_complete_link_train(intel_dp);
2342	Serge	1266	ironlake_edp_backlight_on(intel_dp);
2330	Serge	1267
2342	Serge	1268	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
2330	Serge	1269
2342	Serge	1270	if (HAS_PCH_CPT(dev))
		1271	intel_cpt_verify_modeset(dev, intel_crtc->pipe);
2330	Serge	1272	}
		1273
		1274	static void
		1275	intel_dp_dpms(struct drm_encoder *encoder, int mode)
		1276	{
		1277	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1278	struct drm_device *dev = encoder->dev;
		1279	struct drm_i915_private *dev_priv = dev->dev_private;
		1280	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		1281
		1282	if (mode != DRM_MODE_DPMS_ON) {
2342	Serge	1283	ironlake_edp_backlight_off(intel_dp);
		1284	ironlake_edp_panel_off(intel_dp);
		1285
		1286	ironlake_edp_panel_vdd_on(intel_dp);
2330	Serge	1287	intel_dp_sink_dpms(intel_dp, mode);
		1288	intel_dp_link_down(intel_dp);
2342	Serge	1289	ironlake_edp_panel_vdd_off(intel_dp, false);
		1290
		1291	if (is_cpu_edp(intel_dp))
2330	Serge	1292	ironlake_edp_pll_off(encoder);
		1293	} else {
2342	Serge	1294	if (is_cpu_edp(intel_dp))
		1295	ironlake_edp_pll_on(encoder);
		1296
2330	Serge	1297	ironlake_edp_panel_vdd_on(intel_dp);
		1298	intel_dp_sink_dpms(intel_dp, mode);
		1299	if (!(dp_reg & DP_PORT_EN)) {
		1300	intel_dp_start_link_train(intel_dp);
		1301	ironlake_edp_panel_on(intel_dp);
2342	Serge	1302	ironlake_edp_panel_vdd_off(intel_dp, true);
2330	Serge	1303	intel_dp_complete_link_train(intel_dp);
2342	Serge	1304	} else
		1305	ironlake_edp_panel_vdd_off(intel_dp, false);
		1306	ironlake_edp_backlight_on(intel_dp);
2330	Serge	1307	}
		1308	intel_dp->dpms_mode = mode;
		1309	}
		1310
		1311	/*
		1312	* Native read with retry for link status and receiver capability reads for
		1313	* cases where the sink may still be asleep.
		1314	*/
		1315	static bool
		1316	intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
		1317	uint8_t *recv, int recv_bytes)
		1318	{
		1319	int ret, i;
		1320
		1321	/*
		1322	* Sinks are supposed to come up within 1ms from an off state,
		1323	* but we're also supposed to retry 3 times per the spec.
		1324	*/
		1325	for (i = 0; i < 3; i++) {
		1326	ret = intel_dp_aux_native_read(intel_dp, address, recv,
		1327	recv_bytes);
		1328	if (ret == recv_bytes)
		1329	return true;
		1330	msleep(1);
		1331	}
		1332
		1333	return false;
		1334	}
		1335
		1336	/*
		1337	* Fetch AUX CH registers 0x202 - 0x207 which contain
		1338	* link status information
		1339	*/
		1340	static bool
2342	Serge	1341	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1342	{
		1343	return intel_dp_aux_native_read_retry(intel_dp,
		1344	DP_LANE0_1_STATUS,
2342	Serge	1345	link_status,
2330	Serge	1346	DP_LINK_STATUS_SIZE);
		1347	}
		1348
		1349	static uint8_t
		1350	intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1351	int r)
		1352	{
		1353	return link_status[r - DP_LANE0_1_STATUS];
		1354	}
		1355
		1356	static uint8_t
2342	Serge	1357	intel_get_adjust_request_voltage(uint8_t adjust_request[2],
2330	Serge	1358	int lane)
		1359	{
		1360	int s = ((lane & 1) ?
		1361	DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
		1362	DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
2342	Serge	1363	uint8_t l = adjust_request[lane>>1];
2330	Serge	1364
		1365	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
		1366	}
		1367
		1368	static uint8_t
2342	Serge	1369	intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
2330	Serge	1370	int lane)
		1371	{
		1372	int s = ((lane & 1) ?
		1373	DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
		1374	DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
2342	Serge	1375	uint8_t l = adjust_request[lane>>1];
2330	Serge	1376
		1377	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
		1378	}
		1379
		1380
		1381	#if 0
		1382	static char *voltage_names[] = {
		1383	"0.4V", "0.6V", "0.8V", "1.2V"
		1384	};
		1385	static char *pre_emph_names[] = {
		1386	"0dB", "3.5dB", "6dB", "9.5dB"
		1387	};
		1388	static char *link_train_names[] = {
		1389	"pattern 1", "pattern 2", "idle", "off"
		1390	};
		1391	#endif
		1392
		1393	/*
		1394	* These are source-specific values; current Intel hardware supports
		1395	* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
		1396	*/
		1397
		1398	static uint8_t
2342	Serge	1399	intel_dp_voltage_max(struct intel_dp *intel_dp)
2330	Serge	1400	{
2342	Serge	1401	struct drm_device *dev = intel_dp->base.base.dev;
		1402
		1403	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		1404	return DP_TRAIN_VOLTAGE_SWING_800;
		1405	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		1406	return DP_TRAIN_VOLTAGE_SWING_1200;
		1407	else
		1408	return DP_TRAIN_VOLTAGE_SWING_800;
		1409	}
		1410
		1411	static uint8_t
		1412	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
		1413	{
		1414	struct drm_device *dev = intel_dp->base.base.dev;
		1415
		1416	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1417	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1418	case DP_TRAIN_VOLTAGE_SWING_400:
		1419	return DP_TRAIN_PRE_EMPHASIS_6;
		1420	case DP_TRAIN_VOLTAGE_SWING_600:
		1421	case DP_TRAIN_VOLTAGE_SWING_800:
		1422	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1423	default:
		1424	return DP_TRAIN_PRE_EMPHASIS_0;
		1425	}
		1426	} else {
2330	Serge	1427	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1428	case DP_TRAIN_VOLTAGE_SWING_400:
		1429	return DP_TRAIN_PRE_EMPHASIS_6;
		1430	case DP_TRAIN_VOLTAGE_SWING_600:
		1431	return DP_TRAIN_PRE_EMPHASIS_6;
		1432	case DP_TRAIN_VOLTAGE_SWING_800:
		1433	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1434	case DP_TRAIN_VOLTAGE_SWING_1200:
		1435	default:
		1436	return DP_TRAIN_PRE_EMPHASIS_0;
		1437	}
2342	Serge	1438	}
2330	Serge	1439	}
		1440
		1441	static void
2342	Serge	1442	intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1443	{
		1444	uint8_t v = 0;
		1445	uint8_t p = 0;
		1446	int lane;
2342	Serge	1447	uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
		1448	uint8_t voltage_max;
		1449	uint8_t preemph_max;
2330	Serge	1450
		1451	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2342	Serge	1452	uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
		1453	uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
2330	Serge	1454
		1455	if (this_v > v)
		1456	v = this_v;
		1457	if (this_p > p)
		1458	p = this_p;
		1459	}
		1460
2342	Serge	1461	voltage_max = intel_dp_voltage_max(intel_dp);
		1462	if (v >= voltage_max)
		1463	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
2330	Serge	1464
2342	Serge	1465	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
		1466	if (p >= preemph_max)
		1467	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2330	Serge	1468
		1469	for (lane = 0; lane < 4; lane++)
		1470	intel_dp->train_set[lane] = v \| p;
		1471	}
		1472
		1473	static uint32_t
2342	Serge	1474	intel_dp_signal_levels(uint8_t train_set)
2330	Serge	1475	{
		1476	uint32_t signal_levels = 0;
		1477
		1478	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1479	case DP_TRAIN_VOLTAGE_SWING_400:
		1480	default:
		1481	signal_levels \|= DP_VOLTAGE_0_4;
		1482	break;
		1483	case DP_TRAIN_VOLTAGE_SWING_600:
		1484	signal_levels \|= DP_VOLTAGE_0_6;
		1485	break;
		1486	case DP_TRAIN_VOLTAGE_SWING_800:
		1487	signal_levels \|= DP_VOLTAGE_0_8;
		1488	break;
		1489	case DP_TRAIN_VOLTAGE_SWING_1200:
		1490	signal_levels \|= DP_VOLTAGE_1_2;
		1491	break;
		1492	}
		1493	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		1494	case DP_TRAIN_PRE_EMPHASIS_0:
		1495	default:
		1496	signal_levels \|= DP_PRE_EMPHASIS_0;
		1497	break;
		1498	case DP_TRAIN_PRE_EMPHASIS_3_5:
		1499	signal_levels \|= DP_PRE_EMPHASIS_3_5;
		1500	break;
		1501	case DP_TRAIN_PRE_EMPHASIS_6:
		1502	signal_levels \|= DP_PRE_EMPHASIS_6;
		1503	break;
		1504	case DP_TRAIN_PRE_EMPHASIS_9_5:
		1505	signal_levels \|= DP_PRE_EMPHASIS_9_5;
		1506	break;
		1507	}
		1508	return signal_levels;
		1509	}
		1510
		1511	/* Gen6's DP voltage swing and pre-emphasis control */
		1512	static uint32_t
		1513	intel_gen6_edp_signal_levels(uint8_t train_set)
		1514	{
		1515	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		1516	DP_TRAIN_PRE_EMPHASIS_MASK);
		1517	switch (signal_levels) {
		1518	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		1519	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		1520	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1521	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1522	return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
		1523	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		1524	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		1525	return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
		1526	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1527	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1528	return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
		1529	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		1530	case DP_TRAIN_VOLTAGE_SWING_1200 \| DP_TRAIN_PRE_EMPHASIS_0:
		1531	return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
		1532	default:
		1533	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		1534	"0x%x\n", signal_levels);
		1535	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1536	}
		1537	}
		1538
2342	Serge	1539	/* Gen7's DP voltage swing and pre-emphasis control */
		1540	static uint32_t
		1541	intel_gen7_edp_signal_levels(uint8_t train_set)
		1542	{
		1543	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		1544	DP_TRAIN_PRE_EMPHASIS_MASK);
		1545	switch (signal_levels) {
		1546	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		1547	return EDP_LINK_TRAIN_400MV_0DB_IVB;
		1548	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1549	return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
		1550	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		1551	return EDP_LINK_TRAIN_400MV_6DB_IVB;
		1552
		1553	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		1554	return EDP_LINK_TRAIN_600MV_0DB_IVB;
		1555	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1556	return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
		1557
		1558	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		1559	return EDP_LINK_TRAIN_800MV_0DB_IVB;
		1560	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1561	return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
		1562
		1563	default:
		1564	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		1565	"0x%x\n", signal_levels);
		1566	return EDP_LINK_TRAIN_500MV_0DB_IVB;
		1567	}
		1568	}
		1569
2330	Serge	1570	static uint8_t
		1571	intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1572	int lane)
		1573	{
		1574	int s = (lane & 1) * 4;
2342	Serge	1575	uint8_t l = link_status[lane>>1];
2330	Serge	1576
		1577	return (l >> s) & 0xf;
		1578	}
		1579
		1580	/* Check for clock recovery is done on all channels */
		1581	static bool
		1582	intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
		1583	{
		1584	int lane;
		1585	uint8_t lane_status;
		1586
		1587	for (lane = 0; lane < lane_count; lane++) {
		1588	lane_status = intel_get_lane_status(link_status, lane);
		1589	if ((lane_status & DP_LANE_CR_DONE) == 0)
		1590	return false;
		1591	}
		1592	return true;
		1593	}
		1594
		1595	/* Check to see if channel eq is done on all channels */
		1596	#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE\|\
		1597	DP_LANE_CHANNEL_EQ_DONE\|\
		1598	DP_LANE_SYMBOL_LOCKED)
		1599	static bool
2342	Serge	1600	intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2330	Serge	1601	{
		1602	uint8_t lane_align;
		1603	uint8_t lane_status;
		1604	int lane;
		1605
2342	Serge	1606	lane_align = intel_dp_link_status(link_status,
2330	Serge	1607	DP_LANE_ALIGN_STATUS_UPDATED);
		1608	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		1609	return false;
		1610	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2342	Serge	1611	lane_status = intel_get_lane_status(link_status, lane);
2330	Serge	1612	if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
		1613	return false;
		1614	}
		1615	return true;
		1616	}
		1617
		1618	static bool
		1619	intel_dp_set_link_train(struct intel_dp *intel_dp,
		1620	uint32_t dp_reg_value,
		1621	uint8_t dp_train_pat)
		1622	{
		1623	struct drm_device *dev = intel_dp->base.base.dev;
		1624	struct drm_i915_private *dev_priv = dev->dev_private;
		1625	int ret;
		1626
		1627	I915_WRITE(intel_dp->output_reg, dp_reg_value);
		1628	POSTING_READ(intel_dp->output_reg);
		1629
		1630	intel_dp_aux_native_write_1(intel_dp,
		1631	DP_TRAINING_PATTERN_SET,
		1632	dp_train_pat);
		1633
		1634	ret = intel_dp_aux_native_write(intel_dp,
		1635	DP_TRAINING_LANE0_SET,
2342	Serge	1636	intel_dp->train_set,
		1637	intel_dp->lane_count);
		1638	if (ret != intel_dp->lane_count)
2330	Serge	1639	return false;
		1640
		1641	return true;
		1642	}
		1643
		1644	/* Enable corresponding port and start training pattern 1 */
		1645	static void
		1646	intel_dp_start_link_train(struct intel_dp *intel_dp)
		1647	{
		1648	struct drm_device *dev = intel_dp->base.base.dev;
		1649	struct drm_i915_private *dev_priv = dev->dev_private;
		1650	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
		1651	int i;
		1652	uint8_t voltage;
		1653	bool clock_recovery = false;
2342	Serge	1654	int voltage_tries, loop_tries;
2330	Serge	1655	u32 reg;
		1656	uint32_t DP = intel_dp->DP;
		1657
		1658	/*
		1659	* On CPT we have to enable the port in training pattern 1, which
		1660	* will happen below in intel_dp_set_link_train. Otherwise, enable
		1661	* the port and wait for it to become active.
		1662	*/
		1663	if (!HAS_PCH_CPT(dev)) {
		1664	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
		1665	POSTING_READ(intel_dp->output_reg);
		1666	intel_wait_for_vblank(dev, intel_crtc->pipe);
		1667	}
		1668
		1669	/* Write the link configuration data */
		1670	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
		1671	intel_dp->link_configuration,
		1672	DP_LINK_CONFIGURATION_SIZE);
		1673
		1674	DP \|= DP_PORT_EN;
2342	Serge	1675
		1676	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1677	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1678	else
		1679	DP &= ~DP_LINK_TRAIN_MASK;
		1680	memset(intel_dp->train_set, 0, 4);
		1681	voltage = 0xff;
2342	Serge	1682	voltage_tries = 0;
		1683	loop_tries = 0;
2330	Serge	1684	clock_recovery = false;
		1685	for (;;) {
		1686	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2342	Serge	1687	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	1688	uint32_t signal_levels;
2342	Serge	1689
		1690
		1691	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1692	signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
		1693	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) \| signal_levels;
		1694	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
2330	Serge	1695	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1696	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1697	} else {
2342	Serge	1698	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
		1699	DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
2330	Serge	1700	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1701	}
		1702
2342	Serge	1703	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1704	reg = DP \| DP_LINK_TRAIN_PAT_1_CPT;
		1705	else
		1706	reg = DP \| DP_LINK_TRAIN_PAT_1;
		1707
		1708	if (!intel_dp_set_link_train(intel_dp, reg,
		1709	DP_TRAINING_PATTERN_1 \|
		1710	DP_LINK_SCRAMBLING_DISABLE))
		1711	break;
		1712	/* Set training pattern 1 */
		1713
		1714	udelay(100);
2342	Serge	1715	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		1716	DRM_ERROR("failed to get link status\n");
2330	Serge	1717	break;
2342	Serge	1718	}
2330	Serge	1719
2342	Serge	1720	if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
		1721	DRM_DEBUG_KMS("clock recovery OK\n");
2330	Serge	1722	clock_recovery = true;
		1723	break;
		1724	}
		1725
		1726	/* Check to see if we've tried the max voltage */
		1727	for (i = 0; i < intel_dp->lane_count; i++)
		1728	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
		1729	break;
2342	Serge	1730	if (i == intel_dp->lane_count) {
		1731	++loop_tries;
		1732	if (loop_tries == 5) {
		1733	DRM_DEBUG_KMS("too many full retries, give up\n");
2330	Serge	1734	break;
2342	Serge	1735	}
		1736	memset(intel_dp->train_set, 0, 4);
		1737	voltage_tries = 0;
		1738	continue;
		1739	}
2330	Serge	1740
		1741	/* Check to see if we've tried the same voltage 5 times */
		1742	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2342	Serge	1743	++voltage_tries;
		1744	if (voltage_tries == 5) {
		1745	DRM_DEBUG_KMS("too many voltage retries, give up\n");
2330	Serge	1746	break;
2342	Serge	1747	}
2330	Serge	1748	} else
2342	Serge	1749	voltage_tries = 0;
2330	Serge	1750	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
		1751
		1752	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	1753	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	1754	}
		1755
		1756	intel_dp->DP = DP;
		1757	}
		1758
		1759	static void
		1760	intel_dp_complete_link_train(struct intel_dp *intel_dp)
		1761	{
		1762	struct drm_device *dev = intel_dp->base.base.dev;
		1763	struct drm_i915_private *dev_priv = dev->dev_private;
		1764	bool channel_eq = false;
		1765	int tries, cr_tries;
		1766	u32 reg;
		1767	uint32_t DP = intel_dp->DP;
		1768
		1769	/* channel equalization */
		1770	tries = 0;
		1771	cr_tries = 0;
		1772	channel_eq = false;
		1773	for (;;) {
		1774	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
		1775	uint32_t signal_levels;
2342	Serge	1776	uint8_t link_status[DP_LINK_STATUS_SIZE];
2330	Serge	1777
		1778	if (cr_tries > 5) {
		1779	DRM_ERROR("failed to train DP, aborting\n");
		1780	intel_dp_link_down(intel_dp);
		1781	break;
		1782	}
		1783
2342	Serge	1784	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		1785	signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
		1786	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) \| signal_levels;
		1787	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
2330	Serge	1788	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1789	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1790	} else {
2342	Serge	1791	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
2330	Serge	1792	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1793	}
		1794
2342	Serge	1795	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1796	reg = DP \| DP_LINK_TRAIN_PAT_2_CPT;
		1797	else
		1798	reg = DP \| DP_LINK_TRAIN_PAT_2;
		1799
		1800	/* channel eq pattern */
		1801	if (!intel_dp_set_link_train(intel_dp, reg,
		1802	DP_TRAINING_PATTERN_2 \|
		1803	DP_LINK_SCRAMBLING_DISABLE))
		1804	break;
		1805
		1806	udelay(400);
2342	Serge	1807	if (!intel_dp_get_link_status(intel_dp, link_status))
2330	Serge	1808	break;
		1809
		1810	/* Make sure clock is still ok */
2342	Serge	1811	if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2330	Serge	1812	intel_dp_start_link_train(intel_dp);
		1813	cr_tries++;
		1814	continue;
		1815	}
		1816
2342	Serge	1817	if (intel_channel_eq_ok(intel_dp, link_status)) {
2330	Serge	1818	channel_eq = true;
		1819	break;
		1820	}
		1821
		1822	/* Try 5 times, then try clock recovery if that fails */
		1823	if (tries > 5) {
		1824	intel_dp_link_down(intel_dp);
		1825	intel_dp_start_link_train(intel_dp);
		1826	tries = 0;
		1827	cr_tries++;
		1828	continue;
		1829	}
		1830
		1831	/* Compute new intel_dp->train_set as requested by target */
2342	Serge	1832	intel_get_adjust_train(intel_dp, link_status);
2330	Serge	1833	++tries;
		1834	}
		1835
2342	Serge	1836	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
2330	Serge	1837	reg = DP \| DP_LINK_TRAIN_OFF_CPT;
		1838	else
		1839	reg = DP \| DP_LINK_TRAIN_OFF;
		1840
		1841	I915_WRITE(intel_dp->output_reg, reg);
		1842	POSTING_READ(intel_dp->output_reg);
		1843	intel_dp_aux_native_write_1(intel_dp,
		1844	DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
		1845	}
		1846
		1847	static void
		1848	intel_dp_link_down(struct intel_dp *intel_dp)
		1849	{
		1850	struct drm_device *dev = intel_dp->base.base.dev;
		1851	struct drm_i915_private *dev_priv = dev->dev_private;
		1852	uint32_t DP = intel_dp->DP;
		1853
		1854	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
		1855	return;
		1856
		1857	DRM_DEBUG_KMS("\n");
		1858
		1859	if (is_edp(intel_dp)) {
		1860	DP &= ~DP_PLL_ENABLE;
		1861	I915_WRITE(intel_dp->output_reg, DP);
		1862	POSTING_READ(intel_dp->output_reg);
		1863	udelay(100);
		1864	}
		1865
2342	Serge	1866	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp))) {
2330	Serge	1867	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1868	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE_CPT);
		1869	} else {
		1870	DP &= ~DP_LINK_TRAIN_MASK;
		1871	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE);
		1872	}
		1873	POSTING_READ(intel_dp->output_reg);
		1874
		1875	msleep(17);
		1876
2342	Serge	1877	if (is_edp(intel_dp)) {
		1878	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) \|\| !is_cpu_edp(intel_dp)))
		1879	DP \|= DP_LINK_TRAIN_OFF_CPT;
		1880	else
2330	Serge	1881	DP \|= DP_LINK_TRAIN_OFF;
2342	Serge	1882	}
2330	Serge	1883
		1884	if (!HAS_PCH_CPT(dev) &&
		1885	I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
		1886	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		1887
		1888	/* Hardware workaround: leaving our transcoder select
		1889	* set to transcoder B while it's off will prevent the
		1890	* corresponding HDMI output on transcoder A.
		1891	*
		1892	* Combine this with another hardware workaround:
		1893	* transcoder select bit can only be cleared while the
		1894	* port is enabled.
		1895	*/
		1896	DP &= ~DP_PIPEB_SELECT;
		1897	I915_WRITE(intel_dp->output_reg, DP);
		1898
		1899	/* Changes to enable or select take place the vblank
		1900	* after being written.
		1901	*/
		1902	if (crtc == NULL) {
		1903	/* We can arrive here never having been attached
		1904	* to a CRTC, for instance, due to inheriting
		1905	* random state from the BIOS.
		1906	*
		1907	* If the pipe is not running, play safe and
		1908	* wait for the clocks to stabilise before
		1909	* continuing.
		1910	*/
		1911	POSTING_READ(intel_dp->output_reg);
		1912	msleep(50);
		1913	} else
		1914	intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
		1915	}
		1916
2342	Serge	1917	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2330	Serge	1918	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
		1919	POSTING_READ(intel_dp->output_reg);
2342	Serge	1920	msleep(intel_dp->panel_power_down_delay);
2330	Serge	1921	}
		1922
		1923	static bool
		1924	intel_dp_get_dpcd(struct intel_dp *intel_dp)
		1925	{
		1926	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2342	Serge	1927	sizeof(intel_dp->dpcd)) &&
2330	Serge	1928	(intel_dp->dpcd[DP_DPCD_REV] != 0)) {
		1929	return true;
		1930	}
		1931
		1932	return false;
		1933	}
		1934
2342	Serge	1935	static bool
		1936	intel_dp_get_sink_irq(struct intel_dp intel_dp, u8 sink_irq_vector)
		1937	{
		1938	int ret;
		1939
		1940	ret = intel_dp_aux_native_read_retry(intel_dp,
		1941	DP_DEVICE_SERVICE_IRQ_VECTOR,
		1942	sink_irq_vector, 1);
		1943	if (!ret)
		1944	return false;
		1945
		1946	return true;
		1947	}
		1948
		1949	static void
		1950	intel_dp_handle_test_request(struct intel_dp *intel_dp)
		1951	{
		1952	/* NAK by default */
		1953	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
		1954	}
		1955
2330	Serge	1956	/*
		1957	* According to DP spec
		1958	* 5.1.2:
		1959	* 1. Read DPCD
		1960	* 2. Configure link according to Receiver Capabilities
		1961	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
		1962	* 4. Check link status on receipt of hot-plug interrupt
		1963	*/
		1964
		1965	static void
		1966	intel_dp_check_link_status(struct intel_dp *intel_dp)
		1967	{
2342	Serge	1968	u8 sink_irq_vector;
		1969	u8 link_status[DP_LINK_STATUS_SIZE];
		1970
2330	Serge	1971	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
		1972	return;
		1973
		1974	if (!intel_dp->base.base.crtc)
		1975	return;
		1976
		1977	/* Try to read receiver status if the link appears to be up */
2342	Serge	1978	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2330	Serge	1979	intel_dp_link_down(intel_dp);
		1980	return;
		1981	}
		1982
		1983	/* Now read the DPCD to see if it's actually running */
		1984	if (!intel_dp_get_dpcd(intel_dp)) {
		1985	intel_dp_link_down(intel_dp);
		1986	return;
		1987	}
		1988
2342	Serge	1989	/* Try to read the source of the interrupt */
		1990	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		1991	intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		1992	/* Clear interrupt source */
		1993	intel_dp_aux_native_write_1(intel_dp,
		1994	DP_DEVICE_SERVICE_IRQ_VECTOR,
		1995	sink_irq_vector);
		1996
		1997	if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
		1998	intel_dp_handle_test_request(intel_dp);
		1999	if (sink_irq_vector & (DP_CP_IRQ \| DP_SINK_SPECIFIC_IRQ))
		2000	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
		2001	}
		2002
		2003	if (!intel_channel_eq_ok(intel_dp, link_status)) {
2330	Serge	2004	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
		2005	drm_get_encoder_name(&intel_dp->base.base));
		2006	intel_dp_start_link_train(intel_dp);
		2007	intel_dp_complete_link_train(intel_dp);
		2008	}
		2009	}
		2010
		2011	static enum drm_connector_status
		2012	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
		2013	{
		2014	if (intel_dp_get_dpcd(intel_dp))
		2015	return connector_status_connected;
		2016	return connector_status_disconnected;
		2017	}
		2018
		2019	static enum drm_connector_status
		2020	ironlake_dp_detect(struct intel_dp *intel_dp)
		2021	{
		2022	enum drm_connector_status status;
		2023
		2024	/* Can't disconnect eDP, but you can close the lid... */
		2025	if (is_edp(intel_dp)) {
		2026	status = intel_panel_detect(intel_dp->base.base.dev);
		2027	if (status == connector_status_unknown)
		2028	status = connector_status_connected;
		2029	return status;
		2030	}
		2031
		2032	return intel_dp_detect_dpcd(intel_dp);
		2033	}
		2034
		2035	static enum drm_connector_status
		2036	g4x_dp_detect(struct intel_dp *intel_dp)
		2037	{
		2038	struct drm_device *dev = intel_dp->base.base.dev;
		2039	struct drm_i915_private *dev_priv = dev->dev_private;
		2040	uint32_t temp, bit;
		2041
		2042	switch (intel_dp->output_reg) {
		2043	case DP_B:
		2044	bit = DPB_HOTPLUG_INT_STATUS;
		2045	break;
		2046	case DP_C:
		2047	bit = DPC_HOTPLUG_INT_STATUS;
		2048	break;
		2049	case DP_D:
		2050	bit = DPD_HOTPLUG_INT_STATUS;
		2051	break;
		2052	default:
		2053	return connector_status_unknown;
		2054	}
		2055
		2056	temp = I915_READ(PORT_HOTPLUG_STAT);
		2057
		2058	if ((temp & bit) == 0)
		2059	return connector_status_disconnected;
		2060
		2061	return intel_dp_detect_dpcd(intel_dp);
		2062	}
		2063
2342	Serge	2064	static struct edid *
		2065	intel_dp_get_edid(struct drm_connector connector, struct i2c_adapter adapter)
		2066	{
		2067	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2068	struct edid *edid;
		2069
		2070	ironlake_edp_panel_vdd_on(intel_dp);
		2071	edid = drm_get_edid(connector, adapter);
		2072	ironlake_edp_panel_vdd_off(intel_dp, false);
		2073	return edid;
		2074	}
		2075
		2076	static int
		2077	intel_dp_get_edid_modes(struct drm_connector connector, struct i2c_adapter adapter)
		2078	{
		2079	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2080	int ret;
		2081
		2082	ironlake_edp_panel_vdd_on(intel_dp);
		2083	ret = intel_ddc_get_modes(connector, adapter);
		2084	ironlake_edp_panel_vdd_off(intel_dp, false);
		2085	return ret;
		2086	}
		2087
		2088
2330	Serge	2089	/**
		2090	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
		2091	*
		2092	* \return true if DP port is connected.
		2093	* \return false if DP port is disconnected.
		2094	*/
		2095	static enum drm_connector_status
		2096	intel_dp_detect(struct drm_connector *connector, bool force)
		2097	{
		2098	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2099	struct drm_device *dev = intel_dp->base.base.dev;
		2100	enum drm_connector_status status;
		2101	struct edid *edid = NULL;
		2102
		2103	intel_dp->has_audio = false;
		2104
		2105	if (HAS_PCH_SPLIT(dev))
		2106	status = ironlake_dp_detect(intel_dp);
		2107	else
		2108	status = g4x_dp_detect(intel_dp);
		2109
		2110	DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
		2111	intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
		2112	intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
		2113	intel_dp->dpcd[6], intel_dp->dpcd[7]);
		2114
		2115	if (status != connector_status_connected)
		2116	return status;
		2117	/*
		2118	if (intel_dp->force_audio) {
		2119	intel_dp->has_audio = intel_dp->force_audio > 0;
		2120	} else {
		2121	edid = drm_get_edid(connector, &intel_dp->adapter);
		2122	if (edid) {
		2123	intel_dp->has_audio = drm_detect_monitor_audio(edid);
		2124	connector->display_info.raw_edid = NULL;
		2125	kfree(edid);
		2126	}
		2127	}
		2128	*/
		2129	return connector_status_connected;
		2130	}
		2131
		2132	static int intel_dp_get_modes(struct drm_connector *connector)
		2133	{
		2134	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2135	struct drm_device *dev = intel_dp->base.base.dev;
		2136	struct drm_i915_private *dev_priv = dev->dev_private;
		2137	int ret;
		2138
		2139	/* We should parse the EDID data and find out if it has an audio sink
		2140	*/
		2141
2342	Serge	2142	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2330	Serge	2143	if (ret) {
2342	Serge	2144	if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2330	Serge	2145	struct drm_display_mode *newmode;
		2146	list_for_each_entry(newmode, &connector->probed_modes,
		2147	head) {
2342	Serge	2148	if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
		2149	intel_dp->panel_fixed_mode =
2330	Serge	2150	drm_mode_duplicate(dev, newmode);
		2151	break;
		2152	}
		2153	}
		2154	}
		2155	return ret;
		2156	}
		2157
		2158	/* if eDP has no EDID, try to use fixed panel mode from VBT */
		2159	if (is_edp(intel_dp)) {
2342	Serge	2160	/* initialize panel mode from VBT if available for eDP */
		2161	if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
		2162	intel_dp->panel_fixed_mode =
		2163	drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
		2164	if (intel_dp->panel_fixed_mode) {
		2165	intel_dp->panel_fixed_mode->type \|=
		2166	DRM_MODE_TYPE_PREFERRED;
		2167	}
		2168	}
		2169	if (intel_dp->panel_fixed_mode) {
2330	Serge	2170	struct drm_display_mode *mode;
2342	Serge	2171	mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2330	Serge	2172	drm_mode_probed_add(connector, mode);
		2173	return 1;
		2174	}
		2175	}
		2176	return 0;
		2177	}
		2178
		2179
		2180
		2181
		2182
		2183	static int
		2184	intel_dp_set_property(struct drm_connector *connector,
		2185	struct drm_property *property,
		2186	uint64_t val)
		2187	{
		2188	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		2189	struct intel_dp *intel_dp = intel_attached_dp(connector);
		2190	int ret;
		2191
		2192	ret = drm_connector_property_set_value(connector, property, val);
		2193	if (ret)
		2194	return ret;
		2195	#if 0
		2196	if (property == dev_priv->force_audio_property) {
		2197	int i = val;
		2198	bool has_audio;
		2199
		2200	if (i == intel_dp->force_audio)
		2201	return 0;
		2202
		2203	intel_dp->force_audio = i;
		2204
		2205	if (i == 0)
		2206	has_audio = intel_dp_detect_audio(connector);
		2207	else
		2208	has_audio = i > 0;
		2209
		2210	if (has_audio == intel_dp->has_audio)
		2211	return 0;
		2212
		2213	intel_dp->has_audio = has_audio;
		2214	goto done;
		2215	}
		2216
		2217	if (property == dev_priv->broadcast_rgb_property) {
		2218	if (val == !!intel_dp->color_range)
		2219	return 0;
		2220
		2221	intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
		2222	goto done;
		2223	}
		2224	#endif
		2225
		2226	return -EINVAL;
		2227
		2228	done:
		2229	if (intel_dp->base.base.crtc) {
		2230	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		2231	drm_crtc_helper_set_mode(crtc, &crtc->mode,
		2232	crtc->x, crtc->y,
		2233	crtc->fb);
		2234	}
		2235
		2236	return 0;
		2237	}
		2238
		2239	static void
2342	Serge	2240	intel_dp_destroy(struct drm_connector *connector)
2330	Serge	2241	{
		2242	struct drm_device *dev = connector->dev;
		2243
		2244	if (intel_dpd_is_edp(dev))
		2245	intel_panel_destroy_backlight(dev);
		2246
		2247	drm_sysfs_connector_remove(connector);
		2248	drm_connector_cleanup(connector);
		2249	kfree(connector);
		2250	}
		2251
		2252	static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
		2253	{
		2254	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2255
		2256	// i2c_del_adapter(&intel_dp->adapter);
		2257	drm_encoder_cleanup(encoder);
2342	Serge	2258	if (is_edp(intel_dp)) {
		2259	// cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		2260	ironlake_panel_vdd_off_sync(intel_dp);
		2261	}
2330	Serge	2262	kfree(intel_dp);
		2263	}
		2264
		2265	static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
		2266	.dpms = intel_dp_dpms,
		2267	.mode_fixup = intel_dp_mode_fixup,
		2268	.prepare = intel_dp_prepare,
		2269	.mode_set = intel_dp_mode_set,
		2270	.commit = intel_dp_commit,
		2271	};
		2272
		2273	static const struct drm_connector_funcs intel_dp_connector_funcs = {
		2274	.dpms = drm_helper_connector_dpms,
		2275	.detect = intel_dp_detect,
		2276	.fill_modes = drm_helper_probe_single_connector_modes,
		2277	.set_property = intel_dp_set_property,
		2278	.destroy = intel_dp_destroy,
		2279	};
		2280
		2281	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
		2282	.get_modes = intel_dp_get_modes,
		2283	.mode_valid = intel_dp_mode_valid,
		2284	.best_encoder = intel_best_encoder,
		2285	};
		2286
		2287	static const struct drm_encoder_funcs intel_dp_enc_funcs = {
		2288	.destroy = intel_dp_encoder_destroy,
		2289	};
		2290
		2291	static void
		2292	intel_dp_hot_plug(struct intel_encoder *intel_encoder)
		2293	{
		2294	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		2295
		2296	intel_dp_check_link_status(intel_dp);
		2297	}
		2298
2327	Serge	2299	/* Return which DP Port should be selected for Transcoder DP control */
		2300	int
2342	Serge	2301	intel_trans_dp_port_sel(struct drm_crtc *crtc)
2327	Serge	2302	{
		2303	struct drm_device *dev = crtc->dev;
		2304	struct drm_mode_config *mode_config = &dev->mode_config;
		2305	struct drm_encoder *encoder;
		2306
		2307	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		2308	struct intel_dp *intel_dp;
		2309
		2310	if (encoder->crtc != crtc)
		2311	continue;
		2312
		2313	intel_dp = enc_to_intel_dp(encoder);
2342	Serge	2314	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT \|\|
		2315	intel_dp->base.type == INTEL_OUTPUT_EDP)
2327	Serge	2316	return intel_dp->output_reg;
		2317	}
		2318
		2319	return -1;
		2320	}
2330	Serge	2321
		2322	/* check the VBT to see whether the eDP is on DP-D port */
		2323	bool intel_dpd_is_edp(struct drm_device *dev)
		2324	{
		2325	struct drm_i915_private *dev_priv = dev->dev_private;
		2326	struct child_device_config *p_child;
		2327	int i;
		2328
		2329	if (!dev_priv->child_dev_num)
		2330	return false;
		2331
		2332	for (i = 0; i < dev_priv->child_dev_num; i++) {
		2333	p_child = dev_priv->child_dev + i;
		2334
		2335	if (p_child->dvo_port == PORT_IDPD &&
		2336	p_child->device_type == DEVICE_TYPE_eDP)
		2337	return true;
		2338	}
		2339	return false;
		2340	}
		2341
		2342	static void
		2343	intel_dp_add_properties(struct intel_dp intel_dp, struct drm_connector connector)
		2344	{
		2345	intel_attach_force_audio_property(connector);
		2346	intel_attach_broadcast_rgb_property(connector);
		2347	}
		2348
		2349	void
		2350	intel_dp_init(struct drm_device *dev, int output_reg)
		2351	{
		2352	struct drm_i915_private *dev_priv = dev->dev_private;
		2353	struct drm_connector *connector;
		2354	struct intel_dp *intel_dp;
		2355	struct intel_encoder *intel_encoder;
		2356	struct intel_connector *intel_connector;
		2357	const char *name = NULL;
		2358	int type;
		2359
		2360	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
		2361	if (!intel_dp)
		2362	return;
		2363
		2364	intel_dp->output_reg = output_reg;
		2365	intel_dp->dpms_mode = -1;
		2366
		2367	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
		2368	if (!intel_connector) {
		2369	kfree(intel_dp);
		2370	return;
		2371	}
		2372	intel_encoder = &intel_dp->base;
		2373
		2374	if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
		2375	if (intel_dpd_is_edp(dev))
		2376	intel_dp->is_pch_edp = true;
		2377
		2378	if (output_reg == DP_A \|\| is_pch_edp(intel_dp)) {
		2379	type = DRM_MODE_CONNECTOR_eDP;
		2380	intel_encoder->type = INTEL_OUTPUT_EDP;
		2381	} else {
		2382	type = DRM_MODE_CONNECTOR_DisplayPort;
		2383	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		2384	}
		2385
		2386	connector = &intel_connector->base;
		2387	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
		2388	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
		2389
		2390	connector->polled = DRM_CONNECTOR_POLL_HPD;
		2391
		2392	if (output_reg == DP_B \|\| output_reg == PCH_DP_B)
		2393	intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
		2394	else if (output_reg == DP_C \|\| output_reg == PCH_DP_C)
		2395	intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
		2396	else if (output_reg == DP_D \|\| output_reg == PCH_DP_D)
		2397	intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
		2398
2342	Serge	2399	if (is_edp(intel_dp)) {
2330	Serge	2400	intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2342	Serge	2401	// INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
		2402	// ironlake_panel_vdd_work);
		2403	}
2330	Serge	2404
2342	Serge	2405	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
2330	Serge	2406	connector->interlace_allowed = true;
		2407	connector->doublescan_allowed = 0;
		2408
		2409	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
		2410	DRM_MODE_ENCODER_TMDS);
		2411	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
		2412
		2413	intel_connector_attach_encoder(intel_connector, intel_encoder);
		2414	drm_sysfs_connector_add(connector);
		2415
		2416	/* Set up the DDC bus. */
		2417	switch (output_reg) {
		2418	case DP_A:
		2419	name = "DPDDC-A";
		2420	break;
		2421	case DP_B:
		2422	case PCH_DP_B:
		2423	dev_priv->hotplug_supported_mask \|=
		2424	HDMIB_HOTPLUG_INT_STATUS;
		2425	name = "DPDDC-B";
		2426	break;
		2427	case DP_C:
		2428	case PCH_DP_C:
		2429	dev_priv->hotplug_supported_mask \|=
		2430	HDMIC_HOTPLUG_INT_STATUS;
		2431	name = "DPDDC-C";
		2432	break;
		2433	case DP_D:
		2434	case PCH_DP_D:
		2435	dev_priv->hotplug_supported_mask \|=
		2436	HDMID_HOTPLUG_INT_STATUS;
		2437	name = "DPDDC-D";
		2438	break;
		2439	}
		2440
		2441	/* Cache some DPCD data in the eDP case */
		2442	if (is_edp(intel_dp)) {
		2443	bool ret;
2342	Serge	2444	struct edp_power_seq cur, vbt;
		2445	u32 pp_on, pp_off, pp_div;
2330	Serge	2446
		2447	pp_on = I915_READ(PCH_PP_ON_DELAYS);
2342	Serge	2448	pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2330	Serge	2449	pp_div = I915_READ(PCH_PP_DIVISOR);
		2450
2342	Serge	2451	/* Pull timing values out of registers */
		2452	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		2453	PANEL_POWER_UP_DELAY_SHIFT;
2330	Serge	2454
2342	Serge	2455	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		2456	PANEL_LIGHT_ON_DELAY_SHIFT;
		2457
		2458	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		2459	PANEL_LIGHT_OFF_DELAY_SHIFT;
		2460
		2461	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		2462	PANEL_POWER_DOWN_DELAY_SHIFT;
		2463
		2464	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		2465	PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
		2466
		2467	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		2468	cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
		2469
		2470	vbt = dev_priv->edp.pps;
		2471
		2472	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		2473	vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
		2474
		2475	#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
		2476
		2477	intel_dp->panel_power_up_delay = get_delay(t1_t3);
		2478	intel_dp->backlight_on_delay = get_delay(t8);
		2479	intel_dp->backlight_off_delay = get_delay(t9);
		2480	intel_dp->panel_power_down_delay = get_delay(t10);
		2481	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
		2482
		2483	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		2484	intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		2485	intel_dp->panel_power_cycle_delay);
		2486
		2487	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		2488	intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
		2489
2330	Serge	2490	ironlake_edp_panel_vdd_on(intel_dp);
		2491	ret = intel_dp_get_dpcd(intel_dp);
2342	Serge	2492	ironlake_edp_panel_vdd_off(intel_dp, false);
		2493
2330	Serge	2494	if (ret) {
		2495	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		2496	dev_priv->no_aux_handshake =
		2497	intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
		2498	DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		2499	} else {
		2500	/* if this fails, presume the device is a ghost */
		2501	DRM_INFO("failed to retrieve link info, disabling eDP\n");
		2502	intel_dp_encoder_destroy(&intel_dp->base.base);
		2503	intel_dp_destroy(&intel_connector->base);
		2504	return;
		2505	}
		2506	}
		2507
2342	Serge	2508	intel_dp_i2c_init(intel_dp, intel_connector, name);
		2509
2330	Serge	2510	intel_encoder->hot_plug = intel_dp_hot_plug;
		2511
		2512	if (is_edp(intel_dp)) {
		2513	dev_priv->int_edp_connector = connector;
		2514	intel_panel_setup_backlight(dev);
		2515	}
		2516
		2517	intel_dp_add_properties(intel_dp, connector);
		2518
		2519	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		2520	* 0xd. Failure to do so will result in spurious interrupts being
		2521	* generated on the port when a cable is not attached.
		2522	*/
		2523	if (IS_G4X(dev) && !IS_GM45(dev)) {
		2524	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		2525	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		2526	}
		2527	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c – Rev 2342