WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_dp.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2008 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Keith Packard
		25	*
		26	*/
		27
		28	#include
2330	Serge	29	#include
2327	Serge	30	#include "drmP.h"
		31	#include "drm.h"
		32	#include "drm_crtc.h"
		33	#include "drm_crtc_helper.h"
		34	#include "intel_drv.h"
2330	Serge	35	#include "i915_drm.h"
2327	Serge	36	#include "i915_drv.h"
		37	#include "drm_dp_helper.h"
		38
		39
		40	#define DP_LINK_STATUS_SIZE 6
		41	#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
		42
		43	#define DP_LINK_CONFIGURATION_SIZE 9
		44
		45	struct intel_dp {
		46	struct intel_encoder base;
		47	uint32_t output_reg;
		48	uint32_t DP;
		49	uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
		50	bool has_audio;
		51	int force_audio;
		52	uint32_t color_range;
		53	int dpms_mode;
		54	uint8_t link_bw;
		55	uint8_t lane_count;
		56	uint8_t dpcd[8];
		57	struct i2c_adapter adapter;
		58	struct i2c_algo_dp_aux_data algo;
		59	bool is_pch_edp;
		60	uint8_t train_set[4];
		61	uint8_t link_status[DP_LINK_STATUS_SIZE];
		62	};
		63
		64	/**
		65	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
		66	* @intel_dp: DP struct
		67	*
		68	* If a CPU or PCH DP output is attached to an eDP panel, this function
		69	* will return true, and false otherwise.
		70	*/
		71	static bool is_edp(struct intel_dp *intel_dp)
		72	{
		73	return intel_dp->base.type == INTEL_OUTPUT_EDP;
		74	}
		75
		76	/**
		77	* is_pch_edp - is the port on the PCH and attached to an eDP panel?
		78	* @intel_dp: DP struct
		79	*
		80	* Returns true if the given DP struct corresponds to a PCH DP port attached
		81	* to an eDP panel, false otherwise. Helpful for determining whether we
		82	* may need FDI resources for a given DP output or not.
		83	*/
		84	static bool is_pch_edp(struct intel_dp *intel_dp)
		85	{
		86	return intel_dp->is_pch_edp;
		87	}
		88
		89	static struct intel_dp enc_to_intel_dp(struct drm_encoder encoder)
		90	{
		91	return container_of(encoder, struct intel_dp, base.base);
		92	}
		93
2330	Serge	94	static struct intel_dp intel_attached_dp(struct drm_connector connector)
		95	{
		96	return container_of(intel_attached_encoder(connector),
		97	struct intel_dp, base);
		98	}
2327	Serge	99
		100	/**
		101	* intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
		102	* @encoder: DRM encoder
		103	*
		104	* Return true if @encoder corresponds to a PCH attached eDP panel. Needed
		105	* by intel_display.c.
		106	*/
		107	bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
		108	{
		109	struct intel_dp *intel_dp;
		110
		111	if (!encoder)
		112	return false;
		113
		114	intel_dp = enc_to_intel_dp(encoder);
		115
		116	return is_pch_edp(intel_dp);
		117	}
		118
2330	Serge	119	static void intel_dp_start_link_train(struct intel_dp *intel_dp);
		120	static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
		121	static void intel_dp_link_down(struct intel_dp *intel_dp);
		122
2327	Serge	123	void
		124	intel_edp_link_config (struct intel_encoder *intel_encoder,
		125	int lane_num, int link_bw)
		126	{
		127	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		128
		129	*lane_num = intel_dp->lane_count;
		130	if (intel_dp->link_bw == DP_LINK_BW_1_62)
		131	*link_bw = 162000;
		132	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
		133	*link_bw = 270000;
		134	}
		135
2330	Serge	136	static int
		137	intel_dp_max_lane_count(struct intel_dp *intel_dp)
		138	{
		139	int max_lane_count = 4;
2327	Serge	140
2330	Serge	141	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		142	max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
		143	switch (max_lane_count) {
		144	case 1: case 2: case 4:
		145	break;
		146	default:
		147	max_lane_count = 4;
		148	}
		149	}
		150	return max_lane_count;
		151	}
2327	Serge	152
2330	Serge	153	static int
		154	intel_dp_max_link_bw(struct intel_dp *intel_dp)
		155	{
		156	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
2327	Serge	157
2330	Serge	158	switch (max_link_bw) {
		159	case DP_LINK_BW_1_62:
		160	case DP_LINK_BW_2_7:
		161	break;
		162	default:
		163	max_link_bw = DP_LINK_BW_1_62;
		164	break;
		165	}
		166	return max_link_bw;
		167	}
2327	Serge	168
2330	Serge	169	static int
		170	intel_dp_link_clock(uint8_t link_bw)
		171	{
		172	if (link_bw == DP_LINK_BW_2_7)
		173	return 270000;
		174	else
		175	return 162000;
		176	}
2327	Serge	177
2330	Serge	178	/* I think this is a fiction */
		179	static int
		180	intel_dp_link_required(struct drm_device dev, struct intel_dp intel_dp, int pixel_clock)
		181	{
		182	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		183	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		184	int bpp = 24;
2327	Serge	185
2330	Serge	186	if (intel_crtc)
		187	bpp = intel_crtc->bpp;
2327	Serge	188
2330	Serge	189	return (pixel_clock * bpp + 7) / 8;
		190	}
2327	Serge	191
2330	Serge	192	static int
		193	intel_dp_max_data_rate(int max_link_clock, int max_lanes)
		194	{
		195	return (max_link_clock * max_lanes * 8) / 10;
		196	}
2327	Serge	197
2330	Serge	198	static int
		199	intel_dp_mode_valid(struct drm_connector *connector,
		200	struct drm_display_mode *mode)
		201	{
		202	struct intel_dp *intel_dp = intel_attached_dp(connector);
		203	struct drm_device *dev = connector->dev;
		204	struct drm_i915_private *dev_priv = dev->dev_private;
		205	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
		206	int max_lanes = intel_dp_max_lane_count(intel_dp);
2327	Serge	207
2330	Serge	208	if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
		209	if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
		210	return MODE_PANEL;
2327	Serge	211
2330	Serge	212	if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
		213	return MODE_PANEL;
		214	}
2327	Serge	215
2330	Serge	216	/* only refuse the mode on non eDP since we have seen some weird eDP panels
		217	which are outside spec tolerances but somehow work by magic */
		218	if (!is_edp(intel_dp) &&
		219	(intel_dp_link_required(connector->dev, intel_dp, mode->clock)
		220	> intel_dp_max_data_rate(max_link_clock, max_lanes)))
		221	return MODE_CLOCK_HIGH;
2327	Serge	222
2330	Serge	223	if (mode->clock < 10000)
		224	return MODE_CLOCK_LOW;
		225
		226	return MODE_OK;
		227	}
		228
		229	static uint32_t
		230	pack_aux(uint8_t *src, int src_bytes)
		231	{
		232	int i;
		233	uint32_t v = 0;
		234
		235	if (src_bytes > 4)
		236	src_bytes = 4;
		237	for (i = 0; i < src_bytes; i++)
		238	v \|= ((uint32_t) src[i]) << ((3-i) * 8);
		239	return v;
		240	}
		241
		242	static void
		243	unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
		244	{
		245	int i;
		246	if (dst_bytes > 4)
		247	dst_bytes = 4;
		248	for (i = 0; i < dst_bytes; i++)
		249	dst[i] = src >> ((3-i) * 8);
		250	}
		251
		252	/* hrawclock is 1/4 the FSB frequency */
		253	static int
		254	intel_hrawclk(struct drm_device *dev)
		255	{
		256	struct drm_i915_private *dev_priv = dev->dev_private;
		257	uint32_t clkcfg;
		258
		259	clkcfg = I915_READ(CLKCFG);
		260	switch (clkcfg & CLKCFG_FSB_MASK) {
		261	case CLKCFG_FSB_400:
		262	return 100;
		263	case CLKCFG_FSB_533:
		264	return 133;
		265	case CLKCFG_FSB_667:
		266	return 166;
		267	case CLKCFG_FSB_800:
		268	return 200;
		269	case CLKCFG_FSB_1067:
		270	return 266;
		271	case CLKCFG_FSB_1333:
		272	return 333;
		273	/* these two are just a guess; one of them might be right */
		274	case CLKCFG_FSB_1600:
		275	case CLKCFG_FSB_1600_ALT:
		276	return 400;
		277	default:
		278	return 133;
		279	}
		280	}
		281
		282	static int
		283	intel_dp_aux_ch(struct intel_dp *intel_dp,
		284	uint8_t *send, int send_bytes,
		285	uint8_t *recv, int recv_size)
		286	{
		287	uint32_t output_reg = intel_dp->output_reg;
		288	struct drm_device *dev = intel_dp->base.base.dev;
		289	struct drm_i915_private *dev_priv = dev->dev_private;
		290	uint32_t ch_ctl = output_reg + 0x10;
		291	uint32_t ch_data = ch_ctl + 4;
		292	int i;
		293	int recv_bytes;
		294	uint32_t status;
		295	uint32_t aux_clock_divider;
		296	int try, precharge;
		297
		298	/* The clock divider is based off the hrawclk,
		299	* and would like to run at 2MHz. So, take the
		300	* hrawclk value and divide by 2 and use that
		301	*
		302	* Note that PCH attached eDP panels should use a 125MHz input
		303	* clock divider.
		304	*/
		305	if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
		306	if (IS_GEN6(dev))
		307	aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
		308	else
		309	aux_clock_divider = 225; /* eDP input clock at 450Mhz */
		310	} else if (HAS_PCH_SPLIT(dev))
		311	aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
		312	else
		313	aux_clock_divider = intel_hrawclk(dev) / 2;
		314
		315	if (IS_GEN6(dev))
		316	precharge = 3;
		317	else
		318	precharge = 5;
		319
		320	/* Try to wait for any previous AUX channel activity */
		321	for (try = 0; try < 3; try++) {
		322	status = I915_READ(ch_ctl);
		323	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		324	break;
		325	msleep(1);
		326	}
		327
		328	if (try == 3) {
		329	WARN(1, "dp_aux_ch not started status 0x%08x\n",
		330	I915_READ(ch_ctl));
		331	return -EBUSY;
		332	}
		333
		334	/* Must try at least 3 times according to DP spec */
		335	for (try = 0; try < 5; try++) {
		336	/* Load the send data into the aux channel data registers */
		337	for (i = 0; i < send_bytes; i += 4)
		338	I915_WRITE(ch_data + i,
		339	pack_aux(send + i, send_bytes - i));
		340
		341	/* Send the command and wait for it to complete */
		342	I915_WRITE(ch_ctl,
		343	DP_AUX_CH_CTL_SEND_BUSY \|
		344	DP_AUX_CH_CTL_TIME_OUT_400us \|
		345	(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
		346	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
		347	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) \|
		348	DP_AUX_CH_CTL_DONE \|
		349	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		350	DP_AUX_CH_CTL_RECEIVE_ERROR);
		351	for (;;) {
		352	status = I915_READ(ch_ctl);
		353	if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		354	break;
		355	udelay(100);
		356	}
		357
		358	/* Clear done status and any errors */
		359	I915_WRITE(ch_ctl,
		360	status \|
		361	DP_AUX_CH_CTL_DONE \|
		362	DP_AUX_CH_CTL_TIME_OUT_ERROR \|
		363	DP_AUX_CH_CTL_RECEIVE_ERROR);
		364	if (status & DP_AUX_CH_CTL_DONE)
		365	break;
		366	}
		367
		368	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		369	DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
		370	return -EBUSY;
		371	}
		372
		373	/* Check for timeout or receive error.
		374	* Timeouts occur when the sink is not connected
		375	*/
		376	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
		377	DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
		378	return -EIO;
		379	}
		380
		381	/* Timeouts occur when the device isn't connected, so they're
		382	* "normal" -- don't fill the kernel log with these */
		383	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
		384	DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
		385	return -ETIMEDOUT;
		386	}
		387
		388	/* Unload any bytes sent back from the other side */
		389	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		390	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
		391	if (recv_bytes > recv_size)
		392	recv_bytes = recv_size;
		393
		394	for (i = 0; i < recv_bytes; i += 4)
		395	unpack_aux(I915_READ(ch_data + i),
		396	recv + i, recv_bytes - i);
		397
		398	return recv_bytes;
		399	}
		400
		401	/* Write data to the aux channel in native mode */
		402	static int
		403	intel_dp_aux_native_write(struct intel_dp *intel_dp,
		404	uint16_t address, uint8_t *send, int send_bytes)
		405	{
		406	int ret;
		407	uint8_t msg[20];
		408	int msg_bytes;
		409	uint8_t ack;
		410
		411	if (send_bytes > 16)
		412	return -1;
		413	msg[0] = AUX_NATIVE_WRITE << 4;
		414	msg[1] = address >> 8;
		415	msg[2] = address & 0xff;
		416	msg[3] = send_bytes - 1;
		417	memcpy(&msg[4], send, send_bytes);
		418	msg_bytes = send_bytes + 4;
		419	for (;;) {
		420	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
		421	if (ret < 0)
		422	return ret;
		423	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
		424	break;
		425	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		426	udelay(100);
		427	else
		428	return -EIO;
		429	}
		430	return send_bytes;
		431	}
		432
		433	/* Write a single byte to the aux channel in native mode */
		434	static int
		435	intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
		436	uint16_t address, uint8_t byte)
		437	{
		438	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
		439	}
		440
		441	/* read bytes from a native aux channel */
		442	static int
		443	intel_dp_aux_native_read(struct intel_dp *intel_dp,
		444	uint16_t address, uint8_t *recv, int recv_bytes)
		445	{
		446	uint8_t msg[4];
		447	int msg_bytes;
		448	uint8_t reply[20];
		449	int reply_bytes;
		450	uint8_t ack;
		451	int ret;
		452
		453	msg[0] = AUX_NATIVE_READ << 4;
		454	msg[1] = address >> 8;
		455	msg[2] = address & 0xff;
		456	msg[3] = recv_bytes - 1;
		457
		458	msg_bytes = 4;
		459	reply_bytes = recv_bytes + 1;
		460
		461	for (;;) {
		462	ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
		463	reply, reply_bytes);
		464	if (ret == 0)
		465	return -EPROTO;
		466	if (ret < 0)
		467	return ret;
		468	ack = reply[0];
		469	if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
		470	memcpy(recv, reply + 1, ret - 1);
		471	return ret - 1;
		472	}
		473	else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
		474	udelay(100);
		475	else
		476	return -EIO;
		477	}
		478	}
		479
		480	static int
		481	intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		482	uint8_t write_byte, uint8_t *read_byte)
		483	{
		484	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
		485	struct intel_dp *intel_dp = container_of(adapter,
		486	struct intel_dp,
		487	adapter);
		488	uint16_t address = algo_data->address;
		489	uint8_t msg[5];
		490	uint8_t reply[2];
		491	unsigned retry;
		492	int msg_bytes;
		493	int reply_bytes;
		494	int ret;
		495
		496	/* Set up the command byte */
		497	if (mode & MODE_I2C_READ)
		498	msg[0] = AUX_I2C_READ << 4;
		499	else
		500	msg[0] = AUX_I2C_WRITE << 4;
		501
		502	if (!(mode & MODE_I2C_STOP))
		503	msg[0] \|= AUX_I2C_MOT << 4;
		504
		505	msg[1] = address >> 8;
		506	msg[2] = address;
		507
		508	switch (mode) {
		509	case MODE_I2C_WRITE:
		510	msg[3] = 0;
		511	msg[4] = write_byte;
		512	msg_bytes = 5;
		513	reply_bytes = 1;
		514	break;
		515	case MODE_I2C_READ:
		516	msg[3] = 0;
		517	msg_bytes = 4;
		518	reply_bytes = 2;
		519	break;
		520	default:
		521	msg_bytes = 3;
		522	reply_bytes = 1;
		523	break;
		524	}
		525
		526	for (retry = 0; retry < 5; retry++) {
		527	ret = intel_dp_aux_ch(intel_dp,
		528	msg, msg_bytes,
		529	reply, reply_bytes);
		530	if (ret < 0) {
		531	DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
		532	return ret;
		533	}
		534
		535	switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		536	case AUX_NATIVE_REPLY_ACK:
		537	/* I2C-over-AUX Reply field is only valid
		538	* when paired with AUX ACK.
		539	*/
		540	break;
		541	case AUX_NATIVE_REPLY_NACK:
		542	DRM_DEBUG_KMS("aux_ch native nack\n");
		543	return -EREMOTEIO;
		544	case AUX_NATIVE_REPLY_DEFER:
		545	udelay(100);
		546	continue;
		547	default:
		548	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
		549	reply[0]);
		550	return -EREMOTEIO;
		551	}
		552
		553	switch (reply[0] & AUX_I2C_REPLY_MASK) {
		554	case AUX_I2C_REPLY_ACK:
		555	if (mode == MODE_I2C_READ) {
		556	*read_byte = reply[1];
		557	}
		558	return reply_bytes - 1;
		559	case AUX_I2C_REPLY_NACK:
		560	DRM_DEBUG_KMS("aux_i2c nack\n");
		561	return -EREMOTEIO;
		562	case AUX_I2C_REPLY_DEFER:
		563	DRM_DEBUG_KMS("aux_i2c defer\n");
		564	udelay(100);
		565	break;
		566	default:
		567	DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
		568	return -EREMOTEIO;
		569	}
		570	}
		571
		572	DRM_ERROR("too many retries, giving up\n");
		573	return -EREMOTEIO;
		574	}
		575
		576	static int
		577	intel_dp_i2c_init(struct intel_dp *intel_dp,
		578	struct intel_connector intel_connector, const char name)
		579	{
		580	DRM_DEBUG_KMS("i2c_init %s\n", name);
		581	intel_dp->algo.running = false;
		582	intel_dp->algo.address = 0;
		583	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
		584
		585	memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
		586	// intel_dp->adapter.owner = THIS_MODULE;
		587	intel_dp->adapter.class = I2C_CLASS_DDC;
		588	strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
		589	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
		590	intel_dp->adapter.algo_data = &intel_dp->algo;
		591	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
		592
		593	return i2c_dp_aux_add_bus(&intel_dp->adapter);
		594	}
		595
		596	static bool
		597	intel_dp_mode_fixup(struct drm_encoder encoder, struct drm_display_mode mode,
		598	struct drm_display_mode *adjusted_mode)
		599	{
		600	struct drm_device *dev = encoder->dev;
		601	struct drm_i915_private *dev_priv = dev->dev_private;
		602	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		603	int lane_count, clock;
		604	int max_lane_count = intel_dp_max_lane_count(intel_dp);
		605	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
		606	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
		607
		608	if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
		609	intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
		610	intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
		611	mode, adjusted_mode);
		612	/*
		613	* the mode->clock is used to calculate the Data&Link M/N
		614	* of the pipe. For the eDP the fixed clock should be used.
		615	*/
		616	mode->clock = dev_priv->panel_fixed_mode->clock;
		617	}
		618
		619	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		620	for (clock = 0; clock <= max_clock; clock++) {
		621	int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
		622
		623	if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
		624	<= link_avail) {
		625	intel_dp->link_bw = bws[clock];
		626	intel_dp->lane_count = lane_count;
		627	adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
		628	DRM_DEBUG_KMS("Display port link bw %02x lane "
		629	"count %d clock %d\n",
		630	intel_dp->link_bw, intel_dp->lane_count,
		631	adjusted_mode->clock);
		632	return true;
		633	}
		634	}
		635	}
		636
		637	if (is_edp(intel_dp)) {
		638	/* okay we failed just pick the highest */
		639	intel_dp->lane_count = max_lane_count;
		640	intel_dp->link_bw = bws[max_clock];
		641	adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
		642	DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
		643	"count %d clock %d\n",
		644	intel_dp->link_bw, intel_dp->lane_count,
		645	adjusted_mode->clock);
		646
		647	return true;
		648	}
		649
		650	return false;
		651	}
		652
2327	Serge	653	struct intel_dp_m_n {
		654	uint32_t tu;
		655	uint32_t gmch_m;
		656	uint32_t gmch_n;
		657	uint32_t link_m;
		658	uint32_t link_n;
		659	};
		660
		661	static void
		662	intel_reduce_ratio(uint32_t num, uint32_t den)
		663	{
		664	while (num > 0xffffff \|\| den > 0xffffff) {
		665	*num >>= 1;
		666	*den >>= 1;
		667	}
		668	}
		669
		670	static void
		671	intel_dp_compute_m_n(int bpp,
		672	int nlanes,
		673	int pixel_clock,
		674	int link_clock,
		675	struct intel_dp_m_n *m_n)
		676	{
		677	m_n->tu = 64;
		678	m_n->gmch_m = (pixel_clock * bpp) >> 3;
		679	m_n->gmch_n = link_clock * nlanes;
		680	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		681	m_n->link_m = pixel_clock;
		682	m_n->link_n = link_clock;
		683	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
		684	}
		685
		686	void
		687	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
		688	struct drm_display_mode *adjusted_mode)
		689	{
		690	struct drm_device *dev = crtc->dev;
		691	struct drm_mode_config *mode_config = &dev->mode_config;
		692	struct drm_encoder *encoder;
		693	struct drm_i915_private *dev_priv = dev->dev_private;
		694	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		695	int lane_count = 4;
		696	struct intel_dp_m_n m_n;
		697	int pipe = intel_crtc->pipe;
		698
		699	/*
		700	* Find the lane count in the intel_encoder private
		701	*/
		702	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		703	struct intel_dp *intel_dp;
		704
		705	if (encoder->crtc != crtc)
		706	continue;
		707
		708	intel_dp = enc_to_intel_dp(encoder);
		709	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
		710	lane_count = intel_dp->lane_count;
		711	break;
		712	} else if (is_edp(intel_dp)) {
		713	lane_count = dev_priv->edp.lanes;
		714	break;
		715	}
		716	}
		717
		718	/*
		719	* Compute the GMCH and Link ratios. The '3' here is
		720	* the number of bytes_per_pixel post-LUT, which we always
		721	* set up for 8-bits of R/G/B, or 3 bytes total.
		722	*/
		723	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
		724	mode->clock, adjusted_mode->clock, &m_n);
		725
		726	if (HAS_PCH_SPLIT(dev)) {
		727	I915_WRITE(TRANSDATA_M1(pipe),
		728	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		729	m_n.gmch_m);
		730	I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		731	I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		732	I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
		733	} else {
		734	I915_WRITE(PIPE_GMCH_DATA_M(pipe),
		735	((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) \|
		736	m_n.gmch_m);
		737	I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		738	I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		739	I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
		740	}
		741	}
		742
2330	Serge	743	static void
		744	intel_dp_mode_set(struct drm_encoder encoder, struct drm_display_mode mode,
		745	struct drm_display_mode *adjusted_mode)
		746	{
		747	struct drm_device *dev = encoder->dev;
		748	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		749	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		750	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	751
2330	Serge	752	intel_dp->DP = DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
		753	intel_dp->DP \|= intel_dp->color_range;
2327	Serge	754
2330	Serge	755	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		756	intel_dp->DP \|= DP_SYNC_HS_HIGH;
		757	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		758	intel_dp->DP \|= DP_SYNC_VS_HIGH;
2327	Serge	759
2330	Serge	760	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
		761	intel_dp->DP \|= DP_LINK_TRAIN_OFF_CPT;
		762	else
		763	intel_dp->DP \|= DP_LINK_TRAIN_OFF;
2327	Serge	764
2330	Serge	765	switch (intel_dp->lane_count) {
		766	case 1:
		767	intel_dp->DP \|= DP_PORT_WIDTH_1;
		768	break;
		769	case 2:
		770	intel_dp->DP \|= DP_PORT_WIDTH_2;
		771	break;
		772	case 4:
		773	intel_dp->DP \|= DP_PORT_WIDTH_4;
		774	break;
		775	}
		776	if (intel_dp->has_audio)
		777	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
2327	Serge	778
2330	Serge	779	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
		780	intel_dp->link_configuration[0] = intel_dp->link_bw;
		781	intel_dp->link_configuration[1] = intel_dp->lane_count;
		782	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
2327	Serge	783
2330	Serge	784	/*
		785	* Check for DPCD version > 1.1 and enhanced framing support
		786	*/
		787	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
		788	(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		789	intel_dp->link_configuration[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
		790	intel_dp->DP \|= DP_ENHANCED_FRAMING;
		791	}
2327	Serge	792
2330	Serge	793	/* CPT DP's pipe select is decided in TRANS_DP_CTL */
		794	if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
		795	intel_dp->DP \|= DP_PIPEB_SELECT;
2327	Serge	796
2330	Serge	797	if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
		798	/* don't miss out required setting for eDP */
		799	intel_dp->DP \|= DP_PLL_ENABLE;
		800	if (adjusted_mode->clock < 200000)
		801	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
		802	else
		803	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		804	}
		805	}
2327	Serge	806
2330	Serge	807	static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
		808	{
		809	struct drm_device *dev = intel_dp->base.base.dev;
		810	struct drm_i915_private *dev_priv = dev->dev_private;
		811	u32 pp;
2327	Serge	812
2330	Serge	813	/*
		814	* If the panel wasn't on, make sure there's not a currently
		815	* active PP sequence before enabling AUX VDD.
		816	*/
		817	if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
		818	msleep(dev_priv->panel_t3);
2327	Serge	819
2330	Serge	820	pp = I915_READ(PCH_PP_CONTROL);
		821	pp \|= EDP_FORCE_VDD;
		822	I915_WRITE(PCH_PP_CONTROL, pp);
		823	POSTING_READ(PCH_PP_CONTROL);
		824	}
2327	Serge	825
2330	Serge	826	static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
		827	{
		828	struct drm_device *dev = intel_dp->base.base.dev;
		829	struct drm_i915_private *dev_priv = dev->dev_private;
		830	u32 pp;
2327	Serge	831
2330	Serge	832	pp = I915_READ(PCH_PP_CONTROL);
		833	pp &= ~EDP_FORCE_VDD;
		834	I915_WRITE(PCH_PP_CONTROL, pp);
		835	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	836
2330	Serge	837	/* Make sure sequencer is idle before allowing subsequent activity */
		838	msleep(dev_priv->panel_t12);
		839	}
2327	Serge	840
2330	Serge	841	/* Returns true if the panel was already on when called */
		842	static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
		843	{
		844	struct drm_device *dev = intel_dp->base.base.dev;
		845	struct drm_i915_private *dev_priv = dev->dev_private;
		846	u32 pp, idle_on_mask = PP_ON \| PP_SEQUENCE_STATE_ON_IDLE;
2327	Serge	847
2330	Serge	848	if (I915_READ(PCH_PP_STATUS) & PP_ON)
		849	return true;
2327	Serge	850
2330	Serge	851	pp = I915_READ(PCH_PP_CONTROL);
2327	Serge	852
2330	Serge	853	/* ILK workaround: disable reset around power sequence */
		854	pp &= ~PANEL_POWER_RESET;
		855	I915_WRITE(PCH_PP_CONTROL, pp);
		856	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	857
2330	Serge	858	pp \|= PANEL_UNLOCK_REGS \| POWER_TARGET_ON;
		859	I915_WRITE(PCH_PP_CONTROL, pp);
		860	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	861
2330	Serge	862	if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
		863	5000))
		864	DRM_ERROR("panel on wait timed out: 0x%08x\n",
		865	I915_READ(PCH_PP_STATUS));
2327	Serge	866
2330	Serge	867	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
		868	I915_WRITE(PCH_PP_CONTROL, pp);
		869	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	870
2330	Serge	871	return false;
		872	}
2327	Serge	873
2330	Serge	874	static void ironlake_edp_panel_off (struct drm_device *dev)
		875	{
		876	struct drm_i915_private *dev_priv = dev->dev_private;
		877	u32 pp, idle_off_mask = PP_ON \| PP_SEQUENCE_MASK \|
		878	PP_CYCLE_DELAY_ACTIVE \| PP_SEQUENCE_STATE_MASK;
2327	Serge	879
2330	Serge	880	pp = I915_READ(PCH_PP_CONTROL);
2327	Serge	881
2330	Serge	882	/* ILK workaround: disable reset around power sequence */
		883	pp &= ~PANEL_POWER_RESET;
		884	I915_WRITE(PCH_PP_CONTROL, pp);
		885	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	886
2330	Serge	887	pp &= ~POWER_TARGET_ON;
		888	I915_WRITE(PCH_PP_CONTROL, pp);
		889	POSTING_READ(PCH_PP_CONTROL);
2327	Serge	890
2330	Serge	891	if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
		892	DRM_ERROR("panel off wait timed out: 0x%08x\n",
		893	I915_READ(PCH_PP_STATUS));
2327	Serge	894
2330	Serge	895	pp \|= PANEL_POWER_RESET; /* restore panel reset bit */
		896	I915_WRITE(PCH_PP_CONTROL, pp);
		897	POSTING_READ(PCH_PP_CONTROL);
		898	}
2327	Serge	899
2330	Serge	900	static void ironlake_edp_backlight_on (struct drm_device *dev)
		901	{
		902	struct drm_i915_private *dev_priv = dev->dev_private;
		903	u32 pp;
2327	Serge	904
2330	Serge	905	DRM_DEBUG_KMS("\n");
		906	/*
		907	* If we enable the backlight right away following a panel power
		908	* on, we may see slight flicker as the panel syncs with the eDP
		909	* link. So delay a bit to make sure the image is solid before
		910	* allowing it to appear.
		911	*/
		912	msleep(300);
		913	pp = I915_READ(PCH_PP_CONTROL);
		914	pp \|= EDP_BLC_ENABLE;
		915	I915_WRITE(PCH_PP_CONTROL, pp);
		916	}
2327	Serge	917
2330	Serge	918	static void ironlake_edp_backlight_off (struct drm_device *dev)
		919	{
		920	struct drm_i915_private *dev_priv = dev->dev_private;
		921	u32 pp;
2327	Serge	922
2330	Serge	923	DRM_DEBUG_KMS("\n");
		924	pp = I915_READ(PCH_PP_CONTROL);
		925	pp &= ~EDP_BLC_ENABLE;
		926	I915_WRITE(PCH_PP_CONTROL, pp);
		927	}
2327	Serge	928
2330	Serge	929	static void ironlake_edp_pll_on(struct drm_encoder *encoder)
		930	{
		931	struct drm_device *dev = encoder->dev;
		932	struct drm_i915_private *dev_priv = dev->dev_private;
		933	u32 dpa_ctl;
2327	Serge	934
2330	Serge	935	DRM_DEBUG_KMS("\n");
		936	dpa_ctl = I915_READ(DP_A);
		937	dpa_ctl \|= DP_PLL_ENABLE;
		938	I915_WRITE(DP_A, dpa_ctl);
		939	POSTING_READ(DP_A);
		940	udelay(200);
		941	}
2327	Serge	942
2330	Serge	943	static void ironlake_edp_pll_off(struct drm_encoder *encoder)
		944	{
		945	struct drm_device *dev = encoder->dev;
		946	struct drm_i915_private *dev_priv = dev->dev_private;
		947	u32 dpa_ctl;
2327	Serge	948
2330	Serge	949	dpa_ctl = I915_READ(DP_A);
		950	dpa_ctl &= ~DP_PLL_ENABLE;
		951	I915_WRITE(DP_A, dpa_ctl);
		952	POSTING_READ(DP_A);
		953	udelay(200);
		954	}
2327	Serge	955
2330	Serge	956	/* If the sink supports it, try to set the power state appropriately */
		957	static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
		958	{
		959	int ret, i;
2327	Serge	960
2330	Serge	961	/* Should have a valid DPCD by this point */
		962	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		963	return;
2327	Serge	964
2330	Serge	965	if (mode != DRM_MODE_DPMS_ON) {
		966	ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
		967	DP_SET_POWER_D3);
		968	if (ret != 1)
		969	DRM_DEBUG_DRIVER("failed to write sink power state\n");
		970	} else {
		971	/*
		972	* When turning on, we need to retry for 1ms to give the sink
		973	* time to wake up.
		974	*/
		975	for (i = 0; i < 3; i++) {
		976	ret = intel_dp_aux_native_write_1(intel_dp,
		977	DP_SET_POWER,
		978	DP_SET_POWER_D0);
		979	if (ret == 1)
		980	break;
		981	msleep(1);
		982	}
		983	}
		984	}
2327	Serge	985
2330	Serge	986	static void intel_dp_prepare(struct drm_encoder *encoder)
		987	{
		988	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		989	struct drm_device *dev = encoder->dev;
2327	Serge	990
2330	Serge	991	/* Wake up the sink first */
		992	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2327	Serge	993
2330	Serge	994	if (is_edp(intel_dp)) {
		995	ironlake_edp_backlight_off(dev);
		996	ironlake_edp_panel_off(dev);
		997	if (!is_pch_edp(intel_dp))
		998	ironlake_edp_pll_on(encoder);
		999	else
		1000	ironlake_edp_pll_off(encoder);
		1001	}
		1002	intel_dp_link_down(intel_dp);
		1003	}
2327	Serge	1004
2330	Serge	1005	static void intel_dp_commit(struct drm_encoder *encoder)
		1006	{
		1007	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1008	struct drm_device *dev = encoder->dev;
2327	Serge	1009
2330	Serge	1010	if (is_edp(intel_dp))
		1011	ironlake_edp_panel_vdd_on(intel_dp);
2327	Serge	1012
2330	Serge	1013	intel_dp_start_link_train(intel_dp);
2327	Serge	1014
2330	Serge	1015	if (is_edp(intel_dp)) {
		1016	ironlake_edp_panel_on(intel_dp);
		1017	ironlake_edp_panel_vdd_off(intel_dp);
		1018	}
2327	Serge	1019
2330	Serge	1020	intel_dp_complete_link_train(intel_dp);
		1021
		1022	if (is_edp(intel_dp))
		1023	ironlake_edp_backlight_on(dev);
		1024
		1025	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
		1026	}
		1027
		1028	static void
		1029	intel_dp_dpms(struct drm_encoder *encoder, int mode)
		1030	{
		1031	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1032	struct drm_device *dev = encoder->dev;
		1033	struct drm_i915_private *dev_priv = dev->dev_private;
		1034	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		1035
		1036	if (mode != DRM_MODE_DPMS_ON) {
		1037	if (is_edp(intel_dp))
		1038	ironlake_edp_backlight_off(dev);
		1039	intel_dp_sink_dpms(intel_dp, mode);
		1040	intel_dp_link_down(intel_dp);
		1041	if (is_edp(intel_dp))
		1042	ironlake_edp_panel_off(dev);
		1043	if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
		1044	ironlake_edp_pll_off(encoder);
		1045	} else {
		1046	if (is_edp(intel_dp))
		1047	ironlake_edp_panel_vdd_on(intel_dp);
		1048	intel_dp_sink_dpms(intel_dp, mode);
		1049	if (!(dp_reg & DP_PORT_EN)) {
		1050	intel_dp_start_link_train(intel_dp);
		1051	if (is_edp(intel_dp)) {
		1052	ironlake_edp_panel_on(intel_dp);
		1053	ironlake_edp_panel_vdd_off(intel_dp);
		1054	}
		1055	intel_dp_complete_link_train(intel_dp);
		1056	}
		1057	if (is_edp(intel_dp))
		1058	ironlake_edp_backlight_on(dev);
		1059	}
		1060	intel_dp->dpms_mode = mode;
		1061	}
		1062
		1063	/*
		1064	* Native read with retry for link status and receiver capability reads for
		1065	* cases where the sink may still be asleep.
		1066	*/
		1067	static bool
		1068	intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
		1069	uint8_t *recv, int recv_bytes)
		1070	{
		1071	int ret, i;
		1072
		1073	/*
		1074	* Sinks are supposed to come up within 1ms from an off state,
		1075	* but we're also supposed to retry 3 times per the spec.
		1076	*/
		1077	for (i = 0; i < 3; i++) {
		1078	ret = intel_dp_aux_native_read(intel_dp, address, recv,
		1079	recv_bytes);
		1080	if (ret == recv_bytes)
		1081	return true;
		1082	msleep(1);
		1083	}
		1084
		1085	return false;
		1086	}
		1087
		1088	/*
		1089	* Fetch AUX CH registers 0x202 - 0x207 which contain
		1090	* link status information
		1091	*/
		1092	static bool
		1093	intel_dp_get_link_status(struct intel_dp *intel_dp)
		1094	{
		1095	return intel_dp_aux_native_read_retry(intel_dp,
		1096	DP_LANE0_1_STATUS,
		1097	intel_dp->link_status,
		1098	DP_LINK_STATUS_SIZE);
		1099	}
		1100
		1101	static uint8_t
		1102	intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1103	int r)
		1104	{
		1105	return link_status[r - DP_LANE0_1_STATUS];
		1106	}
		1107
		1108	static uint8_t
		1109	intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1110	int lane)
		1111	{
		1112	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
		1113	int s = ((lane & 1) ?
		1114	DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
		1115	DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
		1116	uint8_t l = intel_dp_link_status(link_status, i);
		1117
		1118	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
		1119	}
		1120
		1121	static uint8_t
		1122	intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1123	int lane)
		1124	{
		1125	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
		1126	int s = ((lane & 1) ?
		1127	DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
		1128	DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
		1129	uint8_t l = intel_dp_link_status(link_status, i);
		1130
		1131	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
		1132	}
		1133
		1134
		1135	#if 0
		1136	static char *voltage_names[] = {
		1137	"0.4V", "0.6V", "0.8V", "1.2V"
		1138	};
		1139	static char *pre_emph_names[] = {
		1140	"0dB", "3.5dB", "6dB", "9.5dB"
		1141	};
		1142	static char *link_train_names[] = {
		1143	"pattern 1", "pattern 2", "idle", "off"
		1144	};
		1145	#endif
		1146
		1147	/*
		1148	* These are source-specific values; current Intel hardware supports
		1149	* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
		1150	*/
		1151	#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
		1152
		1153	static uint8_t
		1154	intel_dp_pre_emphasis_max(uint8_t voltage_swing)
		1155	{
		1156	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1157	case DP_TRAIN_VOLTAGE_SWING_400:
		1158	return DP_TRAIN_PRE_EMPHASIS_6;
		1159	case DP_TRAIN_VOLTAGE_SWING_600:
		1160	return DP_TRAIN_PRE_EMPHASIS_6;
		1161	case DP_TRAIN_VOLTAGE_SWING_800:
		1162	return DP_TRAIN_PRE_EMPHASIS_3_5;
		1163	case DP_TRAIN_VOLTAGE_SWING_1200:
		1164	default:
		1165	return DP_TRAIN_PRE_EMPHASIS_0;
		1166	}
		1167	}
		1168
		1169	static void
		1170	intel_get_adjust_train(struct intel_dp *intel_dp)
		1171	{
		1172	uint8_t v = 0;
		1173	uint8_t p = 0;
		1174	int lane;
		1175
		1176	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		1177	uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
		1178	uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
		1179
		1180	if (this_v > v)
		1181	v = this_v;
		1182	if (this_p > p)
		1183	p = this_p;
		1184	}
		1185
		1186	if (v >= I830_DP_VOLTAGE_MAX)
		1187	v = I830_DP_VOLTAGE_MAX \| DP_TRAIN_MAX_SWING_REACHED;
		1188
		1189	if (p >= intel_dp_pre_emphasis_max(v))
		1190	p = intel_dp_pre_emphasis_max(v) \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
		1191
		1192	for (lane = 0; lane < 4; lane++)
		1193	intel_dp->train_set[lane] = v \| p;
		1194	}
		1195
		1196	static uint32_t
		1197	intel_dp_signal_levels(uint8_t train_set, int lane_count)
		1198	{
		1199	uint32_t signal_levels = 0;
		1200
		1201	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		1202	case DP_TRAIN_VOLTAGE_SWING_400:
		1203	default:
		1204	signal_levels \|= DP_VOLTAGE_0_4;
		1205	break;
		1206	case DP_TRAIN_VOLTAGE_SWING_600:
		1207	signal_levels \|= DP_VOLTAGE_0_6;
		1208	break;
		1209	case DP_TRAIN_VOLTAGE_SWING_800:
		1210	signal_levels \|= DP_VOLTAGE_0_8;
		1211	break;
		1212	case DP_TRAIN_VOLTAGE_SWING_1200:
		1213	signal_levels \|= DP_VOLTAGE_1_2;
		1214	break;
		1215	}
		1216	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
		1217	case DP_TRAIN_PRE_EMPHASIS_0:
		1218	default:
		1219	signal_levels \|= DP_PRE_EMPHASIS_0;
		1220	break;
		1221	case DP_TRAIN_PRE_EMPHASIS_3_5:
		1222	signal_levels \|= DP_PRE_EMPHASIS_3_5;
		1223	break;
		1224	case DP_TRAIN_PRE_EMPHASIS_6:
		1225	signal_levels \|= DP_PRE_EMPHASIS_6;
		1226	break;
		1227	case DP_TRAIN_PRE_EMPHASIS_9_5:
		1228	signal_levels \|= DP_PRE_EMPHASIS_9_5;
		1229	break;
		1230	}
		1231	return signal_levels;
		1232	}
		1233
		1234	/* Gen6's DP voltage swing and pre-emphasis control */
		1235	static uint32_t
		1236	intel_gen6_edp_signal_levels(uint8_t train_set)
		1237	{
		1238	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		1239	DP_TRAIN_PRE_EMPHASIS_MASK);
		1240	switch (signal_levels) {
		1241	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_0:
		1242	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_0:
		1243	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1244	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1245	return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
		1246	case DP_TRAIN_VOLTAGE_SWING_400 \| DP_TRAIN_PRE_EMPHASIS_6:
		1247	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_6:
		1248	return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
		1249	case DP_TRAIN_VOLTAGE_SWING_600 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1250	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_3_5:
		1251	return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
		1252	case DP_TRAIN_VOLTAGE_SWING_800 \| DP_TRAIN_PRE_EMPHASIS_0:
		1253	case DP_TRAIN_VOLTAGE_SWING_1200 \| DP_TRAIN_PRE_EMPHASIS_0:
		1254	return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
		1255	default:
		1256	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
		1257	"0x%x\n", signal_levels);
		1258	return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
		1259	}
		1260	}
		1261
		1262	static uint8_t
		1263	intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		1264	int lane)
		1265	{
		1266	int i = DP_LANE0_1_STATUS + (lane >> 1);
		1267	int s = (lane & 1) * 4;
		1268	uint8_t l = intel_dp_link_status(link_status, i);
		1269
		1270	return (l >> s) & 0xf;
		1271	}
		1272
		1273	/* Check for clock recovery is done on all channels */
		1274	static bool
		1275	intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
		1276	{
		1277	int lane;
		1278	uint8_t lane_status;
		1279
		1280	for (lane = 0; lane < lane_count; lane++) {
		1281	lane_status = intel_get_lane_status(link_status, lane);
		1282	if ((lane_status & DP_LANE_CR_DONE) == 0)
		1283	return false;
		1284	}
		1285	return true;
		1286	}
		1287
		1288	/* Check to see if channel eq is done on all channels */
		1289	#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE\|\
		1290	DP_LANE_CHANNEL_EQ_DONE\|\
		1291	DP_LANE_SYMBOL_LOCKED)
		1292	static bool
		1293	intel_channel_eq_ok(struct intel_dp *intel_dp)
		1294	{
		1295	uint8_t lane_align;
		1296	uint8_t lane_status;
		1297	int lane;
		1298
		1299	lane_align = intel_dp_link_status(intel_dp->link_status,
		1300	DP_LANE_ALIGN_STATUS_UPDATED);
		1301	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		1302	return false;
		1303	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		1304	lane_status = intel_get_lane_status(intel_dp->link_status, lane);
		1305	if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
		1306	return false;
		1307	}
		1308	return true;
		1309	}
		1310
		1311	static bool
		1312	intel_dp_set_link_train(struct intel_dp *intel_dp,
		1313	uint32_t dp_reg_value,
		1314	uint8_t dp_train_pat)
		1315	{
		1316	struct drm_device *dev = intel_dp->base.base.dev;
		1317	struct drm_i915_private *dev_priv = dev->dev_private;
		1318	int ret;
		1319
		1320	I915_WRITE(intel_dp->output_reg, dp_reg_value);
		1321	POSTING_READ(intel_dp->output_reg);
		1322
		1323	intel_dp_aux_native_write_1(intel_dp,
		1324	DP_TRAINING_PATTERN_SET,
		1325	dp_train_pat);
		1326
		1327	ret = intel_dp_aux_native_write(intel_dp,
		1328	DP_TRAINING_LANE0_SET,
		1329	intel_dp->train_set, 4);
		1330	if (ret != 4)
		1331	return false;
		1332
		1333	return true;
		1334	}
		1335
		1336	/* Enable corresponding port and start training pattern 1 */
		1337	static void
		1338	intel_dp_start_link_train(struct intel_dp *intel_dp)
		1339	{
		1340	struct drm_device *dev = intel_dp->base.base.dev;
		1341	struct drm_i915_private *dev_priv = dev->dev_private;
		1342	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
		1343	int i;
		1344	uint8_t voltage;
		1345	bool clock_recovery = false;
		1346	int tries;
		1347	u32 reg;
		1348	uint32_t DP = intel_dp->DP;
		1349
		1350	/*
		1351	* On CPT we have to enable the port in training pattern 1, which
		1352	* will happen below in intel_dp_set_link_train. Otherwise, enable
		1353	* the port and wait for it to become active.
		1354	*/
		1355	if (!HAS_PCH_CPT(dev)) {
		1356	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
		1357	POSTING_READ(intel_dp->output_reg);
		1358	intel_wait_for_vblank(dev, intel_crtc->pipe);
		1359	}
		1360
		1361	/* Write the link configuration data */
		1362	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
		1363	intel_dp->link_configuration,
		1364	DP_LINK_CONFIGURATION_SIZE);
		1365
		1366	DP \|= DP_PORT_EN;
		1367	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
		1368	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1369	else
		1370	DP &= ~DP_LINK_TRAIN_MASK;
		1371	memset(intel_dp->train_set, 0, 4);
		1372	voltage = 0xff;
		1373	tries = 0;
		1374	clock_recovery = false;
		1375	for (;;) {
		1376	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
		1377	uint32_t signal_levels;
		1378	if (IS_GEN6(dev) && is_edp(intel_dp)) {
		1379	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1380	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1381	} else {
		1382	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
		1383	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1384	}
		1385
		1386	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
		1387	reg = DP \| DP_LINK_TRAIN_PAT_1_CPT;
		1388	else
		1389	reg = DP \| DP_LINK_TRAIN_PAT_1;
		1390
		1391	if (!intel_dp_set_link_train(intel_dp, reg,
		1392	DP_TRAINING_PATTERN_1 \|
		1393	DP_LINK_SCRAMBLING_DISABLE))
		1394	break;
		1395	/* Set training pattern 1 */
		1396
		1397	udelay(100);
		1398	if (!intel_dp_get_link_status(intel_dp))
		1399	break;
		1400
		1401	if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
		1402	clock_recovery = true;
		1403	break;
		1404	}
		1405
		1406	/* Check to see if we've tried the max voltage */
		1407	for (i = 0; i < intel_dp->lane_count; i++)
		1408	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
		1409	break;
		1410	if (i == intel_dp->lane_count)
		1411	break;
		1412
		1413	/* Check to see if we've tried the same voltage 5 times */
		1414	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
		1415	++tries;
		1416	if (tries == 5)
		1417	break;
		1418	} else
		1419	tries = 0;
		1420	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
		1421
		1422	/* Compute new intel_dp->train_set as requested by target */
		1423	intel_get_adjust_train(intel_dp);
		1424	}
		1425
		1426	intel_dp->DP = DP;
		1427	}
		1428
		1429	static void
		1430	intel_dp_complete_link_train(struct intel_dp *intel_dp)
		1431	{
		1432	struct drm_device *dev = intel_dp->base.base.dev;
		1433	struct drm_i915_private *dev_priv = dev->dev_private;
		1434	bool channel_eq = false;
		1435	int tries, cr_tries;
		1436	u32 reg;
		1437	uint32_t DP = intel_dp->DP;
		1438
		1439	/* channel equalization */
		1440	tries = 0;
		1441	cr_tries = 0;
		1442	channel_eq = false;
		1443	for (;;) {
		1444	/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
		1445	uint32_t signal_levels;
		1446
		1447	if (cr_tries > 5) {
		1448	DRM_ERROR("failed to train DP, aborting\n");
		1449	intel_dp_link_down(intel_dp);
		1450	break;
		1451	}
		1452
		1453	if (IS_GEN6(dev) && is_edp(intel_dp)) {
		1454	signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
		1455	DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) \| signal_levels;
		1456	} else {
		1457	signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
		1458	DP = (DP & ~(DP_VOLTAGE_MASK\|DP_PRE_EMPHASIS_MASK)) \| signal_levels;
		1459	}
		1460
		1461	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
		1462	reg = DP \| DP_LINK_TRAIN_PAT_2_CPT;
		1463	else
		1464	reg = DP \| DP_LINK_TRAIN_PAT_2;
		1465
		1466	/* channel eq pattern */
		1467	if (!intel_dp_set_link_train(intel_dp, reg,
		1468	DP_TRAINING_PATTERN_2 \|
		1469	DP_LINK_SCRAMBLING_DISABLE))
		1470	break;
		1471
		1472	udelay(400);
		1473	if (!intel_dp_get_link_status(intel_dp))
		1474	break;
		1475
		1476	/* Make sure clock is still ok */
		1477	if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
		1478	intel_dp_start_link_train(intel_dp);
		1479	cr_tries++;
		1480	continue;
		1481	}
		1482
		1483	if (intel_channel_eq_ok(intel_dp)) {
		1484	channel_eq = true;
		1485	break;
		1486	}
		1487
		1488	/* Try 5 times, then try clock recovery if that fails */
		1489	if (tries > 5) {
		1490	intel_dp_link_down(intel_dp);
		1491	intel_dp_start_link_train(intel_dp);
		1492	tries = 0;
		1493	cr_tries++;
		1494	continue;
		1495	}
		1496
		1497	/* Compute new intel_dp->train_set as requested by target */
		1498	intel_get_adjust_train(intel_dp);
		1499	++tries;
		1500	}
		1501
		1502	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
		1503	reg = DP \| DP_LINK_TRAIN_OFF_CPT;
		1504	else
		1505	reg = DP \| DP_LINK_TRAIN_OFF;
		1506
		1507	I915_WRITE(intel_dp->output_reg, reg);
		1508	POSTING_READ(intel_dp->output_reg);
		1509	intel_dp_aux_native_write_1(intel_dp,
		1510	DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
		1511	}
		1512
		1513	static void
		1514	intel_dp_link_down(struct intel_dp *intel_dp)
		1515	{
		1516	struct drm_device *dev = intel_dp->base.base.dev;
		1517	struct drm_i915_private *dev_priv = dev->dev_private;
		1518	uint32_t DP = intel_dp->DP;
		1519
		1520	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
		1521	return;
		1522
		1523	DRM_DEBUG_KMS("\n");
		1524
		1525	if (is_edp(intel_dp)) {
		1526	DP &= ~DP_PLL_ENABLE;
		1527	I915_WRITE(intel_dp->output_reg, DP);
		1528	POSTING_READ(intel_dp->output_reg);
		1529	udelay(100);
		1530	}
		1531
		1532	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
		1533	DP &= ~DP_LINK_TRAIN_MASK_CPT;
		1534	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE_CPT);
		1535	} else {
		1536	DP &= ~DP_LINK_TRAIN_MASK;
		1537	I915_WRITE(intel_dp->output_reg, DP \| DP_LINK_TRAIN_PAT_IDLE);
		1538	}
		1539	POSTING_READ(intel_dp->output_reg);
		1540
		1541	msleep(17);
		1542
		1543	if (is_edp(intel_dp))
		1544	DP \|= DP_LINK_TRAIN_OFF;
		1545
		1546	if (!HAS_PCH_CPT(dev) &&
		1547	I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
		1548	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		1549
		1550	/* Hardware workaround: leaving our transcoder select
		1551	* set to transcoder B while it's off will prevent the
		1552	* corresponding HDMI output on transcoder A.
		1553	*
		1554	* Combine this with another hardware workaround:
		1555	* transcoder select bit can only be cleared while the
		1556	* port is enabled.
		1557	*/
		1558	DP &= ~DP_PIPEB_SELECT;
		1559	I915_WRITE(intel_dp->output_reg, DP);
		1560
		1561	/* Changes to enable or select take place the vblank
		1562	* after being written.
		1563	*/
		1564	if (crtc == NULL) {
		1565	/* We can arrive here never having been attached
		1566	* to a CRTC, for instance, due to inheriting
		1567	* random state from the BIOS.
		1568	*
		1569	* If the pipe is not running, play safe and
		1570	* wait for the clocks to stabilise before
		1571	* continuing.
		1572	*/
		1573	POSTING_READ(intel_dp->output_reg);
		1574	msleep(50);
		1575	} else
		1576	intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
		1577	}
		1578
		1579	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
		1580	POSTING_READ(intel_dp->output_reg);
		1581	}
		1582
		1583	static bool
		1584	intel_dp_get_dpcd(struct intel_dp *intel_dp)
		1585	{
		1586	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
		1587	sizeof (intel_dp->dpcd)) &&
		1588	(intel_dp->dpcd[DP_DPCD_REV] != 0)) {
		1589	return true;
		1590	}
		1591
		1592	return false;
		1593	}
		1594
		1595	/*
		1596	* According to DP spec
		1597	* 5.1.2:
		1598	* 1. Read DPCD
		1599	* 2. Configure link according to Receiver Capabilities
		1600	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
		1601	* 4. Check link status on receipt of hot-plug interrupt
		1602	*/
		1603
		1604	static void
		1605	intel_dp_check_link_status(struct intel_dp *intel_dp)
		1606	{
		1607	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
		1608	return;
		1609
		1610	if (!intel_dp->base.base.crtc)
		1611	return;
		1612
		1613	/* Try to read receiver status if the link appears to be up */
		1614	if (!intel_dp_get_link_status(intel_dp)) {
		1615	intel_dp_link_down(intel_dp);
		1616	return;
		1617	}
		1618
		1619	/* Now read the DPCD to see if it's actually running */
		1620	if (!intel_dp_get_dpcd(intel_dp)) {
		1621	intel_dp_link_down(intel_dp);
		1622	return;
		1623	}
		1624
		1625	if (!intel_channel_eq_ok(intel_dp)) {
		1626	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
		1627	drm_get_encoder_name(&intel_dp->base.base));
		1628	intel_dp_start_link_train(intel_dp);
		1629	intel_dp_complete_link_train(intel_dp);
		1630	}
		1631	}
		1632
		1633	static enum drm_connector_status
		1634	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
		1635	{
		1636	if (intel_dp_get_dpcd(intel_dp))
		1637	return connector_status_connected;
		1638	return connector_status_disconnected;
		1639	}
		1640
		1641	static enum drm_connector_status
		1642	ironlake_dp_detect(struct intel_dp *intel_dp)
		1643	{
		1644	enum drm_connector_status status;
		1645
		1646	/* Can't disconnect eDP, but you can close the lid... */
		1647	if (is_edp(intel_dp)) {
		1648	status = intel_panel_detect(intel_dp->base.base.dev);
		1649	if (status == connector_status_unknown)
		1650	status = connector_status_connected;
		1651	return status;
		1652	}
		1653
		1654	return intel_dp_detect_dpcd(intel_dp);
		1655	}
		1656
		1657	static enum drm_connector_status
		1658	g4x_dp_detect(struct intel_dp *intel_dp)
		1659	{
		1660	struct drm_device *dev = intel_dp->base.base.dev;
		1661	struct drm_i915_private *dev_priv = dev->dev_private;
		1662	uint32_t temp, bit;
		1663
		1664	switch (intel_dp->output_reg) {
		1665	case DP_B:
		1666	bit = DPB_HOTPLUG_INT_STATUS;
		1667	break;
		1668	case DP_C:
		1669	bit = DPC_HOTPLUG_INT_STATUS;
		1670	break;
		1671	case DP_D:
		1672	bit = DPD_HOTPLUG_INT_STATUS;
		1673	break;
		1674	default:
		1675	return connector_status_unknown;
		1676	}
		1677
		1678	temp = I915_READ(PORT_HOTPLUG_STAT);
		1679
		1680	if ((temp & bit) == 0)
		1681	return connector_status_disconnected;
		1682
		1683	return intel_dp_detect_dpcd(intel_dp);
		1684	}
		1685
		1686	/**
		1687	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
		1688	*
		1689	* \return true if DP port is connected.
		1690	* \return false if DP port is disconnected.
		1691	*/
		1692	static enum drm_connector_status
		1693	intel_dp_detect(struct drm_connector *connector, bool force)
		1694	{
		1695	struct intel_dp *intel_dp = intel_attached_dp(connector);
		1696	struct drm_device *dev = intel_dp->base.base.dev;
		1697	enum drm_connector_status status;
		1698	struct edid *edid = NULL;
		1699
		1700	intel_dp->has_audio = false;
		1701
		1702	if (HAS_PCH_SPLIT(dev))
		1703	status = ironlake_dp_detect(intel_dp);
		1704	else
		1705	status = g4x_dp_detect(intel_dp);
		1706
		1707	DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
		1708	intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
		1709	intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
		1710	intel_dp->dpcd[6], intel_dp->dpcd[7]);
		1711
		1712	if (status != connector_status_connected)
		1713	return status;
		1714	/*
		1715	if (intel_dp->force_audio) {
		1716	intel_dp->has_audio = intel_dp->force_audio > 0;
		1717	} else {
		1718	edid = drm_get_edid(connector, &intel_dp->adapter);
		1719	if (edid) {
		1720	intel_dp->has_audio = drm_detect_monitor_audio(edid);
		1721	connector->display_info.raw_edid = NULL;
		1722	kfree(edid);
		1723	}
		1724	}
		1725	*/
		1726	return connector_status_connected;
		1727	}
		1728
		1729	static int intel_dp_get_modes(struct drm_connector *connector)
		1730	{
		1731	struct intel_dp *intel_dp = intel_attached_dp(connector);
		1732	struct drm_device *dev = intel_dp->base.base.dev;
		1733	struct drm_i915_private *dev_priv = dev->dev_private;
		1734	int ret;
		1735
		1736	/* We should parse the EDID data and find out if it has an audio sink
		1737	*/
		1738
		1739	ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
		1740	if (ret) {
		1741	if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
		1742	struct drm_display_mode *newmode;
		1743	list_for_each_entry(newmode, &connector->probed_modes,
		1744	head) {
		1745	if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
		1746	dev_priv->panel_fixed_mode =
		1747	drm_mode_duplicate(dev, newmode);
		1748	break;
		1749	}
		1750	}
		1751	}
		1752
		1753	return ret;
		1754	}
		1755
		1756	/* if eDP has no EDID, try to use fixed panel mode from VBT */
		1757	if (is_edp(intel_dp)) {
		1758	if (dev_priv->panel_fixed_mode != NULL) {
		1759	struct drm_display_mode *mode;
		1760	mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
		1761	drm_mode_probed_add(connector, mode);
		1762	return 1;
		1763	}
		1764	}
		1765	return 0;
		1766	}
		1767
		1768
		1769
		1770
		1771
		1772	static int
		1773	intel_dp_set_property(struct drm_connector *connector,
		1774	struct drm_property *property,
		1775	uint64_t val)
		1776	{
		1777	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1778	struct intel_dp *intel_dp = intel_attached_dp(connector);
		1779	int ret;
		1780
		1781	ret = drm_connector_property_set_value(connector, property, val);
		1782	if (ret)
		1783	return ret;
		1784	#if 0
		1785	if (property == dev_priv->force_audio_property) {
		1786	int i = val;
		1787	bool has_audio;
		1788
		1789	if (i == intel_dp->force_audio)
		1790	return 0;
		1791
		1792	intel_dp->force_audio = i;
		1793
		1794	if (i == 0)
		1795	has_audio = intel_dp_detect_audio(connector);
		1796	else
		1797	has_audio = i > 0;
		1798
		1799	if (has_audio == intel_dp->has_audio)
		1800	return 0;
		1801
		1802	intel_dp->has_audio = has_audio;
		1803	goto done;
		1804	}
		1805
		1806	if (property == dev_priv->broadcast_rgb_property) {
		1807	if (val == !!intel_dp->color_range)
		1808	return 0;
		1809
		1810	intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
		1811	goto done;
		1812	}
		1813	#endif
		1814
		1815	return -EINVAL;
		1816
		1817	done:
		1818	if (intel_dp->base.base.crtc) {
		1819	struct drm_crtc *crtc = intel_dp->base.base.crtc;
		1820	drm_crtc_helper_set_mode(crtc, &crtc->mode,
		1821	crtc->x, crtc->y,
		1822	crtc->fb);
		1823	}
		1824
		1825	return 0;
		1826	}
		1827
		1828	static void
		1829	intel_dp_destroy (struct drm_connector *connector)
		1830	{
		1831	struct drm_device *dev = connector->dev;
		1832
		1833	if (intel_dpd_is_edp(dev))
		1834	intel_panel_destroy_backlight(dev);
		1835
		1836	drm_sysfs_connector_remove(connector);
		1837	drm_connector_cleanup(connector);
		1838	kfree(connector);
		1839	}
		1840
		1841	static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
		1842	{
		1843	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		1844
		1845	// i2c_del_adapter(&intel_dp->adapter);
		1846	drm_encoder_cleanup(encoder);
		1847	kfree(intel_dp);
		1848	}
		1849
		1850	static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
		1851	.dpms = intel_dp_dpms,
		1852	.mode_fixup = intel_dp_mode_fixup,
		1853	.prepare = intel_dp_prepare,
		1854	.mode_set = intel_dp_mode_set,
		1855	.commit = intel_dp_commit,
		1856	};
		1857
		1858	static const struct drm_connector_funcs intel_dp_connector_funcs = {
		1859	.dpms = drm_helper_connector_dpms,
		1860	.detect = intel_dp_detect,
		1861	.fill_modes = drm_helper_probe_single_connector_modes,
		1862	.set_property = intel_dp_set_property,
		1863	.destroy = intel_dp_destroy,
		1864	};
		1865
		1866	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
		1867	.get_modes = intel_dp_get_modes,
		1868	.mode_valid = intel_dp_mode_valid,
		1869	.best_encoder = intel_best_encoder,
		1870	};
		1871
		1872	static const struct drm_encoder_funcs intel_dp_enc_funcs = {
		1873	.destroy = intel_dp_encoder_destroy,
		1874	};
		1875
		1876	static void
		1877	intel_dp_hot_plug(struct intel_encoder *intel_encoder)
		1878	{
		1879	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
		1880
		1881	intel_dp_check_link_status(intel_dp);
		1882	}
		1883
2327	Serge	1884	/* Return which DP Port should be selected for Transcoder DP control */
		1885	int
		1886	intel_trans_dp_port_sel (struct drm_crtc *crtc)
		1887	{
		1888	struct drm_device *dev = crtc->dev;
		1889	struct drm_mode_config *mode_config = &dev->mode_config;
		1890	struct drm_encoder *encoder;
		1891
		1892	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		1893	struct intel_dp *intel_dp;
		1894
		1895	if (encoder->crtc != crtc)
		1896	continue;
		1897
		1898	intel_dp = enc_to_intel_dp(encoder);
		1899	if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
		1900	return intel_dp->output_reg;
		1901	}
		1902
		1903	return -1;
		1904	}
2330	Serge	1905
		1906	/* check the VBT to see whether the eDP is on DP-D port */
		1907	bool intel_dpd_is_edp(struct drm_device *dev)
		1908	{
		1909	struct drm_i915_private *dev_priv = dev->dev_private;
		1910	struct child_device_config *p_child;
		1911	int i;
		1912
		1913	if (!dev_priv->child_dev_num)
		1914	return false;
		1915
		1916	for (i = 0; i < dev_priv->child_dev_num; i++) {
		1917	p_child = dev_priv->child_dev + i;
		1918
		1919	if (p_child->dvo_port == PORT_IDPD &&
		1920	p_child->device_type == DEVICE_TYPE_eDP)
		1921	return true;
		1922	}
		1923	return false;
		1924	}
		1925
		1926	static void
		1927	intel_dp_add_properties(struct intel_dp intel_dp, struct drm_connector connector)
		1928	{
		1929	intel_attach_force_audio_property(connector);
		1930	intel_attach_broadcast_rgb_property(connector);
		1931	}
		1932
		1933	void
		1934	intel_dp_init(struct drm_device *dev, int output_reg)
		1935	{
		1936	struct drm_i915_private *dev_priv = dev->dev_private;
		1937	struct drm_connector *connector;
		1938	struct intel_dp *intel_dp;
		1939	struct intel_encoder *intel_encoder;
		1940	struct intel_connector *intel_connector;
		1941	const char *name = NULL;
		1942	int type;
		1943
		1944	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
		1945	if (!intel_dp)
		1946	return;
		1947
		1948	intel_dp->output_reg = output_reg;
		1949	intel_dp->dpms_mode = -1;
		1950
		1951	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
		1952	if (!intel_connector) {
		1953	kfree(intel_dp);
		1954	return;
		1955	}
		1956	intel_encoder = &intel_dp->base;
		1957
		1958	if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
		1959	if (intel_dpd_is_edp(dev))
		1960	intel_dp->is_pch_edp = true;
		1961
		1962	if (output_reg == DP_A \|\| is_pch_edp(intel_dp)) {
		1963	type = DRM_MODE_CONNECTOR_eDP;
		1964	intel_encoder->type = INTEL_OUTPUT_EDP;
		1965	} else {
		1966	type = DRM_MODE_CONNECTOR_DisplayPort;
		1967	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		1968	}
		1969
		1970	connector = &intel_connector->base;
		1971	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
		1972	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
		1973
		1974	connector->polled = DRM_CONNECTOR_POLL_HPD;
		1975
		1976	if (output_reg == DP_B \|\| output_reg == PCH_DP_B)
		1977	intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
		1978	else if (output_reg == DP_C \|\| output_reg == PCH_DP_C)
		1979	intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
		1980	else if (output_reg == DP_D \|\| output_reg == PCH_DP_D)
		1981	intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
		1982
		1983	if (is_edp(intel_dp))
		1984	intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
		1985
		1986	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
		1987	connector->interlace_allowed = true;
		1988	connector->doublescan_allowed = 0;
		1989
		1990	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
		1991	DRM_MODE_ENCODER_TMDS);
		1992	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
		1993
		1994	intel_connector_attach_encoder(intel_connector, intel_encoder);
		1995	drm_sysfs_connector_add(connector);
		1996
		1997	/* Set up the DDC bus. */
		1998	switch (output_reg) {
		1999	case DP_A:
		2000	name = "DPDDC-A";
		2001	break;
		2002	case DP_B:
		2003	case PCH_DP_B:
		2004	dev_priv->hotplug_supported_mask \|=
		2005	HDMIB_HOTPLUG_INT_STATUS;
		2006	name = "DPDDC-B";
		2007	break;
		2008	case DP_C:
		2009	case PCH_DP_C:
		2010	dev_priv->hotplug_supported_mask \|=
		2011	HDMIC_HOTPLUG_INT_STATUS;
		2012	name = "DPDDC-C";
		2013	break;
		2014	case DP_D:
		2015	case PCH_DP_D:
		2016	dev_priv->hotplug_supported_mask \|=
		2017	HDMID_HOTPLUG_INT_STATUS;
		2018	name = "DPDDC-D";
		2019	break;
		2020	}
		2021
		2022	intel_dp_i2c_init(intel_dp, intel_connector, name);
		2023
		2024	/* Cache some DPCD data in the eDP case */
		2025	if (is_edp(intel_dp)) {
		2026	bool ret;
		2027	u32 pp_on, pp_div;
		2028
		2029	pp_on = I915_READ(PCH_PP_ON_DELAYS);
		2030	pp_div = I915_READ(PCH_PP_DIVISOR);
		2031
		2032	/* Get T3 & T12 values (note: VESA not bspec terminology) */
		2033	dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
		2034	dev_priv->panel_t3 /= 10; /* t3 in 100us units */
		2035	dev_priv->panel_t12 = pp_div & 0xf;
		2036	dev_priv->panel_t12 = 100; / t12 in 100ms units */
		2037
		2038	ironlake_edp_panel_vdd_on(intel_dp);
		2039	ret = intel_dp_get_dpcd(intel_dp);
		2040	ironlake_edp_panel_vdd_off(intel_dp);
		2041	if (ret) {
		2042	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		2043	dev_priv->no_aux_handshake =
		2044	intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
		2045	DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		2046	} else {
		2047	/* if this fails, presume the device is a ghost */
		2048	DRM_INFO("failed to retrieve link info, disabling eDP\n");
		2049	intel_dp_encoder_destroy(&intel_dp->base.base);
		2050	intel_dp_destroy(&intel_connector->base);
		2051	return;
		2052	}
		2053	}
		2054
		2055	intel_encoder->hot_plug = intel_dp_hot_plug;
		2056
		2057	if (is_edp(intel_dp)) {
		2058	/* initialize panel mode from VBT if available for eDP */
		2059	if (dev_priv->lfp_lvds_vbt_mode) {
		2060	dev_priv->panel_fixed_mode =
		2061	drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
		2062	if (dev_priv->panel_fixed_mode) {
		2063	dev_priv->panel_fixed_mode->type \|=
		2064	DRM_MODE_TYPE_PREFERRED;
		2065	}
		2066	}
		2067	dev_priv->int_edp_connector = connector;
		2068	intel_panel_setup_backlight(dev);
		2069	}
		2070
		2071	intel_dp_add_properties(intel_dp, connector);
		2072
		2073	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
		2074	* 0xd. Failure to do so will result in spurious interrupts being
		2075	* generated on the port when a cable is not attached.
		2076	*/
		2077	if (IS_G4X(dev) && !IS_GM45(dev)) {
		2078	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		2079	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
		2080	}
		2081	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dp.c – Rev 2330