WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
4104	Serge	44	#define MAX_ERRNO 4095
2327	Serge	45	phys_addr_t get_bus_addr(void);
		46
2342	Serge	47	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	48	static void intel_increase_pllclock(struct drm_crtc *crtc);
3243	Serge	49	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	50
4104	Serge	51	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		52	struct intel_crtc_config *pipe_config);
		53	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		54	struct intel_crtc_config *pipe_config);
2327	Serge	55
4104	Serge	56	static int intel_set_mode(struct drm_crtc crtc, struct drm_display_mode mode,
		57	int x, int y, struct drm_framebuffer *old_fb);
		58
		59
2327	Serge	60	typedef struct {
		61	int min, max;
		62	} intel_range_t;
		63
		64	typedef struct {
		65	int dot_limit;
		66	int p2_slow, p2_fast;
		67	} intel_p2_t;
		68
		69	typedef struct intel_limit intel_limit_t;
		70	struct intel_limit {
		71	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		72	intel_p2_t p2;
		73	};
		74
		75	/* FDI */
		76	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		77
3243	Serge	78	int
		79	intel_pch_rawclk(struct drm_device *dev)
		80	{
		81	struct drm_i915_private *dev_priv = dev->dev_private;
		82
		83	WARN_ON(!HAS_PCH_SPLIT(dev));
		84
		85	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		86	}
		87
2327	Serge	88	static inline u32 /* units of 100MHz */
		89	intel_fdi_link_freq(struct drm_device *dev)
		90	{
		91	if (IS_GEN5(dev)) {
		92	struct drm_i915_private *dev_priv = dev->dev_private;
		93	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		94	} else
		95	return 27;
		96	}
		97
4104	Serge	98	static const intel_limit_t intel_limits_i8xx_dac = {
		99	.dot = { .min = 25000, .max = 350000 },
		100	.vco = { .min = 930000, .max = 1400000 },
		101	.n = { .min = 3, .max = 16 },
		102	.m = { .min = 96, .max = 140 },
		103	.m1 = { .min = 18, .max = 26 },
		104	.m2 = { .min = 6, .max = 16 },
		105	.p = { .min = 4, .max = 128 },
		106	.p1 = { .min = 2, .max = 33 },
		107	.p2 = { .dot_limit = 165000,
		108	.p2_slow = 4, .p2_fast = 2 },
		109	};
		110
2327	Serge	111	static const intel_limit_t intel_limits_i8xx_dvo = {
		112	.dot = { .min = 25000, .max = 350000 },
		113	.vco = { .min = 930000, .max = 1400000 },
		114	.n = { .min = 3, .max = 16 },
		115	.m = { .min = 96, .max = 140 },
		116	.m1 = { .min = 18, .max = 26 },
		117	.m2 = { .min = 6, .max = 16 },
		118	.p = { .min = 4, .max = 128 },
		119	.p1 = { .min = 2, .max = 33 },
		120	.p2 = { .dot_limit = 165000,
4104	Serge	121	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	122	};
		123
		124	static const intel_limit_t intel_limits_i8xx_lvds = {
		125	.dot = { .min = 25000, .max = 350000 },
		126	.vco = { .min = 930000, .max = 1400000 },
		127	.n = { .min = 3, .max = 16 },
		128	.m = { .min = 96, .max = 140 },
		129	.m1 = { .min = 18, .max = 26 },
		130	.m2 = { .min = 6, .max = 16 },
		131	.p = { .min = 4, .max = 128 },
		132	.p1 = { .min = 1, .max = 6 },
		133	.p2 = { .dot_limit = 165000,
		134	.p2_slow = 14, .p2_fast = 7 },
		135	};
		136
		137	static const intel_limit_t intel_limits_i9xx_sdvo = {
		138	.dot = { .min = 20000, .max = 400000 },
		139	.vco = { .min = 1400000, .max = 2800000 },
		140	.n = { .min = 1, .max = 6 },
		141	.m = { .min = 70, .max = 120 },
3480	Serge	142	.m1 = { .min = 8, .max = 18 },
		143	.m2 = { .min = 3, .max = 7 },
2327	Serge	144	.p = { .min = 5, .max = 80 },
		145	.p1 = { .min = 1, .max = 8 },
		146	.p2 = { .dot_limit = 200000,
		147	.p2_slow = 10, .p2_fast = 5 },
		148	};
		149
		150	static const intel_limit_t intel_limits_i9xx_lvds = {
		151	.dot = { .min = 20000, .max = 400000 },
		152	.vco = { .min = 1400000, .max = 2800000 },
		153	.n = { .min = 1, .max = 6 },
		154	.m = { .min = 70, .max = 120 },
3480	Serge	155	.m1 = { .min = 8, .max = 18 },
		156	.m2 = { .min = 3, .max = 7 },
2327	Serge	157	.p = { .min = 7, .max = 98 },
		158	.p1 = { .min = 1, .max = 8 },
		159	.p2 = { .dot_limit = 112000,
		160	.p2_slow = 14, .p2_fast = 7 },
		161	};
		162
		163
		164	static const intel_limit_t intel_limits_g4x_sdvo = {
		165	.dot = { .min = 25000, .max = 270000 },
		166	.vco = { .min = 1750000, .max = 3500000},
		167	.n = { .min = 1, .max = 4 },
		168	.m = { .min = 104, .max = 138 },
		169	.m1 = { .min = 17, .max = 23 },
		170	.m2 = { .min = 5, .max = 11 },
		171	.p = { .min = 10, .max = 30 },
		172	.p1 = { .min = 1, .max = 3},
		173	.p2 = { .dot_limit = 270000,
		174	.p2_slow = 10,
		175	.p2_fast = 10
		176	},
		177	};
		178
		179	static const intel_limit_t intel_limits_g4x_hdmi = {
		180	.dot = { .min = 22000, .max = 400000 },
		181	.vco = { .min = 1750000, .max = 3500000},
		182	.n = { .min = 1, .max = 4 },
		183	.m = { .min = 104, .max = 138 },
		184	.m1 = { .min = 16, .max = 23 },
		185	.m2 = { .min = 5, .max = 11 },
		186	.p = { .min = 5, .max = 80 },
		187	.p1 = { .min = 1, .max = 8},
		188	.p2 = { .dot_limit = 165000,
		189	.p2_slow = 10, .p2_fast = 5 },
		190	};
		191
		192	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		193	.dot = { .min = 20000, .max = 115000 },
		194	.vco = { .min = 1750000, .max = 3500000 },
		195	.n = { .min = 1, .max = 3 },
		196	.m = { .min = 104, .max = 138 },
		197	.m1 = { .min = 17, .max = 23 },
		198	.m2 = { .min = 5, .max = 11 },
		199	.p = { .min = 28, .max = 112 },
		200	.p1 = { .min = 2, .max = 8 },
		201	.p2 = { .dot_limit = 0,
		202	.p2_slow = 14, .p2_fast = 14
		203	},
		204	};
		205
		206	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		207	.dot = { .min = 80000, .max = 224000 },
		208	.vco = { .min = 1750000, .max = 3500000 },
		209	.n = { .min = 1, .max = 3 },
		210	.m = { .min = 104, .max = 138 },
		211	.m1 = { .min = 17, .max = 23 },
		212	.m2 = { .min = 5, .max = 11 },
		213	.p = { .min = 14, .max = 42 },
		214	.p1 = { .min = 2, .max = 6 },
		215	.p2 = { .dot_limit = 0,
		216	.p2_slow = 7, .p2_fast = 7
		217	},
		218	};
		219
		220	static const intel_limit_t intel_limits_pineview_sdvo = {
		221	.dot = { .min = 20000, .max = 400000},
		222	.vco = { .min = 1700000, .max = 3500000 },
		223	/* Pineview's Ncounter is a ring counter */
		224	.n = { .min = 3, .max = 6 },
		225	.m = { .min = 2, .max = 256 },
		226	/* Pineview only has one combined m divider, which we treat as m2. */
		227	.m1 = { .min = 0, .max = 0 },
		228	.m2 = { .min = 0, .max = 254 },
		229	.p = { .min = 5, .max = 80 },
		230	.p1 = { .min = 1, .max = 8 },
		231	.p2 = { .dot_limit = 200000,
		232	.p2_slow = 10, .p2_fast = 5 },
		233	};
		234
		235	static const intel_limit_t intel_limits_pineview_lvds = {
		236	.dot = { .min = 20000, .max = 400000 },
		237	.vco = { .min = 1700000, .max = 3500000 },
		238	.n = { .min = 3, .max = 6 },
		239	.m = { .min = 2, .max = 256 },
		240	.m1 = { .min = 0, .max = 0 },
		241	.m2 = { .min = 0, .max = 254 },
		242	.p = { .min = 7, .max = 112 },
		243	.p1 = { .min = 1, .max = 8 },
		244	.p2 = { .dot_limit = 112000,
		245	.p2_slow = 14, .p2_fast = 14 },
		246	};
		247
		248	/* Ironlake / Sandybridge
		249	*
		250	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		251	* the range value for them is (actual_value - 2).
		252	*/
		253	static const intel_limit_t intel_limits_ironlake_dac = {
		254	.dot = { .min = 25000, .max = 350000 },
		255	.vco = { .min = 1760000, .max = 3510000 },
		256	.n = { .min = 1, .max = 5 },
		257	.m = { .min = 79, .max = 127 },
		258	.m1 = { .min = 12, .max = 22 },
		259	.m2 = { .min = 5, .max = 9 },
		260	.p = { .min = 5, .max = 80 },
		261	.p1 = { .min = 1, .max = 8 },
		262	.p2 = { .dot_limit = 225000,
		263	.p2_slow = 10, .p2_fast = 5 },
		264	};
		265
		266	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		267	.dot = { .min = 25000, .max = 350000 },
		268	.vco = { .min = 1760000, .max = 3510000 },
		269	.n = { .min = 1, .max = 3 },
		270	.m = { .min = 79, .max = 118 },
		271	.m1 = { .min = 12, .max = 22 },
		272	.m2 = { .min = 5, .max = 9 },
		273	.p = { .min = 28, .max = 112 },
		274	.p1 = { .min = 2, .max = 8 },
		275	.p2 = { .dot_limit = 225000,
		276	.p2_slow = 14, .p2_fast = 14 },
		277	};
		278
		279	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		280	.dot = { .min = 25000, .max = 350000 },
		281	.vco = { .min = 1760000, .max = 3510000 },
		282	.n = { .min = 1, .max = 3 },
		283	.m = { .min = 79, .max = 127 },
		284	.m1 = { .min = 12, .max = 22 },
		285	.m2 = { .min = 5, .max = 9 },
		286	.p = { .min = 14, .max = 56 },
		287	.p1 = { .min = 2, .max = 8 },
		288	.p2 = { .dot_limit = 225000,
		289	.p2_slow = 7, .p2_fast = 7 },
		290	};
		291
		292	/* LVDS 100mhz refclk limits. */
		293	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		294	.dot = { .min = 25000, .max = 350000 },
		295	.vco = { .min = 1760000, .max = 3510000 },
		296	.n = { .min = 1, .max = 2 },
		297	.m = { .min = 79, .max = 126 },
		298	.m1 = { .min = 12, .max = 22 },
		299	.m2 = { .min = 5, .max = 9 },
		300	.p = { .min = 28, .max = 112 },
2342	Serge	301	.p1 = { .min = 2, .max = 8 },
2327	Serge	302	.p2 = { .dot_limit = 225000,
		303	.p2_slow = 14, .p2_fast = 14 },
		304	};
		305
		306	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		307	.dot = { .min = 25000, .max = 350000 },
		308	.vco = { .min = 1760000, .max = 3510000 },
		309	.n = { .min = 1, .max = 3 },
		310	.m = { .min = 79, .max = 126 },
		311	.m1 = { .min = 12, .max = 22 },
		312	.m2 = { .min = 5, .max = 9 },
		313	.p = { .min = 14, .max = 42 },
2342	Serge	314	.p1 = { .min = 2, .max = 6 },
2327	Serge	315	.p2 = { .dot_limit = 225000,
		316	.p2_slow = 7, .p2_fast = 7 },
		317	};
		318
3031	serge	319	static const intel_limit_t intel_limits_vlv_dac = {
		320	.dot = { .min = 25000, .max = 270000 },
		321	.vco = { .min = 4000000, .max = 6000000 },
		322	.n = { .min = 1, .max = 7 },
		323	.m = { .min = 22, .max = 450 }, /* guess */
		324	.m1 = { .min = 2, .max = 3 },
		325	.m2 = { .min = 11, .max = 156 },
		326	.p = { .min = 10, .max = 30 },
4104	Serge	327	.p1 = { .min = 1, .max = 3 },
3031	serge	328	.p2 = { .dot_limit = 270000,
		329	.p2_slow = 2, .p2_fast = 20 },
		330	};
		331
		332	static const intel_limit_t intel_limits_vlv_hdmi = {
4104	Serge	333	.dot = { .min = 25000, .max = 270000 },
		334	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	335	.n = { .min = 1, .max = 7 },
		336	.m = { .min = 60, .max = 300 }, /* guess */
		337	.m1 = { .min = 2, .max = 3 },
		338	.m2 = { .min = 11, .max = 156 },
		339	.p = { .min = 10, .max = 30 },
		340	.p1 = { .min = 2, .max = 3 },
		341	.p2 = { .dot_limit = 270000,
		342	.p2_slow = 2, .p2_fast = 20 },
		343	};
		344
		345	static const intel_limit_t intel_limits_vlv_dp = {
3243	Serge	346	.dot = { .min = 25000, .max = 270000 },
		347	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	348	.n = { .min = 1, .max = 7 },
3243	Serge	349	.m = { .min = 22, .max = 450 },
3031	serge	350	.m1 = { .min = 2, .max = 3 },
		351	.m2 = { .min = 11, .max = 156 },
		352	.p = { .min = 10, .max = 30 },
4104	Serge	353	.p1 = { .min = 1, .max = 3 },
3031	serge	354	.p2 = { .dot_limit = 270000,
		355	.p2_slow = 2, .p2_fast = 20 },
		356	};
		357
2327	Serge	358	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		359	int refclk)
		360	{
		361	struct drm_device *dev = crtc->dev;
		362	const intel_limit_t *limit;
		363
		364	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	365	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	366	if (refclk == 100000)
		367	limit = &intel_limits_ironlake_dual_lvds_100m;
		368	else
		369	limit = &intel_limits_ironlake_dual_lvds;
		370	} else {
		371	if (refclk == 100000)
		372	limit = &intel_limits_ironlake_single_lvds_100m;
		373	else
		374	limit = &intel_limits_ironlake_single_lvds;
		375	}
4104	Serge	376	} else
2327	Serge	377	limit = &intel_limits_ironlake_dac;
		378
		379	return limit;
		380	}
		381
		382	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		383	{
		384	struct drm_device *dev = crtc->dev;
		385	const intel_limit_t *limit;
		386
		387	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	388	if (intel_is_dual_link_lvds(dev))
2327	Serge	389	limit = &intel_limits_g4x_dual_channel_lvds;
		390	else
		391	limit = &intel_limits_g4x_single_channel_lvds;
		392	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		393	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		394	limit = &intel_limits_g4x_hdmi;
		395	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		396	limit = &intel_limits_g4x_sdvo;
		397	} else /* The option is for other outputs */
		398	limit = &intel_limits_i9xx_sdvo;
		399
		400	return limit;
		401	}
		402
		403	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		404	{
		405	struct drm_device *dev = crtc->dev;
		406	const intel_limit_t *limit;
		407
		408	if (HAS_PCH_SPLIT(dev))
		409	limit = intel_ironlake_limit(crtc, refclk);
		410	else if (IS_G4X(dev)) {
		411	limit = intel_g4x_limit(crtc);
		412	} else if (IS_PINEVIEW(dev)) {
		413	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		414	limit = &intel_limits_pineview_lvds;
		415	else
		416	limit = &intel_limits_pineview_sdvo;
3031	serge	417	} else if (IS_VALLEYVIEW(dev)) {
		418	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		419	limit = &intel_limits_vlv_dac;
		420	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		421	limit = &intel_limits_vlv_hdmi;
		422	else
		423	limit = &intel_limits_vlv_dp;
2327	Serge	424	} else if (!IS_GEN2(dev)) {
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		426	limit = &intel_limits_i9xx_lvds;
		427	else
		428	limit = &intel_limits_i9xx_sdvo;
		429	} else {
		430	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		431	limit = &intel_limits_i8xx_lvds;
4104	Serge	432	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
		433	limit = &intel_limits_i8xx_dvo;
2327	Serge	434	else
4104	Serge	435	limit = &intel_limits_i8xx_dac;
2327	Serge	436	}
		437	return limit;
		438	}
		439
		440	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		441	static void pineview_clock(int refclk, intel_clock_t *clock)
		442	{
		443	clock->m = clock->m2 + 2;
		444	clock->p = clock->p1 * clock->p2;
		445	clock->vco = refclk * clock->m / clock->n;
		446	clock->dot = clock->vco / clock->p;
		447	}
		448
4104	Serge	449	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	450	{
4104	Serge	451	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		452	}
		453
		454	static void i9xx_clock(int refclk, intel_clock_t *clock)
		455	{
		456	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	457	clock->p = clock->p1 * clock->p2;
		458	clock->vco = refclk * clock->m / (clock->n + 2);
		459	clock->dot = clock->vco / clock->p;
		460	}
		461
		462	/**
		463	* Returns whether any output on the specified pipe is of the specified type
		464	*/
		465	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		466	{
		467	struct drm_device *dev = crtc->dev;
		468	struct intel_encoder *encoder;
		469
3031	serge	470	for_each_encoder_on_crtc(dev, crtc, encoder)
		471	if (encoder->type == type)
2327	Serge	472	return true;
		473
		474	return false;
		475	}
		476
		477	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		478	/**
		479	* Returns whether the given set of divisors are valid for a given refclk with
		480	* the given connectors.
		481	*/
		482
		483	static bool intel_PLL_is_valid(struct drm_device *dev,
		484	const intel_limit_t *limit,
		485	const intel_clock_t *clock)
		486	{
		487	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	488	INTELPllInvalid("p1 out of range\n");
2327	Serge	489	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	490	INTELPllInvalid("p out of range\n");
2327	Serge	491	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	492	INTELPllInvalid("m2 out of range\n");
2327	Serge	493	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	494	INTELPllInvalid("m1 out of range\n");
2327	Serge	495	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	496	INTELPllInvalid("m1 <= m2\n");
2327	Serge	497	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	498	INTELPllInvalid("m out of range\n");
2327	Serge	499	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	500	INTELPllInvalid("n out of range\n");
2327	Serge	501	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	502	INTELPllInvalid("vco out of range\n");
2327	Serge	503	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		504	* connector, etc., rather than just a single range.
		505	*/
		506	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	507	INTELPllInvalid("dot out of range\n");
2327	Serge	508
		509	return true;
		510	}
		511
		512	static bool
4104	Serge	513	i9xx_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	514	int target, int refclk, intel_clock_t *match_clock,
		515	intel_clock_t *best_clock)
2327	Serge	516	{
		517	struct drm_device *dev = crtc->dev;
		518	intel_clock_t clock;
		519	int err = target;
		520
3480	Serge	521	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	522	/*
3480	Serge	523	* For LVDS just rely on its current settings for dual-channel.
		524	* We haven't figured out how to reliably set up different
		525	* single/dual channel state, if we even can.
2327	Serge	526	*/
3480	Serge	527	if (intel_is_dual_link_lvds(dev))
2327	Serge	528	clock.p2 = limit->p2.p2_fast;
		529	else
		530	clock.p2 = limit->p2.p2_slow;
		531	} else {
		532	if (target < limit->p2.dot_limit)
		533	clock.p2 = limit->p2.p2_slow;
		534	else
		535	clock.p2 = limit->p2.p2_fast;
		536	}
		537
2342	Serge	538	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	539
		540	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		541	clock.m1++) {
		542	for (clock.m2 = limit->m2.min;
		543	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	544	if (clock.m2 >= clock.m1)
2327	Serge	545	break;
		546	for (clock.n = limit->n.min;
		547	clock.n <= limit->n.max; clock.n++) {
		548	for (clock.p1 = limit->p1.min;
		549	clock.p1 <= limit->p1.max; clock.p1++) {
		550	int this_err;
		551
4104	Serge	552	i9xx_clock(refclk, &clock);
2327	Serge	553	if (!intel_PLL_is_valid(dev, limit,
		554	&clock))
		555	continue;
3031	serge	556	if (match_clock &&
		557	clock.p != match_clock->p)
		558	continue;
2327	Serge	559
		560	this_err = abs(clock.dot - target);
		561	if (this_err < err) {
		562	*best_clock = clock;
		563	err = this_err;
		564	}
		565	}
		566	}
		567	}
		568	}
		569
		570	return (err != target);
		571	}
		572
		573	static bool
4104	Serge	574	pnv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		575	int target, int refclk, intel_clock_t *match_clock,
		576	intel_clock_t *best_clock)
		577	{
		578	struct drm_device *dev = crtc->dev;
		579	intel_clock_t clock;
		580	int err = target;
		581
		582	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		583	/*
		584	* For LVDS just rely on its current settings for dual-channel.
		585	* We haven't figured out how to reliably set up different
		586	* single/dual channel state, if we even can.
		587	*/
		588	if (intel_is_dual_link_lvds(dev))
		589	clock.p2 = limit->p2.p2_fast;
		590	else
		591	clock.p2 = limit->p2.p2_slow;
		592	} else {
		593	if (target < limit->p2.dot_limit)
		594	clock.p2 = limit->p2.p2_slow;
		595	else
		596	clock.p2 = limit->p2.p2_fast;
		597	}
		598
		599	memset(best_clock, 0, sizeof(*best_clock));
		600
		601	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		602	clock.m1++) {
		603	for (clock.m2 = limit->m2.min;
		604	clock.m2 <= limit->m2.max; clock.m2++) {
		605	for (clock.n = limit->n.min;
		606	clock.n <= limit->n.max; clock.n++) {
		607	for (clock.p1 = limit->p1.min;
		608	clock.p1 <= limit->p1.max; clock.p1++) {
		609	int this_err;
		610
		611	pineview_clock(refclk, &clock);
		612	if (!intel_PLL_is_valid(dev, limit,
		613	&clock))
		614	continue;
		615	if (match_clock &&
		616	clock.p != match_clock->p)
		617	continue;
		618
		619	this_err = abs(clock.dot - target);
		620	if (this_err < err) {
		621	*best_clock = clock;
		622	err = this_err;
		623	}
		624	}
		625	}
		626	}
		627	}
		628
		629	return (err != target);
		630	}
		631
		632	static bool
		633	g4x_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	634	int target, int refclk, intel_clock_t *match_clock,
		635	intel_clock_t *best_clock)
2327	Serge	636	{
		637	struct drm_device *dev = crtc->dev;
		638	intel_clock_t clock;
		639	int max_n;
		640	bool found;
		641	/* approximately equals target * 0.00585 */
		642	int err_most = (target >> 8) + (target >> 9);
		643	found = false;
		644
		645	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	646	if (intel_is_dual_link_lvds(dev))
2327	Serge	647	clock.p2 = limit->p2.p2_fast;
		648	else
		649	clock.p2 = limit->p2.p2_slow;
		650	} else {
		651	if (target < limit->p2.dot_limit)
		652	clock.p2 = limit->p2.p2_slow;
		653	else
		654	clock.p2 = limit->p2.p2_fast;
		655	}
		656
		657	memset(best_clock, 0, sizeof(*best_clock));
		658	max_n = limit->n.max;
		659	/* based on hardware requirement, prefer smaller n to precision */
		660	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		661	/* based on hardware requirement, prefere larger m1,m2 */
		662	for (clock.m1 = limit->m1.max;
		663	clock.m1 >= limit->m1.min; clock.m1--) {
		664	for (clock.m2 = limit->m2.max;
		665	clock.m2 >= limit->m2.min; clock.m2--) {
		666	for (clock.p1 = limit->p1.max;
		667	clock.p1 >= limit->p1.min; clock.p1--) {
		668	int this_err;
		669
4104	Serge	670	i9xx_clock(refclk, &clock);
2327	Serge	671	if (!intel_PLL_is_valid(dev, limit,
		672	&clock))
		673	continue;
		674
		675	this_err = abs(clock.dot - target);
		676	if (this_err < err_most) {
		677	*best_clock = clock;
		678	err_most = this_err;
		679	max_n = clock.n;
		680	found = true;
		681	}
		682	}
		683	}
		684	}
		685	}
		686	return found;
		687	}
		688
		689	static bool
4104	Serge	690	vlv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	691	int target, int refclk, intel_clock_t *match_clock,
		692	intel_clock_t *best_clock)
		693	{
		694	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		695	u32 m, n, fastclk;
4104	Serge	696	u32 updrate, minupdate, p;
3031	serge	697	unsigned long bestppm, ppm, absppm;
		698	int dotclk, flag;
2327	Serge	699
3031	serge	700	flag = 0;
		701	dotclk = target * 1000;
		702	bestppm = 1000000;
		703	ppm = absppm = 0;
		704	fastclk = dotclk / (2*100);
		705	updrate = 0;
		706	minupdate = 19200;
		707	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		708	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		709
		710	/* based on hardware requirement, prefer smaller n to precision */
		711	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		712	updrate = refclk / n;
		713	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		714	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		715	if (p2 > 10)
		716	p2 = p2 - 1;
		717	p = p1 * p2;
		718	/* based on hardware requirement, prefer bigger m1,m2 values */
		719	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		720	m2 = (((2(fastclk p * n / m1 )) +
		721	refclk) / (2*refclk));
		722	m = m1 * m2;
		723	vco = updrate * m;
		724	if (vco >= limit->vco.min && vco < limit->vco.max) {
		725	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		726	absppm = (ppm > 0) ? ppm : (-ppm);
		727	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		728	bestppm = 0;
		729	flag = 1;
		730	}
		731	if (absppm < bestppm - 10) {
		732	bestppm = absppm;
		733	flag = 1;
		734	}
		735	if (flag) {
		736	bestn = n;
		737	bestm1 = m1;
		738	bestm2 = m2;
		739	bestp1 = p1;
		740	bestp2 = p2;
		741	flag = 0;
		742	}
		743	}
		744	}
		745	}
		746	}
		747	}
		748	best_clock->n = bestn;
		749	best_clock->m1 = bestm1;
		750	best_clock->m2 = bestm2;
		751	best_clock->p1 = bestp1;
		752	best_clock->p2 = bestp2;
		753
		754	return true;
		755	}
		756
3243	Serge	757	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		758	enum pipe pipe)
		759	{
		760	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		762
3746	Serge	763	return intel_crtc->config.cpu_transcoder;
3243	Serge	764	}
		765
3031	serge	766	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		767	{
		768	struct drm_i915_private *dev_priv = dev->dev_private;
		769	u32 frame, frame_reg = PIPEFRAME(pipe);
		770
		771	frame = I915_READ(frame_reg);
		772
		773	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		774	DRM_DEBUG_KMS("vblank wait timed out\n");
		775	}
		776
2327	Serge	777	/**
		778	* intel_wait_for_vblank - wait for vblank on a given pipe
		779	* @dev: drm device
		780	* @pipe: pipe to wait for
		781	*
		782	* Wait for vblank to occur on a given pipe. Needed for various bits of
		783	* mode setting code.
		784	*/
		785	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		786	{
		787	struct drm_i915_private *dev_priv = dev->dev_private;
		788	int pipestat_reg = PIPESTAT(pipe);
		789
3031	serge	790	if (INTEL_INFO(dev)->gen >= 5) {
		791	ironlake_wait_for_vblank(dev, pipe);
		792	return;
		793	}
		794
2327	Serge	795	/* Clear existing vblank status. Note this will clear any other
		796	* sticky status fields as well.
		797	*
		798	* This races with i915_driver_irq_handler() with the result
		799	* that either function could miss a vblank event. Here it is not
		800	* fatal, as we will either wait upon the next vblank interrupt or
		801	* timeout. Generally speaking intel_wait_for_vblank() is only
		802	* called during modeset at which time the GPU should be idle and
		803	* should not be performing page flips and thus not waiting on
		804	* vblanks...
		805	* Currently, the result of us stealing a vblank from the irq
		806	* handler is that a single frame will be skipped during swapbuffers.
		807	*/
		808	I915_WRITE(pipestat_reg,
		809	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		810
		811	/* Wait for vblank interrupt bit to set */
		812	if (wait_for(I915_READ(pipestat_reg) &
		813	PIPE_VBLANK_INTERRUPT_STATUS,
		814	50))
		815	DRM_DEBUG_KMS("vblank wait timed out\n");
		816	}
		817
		818	/*
		819	* intel_wait_for_pipe_off - wait for pipe to turn off
		820	* @dev: drm device
		821	* @pipe: pipe to wait for
		822	*
		823	* After disabling a pipe, we can't wait for vblank in the usual way,
		824	* spinning on the vblank interrupt status bit, since we won't actually
		825	* see an interrupt when the pipe is disabled.
		826	*
		827	* On Gen4 and above:
		828	* wait for the pipe register state bit to turn off
		829	*
		830	* Otherwise:
		831	* wait for the display line value to settle (it usually
		832	* ends up stopping at the start of the next frame).
		833	*
		834	*/
		835	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		836	{
		837	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	838	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		839	pipe);
2327	Serge	840
		841	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	842	int reg = PIPECONF(cpu_transcoder);
2327	Serge	843
		844	/* Wait for the Pipe State to go off */
		845	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		846	100))
3031	serge	847	WARN(1, "pipe_off wait timed out\n");
2327	Serge	848	} else {
3031	serge	849	u32 last_line, line_mask;
2327	Serge	850	int reg = PIPEDSL(pipe);
4104	Serge	851	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	852
3031	serge	853	if (IS_GEN2(dev))
		854	line_mask = DSL_LINEMASK_GEN2;
		855	else
		856	line_mask = DSL_LINEMASK_GEN3;
		857
2327	Serge	858	/* Wait for the display line to settle */
		859	do {
3031	serge	860	last_line = I915_READ(reg) & line_mask;
2327	Serge	861	mdelay(5);
3031	serge	862	} while (((I915_READ(reg) & line_mask) != last_line) &&
		863	time_after(timeout, GetTimerTicks()));
		864	if (time_after(GetTimerTicks(), timeout))
		865	WARN(1, "pipe_off wait timed out\n");
2327	Serge	866	}
		867	}
		868
3480	Serge	869	/*
		870	* ibx_digital_port_connected - is the specified port connected?
		871	* @dev_priv: i915 private structure
		872	* @port: the port to test
		873	*
		874	* Returns true if @port is connected, false otherwise.
		875	*/
		876	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		877	struct intel_digital_port *port)
		878	{
		879	u32 bit;
		880
		881	if (HAS_PCH_IBX(dev_priv->dev)) {
		882	switch(port->port) {
		883	case PORT_B:
		884	bit = SDE_PORTB_HOTPLUG;
		885	break;
		886	case PORT_C:
		887	bit = SDE_PORTC_HOTPLUG;
		888	break;
		889	case PORT_D:
		890	bit = SDE_PORTD_HOTPLUG;
		891	break;
		892	default:
		893	return true;
		894	}
		895	} else {
		896	switch(port->port) {
		897	case PORT_B:
		898	bit = SDE_PORTB_HOTPLUG_CPT;
		899	break;
		900	case PORT_C:
		901	bit = SDE_PORTC_HOTPLUG_CPT;
		902	break;
		903	case PORT_D:
		904	bit = SDE_PORTD_HOTPLUG_CPT;
		905	break;
		906	default:
		907	return true;
		908	}
		909	}
		910
		911	return I915_READ(SDEISR) & bit;
		912	}
		913
2327	Serge	914	static const char *state_string(bool enabled)
		915	{
		916	return enabled ? "on" : "off";
		917	}
		918
		919	/* Only for pre-ILK configs */
4104	Serge	920	void assert_pll(struct drm_i915_private *dev_priv,
2327	Serge	921	enum pipe pipe, bool state)
		922	{
		923	int reg;
		924	u32 val;
		925	bool cur_state;
		926
		927	reg = DPLL(pipe);
		928	val = I915_READ(reg);
		929	cur_state = !!(val & DPLL_VCO_ENABLE);
		930	WARN(cur_state != state,
		931	"PLL state assertion failure (expected %s, current %s)\n",
		932	state_string(state), state_string(cur_state));
		933	}
		934
4104	Serge	935	struct intel_shared_dpll *
		936	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		937	{
		938	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		939
		940	if (crtc->config.shared_dpll < 0)
		941	return NULL;
		942
		943	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
		944	}
		945
2327	Serge	946	/* For ILK+ */
4104	Serge	947	void assert_shared_dpll(struct drm_i915_private *dev_priv,
		948	struct intel_shared_dpll *pll,
3031	serge	949	bool state)
2327	Serge	950	{
		951	bool cur_state;
4104	Serge	952	struct intel_dpll_hw_state hw_state;
2327	Serge	953
3031	serge	954	if (HAS_PCH_LPT(dev_priv->dev)) {
		955	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		956	return;
		957	}
2342	Serge	958
3031	serge	959	if (WARN (!pll,
4104	Serge	960	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	961	return;
2342	Serge	962
4104	Serge	963	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
3031	serge	964	WARN(cur_state != state,
4104	Serge	965	"%s assertion failure (expected %s, current %s)\n",
		966	pll->name, state_string(state), state_string(cur_state));
2327	Serge	967	}
		968
		969	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		970	enum pipe pipe, bool state)
		971	{
		972	int reg;
		973	u32 val;
		974	bool cur_state;
3243	Serge	975	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		976	pipe);
2327	Serge	977
3480	Serge	978	if (HAS_DDI(dev_priv->dev)) {
		979	/* DDI does not have a specific FDI_TX register */
3243	Serge	980	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	981	val = I915_READ(reg);
3243	Serge	982	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	983	} else {
2327	Serge	984	reg = FDI_TX_CTL(pipe);
		985	val = I915_READ(reg);
		986	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	987	}
2327	Serge	988	WARN(cur_state != state,
		989	"FDI TX state assertion failure (expected %s, current %s)\n",
		990	state_string(state), state_string(cur_state));
		991	}
		992	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		993	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		994
		995	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		996	enum pipe pipe, bool state)
		997	{
		998	int reg;
		999	u32 val;
		1000	bool cur_state;
		1001
		1002	reg = FDI_RX_CTL(pipe);
		1003	val = I915_READ(reg);
		1004	cur_state = !!(val & FDI_RX_ENABLE);
		1005	WARN(cur_state != state,
		1006	"FDI RX state assertion failure (expected %s, current %s)\n",
		1007	state_string(state), state_string(cur_state));
		1008	}
		1009	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1010	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1011
		1012	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1013	enum pipe pipe)
		1014	{
		1015	int reg;
		1016	u32 val;
		1017
		1018	/* ILK FDI PLL is always enabled */
		1019	if (dev_priv->info->gen == 5)
		1020	return;
		1021
3031	serge	1022	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1023	if (HAS_DDI(dev_priv->dev))
3031	serge	1024	return;
		1025
2327	Serge	1026	reg = FDI_TX_CTL(pipe);
		1027	val = I915_READ(reg);
		1028	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1029	}
		1030
4104	Serge	1031	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1032	enum pipe pipe, bool state)
2327	Serge	1033	{
		1034	int reg;
		1035	u32 val;
4104	Serge	1036	bool cur_state;
2327	Serge	1037
		1038	reg = FDI_RX_CTL(pipe);
		1039	val = I915_READ(reg);
4104	Serge	1040	cur_state = !!(val & FDI_RX_PLL_ENABLE);
		1041	WARN(cur_state != state,
		1042	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1043	state_string(state), state_string(cur_state));
2327	Serge	1044	}
		1045
		1046	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1047	enum pipe pipe)
		1048	{
		1049	int pp_reg, lvds_reg;
		1050	u32 val;
		1051	enum pipe panel_pipe = PIPE_A;
		1052	bool locked = true;
		1053
		1054	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1055	pp_reg = PCH_PP_CONTROL;
		1056	lvds_reg = PCH_LVDS;
		1057	} else {
		1058	pp_reg = PP_CONTROL;
		1059	lvds_reg = LVDS;
		1060	}
		1061
		1062	val = I915_READ(pp_reg);
		1063	if (!(val & PANEL_POWER_ON) \|\|
		1064	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1065	locked = false;
		1066
		1067	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1068	panel_pipe = PIPE_B;
		1069
		1070	WARN(panel_pipe == pipe && locked,
		1071	"panel assertion failure, pipe %c regs locked\n",
		1072	pipe_name(pipe));
		1073	}
		1074
2342	Serge	1075	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1076	enum pipe pipe, bool state)
		1077	{
		1078	int reg;
		1079	u32 val;
		1080	bool cur_state;
3243	Serge	1081	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1082	pipe);
2327	Serge	1083
3031	serge	1084	/* if we need the pipe A quirk it must be always on */
		1085	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1086	state = true;
		1087
4104	Serge	1088	if (!intel_display_power_enabled(dev_priv->dev,
		1089	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1090	cur_state = false;
		1091	} else {
3243	Serge	1092	reg = PIPECONF(cpu_transcoder);
2327	Serge	1093	val = I915_READ(reg);
		1094	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1095	}
		1096
2327	Serge	1097	WARN(cur_state != state,
		1098	"pipe %c assertion failure (expected %s, current %s)\n",
		1099	pipe_name(pipe), state_string(state), state_string(cur_state));
		1100	}
		1101
3031	serge	1102	static void assert_plane(struct drm_i915_private *dev_priv,
		1103	enum plane plane, bool state)
2327	Serge	1104	{
		1105	int reg;
		1106	u32 val;
3031	serge	1107	bool cur_state;
2327	Serge	1108
		1109	reg = DSPCNTR(plane);
		1110	val = I915_READ(reg);
3031	serge	1111	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1112	WARN(cur_state != state,
		1113	"plane %c assertion failure (expected %s, current %s)\n",
		1114	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1115	}
		1116
3031	serge	1117	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1118	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1119
2327	Serge	1120	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1121	enum pipe pipe)
		1122	{
4104	Serge	1123	struct drm_device *dev = dev_priv->dev;
2327	Serge	1124	int reg, i;
		1125	u32 val;
		1126	int cur_pipe;
		1127
4104	Serge	1128	/* Primary planes are fixed to pipes on gen4+ */
		1129	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	1130	reg = DSPCNTR(pipe);
		1131	val = I915_READ(reg);
		1132	WARN((val & DISPLAY_PLANE_ENABLE),
		1133	"plane %c assertion failure, should be disabled but not\n",
		1134	plane_name(pipe));
2327	Serge	1135	return;
3031	serge	1136	}
2327	Serge	1137
		1138	/* Need to check both planes against the pipe */
4104	Serge	1139	for_each_pipe(i) {
2327	Serge	1140	reg = DSPCNTR(i);
		1141	val = I915_READ(reg);
		1142	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1143	DISPPLANE_SEL_PIPE_SHIFT;
		1144	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1145	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1146	plane_name(i), pipe_name(pipe));
		1147	}
		1148	}
		1149
3746	Serge	1150	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1151	enum pipe pipe)
		1152	{
4104	Serge	1153	struct drm_device *dev = dev_priv->dev;
3746	Serge	1154	int reg, i;
		1155	u32 val;
		1156
4104	Serge	1157	if (IS_VALLEYVIEW(dev)) {
3746	Serge	1158	for (i = 0; i < dev_priv->num_plane; i++) {
		1159	reg = SPCNTR(pipe, i);
		1160	val = I915_READ(reg);
		1161	WARN((val & SP_ENABLE),
4104	Serge	1162	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1163	sprite_name(pipe, i), pipe_name(pipe));
		1164	}
		1165	} else if (INTEL_INFO(dev)->gen >= 7) {
		1166	reg = SPRCTL(pipe);
		1167	val = I915_READ(reg);
		1168	WARN((val & SPRITE_ENABLE),
		1169	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1170	plane_name(pipe), pipe_name(pipe));
		1171	} else if (INTEL_INFO(dev)->gen >= 5) {
		1172	reg = DVSCNTR(pipe);
		1173	val = I915_READ(reg);
		1174	WARN((val & DVS_ENABLE),
		1175	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1176	plane_name(pipe), pipe_name(pipe));
3746	Serge	1177	}
		1178	}
		1179
2327	Serge	1180	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1181	{
		1182	u32 val;
		1183	bool enabled;
		1184
3031	serge	1185	if (HAS_PCH_LPT(dev_priv->dev)) {
		1186	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1187	return;
		1188	}
		1189
2327	Serge	1190	val = I915_READ(PCH_DREF_CONTROL);
		1191	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1192	DREF_SUPERSPREAD_SOURCE_MASK));
		1193	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1194	}
		1195
4104	Serge	1196	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
2327	Serge	1197	enum pipe pipe)
		1198	{
		1199	int reg;
		1200	u32 val;
		1201	bool enabled;
		1202
4104	Serge	1203	reg = PCH_TRANSCONF(pipe);
2327	Serge	1204	val = I915_READ(reg);
		1205	enabled = !!(val & TRANS_ENABLE);
		1206	WARN(enabled,
		1207	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1208	pipe_name(pipe));
		1209	}
		1210
		1211	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1212	enum pipe pipe, u32 port_sel, u32 val)
		1213	{
		1214	if ((val & DP_PORT_EN) == 0)
		1215	return false;
		1216
		1217	if (HAS_PCH_CPT(dev_priv->dev)) {
		1218	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1219	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1220	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1221	return false;
		1222	} else {
		1223	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1224	return false;
		1225	}
		1226	return true;
		1227	}
		1228
		1229	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1230	enum pipe pipe, u32 val)
		1231	{
3746	Serge	1232	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1233	return false;
		1234
		1235	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1236	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1237	return false;
		1238	} else {
3746	Serge	1239	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1240	return false;
		1241	}
		1242	return true;
		1243	}
		1244
		1245	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1246	enum pipe pipe, u32 val)
		1247	{
		1248	if ((val & LVDS_PORT_EN) == 0)
		1249	return false;
		1250
		1251	if (HAS_PCH_CPT(dev_priv->dev)) {
		1252	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1253	return false;
		1254	} else {
		1255	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1256	return false;
		1257	}
		1258	return true;
		1259	}
		1260
		1261	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1262	enum pipe pipe, u32 val)
		1263	{
		1264	if ((val & ADPA_DAC_ENABLE) == 0)
		1265	return false;
		1266	if (HAS_PCH_CPT(dev_priv->dev)) {
		1267	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1268	return false;
		1269	} else {
		1270	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1271	return false;
		1272	}
		1273	return true;
		1274	}
		1275
		1276	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1277	enum pipe pipe, int reg, u32 port_sel)
		1278	{
		1279	u32 val = I915_READ(reg);
		1280	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1281	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1282	reg, pipe_name(pipe));
3031	serge	1283
		1284	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1285	&& (val & DP_PIPEB_SELECT),
		1286	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1287	}
		1288
		1289	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1290	enum pipe pipe, int reg)
		1291	{
		1292	u32 val = I915_READ(reg);
3031	serge	1293	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1294	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1295	reg, pipe_name(pipe));
3031	serge	1296
3746	Serge	1297	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1298	&& (val & SDVO_PIPE_B_SELECT),
		1299	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1300	}
		1301
		1302	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1303	enum pipe pipe)
		1304	{
		1305	int reg;
		1306	u32 val;
		1307
		1308	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1309	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1310	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1311
		1312	reg = PCH_ADPA;
		1313	val = I915_READ(reg);
3031	serge	1314	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1315	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1316	pipe_name(pipe));
		1317
		1318	reg = PCH_LVDS;
		1319	val = I915_READ(reg);
3031	serge	1320	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1321	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1322	pipe_name(pipe));
		1323
3746	Serge	1324	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1325	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1326	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1327	}
		1328
4104	Serge	1329	static void vlv_enable_pll(struct intel_crtc *crtc)
2327	Serge	1330	{
4104	Serge	1331	struct drm_device *dev = crtc->base.dev;
		1332	struct drm_i915_private *dev_priv = dev->dev_private;
		1333	int reg = DPLL(crtc->pipe);
		1334	u32 dpll = crtc->config.dpll_hw_state.dpll;
2327	Serge	1335
4104	Serge	1336	assert_pipe_disabled(dev_priv, crtc->pipe);
		1337
2327	Serge	1338	/* No really, not for ILK+ */
4104	Serge	1339	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1340
		1341	/* PLL is protected by panel, make sure we can write it */
		1342	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
4104	Serge	1343	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1344
4104	Serge	1345	I915_WRITE(reg, dpll);
		1346	POSTING_READ(reg);
		1347	udelay(150);
2327	Serge	1348
4104	Serge	1349	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1350	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1351
		1352	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
		1353	POSTING_READ(DPLL_MD(crtc->pipe));
		1354
		1355	/* We do this three times for luck */
		1356	I915_WRITE(reg, dpll);
		1357	POSTING_READ(reg);
		1358	udelay(150); /* wait for warmup */
		1359	I915_WRITE(reg, dpll);
		1360	POSTING_READ(reg);
		1361	udelay(150); /* wait for warmup */
		1362	I915_WRITE(reg, dpll);
		1363	POSTING_READ(reg);
		1364	udelay(150); /* wait for warmup */
		1365	}
		1366
		1367	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1368	{
		1369	struct drm_device *dev = crtc->base.dev;
		1370	struct drm_i915_private *dev_priv = dev->dev_private;
		1371	int reg = DPLL(crtc->pipe);
		1372	u32 dpll = crtc->config.dpll_hw_state.dpll;
		1373
		1374	assert_pipe_disabled(dev_priv, crtc->pipe);
		1375
		1376	/* No really, not for ILK+ */
		1377	BUG_ON(dev_priv->info->gen >= 5);
		1378
		1379	/* PLL is protected by panel, make sure we can write it */
		1380	if (IS_MOBILE(dev) && !IS_I830(dev))
		1381	assert_panel_unlocked(dev_priv, crtc->pipe);
		1382
		1383	I915_WRITE(reg, dpll);
		1384
		1385	/* Wait for the clocks to stabilize. */
		1386	POSTING_READ(reg);
		1387	udelay(150);
		1388
		1389	if (INTEL_INFO(dev)->gen >= 4) {
		1390	I915_WRITE(DPLL_MD(crtc->pipe),
		1391	crtc->config.dpll_hw_state.dpll_md);
		1392	} else {
		1393	/* The pixel multiplier can only be updated once the
		1394	* DPLL is enabled and the clocks are stable.
		1395	*
		1396	* So write it again.
		1397	*/
		1398	I915_WRITE(reg, dpll);
		1399	}
		1400
2327	Serge	1401	/* We do this three times for luck */
4104	Serge	1402	I915_WRITE(reg, dpll);
2327	Serge	1403	POSTING_READ(reg);
		1404	udelay(150); /* wait for warmup */
4104	Serge	1405	I915_WRITE(reg, dpll);
2327	Serge	1406	POSTING_READ(reg);
		1407	udelay(150); /* wait for warmup */
4104	Serge	1408	I915_WRITE(reg, dpll);
2327	Serge	1409	POSTING_READ(reg);
		1410	udelay(150); /* wait for warmup */
		1411	}
		1412
		1413	/**
4104	Serge	1414	* i9xx_disable_pll - disable a PLL
2327	Serge	1415	* @dev_priv: i915 private structure
		1416	* @pipe: pipe PLL to disable
		1417	*
		1418	* Disable the PLL for @pipe, making sure the pipe is off first.
		1419	*
		1420	* Note! This is for pre-ILK only.
		1421	*/
4104	Serge	1422	static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2327	Serge	1423	{
		1424	/* Don't disable pipe A or pipe A PLLs if needed */
		1425	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1426	return;
		1427
		1428	/* Make sure the pipe isn't still relying on us */
		1429	assert_pipe_disabled(dev_priv, pipe);
		1430
4104	Serge	1431	I915_WRITE(DPLL(pipe), 0);
		1432	POSTING_READ(DPLL(pipe));
2327	Serge	1433	}
		1434
4539	Serge	1435	static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1436	{
		1437	u32 val = 0;
		1438
		1439	/* Make sure the pipe isn't still relying on us */
		1440	assert_pipe_disabled(dev_priv, pipe);
		1441
		1442	/* Leave integrated clock source enabled */
		1443	if (pipe == PIPE_B)
		1444	val = DPLL_INTEGRATED_CRI_CLK_VLV;
		1445	I915_WRITE(DPLL(pipe), val);
		1446	POSTING_READ(DPLL(pipe));
		1447	}
		1448
4104	Serge	1449	void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
3031	serge	1450	{
4104	Serge	1451	u32 port_mask;
3031	serge	1452
4104	Serge	1453	if (!port)
		1454	port_mask = DPLL_PORTB_READY_MASK;
3243	Serge	1455	else
4104	Serge	1456	port_mask = DPLL_PORTC_READY_MASK;
3243	Serge	1457
4104	Serge	1458	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		1459	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		1460	'B' + port, I915_READ(DPLL(0)));
3031	serge	1461	}
		1462
2327	Serge	1463	/**
4104	Serge	1464	* ironlake_enable_shared_dpll - enable PCH PLL
2327	Serge	1465	* @dev_priv: i915 private structure
		1466	* @pipe: pipe PLL to enable
		1467	*
		1468	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1469	* drives the transcoder clock.
		1470	*/
4104	Serge	1471	static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1472	{
4104	Serge	1473	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1474	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1475
3031	serge	1476	/* PCH PLLs only available on ILK, SNB and IVB */
		1477	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1478	if (WARN_ON(pll == NULL))
2342	Serge	1479	return;
		1480
3031	serge	1481	if (WARN_ON(pll->refcount == 0))
		1482	return;
2327	Serge	1483
4104	Serge	1484	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		1485	pll->name, pll->active, pll->on,
		1486	crtc->base.base.id);
3031	serge	1487
4104	Serge	1488	if (pll->active++) {
		1489	WARN_ON(!pll->on);
		1490	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1491	return;
		1492	}
4104	Serge	1493	WARN_ON(pll->on);
3031	serge	1494
4104	Serge	1495	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1496	pll->enable(dev_priv, pll);
3031	serge	1497	pll->on = true;
2327	Serge	1498	}
		1499
4104	Serge	1500	static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1501	{
4104	Serge	1502	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1503	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1504
		1505	/* PCH only available on ILK+ */
		1506	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1507	if (WARN_ON(pll == NULL))
3031	serge	1508	return;
2327	Serge	1509
3031	serge	1510	if (WARN_ON(pll->refcount == 0))
		1511	return;
2327	Serge	1512
4104	Serge	1513	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1514	pll->name, pll->active, pll->on,
		1515	crtc->base.base.id);
2342	Serge	1516
3031	serge	1517	if (WARN_ON(pll->active == 0)) {
4104	Serge	1518	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1519	return;
		1520	}
2342	Serge	1521
4104	Serge	1522	assert_shared_dpll_enabled(dev_priv, pll);
		1523	WARN_ON(!pll->on);
		1524	if (--pll->active)
2342	Serge	1525	return;
		1526
4104	Serge	1527	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1528	pll->disable(dev_priv, pll);
3031	serge	1529	pll->on = false;
2327	Serge	1530	}
		1531
3243	Serge	1532	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1533	enum pipe pipe)
		1534	{
3243	Serge	1535	struct drm_device *dev = dev_priv->dev;
3031	serge	1536	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1537	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1538	uint32_t reg, val, pipeconf_val;
2327	Serge	1539
		1540	/* PCH only available on ILK+ */
		1541	BUG_ON(dev_priv->info->gen < 5);
		1542
		1543	/* Make sure PCH DPLL is enabled */
4104	Serge	1544	assert_shared_dpll_enabled(dev_priv,
		1545	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1546
		1547	/* FDI must be feeding us bits for PCH ports */
		1548	assert_fdi_tx_enabled(dev_priv, pipe);
		1549	assert_fdi_rx_enabled(dev_priv, pipe);
		1550
3243	Serge	1551	if (HAS_PCH_CPT(dev)) {
		1552	/* Workaround: Set the timing override bit before enabling the
		1553	* pch transcoder. */
		1554	reg = TRANS_CHICKEN2(pipe);
		1555	val = I915_READ(reg);
		1556	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1557	I915_WRITE(reg, val);
3031	serge	1558	}
3243	Serge	1559
4104	Serge	1560	reg = PCH_TRANSCONF(pipe);
2327	Serge	1561	val = I915_READ(reg);
3031	serge	1562	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1563
		1564	if (HAS_PCH_IBX(dev_priv->dev)) {
		1565	/*
		1566	* make the BPC in transcoder be consistent with
		1567	* that in pipeconf reg.
		1568	*/
3480	Serge	1569	val &= ~PIPECONF_BPC_MASK;
		1570	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1571	}
3031	serge	1572
		1573	val &= ~TRANS_INTERLACE_MASK;
		1574	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1575	if (HAS_PCH_IBX(dev_priv->dev) &&
		1576	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1577	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1578	else
		1579	val \|= TRANS_INTERLACED;
		1580	else
		1581	val \|= TRANS_PROGRESSIVE;
		1582
2327	Serge	1583	I915_WRITE(reg, val \| TRANS_ENABLE);
		1584	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	1585	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	1586	}
		1587
3243	Serge	1588	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1589	enum transcoder cpu_transcoder)
		1590	{
		1591	u32 val, pipeconf_val;
		1592
		1593	/* PCH only available on ILK+ */
		1594	BUG_ON(dev_priv->info->gen < 5);
		1595
		1596	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1597	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1598	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1599
		1600	/* Workaround: set timing override bit. */
		1601	val = I915_READ(_TRANSA_CHICKEN2);
		1602	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1603	I915_WRITE(_TRANSA_CHICKEN2, val);
		1604
		1605	val = TRANS_ENABLE;
		1606	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1607
		1608	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1609	PIPECONF_INTERLACED_ILK)
		1610	val \|= TRANS_INTERLACED;
		1611	else
		1612	val \|= TRANS_PROGRESSIVE;
		1613
4104	Serge	1614	I915_WRITE(LPT_TRANSCONF, val);
		1615	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	1616	DRM_ERROR("Failed to enable PCH transcoder\n");
		1617	}
		1618
		1619	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1620	enum pipe pipe)
		1621	{
3243	Serge	1622	struct drm_device *dev = dev_priv->dev;
		1623	uint32_t reg, val;
2327	Serge	1624
		1625	/* FDI relies on the transcoder */
		1626	assert_fdi_tx_disabled(dev_priv, pipe);
		1627	assert_fdi_rx_disabled(dev_priv, pipe);
		1628
		1629	/* Ports must be off as well */
		1630	assert_pch_ports_disabled(dev_priv, pipe);
		1631
4104	Serge	1632	reg = PCH_TRANSCONF(pipe);
2327	Serge	1633	val = I915_READ(reg);
		1634	val &= ~TRANS_ENABLE;
		1635	I915_WRITE(reg, val);
		1636	/* wait for PCH transcoder off, transcoder state */
		1637	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	1638	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	1639
		1640	if (!HAS_PCH_IBX(dev)) {
		1641	/* Workaround: Clear the timing override chicken bit again. */
		1642	reg = TRANS_CHICKEN2(pipe);
		1643	val = I915_READ(reg);
		1644	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1645	I915_WRITE(reg, val);
		1646	}
2327	Serge	1647	}
		1648
3243	Serge	1649	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1650	{
		1651	u32 val;
		1652
4104	Serge	1653	val = I915_READ(LPT_TRANSCONF);
3243	Serge	1654	val &= ~TRANS_ENABLE;
4104	Serge	1655	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	1656	/* wait for PCH transcoder off, transcoder state */
4104	Serge	1657	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	1658	DRM_ERROR("Failed to disable PCH transcoder\n");
		1659
		1660	/* Workaround: clear timing override bit. */
		1661	val = I915_READ(_TRANSA_CHICKEN2);
		1662	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1663	I915_WRITE(_TRANSA_CHICKEN2, val);
		1664	}
		1665
2327	Serge	1666	/**
		1667	* intel_enable_pipe - enable a pipe, asserting requirements
		1668	* @dev_priv: i915 private structure
		1669	* @pipe: pipe to enable
		1670	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1671	*
		1672	* Enable @pipe, making sure that various hardware specific requirements
		1673	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1674	*
		1675	* @pipe should be %PIPE_A or %PIPE_B.
		1676	*
		1677	* Will wait until the pipe is actually running (i.e. first vblank) before
		1678	* returning.
		1679	*/
		1680	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1681	bool pch_port)
		1682	{
3243	Serge	1683	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1684	pipe);
3480	Serge	1685	enum pipe pch_transcoder;
2327	Serge	1686	int reg;
		1687	u32 val;
		1688
4104	Serge	1689	assert_planes_disabled(dev_priv, pipe);
		1690	assert_sprites_disabled(dev_priv, pipe);
		1691
3480	Serge	1692	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	1693	pch_transcoder = TRANSCODER_A;
		1694	else
		1695	pch_transcoder = pipe;
		1696
2327	Serge	1697	/*
		1698	* A pipe without a PLL won't actually be able to drive bits from
		1699	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1700	* need the check.
		1701	*/
		1702	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1703	assert_pll_enabled(dev_priv, pipe);
		1704	else {
		1705	if (pch_port) {
		1706	/* if driving the PCH, we need FDI enabled */
3243	Serge	1707	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	1708	assert_fdi_tx_pll_enabled(dev_priv,
		1709	(enum pipe) cpu_transcoder);
2327	Serge	1710	}
		1711	/* FIXME: assert CPU port conditions for SNB+ */
		1712	}
		1713
3243	Serge	1714	reg = PIPECONF(cpu_transcoder);
2327	Serge	1715	val = I915_READ(reg);
		1716	if (val & PIPECONF_ENABLE)
		1717	return;
		1718
		1719	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1720	intel_wait_for_vblank(dev_priv->dev, pipe);
		1721	}
		1722
		1723	/**
		1724	* intel_disable_pipe - disable a pipe, asserting requirements
		1725	* @dev_priv: i915 private structure
		1726	* @pipe: pipe to disable
		1727	*
		1728	* Disable @pipe, making sure that various hardware specific requirements
		1729	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1730	*
		1731	* @pipe should be %PIPE_A or %PIPE_B.
		1732	*
		1733	* Will wait until the pipe has shut down before returning.
		1734	*/
		1735	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1736	enum pipe pipe)
		1737	{
3243	Serge	1738	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1739	pipe);
2327	Serge	1740	int reg;
		1741	u32 val;
		1742
3031	serge	1743	/*
2327	Serge	1744	* Make sure planes won't keep trying to pump pixels to us,
		1745	* or we might hang the display.
		1746	*/
		1747	assert_planes_disabled(dev_priv, pipe);
3746	Serge	1748	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	1749
		1750	/* Don't disable pipe A or pipe A PLLs if needed */
		1751	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1752	return;
		1753
3243	Serge	1754	reg = PIPECONF(cpu_transcoder);
2327	Serge	1755	val = I915_READ(reg);
		1756	if ((val & PIPECONF_ENABLE) == 0)
		1757	return;
		1758
		1759	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1760	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1761	}
		1762
		1763	/*
		1764	* Plane regs are double buffered, going from enabled->disabled needs a
		1765	* trigger in order to latch. The display address reg provides this.
		1766	*/
3031	serge	1767	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1768	enum plane plane)
		1769	{
3243	Serge	1770	if (dev_priv->info->gen >= 4)
		1771	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1772	else
2327	Serge	1773	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1774	}
		1775
		1776	/**
		1777	* intel_enable_plane - enable a display plane on a given pipe
		1778	* @dev_priv: i915 private structure
		1779	* @plane: plane to enable
		1780	* @pipe: pipe being fed
		1781	*
		1782	* Enable @plane on @pipe, making sure that @pipe is running first.
		1783	*/
		1784	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1785	enum plane plane, enum pipe pipe)
		1786	{
		1787	int reg;
		1788	u32 val;
		1789
		1790	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1791	assert_pipe_enabled(dev_priv, pipe);
		1792
		1793	reg = DSPCNTR(plane);
		1794	val = I915_READ(reg);
		1795	if (val & DISPLAY_PLANE_ENABLE)
		1796	return;
		1797
		1798	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1799	intel_flush_display_plane(dev_priv, plane);
		1800	intel_wait_for_vblank(dev_priv->dev, pipe);
		1801	}
		1802
		1803	/**
		1804	* intel_disable_plane - disable a display plane
		1805	* @dev_priv: i915 private structure
		1806	* @plane: plane to disable
		1807	* @pipe: pipe consuming the data
		1808	*
		1809	* Disable @plane; should be an independent operation.
		1810	*/
		1811	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1812	enum plane plane, enum pipe pipe)
		1813	{
		1814	int reg;
		1815	u32 val;
		1816
		1817	reg = DSPCNTR(plane);
		1818	val = I915_READ(reg);
		1819	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1820	return;
		1821
		1822	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1823	intel_flush_display_plane(dev_priv, plane);
3031	serge	1824	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1825	}
		1826
3746	Serge	1827	static bool need_vtd_wa(struct drm_device *dev)
		1828	{
		1829	#ifdef CONFIG_INTEL_IOMMU
		1830	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		1831	return true;
		1832	#endif
		1833	return false;
		1834	}
		1835
2335	Serge	1836	int
		1837	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1838	struct drm_i915_gem_object *obj,
		1839	struct intel_ring_buffer *pipelined)
		1840	{
		1841	struct drm_i915_private *dev_priv = dev->dev_private;
		1842	u32 alignment;
		1843	int ret;
2327	Serge	1844
2335	Serge	1845	switch (obj->tiling_mode) {
		1846	case I915_TILING_NONE:
		1847	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1848	alignment = 128 * 1024;
		1849	else if (INTEL_INFO(dev)->gen >= 4)
		1850	alignment = 4 * 1024;
		1851	else
		1852	alignment = 64 * 1024;
		1853	break;
		1854	case I915_TILING_X:
		1855	/* pin() will align the object as required by fence */
		1856	alignment = 0;
		1857	break;
		1858	case I915_TILING_Y:
3746	Serge	1859	/* Despite that we check this in framebuffer_init userspace can
		1860	* screw us over and change the tiling after the fact. Only
		1861	* pinned buffers can't change their tiling. */
		1862	DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2335	Serge	1863	return -EINVAL;
		1864	default:
		1865	BUG();
		1866	}
2327	Serge	1867
3746	Serge	1868	/* Note that the w/a also requires 64 PTE of padding following the
		1869	* bo. We currently fill all unused PTE with the shadow page and so
		1870	* we should always have valid PTE following the scanout preventing
		1871	* the VT-d warning.
		1872	*/
		1873	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		1874	alignment = 256 * 1024;
		1875
2335	Serge	1876	dev_priv->mm.interruptible = false;
		1877	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1878	if (ret)
		1879	goto err_interruptible;
2327	Serge	1880
2335	Serge	1881	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1882	* fence, whereas 965+ only requires a fence if using
		1883	* framebuffer compression. For simplicity, we always install
		1884	* a fence as the cost is not that onerous.
		1885	*/
3480	Serge	1886	ret = i915_gem_object_get_fence(obj);
		1887	if (ret)
		1888	goto err_unpin;
2327	Serge	1889
3480	Serge	1890	i915_gem_object_pin_fence(obj);
		1891
2335	Serge	1892	dev_priv->mm.interruptible = true;
		1893	return 0;
2327	Serge	1894
2335	Serge	1895	err_unpin:
4104	Serge	1896	i915_gem_object_unpin_from_display_plane(obj);
2335	Serge	1897	err_interruptible:
		1898	dev_priv->mm.interruptible = true;
		1899	return ret;
		1900	}
2327	Serge	1901
3031	serge	1902	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1903	{
		1904	// i915_gem_object_unpin_fence(obj);
		1905	// i915_gem_object_unpin(obj);
		1906	}
		1907
		1908	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1909	* is assumed to be a power-of-two. */
3480	Serge	1910	unsigned long intel_gen4_compute_page_offset(int x, int y,
		1911	unsigned int tiling_mode,
		1912	unsigned int cpp,
3031	serge	1913	unsigned int pitch)
		1914	{
3480	Serge	1915	if (tiling_mode != I915_TILING_NONE) {
		1916	unsigned int tile_rows, tiles;
3031	serge	1917
		1918	tile_rows = *y / 8;
		1919	*y %= 8;
		1920
3480	Serge	1921	tiles = *x / (512/cpp);
		1922	*x %= 512/cpp;
		1923
3031	serge	1924	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	1925	} else {
		1926	unsigned int offset;
		1927
		1928	offset = y pitch + x cpp;
		1929	*y = 0;
		1930	*x = (offset & 4095) / cpp;
		1931	return offset & -4096;
		1932	}
3031	serge	1933	}
		1934
2327	Serge	1935	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1936	int x, int y)
		1937	{
		1938	struct drm_device *dev = crtc->dev;
		1939	struct drm_i915_private *dev_priv = dev->dev_private;
		1940	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1941	struct intel_framebuffer *intel_fb;
		1942	struct drm_i915_gem_object *obj;
		1943	int plane = intel_crtc->plane;
3031	serge	1944	unsigned long linear_offset;
2327	Serge	1945	u32 dspcntr;
		1946	u32 reg;
		1947
		1948	switch (plane) {
		1949	case 0:
		1950	case 1:
		1951	break;
		1952	default:
4104	Serge	1953	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	1954	return -EINVAL;
		1955	}
		1956
		1957	intel_fb = to_intel_framebuffer(fb);
		1958	obj = intel_fb->obj;
		1959
		1960	reg = DSPCNTR(plane);
		1961	dspcntr = I915_READ(reg);
		1962	/* Mask out pixel format bits in case we change it */
		1963	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	1964	switch (fb->pixel_format) {
		1965	case DRM_FORMAT_C8:
2327	Serge	1966	dspcntr \|= DISPPLANE_8BPP;
		1967	break;
3243	Serge	1968	case DRM_FORMAT_XRGB1555:
		1969	case DRM_FORMAT_ARGB1555:
		1970	dspcntr \|= DISPPLANE_BGRX555;
		1971	break;
		1972	case DRM_FORMAT_RGB565:
		1973	dspcntr \|= DISPPLANE_BGRX565;
		1974	break;
		1975	case DRM_FORMAT_XRGB8888:
		1976	case DRM_FORMAT_ARGB8888:
		1977	dspcntr \|= DISPPLANE_BGRX888;
		1978	break;
		1979	case DRM_FORMAT_XBGR8888:
		1980	case DRM_FORMAT_ABGR8888:
		1981	dspcntr \|= DISPPLANE_RGBX888;
		1982	break;
		1983	case DRM_FORMAT_XRGB2101010:
		1984	case DRM_FORMAT_ARGB2101010:
		1985	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	1986	break;
3243	Serge	1987	case DRM_FORMAT_XBGR2101010:
		1988	case DRM_FORMAT_ABGR2101010:
		1989	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	1990	break;
		1991	default:
3746	Serge	1992	BUG();
2327	Serge	1993	}
3243	Serge	1994
2327	Serge	1995	if (INTEL_INFO(dev)->gen >= 4) {
		1996	if (obj->tiling_mode != I915_TILING_NONE)
		1997	dspcntr \|= DISPPLANE_TILED;
		1998	else
		1999	dspcntr &= ~DISPPLANE_TILED;
		2000	}
		2001
4104	Serge	2002	if (IS_G4X(dev))
		2003	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2004
2327	Serge	2005	I915_WRITE(reg, dspcntr);
		2006
3031	serge	2007	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	2008
3031	serge	2009	if (INTEL_INFO(dev)->gen >= 4) {
		2010	intel_crtc->dspaddr_offset =
3480	Serge	2011	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2012	fb->bits_per_pixel / 8,
		2013	fb->pitches[0]);
		2014	linear_offset -= intel_crtc->dspaddr_offset;
		2015	} else {
		2016	intel_crtc->dspaddr_offset = linear_offset;
		2017	}
		2018
4104	Serge	2019	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2020	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2021	fb->pitches[0]);
2342	Serge	2022	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2023	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2024	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2025	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	2026	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2027	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2028	} else
4104	Serge	2029	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2327	Serge	2030	POSTING_READ(reg);
		2031
		2032	return 0;
		2033	}
		2034
		2035	static int ironlake_update_plane(struct drm_crtc *crtc,
		2036	struct drm_framebuffer *fb, int x, int y)
		2037	{
		2038	struct drm_device *dev = crtc->dev;
		2039	struct drm_i915_private *dev_priv = dev->dev_private;
		2040	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2041	struct intel_framebuffer *intel_fb;
		2042	struct drm_i915_gem_object *obj;
		2043	int plane = intel_crtc->plane;
3031	serge	2044	unsigned long linear_offset;
2327	Serge	2045	u32 dspcntr;
		2046	u32 reg;
		2047
		2048	switch (plane) {
		2049	case 0:
		2050	case 1:
2342	Serge	2051	case 2:
2327	Serge	2052	break;
		2053	default:
4104	Serge	2054	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	2055	return -EINVAL;
		2056	}
		2057
		2058	intel_fb = to_intel_framebuffer(fb);
		2059	obj = intel_fb->obj;
		2060
		2061	reg = DSPCNTR(plane);
		2062	dspcntr = I915_READ(reg);
		2063	/* Mask out pixel format bits in case we change it */
		2064	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2065	switch (fb->pixel_format) {
		2066	case DRM_FORMAT_C8:
2327	Serge	2067	dspcntr \|= DISPPLANE_8BPP;
		2068	break;
3243	Serge	2069	case DRM_FORMAT_RGB565:
		2070	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2071	break;
3243	Serge	2072	case DRM_FORMAT_XRGB8888:
		2073	case DRM_FORMAT_ARGB8888:
		2074	dspcntr \|= DISPPLANE_BGRX888;
		2075	break;
		2076	case DRM_FORMAT_XBGR8888:
		2077	case DRM_FORMAT_ABGR8888:
		2078	dspcntr \|= DISPPLANE_RGBX888;
		2079	break;
		2080	case DRM_FORMAT_XRGB2101010:
		2081	case DRM_FORMAT_ARGB2101010:
		2082	dspcntr \|= DISPPLANE_BGRX101010;
		2083	break;
		2084	case DRM_FORMAT_XBGR2101010:
		2085	case DRM_FORMAT_ABGR2101010:
		2086	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2087	break;
		2088	default:
3746	Serge	2089	BUG();
2327	Serge	2090	}
		2091
3480	Serge	2092	if (obj->tiling_mode != I915_TILING_NONE)
		2093	dspcntr \|= DISPPLANE_TILED;
		2094	else
2327	Serge	2095	dspcntr &= ~DISPPLANE_TILED;
		2096
4104	Serge	2097	if (IS_HASWELL(dev))
		2098	dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
		2099	else
2327	Serge	2100	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2101
		2102	I915_WRITE(reg, dspcntr);
		2103
3031	serge	2104	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2105	intel_crtc->dspaddr_offset =
3480	Serge	2106	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2107	fb->bits_per_pixel / 8,
		2108	fb->pitches[0]);
		2109	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2110
4104	Serge	2111	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2112	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2113	fb->pitches[0]);
2342	Serge	2114	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2115	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2116	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3243	Serge	2117	if (IS_HASWELL(dev)) {
		2118	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2119	} else {
2330	Serge	2120	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2121	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2122	}
2330	Serge	2123	POSTING_READ(reg);
2327	Serge	2124
		2125	return 0;
		2126	}
		2127
		2128	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2129	static int
		2130	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2131	int x, int y, enum mode_set_atomic state)
		2132	{
		2133	struct drm_device *dev = crtc->dev;
		2134	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2135
		2136	if (dev_priv->display.disable_fbc)
		2137	dev_priv->display.disable_fbc(dev);
		2138	intel_increase_pllclock(crtc);
		2139
		2140	return dev_priv->display.update_plane(crtc, fb, x, y);
		2141	}
		2142
		2143	#if 0
4104	Serge	2144	void intel_display_handle_reset(struct drm_device *dev)
		2145	{
		2146	struct drm_i915_private *dev_priv = dev->dev_private;
		2147	struct drm_crtc *crtc;
		2148
		2149	/*
		2150	* Flips in the rings have been nuked by the reset,
		2151	* so complete all pending flips so that user space
		2152	* will get its events and not get stuck.
		2153	*
		2154	* Also update the base address of all primary
		2155	* planes to the the last fb to make sure we're
		2156	* showing the correct fb after a reset.
		2157	*
		2158	* Need to make two loops over the crtcs so that we
		2159	* don't try to grab a crtc mutex before the
		2160	* pending_flip_queue really got woken up.
		2161	*/
		2162
		2163	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2164	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2165	enum plane plane = intel_crtc->plane;
		2166
		2167	intel_prepare_page_flip(dev, plane);
		2168	intel_finish_page_flip_plane(dev, plane);
		2169	}
		2170
		2171	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2172	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2173
		2174	mutex_lock(&crtc->mutex);
		2175	if (intel_crtc->active)
		2176	dev_priv->display.update_plane(crtc, crtc->fb,
		2177	crtc->x, crtc->y);
		2178	mutex_unlock(&crtc->mutex);
		2179	}
		2180	}
		2181
3031	serge	2182	static int
		2183	intel_finish_fb(struct drm_framebuffer *old_fb)
		2184	{
		2185	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2186	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2187	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2188	int ret;
		2189
3031	serge	2190	/* Big Hammer, we also need to ensure that any pending
		2191	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2192	* current scanout is retired before unpinning the old
		2193	* framebuffer.
		2194	*
		2195	* This should only fail upon a hung GPU, in which case we
		2196	* can safely continue.
		2197	*/
		2198	dev_priv->mm.interruptible = false;
		2199	ret = i915_gem_object_finish_gpu(obj);
		2200	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2201
3031	serge	2202	return ret;
2327	Serge	2203	}
4104	Serge	2204
		2205	static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
		2206	{
		2207	struct drm_device *dev = crtc->dev;
		2208	struct drm_i915_master_private *master_priv;
		2209	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2210
		2211	if (!dev->primary->master)
		2212	return;
		2213
		2214	master_priv = dev->primary->master->driver_priv;
		2215	if (!master_priv->sarea_priv)
		2216	return;
		2217
		2218	switch (intel_crtc->pipe) {
		2219	case 0:
		2220	master_priv->sarea_priv->pipeA_x = x;
		2221	master_priv->sarea_priv->pipeA_y = y;
		2222	break;
		2223	case 1:
		2224	master_priv->sarea_priv->pipeB_x = x;
		2225	master_priv->sarea_priv->pipeB_y = y;
		2226	break;
		2227	default:
		2228	break;
		2229	}
		2230	}
3031	serge	2231	#endif
2327	Serge	2232
		2233	static int
		2234	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2235	struct drm_framebuffer *fb)
2327	Serge	2236	{
		2237	struct drm_device *dev = crtc->dev;
3031	serge	2238	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2239	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2240	struct drm_framebuffer *old_fb;
2342	Serge	2241	int ret;
2327	Serge	2242
		2243	/* no fb bound */
3031	serge	2244	if (!fb) {
2327	Serge	2245	DRM_ERROR("No FB bound\n");
		2246	return 0;
		2247	}
		2248
3746	Serge	2249	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
4104	Serge	2250	DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
		2251	plane_name(intel_crtc->plane),
3746	Serge	2252	INTEL_INFO(dev)->num_pipes);
2327	Serge	2253	return -EINVAL;
		2254	}
		2255
		2256	mutex_lock(&dev->struct_mutex);
4280	Serge	2257	ret = intel_pin_and_fence_fb_obj(dev,
		2258	to_intel_framebuffer(fb)->obj,
		2259	NULL);
		2260	if (ret != 0) {
		2261	mutex_unlock(&dev->struct_mutex);
		2262	DRM_ERROR("pin & fence failed\n");
		2263	return ret;
		2264	}
2327	Serge	2265
4280	Serge	2266	/* Update pipe size and adjust fitter if needed */
		2267	if (i915_fastboot) {
		2268	I915_WRITE(PIPESRC(intel_crtc->pipe),
		2269	((crtc->mode.hdisplay - 1) << 16) \|
		2270	(crtc->mode.vdisplay - 1));
		2271	if (!intel_crtc->config.pch_pfit.enabled &&
		2272	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\|
		2273	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
		2274	I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
		2275	I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
		2276	I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
		2277	}
		2278	}
3031	serge	2279
		2280	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2281	if (ret) {
3031	serge	2282	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2283	mutex_unlock(&dev->struct_mutex);
		2284	DRM_ERROR("failed to update base address\n");
3243	Serge	2285	return ret;
2327	Serge	2286	}
		2287
3031	serge	2288	old_fb = crtc->fb;
		2289	crtc->fb = fb;
		2290	crtc->x = x;
		2291	crtc->y = y;
		2292
		2293	if (old_fb) {
4104	Serge	2294	if (intel_crtc->active && old_fb != fb)
3031	serge	2295	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2296	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2297	}
		2298
		2299	intel_update_fbc(dev);
4104	Serge	2300	intel_edp_psr_update(dev);
2336	Serge	2301	mutex_unlock(&dev->struct_mutex);
2327	Serge	2302
2336	Serge	2303	return 0;
2327	Serge	2304	}
		2305
		2306	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2307	{
		2308	struct drm_device *dev = crtc->dev;
		2309	struct drm_i915_private *dev_priv = dev->dev_private;
		2310	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2311	int pipe = intel_crtc->pipe;
		2312	u32 reg, temp;
		2313
		2314	/* enable normal train */
		2315	reg = FDI_TX_CTL(pipe);
		2316	temp = I915_READ(reg);
		2317	if (IS_IVYBRIDGE(dev)) {
		2318	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2319	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2320	} else {
		2321	temp &= ~FDI_LINK_TRAIN_NONE;
		2322	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2323	}
		2324	I915_WRITE(reg, temp);
		2325
		2326	reg = FDI_RX_CTL(pipe);
		2327	temp = I915_READ(reg);
		2328	if (HAS_PCH_CPT(dev)) {
		2329	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2330	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2331	} else {
		2332	temp &= ~FDI_LINK_TRAIN_NONE;
		2333	temp \|= FDI_LINK_TRAIN_NONE;
		2334	}
		2335	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2336
		2337	/* wait one idle pattern time */
		2338	POSTING_READ(reg);
		2339	udelay(1000);
		2340
		2341	/* IVB wants error correction enabled */
		2342	if (IS_IVYBRIDGE(dev))
		2343	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2344	FDI_FE_ERRC_ENABLE);
		2345	}
		2346
4280	Serge	2347	static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
4104	Serge	2348	{
4280	Serge	2349	return crtc->base.enabled && crtc->active &&
		2350	crtc->config.has_pch_encoder;
4104	Serge	2351	}
		2352
3243	Serge	2353	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2354	{
		2355	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2356	struct intel_crtc *pipe_B_crtc =
		2357	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2358	struct intel_crtc *pipe_C_crtc =
		2359	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2360	uint32_t temp;
2327	Serge	2361
4104	Serge	2362	/*
		2363	* When everything is off disable fdi C so that we could enable fdi B
		2364	* with all lanes. Note that we don't care about enabled pipes without
		2365	* an enabled pch encoder.
		2366	*/
		2367	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
		2368	!pipe_has_enabled_pch(pipe_C_crtc)) {
3243	Serge	2369	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2370	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2371
		2372	temp = I915_READ(SOUTH_CHICKEN1);
		2373	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2374	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2375	I915_WRITE(SOUTH_CHICKEN1, temp);
		2376	}
2327	Serge	2377	}
		2378
		2379	/* The FDI link training functions for ILK/Ibexpeak. */
		2380	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2381	{
		2382	struct drm_device *dev = crtc->dev;
		2383	struct drm_i915_private *dev_priv = dev->dev_private;
		2384	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2385	int pipe = intel_crtc->pipe;
		2386	int plane = intel_crtc->plane;
		2387	u32 reg, temp, tries;
		2388
		2389	/* FDI needs bits from pipe & plane first */
		2390	assert_pipe_enabled(dev_priv, pipe);
		2391	assert_plane_enabled(dev_priv, plane);
		2392
		2393	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2394	for train result */
		2395	reg = FDI_RX_IMR(pipe);
		2396	temp = I915_READ(reg);
		2397	temp &= ~FDI_RX_SYMBOL_LOCK;
		2398	temp &= ~FDI_RX_BIT_LOCK;
		2399	I915_WRITE(reg, temp);
		2400	I915_READ(reg);
		2401	udelay(150);
		2402
		2403	/* enable CPU FDI TX and PCH FDI RX */
		2404	reg = FDI_TX_CTL(pipe);
		2405	temp = I915_READ(reg);
4104	Serge	2406	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2407	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2408	temp &= ~FDI_LINK_TRAIN_NONE;
		2409	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2410	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2411
		2412	reg = FDI_RX_CTL(pipe);
		2413	temp = I915_READ(reg);
		2414	temp &= ~FDI_LINK_TRAIN_NONE;
		2415	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2416	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2417
		2418	POSTING_READ(reg);
		2419	udelay(150);
		2420
		2421	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2422	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2423	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2424	FDI_RX_PHASE_SYNC_POINTER_EN);
		2425
		2426	reg = FDI_RX_IIR(pipe);
		2427	for (tries = 0; tries < 5; tries++) {
		2428	temp = I915_READ(reg);
		2429	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2430
		2431	if ((temp & FDI_RX_BIT_LOCK)) {
		2432	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2433	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2434	break;
		2435	}
		2436	}
		2437	if (tries == 5)
		2438	DRM_ERROR("FDI train 1 fail!\n");
		2439
		2440	/* Train 2 */
		2441	reg = FDI_TX_CTL(pipe);
		2442	temp = I915_READ(reg);
		2443	temp &= ~FDI_LINK_TRAIN_NONE;
		2444	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2445	I915_WRITE(reg, temp);
		2446
		2447	reg = FDI_RX_CTL(pipe);
		2448	temp = I915_READ(reg);
		2449	temp &= ~FDI_LINK_TRAIN_NONE;
		2450	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2451	I915_WRITE(reg, temp);
		2452
		2453	POSTING_READ(reg);
		2454	udelay(150);
		2455
		2456	reg = FDI_RX_IIR(pipe);
		2457	for (tries = 0; tries < 5; tries++) {
		2458	temp = I915_READ(reg);
		2459	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2460
		2461	if (temp & FDI_RX_SYMBOL_LOCK) {
		2462	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2463	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2464	break;
		2465	}
		2466	}
		2467	if (tries == 5)
		2468	DRM_ERROR("FDI train 2 fail!\n");
		2469
		2470	DRM_DEBUG_KMS("FDI train done\n");
		2471
		2472	}
		2473
2342	Serge	2474	static const int snb_b_fdi_train_param[] = {
2327	Serge	2475	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2476	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2477	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2478	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2479	};
		2480
		2481	/* The FDI link training functions for SNB/Cougarpoint. */
		2482	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2483	{
		2484	struct drm_device *dev = crtc->dev;
		2485	struct drm_i915_private *dev_priv = dev->dev_private;
		2486	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2487	int pipe = intel_crtc->pipe;
3031	serge	2488	u32 reg, temp, i, retry;
2327	Serge	2489
		2490	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2491	for train result */
		2492	reg = FDI_RX_IMR(pipe);
		2493	temp = I915_READ(reg);
		2494	temp &= ~FDI_RX_SYMBOL_LOCK;
		2495	temp &= ~FDI_RX_BIT_LOCK;
		2496	I915_WRITE(reg, temp);
		2497
		2498	POSTING_READ(reg);
		2499	udelay(150);
		2500
		2501	/* enable CPU FDI TX and PCH FDI RX */
		2502	reg = FDI_TX_CTL(pipe);
		2503	temp = I915_READ(reg);
4104	Serge	2504	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2505	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2506	temp &= ~FDI_LINK_TRAIN_NONE;
		2507	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2508	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2509	/* SNB-B */
		2510	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2511	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2512
3243	Serge	2513	I915_WRITE(FDI_RX_MISC(pipe),
		2514	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2515
2327	Serge	2516	reg = FDI_RX_CTL(pipe);
		2517	temp = I915_READ(reg);
		2518	if (HAS_PCH_CPT(dev)) {
		2519	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2520	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2521	} else {
		2522	temp &= ~FDI_LINK_TRAIN_NONE;
		2523	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2524	}
		2525	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2526
		2527	POSTING_READ(reg);
		2528	udelay(150);
		2529
2342	Serge	2530	for (i = 0; i < 4; i++) {
2327	Serge	2531	reg = FDI_TX_CTL(pipe);
		2532	temp = I915_READ(reg);
		2533	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2534	temp \|= snb_b_fdi_train_param[i];
		2535	I915_WRITE(reg, temp);
		2536
		2537	POSTING_READ(reg);
		2538	udelay(500);
		2539
3031	serge	2540	for (retry = 0; retry < 5; retry++) {
2327	Serge	2541	reg = FDI_RX_IIR(pipe);
		2542	temp = I915_READ(reg);
		2543	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2544	if (temp & FDI_RX_BIT_LOCK) {
		2545	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2546	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2547	break;
		2548	}
3031	serge	2549	udelay(50);
		2550	}
		2551	if (retry < 5)
		2552	break;
2327	Serge	2553	}
		2554	if (i == 4)
		2555	DRM_ERROR("FDI train 1 fail!\n");
		2556
		2557	/* Train 2 */
		2558	reg = FDI_TX_CTL(pipe);
		2559	temp = I915_READ(reg);
		2560	temp &= ~FDI_LINK_TRAIN_NONE;
		2561	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2562	if (IS_GEN6(dev)) {
		2563	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2564	/* SNB-B */
		2565	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2566	}
		2567	I915_WRITE(reg, temp);
		2568
		2569	reg = FDI_RX_CTL(pipe);
		2570	temp = I915_READ(reg);
		2571	if (HAS_PCH_CPT(dev)) {
		2572	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2573	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2574	} else {
		2575	temp &= ~FDI_LINK_TRAIN_NONE;
		2576	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2577	}
		2578	I915_WRITE(reg, temp);
		2579
		2580	POSTING_READ(reg);
		2581	udelay(150);
		2582
2342	Serge	2583	for (i = 0; i < 4; i++) {
2327	Serge	2584	reg = FDI_TX_CTL(pipe);
		2585	temp = I915_READ(reg);
		2586	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2587	temp \|= snb_b_fdi_train_param[i];
		2588	I915_WRITE(reg, temp);
		2589
		2590	POSTING_READ(reg);
		2591	udelay(500);
		2592
3031	serge	2593	for (retry = 0; retry < 5; retry++) {
2327	Serge	2594	reg = FDI_RX_IIR(pipe);
		2595	temp = I915_READ(reg);
		2596	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2597	if (temp & FDI_RX_SYMBOL_LOCK) {
		2598	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2599	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2600	break;
		2601	}
3031	serge	2602	udelay(50);
		2603	}
		2604	if (retry < 5)
		2605	break;
2327	Serge	2606	}
		2607	if (i == 4)
		2608	DRM_ERROR("FDI train 2 fail!\n");
		2609
		2610	DRM_DEBUG_KMS("FDI train done.\n");
		2611	}
		2612
		2613	/* Manual link training for Ivy Bridge A0 parts */
		2614	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2615	{
		2616	struct drm_device *dev = crtc->dev;
		2617	struct drm_i915_private *dev_priv = dev->dev_private;
		2618	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2619	int pipe = intel_crtc->pipe;
4104	Serge	2620	u32 reg, temp, i, j;
2327	Serge	2621
		2622	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2623	for train result */
		2624	reg = FDI_RX_IMR(pipe);
		2625	temp = I915_READ(reg);
		2626	temp &= ~FDI_RX_SYMBOL_LOCK;
		2627	temp &= ~FDI_RX_BIT_LOCK;
		2628	I915_WRITE(reg, temp);
		2629
		2630	POSTING_READ(reg);
		2631	udelay(150);
		2632
3243	Serge	2633	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		2634	I915_READ(FDI_RX_IIR(pipe)));
		2635
4104	Serge	2636	/* Try each vswing and preemphasis setting twice before moving on */
		2637	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		2638	/* disable first in case we need to retry */
		2639	reg = FDI_TX_CTL(pipe);
		2640	temp = I915_READ(reg);
		2641	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2642	temp &= ~FDI_TX_ENABLE;
		2643	I915_WRITE(reg, temp);
		2644
		2645	reg = FDI_RX_CTL(pipe);
		2646	temp = I915_READ(reg);
		2647	temp &= ~FDI_LINK_TRAIN_AUTO;
		2648	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2649	temp &= ~FDI_RX_ENABLE;
		2650	I915_WRITE(reg, temp);
		2651
2327	Serge	2652	/* enable CPU FDI TX and PCH FDI RX */
		2653	reg = FDI_TX_CTL(pipe);
		2654	temp = I915_READ(reg);
4104	Serge	2655	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2656	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2657	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2658	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	2659	temp \|= snb_b_fdi_train_param[j/2];
2342	Serge	2660	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2661	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2662
3243	Serge	2663	I915_WRITE(FDI_RX_MISC(pipe),
		2664	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2665
2327	Serge	2666	reg = FDI_RX_CTL(pipe);
		2667	temp = I915_READ(reg);
		2668	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2669	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2670	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2671
		2672	POSTING_READ(reg);
4104	Serge	2673	udelay(1); /* should be 0.5us */
2327	Serge	2674
2342	Serge	2675	for (i = 0; i < 4; i++) {
2327	Serge	2676	reg = FDI_RX_IIR(pipe);
		2677	temp = I915_READ(reg);
		2678	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2679
		2680	if (temp & FDI_RX_BIT_LOCK \|\|
		2681	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2682	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	2683	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		2684	i);
2327	Serge	2685	break;
		2686	}
4104	Serge	2687	udelay(1); /* should be 0.5us */
		2688	}
		2689	if (i == 4) {
		2690	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		2691	continue;
2327	Serge	2692	}
		2693
		2694	/* Train 2 */
		2695	reg = FDI_TX_CTL(pipe);
		2696	temp = I915_READ(reg);
		2697	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2698	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2699	I915_WRITE(reg, temp);
		2700
		2701	reg = FDI_RX_CTL(pipe);
		2702	temp = I915_READ(reg);
		2703	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2704	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2705	I915_WRITE(reg, temp);
		2706
		2707	POSTING_READ(reg);
4104	Serge	2708	udelay(2); /* should be 1.5us */
2327	Serge	2709
2342	Serge	2710	for (i = 0; i < 4; i++) {
2327	Serge	2711	reg = FDI_RX_IIR(pipe);
		2712	temp = I915_READ(reg);
		2713	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2714
4104	Serge	2715	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		2716	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2327	Serge	2717	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	2718	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		2719	i);
		2720	goto train_done;
2327	Serge	2721	}
4104	Serge	2722	udelay(2); /* should be 1.5us */
2327	Serge	2723	}
		2724	if (i == 4)
4104	Serge	2725	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		2726	}
2327	Serge	2727
4104	Serge	2728	train_done:
2327	Serge	2729	DRM_DEBUG_KMS("FDI train done.\n");
		2730	}
		2731
3031	serge	2732	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2733	{
3031	serge	2734	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2735	struct drm_i915_private *dev_priv = dev->dev_private;
		2736	int pipe = intel_crtc->pipe;
		2737	u32 reg, temp;
		2738
		2739
		2740	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2741	reg = FDI_RX_CTL(pipe);
		2742	temp = I915_READ(reg);
4104	Serge	2743	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
		2744	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3480	Serge	2745	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2746	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2747
		2748	POSTING_READ(reg);
		2749	udelay(200);
		2750
		2751	/* Switch from Rawclk to PCDclk */
		2752	temp = I915_READ(reg);
		2753	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2754
		2755	POSTING_READ(reg);
		2756	udelay(200);
		2757
		2758	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2759	reg = FDI_TX_CTL(pipe);
		2760	temp = I915_READ(reg);
		2761	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2762	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2763
		2764	POSTING_READ(reg);
		2765	udelay(100);
		2766	}
		2767	}
		2768
3031	serge	2769	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2770	{
		2771	struct drm_device *dev = intel_crtc->base.dev;
		2772	struct drm_i915_private *dev_priv = dev->dev_private;
		2773	int pipe = intel_crtc->pipe;
		2774	u32 reg, temp;
		2775
		2776	/* Switch from PCDclk to Rawclk */
		2777	reg = FDI_RX_CTL(pipe);
		2778	temp = I915_READ(reg);
		2779	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2780
		2781	/* Disable CPU FDI TX PLL */
		2782	reg = FDI_TX_CTL(pipe);
		2783	temp = I915_READ(reg);
		2784	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2785
		2786	POSTING_READ(reg);
		2787	udelay(100);
		2788
		2789	reg = FDI_RX_CTL(pipe);
		2790	temp = I915_READ(reg);
		2791	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2792
		2793	/* Wait for the clocks to turn off. */
		2794	POSTING_READ(reg);
		2795	udelay(100);
		2796	}
		2797
2327	Serge	2798	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2799	{
		2800	struct drm_device *dev = crtc->dev;
		2801	struct drm_i915_private *dev_priv = dev->dev_private;
		2802	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2803	int pipe = intel_crtc->pipe;
		2804	u32 reg, temp;
		2805
		2806	/* disable CPU FDI tx and PCH FDI rx */
		2807	reg = FDI_TX_CTL(pipe);
		2808	temp = I915_READ(reg);
		2809	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2810	POSTING_READ(reg);
		2811
		2812	reg = FDI_RX_CTL(pipe);
		2813	temp = I915_READ(reg);
		2814	temp &= ~(0x7 << 16);
3480	Serge	2815	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2816	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2817
		2818	POSTING_READ(reg);
		2819	udelay(100);
		2820
		2821	/* Ironlake workaround, disable clock pointer after downing FDI */
		2822	if (HAS_PCH_IBX(dev)) {
		2823	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2824	}
		2825
		2826	/* still set train pattern 1 */
		2827	reg = FDI_TX_CTL(pipe);
		2828	temp = I915_READ(reg);
		2829	temp &= ~FDI_LINK_TRAIN_NONE;
		2830	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2831	I915_WRITE(reg, temp);
		2832
		2833	reg = FDI_RX_CTL(pipe);
		2834	temp = I915_READ(reg);
		2835	if (HAS_PCH_CPT(dev)) {
		2836	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2837	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2838	} else {
		2839	temp &= ~FDI_LINK_TRAIN_NONE;
		2840	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2841	}
		2842	/* BPC in FDI rx is consistent with that in PIPECONF */
		2843	temp &= ~(0x07 << 16);
3480	Serge	2844	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2845	I915_WRITE(reg, temp);
		2846
		2847	POSTING_READ(reg);
		2848	udelay(100);
		2849	}
		2850
3031	serge	2851	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2852	{
3031	serge	2853	struct drm_device *dev = crtc->dev;
2327	Serge	2854	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2855	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2856	unsigned long flags;
		2857	bool pending;
2327	Serge	2858
3480	Serge	2859	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2860	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3031	serge	2861	return false;
2327	Serge	2862
3031	serge	2863	spin_lock_irqsave(&dev->event_lock, flags);
		2864	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2865	spin_unlock_irqrestore(&dev->event_lock, flags);
		2866
		2867	return pending;
2327	Serge	2868	}
		2869
3031	serge	2870	#if 0
2327	Serge	2871	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2872	{
3031	serge	2873	struct drm_device *dev = crtc->dev;
		2874	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2875
		2876	if (crtc->fb == NULL)
		2877	return;
		2878
3480	Serge	2879	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		2880
2360	Serge	2881	wait_event(dev_priv->pending_flip_queue,
3031	serge	2882	!intel_crtc_has_pending_flip(crtc));
		2883
		2884	mutex_lock(&dev->struct_mutex);
		2885	intel_finish_fb(crtc->fb);
		2886	mutex_unlock(&dev->struct_mutex);
2327	Serge	2887	}
3031	serge	2888	#endif
2327	Serge	2889
3031	serge	2890	/* Program iCLKIP clock to the desired frequency */
		2891	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2892	{
		2893	struct drm_device *dev = crtc->dev;
		2894	struct drm_i915_private *dev_priv = dev->dev_private;
		2895	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2896	u32 temp;
		2897
3480	Serge	2898	mutex_lock(&dev_priv->dpio_lock);
		2899
3031	serge	2900	/* It is necessary to ungate the pixclk gate prior to programming
		2901	* the divisors, and gate it back when it is done.
		2902	*/
		2903	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2904
		2905	/* Disable SSCCTL */
		2906	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	2907	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		2908	SBI_SSCCTL_DISABLE,
		2909	SBI_ICLK);
3031	serge	2910
		2911	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2912	if (crtc->mode.clock == 20000) {
		2913	auxdiv = 1;
		2914	divsel = 0x41;
		2915	phaseinc = 0x20;
		2916	} else {
		2917	/* The iCLK virtual clock root frequency is in MHz,
		2918	* but the crtc->mode.clock in in KHz. To get the divisors,
		2919	* it is necessary to divide one by another, so we
		2920	* convert the virtual clock precision to KHz here for higher
		2921	* precision.
		2922	*/
		2923	u32 iclk_virtual_root_freq = 172800 * 1000;
		2924	u32 iclk_pi_range = 64;
		2925	u32 desired_divisor, msb_divisor_value, pi_value;
		2926
		2927	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2928	msb_divisor_value = desired_divisor / iclk_pi_range;
		2929	pi_value = desired_divisor % iclk_pi_range;
		2930
		2931	auxdiv = 0;
		2932	divsel = msb_divisor_value - 2;
		2933	phaseinc = pi_value;
		2934	}
		2935
		2936	/* This should not happen with any sane values */
		2937	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2938	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2939	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2940	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2941
		2942	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2943	crtc->mode.clock,
		2944	auxdiv,
		2945	divsel,
		2946	phasedir,
		2947	phaseinc);
		2948
		2949	/* Program SSCDIVINTPHASE6 */
3243	Serge	2950	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	2951	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2952	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2953	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2954	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2955	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2956	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	2957	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	2958
		2959	/* Program SSCAUXDIV */
3243	Serge	2960	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	2961	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2962	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	2963	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	2964
		2965	/* Enable modulator and associated divider */
3243	Serge	2966	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	2967	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	2968	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	2969
		2970	/* Wait for initialization time */
		2971	udelay(24);
		2972
		2973	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	2974
		2975	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	2976	}
		2977
4104	Serge	2978	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		2979	enum pipe pch_transcoder)
		2980	{
		2981	struct drm_device *dev = crtc->base.dev;
		2982	struct drm_i915_private *dev_priv = dev->dev_private;
		2983	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
		2984
		2985	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		2986	I915_READ(HTOTAL(cpu_transcoder)));
		2987	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		2988	I915_READ(HBLANK(cpu_transcoder)));
		2989	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		2990	I915_READ(HSYNC(cpu_transcoder)));
		2991
		2992	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		2993	I915_READ(VTOTAL(cpu_transcoder)));
		2994	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		2995	I915_READ(VBLANK(cpu_transcoder)));
		2996	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		2997	I915_READ(VSYNC(cpu_transcoder)));
		2998	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		2999	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		3000	}
		3001
4280	Serge	3002	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		3003	{
		3004	struct drm_i915_private *dev_priv = dev->dev_private;
		3005	uint32_t temp;
		3006
		3007	temp = I915_READ(SOUTH_CHICKEN1);
		3008	if (temp & FDI_BC_BIFURCATION_SELECT)
		3009	return;
		3010
		3011	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		3012	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		3013
		3014	temp \|= FDI_BC_BIFURCATION_SELECT;
		3015	DRM_DEBUG_KMS("enabling fdi C rx\n");
		3016	I915_WRITE(SOUTH_CHICKEN1, temp);
		3017	POSTING_READ(SOUTH_CHICKEN1);
		3018	}
		3019
		3020	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
		3021	{
		3022	struct drm_device *dev = intel_crtc->base.dev;
		3023	struct drm_i915_private *dev_priv = dev->dev_private;
		3024
		3025	switch (intel_crtc->pipe) {
		3026	case PIPE_A:
		3027	break;
		3028	case PIPE_B:
		3029	if (intel_crtc->config.fdi_lanes > 2)
		3030	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		3031	else
		3032	cpt_enable_fdi_bc_bifurcation(dev);
		3033
		3034	break;
		3035	case PIPE_C:
		3036	cpt_enable_fdi_bc_bifurcation(dev);
		3037
		3038	break;
		3039	default:
		3040	BUG();
		3041	}
		3042	}
		3043
2327	Serge	3044	/*
		3045	* Enable PCH resources required for PCH ports:
		3046	* - PCH PLLs
		3047	* - FDI training & RX/TX
		3048	* - update transcoder timings
		3049	* - DP transcoding bits
		3050	* - transcoder
		3051	*/
		3052	static void ironlake_pch_enable(struct drm_crtc *crtc)
		3053	{
		3054	struct drm_device *dev = crtc->dev;
		3055	struct drm_i915_private *dev_priv = dev->dev_private;
		3056	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3057	int pipe = intel_crtc->pipe;
3031	serge	3058	u32 reg, temp;
2327	Serge	3059
4104	Serge	3060	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	3061
4280	Serge	3062	if (IS_IVYBRIDGE(dev))
		3063	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
		3064
3243	Serge	3065	/* Write the TU size bits before fdi link training, so that error
		3066	* detection works. */
		3067	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		3068	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		3069
2327	Serge	3070	/* For PCH output, training FDI link */
		3071	dev_priv->display.fdi_link_train(crtc);
		3072
4104	Serge	3073	/* We need to program the right clock selection before writing the pixel
		3074	* mutliplier into the DPLL. */
3243	Serge	3075	if (HAS_PCH_CPT(dev)) {
3031	serge	3076	u32 sel;
2342	Serge	3077
2327	Serge	3078	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3079	temp \|= TRANS_DPLL_ENABLE(pipe);
		3080	sel = TRANS_DPLLB_SEL(pipe);
		3081	if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	3082	temp \|= sel;
		3083	else
		3084	temp &= ~sel;
2327	Serge	3085	I915_WRITE(PCH_DPLL_SEL, temp);
		3086	}
		3087
4104	Serge	3088	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3089	* transcoder, and we actually should do this to not upset any PCH
		3090	* transcoder that already use the clock when we share it.
		3091	*
		3092	* Note that enable_shared_dpll tries to do the right thing, but
		3093	* get_shared_dpll unconditionally resets the pll - we need that to have
		3094	* the right LVDS enable sequence. */
		3095	ironlake_enable_shared_dpll(intel_crtc);
		3096
2327	Serge	3097	/* set transcoder timing, panel must allow it */
		3098	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	3099	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	3100
		3101	intel_fdi_normal_train(crtc);
		3102
		3103	/* For PCH DP, enable TRANS_DP_CTL */
		3104	if (HAS_PCH_CPT(dev) &&
2342	Serge	3105	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3106	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3107	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3108	reg = TRANS_DP_CTL(pipe);
		3109	temp = I915_READ(reg);
		3110	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3111	TRANS_DP_SYNC_MASK \|
		3112	TRANS_DP_BPC_MASK);
		3113	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3114	TRANS_DP_ENH_FRAMING);
		3115	temp \|= bpc << 9; /* same format but at 11:9 */
		3116
		3117	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3118	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3119	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3120	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3121
		3122	switch (intel_trans_dp_port_sel(crtc)) {
		3123	case PCH_DP_B:
		3124	temp \|= TRANS_DP_PORT_SEL_B;
		3125	break;
		3126	case PCH_DP_C:
		3127	temp \|= TRANS_DP_PORT_SEL_C;
		3128	break;
		3129	case PCH_DP_D:
		3130	temp \|= TRANS_DP_PORT_SEL_D;
		3131	break;
		3132	default:
3243	Serge	3133	BUG();
2327	Serge	3134	}
		3135
		3136	I915_WRITE(reg, temp);
		3137	}
		3138
3243	Serge	3139	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3140	}
		3141
3243	Serge	3142	static void lpt_pch_enable(struct drm_crtc *crtc)
		3143	{
		3144	struct drm_device *dev = crtc->dev;
		3145	struct drm_i915_private *dev_priv = dev->dev_private;
		3146	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3147	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3148
4104	Serge	3149	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	3150
		3151	lpt_program_iclkip(crtc);
		3152
		3153	/* Set transcoder timing. */
4104	Serge	3154	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	3155
		3156	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3157	}
		3158
4104	Serge	3159	static void intel_put_shared_dpll(struct intel_crtc *crtc)
3031	serge	3160	{
4104	Serge	3161	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031	serge	3162
		3163	if (pll == NULL)
		3164	return;
		3165
		3166	if (pll->refcount == 0) {
4104	Serge	3167	WARN(1, "bad %s refcount\n", pll->name);
3031	serge	3168	return;
		3169	}
		3170
4104	Serge	3171	if (--pll->refcount == 0) {
		3172	WARN_ON(pll->on);
		3173	WARN_ON(pll->active);
		3174	}
		3175
		3176	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3031	serge	3177	}
		3178
4104	Serge	3179	static struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc)
3031	serge	3180	{
4104	Serge	3181	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3182	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		3183	enum intel_dpll_id i;
3031	serge	3184
		3185	if (pll) {
4104	Serge	3186	DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
		3187	crtc->base.base.id, pll->name);
		3188	intel_put_shared_dpll(crtc);
3031	serge	3189	}
		3190
		3191	if (HAS_PCH_IBX(dev_priv->dev)) {
		3192	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	3193	i = (enum intel_dpll_id) crtc->pipe;
		3194	pll = &dev_priv->shared_dplls[i];
3031	serge	3195
4104	Serge	3196	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		3197	crtc->base.base.id, pll->name);
3031	serge	3198
		3199	goto found;
		3200	}
		3201
4104	Serge	3202	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3203	pll = &dev_priv->shared_dplls[i];
3031	serge	3204
		3205	/* Only want to check enabled timings first */
		3206	if (pll->refcount == 0)
		3207	continue;
		3208
4104	Serge	3209	if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
		3210	sizeof(pll->hw_state)) == 0) {
		3211	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
		3212	crtc->base.base.id,
		3213	pll->name, pll->refcount, pll->active);
3031	serge	3214
		3215	goto found;
		3216	}
		3217	}
		3218
		3219	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	3220	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3221	pll = &dev_priv->shared_dplls[i];
3031	serge	3222	if (pll->refcount == 0) {
4104	Serge	3223	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		3224	crtc->base.base.id, pll->name);
3031	serge	3225	goto found;
		3226	}
		3227	}
		3228
		3229	return NULL;
		3230
		3231	found:
4104	Serge	3232	crtc->config.shared_dpll = i;
		3233	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		3234	pipe_name(crtc->pipe));
		3235
		3236	if (pll->active == 0) {
		3237	memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
		3238	sizeof(pll->hw_state));
		3239
		3240	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		3241	WARN_ON(pll->on);
		3242	assert_shared_dpll_disabled(dev_priv, pll);
		3243
		3244	pll->mode_set(dev_priv, pll);
		3245	}
3031	serge	3246	pll->refcount++;
		3247
		3248	return pll;
		3249	}
		3250
4104	Serge	3251	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
2342	Serge	3252	{
		3253	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3254	int dslreg = PIPEDSL(pipe);
2342	Serge	3255	u32 temp;
		3256
		3257	temp = I915_READ(dslreg);
		3258	udelay(500);
		3259	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3260	if (wait_for(I915_READ(dslreg) != temp, 5))
4104	Serge	3261	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
2342	Serge	3262	}
		3263	}
		3264
4104	Serge	3265	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		3266	{
		3267	struct drm_device *dev = crtc->base.dev;
		3268	struct drm_i915_private *dev_priv = dev->dev_private;
		3269	int pipe = crtc->pipe;
		3270
		3271	if (crtc->config.pch_pfit.enabled) {
		3272	/* Force use of hard-coded filter coefficients
		3273	* as some pre-programmed values are broken,
		3274	* e.g. x201.
		3275	*/
		3276	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		3277	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3278	PF_PIPE_SEL_IVB(pipe));
		3279	else
		3280	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3281	I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		3282	I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
		3283	}
		3284	}
		3285
		3286	static void intel_enable_planes(struct drm_crtc *crtc)
		3287	{
		3288	struct drm_device *dev = crtc->dev;
		3289	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3290	struct intel_plane *intel_plane;
		3291
		3292	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3293	if (intel_plane->pipe == pipe)
		3294	intel_plane_restore(&intel_plane->base);
		3295	}
		3296
		3297	static void intel_disable_planes(struct drm_crtc *crtc)
		3298	{
		3299	struct drm_device *dev = crtc->dev;
		3300	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3301	struct intel_plane *intel_plane;
		3302
		3303	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3304	if (intel_plane->pipe == pipe)
		3305	intel_plane_disable(&intel_plane->base);
		3306	}
		3307
2327	Serge	3308	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3309	{
		3310	struct drm_device *dev = crtc->dev;
		3311	struct drm_i915_private *dev_priv = dev->dev_private;
		3312	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3313	struct intel_encoder *encoder;
2327	Serge	3314	int pipe = intel_crtc->pipe;
		3315	int plane = intel_crtc->plane;
		3316
3031	serge	3317	WARN_ON(!crtc->enabled);
		3318
2327	Serge	3319	if (intel_crtc->active)
		3320	return;
		3321
		3322	intel_crtc->active = true;
4104	Serge	3323
		3324	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3325	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
		3326
2327	Serge	3327	intel_update_watermarks(dev);
		3328
4104	Serge	3329	for_each_encoder_on_crtc(dev, crtc, encoder)
		3330	if (encoder->pre_enable)
		3331	encoder->pre_enable(encoder);
2327	Serge	3332
3746	Serge	3333	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3334	/* Note: FDI PLL enabling _must_ be done before we enable the
		3335	* cpu pipes, hence this is separate from all the other fdi/pch
		3336	* enabling. */
3031	serge	3337	ironlake_fdi_pll_enable(intel_crtc);
		3338	} else {
		3339	assert_fdi_tx_disabled(dev_priv, pipe);
		3340	assert_fdi_rx_disabled(dev_priv, pipe);
		3341	}
2327	Serge	3342
4104	Serge	3343	ironlake_pfit_enable(intel_crtc);
3031	serge	3344
2327	Serge	3345	/*
		3346	* On ILK+ LUT must be loaded before the pipe is running but with
		3347	* clocks enabled
		3348	*/
		3349	intel_crtc_load_lut(crtc);
		3350
3746	Serge	3351	intel_enable_pipe(dev_priv, pipe,
		3352	intel_crtc->config.has_pch_encoder);
2327	Serge	3353	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3354	intel_enable_planes(crtc);
		3355	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3356
3746	Serge	3357	if (intel_crtc->config.has_pch_encoder)
2327	Serge	3358	ironlake_pch_enable(crtc);
		3359
		3360	mutex_lock(&dev->struct_mutex);
		3361	intel_update_fbc(dev);
		3362	mutex_unlock(&dev->struct_mutex);
		3363
3031	serge	3364	for_each_encoder_on_crtc(dev, crtc, encoder)
		3365	encoder->enable(encoder);
		3366
		3367	if (HAS_PCH_CPT(dev))
4104	Serge	3368	cpt_verify_modeset(dev, intel_crtc->pipe);
3031	serge	3369
		3370	/*
		3371	* There seems to be a race in PCH platform hw (at least on some
		3372	* outputs) where an enabled pipe still completes any pageflip right
		3373	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3374	* as the first vblank happend, everything works as expected. Hence just
		3375	* wait for one vblank before returning to avoid strange things
		3376	* happening.
		3377	*/
		3378	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3379	}
		3380
4104	Serge	3381	/* IPS only exists on ULT machines and is tied to pipe A. */
		3382	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		3383	{
		3384	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		3385	}
		3386
		3387	static void hsw_enable_ips(struct intel_crtc *crtc)
		3388	{
		3389	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3390
		3391	if (!crtc->config.ips_enabled)
		3392	return;
		3393
		3394	/* We can only enable IPS after we enable a plane and wait for a vblank.
		3395	* We guarantee that the plane is enabled by calling intel_enable_ips
		3396	* only after intel_enable_plane. And intel_enable_plane already waits
		3397	* for a vblank, so all we need to do here is to enable the IPS bit. */
		3398	assert_plane_enabled(dev_priv, crtc->plane);
		3399	I915_WRITE(IPS_CTL, IPS_ENABLE);
		3400	}
		3401
		3402	static void hsw_disable_ips(struct intel_crtc *crtc)
		3403	{
		3404	struct drm_device *dev = crtc->base.dev;
		3405	struct drm_i915_private *dev_priv = dev->dev_private;
		3406
		3407	if (!crtc->config.ips_enabled)
		3408	return;
		3409
		3410	assert_plane_enabled(dev_priv, crtc->plane);
		3411	I915_WRITE(IPS_CTL, 0);
		3412
		3413	/* We need to wait for a vblank before we can disable the plane. */
		3414	intel_wait_for_vblank(dev, crtc->pipe);
		3415	}
		3416
3243	Serge	3417	static void haswell_crtc_enable(struct drm_crtc *crtc)
		3418	{
		3419	struct drm_device *dev = crtc->dev;
		3420	struct drm_i915_private *dev_priv = dev->dev_private;
		3421	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3422	struct intel_encoder *encoder;
		3423	int pipe = intel_crtc->pipe;
		3424	int plane = intel_crtc->plane;
		3425
		3426	WARN_ON(!crtc->enabled);
		3427
		3428	if (intel_crtc->active)
		3429	return;
		3430
		3431	intel_crtc->active = true;
4104	Serge	3432
		3433	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3434	if (intel_crtc->config.has_pch_encoder)
		3435	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
		3436
3243	Serge	3437	intel_update_watermarks(dev);
		3438
3746	Serge	3439	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3440	dev_priv->display.fdi_link_train(crtc);
		3441
		3442	for_each_encoder_on_crtc(dev, crtc, encoder)
		3443	if (encoder->pre_enable)
		3444	encoder->pre_enable(encoder);
		3445
		3446	intel_ddi_enable_pipe_clock(intel_crtc);
		3447
4104	Serge	3448	ironlake_pfit_enable(intel_crtc);
3243	Serge	3449
		3450	/*
		3451	* On ILK+ LUT must be loaded before the pipe is running but with
		3452	* clocks enabled
		3453	*/
		3454	intel_crtc_load_lut(crtc);
		3455
		3456	intel_ddi_set_pipe_settings(crtc);
3746	Serge	3457	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	3458
3746	Serge	3459	intel_enable_pipe(dev_priv, pipe,
		3460	intel_crtc->config.has_pch_encoder);
3243	Serge	3461	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3462	intel_enable_planes(crtc);
		3463	// intel_crtc_update_cursor(crtc, true);
3243	Serge	3464
4104	Serge	3465	hsw_enable_ips(intel_crtc);
		3466
3746	Serge	3467	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3468	lpt_pch_enable(crtc);
		3469
		3470	mutex_lock(&dev->struct_mutex);
		3471	intel_update_fbc(dev);
		3472	mutex_unlock(&dev->struct_mutex);
		3473
		3474	for_each_encoder_on_crtc(dev, crtc, encoder)
		3475	encoder->enable(encoder);
		3476
		3477	/*
		3478	* There seems to be a race in PCH platform hw (at least on some
		3479	* outputs) where an enabled pipe still completes any pageflip right
		3480	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3481	* as the first vblank happend, everything works as expected. Hence just
		3482	* wait for one vblank before returning to avoid strange things
		3483	* happening.
		3484	*/
		3485	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3486	}
		3487
4104	Serge	3488	static void ironlake_pfit_disable(struct intel_crtc *crtc)
		3489	{
		3490	struct drm_device *dev = crtc->base.dev;
		3491	struct drm_i915_private *dev_priv = dev->dev_private;
		3492	int pipe = crtc->pipe;
		3493
		3494	/* To avoid upsetting the power well on haswell only disable the pfit if
		3495	* it's in use. The hw state code will make sure we get this right. */
		3496	if (crtc->config.pch_pfit.enabled) {
		3497	I915_WRITE(PF_CTL(pipe), 0);
		3498	I915_WRITE(PF_WIN_POS(pipe), 0);
		3499	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3500	}
		3501	}
		3502
2327	Serge	3503	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3504	{
		3505	struct drm_device *dev = crtc->dev;
		3506	struct drm_i915_private *dev_priv = dev->dev_private;
		3507	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3508	struct intel_encoder *encoder;
2327	Serge	3509	int pipe = intel_crtc->pipe;
		3510	int plane = intel_crtc->plane;
		3511	u32 reg, temp;
		3512
3031	serge	3513
2327	Serge	3514	if (!intel_crtc->active)
		3515	return;
		3516
3031	serge	3517	for_each_encoder_on_crtc(dev, crtc, encoder)
		3518	encoder->disable(encoder);
2336	Serge	3519
3031	serge	3520	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3521	// drm_vblank_off(dev, pipe);
		3522
4104	Serge	3523	if (dev_priv->fbc.plane == plane)
		3524	intel_disable_fbc(dev);
		3525
		3526	// intel_crtc_update_cursor(crtc, false);
		3527	intel_disable_planes(crtc);
2327	Serge	3528	intel_disable_plane(dev_priv, plane, pipe);
		3529
4104	Serge	3530	if (intel_crtc->config.has_pch_encoder)
		3531	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
2327	Serge	3532
		3533	intel_disable_pipe(dev_priv, pipe);
		3534
4104	Serge	3535	ironlake_pfit_disable(intel_crtc);
2327	Serge	3536
3031	serge	3537	for_each_encoder_on_crtc(dev, crtc, encoder)
		3538	if (encoder->post_disable)
		3539	encoder->post_disable(encoder);
		3540
4104	Serge	3541	if (intel_crtc->config.has_pch_encoder) {
2327	Serge	3542	ironlake_fdi_disable(crtc);
		3543
3243	Serge	3544	ironlake_disable_pch_transcoder(dev_priv, pipe);
4104	Serge	3545	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
2327	Serge	3546
		3547	if (HAS_PCH_CPT(dev)) {
		3548	/* disable TRANS_DP_CTL */
		3549	reg = TRANS_DP_CTL(pipe);
		3550	temp = I915_READ(reg);
4104	Serge	3551	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		3552	TRANS_DP_PORT_SEL_MASK);
2327	Serge	3553	temp \|= TRANS_DP_PORT_SEL_NONE;
		3554	I915_WRITE(reg, temp);
		3555
		3556	/* disable DPLL_SEL */
		3557	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3558	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
2327	Serge	3559	I915_WRITE(PCH_DPLL_SEL, temp);
		3560	}
		3561
		3562	/* disable PCH DPLL */
4104	Serge	3563	intel_disable_shared_dpll(intel_crtc);
2327	Serge	3564
3031	serge	3565	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	3566	}
2327	Serge	3567
		3568	intel_crtc->active = false;
		3569	intel_update_watermarks(dev);
		3570
		3571	mutex_lock(&dev->struct_mutex);
		3572	intel_update_fbc(dev);
		3573	mutex_unlock(&dev->struct_mutex);
		3574	}
		3575
3243	Serge	3576	static void haswell_crtc_disable(struct drm_crtc *crtc)
		3577	{
		3578	struct drm_device *dev = crtc->dev;
		3579	struct drm_i915_private *dev_priv = dev->dev_private;
		3580	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3581	struct intel_encoder *encoder;
		3582	int pipe = intel_crtc->pipe;
		3583	int plane = intel_crtc->plane;
3746	Serge	3584	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3585
		3586	if (!intel_crtc->active)
		3587	return;
		3588
		3589	for_each_encoder_on_crtc(dev, crtc, encoder)
		3590	encoder->disable(encoder);
		3591
		3592
4104	Serge	3593	/* FBC must be disabled before disabling the plane on HSW. */
		3594	if (dev_priv->fbc.plane == plane)
		3595	intel_disable_fbc(dev);
		3596
		3597	hsw_disable_ips(intel_crtc);
		3598
		3599	// intel_crtc_update_cursor(crtc, false);
		3600	intel_disable_planes(crtc);
3243	Serge	3601	intel_disable_plane(dev_priv, plane, pipe);
		3602
4104	Serge	3603	if (intel_crtc->config.has_pch_encoder)
		3604	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3243	Serge	3605	intel_disable_pipe(dev_priv, pipe);
		3606
		3607	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		3608
4104	Serge	3609	ironlake_pfit_disable(intel_crtc);
3243	Serge	3610
		3611	intel_ddi_disable_pipe_clock(intel_crtc);
		3612
		3613	for_each_encoder_on_crtc(dev, crtc, encoder)
		3614	if (encoder->post_disable)
		3615	encoder->post_disable(encoder);
		3616
3746	Serge	3617	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3618	lpt_disable_pch_transcoder(dev_priv);
4104	Serge	3619	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3243	Serge	3620	intel_ddi_fdi_disable(crtc);
		3621	}
		3622
		3623	intel_crtc->active = false;
		3624	intel_update_watermarks(dev);
		3625
		3626	mutex_lock(&dev->struct_mutex);
		3627	intel_update_fbc(dev);
		3628	mutex_unlock(&dev->struct_mutex);
		3629	}
		3630
3031	serge	3631	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3632	{
		3633	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	3634	intel_put_shared_dpll(intel_crtc);
2327	Serge	3635	}
		3636
3243	Serge	3637	static void haswell_crtc_off(struct drm_crtc *crtc)
		3638	{
		3639	intel_ddi_put_crtc_pll(crtc);
		3640	}
		3641
2327	Serge	3642	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3643	{
		3644	if (!enable && intel_crtc->overlay) {
		3645	struct drm_device *dev = intel_crtc->base.dev;
		3646	struct drm_i915_private *dev_priv = dev->dev_private;
		3647
		3648	mutex_lock(&dev->struct_mutex);
		3649	dev_priv->mm.interruptible = false;
		3650	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3651	dev_priv->mm.interruptible = true;
		3652	mutex_unlock(&dev->struct_mutex);
		3653	}
		3654
		3655	/* Let userspace switch the overlay on again. In most cases userspace
		3656	* has to recompute where to put it anyway.
		3657	*/
		3658	}
		3659
3480	Serge	3660	/**
		3661	* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
		3662	* cursor plane briefly if not already running after enabling the display
		3663	* plane.
		3664	* This workaround avoids occasional blank screens when self refresh is
		3665	* enabled.
		3666	*/
		3667	static void
		3668	g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
		3669	{
		3670	u32 cntl = I915_READ(CURCNTR(pipe));
		3671
		3672	if ((cntl & CURSOR_MODE) == 0) {
		3673	u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
		3674
		3675	I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		3676	I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		3677	intel_wait_for_vblank(dev_priv->dev, pipe);
		3678	I915_WRITE(CURCNTR(pipe), cntl);
		3679	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		3680	I915_WRITE(FW_BLC_SELF, fw_bcl_self);
		3681	}
		3682	}
		3683
4104	Serge	3684	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		3685	{
		3686	struct drm_device *dev = crtc->base.dev;
		3687	struct drm_i915_private *dev_priv = dev->dev_private;
		3688	struct intel_crtc_config *pipe_config = &crtc->config;
		3689
		3690	if (!crtc->config.gmch_pfit.control)
		3691	return;
		3692
		3693	/*
		3694	* The panel fitter should only be adjusted whilst the pipe is disabled,
		3695	* according to register description and PRM.
		3696	*/
		3697	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		3698	assert_pipe_disabled(dev_priv, crtc->pipe);
		3699
		3700	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		3701	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		3702
		3703	/* Border color in case we don't scale up to the full screen. Black by
		3704	* default, change to something else for debugging. */
		3705	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		3706	}
		3707
		3708	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		3709	{
		3710	struct drm_device *dev = crtc->dev;
		3711	struct drm_i915_private *dev_priv = dev->dev_private;
		3712	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3713	struct intel_encoder *encoder;
		3714	int pipe = intel_crtc->pipe;
		3715	int plane = intel_crtc->plane;
		3716
		3717	WARN_ON(!crtc->enabled);
		3718
		3719	if (intel_crtc->active)
		3720	return;
		3721
		3722	intel_crtc->active = true;
		3723	intel_update_watermarks(dev);
		3724
		3725	for_each_encoder_on_crtc(dev, crtc, encoder)
		3726	if (encoder->pre_pll_enable)
		3727	encoder->pre_pll_enable(encoder);
		3728
		3729	vlv_enable_pll(intel_crtc);
		3730
		3731	for_each_encoder_on_crtc(dev, crtc, encoder)
		3732	if (encoder->pre_enable)
		3733	encoder->pre_enable(encoder);
		3734
		3735	i9xx_pfit_enable(intel_crtc);
		3736
		3737	intel_crtc_load_lut(crtc);
		3738
		3739	intel_enable_pipe(dev_priv, pipe, false);
		3740	intel_enable_plane(dev_priv, plane, pipe);
		3741	intel_enable_planes(crtc);
		3742	// intel_crtc_update_cursor(crtc, true);
		3743
		3744	intel_update_fbc(dev);
		3745
		3746	for_each_encoder_on_crtc(dev, crtc, encoder)
		3747	encoder->enable(encoder);
		3748	}
		3749
2327	Serge	3750	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3751	{
		3752	struct drm_device *dev = crtc->dev;
		3753	struct drm_i915_private *dev_priv = dev->dev_private;
		3754	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3755	struct intel_encoder *encoder;
2327	Serge	3756	int pipe = intel_crtc->pipe;
		3757	int plane = intel_crtc->plane;
		3758
3031	serge	3759	WARN_ON(!crtc->enabled);
		3760
2327	Serge	3761	if (intel_crtc->active)
		3762	return;
		3763
		3764	intel_crtc->active = true;
		3765	intel_update_watermarks(dev);
		3766
3480	Serge	3767	for_each_encoder_on_crtc(dev, crtc, encoder)
		3768	if (encoder->pre_enable)
		3769	encoder->pre_enable(encoder);
		3770
4104	Serge	3771	i9xx_enable_pll(intel_crtc);
		3772
		3773	i9xx_pfit_enable(intel_crtc);
		3774
		3775	intel_crtc_load_lut(crtc);
		3776
2327	Serge	3777	intel_enable_pipe(dev_priv, pipe, false);
		3778	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3779	intel_enable_planes(crtc);
		3780	/* The fixup needs to happen before cursor is enabled */
3480	Serge	3781	if (IS_G4X(dev))
		3782	g4x_fixup_plane(dev_priv, pipe);
4104	Serge	3783	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3784
		3785	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3786	intel_crtc_dpms_overlay(intel_crtc, true);
3031	serge	3787
4104	Serge	3788	intel_update_fbc(dev);
		3789
3031	serge	3790	for_each_encoder_on_crtc(dev, crtc, encoder)
		3791	encoder->enable(encoder);
2327	Serge	3792	}
		3793
3746	Serge	3794	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		3795	{
		3796	struct drm_device *dev = crtc->base.dev;
		3797	struct drm_i915_private *dev_priv = dev->dev_private;
		3798
4104	Serge	3799	if (!crtc->config.gmch_pfit.control)
		3800	return;
		3801
3746	Serge	3802	assert_pipe_disabled(dev_priv, crtc->pipe);
		3803
4104	Serge	3804	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		3805	I915_READ(PFIT_CONTROL));
3746	Serge	3806	I915_WRITE(PFIT_CONTROL, 0);
		3807	}
		3808
2327	Serge	3809	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3810	{
		3811	struct drm_device *dev = crtc->dev;
		3812	struct drm_i915_private *dev_priv = dev->dev_private;
		3813	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3814	struct intel_encoder *encoder;
2327	Serge	3815	int pipe = intel_crtc->pipe;
		3816	int plane = intel_crtc->plane;
		3817
		3818	if (!intel_crtc->active)
		3819	return;
		3820
3031	serge	3821	for_each_encoder_on_crtc(dev, crtc, encoder)
		3822	encoder->disable(encoder);
		3823
2327	Serge	3824	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3825	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3826	// drm_vblank_off(dev, pipe);
		3827
4104	Serge	3828	if (dev_priv->fbc.plane == plane)
2327	Serge	3829	intel_disable_fbc(dev);
		3830
4104	Serge	3831	intel_crtc_dpms_overlay(intel_crtc, false);
		3832	// intel_crtc_update_cursor(crtc, false);
		3833	intel_disable_planes(crtc);
2327	Serge	3834	intel_disable_plane(dev_priv, plane, pipe);
4104	Serge	3835
2327	Serge	3836	intel_disable_pipe(dev_priv, pipe);
3480	Serge	3837
3746	Serge	3838	i9xx_pfit_disable(intel_crtc);
3480	Serge	3839
4104	Serge	3840	for_each_encoder_on_crtc(dev, crtc, encoder)
		3841	if (encoder->post_disable)
		3842	encoder->post_disable(encoder);
2327	Serge	3843
4104	Serge	3844	i9xx_disable_pll(dev_priv, pipe);
		3845
2327	Serge	3846	intel_crtc->active = false;
		3847	intel_update_fbc(dev);
		3848	intel_update_watermarks(dev);
		3849	}
		3850
3031	serge	3851	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3852	{
		3853	}
		3854
3031	serge	3855	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3856	bool enabled)
2330	Serge	3857	{
		3858	struct drm_device *dev = crtc->dev;
		3859	struct drm_i915_master_private *master_priv;
		3860	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3861	int pipe = intel_crtc->pipe;
2327	Serge	3862
		3863
2340	Serge	3864	#if 0
2330	Serge	3865	if (!dev->primary->master)
		3866	return;
2327	Serge	3867
2330	Serge	3868	master_priv = dev->primary->master->driver_priv;
		3869	if (!master_priv->sarea_priv)
		3870	return;
2327	Serge	3871
2330	Serge	3872	switch (pipe) {
		3873	case 0:
		3874	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3875	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3876	break;
		3877	case 1:
		3878	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3879	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3880	break;
		3881	default:
		3882	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3883	break;
		3884	}
2340	Serge	3885	#endif
		3886
2330	Serge	3887	}
2327	Serge	3888
3031	serge	3889	/**
		3890	* Sets the power management mode of the pipe and plane.
		3891	*/
		3892	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3893	{
		3894	struct drm_device *dev = crtc->dev;
		3895	struct drm_i915_private *dev_priv = dev->dev_private;
		3896	struct intel_encoder *intel_encoder;
		3897	bool enable = false;
		3898
		3899	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3900	enable \|= intel_encoder->connectors_active;
		3901
		3902	if (enable)
		3903	dev_priv->display.crtc_enable(crtc);
		3904	else
		3905	dev_priv->display.crtc_disable(crtc);
		3906
		3907	intel_crtc_update_sarea(crtc, enable);
		3908	}
		3909
2330	Serge	3910	static void intel_crtc_disable(struct drm_crtc *crtc)
		3911	{
		3912	struct drm_device *dev = crtc->dev;
3031	serge	3913	struct drm_connector *connector;
		3914	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3915	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	3916
3031	serge	3917	/* crtc should still be enabled when we disable it. */
		3918	WARN_ON(!crtc->enabled);
2327	Serge	3919
4104	Serge	3920	dev_priv->display.crtc_disable(crtc);
3480	Serge	3921	intel_crtc->eld_vld = false;
3031	serge	3922	intel_crtc_update_sarea(crtc, false);
		3923	dev_priv->display.off(crtc);
		3924
		3925	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3926	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3927
4280	Serge	3928	if (crtc->fb) {
		3929	mutex_lock(&dev->struct_mutex);
		3930	intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3931	mutex_unlock(&dev->struct_mutex);
		3932	crtc->fb = NULL;
		3933	}
3031	serge	3934
		3935	/* Update computed state. */
		3936	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3937	if (!connector->encoder \|\| !connector->encoder->crtc)
		3938	continue;
		3939
		3940	if (connector->encoder->crtc != crtc)
		3941	continue;
		3942
		3943	connector->dpms = DRM_MODE_DPMS_OFF;
		3944	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3945	}
		3946	}
2327	Serge	3947
3031	serge	3948	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3949	{
3031	serge	3950	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3951
		3952	drm_encoder_cleanup(encoder);
		3953	kfree(intel_encoder);
2330	Serge	3954	}
2327	Serge	3955
4104	Serge	3956	/* Simple dpms helper for encoders with just one connector, no cloning and only
3031	serge	3957	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3958	* state of the entire output pipe. */
4104	Serge	3959	static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3960	{
3031	serge	3961	if (mode == DRM_MODE_DPMS_ON) {
		3962	encoder->connectors_active = true;
		3963
		3964	intel_crtc_update_dpms(encoder->base.crtc);
		3965	} else {
		3966	encoder->connectors_active = false;
		3967
		3968	intel_crtc_update_dpms(encoder->base.crtc);
		3969	}
2330	Serge	3970	}
2327	Serge	3971
3031	serge	3972	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3973	* internal consistency). */
		3974	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3975	{
3031	serge	3976	if (connector->get_hw_state(connector)) {
		3977	struct intel_encoder *encoder = connector->encoder;
		3978	struct drm_crtc *crtc;
		3979	bool encoder_enabled;
		3980	enum pipe pipe;
		3981
		3982	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3983	connector->base.base.id,
		3984	drm_get_connector_name(&connector->base));
		3985
		3986	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3987	"wrong connector dpms state\n");
		3988	WARN(connector->base.encoder != &encoder->base,
		3989	"active connector not linked to encoder\n");
		3990	WARN(!encoder->connectors_active,
		3991	"encoder->connectors_active not set\n");
		3992
		3993	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3994	WARN(!encoder_enabled, "encoder not enabled\n");
		3995	if (WARN_ON(!encoder->base.crtc))
		3996	return;
		3997
		3998	crtc = encoder->base.crtc;
		3999
		4000	WARN(!crtc->enabled, "crtc not enabled\n");
		4001	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		4002	WARN(pipe != to_intel_crtc(crtc)->pipe,
		4003	"encoder active on the wrong pipe\n");
		4004	}
2330	Serge	4005	}
2327	Serge	4006
3031	serge	4007	/* Even simpler default implementation, if there's really no special case to
		4008	* consider. */
		4009	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	4010	{
3031	serge	4011	/* All the simple cases only support two dpms states. */
		4012	if (mode != DRM_MODE_DPMS_ON)
		4013	mode = DRM_MODE_DPMS_OFF;
2342	Serge	4014
3031	serge	4015	if (mode == connector->dpms)
		4016	return;
		4017
		4018	connector->dpms = mode;
		4019
		4020	/* Only need to change hw state when actually enabled */
4104	Serge	4021	if (connector->encoder)
		4022	intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3031	serge	4023
		4024	intel_modeset_check_state(connector->dev);
2330	Serge	4025	}
2327	Serge	4026
3031	serge	4027	/* Simple connector->get_hw_state implementation for encoders that support only
		4028	* one connector and no cloning and hence the encoder state determines the state
		4029	* of the connector. */
		4030	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	4031	{
3031	serge	4032	enum pipe pipe = 0;
		4033	struct intel_encoder *encoder = connector->encoder;
2330	Serge	4034
3031	serge	4035	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	4036	}
		4037
4104	Serge	4038	static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		4039	struct intel_crtc_config *pipe_config)
		4040	{
		4041	struct drm_i915_private *dev_priv = dev->dev_private;
		4042	struct intel_crtc *pipe_B_crtc =
		4043	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		4044
		4045	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		4046	pipe_name(pipe), pipe_config->fdi_lanes);
		4047	if (pipe_config->fdi_lanes > 4) {
		4048	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		4049	pipe_name(pipe), pipe_config->fdi_lanes);
		4050	return false;
		4051	}
		4052
		4053	if (IS_HASWELL(dev)) {
		4054	if (pipe_config->fdi_lanes > 2) {
		4055	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		4056	pipe_config->fdi_lanes);
		4057	return false;
		4058	} else {
		4059	return true;
		4060	}
		4061	}
		4062
		4063	if (INTEL_INFO(dev)->num_pipes == 2)
		4064	return true;
		4065
		4066	/* Ivybridge 3 pipe is really complicated */
		4067	switch (pipe) {
		4068	case PIPE_A:
		4069	return true;
		4070	case PIPE_B:
		4071	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		4072	pipe_config->fdi_lanes > 2) {
		4073	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4074	pipe_name(pipe), pipe_config->fdi_lanes);
		4075	return false;
		4076	}
		4077	return true;
		4078	case PIPE_C:
		4079	if (!pipe_has_enabled_pch(pipe_B_crtc) \|\|
		4080	pipe_B_crtc->config.fdi_lanes <= 2) {
		4081	if (pipe_config->fdi_lanes > 2) {
		4082	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4083	pipe_name(pipe), pipe_config->fdi_lanes);
		4084	return false;
		4085	}
		4086	} else {
		4087	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		4088	return false;
		4089	}
		4090	return true;
		4091	default:
		4092	BUG();
		4093	}
		4094	}
		4095
		4096	#define RETRY 1
		4097	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3746	Serge	4098	struct intel_crtc_config *pipe_config)
2330	Serge	4099	{
4104	Serge	4100	struct drm_device *dev = intel_crtc->base.dev;
3746	Serge	4101	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104	Serge	4102	int lane, link_bw, fdi_dotclock;
		4103	bool setup_ok, needs_recompute = false;
2330	Serge	4104
4104	Serge	4105	retry:
		4106	/* FDI is a binary signal running at ~2.7GHz, encoding
		4107	* each output octet as 10 bits. The actual frequency
		4108	* is stored as a divider into a 100MHz clock, and the
		4109	* mode pixel clock is stored in units of 1KHz.
		4110	* Hence the bw of each lane in terms of the mode signal
		4111	* is:
		4112	*/
		4113	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4114
		4115	fdi_dotclock = adjusted_mode->clock;
		4116	fdi_dotclock /= pipe_config->pixel_multiplier;
		4117
		4118	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		4119	pipe_config->pipe_bpp);
		4120
		4121	pipe_config->fdi_lanes = lane;
		4122
		4123	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		4124	link_bw, &pipe_config->fdi_m_n);
		4125
		4126	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		4127	intel_crtc->pipe, pipe_config);
		4128	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		4129	pipe_config->pipe_bpp -= 2*3;
		4130	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		4131	pipe_config->pipe_bpp);
		4132	needs_recompute = true;
		4133	pipe_config->bw_constrained = true;
		4134
		4135	goto retry;
		4136	}
		4137
		4138	if (needs_recompute)
		4139	return RETRY;
		4140
		4141	return setup_ok ? 0 : -EINVAL;
		4142	}
		4143
		4144	static void hsw_compute_ips_config(struct intel_crtc *crtc,
		4145	struct intel_crtc_config *pipe_config)
		4146	{
		4147	pipe_config->ips_enabled = i915_enable_ips &&
		4148	hsw_crtc_supports_ips(crtc) &&
		4149	pipe_config->pipe_bpp <= 24;
		4150	}
		4151
		4152	static int intel_crtc_compute_config(struct intel_crtc *crtc,
		4153	struct intel_crtc_config *pipe_config)
		4154	{
		4155	struct drm_device *dev = crtc->base.dev;
		4156	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		4157
2330	Serge	4158	if (HAS_PCH_SPLIT(dev)) {
		4159	/* FDI link clock is fixed at 2.7G */
3746	Serge	4160	if (pipe_config->requested_mode.clock * 3
		4161	> IRONLAKE_FDI_FREQ * 4)
4104	Serge	4162	return -EINVAL;
2330	Serge	4163	}
		4164
4104	Serge	4165	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		4166	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	4167	*/
		4168	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		4169	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104	Serge	4170	return -EINVAL;
3031	serge	4171
3746	Serge	4172	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		4173	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		4174	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		4175	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		4176	* for lvds. */
		4177	pipe_config->pipe_bpp = 8*3;
		4178	}
		4179
4104	Serge	4180	if (HAS_IPS(dev))
		4181	hsw_compute_ips_config(crtc, pipe_config);
		4182
		4183	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
		4184	* clock survives for now. */
		4185	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		4186	pipe_config->shared_dpll = crtc->config.shared_dpll;
		4187
		4188	if (pipe_config->has_pch_encoder)
		4189	return ironlake_fdi_compute_config(crtc, pipe_config);
		4190
		4191	return 0;
2330	Serge	4192	}
		4193
3031	serge	4194	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		4195	{
		4196	return 400000; /* FIXME */
		4197	}
		4198
2327	Serge	4199	static int i945_get_display_clock_speed(struct drm_device *dev)
		4200	{
		4201	return 400000;
		4202	}
		4203
		4204	static int i915_get_display_clock_speed(struct drm_device *dev)
		4205	{
		4206	return 333000;
		4207	}
		4208
		4209	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		4210	{
		4211	return 200000;
		4212	}
		4213
4104	Serge	4214	static int pnv_get_display_clock_speed(struct drm_device *dev)
		4215	{
		4216	u16 gcfgc = 0;
		4217
		4218	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4219
		4220	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4221	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		4222	return 267000;
		4223	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		4224	return 333000;
		4225	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		4226	return 444000;
		4227	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		4228	return 200000;
		4229	default:
		4230	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		4231	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		4232	return 133000;
		4233	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		4234	return 167000;
		4235	}
		4236	}
		4237
2327	Serge	4238	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		4239	{
		4240	u16 gcfgc = 0;
		4241
		4242	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4243
		4244	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		4245	return 133000;
		4246	else {
		4247	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4248	case GC_DISPLAY_CLOCK_333_MHZ:
		4249	return 333000;
		4250	default:
		4251	case GC_DISPLAY_CLOCK_190_200_MHZ:
		4252	return 190000;
		4253	}
		4254	}
		4255	}
		4256
		4257	static int i865_get_display_clock_speed(struct drm_device *dev)
		4258	{
		4259	return 266000;
		4260	}
		4261
		4262	static int i855_get_display_clock_speed(struct drm_device *dev)
		4263	{
		4264	u16 hpllcc = 0;
		4265	/* Assume that the hardware is in the high speed state. This
		4266	* should be the default.
		4267	*/
		4268	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		4269	case GC_CLOCK_133_200:
		4270	case GC_CLOCK_100_200:
		4271	return 200000;
		4272	case GC_CLOCK_166_250:
		4273	return 250000;
		4274	case GC_CLOCK_100_133:
		4275	return 133000;
		4276	}
		4277
		4278	/* Shouldn't happen */
		4279	return 0;
		4280	}
		4281
		4282	static int i830_get_display_clock_speed(struct drm_device *dev)
		4283	{
		4284	return 133000;
		4285	}
		4286
		4287	static void
3746	Serge	4288	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	4289	{
3746	Serge	4290	while (*num > DATA_LINK_M_N_MASK \|\|
		4291	*den > DATA_LINK_M_N_MASK) {
2327	Serge	4292	*num >>= 1;
		4293	*den >>= 1;
		4294	}
		4295	}
		4296
3746	Serge	4297	static void compute_m_n(unsigned int m, unsigned int n,
		4298	uint32_t ret_m, uint32_t ret_n)
		4299	{
		4300	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		4301	ret_m = div_u64((uint64_t) m *ret_n, n);
		4302	intel_reduce_m_n_ratio(ret_m, ret_n);
		4303	}
		4304
3480	Serge	4305	void
		4306	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		4307	int pixel_clock, int link_clock,
		4308	struct intel_link_m_n *m_n)
2327	Serge	4309	{
3480	Serge	4310	m_n->tu = 64;
3746	Serge	4311
		4312	compute_m_n(bits_per_pixel * pixel_clock,
		4313	link_clock * nlanes * 8,
		4314	&m_n->gmch_m, &m_n->gmch_n);
		4315
		4316	compute_m_n(pixel_clock, link_clock,
		4317	&m_n->link_m, &m_n->link_n);
2327	Serge	4318	}
		4319
		4320	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4321	{
2342	Serge	4322	if (i915_panel_use_ssc >= 0)
		4323	return i915_panel_use_ssc != 0;
4104	Serge	4324	return dev_priv->vbt.lvds_use_ssc
2327	Serge	4325	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4326	}
		4327
3031	serge	4328	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	4329	{
3031	serge	4330	struct drm_device *dev = crtc->dev;
		4331	struct drm_i915_private *dev_priv = dev->dev_private;
		4332	int refclk = 27000; /* for DP & HDMI */
2327	Serge	4333
3031	serge	4334	return 100000; /* only one validated so far */
2327	Serge	4335
3031	serge	4336	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		4337	refclk = 96000;
		4338	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4339	if (intel_panel_use_ssc(dev_priv))
		4340	refclk = 100000;
		4341	else
		4342	refclk = 96000;
		4343	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		4344	refclk = 100000;
		4345	}
2327	Serge	4346
3031	serge	4347	return refclk;
		4348	}
2327	Serge	4349
3031	serge	4350	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		4351	{
		4352	struct drm_device *dev = crtc->dev;
		4353	struct drm_i915_private *dev_priv = dev->dev_private;
		4354	int refclk;
2327	Serge	4355
3031	serge	4356	if (IS_VALLEYVIEW(dev)) {
		4357	refclk = vlv_get_refclk(crtc);
		4358	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4359	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4104	Serge	4360	refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
3031	serge	4361	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4362	refclk / 1000);
		4363	} else if (!IS_GEN2(dev)) {
		4364	refclk = 96000;
		4365	} else {
		4366	refclk = 48000;
		4367	}
2327	Serge	4368
3031	serge	4369	return refclk;
		4370	}
2327	Serge	4371
4104	Serge	4372	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	4373	{
4104	Serge	4374	return (1 << dpll->n) << 16 \| dpll->m2;
		4375	}
3746	Serge	4376
4104	Serge	4377	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		4378	{
		4379	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	4380	}
2327	Serge	4381
3746	Serge	4382	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	4383	intel_clock_t *reduced_clock)
		4384	{
3746	Serge	4385	struct drm_device *dev = crtc->base.dev;
3031	serge	4386	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4387	int pipe = crtc->pipe;
3031	serge	4388	u32 fp, fp2 = 0;
2327	Serge	4389
3031	serge	4390	if (IS_PINEVIEW(dev)) {
4104	Serge	4391	fp = pnv_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4392	if (reduced_clock)
4104	Serge	4393	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	4394	} else {
4104	Serge	4395	fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4396	if (reduced_clock)
4104	Serge	4397	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	4398	}
2327	Serge	4399
3031	serge	4400	I915_WRITE(FP0(pipe), fp);
4104	Serge	4401	crtc->config.dpll_hw_state.fp0 = fp;
2327	Serge	4402
3746	Serge	4403	crtc->lowfreq_avail = false;
		4404	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4405	reduced_clock && i915_powersave) {
		4406	I915_WRITE(FP1(pipe), fp2);
4104	Serge	4407	crtc->config.dpll_hw_state.fp1 = fp2;
3746	Serge	4408	crtc->lowfreq_avail = true;
3031	serge	4409	} else {
		4410	I915_WRITE(FP1(pipe), fp);
4104	Serge	4411	crtc->config.dpll_hw_state.fp1 = fp;
3031	serge	4412	}
		4413	}
2327	Serge	4414
4104	Serge	4415	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
		4416	{
		4417	u32 reg_val;
		4418
		4419	/*
		4420	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		4421	* and set it to a reasonable value instead.
		4422	*/
		4423	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4424	reg_val &= 0xffffff00;
		4425	reg_val \|= 0x00000030;
		4426	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4427
		4428	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4429	reg_val &= 0x8cffffff;
		4430	reg_val = 0x8c000000;
		4431	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4432
		4433	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4434	reg_val &= 0xffffff00;
		4435	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4436
		4437	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4438	reg_val &= 0x00ffffff;
		4439	reg_val \|= 0xb0000000;
		4440	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4441	}
		4442
		4443	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		4444	struct intel_link_m_n *m_n)
		4445	{
		4446	struct drm_device *dev = crtc->base.dev;
		4447	struct drm_i915_private *dev_priv = dev->dev_private;
		4448	int pipe = crtc->pipe;
		4449
		4450	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4451	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		4452	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		4453	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		4454	}
		4455
		4456	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		4457	struct intel_link_m_n *m_n)
		4458	{
		4459	struct drm_device *dev = crtc->base.dev;
		4460	struct drm_i915_private *dev_priv = dev->dev_private;
		4461	int pipe = crtc->pipe;
		4462	enum transcoder transcoder = crtc->config.cpu_transcoder;
		4463
		4464	if (INTEL_INFO(dev)->gen >= 5) {
		4465	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4466	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		4467	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		4468	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		4469	} else {
		4470	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4471	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		4472	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		4473	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		4474	}
		4475	}
		4476
3746	Serge	4477	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	4478	{
3746	Serge	4479	if (crtc->config.has_pch_encoder)
		4480	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4481	else
		4482	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4483	}
		4484
		4485	static void vlv_update_pll(struct intel_crtc *crtc)
		4486	{
		4487	struct drm_device *dev = crtc->base.dev;
3031	serge	4488	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4489	int pipe = crtc->pipe;
4104	Serge	4490	u32 dpll, mdiv;
3031	serge	4491	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4104	Serge	4492	u32 coreclk, reg_val, dpll_md;
2327	Serge	4493
3480	Serge	4494	mutex_lock(&dev_priv->dpio_lock);
		4495
3746	Serge	4496	bestn = crtc->config.dpll.n;
		4497	bestm1 = crtc->config.dpll.m1;
		4498	bestm2 = crtc->config.dpll.m2;
		4499	bestp1 = crtc->config.dpll.p1;
		4500	bestp2 = crtc->config.dpll.p2;
3031	serge	4501
4104	Serge	4502	/* See eDP HDMI DPIO driver vbios notes doc */
		4503
		4504	/* PLL B needs special handling */
		4505	if (pipe)
		4506	vlv_pllb_recal_opamp(dev_priv);
		4507
		4508	/* Set up Tx target for periodic Rcomp update */
		4509	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
		4510
		4511	/* Disable target IRef on PLL */
		4512	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
		4513	reg_val &= 0x00ffffff;
		4514	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
		4515
		4516	/* Disable fast lock */
		4517	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
		4518
		4519	/* Set idtafcrecal before PLL is enabled */
3031	serge	4520	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4521	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4522	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4523	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	4524
		4525	/*
		4526	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		4527	* but we don't support that).
		4528	* Note: don't use the DAC post divider as it seems unstable.
		4529	*/
		4530	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
		4531	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4532
3031	serge	4533	mdiv \|= DPIO_ENABLE_CALIBRATION;
4104	Serge	4534	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
3031	serge	4535
4104	Serge	4536	/* Set HBR and RBR LPF coefficients */
		4537	if (crtc->config.port_clock == 162000 \|\|
		4538	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) \|\|
		4539	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
		4540	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4541	0x009f0003);
		4542	else
		4543	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4544	0x00d0000f);
3031	serge	4545
4104	Serge	4546	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) \|\|
		4547	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		4548	/* Use SSC source */
		4549	if (!pipe)
		4550	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4551	0x0df40000);
		4552	else
		4553	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4554	0x0df70000);
		4555	} else { /* HDMI or VGA */
		4556	/* Use bend source */
		4557	if (!pipe)
		4558	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4559	0x0df70000);
		4560	else
		4561	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4562	0x0df40000);
		4563	}
3031	serge	4564
4104	Serge	4565	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
		4566	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
		4567	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) \|\|
		4568	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		4569	coreclk \|= 0x01000000;
		4570	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
3031	serge	4571
4104	Serge	4572	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
		4573
		4574	/* Enable DPIO clock input */
		4575	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4576	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
4398	Serge	4577	/* We should never disable this, set it here for state tracking */
		4578	if (pipe == PIPE_B)
4104	Serge	4579	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
3031	serge	4580	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4581	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4582
4104	Serge	4583	dpll_md = (crtc->config.pixel_multiplier - 1)
		4584	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4585	crtc->config.dpll_hw_state.dpll_md = dpll_md;
3031	serge	4586
3746	Serge	4587	if (crtc->config.has_dp_encoder)
		4588	intel_dp_set_m_n(crtc);
3243	Serge	4589
3480	Serge	4590	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	4591	}
		4592
3746	Serge	4593	static void i9xx_update_pll(struct intel_crtc *crtc,
		4594	intel_clock_t *reduced_clock,
3031	serge	4595	int num_connectors)
		4596	{
3746	Serge	4597	struct drm_device *dev = crtc->base.dev;
3031	serge	4598	struct drm_i915_private *dev_priv = dev->dev_private;
		4599	u32 dpll;
		4600	bool is_sdvo;
3746	Serge	4601	struct dpll *clock = &crtc->config.dpll;
3031	serge	4602
3746	Serge	4603	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4604
3746	Serge	4605	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4606	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	4607
		4608	dpll = DPLL_VGA_MODE_DIS;
		4609
3746	Serge	4610	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	4611	dpll \|= DPLLB_MODE_LVDS;
		4612	else
		4613	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	4614
4104	Serge	4615	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
3746	Serge	4616	dpll \|= (crtc->config.pixel_multiplier - 1)
		4617	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4618	}
4104	Serge	4619
		4620	if (is_sdvo)
		4621	dpll \|= DPLL_SDVO_HIGH_SPEED;
		4622
3746	Serge	4623	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4104	Serge	4624	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	4625
3031	serge	4626	/* compute bitmask from p1 value */
		4627	if (IS_PINEVIEW(dev))
		4628	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4629	else {
		4630	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4631	if (IS_G4X(dev) && reduced_clock)
		4632	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4633	}
		4634	switch (clock->p2) {
		4635	case 5:
		4636	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4637	break;
		4638	case 7:
		4639	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4640	break;
		4641	case 10:
		4642	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4643	break;
		4644	case 14:
		4645	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4646	break;
		4647	}
		4648	if (INTEL_INFO(dev)->gen >= 4)
		4649	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4650
4104	Serge	4651	if (crtc->config.sdvo_tv_clock)
3031	serge	4652	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	4653	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4654	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4655	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4656	else
		4657	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4658
3031	serge	4659	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4660	crtc->config.dpll_hw_state.dpll = dpll;
2327	Serge	4661
4104	Serge	4662	if (INTEL_INFO(dev)->gen >= 4) {
		4663	u32 dpll_md = (crtc->config.pixel_multiplier - 1)
		4664	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4665	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		4666	}
2327	Serge	4667
3746	Serge	4668	if (crtc->config.has_dp_encoder)
		4669	intel_dp_set_m_n(crtc);
3031	serge	4670	}
2327	Serge	4671
3746	Serge	4672	static void i8xx_update_pll(struct intel_crtc *crtc,
		4673	intel_clock_t *reduced_clock,
3031	serge	4674	int num_connectors)
		4675	{
3746	Serge	4676	struct drm_device *dev = crtc->base.dev;
3031	serge	4677	struct drm_i915_private *dev_priv = dev->dev_private;
		4678	u32 dpll;
3746	Serge	4679	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4680
3746	Serge	4681	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4682
3031	serge	4683	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4684
3746	Serge	4685	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	4686	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4687	} else {
		4688	if (clock->p1 == 2)
		4689	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4690	else
		4691	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4692	if (clock->p2 == 4)
		4693	dpll \|= PLL_P2_DIVIDE_BY_4;
		4694	}
2327	Serge	4695
4104	Serge	4696	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		4697	dpll \|= DPLL_DVO_2X_MODE;
		4698
3746	Serge	4699	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4700	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4701	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4702	else
		4703	dpll \|= PLL_REF_INPUT_DREFCLK;
		4704
		4705	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4706	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4707	}
		4708
4104	Serge	4709	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	4710	{
		4711	struct drm_device *dev = intel_crtc->base.dev;
		4712	struct drm_i915_private *dev_priv = dev->dev_private;
		4713	enum pipe pipe = intel_crtc->pipe;
3746	Serge	4714	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4104	Serge	4715	struct drm_display_mode *adjusted_mode =
		4716	&intel_crtc->config.adjusted_mode;
		4717	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
		4718	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
3243	Serge	4719
4104	Serge	4720	/* We need to be careful not to changed the adjusted mode, for otherwise
		4721	* the hw state checker will get angry at the mismatch. */
		4722	crtc_vtotal = adjusted_mode->crtc_vtotal;
		4723	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		4724
3243	Serge	4725	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4726	/* the chip adds 2 halflines automatically */
4104	Serge	4727	crtc_vtotal -= 1;
		4728	crtc_vblank_end -= 1;
3243	Serge	4729	vsyncshift = adjusted_mode->crtc_hsync_start
		4730	- adjusted_mode->crtc_htotal / 2;
		4731	} else {
		4732	vsyncshift = 0;
		4733	}
		4734
		4735	if (INTEL_INFO(dev)->gen > 3)
		4736	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		4737
		4738	I915_WRITE(HTOTAL(cpu_transcoder),
		4739	(adjusted_mode->crtc_hdisplay - 1) \|
		4740	((adjusted_mode->crtc_htotal - 1) << 16));
		4741	I915_WRITE(HBLANK(cpu_transcoder),
		4742	(adjusted_mode->crtc_hblank_start - 1) \|
		4743	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4744	I915_WRITE(HSYNC(cpu_transcoder),
		4745	(adjusted_mode->crtc_hsync_start - 1) \|
		4746	((adjusted_mode->crtc_hsync_end - 1) << 16));
		4747
		4748	I915_WRITE(VTOTAL(cpu_transcoder),
		4749	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	4750	((crtc_vtotal - 1) << 16));
3243	Serge	4751	I915_WRITE(VBLANK(cpu_transcoder),
		4752	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	4753	((crtc_vblank_end - 1) << 16));
3243	Serge	4754	I915_WRITE(VSYNC(cpu_transcoder),
		4755	(adjusted_mode->crtc_vsync_start - 1) \|
		4756	((adjusted_mode->crtc_vsync_end - 1) << 16));
		4757
		4758	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		4759	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		4760	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		4761	* bits. */
		4762	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		4763	(pipe == PIPE_B \|\| pipe == PIPE_C))
		4764	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		4765
		4766	/* pipesrc controls the size that is scaled from, which should
		4767	* always be the user's requested size.
		4768	*/
		4769	I915_WRITE(PIPESRC(pipe),
		4770	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		4771	}
		4772
4104	Serge	4773	static void intel_get_pipe_timings(struct intel_crtc *crtc,
		4774	struct intel_crtc_config *pipe_config)
		4775	{
		4776	struct drm_device *dev = crtc->base.dev;
		4777	struct drm_i915_private *dev_priv = dev->dev_private;
		4778	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		4779	uint32_t tmp;
		4780
		4781	tmp = I915_READ(HTOTAL(cpu_transcoder));
		4782	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		4783	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
		4784	tmp = I915_READ(HBLANK(cpu_transcoder));
		4785	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		4786	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
		4787	tmp = I915_READ(HSYNC(cpu_transcoder));
		4788	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		4789	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
		4790
		4791	tmp = I915_READ(VTOTAL(cpu_transcoder));
		4792	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		4793	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
		4794	tmp = I915_READ(VBLANK(cpu_transcoder));
		4795	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		4796	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
		4797	tmp = I915_READ(VSYNC(cpu_transcoder));
		4798	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		4799	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
		4800
		4801	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		4802	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		4803	pipe_config->adjusted_mode.crtc_vtotal += 1;
		4804	pipe_config->adjusted_mode.crtc_vblank_end += 1;
		4805	}
		4806
		4807	tmp = I915_READ(PIPESRC(crtc->pipe));
		4808	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
		4809	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
		4810	}
		4811
		4812	static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
		4813	struct intel_crtc_config *pipe_config)
		4814	{
		4815	struct drm_crtc *crtc = &intel_crtc->base;
		4816
		4817	crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
		4818	crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
		4819	crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
		4820	crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
		4821
		4822	crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
		4823	crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
		4824	crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
		4825	crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
		4826
		4827	crtc->mode.flags = pipe_config->adjusted_mode.flags;
		4828
		4829	crtc->mode.clock = pipe_config->adjusted_mode.clock;
		4830	crtc->mode.flags \|= pipe_config->adjusted_mode.flags;
		4831	}
		4832
3746	Serge	4833	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		4834	{
		4835	struct drm_device *dev = intel_crtc->base.dev;
		4836	struct drm_i915_private *dev_priv = dev->dev_private;
		4837	uint32_t pipeconf;
		4838
4104	Serge	4839	pipeconf = 0;
3746	Serge	4840
4104	Serge	4841	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		4842	I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
		4843	pipeconf \|= PIPECONF_ENABLE;
		4844
3746	Serge	4845	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4846	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4847	* core speed.
		4848	*
		4849	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4850	* pipe == 0 check?
		4851	*/
		4852	if (intel_crtc->config.requested_mode.clock >
		4853	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4854	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4855	}
		4856
4104	Serge	4857	/* only g4x and later have fancy bpc/dither controls */
		4858	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		4859	/* Bspec claims that we can't use dithering for 30bpp pipes. */
		4860	if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
		4861	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	4862	PIPECONF_DITHER_TYPE_SP;
		4863
4104	Serge	4864	switch (intel_crtc->config.pipe_bpp) {
		4865	case 18:
		4866	pipeconf \|= PIPECONF_6BPC;
		4867	break;
		4868	case 24:
		4869	pipeconf \|= PIPECONF_8BPC;
		4870	break;
		4871	case 30:
		4872	pipeconf \|= PIPECONF_10BPC;
		4873	break;
		4874	default:
		4875	/* Case prevented by intel_choose_pipe_bpp_dither. */
		4876	BUG();
3746	Serge	4877	}
		4878	}
		4879
		4880	if (HAS_PIPE_CXSR(dev)) {
		4881	if (intel_crtc->lowfreq_avail) {
		4882	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4883	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4884	} else {
		4885	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4886	}
		4887	}
		4888
		4889	if (!IS_GEN2(dev) &&
		4890	intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		4891	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4892	else
		4893	pipeconf \|= PIPECONF_PROGRESSIVE;
		4894
4104	Serge	4895	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
3746	Serge	4896	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		4897
		4898	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		4899	POSTING_READ(PIPECONF(intel_crtc->pipe));
		4900	}
		4901
3031	serge	4902	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4903	int x, int y,
		4904	struct drm_framebuffer *fb)
		4905	{
		4906	struct drm_device *dev = crtc->dev;
		4907	struct drm_i915_private *dev_priv = dev->dev_private;
		4908	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	4909	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3031	serge	4910	int pipe = intel_crtc->pipe;
		4911	int plane = intel_crtc->plane;
		4912	int refclk, num_connectors = 0;
		4913	intel_clock_t clock, reduced_clock;
3746	Serge	4914	u32 dspcntr;
4104	Serge	4915	bool ok, has_reduced_clock = false;
		4916	bool is_lvds = false;
3031	serge	4917	struct intel_encoder *encoder;
		4918	const intel_limit_t *limit;
		4919	int ret;
		4920
		4921	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4922	switch (encoder->type) {
		4923	case INTEL_OUTPUT_LVDS:
		4924	is_lvds = true;
		4925	break;
		4926	}
		4927
		4928	num_connectors++;
		4929	}
		4930
		4931	refclk = i9xx_get_refclk(crtc, num_connectors);
		4932
		4933	/*
		4934	* Returns a set of divisors for the desired target clock with the given
		4935	* refclk, or FALSE. The returned values represent the clock equation:
		4936	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4937	*/
		4938	limit = intel_limit(crtc, refclk);
4104	Serge	4939	ok = dev_priv->display.find_dpll(limit, crtc,
		4940	intel_crtc->config.port_clock,
		4941	refclk, NULL, &clock);
		4942	if (!ok && !intel_crtc->config.clock_set) {
3031	serge	4943	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4944	return -EINVAL;
		4945	}
		4946
		4947	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4948	/*
		4949	* Ensure we match the reduced clock's P to the target clock.
		4950	* If the clocks don't match, we can't switch the display clock
		4951	* by using the FP0/FP1. In such case we will disable the LVDS
		4952	* downclock feature.
		4953	*/
4104	Serge	4954	has_reduced_clock =
		4955	dev_priv->display.find_dpll(limit, crtc,
3031	serge	4956	dev_priv->lvds_downclock,
4104	Serge	4957	refclk, &clock,
3031	serge	4958	&reduced_clock);
		4959	}
3746	Serge	4960	/* Compat-code for transition, will disappear. */
		4961	if (!intel_crtc->config.clock_set) {
		4962	intel_crtc->config.dpll.n = clock.n;
		4963	intel_crtc->config.dpll.m1 = clock.m1;
		4964	intel_crtc->config.dpll.m2 = clock.m2;
		4965	intel_crtc->config.dpll.p1 = clock.p1;
		4966	intel_crtc->config.dpll.p2 = clock.p2;
		4967	}
3031	serge	4968
		4969	if (IS_GEN2(dev))
4104	Serge	4970	i8xx_update_pll(intel_crtc,
3243	Serge	4971	has_reduced_clock ? &reduced_clock : NULL,
		4972	num_connectors);
3031	serge	4973	else if (IS_VALLEYVIEW(dev))
3746	Serge	4974	vlv_update_pll(intel_crtc);
3031	serge	4975	else
3746	Serge	4976	i9xx_update_pll(intel_crtc,
3031	serge	4977	has_reduced_clock ? &reduced_clock : NULL,
		4978	num_connectors);
		4979
		4980	/* Set up the display plane register */
		4981	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4982
3746	Serge	4983	if (!IS_VALLEYVIEW(dev)) {
3031	serge	4984	if (pipe == 0)
		4985	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4986	else
		4987	dspcntr \|= DISPPLANE_SEL_PIPE_B;
3243	Serge	4988	}
		4989
4104	Serge	4990	intel_set_pipe_timings(intel_crtc);
3031	serge	4991
		4992	/* pipesrc and dspsize control the size that is scaled from,
		4993	* which should always be the user's requested size.
		4994	*/
		4995	I915_WRITE(DSPSIZE(plane),
		4996	((mode->vdisplay - 1) << 16) \|
		4997	(mode->hdisplay - 1));
		4998	I915_WRITE(DSPPOS(plane), 0);
2327	Serge	4999
3746	Serge	5000	i9xx_set_pipeconf(intel_crtc);
		5001
3031	serge	5002	I915_WRITE(DSPCNTR(plane), dspcntr);
		5003	POSTING_READ(DSPCNTR(plane));
2327	Serge	5004
3031	serge	5005	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	5006
3031	serge	5007	intel_update_watermarks(dev);
		5008
2327	Serge	5009	return ret;
		5010	}
		5011
4104	Serge	5012	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
		5013	struct intel_crtc_config *pipe_config)
		5014	{
		5015	struct drm_device *dev = crtc->base.dev;
		5016	struct drm_i915_private *dev_priv = dev->dev_private;
		5017	uint32_t tmp;
		5018
		5019	tmp = I915_READ(PFIT_CONTROL);
		5020	if (!(tmp & PFIT_ENABLE))
		5021	return;
		5022
		5023	/* Check whether the pfit is attached to our pipe. */
		5024	if (INTEL_INFO(dev)->gen < 4) {
		5025	if (crtc->pipe != PIPE_B)
		5026	return;
		5027	} else {
		5028	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		5029	return;
		5030	}
		5031
		5032	pipe_config->gmch_pfit.control = tmp;
		5033	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		5034	if (INTEL_INFO(dev)->gen < 5)
		5035	pipe_config->gmch_pfit.lvds_border_bits =
		5036	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		5037	}
		5038
4398	Serge	5039	static void vlv_crtc_clock_get(struct intel_crtc *crtc,
		5040	struct intel_crtc_config *pipe_config)
		5041	{
		5042	struct drm_device *dev = crtc->base.dev;
		5043	struct drm_i915_private *dev_priv = dev->dev_private;
		5044	int pipe = pipe_config->cpu_transcoder;
		5045	intel_clock_t clock;
		5046	u32 mdiv;
		5047	int refclk = 100000;
		5048
		5049	mutex_lock(&dev_priv->dpio_lock);
		5050	mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe));
		5051	mutex_unlock(&dev_priv->dpio_lock);
		5052
		5053	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
		5054	clock.m2 = mdiv & DPIO_M2DIV_MASK;
		5055	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
		5056	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
		5057	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
		5058
		5059	clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
		5060	clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
		5061
		5062	pipe_config->adjusted_mode.clock = clock.dot / 10;
		5063	}
		5064
3746	Serge	5065	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		5066	struct intel_crtc_config *pipe_config)
		5067	{
		5068	struct drm_device *dev = crtc->base.dev;
		5069	struct drm_i915_private *dev_priv = dev->dev_private;
		5070	uint32_t tmp;
		5071
4104	Serge	5072	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5073	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5074
3746	Serge	5075	tmp = I915_READ(PIPECONF(crtc->pipe));
		5076	if (!(tmp & PIPECONF_ENABLE))
		5077	return false;
		5078
4280	Serge	5079	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		5080	switch (tmp & PIPECONF_BPC_MASK) {
		5081	case PIPECONF_6BPC:
		5082	pipe_config->pipe_bpp = 18;
		5083	break;
		5084	case PIPECONF_8BPC:
		5085	pipe_config->pipe_bpp = 24;
		5086	break;
		5087	case PIPECONF_10BPC:
		5088	pipe_config->pipe_bpp = 30;
		5089	break;
		5090	default:
		5091	break;
		5092	}
		5093	}
		5094
4104	Serge	5095	intel_get_pipe_timings(crtc, pipe_config);
		5096
		5097	i9xx_get_pfit_config(crtc, pipe_config);
		5098
		5099	if (INTEL_INFO(dev)->gen >= 4) {
		5100	tmp = I915_READ(DPLL_MD(crtc->pipe));
		5101	pipe_config->pixel_multiplier =
		5102	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		5103	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		5104	pipe_config->dpll_hw_state.dpll_md = tmp;
		5105	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		5106	tmp = I915_READ(DPLL(crtc->pipe));
		5107	pipe_config->pixel_multiplier =
		5108	((tmp & SDVO_MULTIPLIER_MASK)
		5109	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		5110	} else {
		5111	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		5112	* port and will be fixed up in the encoder->get_config
		5113	* function. */
		5114	pipe_config->pixel_multiplier = 1;
		5115	}
		5116	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		5117	if (!IS_VALLEYVIEW(dev)) {
		5118	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		5119	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		5120	} else {
		5121	/* Mask out read-only status bits. */
		5122	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		5123	DPLL_PORTC_READY_MASK \|
		5124	DPLL_PORTB_READY_MASK);
		5125	}
		5126
3746	Serge	5127	return true;
		5128	}
		5129
3243	Serge	5130	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	5131	{
		5132	struct drm_i915_private *dev_priv = dev->dev_private;
		5133	struct drm_mode_config *mode_config = &dev->mode_config;
		5134	struct intel_encoder *encoder;
3746	Serge	5135	u32 val, final;
2327	Serge	5136	bool has_lvds = false;
2342	Serge	5137	bool has_cpu_edp = false;
		5138	bool has_panel = false;
		5139	bool has_ck505 = false;
		5140	bool can_ssc = false;
2327	Serge	5141
		5142	/* We need to take the global config into account */
		5143	list_for_each_entry(encoder, &mode_config->encoder_list,
		5144	base.head) {
		5145	switch (encoder->type) {
		5146	case INTEL_OUTPUT_LVDS:
2342	Serge	5147	has_panel = true;
2327	Serge	5148	has_lvds = true;
2342	Serge	5149	break;
2327	Serge	5150	case INTEL_OUTPUT_EDP:
2342	Serge	5151	has_panel = true;
4104	Serge	5152	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	5153	has_cpu_edp = true;
2327	Serge	5154	break;
		5155	}
		5156	}
2342	Serge	5157
		5158	if (HAS_PCH_IBX(dev)) {
4104	Serge	5159	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	5160	can_ssc = has_ck505;
		5161	} else {
		5162	has_ck505 = false;
		5163	can_ssc = true;
2327	Serge	5164	}
		5165
4104	Serge	5166	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		5167	has_panel, has_lvds, has_ck505);
2342	Serge	5168
2327	Serge	5169	/* Ironlake: try to setup display ref clock before DPLL
		5170	* enabling. This is only under driver's control after
		5171	* PCH B stepping, previous chipset stepping should be
		5172	* ignoring this setting.
		5173	*/
3746	Serge	5174	val = I915_READ(PCH_DREF_CONTROL);
		5175
		5176	/* As we must carefully and slowly disable/enable each source in turn,
		5177	* compute the final state we want first and check if we need to
		5178	* make any changes at all.
		5179	*/
		5180	final = val;
		5181	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		5182	if (has_ck505)
		5183	final \|= DREF_NONSPREAD_CK505_ENABLE;
		5184	else
		5185	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5186
		5187	final &= ~DREF_SSC_SOURCE_MASK;
		5188	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5189	final &= ~DREF_SSC1_ENABLE;
		5190
		5191	if (has_panel) {
		5192	final \|= DREF_SSC_SOURCE_ENABLE;
		5193
		5194	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5195	final \|= DREF_SSC1_ENABLE;
		5196
		5197	if (has_cpu_edp) {
		5198	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5199	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5200	else
		5201	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5202	} else
		5203	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5204	} else {
		5205	final \|= DREF_SSC_SOURCE_DISABLE;
		5206	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5207	}
		5208
		5209	if (final == val)
		5210	return;
		5211
2327	Serge	5212	/* Always enable nonspread source */
3746	Serge	5213	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	5214
		5215	if (has_ck505)
3746	Serge	5216	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	5217	else
3746	Serge	5218	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	5219
		5220	if (has_panel) {
3746	Serge	5221	val &= ~DREF_SSC_SOURCE_MASK;
		5222	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	5223
2342	Serge	5224	/* SSC must be turned on before enabling the CPU output */
		5225	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5226	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	5227	val \|= DREF_SSC1_ENABLE;
3031	serge	5228	} else
3746	Serge	5229	val &= ~DREF_SSC1_ENABLE;
2327	Serge	5230
2342	Serge	5231	/* Get SSC going before enabling the outputs */
3746	Serge	5232	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5233	POSTING_READ(PCH_DREF_CONTROL);
		5234	udelay(200);
2342	Serge	5235
3746	Serge	5236	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	5237
		5238	/* Enable CPU source on CPU attached eDP */
2342	Serge	5239	if (has_cpu_edp) {
		5240	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5241	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	5242	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	5243	}
2327	Serge	5244	else
3746	Serge	5245	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	5246	} else
3746	Serge	5247	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5248
3746	Serge	5249	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5250	POSTING_READ(PCH_DREF_CONTROL);
		5251	udelay(200);
2327	Serge	5252	} else {
2342	Serge	5253	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		5254
3746	Serge	5255	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	5256
		5257	/* Turn off CPU output */
3746	Serge	5258	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5259
3746	Serge	5260	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5261	POSTING_READ(PCH_DREF_CONTROL);
		5262	udelay(200);
2342	Serge	5263
		5264	/* Turn off the SSC source */
3746	Serge	5265	val &= ~DREF_SSC_SOURCE_MASK;
		5266	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	5267
		5268	/* Turn off SSC1 */
3746	Serge	5269	val &= ~DREF_SSC1_ENABLE;
2342	Serge	5270
3746	Serge	5271	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5272	POSTING_READ(PCH_DREF_CONTROL);
		5273	udelay(200);
2327	Serge	5274	}
3746	Serge	5275
		5276	BUG_ON(val != final);
2327	Serge	5277	}
		5278
4104	Serge	5279	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	5280	{
4104	Serge	5281	uint32_t tmp;
3243	Serge	5282
		5283	tmp = I915_READ(SOUTH_CHICKEN2);
		5284	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		5285	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5286
		5287	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		5288	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		5289	DRM_ERROR("FDI mPHY reset assert timeout\n");
		5290
		5291	tmp = I915_READ(SOUTH_CHICKEN2);
		5292	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		5293	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5294
		5295	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	5296	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
3243	Serge	5297	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4539	Serge	5298	}
3243	Serge	5299
4104	Serge	5300	/* WaMPhyProgramming:hsw */
		5301	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		5302	{
		5303	uint32_t tmp;
		5304
3243	Serge	5305	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		5306	tmp &= ~(0xFF << 24);
		5307	tmp \|= (0x12 << 24);
		5308	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		5309
		5310	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		5311	tmp \|= (1 << 11);
		5312	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		5313
		5314	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		5315	tmp \|= (1 << 11);
		5316	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		5317
		5318	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		5319	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5320	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		5321
		5322	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		5323	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5324	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		5325
		5326	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		5327	tmp &= ~(7 << 13);
		5328	tmp \|= (5 << 13);
		5329	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		5330
		5331	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		5332	tmp &= ~(7 << 13);
		5333	tmp \|= (5 << 13);
		5334	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		5335
		5336	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		5337	tmp &= ~0xFF;
		5338	tmp \|= 0x1C;
		5339	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		5340
		5341	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		5342	tmp &= ~0xFF;
		5343	tmp \|= 0x1C;
		5344	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		5345
		5346	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		5347	tmp &= ~(0xFF << 16);
		5348	tmp \|= (0x1C << 16);
		5349	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		5350
		5351	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		5352	tmp &= ~(0xFF << 16);
		5353	tmp \|= (0x1C << 16);
		5354	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		5355
		5356	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		5357	tmp \|= (1 << 27);
		5358	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		5359
		5360	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		5361	tmp \|= (1 << 27);
		5362	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		5363
		5364	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		5365	tmp &= ~(0xF << 28);
		5366	tmp \|= (4 << 28);
		5367	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		5368
		5369	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		5370	tmp &= ~(0xF << 28);
		5371	tmp \|= (4 << 28);
		5372	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4539	Serge	5373	}
3243	Serge	5374
4104	Serge	5375	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		5376	* Programming" based on the parameters passed:
		5377	* - Sequence to enable CLKOUT_DP
		5378	* - Sequence to enable CLKOUT_DP without spread
		5379	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		5380	*/
		5381	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		5382	bool with_fdi)
		5383	{
		5384	struct drm_i915_private *dev_priv = dev->dev_private;
		5385	uint32_t reg, tmp;
3480	Serge	5386
4104	Serge	5387	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		5388	with_spread = true;
		5389	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		5390	with_fdi, "LP PCH doesn't have FDI\n"))
		5391	with_fdi = false;
		5392
		5393	mutex_lock(&dev_priv->dpio_lock);
		5394
		5395	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5396	tmp &= ~SBI_SSCCTL_DISABLE;
		5397	tmp \|= SBI_SSCCTL_PATHALT;
		5398	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5399
		5400	udelay(24);
		5401
		5402	if (with_spread) {
		5403	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5404	tmp &= ~SBI_SSCCTL_PATHALT;
		5405	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5406
		5407	if (with_fdi) {
		5408	lpt_reset_fdi_mphy(dev_priv);
		5409	lpt_program_fdi_mphy(dev_priv);
		5410	}
		5411	}
		5412
		5413	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5414	SBI_GEN0 : SBI_DBUFF0;
		5415	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5416	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5417	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5418
3480	Serge	5419	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	5420	}
		5421
4104	Serge	5422	/* Sequence to disable CLKOUT_DP */
		5423	static void lpt_disable_clkout_dp(struct drm_device *dev)
		5424	{
		5425	struct drm_i915_private *dev_priv = dev->dev_private;
		5426	uint32_t reg, tmp;
		5427
		5428	mutex_lock(&dev_priv->dpio_lock);
		5429
		5430	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5431	SBI_GEN0 : SBI_DBUFF0;
		5432	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5433	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5434	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5435
		5436	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5437	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		5438	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		5439	tmp \|= SBI_SSCCTL_PATHALT;
		5440	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5441	udelay(32);
		5442	}
		5443	tmp \|= SBI_SSCCTL_DISABLE;
		5444	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5445	}
		5446
		5447	mutex_unlock(&dev_priv->dpio_lock);
		5448	}
		5449
		5450	static void lpt_init_pch_refclk(struct drm_device *dev)
		5451	{
		5452	struct drm_mode_config *mode_config = &dev->mode_config;
		5453	struct intel_encoder *encoder;
		5454	bool has_vga = false;
		5455
		5456	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5457	switch (encoder->type) {
		5458	case INTEL_OUTPUT_ANALOG:
		5459	has_vga = true;
		5460	break;
		5461	}
		5462	}
		5463
		5464	if (has_vga)
		5465	lpt_enable_clkout_dp(dev, true, true);
		5466	else
		5467	lpt_disable_clkout_dp(dev);
		5468	}
		5469
3243	Serge	5470	/*
		5471	* Initialize reference clocks when the driver loads
		5472	*/
		5473	void intel_init_pch_refclk(struct drm_device *dev)
		5474	{
		5475	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		5476	ironlake_init_pch_refclk(dev);
		5477	else if (HAS_PCH_LPT(dev))
		5478	lpt_init_pch_refclk(dev);
		5479	}
		5480
2342	Serge	5481	static int ironlake_get_refclk(struct drm_crtc *crtc)
		5482	{
		5483	struct drm_device *dev = crtc->dev;
		5484	struct drm_i915_private *dev_priv = dev->dev_private;
		5485	struct intel_encoder *encoder;
		5486	int num_connectors = 0;
		5487	bool is_lvds = false;
		5488
3031	serge	5489	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	5490	switch (encoder->type) {
		5491	case INTEL_OUTPUT_LVDS:
		5492	is_lvds = true;
		5493	break;
		5494	}
		5495	num_connectors++;
		5496	}
		5497
		5498	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5499	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4104	Serge	5500	dev_priv->vbt.lvds_ssc_freq);
		5501	return dev_priv->vbt.lvds_ssc_freq * 1000;
2342	Serge	5502	}
		5503
		5504	return 120000;
		5505	}
		5506
4104	Serge	5507	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	5508	{
		5509	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5510	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5511	int pipe = intel_crtc->pipe;
		5512	uint32_t val;
		5513
4104	Serge	5514	val = 0;
3031	serge	5515
3746	Serge	5516	switch (intel_crtc->config.pipe_bpp) {
3031	serge	5517	case 18:
3480	Serge	5518	val \|= PIPECONF_6BPC;
3031	serge	5519	break;
		5520	case 24:
3480	Serge	5521	val \|= PIPECONF_8BPC;
3031	serge	5522	break;
		5523	case 30:
3480	Serge	5524	val \|= PIPECONF_10BPC;
3031	serge	5525	break;
		5526	case 36:
3480	Serge	5527	val \|= PIPECONF_12BPC;
3031	serge	5528	break;
		5529	default:
3243	Serge	5530	/* Case prevented by intel_choose_pipe_bpp_dither. */
		5531	BUG();
3031	serge	5532	}
		5533
4104	Serge	5534	if (intel_crtc->config.dither)
3031	serge	5535	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5536
4104	Serge	5537	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	5538	val \|= PIPECONF_INTERLACED_ILK;
		5539	else
		5540	val \|= PIPECONF_PROGRESSIVE;
		5541
3746	Serge	5542	if (intel_crtc->config.limited_color_range)
3480	Serge	5543	val \|= PIPECONF_COLOR_RANGE_SELECT;
		5544
3031	serge	5545	I915_WRITE(PIPECONF(pipe), val);
		5546	POSTING_READ(PIPECONF(pipe));
		5547	}
		5548
3480	Serge	5549	/*
		5550	* Set up the pipe CSC unit.
		5551	*
		5552	* Currently only full range RGB to limited range RGB conversion
		5553	* is supported, but eventually this should handle various
		5554	* RGB<->YCbCr scenarios as well.
		5555	*/
3746	Serge	5556	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	5557	{
		5558	struct drm_device *dev = crtc->dev;
		5559	struct drm_i915_private *dev_priv = dev->dev_private;
		5560	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5561	int pipe = intel_crtc->pipe;
		5562	uint16_t coeff = 0x7800; /* 1.0 */
		5563
		5564	/*
		5565	* TODO: Check what kind of values actually come out of the pipe
		5566	* with these coeff/postoff values and adjust to get the best
		5567	* accuracy. Perhaps we even need to take the bpc value into
		5568	* consideration.
		5569	*/
		5570
3746	Serge	5571	if (intel_crtc->config.limited_color_range)
3480	Serge	5572	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		5573
		5574	/*
		5575	* GY/GU and RY/RU should be the other way around according
		5576	* to BSpec, but reality doesn't agree. Just set them up in
		5577	* a way that results in the correct picture.
		5578	*/
		5579	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		5580	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		5581
		5582	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		5583	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		5584
		5585	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		5586	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		5587
		5588	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		5589	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		5590	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		5591
		5592	if (INTEL_INFO(dev)->gen > 6) {
		5593	uint16_t postoff = 0;
		5594
3746	Serge	5595	if (intel_crtc->config.limited_color_range)
4398	Serge	5596	postoff = (16 * (1 << 12) / 255) & 0x1fff;
3480	Serge	5597
		5598	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		5599	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		5600	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		5601
		5602	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		5603	} else {
		5604	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		5605
3746	Serge	5606	if (intel_crtc->config.limited_color_range)
3480	Serge	5607	mode \|= CSC_BLACK_SCREEN_OFFSET;
		5608
		5609	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		5610	}
		5611	}
		5612
4104	Serge	5613	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	5614	{
		5615	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5616	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5617	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	5618	uint32_t val;
		5619
4104	Serge	5620	val = 0;
3243	Serge	5621
4104	Serge	5622	if (intel_crtc->config.dither)
3243	Serge	5623	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5624
4104	Serge	5625	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	5626	val \|= PIPECONF_INTERLACED_ILK;
		5627	else
		5628	val \|= PIPECONF_PROGRESSIVE;
		5629
		5630	I915_WRITE(PIPECONF(cpu_transcoder), val);
		5631	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	5632
		5633	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		5634	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
3243	Serge	5635	}
		5636
3031	serge	5637	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		5638	intel_clock_t *clock,
		5639	bool *has_reduced_clock,
		5640	intel_clock_t *reduced_clock)
		5641	{
		5642	struct drm_device *dev = crtc->dev;
		5643	struct drm_i915_private *dev_priv = dev->dev_private;
		5644	struct intel_encoder *intel_encoder;
		5645	int refclk;
		5646	const intel_limit_t *limit;
4104	Serge	5647	bool ret, is_lvds = false;
3031	serge	5648
		5649	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5650	switch (intel_encoder->type) {
		5651	case INTEL_OUTPUT_LVDS:
		5652	is_lvds = true;
		5653	break;
		5654	}
		5655	}
		5656
		5657	refclk = ironlake_get_refclk(crtc);
		5658
		5659	/*
		5660	* Returns a set of divisors for the desired target clock with the given
		5661	* refclk, or FALSE. The returned values represent the clock equation:
		5662	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5663	*/
		5664	limit = intel_limit(crtc, refclk);
4104	Serge	5665	ret = dev_priv->display.find_dpll(limit, crtc,
		5666	to_intel_crtc(crtc)->config.port_clock,
		5667	refclk, NULL, clock);
3031	serge	5668	if (!ret)
		5669	return false;
		5670
		5671	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5672	/*
		5673	* Ensure we match the reduced clock's P to the target clock.
		5674	* If the clocks don't match, we can't switch the display clock
		5675	* by using the FP0/FP1. In such case we will disable the LVDS
		5676	* downclock feature.
		5677	*/
4104	Serge	5678	*has_reduced_clock =
		5679	dev_priv->display.find_dpll(limit, crtc,
3031	serge	5680	dev_priv->lvds_downclock,
4104	Serge	5681	refclk, clock,
3031	serge	5682	reduced_clock);
		5683	}
		5684
		5685	return true;
		5686	}
		5687
3243	Serge	5688	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		5689	{
		5690	/*
		5691	* Account for spread spectrum to avoid
		5692	* oversubscribing the link. Max center spread
		5693	* is 2.5%; use 5% for safety's sake.
		5694	*/
		5695	u32 bps = target_clock * bpp * 21 / 20;
		5696	return bps / (link_bw * 8) + 1;
		5697	}
		5698
4104	Serge	5699	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	5700	{
4104	Serge	5701	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	5702	}
		5703
3243	Serge	5704	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4104	Serge	5705	u32 *fp,
3746	Serge	5706	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	5707	{
		5708	struct drm_crtc *crtc = &intel_crtc->base;
		5709	struct drm_device *dev = crtc->dev;
		5710	struct drm_i915_private *dev_priv = dev->dev_private;
		5711	struct intel_encoder *intel_encoder;
		5712	uint32_t dpll;
3746	Serge	5713	int factor, num_connectors = 0;
4104	Serge	5714	bool is_lvds = false, is_sdvo = false;
3243	Serge	5715
		5716	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5717	switch (intel_encoder->type) {
		5718	case INTEL_OUTPUT_LVDS:
		5719	is_lvds = true;
		5720	break;
		5721	case INTEL_OUTPUT_SDVO:
		5722	case INTEL_OUTPUT_HDMI:
		5723	is_sdvo = true;
		5724	break;
		5725	}
		5726
		5727	num_connectors++;
		5728	}
		5729
2327	Serge	5730	/* Enable autotuning of the PLL clock (if permissible) */
		5731	factor = 21;
		5732	if (is_lvds) {
		5733	if ((intel_panel_use_ssc(dev_priv) &&
4104	Serge	5734	dev_priv->vbt.lvds_ssc_freq == 100) \|\|
3746	Serge	5735	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	5736	factor = 25;
4104	Serge	5737	} else if (intel_crtc->config.sdvo_tv_clock)
2327	Serge	5738	factor = 20;
		5739
4104	Serge	5740	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
3746	Serge	5741	*fp \|= FP_CB_TUNE;
2327	Serge	5742
3746	Serge	5743	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		5744	*fp2 \|= FP_CB_TUNE;
		5745
2327	Serge	5746	dpll = 0;
		5747
		5748	if (is_lvds)
		5749	dpll \|= DPLLB_MODE_LVDS;
		5750	else
		5751	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	5752
3746	Serge	5753	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		5754	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	5755
4104	Serge	5756	if (is_sdvo)
		5757	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5758	if (intel_crtc->config.has_dp_encoder)
		5759	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5760
2327	Serge	5761	/* compute bitmask from p1 value */
4104	Serge	5762	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	5763	/* also FPA1 */
4104	Serge	5764	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	5765
4104	Serge	5766	switch (intel_crtc->config.dpll.p2) {
2327	Serge	5767	case 5:
		5768	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5769	break;
		5770	case 7:
		5771	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5772	break;
		5773	case 10:
		5774	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5775	break;
		5776	case 14:
		5777	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5778	break;
		5779	}
		5780
4104	Serge	5781	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
2327	Serge	5782	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5783	else
		5784	dpll \|= PLL_REF_INPUT_DREFCLK;
		5785
4104	Serge	5786	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	5787	}
		5788
		5789	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5790	int x, int y,
		5791	struct drm_framebuffer *fb)
		5792	{
		5793	struct drm_device *dev = crtc->dev;
		5794	struct drm_i915_private *dev_priv = dev->dev_private;
		5795	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5796	int pipe = intel_crtc->pipe;
		5797	int plane = intel_crtc->plane;
		5798	int num_connectors = 0;
		5799	intel_clock_t clock, reduced_clock;
4104	Serge	5800	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	5801	bool ok, has_reduced_clock = false;
3746	Serge	5802	bool is_lvds = false;
3243	Serge	5803	struct intel_encoder *encoder;
4104	Serge	5804	struct intel_shared_dpll *pll;
3243	Serge	5805	int ret;
		5806
		5807	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5808	switch (encoder->type) {
		5809	case INTEL_OUTPUT_LVDS:
		5810	is_lvds = true;
		5811	break;
		5812	}
		5813
		5814	num_connectors++;
		5815	}
		5816
		5817	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		5818	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		5819
4104	Serge	5820	ok = ironlake_compute_clocks(crtc, &clock,
3243	Serge	5821	&has_reduced_clock, &reduced_clock);
4104	Serge	5822	if (!ok && !intel_crtc->config.clock_set) {
3243	Serge	5823	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5824	return -EINVAL;
		5825	}
3746	Serge	5826	/* Compat-code for transition, will disappear. */
		5827	if (!intel_crtc->config.clock_set) {
		5828	intel_crtc->config.dpll.n = clock.n;
		5829	intel_crtc->config.dpll.m1 = clock.m1;
		5830	intel_crtc->config.dpll.m2 = clock.m2;
		5831	intel_crtc->config.dpll.p1 = clock.p1;
		5832	intel_crtc->config.dpll.p2 = clock.p2;
		5833	}
3243	Serge	5834
4104	Serge	5835	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
		5836	if (intel_crtc->config.has_pch_encoder) {
		5837	fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
3243	Serge	5838	if (has_reduced_clock)
4104	Serge	5839	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	5840
4104	Serge	5841	dpll = ironlake_compute_dpll(intel_crtc,
		5842	&fp, &reduced_clock,
3746	Serge	5843	has_reduced_clock ? &fp2 : NULL);
3243	Serge	5844
4104	Serge	5845	intel_crtc->config.dpll_hw_state.dpll = dpll;
		5846	intel_crtc->config.dpll_hw_state.fp0 = fp;
		5847	if (has_reduced_clock)
		5848	intel_crtc->config.dpll_hw_state.fp1 = fp2;
		5849	else
		5850	intel_crtc->config.dpll_hw_state.fp1 = fp;
2327	Serge	5851
4104	Serge	5852	pll = intel_get_shared_dpll(intel_crtc);
3031	serge	5853	if (pll == NULL) {
4104	Serge	5854	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		5855	pipe_name(pipe));
2342	Serge	5856	return -EINVAL;
2327	Serge	5857	}
3031	serge	5858	} else
4104	Serge	5859	intel_put_shared_dpll(intel_crtc);
2327	Serge	5860
3746	Serge	5861	if (intel_crtc->config.has_dp_encoder)
		5862	intel_dp_set_m_n(intel_crtc);
2342	Serge	5863
4104	Serge	5864	if (is_lvds && has_reduced_clock && i915_powersave)
		5865	intel_crtc->lowfreq_avail = true;
		5866	else
		5867	intel_crtc->lowfreq_avail = false;
2327	Serge	5868
4104	Serge	5869	if (intel_crtc->config.has_pch_encoder) {
		5870	pll = intel_crtc_to_shared_dpll(intel_crtc);
2327	Serge	5871
4104	Serge	5872	}
2327	Serge	5873
4104	Serge	5874	intel_set_pipe_timings(intel_crtc);
2327	Serge	5875
4104	Serge	5876	if (intel_crtc->config.has_pch_encoder) {
		5877	intel_cpu_transcoder_set_m_n(intel_crtc,
		5878	&intel_crtc->config.fdi_m_n);
2342	Serge	5879	}
2327	Serge	5880
4104	Serge	5881	ironlake_set_pipeconf(crtc);
3243	Serge	5882
		5883	/* Set up the display plane register */
		5884	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		5885	POSTING_READ(DSPCNTR(plane));
		5886
		5887	ret = intel_pipe_set_base(crtc, x, y, fb);
		5888
		5889	intel_update_watermarks(dev);
		5890
4104	Serge	5891	return ret;
		5892	}
3243	Serge	5893
4104	Serge	5894	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
		5895	struct intel_crtc_config *pipe_config)
		5896	{
		5897	struct drm_device *dev = crtc->base.dev;
		5898	struct drm_i915_private *dev_priv = dev->dev_private;
		5899	enum transcoder transcoder = pipe_config->cpu_transcoder;
		5900
		5901	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
		5902	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
		5903	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
		5904	& ~TU_SIZE_MASK;
		5905	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		5906	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
		5907	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3243	Serge	5908	}
		5909
4104	Serge	5910	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
		5911	struct intel_crtc_config *pipe_config)
		5912	{
		5913	struct drm_device *dev = crtc->base.dev;
		5914	struct drm_i915_private *dev_priv = dev->dev_private;
		5915	uint32_t tmp;
		5916
		5917	tmp = I915_READ(PF_CTL(crtc->pipe));
		5918
		5919	if (tmp & PF_ENABLE) {
		5920	pipe_config->pch_pfit.enabled = true;
		5921	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		5922	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		5923
		5924	/* We currently do not free assignements of panel fitters on
		5925	* ivb/hsw (since we don't use the higher upscaling modes which
		5926	* differentiates them) so just WARN about this case for now. */
		5927	if (IS_GEN7(dev)) {
		5928	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		5929	PF_PIPE_SEL_IVB(crtc->pipe));
		5930	}
		5931	}
		5932	}
		5933
3746	Serge	5934	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		5935	struct intel_crtc_config *pipe_config)
		5936	{
		5937	struct drm_device *dev = crtc->base.dev;
		5938	struct drm_i915_private *dev_priv = dev->dev_private;
		5939	uint32_t tmp;
		5940
4104	Serge	5941	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5942	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5943
3746	Serge	5944	tmp = I915_READ(PIPECONF(crtc->pipe));
		5945	if (!(tmp & PIPECONF_ENABLE))
		5946	return false;
		5947
4280	Serge	5948	switch (tmp & PIPECONF_BPC_MASK) {
		5949	case PIPECONF_6BPC:
		5950	pipe_config->pipe_bpp = 18;
		5951	break;
		5952	case PIPECONF_8BPC:
		5953	pipe_config->pipe_bpp = 24;
		5954	break;
		5955	case PIPECONF_10BPC:
		5956	pipe_config->pipe_bpp = 30;
		5957	break;
		5958	case PIPECONF_12BPC:
		5959	pipe_config->pipe_bpp = 36;
		5960	break;
		5961	default:
		5962	break;
		5963	}
		5964
4104	Serge	5965	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		5966	struct intel_shared_dpll *pll;
		5967
3746	Serge	5968	pipe_config->has_pch_encoder = true;
		5969
4104	Serge	5970	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		5971	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		5972	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		5973
		5974	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		5975
		5976	if (HAS_PCH_IBX(dev_priv->dev)) {
		5977	pipe_config->shared_dpll =
		5978	(enum intel_dpll_id) crtc->pipe;
		5979	} else {
		5980	tmp = I915_READ(PCH_DPLL_SEL);
		5981	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		5982	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		5983	else
		5984	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		5985	}
		5986
		5987	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		5988
		5989	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		5990	&pipe_config->dpll_hw_state));
		5991
		5992	tmp = pipe_config->dpll_hw_state.dpll;
		5993	pipe_config->pixel_multiplier =
		5994	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		5995	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
		5996	} else {
		5997	pipe_config->pixel_multiplier = 1;
		5998	}
		5999
		6000	intel_get_pipe_timings(crtc, pipe_config);
		6001
		6002	ironlake_get_pfit_config(crtc, pipe_config);
		6003
3746	Serge	6004	return true;
		6005	}
		6006
4104	Serge	6007	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		6008	{
		6009	struct drm_device *dev = dev_priv->dev;
		6010	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		6011	struct intel_crtc *crtc;
		6012	unsigned long irqflags;
		6013	uint32_t val;
		6014
		6015	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
4539	Serge	6016	WARN(crtc->active, "CRTC for pipe %c enabled\n",
4104	Serge	6017	pipe_name(crtc->pipe));
		6018
		6019	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
		6020	WARN(plls->spll_refcount, "SPLL enabled\n");
		6021	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
		6022	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
		6023	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		6024	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
		6025	"CPU PWM1 enabled\n");
		6026	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		6027	"CPU PWM2 enabled\n");
		6028	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
		6029	"PCH PWM1 enabled\n");
		6030	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
		6031	"Utility pin enabled\n");
		6032	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
		6033
		6034	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		6035	val = I915_READ(DEIMR);
		6036	WARN((val & ~DE_PCH_EVENT_IVB) != val,
		6037	"Unexpected DEIMR bits enabled: 0x%x\n", val);
		6038	val = I915_READ(SDEIMR);
		6039	WARN((val \| SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
		6040	"Unexpected SDEIMR bits enabled: 0x%x\n", val);
		6041	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
		6042	}
		6043
		6044	/*
		6045	* This function implements pieces of two sequences from BSpec:
		6046	* - Sequence for display software to disable LCPLL
		6047	* - Sequence for display software to allow package C8+
		6048	* The steps implemented here are just the steps that actually touch the LCPLL
		6049	* register. Callers should take care of disabling all the display engine
		6050	* functions, doing the mode unset, fixing interrupts, etc.
		6051	*/
		6052	void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
		6053	bool switch_to_fclk, bool allow_power_down)
		6054	{
		6055	uint32_t val;
		6056
		6057	assert_can_disable_lcpll(dev_priv);
		6058
		6059	val = I915_READ(LCPLL_CTL);
		6060
		6061	if (switch_to_fclk) {
		6062	val \|= LCPLL_CD_SOURCE_FCLK;
		6063	I915_WRITE(LCPLL_CTL, val);
		6064
		6065	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		6066	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		6067	DRM_ERROR("Switching to FCLK failed\n");
		6068
		6069	val = I915_READ(LCPLL_CTL);
		6070	}
		6071
		6072	val \|= LCPLL_PLL_DISABLE;
		6073	I915_WRITE(LCPLL_CTL, val);
		6074	POSTING_READ(LCPLL_CTL);
		6075
		6076	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		6077	DRM_ERROR("LCPLL still locked\n");
		6078
		6079	val = I915_READ(D_COMP);
		6080	val \|= D_COMP_COMP_DISABLE;
		6081	I915_WRITE(D_COMP, val);
		6082	POSTING_READ(D_COMP);
		6083	udelay(100);
		6084
		6085	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
		6086	DRM_ERROR("D_COMP RCOMP still in progress\n");
		6087
		6088	if (allow_power_down) {
		6089	val = I915_READ(LCPLL_CTL);
		6090	val \|= LCPLL_POWER_DOWN_ALLOW;
		6091	I915_WRITE(LCPLL_CTL, val);
		6092	POSTING_READ(LCPLL_CTL);
		6093	}
		6094	}
		6095
		6096	/*
		6097	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		6098	* source.
		6099	*/
		6100	void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
		6101	{
		6102	uint32_t val;
		6103
		6104	val = I915_READ(LCPLL_CTL);
		6105
		6106	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		6107	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		6108	return;
		6109
		6110	/* Make sure we're not on PC8 state before disabling PC8, otherwise
		6111	* we'll hang the machine! */
4398	Serge	6112	gen6_gt_force_wake_get(dev_priv);
4104	Serge	6113
		6114	if (val & LCPLL_POWER_DOWN_ALLOW) {
		6115	val &= ~LCPLL_POWER_DOWN_ALLOW;
		6116	I915_WRITE(LCPLL_CTL, val);
		6117	POSTING_READ(LCPLL_CTL);
		6118	}
		6119
		6120	val = I915_READ(D_COMP);
		6121	val \|= D_COMP_COMP_FORCE;
		6122	val &= ~D_COMP_COMP_DISABLE;
		6123	I915_WRITE(D_COMP, val);
		6124	POSTING_READ(D_COMP);
		6125
		6126	val = I915_READ(LCPLL_CTL);
		6127	val &= ~LCPLL_PLL_DISABLE;
		6128	I915_WRITE(LCPLL_CTL, val);
		6129
		6130	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		6131	DRM_ERROR("LCPLL not locked yet\n");
		6132
		6133	if (val & LCPLL_CD_SOURCE_FCLK) {
		6134	val = I915_READ(LCPLL_CTL);
		6135	val &= ~LCPLL_CD_SOURCE_FCLK;
		6136	I915_WRITE(LCPLL_CTL, val);
		6137
		6138	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		6139	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		6140	DRM_ERROR("Switching back to LCPLL failed\n");
		6141	}
		6142
4398	Serge	6143	gen6_gt_force_wake_put(dev_priv);
4104	Serge	6144	}
		6145
		6146	void hsw_enable_pc8_work(struct work_struct *__work)
		6147	{
		6148	struct drm_i915_private *dev_priv =
		6149	container_of(to_delayed_work(__work), struct drm_i915_private,
		6150	pc8.enable_work);
		6151	struct drm_device *dev = dev_priv->dev;
		6152	uint32_t val;
		6153
		6154	if (dev_priv->pc8.enabled)
		6155	return;
		6156
		6157	DRM_DEBUG_KMS("Enabling package C8+\n");
		6158
		6159	dev_priv->pc8.enabled = true;
		6160
		6161	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6162	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6163	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		6164	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6165	}
		6166
		6167	lpt_disable_clkout_dp(dev);
		6168	hsw_pc8_disable_interrupts(dev);
		6169	hsw_disable_lcpll(dev_priv, true, true);
		6170	}
		6171
		6172	static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6173	{
		6174	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6175	WARN(dev_priv->pc8.disable_count < 1,
		6176	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6177
		6178	dev_priv->pc8.disable_count--;
		6179	if (dev_priv->pc8.disable_count != 0)
		6180	return;
		6181
		6182	schedule_delayed_work(&dev_priv->pc8.enable_work,
		6183	msecs_to_jiffies(i915_pc8_timeout));
		6184	}
		6185
		6186	static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6187	{
		6188	struct drm_device *dev = dev_priv->dev;
		6189	uint32_t val;
		6190
		6191	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6192	WARN(dev_priv->pc8.disable_count < 0,
		6193	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6194
		6195	dev_priv->pc8.disable_count++;
		6196	if (dev_priv->pc8.disable_count != 1)
		6197	return;
		6198
4293	Serge	6199	cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
4104	Serge	6200	if (!dev_priv->pc8.enabled)
		6201	return;
		6202
		6203	DRM_DEBUG_KMS("Disabling package C8+\n");
		6204
		6205	hsw_restore_lcpll(dev_priv);
		6206	hsw_pc8_restore_interrupts(dev);
		6207	lpt_init_pch_refclk(dev);
		6208
		6209	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6210	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6211	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		6212	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6213	}
		6214
		6215	intel_prepare_ddi(dev);
		6216	i915_gem_init_swizzling(dev);
		6217	mutex_lock(&dev_priv->rps.hw_lock);
		6218	gen6_update_ring_freq(dev);
		6219	mutex_unlock(&dev_priv->rps.hw_lock);
		6220	dev_priv->pc8.enabled = false;
		6221	}
		6222
		6223	void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6224	{
		6225	mutex_lock(&dev_priv->pc8.lock);
		6226	__hsw_enable_package_c8(dev_priv);
		6227	mutex_unlock(&dev_priv->pc8.lock);
		6228	}
		6229
		6230	void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6231	{
		6232	mutex_lock(&dev_priv->pc8.lock);
		6233	__hsw_disable_package_c8(dev_priv);
		6234	mutex_unlock(&dev_priv->pc8.lock);
		6235	}
		6236
		6237	static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
		6238	{
		6239	struct drm_device *dev = dev_priv->dev;
		6240	struct intel_crtc *crtc;
		6241	uint32_t val;
		6242
		6243	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		6244	if (crtc->base.enabled)
		6245	return false;
		6246
		6247	/* This case is still possible since we have the i915.disable_power_well
		6248	* parameter and also the KVMr or something else might be requesting the
		6249	* power well. */
		6250	val = I915_READ(HSW_PWR_WELL_DRIVER);
		6251	if (val != 0) {
		6252	DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
		6253	return false;
		6254	}
		6255
		6256	return true;
		6257	}
		6258
		6259	/* Since we're called from modeset_global_resources there's no way to
		6260	* symmetrically increase and decrease the refcount, so we use
		6261	* dev_priv->pc8.requirements_met to track whether we already have the refcount
		6262	* or not.
		6263	*/
		6264	static void hsw_update_package_c8(struct drm_device *dev)
		6265	{
		6266	struct drm_i915_private *dev_priv = dev->dev_private;
		6267	bool allow;
		6268
		6269	if (!i915_enable_pc8)
		6270	return;
		6271
		6272	mutex_lock(&dev_priv->pc8.lock);
		6273
		6274	allow = hsw_can_enable_package_c8(dev_priv);
		6275
		6276	if (allow == dev_priv->pc8.requirements_met)
		6277	goto done;
		6278
		6279	dev_priv->pc8.requirements_met = allow;
		6280
		6281	if (allow)
		6282	__hsw_enable_package_c8(dev_priv);
		6283	else
		6284	__hsw_disable_package_c8(dev_priv);
		6285
		6286	done:
		6287	mutex_unlock(&dev_priv->pc8.lock);
		6288	}
		6289
		6290	static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
		6291	{
		6292	if (!dev_priv->pc8.gpu_idle) {
		6293	dev_priv->pc8.gpu_idle = true;
		6294	hsw_enable_package_c8(dev_priv);
		6295	}
		6296	}
		6297
		6298	static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
		6299	{
		6300	if (dev_priv->pc8.gpu_idle) {
		6301	dev_priv->pc8.gpu_idle = false;
		6302	hsw_disable_package_c8(dev_priv);
		6303	}
		6304	}
		6305
3480	Serge	6306	static void haswell_modeset_global_resources(struct drm_device *dev)
		6307	{
		6308	bool enable = false;
		6309	struct intel_crtc *crtc;
		6310
		6311	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4104	Serge	6312	if (!crtc->base.enabled)
		6313	continue;
3480	Serge	6314
4104	Serge	6315	if (crtc->pipe != PIPE_A \|\| crtc->config.pch_pfit.enabled \|\|
		6316	crtc->config.cpu_transcoder != TRANSCODER_EDP)
3480	Serge	6317	enable = true;
		6318	}
		6319
4104	Serge	6320	intel_set_power_well(dev, enable);
3480	Serge	6321
4104	Serge	6322	hsw_update_package_c8(dev);
3480	Serge	6323	}
		6324
3243	Serge	6325	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		6326	int x, int y,
		6327	struct drm_framebuffer *fb)
		6328	{
		6329	struct drm_device *dev = crtc->dev;
		6330	struct drm_i915_private *dev_priv = dev->dev_private;
		6331	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6332	int plane = intel_crtc->plane;
		6333	int ret;
		6334
4104	Serge	6335	if (!intel_ddi_pll_mode_set(crtc))
3243	Serge	6336	return -EINVAL;
		6337
3746	Serge	6338	if (intel_crtc->config.has_dp_encoder)
		6339	intel_dp_set_m_n(intel_crtc);
2327	Serge	6340
3243	Serge	6341	intel_crtc->lowfreq_avail = false;
2327	Serge	6342
4104	Serge	6343	intel_set_pipe_timings(intel_crtc);
3243	Serge	6344
4104	Serge	6345	if (intel_crtc->config.has_pch_encoder) {
		6346	intel_cpu_transcoder_set_m_n(intel_crtc,
		6347	&intel_crtc->config.fdi_m_n);
		6348	}
3243	Serge	6349
4104	Serge	6350	haswell_set_pipeconf(crtc);
2327	Serge	6351
3746	Serge	6352	intel_set_pipe_csc(crtc);
3480	Serge	6353
3031	serge	6354	/* Set up the display plane register */
3480	Serge	6355	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
2327	Serge	6356	POSTING_READ(DSPCNTR(plane));
		6357
3031	serge	6358	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	6359
		6360	intel_update_watermarks(dev);
		6361
		6362	return ret;
		6363	}
		6364
3746	Serge	6365	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		6366	struct intel_crtc_config *pipe_config)
		6367	{
		6368	struct drm_device *dev = crtc->base.dev;
		6369	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	6370	enum intel_display_power_domain pfit_domain;
3746	Serge	6371	uint32_t tmp;
		6372
4104	Serge	6373	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		6374	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		6375
		6376	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		6377	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		6378	enum pipe trans_edp_pipe;
		6379	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		6380	default:
		6381	WARN(1, "unknown pipe linked to edp transcoder\n");
		6382	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		6383	case TRANS_DDI_EDP_INPUT_A_ON:
		6384	trans_edp_pipe = PIPE_A;
		6385	break;
		6386	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		6387	trans_edp_pipe = PIPE_B;
		6388	break;
		6389	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		6390	trans_edp_pipe = PIPE_C;
		6391	break;
		6392	}
		6393
		6394	if (trans_edp_pipe == crtc->pipe)
		6395	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		6396	}
		6397
		6398	if (!intel_display_power_enabled(dev,
		6399	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		6400	return false;
		6401
		6402	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	6403	if (!(tmp & PIPECONF_ENABLE))
		6404	return false;
		6405
		6406	/*
4104	Serge	6407	* Haswell has only FDI/PCH transcoder A. It is which is connected to
3746	Serge	6408	* DDI E. So just check whether this pipe is wired to DDI E and whether
		6409	* the PCH transcoder is on.
		6410	*/
4104	Serge	6411	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3746	Serge	6412	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
4104	Serge	6413	I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
3746	Serge	6414	pipe_config->has_pch_encoder = true;
		6415
4104	Serge	6416	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		6417	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		6418	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3746	Serge	6419
4104	Serge	6420	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		6421	}
		6422
		6423	intel_get_pipe_timings(crtc, pipe_config);
		6424
		6425	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
		6426	if (intel_display_power_enabled(dev, pfit_domain))
		6427	ironlake_get_pfit_config(crtc, pipe_config);
		6428
		6429	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		6430	(I915_READ(IPS_CTL) & IPS_ENABLE);
		6431
		6432	pipe_config->pixel_multiplier = 1;
		6433
3746	Serge	6434	return true;
		6435	}
		6436
2330	Serge	6437	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		6438	int x, int y,
3031	serge	6439	struct drm_framebuffer *fb)
2330	Serge	6440	{
		6441	struct drm_device *dev = crtc->dev;
		6442	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	6443	struct intel_encoder *encoder;
2330	Serge	6444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	6445	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
2330	Serge	6446	int pipe = intel_crtc->pipe;
		6447	int ret;
2327	Serge	6448
3031	serge	6449	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	6450
3746	Serge	6451	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
		6452
3031	serge	6453	drm_vblank_post_modeset(dev, pipe);
2327	Serge	6454
3243	Serge	6455	if (ret != 0)
2330	Serge	6456	return ret;
3243	Serge	6457
		6458	for_each_encoder_on_crtc(dev, crtc, encoder) {
		6459	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		6460	encoder->base.base.id,
		6461	drm_get_encoder_name(&encoder->base),
		6462	mode->base.id, mode->name);
3746	Serge	6463	encoder->mode_set(encoder);
3243	Serge	6464	}
		6465
		6466	return 0;
2330	Serge	6467	}
2327	Serge	6468
2342	Serge	6469	static bool intel_eld_uptodate(struct drm_connector *connector,
		6470	int reg_eldv, uint32_t bits_eldv,
		6471	int reg_elda, uint32_t bits_elda,
		6472	int reg_edid)
		6473	{
		6474	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6475	uint8_t *eld = connector->eld;
		6476	uint32_t i;
		6477
		6478	i = I915_READ(reg_eldv);
		6479	i &= bits_eldv;
		6480
		6481	if (!eld[0])
		6482	return !i;
		6483
		6484	if (!i)
		6485	return false;
		6486
		6487	i = I915_READ(reg_elda);
		6488	i &= ~bits_elda;
		6489	I915_WRITE(reg_elda, i);
		6490
		6491	for (i = 0; i < eld[2]; i++)
		6492	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		6493	return false;
		6494
		6495	return true;
		6496	}
		6497
		6498	static void g4x_write_eld(struct drm_connector *connector,
		6499	struct drm_crtc *crtc)
		6500	{
		6501	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6502	uint8_t *eld = connector->eld;
		6503	uint32_t eldv;
		6504	uint32_t len;
		6505	uint32_t i;
		6506
		6507	i = I915_READ(G4X_AUD_VID_DID);
		6508
		6509	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		6510	eldv = G4X_ELDV_DEVCL_DEVBLC;
		6511	else
		6512	eldv = G4X_ELDV_DEVCTG;
		6513
		6514	if (intel_eld_uptodate(connector,
		6515	G4X_AUD_CNTL_ST, eldv,
		6516	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		6517	G4X_HDMIW_HDMIEDID))
		6518	return;
		6519
		6520	i = I915_READ(G4X_AUD_CNTL_ST);
		6521	i &= ~(eldv \| G4X_ELD_ADDR);
		6522	len = (i >> 9) & 0x1f; /* ELD buffer size */
		6523	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6524
		6525	if (!eld[0])
		6526	return;
		6527
		6528	len = min_t(uint8_t, eld[2], len);
		6529	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6530	for (i = 0; i < len; i++)
		6531	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		6532
		6533	i = I915_READ(G4X_AUD_CNTL_ST);
		6534	i \|= eldv;
		6535	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6536	}
		6537
3031	serge	6538	static void haswell_write_eld(struct drm_connector *connector,
		6539	struct drm_crtc *crtc)
		6540	{
		6541	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6542	uint8_t *eld = connector->eld;
		6543	struct drm_device *dev = crtc->dev;
3480	Serge	6544	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6545	uint32_t eldv;
		6546	uint32_t i;
		6547	int len;
		6548	int pipe = to_intel_crtc(crtc)->pipe;
		6549	int tmp;
		6550
		6551	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		6552	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		6553	int aud_config = HSW_AUD_CFG(pipe);
		6554	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		6555
		6556
		6557	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		6558
		6559	/* Audio output enable */
		6560	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		6561	tmp = I915_READ(aud_cntrl_st2);
		6562	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		6563	I915_WRITE(aud_cntrl_st2, tmp);
		6564
		6565	/* Wait for 1 vertical blank */
		6566	intel_wait_for_vblank(dev, pipe);
		6567
		6568	/* Set ELD valid state */
		6569	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6570	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
3031	serge	6571	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		6572	I915_WRITE(aud_cntrl_st2, tmp);
		6573	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6574	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
3031	serge	6575
		6576	/* Enable HDMI mode */
		6577	tmp = I915_READ(aud_config);
4104	Serge	6578	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
3031	serge	6579	/* clear N_programing_enable and N_value_index */
		6580	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		6581	I915_WRITE(aud_config, tmp);
		6582
		6583	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		6584
		6585	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
3480	Serge	6586	intel_crtc->eld_vld = true;
3031	serge	6587
		6588	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6589	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6590	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		6591	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6592	} else
		6593	I915_WRITE(aud_config, 0);
		6594
		6595	if (intel_eld_uptodate(connector,
		6596	aud_cntrl_st2, eldv,
		6597	aud_cntl_st, IBX_ELD_ADDRESS,
		6598	hdmiw_hdmiedid))
		6599	return;
		6600
		6601	i = I915_READ(aud_cntrl_st2);
		6602	i &= ~eldv;
		6603	I915_WRITE(aud_cntrl_st2, i);
		6604
		6605	if (!eld[0])
		6606	return;
		6607
		6608	i = I915_READ(aud_cntl_st);
		6609	i &= ~IBX_ELD_ADDRESS;
		6610	I915_WRITE(aud_cntl_st, i);
		6611	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		6612	DRM_DEBUG_DRIVER("port num:%d\n", i);
		6613
		6614	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6615	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6616	for (i = 0; i < len; i++)
		6617	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6618
		6619	i = I915_READ(aud_cntrl_st2);
		6620	i \|= eldv;
		6621	I915_WRITE(aud_cntrl_st2, i);
		6622
		6623	}
		6624
2342	Serge	6625	static void ironlake_write_eld(struct drm_connector *connector,
		6626	struct drm_crtc *crtc)
		6627	{
		6628	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6629	uint8_t *eld = connector->eld;
		6630	uint32_t eldv;
		6631	uint32_t i;
		6632	int len;
		6633	int hdmiw_hdmiedid;
3031	serge	6634	int aud_config;
2342	Serge	6635	int aud_cntl_st;
		6636	int aud_cntrl_st2;
3031	serge	6637	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	6638
		6639	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	6640	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		6641	aud_config = IBX_AUD_CFG(pipe);
		6642	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	6643	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		6644	} else {
3031	serge	6645	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		6646	aud_config = CPT_AUD_CFG(pipe);
		6647	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	6648	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		6649	}
		6650
3031	serge	6651	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	6652
		6653	i = I915_READ(aud_cntl_st);
3031	serge	6654	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	6655	if (!i) {
		6656	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		6657	/* operate blindly on all ports */
		6658	eldv = IBX_ELD_VALIDB;
		6659	eldv \|= IBX_ELD_VALIDB << 4;
		6660	eldv \|= IBX_ELD_VALIDB << 8;
		6661	} else {
4104	Serge	6662	DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
2342	Serge	6663	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		6664	}
		6665
		6666	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6667	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6668	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	6669	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6670	} else
		6671	I915_WRITE(aud_config, 0);
2342	Serge	6672
		6673	if (intel_eld_uptodate(connector,
		6674	aud_cntrl_st2, eldv,
		6675	aud_cntl_st, IBX_ELD_ADDRESS,
		6676	hdmiw_hdmiedid))
		6677	return;
		6678
		6679	i = I915_READ(aud_cntrl_st2);
		6680	i &= ~eldv;
		6681	I915_WRITE(aud_cntrl_st2, i);
		6682
		6683	if (!eld[0])
		6684	return;
		6685
		6686	i = I915_READ(aud_cntl_st);
		6687	i &= ~IBX_ELD_ADDRESS;
		6688	I915_WRITE(aud_cntl_st, i);
		6689
		6690	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6691	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6692	for (i = 0; i < len; i++)
		6693	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6694
		6695	i = I915_READ(aud_cntrl_st2);
		6696	i \|= eldv;
		6697	I915_WRITE(aud_cntrl_st2, i);
		6698	}
		6699
		6700	void intel_write_eld(struct drm_encoder *encoder,
		6701	struct drm_display_mode *mode)
		6702	{
		6703	struct drm_crtc *crtc = encoder->crtc;
		6704	struct drm_connector *connector;
		6705	struct drm_device *dev = encoder->dev;
		6706	struct drm_i915_private *dev_priv = dev->dev_private;
		6707
		6708	connector = drm_select_eld(encoder, mode);
		6709	if (!connector)
		6710	return;
		6711
		6712	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6713	connector->base.id,
		6714	drm_get_connector_name(connector),
		6715	connector->encoder->base.id,
		6716	drm_get_encoder_name(connector->encoder));
		6717
		6718	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		6719
		6720	if (dev_priv->display.write_eld)
		6721	dev_priv->display.write_eld(connector, crtc);
		6722	}
		6723
2327	Serge	6724	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		6725	void intel_crtc_load_lut(struct drm_crtc *crtc)
		6726	{
		6727	struct drm_device *dev = crtc->dev;
		6728	struct drm_i915_private *dev_priv = dev->dev_private;
		6729	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	6730	enum pipe pipe = intel_crtc->pipe;
		6731	int palreg = PALETTE(pipe);
2327	Serge	6732	int i;
4104	Serge	6733	bool reenable_ips = false;
2327	Serge	6734
		6735	/* The clocks have to be on to load the palette. */
3031	serge	6736	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	6737	return;
		6738
4104	Serge	6739	if (!HAS_PCH_SPLIT(dev_priv->dev))
		6740	assert_pll_enabled(dev_priv, pipe);
		6741
2327	Serge	6742	/* use legacy palette for Ironlake */
		6743	if (HAS_PCH_SPLIT(dev))
4104	Serge	6744	palreg = LGC_PALETTE(pipe);
2327	Serge	6745
4104	Serge	6746	/* Workaround : Do not read or write the pipe palette/gamma data while
		6747	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		6748	*/
		6749	if (intel_crtc->config.ips_enabled &&
		6750	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		6751	GAMMA_MODE_MODE_SPLIT)) {
		6752	hsw_disable_ips(intel_crtc);
		6753	reenable_ips = true;
		6754	}
		6755
2327	Serge	6756	for (i = 0; i < 256; i++) {
		6757	I915_WRITE(palreg + 4 * i,
		6758	(intel_crtc->lut_r[i] << 16) \|
		6759	(intel_crtc->lut_g[i] << 8) \|
		6760	intel_crtc->lut_b[i]);
		6761	}
4104	Serge	6762
		6763	if (reenable_ips)
		6764	hsw_enable_ips(intel_crtc);
2327	Serge	6765	}
		6766
3031	serge	6767	#if 0
		6768	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		6769	{
		6770	struct drm_device *dev = crtc->dev;
		6771	struct drm_i915_private *dev_priv = dev->dev_private;
		6772	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6773	bool visible = base != 0;
		6774	u32 cntl;
2327	Serge	6775
3031	serge	6776	if (intel_crtc->cursor_visible == visible)
		6777	return;
2327	Serge	6778
3031	serge	6779	cntl = I915_READ(_CURACNTR);
		6780	if (visible) {
		6781	/* On these chipsets we can only modify the base whilst
		6782	* the cursor is disabled.
		6783	*/
		6784	I915_WRITE(_CURABASE, base);
2327	Serge	6785
3031	serge	6786	cntl &= ~(CURSOR_FORMAT_MASK);
		6787	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		6788	cntl \|= CURSOR_ENABLE \|
		6789	CURSOR_GAMMA_ENABLE \|
		6790	CURSOR_FORMAT_ARGB;
		6791	} else
		6792	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		6793	I915_WRITE(_CURACNTR, cntl);
2327	Serge	6794
3031	serge	6795	intel_crtc->cursor_visible = visible;
		6796	}
2327	Serge	6797
3031	serge	6798	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		6799	{
		6800	struct drm_device *dev = crtc->dev;
		6801	struct drm_i915_private *dev_priv = dev->dev_private;
		6802	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6803	int pipe = intel_crtc->pipe;
		6804	bool visible = base != 0;
2327	Serge	6805
3031	serge	6806	if (intel_crtc->cursor_visible != visible) {
		6807	uint32_t cntl = I915_READ(CURCNTR(pipe));
		6808	if (base) {
		6809	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		6810	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6811	cntl \|= pipe << 28; /* Connect to correct pipe */
		6812	} else {
		6813	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6814	cntl \|= CURSOR_MODE_DISABLE;
		6815	}
		6816	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	6817
3031	serge	6818	intel_crtc->cursor_visible = visible;
		6819	}
		6820	/* and commit changes on next vblank */
4371	Serge	6821	POSTING_READ(CURCNTR(pipe));
3031	serge	6822	I915_WRITE(CURBASE(pipe), base);
4371	Serge	6823	POSTING_READ(CURBASE(pipe));
3031	serge	6824	}
2327	Serge	6825
3031	serge	6826	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		6827	{
		6828	struct drm_device *dev = crtc->dev;
		6829	struct drm_i915_private *dev_priv = dev->dev_private;
		6830	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6831	int pipe = intel_crtc->pipe;
		6832	bool visible = base != 0;
2327	Serge	6833
3031	serge	6834	if (intel_crtc->cursor_visible != visible) {
		6835	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		6836	if (base) {
		6837	cntl &= ~CURSOR_MODE;
		6838	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6839	} else {
		6840	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6841	cntl \|= CURSOR_MODE_DISABLE;
		6842	}
4104	Serge	6843	if (IS_HASWELL(dev)) {
3480	Serge	6844	cntl \|= CURSOR_PIPE_CSC_ENABLE;
4104	Serge	6845	cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
		6846	}
3031	serge	6847	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	6848
3031	serge	6849	intel_crtc->cursor_visible = visible;
		6850	}
		6851	/* and commit changes on next vblank */
4371	Serge	6852	POSTING_READ(CURCNTR_IVB(pipe));
3031	serge	6853	I915_WRITE(CURBASE_IVB(pipe), base);
4371	Serge	6854	POSTING_READ(CURBASE_IVB(pipe));
3031	serge	6855	}
2327	Serge	6856
3031	serge	6857	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		6858	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		6859	bool on)
		6860	{
		6861	struct drm_device *dev = crtc->dev;
		6862	struct drm_i915_private *dev_priv = dev->dev_private;
		6863	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6864	int pipe = intel_crtc->pipe;
		6865	int x = intel_crtc->cursor_x;
		6866	int y = intel_crtc->cursor_y;
		6867	u32 base, pos;
		6868	bool visible;
2327	Serge	6869
3031	serge	6870	pos = 0;
2327	Serge	6871
3031	serge	6872	if (on && crtc->enabled && crtc->fb) {
		6873	base = intel_crtc->cursor_addr;
		6874	if (x > (int) crtc->fb->width)
		6875	base = 0;
2327	Serge	6876
3031	serge	6877	if (y > (int) crtc->fb->height)
		6878	base = 0;
		6879	} else
		6880	base = 0;
2327	Serge	6881
3031	serge	6882	if (x < 0) {
		6883	if (x + intel_crtc->cursor_width < 0)
		6884	base = 0;
2327	Serge	6885
3031	serge	6886	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		6887	x = -x;
		6888	}
		6889	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	6890
3031	serge	6891	if (y < 0) {
		6892	if (y + intel_crtc->cursor_height < 0)
		6893	base = 0;
2327	Serge	6894
3031	serge	6895	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		6896	y = -y;
		6897	}
		6898	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	6899
3031	serge	6900	visible = base != 0;
		6901	if (!visible && !intel_crtc->cursor_visible)
		6902	return;
2327	Serge	6903
3031	serge	6904	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		6905	I915_WRITE(CURPOS_IVB(pipe), pos);
		6906	ivb_update_cursor(crtc, base);
		6907	} else {
		6908	I915_WRITE(CURPOS(pipe), pos);
		6909	if (IS_845G(dev) \|\| IS_I865G(dev))
		6910	i845_update_cursor(crtc, base);
		6911	else
		6912	i9xx_update_cursor(crtc, base);
		6913	}
		6914	}
2327	Serge	6915
3031	serge	6916	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		6917	struct drm_file *file,
		6918	uint32_t handle,
		6919	uint32_t width, uint32_t height)
		6920	{
		6921	struct drm_device *dev = crtc->dev;
		6922	struct drm_i915_private *dev_priv = dev->dev_private;
		6923	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6924	struct drm_i915_gem_object *obj;
		6925	uint32_t addr;
		6926	int ret;
2327	Serge	6927
3031	serge	6928	/* if we want to turn off the cursor ignore width and height */
		6929	if (!handle) {
		6930	DRM_DEBUG_KMS("cursor off\n");
		6931	addr = 0;
		6932	obj = NULL;
		6933	mutex_lock(&dev->struct_mutex);
		6934	goto finish;
		6935	}
2327	Serge	6936
3031	serge	6937	/* Currently we only support 64x64 cursors */
		6938	if (width != 64 \|\| height != 64) {
		6939	DRM_ERROR("we currently only support 64x64 cursors\n");
		6940	return -EINVAL;
		6941	}
2327	Serge	6942
3031	serge	6943	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		6944	if (&obj->base == NULL)
		6945	return -ENOENT;
2327	Serge	6946
3031	serge	6947	if (obj->base.size < width * height * 4) {
		6948	DRM_ERROR("buffer is to small\n");
		6949	ret = -ENOMEM;
		6950	goto fail;
		6951	}
2327	Serge	6952
3031	serge	6953	/* we only need to pin inside GTT if cursor is non-phy */
		6954	mutex_lock(&dev->struct_mutex);
		6955	if (!dev_priv->info->cursor_needs_physical) {
3746	Serge	6956	unsigned alignment;
		6957
3031	serge	6958	if (obj->tiling_mode) {
		6959	DRM_ERROR("cursor cannot be tiled\n");
		6960	ret = -EINVAL;
		6961	goto fail_locked;
		6962	}
2327	Serge	6963
3746	Serge	6964	/* Note that the w/a also requires 2 PTE of padding following
		6965	* the bo. We currently fill all unused PTE with the shadow
		6966	* page and so we should always have valid PTE following the
		6967	* cursor preventing the VT-d warning.
		6968	*/
		6969	alignment = 0;
		6970	if (need_vtd_wa(dev))
		6971	alignment = 64*1024;
		6972
		6973	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	6974	if (ret) {
		6975	DRM_ERROR("failed to move cursor bo into the GTT\n");
		6976	goto fail_locked;
		6977	}
2327	Serge	6978
3031	serge	6979	ret = i915_gem_object_put_fence(obj);
		6980	if (ret) {
		6981	DRM_ERROR("failed to release fence for cursor");
		6982	goto fail_unpin;
		6983	}
2327	Serge	6984
4104	Serge	6985	addr = i915_gem_obj_ggtt_offset(obj);
3031	serge	6986	} else {
		6987	int align = IS_I830(dev) ? 16 * 1024 : 256;
		6988	ret = i915_gem_attach_phys_object(dev, obj,
		6989	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		6990	align);
		6991	if (ret) {
		6992	DRM_ERROR("failed to attach phys object\n");
		6993	goto fail_locked;
		6994	}
		6995	addr = obj->phys_obj->handle->busaddr;
		6996	}
2327	Serge	6997
3031	serge	6998	if (IS_GEN2(dev))
		6999	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	7000
3031	serge	7001	finish:
		7002	if (intel_crtc->cursor_bo) {
		7003	if (dev_priv->info->cursor_needs_physical) {
		7004	if (intel_crtc->cursor_bo != obj)
		7005	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		7006	} else
4104	Serge	7007	i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
3031	serge	7008	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		7009	}
2327	Serge	7010
3031	serge	7011	mutex_unlock(&dev->struct_mutex);
2327	Serge	7012
3031	serge	7013	intel_crtc->cursor_addr = addr;
		7014	intel_crtc->cursor_bo = obj;
		7015	intel_crtc->cursor_width = width;
		7016	intel_crtc->cursor_height = height;
2327	Serge	7017
4104	Serge	7018	if (intel_crtc->active)
		7019	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
2327	Serge	7020
3031	serge	7021	return 0;
		7022	fail_unpin:
4104	Serge	7023	i915_gem_object_unpin_from_display_plane(obj);
3031	serge	7024	fail_locked:
		7025	mutex_unlock(&dev->struct_mutex);
		7026	fail:
		7027	drm_gem_object_unreference_unlocked(&obj->base);
		7028	return ret;
		7029	}
2327	Serge	7030
3031	serge	7031	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		7032	{
		7033	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7034
		7035	intel_crtc->cursor_x = x;
		7036	intel_crtc->cursor_y = y;
		7037
4104	Serge	7038	if (intel_crtc->active)
		7039	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3031	serge	7040
		7041	return 0;
		7042	}
		7043	#endif
		7044
2332	Serge	7045	/** Sets the color ramps on behalf of RandR */
		7046	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		7047	u16 blue, int regno)
		7048	{
		7049	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7050
2332	Serge	7051	intel_crtc->lut_r[regno] = red >> 8;
		7052	intel_crtc->lut_g[regno] = green >> 8;
		7053	intel_crtc->lut_b[regno] = blue >> 8;
		7054	}
2327	Serge	7055
2332	Serge	7056	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		7057	u16 *blue, int regno)
		7058	{
		7059	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7060
2332	Serge	7061	*red = intel_crtc->lut_r[regno] << 8;
		7062	*green = intel_crtc->lut_g[regno] << 8;
		7063	*blue = intel_crtc->lut_b[regno] << 8;
		7064	}
2327	Serge	7065
2330	Serge	7066	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		7067	u16 *blue, uint32_t start, uint32_t size)
		7068	{
		7069	int end = (start + size > 256) ? 256 : start + size, i;
		7070	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7071
2330	Serge	7072	for (i = start; i < end; i++) {
		7073	intel_crtc->lut_r[i] = red[i] >> 8;
		7074	intel_crtc->lut_g[i] = green[i] >> 8;
		7075	intel_crtc->lut_b[i] = blue[i] >> 8;
		7076	}
2327	Serge	7077
2330	Serge	7078	intel_crtc_load_lut(crtc);
		7079	}
2327	Serge	7080
2330	Serge	7081	/* VESA 640x480x72Hz mode to set on the pipe */
		7082	static struct drm_display_mode load_detect_mode = {
		7083	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		7084	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		7085	};
2327	Serge	7086
3031	serge	7087	static struct drm_framebuffer *
		7088	intel_framebuffer_create(struct drm_device *dev,
		7089	struct drm_mode_fb_cmd2 *mode_cmd,
		7090	struct drm_i915_gem_object *obj)
		7091	{
		7092	struct intel_framebuffer *intel_fb;
		7093	int ret;
2327	Serge	7094
3031	serge	7095	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		7096	if (!intel_fb) {
		7097	drm_gem_object_unreference_unlocked(&obj->base);
		7098	return ERR_PTR(-ENOMEM);
		7099	}
2327	Serge	7100
3031	serge	7101	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		7102	if (ret) {
		7103	drm_gem_object_unreference_unlocked(&obj->base);
		7104	kfree(intel_fb);
		7105	return ERR_PTR(ret);
		7106	}
2327	Serge	7107
3031	serge	7108	return &intel_fb->base;
		7109	}
2327	Serge	7110
2330	Serge	7111	static u32
		7112	intel_framebuffer_pitch_for_width(int width, int bpp)
		7113	{
		7114	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		7115	return ALIGN(pitch, 64);
		7116	}
2327	Serge	7117
2330	Serge	7118	static u32
		7119	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		7120	{
		7121	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		7122	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		7123	}
2327	Serge	7124
2330	Serge	7125	static struct drm_framebuffer *
		7126	intel_framebuffer_create_for_mode(struct drm_device *dev,
		7127	struct drm_display_mode *mode,
		7128	int depth, int bpp)
		7129	{
		7130	struct drm_i915_gem_object *obj;
3243	Serge	7131	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	7132
4104	Serge	7133	return NULL;
2330	Serge	7134	}
2327	Serge	7135
2330	Serge	7136	static struct drm_framebuffer *
		7137	mode_fits_in_fbdev(struct drm_device *dev,
		7138	struct drm_display_mode *mode)
		7139	{
		7140	struct drm_i915_private *dev_priv = dev->dev_private;
		7141	struct drm_i915_gem_object *obj;
		7142	struct drm_framebuffer *fb;
2327	Serge	7143
4280	Serge	7144	if (dev_priv->fbdev == NULL)
		7145	return NULL;
2327	Serge	7146
4280	Serge	7147	obj = dev_priv->fbdev->ifb.obj;
		7148	if (obj == NULL)
2330	Serge	7149	return NULL;
2327	Serge	7150
4280	Serge	7151	fb = &dev_priv->fbdev->ifb.base;
3031	serge	7152	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		7153	fb->bits_per_pixel))
4280	Serge	7154	return NULL;
2327	Serge	7155
3031	serge	7156	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		7157	return NULL;
		7158
4280	Serge	7159	return fb;
2330	Serge	7160	}
2327	Serge	7161
3031	serge	7162	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7163	struct drm_display_mode *mode,
		7164	struct intel_load_detect_pipe *old)
		7165	{
		7166	struct intel_crtc *intel_crtc;
3031	serge	7167	struct intel_encoder *intel_encoder =
		7168	intel_attached_encoder(connector);
2330	Serge	7169	struct drm_crtc *possible_crtc;
		7170	struct drm_encoder *encoder = &intel_encoder->base;
		7171	struct drm_crtc *crtc = NULL;
		7172	struct drm_device *dev = encoder->dev;
3031	serge	7173	struct drm_framebuffer *fb;
2330	Serge	7174	int i = -1;
2327	Serge	7175
2330	Serge	7176	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7177	connector->base.id, drm_get_connector_name(connector),
		7178	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7179
2330	Serge	7180	/*
		7181	* Algorithm gets a little messy:
		7182	*
		7183	* - if the connector already has an assigned crtc, use it (but make
		7184	* sure it's on first)
		7185	*
		7186	* - try to find the first unused crtc that can drive this connector,
		7187	* and use that if we find one
		7188	*/
2327	Serge	7189
2330	Serge	7190	/* See if we already have a CRTC for this connector */
		7191	if (encoder->crtc) {
		7192	crtc = encoder->crtc;
2327	Serge	7193
3480	Serge	7194	mutex_lock(&crtc->mutex);
		7195
3031	serge	7196	old->dpms_mode = connector->dpms;
2330	Serge	7197	old->load_detect_temp = false;
2327	Serge	7198
2330	Serge	7199	/* Make sure the crtc and connector are running */
3031	serge	7200	if (connector->dpms != DRM_MODE_DPMS_ON)
		7201	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	7202
2330	Serge	7203	return true;
		7204	}
2327	Serge	7205
2330	Serge	7206	/* Find an unused one (if possible) */
		7207	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		7208	i++;
		7209	if (!(encoder->possible_crtcs & (1 << i)))
		7210	continue;
		7211	if (!possible_crtc->enabled) {
		7212	crtc = possible_crtc;
		7213	break;
		7214	}
		7215	}
2327	Serge	7216
2330	Serge	7217	/*
		7218	* If we didn't find an unused CRTC, don't use any.
		7219	*/
		7220	if (!crtc) {
		7221	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		7222	return false;
		7223	}
2327	Serge	7224
3480	Serge	7225	mutex_lock(&crtc->mutex);
3031	serge	7226	intel_encoder->new_crtc = to_intel_crtc(crtc);
		7227	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	7228
2330	Serge	7229	intel_crtc = to_intel_crtc(crtc);
3031	serge	7230	old->dpms_mode = connector->dpms;
2330	Serge	7231	old->load_detect_temp = true;
		7232	old->release_fb = NULL;
2327	Serge	7233
2330	Serge	7234	if (!mode)
		7235	mode = &load_detect_mode;
2327	Serge	7236
2330	Serge	7237	/* We need a framebuffer large enough to accommodate all accesses
		7238	* that the plane may generate whilst we perform load detection.
		7239	* We can not rely on the fbcon either being present (we get called
		7240	* during its initialisation to detect all boot displays, or it may
		7241	* not even exist) or that it is large enough to satisfy the
		7242	* requested mode.
		7243	*/
3031	serge	7244	fb = mode_fits_in_fbdev(dev, mode);
		7245	if (fb == NULL) {
2330	Serge	7246	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	7247	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		7248	old->release_fb = fb;
2330	Serge	7249	} else
		7250	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	7251	if (IS_ERR(fb)) {
2330	Serge	7252	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3480	Serge	7253	mutex_unlock(&crtc->mutex);
3243	Serge	7254	return false;
2330	Serge	7255	}
2327	Serge	7256
3480	Serge	7257	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	7258	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		7259	if (old->release_fb)
		7260	old->release_fb->funcs->destroy(old->release_fb);
3480	Serge	7261	mutex_unlock(&crtc->mutex);
3243	Serge	7262	return false;
2330	Serge	7263	}
2327	Serge	7264
2330	Serge	7265	/* let the connector get through one full cycle before testing */
		7266	intel_wait_for_vblank(dev, intel_crtc->pipe);
		7267	return true;
		7268	}
2327	Serge	7269
3031	serge	7270	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7271	struct intel_load_detect_pipe *old)
		7272	{
3031	serge	7273	struct intel_encoder *intel_encoder =
		7274	intel_attached_encoder(connector);
2330	Serge	7275	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	7276	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	7277
2330	Serge	7278	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7279	connector->base.id, drm_get_connector_name(connector),
		7280	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7281
2330	Serge	7282	if (old->load_detect_temp) {
3031	serge	7283	to_intel_connector(connector)->new_encoder = NULL;
		7284	intel_encoder->new_crtc = NULL;
		7285	intel_set_mode(crtc, NULL, 0, 0, NULL);
		7286
3480	Serge	7287	if (old->release_fb) {
		7288	drm_framebuffer_unregister_private(old->release_fb);
		7289	drm_framebuffer_unreference(old->release_fb);
		7290	}
2327	Serge	7291
3480	Serge	7292	mutex_unlock(&crtc->mutex);
2330	Serge	7293	return;
		7294	}
2327	Serge	7295
2330	Serge	7296	/* Switch crtc and encoder back off if necessary */
3031	serge	7297	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		7298	connector->funcs->dpms(connector, old->dpms_mode);
3480	Serge	7299
		7300	mutex_unlock(&crtc->mutex);
2330	Serge	7301	}
2327	Serge	7302
2330	Serge	7303	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	7304	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		7305	struct intel_crtc_config *pipe_config)
2330	Serge	7306	{
4104	Serge	7307	struct drm_device *dev = crtc->base.dev;
2330	Serge	7308	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	7309	int pipe = pipe_config->cpu_transcoder;
2330	Serge	7310	u32 dpll = I915_READ(DPLL(pipe));
		7311	u32 fp;
		7312	intel_clock_t clock;
2327	Serge	7313
2330	Serge	7314	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		7315	fp = I915_READ(FP0(pipe));
		7316	else
		7317	fp = I915_READ(FP1(pipe));
2327	Serge	7318
2330	Serge	7319	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		7320	if (IS_PINEVIEW(dev)) {
		7321	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		7322	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7323	} else {
		7324	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		7325	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7326	}
2327	Serge	7327
2330	Serge	7328	if (!IS_GEN2(dev)) {
		7329	if (IS_PINEVIEW(dev))
		7330	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		7331	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		7332	else
		7333	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		7334	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	7335
2330	Serge	7336	switch (dpll & DPLL_MODE_MASK) {
		7337	case DPLLB_MODE_DAC_SERIAL:
		7338	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		7339	5 : 10;
		7340	break;
		7341	case DPLLB_MODE_LVDS:
		7342	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		7343	7 : 14;
		7344	break;
		7345	default:
		7346	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		7347	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	7348	pipe_config->adjusted_mode.clock = 0;
		7349	return;
2330	Serge	7350	}
2327	Serge	7351
4104	Serge	7352	if (IS_PINEVIEW(dev))
		7353	pineview_clock(96000, &clock);
		7354	else
		7355	i9xx_clock(96000, &clock);
2330	Serge	7356	} else {
		7357	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	7358
2330	Serge	7359	if (is_lvds) {
		7360	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		7361	DPLL_FPA01_P1_POST_DIV_SHIFT);
		7362	clock.p2 = 14;
2327	Serge	7363
2330	Serge	7364	if ((dpll & PLL_REF_INPUT_MASK) ==
		7365	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		7366	/* XXX: might not be 66MHz */
4104	Serge	7367	i9xx_clock(66000, &clock);
2330	Serge	7368	} else
4104	Serge	7369	i9xx_clock(48000, &clock);
2330	Serge	7370	} else {
		7371	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		7372	clock.p1 = 2;
		7373	else {
		7374	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		7375	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		7376	}
		7377	if (dpll & PLL_P2_DIVIDE_BY_4)
		7378	clock.p2 = 4;
		7379	else
		7380	clock.p2 = 2;
2327	Serge	7381
4104	Serge	7382	i9xx_clock(48000, &clock);
2330	Serge	7383	}
		7384	}
2327	Serge	7385
4104	Serge	7386	pipe_config->adjusted_mode.clock = clock.dot;
		7387	}
		7388
		7389	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		7390	struct intel_crtc_config *pipe_config)
		7391	{
		7392	struct drm_device *dev = crtc->base.dev;
		7393	struct drm_i915_private *dev_priv = dev->dev_private;
		7394	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		7395	int link_freq, repeat;
		7396	u64 clock;
		7397	u32 link_m, link_n;
		7398
		7399	repeat = pipe_config->pixel_multiplier;
		7400
		7401	/*
		7402	* The calculation for the data clock is:
		7403	* pixel_clock = ((m/n)(link_clock nr_lanes * repeat))/bpp
		7404	* But we want to avoid losing precison if possible, so:
		7405	* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
		7406	*
		7407	* and the link clock is simpler:
		7408	* link_clock = (m * link_clock * repeat) / n
2330	Serge	7409	*/
2327	Serge	7410
4104	Serge	7411	/*
		7412	* We need to get the FDI or DP link clock here to derive
		7413	* the M/N dividers.
		7414	*
		7415	* For FDI, we read it from the BIOS or use a fixed 2.7GHz.
		7416	* For DP, it's either 1.62GHz or 2.7GHz.
		7417	* We do our calculations in 10*MHz since we don't need much precison.
		7418	*/
		7419	if (pipe_config->has_pch_encoder)
		7420	link_freq = intel_fdi_link_freq(dev) * 10000;
		7421	else
		7422	link_freq = pipe_config->port_clock;
		7423
		7424	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
		7425	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
		7426
		7427	if (!link_m \|\| !link_n)
		7428	return;
		7429
		7430	clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
		7431	do_div(clock, link_n);
		7432
		7433	pipe_config->adjusted_mode.clock = clock;
2330	Serge	7434	}
2327	Serge	7435
2330	Serge	7436	/** Returns the currently programmed mode of the given pipe. */
		7437	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		7438	struct drm_crtc *crtc)
		7439	{
		7440	struct drm_i915_private *dev_priv = dev->dev_private;
		7441	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	7442	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	7443	struct drm_display_mode *mode;
4104	Serge	7444	struct intel_crtc_config pipe_config;
3243	Serge	7445	int htot = I915_READ(HTOTAL(cpu_transcoder));
		7446	int hsync = I915_READ(HSYNC(cpu_transcoder));
		7447	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		7448	int vsync = I915_READ(VSYNC(cpu_transcoder));
2327	Serge	7449
2330	Serge	7450	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		7451	if (!mode)
		7452	return NULL;
		7453
4104	Serge	7454	/*
		7455	* Construct a pipe_config sufficient for getting the clock info
		7456	* back out of crtc_clock_get.
		7457	*
		7458	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		7459	* to use a real value here instead.
		7460	*/
		7461	pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
		7462	pipe_config.pixel_multiplier = 1;
		7463	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		7464
		7465	mode->clock = pipe_config.adjusted_mode.clock;
2330	Serge	7466	mode->hdisplay = (htot & 0xffff) + 1;
		7467	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		7468	mode->hsync_start = (hsync & 0xffff) + 1;
		7469	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		7470	mode->vdisplay = (vtot & 0xffff) + 1;
		7471	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		7472	mode->vsync_start = (vsync & 0xffff) + 1;
		7473	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		7474
		7475	drm_mode_set_name(mode);
		7476
		7477	return mode;
		7478	}
		7479
2327	Serge	7480	static void intel_increase_pllclock(struct drm_crtc *crtc)
		7481	{
		7482	struct drm_device *dev = crtc->dev;
		7483	drm_i915_private_t *dev_priv = dev->dev_private;
		7484	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7485	int pipe = intel_crtc->pipe;
		7486	int dpll_reg = DPLL(pipe);
		7487	int dpll;
		7488
		7489	if (HAS_PCH_SPLIT(dev))
		7490	return;
		7491
		7492	if (!dev_priv->lvds_downclock_avail)
		7493	return;
		7494
		7495	dpll = I915_READ(dpll_reg);
		7496	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		7497	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		7498
3031	serge	7499	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7500
		7501	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		7502	I915_WRITE(dpll_reg, dpll);
		7503	intel_wait_for_vblank(dev, pipe);
		7504
		7505	dpll = I915_READ(dpll_reg);
		7506	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		7507	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		7508	}
		7509	}
		7510
3031	serge	7511	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		7512	{
		7513	struct drm_device *dev = crtc->dev;
		7514	drm_i915_private_t *dev_priv = dev->dev_private;
		7515	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7516
3031	serge	7517	if (HAS_PCH_SPLIT(dev))
		7518	return;
2327	Serge	7519
3031	serge	7520	if (!dev_priv->lvds_downclock_avail)
		7521	return;
2327	Serge	7522
3031	serge	7523	/*
		7524	* Since this is called by a timer, we should never get here in
		7525	* the manual case.
		7526	*/
		7527	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		7528	int pipe = intel_crtc->pipe;
		7529	int dpll_reg = DPLL(pipe);
		7530	int dpll;
2327	Serge	7531
3031	serge	7532	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	7533
3031	serge	7534	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7535
3031	serge	7536	dpll = I915_READ(dpll_reg);
		7537	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		7538	I915_WRITE(dpll_reg, dpll);
		7539	intel_wait_for_vblank(dev, pipe);
		7540	dpll = I915_READ(dpll_reg);
		7541	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		7542	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		7543	}
2327	Serge	7544
3031	serge	7545	}
2327	Serge	7546
3031	serge	7547	void intel_mark_busy(struct drm_device *dev)
		7548	{
4104	Serge	7549	struct drm_i915_private *dev_priv = dev->dev_private;
		7550
		7551	hsw_package_c8_gpu_busy(dev_priv);
		7552	i915_update_gfx_val(dev_priv);
3031	serge	7553	}
2327	Serge	7554
3031	serge	7555	void intel_mark_idle(struct drm_device *dev)
		7556	{
4104	Serge	7557	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7558	struct drm_crtc *crtc;
2327	Serge	7559
4104	Serge	7560	hsw_package_c8_gpu_idle(dev_priv);
		7561
3031	serge	7562	if (!i915_powersave)
		7563	return;
2327	Serge	7564
3031	serge	7565	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7566	if (!crtc->fb)
		7567	continue;
2327	Serge	7568
3480	Serge	7569	intel_decrease_pllclock(crtc);
3031	serge	7570	}
		7571	}
2327	Serge	7572
4104	Serge	7573	void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
		7574	struct intel_ring_buffer *ring)
3031	serge	7575	{
		7576	struct drm_device *dev = obj->base.dev;
		7577	struct drm_crtc *crtc;
2327	Serge	7578
3031	serge	7579	if (!i915_powersave)
		7580	return;
2327	Serge	7581
3031	serge	7582	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7583	if (!crtc->fb)
		7584	continue;
2327	Serge	7585
4104	Serge	7586	if (to_intel_framebuffer(crtc->fb)->obj != obj)
		7587	continue;
		7588
3480	Serge	7589	intel_increase_pllclock(crtc);
4104	Serge	7590	if (ring && intel_fbc_enabled(dev))
		7591	ring->fbc_dirty = true;
3031	serge	7592	}
		7593	}
2327	Serge	7594
2330	Serge	7595	static void intel_crtc_destroy(struct drm_crtc *crtc)
		7596	{
		7597	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7598	struct drm_device *dev = crtc->dev;
		7599	struct intel_unpin_work *work;
		7600	unsigned long flags;
2327	Serge	7601
2330	Serge	7602	spin_lock_irqsave(&dev->event_lock, flags);
		7603	work = intel_crtc->unpin_work;
		7604	intel_crtc->unpin_work = NULL;
		7605	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7606
2330	Serge	7607	if (work) {
4293	Serge	7608	cancel_work_sync(&work->work);
2330	Serge	7609	kfree(work);
		7610	}
2327	Serge	7611
2330	Serge	7612	drm_crtc_cleanup(crtc);
2327	Serge	7613
2330	Serge	7614	kfree(intel_crtc);
		7615	}
2327	Serge	7616
3031	serge	7617	#if 0
		7618	static void intel_unpin_work_fn(struct work_struct *__work)
		7619	{
		7620	struct intel_unpin_work *work =
		7621	container_of(__work, struct intel_unpin_work, work);
3243	Serge	7622	struct drm_device *dev = work->crtc->dev;
2327	Serge	7623
3243	Serge	7624	mutex_lock(&dev->struct_mutex);
3031	serge	7625	intel_unpin_fb_obj(work->old_fb_obj);
		7626	drm_gem_object_unreference(&work->pending_flip_obj->base);
		7627	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	7628
3243	Serge	7629	intel_update_fbc(dev);
		7630	mutex_unlock(&dev->struct_mutex);
		7631
		7632	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		7633	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		7634
3031	serge	7635	kfree(work);
		7636	}
2327	Serge	7637
3031	serge	7638	static void do_intel_finish_page_flip(struct drm_device *dev,
		7639	struct drm_crtc *crtc)
		7640	{
		7641	drm_i915_private_t *dev_priv = dev->dev_private;
		7642	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7643	struct intel_unpin_work *work;
		7644	unsigned long flags;
2327	Serge	7645
3031	serge	7646	/* Ignore early vblank irqs */
		7647	if (intel_crtc == NULL)
		7648	return;
2327	Serge	7649
3031	serge	7650	spin_lock_irqsave(&dev->event_lock, flags);
		7651	work = intel_crtc->unpin_work;
3243	Serge	7652
		7653	/* Ensure we don't miss a work->pending update ... */
		7654	smp_rmb();
		7655
		7656	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	7657	spin_unlock_irqrestore(&dev->event_lock, flags);
		7658	return;
		7659	}
2327	Serge	7660
3243	Serge	7661	/* and that the unpin work is consistent wrt ->pending. */
		7662	smp_rmb();
		7663
3031	serge	7664	intel_crtc->unpin_work = NULL;
2327	Serge	7665
3243	Serge	7666	if (work->event)
		7667	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	7668
3031	serge	7669	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7670
3031	serge	7671	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7672
3480	Serge	7673	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	7674
3243	Serge	7675	queue_work(dev_priv->wq, &work->work);
		7676
3031	serge	7677	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		7678	}
2327	Serge	7679
3031	serge	7680	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		7681	{
		7682	drm_i915_private_t *dev_priv = dev->dev_private;
		7683	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	7684
3031	serge	7685	do_intel_finish_page_flip(dev, crtc);
		7686	}
2327	Serge	7687
3031	serge	7688	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		7689	{
		7690	drm_i915_private_t *dev_priv = dev->dev_private;
		7691	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	7692
3031	serge	7693	do_intel_finish_page_flip(dev, crtc);
		7694	}
2327	Serge	7695
3031	serge	7696	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		7697	{
		7698	drm_i915_private_t *dev_priv = dev->dev_private;
		7699	struct intel_crtc *intel_crtc =
		7700	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		7701	unsigned long flags;
2327	Serge	7702
3243	Serge	7703	/* NB: An MMIO update of the plane base pointer will also
		7704	* generate a page-flip completion irq, i.e. every modeset
		7705	* is also accompanied by a spurious intel_prepare_page_flip().
		7706	*/
3031	serge	7707	spin_lock_irqsave(&dev->event_lock, flags);
3243	Serge	7708	if (intel_crtc->unpin_work)
		7709	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	7710	spin_unlock_irqrestore(&dev->event_lock, flags);
		7711	}
2327	Serge	7712
3243	Serge	7713	inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
		7714	{
		7715	/* Ensure that the work item is consistent when activating it ... */
		7716	smp_wmb();
		7717	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		7718	/* and that it is marked active as soon as the irq could fire. */
		7719	smp_wmb();
		7720	}
		7721
3031	serge	7722	static int intel_gen2_queue_flip(struct drm_device *dev,
		7723	struct drm_crtc *crtc,
		7724	struct drm_framebuffer *fb,
4104	Serge	7725	struct drm_i915_gem_object *obj,
		7726	uint32_t flags)
3031	serge	7727	{
		7728	struct drm_i915_private *dev_priv = dev->dev_private;
		7729	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7730	u32 flip_mask;
		7731	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7732	int ret;
2327	Serge	7733
3031	serge	7734	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7735	if (ret)
		7736	goto err;
2327	Serge	7737
3031	serge	7738	ret = intel_ring_begin(ring, 6);
		7739	if (ret)
		7740	goto err_unpin;
2327	Serge	7741
3031	serge	7742	/* Can't queue multiple flips, so wait for the previous
		7743	* one to finish before executing the next.
		7744	*/
		7745	if (intel_crtc->plane)
		7746	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7747	else
		7748	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7749	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7750	intel_ring_emit(ring, MI_NOOP);
		7751	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7752	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7753	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7754	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7755	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	7756
		7757	intel_mark_page_flip_active(intel_crtc);
3031	serge	7758	intel_ring_advance(ring);
		7759	return 0;
2327	Serge	7760
3031	serge	7761	err_unpin:
		7762	intel_unpin_fb_obj(obj);
		7763	err:
		7764	return ret;
		7765	}
2327	Serge	7766
3031	serge	7767	static int intel_gen3_queue_flip(struct drm_device *dev,
		7768	struct drm_crtc *crtc,
		7769	struct drm_framebuffer *fb,
4104	Serge	7770	struct drm_i915_gem_object *obj,
		7771	uint32_t flags)
3031	serge	7772	{
		7773	struct drm_i915_private *dev_priv = dev->dev_private;
		7774	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7775	u32 flip_mask;
		7776	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7777	int ret;
2327	Serge	7778
3031	serge	7779	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7780	if (ret)
		7781	goto err;
2327	Serge	7782
3031	serge	7783	ret = intel_ring_begin(ring, 6);
		7784	if (ret)
		7785	goto err_unpin;
2327	Serge	7786
3031	serge	7787	if (intel_crtc->plane)
		7788	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7789	else
		7790	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7791	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7792	intel_ring_emit(ring, MI_NOOP);
		7793	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		7794	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7795	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7796	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7797	intel_ring_emit(ring, MI_NOOP);
2327	Serge	7798
3243	Serge	7799	intel_mark_page_flip_active(intel_crtc);
3031	serge	7800	intel_ring_advance(ring);
		7801	return 0;
2327	Serge	7802
3031	serge	7803	err_unpin:
		7804	intel_unpin_fb_obj(obj);
		7805	err:
		7806	return ret;
		7807	}
2327	Serge	7808
3031	serge	7809	static int intel_gen4_queue_flip(struct drm_device *dev,
		7810	struct drm_crtc *crtc,
		7811	struct drm_framebuffer *fb,
4104	Serge	7812	struct drm_i915_gem_object *obj,
		7813	uint32_t flags)
3031	serge	7814	{
		7815	struct drm_i915_private *dev_priv = dev->dev_private;
		7816	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7817	uint32_t pf, pipesrc;
		7818	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7819	int ret;
2327	Serge	7820
3031	serge	7821	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7822	if (ret)
		7823	goto err;
2327	Serge	7824
3031	serge	7825	ret = intel_ring_begin(ring, 4);
		7826	if (ret)
		7827	goto err_unpin;
2327	Serge	7828
3031	serge	7829	/* i965+ uses the linear or tiled offsets from the
		7830	* Display Registers (which do not change across a page-flip)
		7831	* so we need only reprogram the base address.
		7832	*/
		7833	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7834	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7835	intel_ring_emit(ring, fb->pitches[0]);
		7836	intel_ring_emit(ring,
4104	Serge	7837	(i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) \|
3031	serge	7838	obj->tiling_mode);
2327	Serge	7839
3031	serge	7840	/* XXX Enabling the panel-fitter across page-flip is so far
		7841	* untested on non-native modes, so ignore it for now.
		7842	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		7843	*/
		7844	pf = 0;
		7845	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7846	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7847
		7848	intel_mark_page_flip_active(intel_crtc);
3031	serge	7849	intel_ring_advance(ring);
		7850	return 0;
2327	Serge	7851
3031	serge	7852	err_unpin:
		7853	intel_unpin_fb_obj(obj);
		7854	err:
		7855	return ret;
		7856	}
2327	Serge	7857
3031	serge	7858	static int intel_gen6_queue_flip(struct drm_device *dev,
		7859	struct drm_crtc *crtc,
		7860	struct drm_framebuffer *fb,
4104	Serge	7861	struct drm_i915_gem_object *obj,
		7862	uint32_t flags)
3031	serge	7863	{
		7864	struct drm_i915_private *dev_priv = dev->dev_private;
		7865	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7866	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7867	uint32_t pf, pipesrc;
		7868	int ret;
2327	Serge	7869
3031	serge	7870	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7871	if (ret)
		7872	goto err;
2327	Serge	7873
3031	serge	7874	ret = intel_ring_begin(ring, 4);
		7875	if (ret)
		7876	goto err_unpin;
2327	Serge	7877
3031	serge	7878	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7879	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7880	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
4104	Serge	7881	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	7882
3031	serge	7883	/* Contrary to the suggestions in the documentation,
		7884	* "Enable Panel Fitter" does not seem to be required when page
		7885	* flipping with a non-native mode, and worse causes a normal
		7886	* modeset to fail.
		7887	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		7888	*/
		7889	pf = 0;
		7890	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7891	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7892
		7893	intel_mark_page_flip_active(intel_crtc);
3031	serge	7894	intel_ring_advance(ring);
		7895	return 0;
2327	Serge	7896
3031	serge	7897	err_unpin:
		7898	intel_unpin_fb_obj(obj);
		7899	err:
		7900	return ret;
		7901	}
2327	Serge	7902
3031	serge	7903	static int intel_gen7_queue_flip(struct drm_device *dev,
		7904	struct drm_crtc *crtc,
		7905	struct drm_framebuffer *fb,
4104	Serge	7906	struct drm_i915_gem_object *obj,
		7907	uint32_t flags)
3031	serge	7908	{
		7909	struct drm_i915_private *dev_priv = dev->dev_private;
		7910	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	7911	struct intel_ring_buffer *ring;
3031	serge	7912	uint32_t plane_bit = 0;
4104	Serge	7913	int len, ret;
2327	Serge	7914
4104	Serge	7915	ring = obj->ring;
		7916	if (IS_VALLEYVIEW(dev) \|\| ring == NULL \|\| ring->id != RCS)
		7917	ring = &dev_priv->ring[BCS];
		7918
3031	serge	7919	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7920	if (ret)
		7921	goto err;
2327	Serge	7922
3031	serge	7923	switch(intel_crtc->plane) {
		7924	case PLANE_A:
		7925	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		7926	break;
		7927	case PLANE_B:
		7928	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		7929	break;
		7930	case PLANE_C:
		7931	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		7932	break;
		7933	default:
		7934	WARN_ONCE(1, "unknown plane in flip command\n");
		7935	ret = -ENODEV;
		7936	goto err_unpin;
		7937	}
2327	Serge	7938
4104	Serge	7939	len = 4;
		7940	if (ring->id == RCS)
		7941	len += 6;
		7942
		7943	ret = intel_ring_begin(ring, len);
3031	serge	7944	if (ret)
		7945	goto err_unpin;
2327	Serge	7946
4104	Serge	7947	/* Unmask the flip-done completion message. Note that the bspec says that
		7948	* we should do this for both the BCS and RCS, and that we must not unmask
		7949	* more than one flip event at any time (or ensure that one flip message
		7950	* can be sent by waiting for flip-done prior to queueing new flips).
		7951	* Experimentation says that BCS works despite DERRMR masking all
		7952	* flip-done completion events and that unmasking all planes at once
		7953	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		7954	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		7955	*/
		7956	if (ring->id == RCS) {
		7957	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		7958	intel_ring_emit(ring, DERRMR);
		7959	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		7960	DERRMR_PIPEB_PRI_FLIP_DONE \|
		7961	DERRMR_PIPEC_PRI_FLIP_DONE));
		7962	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
		7963	intel_ring_emit(ring, DERRMR);
		7964	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
		7965	}
		7966
3031	serge	7967	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		7968	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
4104	Serge	7969	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7970	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	7971
		7972	intel_mark_page_flip_active(intel_crtc);
3031	serge	7973	intel_ring_advance(ring);
		7974	return 0;
2327	Serge	7975
3031	serge	7976	err_unpin:
		7977	intel_unpin_fb_obj(obj);
		7978	err:
		7979	return ret;
		7980	}
2327	Serge	7981
3031	serge	7982	static int intel_default_queue_flip(struct drm_device *dev,
		7983	struct drm_crtc *crtc,
		7984	struct drm_framebuffer *fb,
4104	Serge	7985	struct drm_i915_gem_object *obj,
		7986	uint32_t flags)
3031	serge	7987	{
		7988	return -ENODEV;
		7989	}
2327	Serge	7990
3031	serge	7991	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		7992	struct drm_framebuffer *fb,
4104	Serge	7993	struct drm_pending_vblank_event *event,
		7994	uint32_t page_flip_flags)
3031	serge	7995	{
		7996	struct drm_device *dev = crtc->dev;
		7997	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	7998	struct drm_framebuffer *old_fb = crtc->fb;
		7999	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
3031	serge	8000	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		8001	struct intel_unpin_work *work;
		8002	unsigned long flags;
		8003	int ret;
2327	Serge	8004
3031	serge	8005	/* Can't change pixel format via MI display flips. */
		8006	if (fb->pixel_format != crtc->fb->pixel_format)
		8007	return -EINVAL;
2327	Serge	8008
3031	serge	8009	/*
		8010	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		8011	* Note that pitch changes could also affect these register.
		8012	*/
		8013	if (INTEL_INFO(dev)->gen > 3 &&
		8014	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		8015	fb->pitches[0] != crtc->fb->pitches[0]))
		8016	return -EINVAL;
2327	Serge	8017
3031	serge	8018	work = kzalloc(sizeof *work, GFP_KERNEL);
		8019	if (work == NULL)
		8020	return -ENOMEM;
2327	Serge	8021
3031	serge	8022	work->event = event;
3243	Serge	8023	work->crtc = crtc;
3480	Serge	8024	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
3031	serge	8025	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	8026
3031	serge	8027	ret = drm_vblank_get(dev, intel_crtc->pipe);
		8028	if (ret)
		8029	goto free_work;
2327	Serge	8030
3031	serge	8031	/* We borrow the event spin lock for protecting unpin_work */
		8032	spin_lock_irqsave(&dev->event_lock, flags);
		8033	if (intel_crtc->unpin_work) {
		8034	spin_unlock_irqrestore(&dev->event_lock, flags);
		8035	kfree(work);
		8036	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	8037
3031	serge	8038	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		8039	return -EBUSY;
		8040	}
		8041	intel_crtc->unpin_work = work;
		8042	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	8043
3243	Serge	8044	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		8045	flush_workqueue(dev_priv->wq);
		8046
3031	serge	8047	ret = i915_mutex_lock_interruptible(dev);
		8048	if (ret)
		8049	goto cleanup;
2327	Serge	8050
3031	serge	8051	/* Reference the objects for the scheduled work. */
		8052	drm_gem_object_reference(&work->old_fb_obj->base);
		8053	drm_gem_object_reference(&obj->base);
2327	Serge	8054
3031	serge	8055	crtc->fb = fb;
2327	Serge	8056
3031	serge	8057	work->pending_flip_obj = obj;
2327	Serge	8058
3031	serge	8059	work->enable_stall_check = true;
		8060
3243	Serge	8061	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	8062	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	8063
4104	Serge	8064	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
3031	serge	8065	if (ret)
		8066	goto cleanup_pending;
		8067
		8068	intel_disable_fbc(dev);
4104	Serge	8069	intel_mark_fb_busy(obj, NULL);
3031	serge	8070	mutex_unlock(&dev->struct_mutex);
		8071
		8072	trace_i915_flip_request(intel_crtc->plane, obj);
		8073
		8074	return 0;
		8075
		8076	cleanup_pending:
3243	Serge	8077	atomic_dec(&intel_crtc->unpin_work_count);
3480	Serge	8078	crtc->fb = old_fb;
3031	serge	8079	drm_gem_object_unreference(&work->old_fb_obj->base);
		8080	drm_gem_object_unreference(&obj->base);
		8081	mutex_unlock(&dev->struct_mutex);
		8082
		8083	cleanup:
		8084	spin_lock_irqsave(&dev->event_lock, flags);
		8085	intel_crtc->unpin_work = NULL;
		8086	spin_unlock_irqrestore(&dev->event_lock, flags);
		8087
		8088	drm_vblank_put(dev, intel_crtc->pipe);
		8089	free_work:
		8090	kfree(work);
		8091
		8092	return ret;
		8093	}
		8094	#endif
		8095
		8096	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		8097	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		8098	.load_lut = intel_crtc_load_lut,
		8099	};
		8100
		8101	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		8102	struct drm_crtc *crtc)
		8103	{
		8104	struct drm_device *dev;
		8105	struct drm_crtc *tmp;
		8106	int crtc_mask = 1;
		8107
		8108	WARN(!crtc, "checking null crtc?\n");
		8109
		8110	dev = crtc->dev;
		8111
		8112	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		8113	if (tmp == crtc)
		8114	break;
		8115	crtc_mask <<= 1;
		8116	}
		8117
		8118	if (encoder->possible_crtcs & crtc_mask)
		8119	return true;
		8120	return false;
		8121	}
		8122
		8123	/**
		8124	* intel_modeset_update_staged_output_state
		8125	*
		8126	* Updates the staged output configuration state, e.g. after we've read out the
		8127	* current hw state.
		8128	*/
		8129	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		8130	{
		8131	struct intel_encoder *encoder;
		8132	struct intel_connector *connector;
		8133
		8134	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8135	base.head) {
		8136	connector->new_encoder =
		8137	to_intel_encoder(connector->base.encoder);
		8138	}
		8139
		8140	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8141	base.head) {
		8142	encoder->new_crtc =
		8143	to_intel_crtc(encoder->base.crtc);
		8144	}
		8145	}
		8146
		8147	/**
		8148	* intel_modeset_commit_output_state
		8149	*
		8150	* This function copies the stage display pipe configuration to the real one.
		8151	*/
		8152	static void intel_modeset_commit_output_state(struct drm_device *dev)
		8153	{
		8154	struct intel_encoder *encoder;
		8155	struct intel_connector *connector;
		8156
		8157	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8158	base.head) {
		8159	connector->base.encoder = &connector->new_encoder->base;
		8160	}
		8161
		8162	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8163	base.head) {
		8164	encoder->base.crtc = &encoder->new_crtc->base;
		8165	}
		8166	}
		8167
4104	Serge	8168	static void
		8169	connected_sink_compute_bpp(struct intel_connector * connector,
		8170	struct intel_crtc_config *pipe_config)
		8171	{
		8172	int bpp = pipe_config->pipe_bpp;
		8173
		8174	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		8175	connector->base.base.id,
		8176	drm_get_connector_name(&connector->base));
		8177
		8178	/* Don't use an invalid EDID bpc value */
		8179	if (connector->base.display_info.bpc &&
		8180	connector->base.display_info.bpc * 3 < bpp) {
		8181	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		8182	bpp, connector->base.display_info.bpc*3);
		8183	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		8184	}
		8185
		8186	/* Clamp bpp to 8 on screens without EDID 1.4 */
		8187	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		8188	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
		8189	bpp);
		8190	pipe_config->pipe_bpp = 24;
		8191	}
		8192	}
		8193
3746	Serge	8194	static int
4104	Serge	8195	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
3746	Serge	8196	struct drm_framebuffer *fb,
		8197	struct intel_crtc_config *pipe_config)
		8198	{
4104	Serge	8199	struct drm_device *dev = crtc->base.dev;
		8200	struct intel_connector *connector;
3746	Serge	8201	int bpp;
		8202
		8203	switch (fb->pixel_format) {
		8204	case DRM_FORMAT_C8:
		8205	bpp = 83; / since we go through a colormap */
		8206	break;
		8207	case DRM_FORMAT_XRGB1555:
		8208	case DRM_FORMAT_ARGB1555:
		8209	/* checked in intel_framebuffer_init already */
		8210	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		8211	return -EINVAL;
		8212	case DRM_FORMAT_RGB565:
		8213	bpp = 63; / min is 18bpp */
		8214	break;
		8215	case DRM_FORMAT_XBGR8888:
		8216	case DRM_FORMAT_ABGR8888:
		8217	/* checked in intel_framebuffer_init already */
		8218	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8219	return -EINVAL;
		8220	case DRM_FORMAT_XRGB8888:
		8221	case DRM_FORMAT_ARGB8888:
		8222	bpp = 8*3;
		8223	break;
		8224	case DRM_FORMAT_XRGB2101010:
		8225	case DRM_FORMAT_ARGB2101010:
		8226	case DRM_FORMAT_XBGR2101010:
		8227	case DRM_FORMAT_ABGR2101010:
		8228	/* checked in intel_framebuffer_init already */
		8229	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8230	return -EINVAL;
		8231	bpp = 10*3;
		8232	break;
		8233	/* TODO: gen4+ supports 16 bpc floating point, too. */
		8234	default:
		8235	DRM_DEBUG_KMS("unsupported depth\n");
		8236	return -EINVAL;
		8237	}
		8238
		8239	pipe_config->pipe_bpp = bpp;
		8240
		8241	/* Clamp display bpp to EDID value */
		8242	list_for_each_entry(connector, &dev->mode_config.connector_list,
4104	Serge	8243	base.head) {
		8244	if (!connector->new_encoder \|\|
		8245	connector->new_encoder->new_crtc != crtc)
3746	Serge	8246	continue;
		8247
4104	Serge	8248	connected_sink_compute_bpp(connector, pipe_config);
3746	Serge	8249	}
		8250
		8251	return bpp;
		8252	}
		8253
4104	Serge	8254	static void intel_dump_pipe_config(struct intel_crtc *crtc,
		8255	struct intel_crtc_config *pipe_config,
		8256	const char *context)
		8257	{
		8258	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		8259	context, pipe_name(crtc->pipe));
		8260
		8261	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		8262	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		8263	pipe_config->pipe_bpp, pipe_config->dither);
		8264	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		8265	pipe_config->has_pch_encoder,
		8266	pipe_config->fdi_lanes,
		8267	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		8268	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		8269	pipe_config->fdi_m_n.tu);
		8270	DRM_DEBUG_KMS("requested mode:\n");
		8271	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
		8272	DRM_DEBUG_KMS("adjusted mode:\n");
		8273	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
		8274	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		8275	pipe_config->gmch_pfit.control,
		8276	pipe_config->gmch_pfit.pgm_ratios,
		8277	pipe_config->gmch_pfit.lvds_border_bits);
		8278	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		8279	pipe_config->pch_pfit.pos,
		8280	pipe_config->pch_pfit.size,
		8281	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		8282	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
		8283	}
		8284
		8285	static bool check_encoder_cloning(struct drm_crtc *crtc)
		8286	{
		8287	int num_encoders = 0;
		8288	bool uncloneable_encoders = false;
		8289	struct intel_encoder *encoder;
		8290
		8291	list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
		8292	base.head) {
		8293	if (&encoder->new_crtc->base != crtc)
		8294	continue;
		8295
		8296	num_encoders++;
		8297	if (!encoder->cloneable)
		8298	uncloneable_encoders = true;
		8299	}
		8300
		8301	return !(num_encoders > 1 && uncloneable_encoders);
		8302	}
		8303
3746	Serge	8304	static struct intel_crtc_config *
		8305	intel_modeset_pipe_config(struct drm_crtc *crtc,
		8306	struct drm_framebuffer *fb,
3031	serge	8307	struct drm_display_mode *mode)
		8308	{
		8309	struct drm_device *dev = crtc->dev;
		8310	struct intel_encoder *encoder;
3746	Serge	8311	struct intel_crtc_config *pipe_config;
4104	Serge	8312	int plane_bpp, ret = -EINVAL;
		8313	bool retry = true;
3031	serge	8314
4104	Serge	8315	if (!check_encoder_cloning(crtc)) {
		8316	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		8317	return ERR_PTR(-EINVAL);
		8318	}
		8319
3746	Serge	8320	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		8321	if (!pipe_config)
3031	serge	8322	return ERR_PTR(-ENOMEM);
		8323
3746	Serge	8324	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		8325	drm_mode_copy(&pipe_config->requested_mode, mode);
4104	Serge	8326	pipe_config->cpu_transcoder =
		8327	(enum transcoder) to_intel_crtc(crtc)->pipe;
		8328	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
3746	Serge	8329
4104	Serge	8330	/*
		8331	* Sanitize sync polarity flags based on requested ones. If neither
		8332	* positive or negative polarity is requested, treat this as meaning
		8333	* negative polarity.
		8334	*/
		8335	if (!(pipe_config->adjusted_mode.flags &
		8336	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
		8337	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		8338
		8339	if (!(pipe_config->adjusted_mode.flags &
		8340	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
		8341	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		8342
		8343	/* Compute a starting value for pipe_config->pipe_bpp taking the source
		8344	* plane pixel format and any sink constraints into account. Returns the
		8345	* source plane bpp so that dithering can be selected on mismatches
		8346	* after encoders and crtc also have had their say. */
		8347	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		8348	fb, pipe_config);
3746	Serge	8349	if (plane_bpp < 0)
		8350	goto fail;
		8351
4104	Serge	8352	encoder_retry:
		8353	/* Ensure the port clock defaults are reset when retrying. */
		8354	pipe_config->port_clock = 0;
		8355	pipe_config->pixel_multiplier = 1;
		8356
		8357	/* Fill in default crtc timings, allow encoders to overwrite them. */
		8358	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
		8359
3031	serge	8360	/* Pass our mode to the connectors and the CRTC to give them a chance to
		8361	* adjust it according to limitations or connector properties, and also
		8362	* a chance to reject the mode entirely.
2330	Serge	8363	*/
3031	serge	8364	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8365	base.head) {
2327	Serge	8366
3031	serge	8367	if (&encoder->new_crtc->base != crtc)
		8368	continue;
3746	Serge	8369
		8370	if (!(encoder->compute_config(encoder, pipe_config))) {
		8371	DRM_DEBUG_KMS("Encoder config failure\n");
		8372	goto fail;
		8373	}
		8374	}
		8375
4104	Serge	8376	/* Set default port clock if not overwritten by the encoder. Needs to be
		8377	* done afterwards in case the encoder adjusts the mode. */
		8378	if (!pipe_config->port_clock)
		8379	pipe_config->port_clock = pipe_config->adjusted_mode.clock;
2327	Serge	8380
4104	Serge	8381	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		8382	if (ret < 0) {
3031	serge	8383	DRM_DEBUG_KMS("CRTC fixup failed\n");
		8384	goto fail;
		8385	}
2327	Serge	8386
4104	Serge	8387	if (ret == RETRY) {
		8388	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		8389	ret = -EINVAL;
		8390	goto fail;
		8391	}
		8392
		8393	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		8394	retry = false;
		8395	goto encoder_retry;
		8396	}
		8397
3746	Serge	8398	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		8399	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		8400	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		8401
		8402	return pipe_config;
3031	serge	8403	fail:
3746	Serge	8404	kfree(pipe_config);
4104	Serge	8405	return ERR_PTR(ret);
3031	serge	8406	}
2327	Serge	8407
3031	serge	8408	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		8409	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		8410	static void
		8411	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		8412	unsigned prepare_pipes, unsigned disable_pipes)
		8413	{
		8414	struct intel_crtc *intel_crtc;
		8415	struct drm_device *dev = crtc->dev;
		8416	struct intel_encoder *encoder;
		8417	struct intel_connector *connector;
		8418	struct drm_crtc *tmp_crtc;
		8419
		8420	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		8421
		8422	/* Check which crtcs have changed outputs connected to them, these need
		8423	* to be part of the prepare_pipes mask. We don't (yet) support global
		8424	* modeset across multiple crtcs, so modeset_pipes will only have one
		8425	* bit set at most. */
		8426	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8427	base.head) {
		8428	if (connector->base.encoder == &connector->new_encoder->base)
		8429	continue;
		8430
		8431	if (connector->base.encoder) {
		8432	tmp_crtc = connector->base.encoder->crtc;
		8433
		8434	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8435	}
		8436
		8437	if (connector->new_encoder)
		8438	*prepare_pipes \|=
		8439	1 << connector->new_encoder->new_crtc->pipe;
		8440	}
		8441
		8442	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8443	base.head) {
		8444	if (encoder->base.crtc == &encoder->new_crtc->base)
		8445	continue;
		8446
		8447	if (encoder->base.crtc) {
		8448	tmp_crtc = encoder->base.crtc;
		8449
		8450	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8451	}
		8452
		8453	if (encoder->new_crtc)
		8454	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		8455	}
		8456
		8457	/* Check for any pipes that will be fully disabled ... */
		8458	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8459	base.head) {
		8460	bool used = false;
		8461
		8462	/* Don't try to disable disabled crtcs. */
		8463	if (!intel_crtc->base.enabled)
		8464	continue;
		8465
		8466	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8467	base.head) {
		8468	if (encoder->new_crtc == intel_crtc)
		8469	used = true;
		8470	}
		8471
		8472	if (!used)
		8473	*disable_pipes \|= 1 << intel_crtc->pipe;
		8474	}
		8475
		8476
		8477	/* set_mode is also used to update properties on life display pipes. */
		8478	intel_crtc = to_intel_crtc(crtc);
		8479	if (crtc->enabled)
		8480	*prepare_pipes \|= 1 << intel_crtc->pipe;
		8481
3746	Serge	8482	/*
		8483	* For simplicity do a full modeset on any pipe where the output routing
		8484	* changed. We could be more clever, but that would require us to be
		8485	* more careful with calling the relevant encoder->mode_set functions.
		8486	*/
3031	serge	8487	if (*prepare_pipes)
		8488	modeset_pipes = prepare_pipes;
		8489
		8490	/* ... and mask these out. */
		8491	modeset_pipes &= ~(disable_pipes);
		8492	prepare_pipes &= ~(disable_pipes);
3746	Serge	8493
		8494	/*
		8495	* HACK: We don't (yet) fully support global modesets. intel_set_config
		8496	* obies this rule, but the modeset restore mode of
		8497	* intel_modeset_setup_hw_state does not.
		8498	*/
		8499	*modeset_pipes &= 1 << intel_crtc->pipe;
		8500	*prepare_pipes &= 1 << intel_crtc->pipe;
4104	Serge	8501
		8502	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		8503	modeset_pipes, prepare_pipes, *disable_pipes);
2330	Serge	8504	}
2327	Serge	8505
3031	serge	8506	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	8507	{
3031	serge	8508	struct drm_encoder *encoder;
2330	Serge	8509	struct drm_device *dev = crtc->dev;
2327	Serge	8510
3031	serge	8511	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		8512	if (encoder->crtc == crtc)
		8513	return true;
		8514
		8515	return false;
		8516	}
		8517
		8518	static void
		8519	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		8520	{
		8521	struct intel_encoder *intel_encoder;
		8522	struct intel_crtc *intel_crtc;
		8523	struct drm_connector *connector;
		8524
		8525	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		8526	base.head) {
		8527	if (!intel_encoder->base.crtc)
		8528	continue;
		8529
		8530	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		8531
		8532	if (prepare_pipes & (1 << intel_crtc->pipe))
		8533	intel_encoder->connectors_active = false;
		8534	}
		8535
		8536	intel_modeset_commit_output_state(dev);
		8537
		8538	/* Update computed state. */
		8539	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8540	base.head) {
		8541	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		8542	}
		8543
		8544	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8545	if (!connector->encoder \|\| !connector->encoder->crtc)
		8546	continue;
		8547
		8548	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		8549
		8550	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		8551	struct drm_property *dpms_property =
		8552	dev->mode_config.dpms_property;
		8553
		8554	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	8555	drm_object_property_set_value(&connector->base,
3031	serge	8556	dpms_property,
		8557	DRM_MODE_DPMS_ON);
		8558
		8559	intel_encoder = to_intel_encoder(connector->encoder);
		8560	intel_encoder->connectors_active = true;
		8561	}
		8562	}
		8563
		8564	}
		8565
4104	Serge	8566	static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
		8567	struct intel_crtc_config *new)
		8568	{
		8569	int clock1, clock2, diff;
		8570
		8571	clock1 = cur->adjusted_mode.clock;
		8572	clock2 = new->adjusted_mode.clock;
		8573
		8574	if (clock1 == clock2)
		8575	return true;
		8576
		8577	if (!clock1 \|\| !clock2)
		8578	return false;
		8579
		8580	diff = abs(clock1 - clock2);
		8581
		8582	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		8583	return true;
		8584
		8585	return false;
		8586	}
		8587
3031	serge	8588	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		8589	list_for_each_entry((intel_crtc), \
		8590	&(dev)->mode_config.crtc_list, \
		8591	base.head) \
4104	Serge	8592	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	8593
3746	Serge	8594	static bool
4104	Serge	8595	intel_pipe_config_compare(struct drm_device *dev,
		8596	struct intel_crtc_config *current_config,
3746	Serge	8597	struct intel_crtc_config *pipe_config)
		8598	{
4104	Serge	8599	#define PIPE_CONF_CHECK_X(name) \
		8600	if (current_config->name != pipe_config->name) { \
		8601	DRM_ERROR("mismatch in " #name " " \
		8602	"(expected 0x%08x, found 0x%08x)\n", \
		8603	current_config->name, \
		8604	pipe_config->name); \
		8605	return false; \
3746	Serge	8606	}
		8607
4104	Serge	8608	#define PIPE_CONF_CHECK_I(name) \
		8609	if (current_config->name != pipe_config->name) { \
		8610	DRM_ERROR("mismatch in " #name " " \
		8611	"(expected %i, found %i)\n", \
		8612	current_config->name, \
		8613	pipe_config->name); \
		8614	return false; \
		8615	}
		8616
		8617	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		8618	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		8619	DRM_ERROR("mismatch in " #name "(" #mask ") " \
		8620	"(expected %i, found %i)\n", \
		8621	current_config->name & (mask), \
		8622	pipe_config->name & (mask)); \
		8623	return false; \
		8624	}
		8625
		8626	#define PIPE_CONF_QUIRK(quirk) \
		8627	((current_config->quirks \| pipe_config->quirks) & (quirk))
		8628
		8629	PIPE_CONF_CHECK_I(cpu_transcoder);
		8630
		8631	PIPE_CONF_CHECK_I(has_pch_encoder);
		8632	PIPE_CONF_CHECK_I(fdi_lanes);
		8633	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
		8634	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
		8635	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
		8636	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
		8637	PIPE_CONF_CHECK_I(fdi_m_n.tu);
		8638
		8639	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
		8640	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
		8641	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
		8642	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
		8643	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
		8644	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
		8645
		8646	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
		8647	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
		8648	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
		8649	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
		8650	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
		8651	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
		8652
		8653	PIPE_CONF_CHECK_I(pixel_multiplier);
		8654
		8655	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8656	DRM_MODE_FLAG_INTERLACE);
		8657
		8658	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		8659	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8660	DRM_MODE_FLAG_PHSYNC);
		8661	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8662	DRM_MODE_FLAG_NHSYNC);
		8663	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8664	DRM_MODE_FLAG_PVSYNC);
		8665	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8666	DRM_MODE_FLAG_NVSYNC);
		8667	}
		8668
		8669	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
		8670	PIPE_CONF_CHECK_I(requested_mode.vdisplay);
		8671
		8672	PIPE_CONF_CHECK_I(gmch_pfit.control);
		8673	/* pfit ratios are autocomputed by the hw on gen4+ */
		8674	if (INTEL_INFO(dev)->gen < 4)
		8675	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
		8676	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
		8677	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		8678	if (current_config->pch_pfit.enabled) {
		8679	PIPE_CONF_CHECK_I(pch_pfit.pos);
		8680	PIPE_CONF_CHECK_I(pch_pfit.size);
		8681	}
		8682
		8683	PIPE_CONF_CHECK_I(ips_enabled);
		8684
		8685	PIPE_CONF_CHECK_I(shared_dpll);
		8686	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		8687	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		8688	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		8689	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
		8690
4280	Serge	8691	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5)
		8692	PIPE_CONF_CHECK_I(pipe_bpp);
		8693
4104	Serge	8694	#undef PIPE_CONF_CHECK_X
		8695	#undef PIPE_CONF_CHECK_I
		8696	#undef PIPE_CONF_CHECK_FLAGS
		8697	#undef PIPE_CONF_QUIRK
		8698
		8699	if (!IS_HASWELL(dev)) {
		8700	if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
		8701	DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
		8702	current_config->adjusted_mode.clock,
		8703	pipe_config->adjusted_mode.clock);
		8704	return false;
		8705	}
		8706	}
		8707
3746	Serge	8708	return true;
		8709	}
		8710
4104	Serge	8711	static void
		8712	check_connector_state(struct drm_device *dev)
3031	serge	8713	{
		8714	struct intel_connector *connector;
		8715
		8716	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8717	base.head) {
		8718	/* This also checks the encoder/connector hw state with the
		8719	* ->get_hw_state callbacks. */
		8720	intel_connector_check_state(connector);
		8721
		8722	WARN(&connector->new_encoder->base != connector->base.encoder,
		8723	"connector's staged encoder doesn't match current encoder\n");
		8724	}
4104	Serge	8725	}
3031	serge	8726
4104	Serge	8727	static void
		8728	check_encoder_state(struct drm_device *dev)
		8729	{
		8730	struct intel_encoder *encoder;
		8731	struct intel_connector *connector;
		8732
3031	serge	8733	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8734	base.head) {
		8735	bool enabled = false;
		8736	bool active = false;
		8737	enum pipe pipe, tracked_pipe;
		8738
		8739	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		8740	encoder->base.base.id,
		8741	drm_get_encoder_name(&encoder->base));
		8742
		8743	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		8744	"encoder's stage crtc doesn't match current crtc\n");
		8745	WARN(encoder->connectors_active && !encoder->base.crtc,
		8746	"encoder's active_connectors set, but no crtc\n");
		8747
		8748	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8749	base.head) {
		8750	if (connector->base.encoder != &encoder->base)
		8751	continue;
		8752	enabled = true;
		8753	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		8754	active = true;
		8755	}
		8756	WARN(!!encoder->base.crtc != enabled,
		8757	"encoder's enabled state mismatch "
		8758	"(expected %i, found %i)\n",
		8759	!!encoder->base.crtc, enabled);
		8760	WARN(active && !encoder->base.crtc,
		8761	"active encoder with no crtc\n");
		8762
		8763	WARN(encoder->connectors_active != active,
		8764	"encoder's computed active state doesn't match tracked active state "
		8765	"(expected %i, found %i)\n", active, encoder->connectors_active);
		8766
		8767	active = encoder->get_hw_state(encoder, &pipe);
		8768	WARN(active != encoder->connectors_active,
		8769	"encoder's hw state doesn't match sw tracking "
		8770	"(expected %i, found %i)\n",
		8771	encoder->connectors_active, active);
		8772
		8773	if (!encoder->base.crtc)
		8774	continue;
		8775
		8776	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		8777	WARN(active && pipe != tracked_pipe,
		8778	"active encoder's pipe doesn't match"
		8779	"(expected %i, found %i)\n",
		8780	tracked_pipe, pipe);
		8781
		8782	}
4104	Serge	8783	}
3031	serge	8784
4104	Serge	8785	static void
		8786	check_crtc_state(struct drm_device *dev)
		8787	{
		8788	drm_i915_private_t *dev_priv = dev->dev_private;
		8789	struct intel_crtc *crtc;
		8790	struct intel_encoder *encoder;
		8791	struct intel_crtc_config pipe_config;
		8792
3031	serge	8793	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8794	base.head) {
		8795	bool enabled = false;
		8796	bool active = false;
		8797
4104	Serge	8798	memset(&pipe_config, 0, sizeof(pipe_config));
		8799
3031	serge	8800	DRM_DEBUG_KMS("[CRTC:%d]\n",
		8801	crtc->base.base.id);
		8802
		8803	WARN(crtc->active && !crtc->base.enabled,
		8804	"active crtc, but not enabled in sw tracking\n");
		8805
		8806	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8807	base.head) {
		8808	if (encoder->base.crtc != &crtc->base)
		8809	continue;
		8810	enabled = true;
		8811	if (encoder->connectors_active)
		8812	active = true;
		8813	}
4104	Serge	8814
3031	serge	8815	WARN(active != crtc->active,
		8816	"crtc's computed active state doesn't match tracked active state "
		8817	"(expected %i, found %i)\n", active, crtc->active);
		8818	WARN(enabled != crtc->base.enabled,
		8819	"crtc's computed enabled state doesn't match tracked enabled state "
		8820	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		8821
3746	Serge	8822	active = dev_priv->display.get_pipe_config(crtc,
		8823	&pipe_config);
		8824
		8825	/* hw state is inconsistent with the pipe A quirk */
		8826	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		8827	active = crtc->active;
		8828
4104	Serge	8829	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8830	base.head) {
		8831	enum pipe pipe;
		8832	if (encoder->base.crtc != &crtc->base)
		8833	continue;
		8834	if (encoder->get_config &&
		8835	encoder->get_hw_state(encoder, &pipe))
		8836	encoder->get_config(encoder, &pipe_config);
		8837	}
		8838
		8839	if (dev_priv->display.get_clock)
		8840	dev_priv->display.get_clock(crtc, &pipe_config);
		8841
3746	Serge	8842	WARN(crtc->active != active,
		8843	"crtc active state doesn't match with hw state "
		8844	"(expected %i, found %i)\n", crtc->active, active);
		8845
4104	Serge	8846	if (active &&
		8847	!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
		8848	WARN(1, "pipe state doesn't match!\n");
		8849	intel_dump_pipe_config(crtc, &pipe_config,
		8850	"[hw state]");
		8851	intel_dump_pipe_config(crtc, &crtc->config,
		8852	"[sw state]");
		8853	}
3031	serge	8854	}
		8855	}
		8856
4104	Serge	8857	static void
		8858	check_shared_dpll_state(struct drm_device *dev)
		8859	{
		8860	drm_i915_private_t *dev_priv = dev->dev_private;
		8861	struct intel_crtc *crtc;
		8862	struct intel_dpll_hw_state dpll_hw_state;
		8863	int i;
		8864
		8865	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		8866	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		8867	int enabled_crtcs = 0, active_crtcs = 0;
		8868	bool active;
		8869
		8870	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		8871
		8872	DRM_DEBUG_KMS("%s\n", pll->name);
		8873
		8874	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		8875
		8876	WARN(pll->active > pll->refcount,
		8877	"more active pll users than references: %i vs %i\n",
		8878	pll->active, pll->refcount);
		8879	WARN(pll->active && !pll->on,
		8880	"pll in active use but not on in sw tracking\n");
		8881	WARN(pll->on && !pll->active,
		8882	"pll in on but not on in use in sw tracking\n");
		8883	WARN(pll->on != active,
		8884	"pll on state mismatch (expected %i, found %i)\n",
		8885	pll->on, active);
		8886
		8887	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8888	base.head) {
		8889	if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
		8890	enabled_crtcs++;
		8891	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		8892	active_crtcs++;
		8893	}
		8894	WARN(pll->active != active_crtcs,
		8895	"pll active crtcs mismatch (expected %i, found %i)\n",
		8896	pll->active, active_crtcs);
		8897	WARN(pll->refcount != enabled_crtcs,
		8898	"pll enabled crtcs mismatch (expected %i, found %i)\n",
		8899	pll->refcount, enabled_crtcs);
		8900
		8901	WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
		8902	sizeof(dpll_hw_state)),
		8903	"pll hw state mismatch\n");
		8904	}
		8905	}
		8906
		8907	void
		8908	intel_modeset_check_state(struct drm_device *dev)
		8909	{
		8910	check_connector_state(dev);
		8911	check_encoder_state(dev);
		8912	check_crtc_state(dev);
		8913	check_shared_dpll_state(dev);
		8914	}
		8915
3746	Serge	8916	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	8917	struct drm_display_mode *mode,
		8918	int x, int y, struct drm_framebuffer *fb)
		8919	{
		8920	struct drm_device *dev = crtc->dev;
		8921	drm_i915_private_t *dev_priv = dev->dev_private;
3746	Serge	8922	struct drm_display_mode saved_mode, saved_hwmode;
		8923	struct intel_crtc_config *pipe_config = NULL;
3031	serge	8924	struct intel_crtc *intel_crtc;
		8925	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	8926	int ret = 0;
3031	serge	8927
3480	Serge	8928	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
		8929	if (!saved_mode)
		8930	return -ENOMEM;
		8931	saved_hwmode = saved_mode + 1;
		8932
3031	serge	8933	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		8934	&prepare_pipes, &disable_pipes);
		8935
3480	Serge	8936	*saved_hwmode = crtc->hwmode;
		8937	*saved_mode = crtc->mode;
3031	serge	8938
		8939	/* Hack: Because we don't (yet) support global modeset on multiple
		8940	* crtcs, we don't keep track of the new mode for more than one crtc.
		8941	* Hence simply check whether any bit is set in modeset_pipes in all the
		8942	* pieces of code that are not yet converted to deal with mutliple crtcs
		8943	* changing their mode at the same time. */
		8944	if (modeset_pipes) {
3746	Serge	8945	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		8946	if (IS_ERR(pipe_config)) {
		8947	ret = PTR_ERR(pipe_config);
		8948	pipe_config = NULL;
		8949
3480	Serge	8950	goto out;
3031	serge	8951	}
4104	Serge	8952	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		8953	"[modeset]");
3031	serge	8954	}
		8955
3746	Serge	8956	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		8957	intel_crtc_disable(&intel_crtc->base);
		8958
3031	serge	8959	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		8960	if (intel_crtc->base.enabled)
		8961	dev_priv->display.crtc_disable(&intel_crtc->base);
		8962	}
		8963
		8964	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		8965	* to set it here already despite that we pass it down the callchain.
2330	Serge	8966	*/
3746	Serge	8967	if (modeset_pipes) {
3031	serge	8968	crtc->mode = *mode;
3746	Serge	8969	/* mode_set/enable/disable functions rely on a correct pipe
		8970	* config. */
		8971	to_intel_crtc(crtc)->config = *pipe_config;
		8972	}
2327	Serge	8973
3031	serge	8974	/* Only after disabling all output pipelines that will be changed can we
		8975	* update the the output configuration. */
		8976	intel_modeset_update_state(dev, prepare_pipes);
		8977
3243	Serge	8978	if (dev_priv->display.modeset_global_resources)
		8979	dev_priv->display.modeset_global_resources(dev);
		8980
3031	serge	8981	/* Set up the DPLL and any encoders state that needs to adjust or depend
		8982	* on the DPLL.
2330	Serge	8983	*/
3031	serge	8984	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
3480	Serge	8985	ret = intel_crtc_mode_set(&intel_crtc->base,
3031	serge	8986	x, y, fb);
3480	Serge	8987	if (ret)
3031	serge	8988	goto done;
		8989	}
		8990
		8991	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		8992	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		8993	dev_priv->display.crtc_enable(&intel_crtc->base);
		8994
		8995	if (modeset_pipes) {
		8996	/* Store real post-adjustment hardware mode. */
3746	Serge	8997	crtc->hwmode = pipe_config->adjusted_mode;
3031	serge	8998
		8999	/* Calculate and store various constants which
		9000	* are later needed by vblank and swap-completion
		9001	* timestamping. They are derived from true hwmode.
		9002	*/
		9003	drm_calc_timestamping_constants(crtc);
		9004	}
		9005
		9006	/* FIXME: add subpixel order */
		9007	done:
3480	Serge	9008	if (ret && crtc->enabled) {
		9009	crtc->hwmode = *saved_hwmode;
		9010	crtc->mode = *saved_mode;
3031	serge	9011	}
		9012
3480	Serge	9013	out:
3746	Serge	9014	kfree(pipe_config);
3480	Serge	9015	kfree(saved_mode);
3031	serge	9016	return ret;
2330	Serge	9017	}
2327	Serge	9018
4104	Serge	9019	static int intel_set_mode(struct drm_crtc *crtc,
3746	Serge	9020	struct drm_display_mode *mode,
		9021	int x, int y, struct drm_framebuffer *fb)
		9022	{
		9023	int ret;
		9024
		9025	ret = __intel_set_mode(crtc, mode, x, y, fb);
		9026
		9027	if (ret == 0)
		9028	intel_modeset_check_state(crtc->dev);
		9029
		9030	return ret;
		9031	}
		9032
3480	Serge	9033	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		9034	{
		9035	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
		9036	}
		9037
3031	serge	9038	#undef for_each_intel_crtc_masked
2327	Serge	9039
3031	serge	9040	static void intel_set_config_free(struct intel_set_config *config)
		9041	{
		9042	if (!config)
		9043	return;
		9044
		9045	kfree(config->save_connector_encoders);
		9046	kfree(config->save_encoder_crtcs);
		9047	kfree(config);
		9048	}
		9049
		9050	static int intel_set_config_save_state(struct drm_device *dev,
		9051	struct intel_set_config *config)
		9052	{
		9053	struct drm_encoder *encoder;
		9054	struct drm_connector *connector;
		9055	int count;
		9056
		9057	config->save_encoder_crtcs =
		9058	kcalloc(dev->mode_config.num_encoder,
		9059	sizeof(struct drm_crtc *), GFP_KERNEL);
		9060	if (!config->save_encoder_crtcs)
		9061	return -ENOMEM;
		9062
		9063	config->save_connector_encoders =
		9064	kcalloc(dev->mode_config.num_connector,
		9065	sizeof(struct drm_encoder *), GFP_KERNEL);
		9066	if (!config->save_connector_encoders)
		9067	return -ENOMEM;
		9068
		9069	/* Copy data. Note that driver private data is not affected.
		9070	* Should anything bad happen only the expected state is
		9071	* restored, not the drivers personal bookkeeping.
		9072	*/
		9073	count = 0;
		9074	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		9075	config->save_encoder_crtcs[count++] = encoder->crtc;
		9076	}
		9077
		9078	count = 0;
		9079	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		9080	config->save_connector_encoders[count++] = connector->encoder;
		9081	}
		9082
		9083	return 0;
		9084	}
		9085
		9086	static void intel_set_config_restore_state(struct drm_device *dev,
		9087	struct intel_set_config *config)
		9088	{
		9089	struct intel_encoder *encoder;
		9090	struct intel_connector *connector;
		9091	int count;
		9092
		9093	count = 0;
		9094	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9095	encoder->new_crtc =
		9096	to_intel_crtc(config->save_encoder_crtcs[count++]);
		9097	}
		9098
		9099	count = 0;
		9100	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		9101	connector->new_encoder =
		9102	to_intel_encoder(config->save_connector_encoders[count++]);
		9103	}
		9104	}
		9105
3746	Serge	9106	static bool
4104	Serge	9107	is_crtc_connector_off(struct drm_mode_set *set)
3746	Serge	9108	{
		9109	int i;
		9110
4104	Serge	9111	if (set->num_connectors == 0)
		9112	return false;
		9113
		9114	if (WARN_ON(set->connectors == NULL))
		9115	return false;
		9116
		9117	for (i = 0; i < set->num_connectors; i++)
		9118	if (set->connectors[i]->encoder &&
		9119	set->connectors[i]->encoder->crtc == set->crtc &&
		9120	set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
3746	Serge	9121	return true;
		9122
		9123	return false;
		9124	}
		9125
3031	serge	9126	static void
		9127	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		9128	struct intel_set_config *config)
		9129	{
		9130
		9131	/* We should be able to check here if the fb has the same properties
		9132	* and then just flip_or_move it */
4104	Serge	9133	if (is_crtc_connector_off(set)) {
3746	Serge	9134	config->mode_changed = true;
		9135	} else if (set->crtc->fb != set->fb) {
3031	serge	9136	/* If we have no fb then treat it as a full mode set */
		9137	if (set->crtc->fb == NULL) {
4104	Serge	9138	struct intel_crtc *intel_crtc =
		9139	to_intel_crtc(set->crtc);
		9140
		9141	if (intel_crtc->active && i915_fastboot) {
		9142	DRM_DEBUG_KMS("crtc has no fb, will flip\n");
		9143	config->fb_changed = true;
		9144	} else {
		9145	DRM_DEBUG_KMS("inactive crtc, full mode set\n");
3031	serge	9146	config->mode_changed = true;
4104	Serge	9147	}
3031	serge	9148	} else if (set->fb == NULL) {
		9149	config->mode_changed = true;
3746	Serge	9150	} else if (set->fb->pixel_format !=
		9151	set->crtc->fb->pixel_format) {
3031	serge	9152	config->mode_changed = true;
3746	Serge	9153	} else {
3031	serge	9154	config->fb_changed = true;
		9155	}
3746	Serge	9156	}
3031	serge	9157
		9158	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		9159	config->fb_changed = true;
		9160
		9161	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		9162	DRM_DEBUG_KMS("modes are different, full mode set\n");
		9163	drm_mode_debug_printmodeline(&set->crtc->mode);
		9164	drm_mode_debug_printmodeline(set->mode);
		9165	config->mode_changed = true;
		9166	}
4104	Serge	9167
		9168	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
		9169	set->crtc->base.id, config->mode_changed, config->fb_changed);
3031	serge	9170	}
		9171
		9172	static int
		9173	intel_modeset_stage_output_state(struct drm_device *dev,
		9174	struct drm_mode_set *set,
		9175	struct intel_set_config *config)
		9176	{
		9177	struct drm_crtc *new_crtc;
		9178	struct intel_connector *connector;
		9179	struct intel_encoder *encoder;
4104	Serge	9180	int ro;
3031	serge	9181
3480	Serge	9182	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	9183	* of connectors. For paranoia, double-check this. */
		9184	WARN_ON(!set->fb && (set->num_connectors != 0));
		9185	WARN_ON(set->fb && (set->num_connectors == 0));
		9186
		9187	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9188	base.head) {
		9189	/* Otherwise traverse passed in connector list and get encoders
		9190	* for them. */
		9191	for (ro = 0; ro < set->num_connectors; ro++) {
		9192	if (set->connectors[ro] == &connector->base) {
		9193	connector->new_encoder = connector->encoder;
		9194	break;
		9195	}
		9196	}
		9197
		9198	/* If we disable the crtc, disable all its connectors. Also, if
		9199	* the connector is on the changing crtc but not on the new
		9200	* connector list, disable it. */
		9201	if ((!set->fb \|\| ro == set->num_connectors) &&
		9202	connector->base.encoder &&
		9203	connector->base.encoder->crtc == set->crtc) {
		9204	connector->new_encoder = NULL;
		9205
		9206	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		9207	connector->base.base.id,
		9208	drm_get_connector_name(&connector->base));
		9209	}
		9210
		9211
		9212	if (&connector->new_encoder->base != connector->base.encoder) {
		9213	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		9214	config->mode_changed = true;
		9215	}
		9216	}
		9217	/* connector->new_encoder is now updated for all connectors. */
		9218
		9219	/* Update crtc of enabled connectors. */
		9220	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9221	base.head) {
		9222	if (!connector->new_encoder)
		9223	continue;
		9224
		9225	new_crtc = connector->new_encoder->base.crtc;
		9226
		9227	for (ro = 0; ro < set->num_connectors; ro++) {
		9228	if (set->connectors[ro] == &connector->base)
		9229	new_crtc = set->crtc;
		9230	}
		9231
		9232	/* Make sure the new CRTC will work with the encoder */
		9233	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		9234	new_crtc)) {
		9235	return -EINVAL;
		9236	}
		9237	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		9238
		9239	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		9240	connector->base.base.id,
		9241	drm_get_connector_name(&connector->base),
		9242	new_crtc->base.id);
		9243	}
		9244
		9245	/* Check for any encoders that needs to be disabled. */
		9246	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9247	base.head) {
		9248	list_for_each_entry(connector,
		9249	&dev->mode_config.connector_list,
		9250	base.head) {
		9251	if (connector->new_encoder == encoder) {
		9252	WARN_ON(!connector->new_encoder->new_crtc);
		9253
		9254	goto next_encoder;
		9255	}
		9256	}
		9257	encoder->new_crtc = NULL;
		9258	next_encoder:
		9259	/* Only now check for crtc changes so we don't miss encoders
		9260	* that will be disabled. */
		9261	if (&encoder->new_crtc->base != encoder->base.crtc) {
		9262	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		9263	config->mode_changed = true;
		9264	}
		9265	}
		9266	/* Now we've also updated encoder->new_crtc for all encoders. */
		9267
		9268	return 0;
		9269	}
		9270
		9271	static int intel_crtc_set_config(struct drm_mode_set *set)
		9272	{
		9273	struct drm_device *dev;
		9274	struct drm_mode_set save_set;
		9275	struct intel_set_config *config;
		9276	int ret;
		9277
		9278	BUG_ON(!set);
		9279	BUG_ON(!set->crtc);
		9280	BUG_ON(!set->crtc->helper_private);
		9281
3480	Serge	9282	/* Enforce sane interface api - has been abused by the fb helper. */
		9283	BUG_ON(!set->mode && set->fb);
		9284	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	9285
		9286	if (set->fb) {
		9287	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		9288	set->crtc->base.id, set->fb->base.id,
		9289	(int)set->num_connectors, set->x, set->y);
		9290	} else {
		9291	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		9292	}
		9293
		9294	dev = set->crtc->dev;
		9295
		9296	ret = -ENOMEM;
		9297	config = kzalloc(sizeof(*config), GFP_KERNEL);
		9298	if (!config)
		9299	goto out_config;
		9300
		9301	ret = intel_set_config_save_state(dev, config);
		9302	if (ret)
		9303	goto out_config;
		9304
		9305	save_set.crtc = set->crtc;
		9306	save_set.mode = &set->crtc->mode;
		9307	save_set.x = set->crtc->x;
		9308	save_set.y = set->crtc->y;
		9309	save_set.fb = set->crtc->fb;
		9310
		9311	/* Compute whether we need a full modeset, only an fb base update or no
		9312	* change at all. In the future we might also check whether only the
		9313	* mode changed, e.g. for LVDS where we only change the panel fitter in
		9314	* such cases. */
		9315	intel_set_config_compute_mode_changes(set, config);
		9316
		9317	ret = intel_modeset_stage_output_state(dev, set, config);
		9318	if (ret)
		9319	goto fail;
		9320
		9321	if (config->mode_changed) {
3480	Serge	9322	ret = intel_set_mode(set->crtc, set->mode,
		9323	set->x, set->y, set->fb);
3031	serge	9324	} else if (config->fb_changed) {
3746	Serge	9325	// intel_crtc_wait_for_pending_flips(set->crtc);
		9326
3031	serge	9327	ret = intel_pipe_set_base(set->crtc,
		9328	set->x, set->y, set->fb);
		9329	}
		9330
3746	Serge	9331	if (ret) {
4104	Serge	9332	DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
3746	Serge	9333	set->crtc->base.id, ret);
3031	serge	9334	fail:
		9335	intel_set_config_restore_state(dev, config);
		9336
		9337	/* Try to restore the config */
		9338	if (config->mode_changed &&
3480	Serge	9339	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	9340	save_set.x, save_set.y, save_set.fb))
		9341	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	9342	}
3031	serge	9343
		9344	out_config:
		9345	intel_set_config_free(config);
		9346	return ret;
		9347	}
		9348
2330	Serge	9349	static const struct drm_crtc_funcs intel_crtc_funcs = {
		9350	// .cursor_set = intel_crtc_cursor_set,
		9351	// .cursor_move = intel_crtc_cursor_move,
		9352	.gamma_set = intel_crtc_gamma_set,
3031	serge	9353	.set_config = intel_crtc_set_config,
2330	Serge	9354	.destroy = intel_crtc_destroy,
		9355	// .page_flip = intel_crtc_page_flip,
		9356	};
2327	Serge	9357
3243	Serge	9358	static void intel_cpu_pll_init(struct drm_device *dev)
		9359	{
3480	Serge	9360	if (HAS_DDI(dev))
3243	Serge	9361	intel_ddi_pll_init(dev);
		9362	}
		9363
4104	Serge	9364	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		9365	struct intel_shared_dpll *pll,
		9366	struct intel_dpll_hw_state *hw_state)
3031	serge	9367	{
4104	Serge	9368	uint32_t val;
3031	serge	9369
4104	Serge	9370	val = I915_READ(PCH_DPLL(pll->id));
		9371	hw_state->dpll = val;
		9372	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		9373	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		9374
		9375	return val & DPLL_VCO_ENABLE;
		9376	}
		9377
		9378	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		9379	struct intel_shared_dpll *pll)
		9380	{
		9381	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
		9382	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
		9383	}
		9384
		9385	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		9386	struct intel_shared_dpll *pll)
		9387	{
		9388	/* PCH refclock must be enabled first */
		9389	assert_pch_refclk_enabled(dev_priv);
		9390
		9391	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9392
		9393	/* Wait for the clocks to stabilize. */
		9394	POSTING_READ(PCH_DPLL(pll->id));
		9395	udelay(150);
		9396
		9397	/* The pixel multiplier can only be updated once the
		9398	* DPLL is enabled and the clocks are stable.
		9399	*
		9400	* So write it again.
		9401	*/
		9402	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9403	POSTING_READ(PCH_DPLL(pll->id));
		9404	udelay(200);
		9405	}
		9406
		9407	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		9408	struct intel_shared_dpll *pll)
		9409	{
		9410	struct drm_device *dev = dev_priv->dev;
		9411	struct intel_crtc *crtc;
		9412
		9413	/* Make sure no transcoder isn't still depending on us. */
		9414	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		9415	if (intel_crtc_to_shared_dpll(crtc) == pll)
		9416	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	9417	}
		9418
4104	Serge	9419	I915_WRITE(PCH_DPLL(pll->id), 0);
		9420	POSTING_READ(PCH_DPLL(pll->id));
		9421	udelay(200);
		9422	}
		9423
		9424	static char *ibx_pch_dpll_names[] = {
		9425	"PCH DPLL A",
		9426	"PCH DPLL B",
		9427	};
		9428
		9429	static void ibx_pch_dpll_init(struct drm_device *dev)
		9430	{
		9431	struct drm_i915_private *dev_priv = dev->dev_private;
		9432	int i;
		9433
		9434	dev_priv->num_shared_dpll = 2;
		9435
		9436	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		9437	dev_priv->shared_dplls[i].id = i;
		9438	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		9439	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		9440	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		9441	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		9442	dev_priv->shared_dplls[i].get_hw_state =
		9443	ibx_pch_dpll_get_hw_state;
3031	serge	9444	}
		9445	}
		9446
4104	Serge	9447	static void intel_shared_dpll_init(struct drm_device *dev)
		9448	{
		9449	struct drm_i915_private *dev_priv = dev->dev_private;
		9450
		9451	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		9452	ibx_pch_dpll_init(dev);
		9453	else
		9454	dev_priv->num_shared_dpll = 0;
		9455
		9456	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		9457	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
		9458	dev_priv->num_shared_dpll);
		9459	}
		9460
2330	Serge	9461	static void intel_crtc_init(struct drm_device *dev, int pipe)
		9462	{
		9463	drm_i915_private_t *dev_priv = dev->dev_private;
		9464	struct intel_crtc *intel_crtc;
		9465	int i;
2327	Serge	9466
2330	Serge	9467	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		9468	if (intel_crtc == NULL)
		9469	return;
2327	Serge	9470
2330	Serge	9471	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	9472
2330	Serge	9473	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		9474	for (i = 0; i < 256; i++) {
		9475	intel_crtc->lut_r[i] = i;
		9476	intel_crtc->lut_g[i] = i;
		9477	intel_crtc->lut_b[i] = i;
		9478	}
2327	Serge	9479
2330	Serge	9480	/* Swap pipes & planes for FBC on pre-965 */
		9481	intel_crtc->pipe = pipe;
		9482	intel_crtc->plane = pipe;
		9483	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		9484	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		9485	intel_crtc->plane = !pipe;
		9486	}
2327	Serge	9487
2330	Serge	9488	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		9489	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		9490	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		9491	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	9492
2330	Serge	9493	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
		9494	}
2327	Serge	9495
3031	serge	9496	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		9497	struct drm_file *file)
		9498	{
		9499	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		9500	struct drm_mode_object *drmmode_obj;
		9501	struct intel_crtc *crtc;
2327	Serge	9502
3482	Serge	9503	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		9504	return -ENODEV;
		9505
3031	serge	9506	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		9507	DRM_MODE_OBJECT_CRTC);
2327	Serge	9508
3031	serge	9509	if (!drmmode_obj) {
		9510	DRM_ERROR("no such CRTC id\n");
		9511	return -EINVAL;
		9512	}
2327	Serge	9513
3031	serge	9514	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		9515	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	9516
3031	serge	9517	return 0;
		9518	}
2327	Serge	9519
3031	serge	9520	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	9521	{
3031	serge	9522	struct drm_device *dev = encoder->base.dev;
		9523	struct intel_encoder *source_encoder;
2330	Serge	9524	int index_mask = 0;
		9525	int entry = 0;
2327	Serge	9526
3031	serge	9527	list_for_each_entry(source_encoder,
		9528	&dev->mode_config.encoder_list, base.head) {
		9529
		9530	if (encoder == source_encoder)
2330	Serge	9531	index_mask \|= (1 << entry);
3031	serge	9532
		9533	/* Intel hw has only one MUX where enocoders could be cloned. */
		9534	if (encoder->cloneable && source_encoder->cloneable)
		9535	index_mask \|= (1 << entry);
		9536
2330	Serge	9537	entry++;
		9538	}
2327	Serge	9539
2330	Serge	9540	return index_mask;
		9541	}
2327	Serge	9542
2330	Serge	9543	static bool has_edp_a(struct drm_device *dev)
		9544	{
		9545	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9546
2330	Serge	9547	if (!IS_MOBILE(dev))
		9548	return false;
2327	Serge	9549
2330	Serge	9550	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		9551	return false;
2327	Serge	9552
2330	Serge	9553	if (IS_GEN5(dev) &&
		9554	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		9555	return false;
2327	Serge	9556
2330	Serge	9557	return true;
		9558	}
2327	Serge	9559
2330	Serge	9560	static void intel_setup_outputs(struct drm_device *dev)
		9561	{
		9562	struct drm_i915_private *dev_priv = dev->dev_private;
		9563	struct intel_encoder *encoder;
		9564	bool dpd_is_edp = false;
2327	Serge	9565
4104	Serge	9566	intel_lvds_init(dev);
2327	Serge	9567
3746	Serge	9568	if (!IS_ULT(dev))
2330	Serge	9569	intel_crt_init(dev);
2327	Serge	9570
3480	Serge	9571	if (HAS_DDI(dev)) {
2330	Serge	9572	int found;
2327	Serge	9573
3031	serge	9574	/* Haswell uses DDI functions to detect digital outputs */
		9575	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		9576	/* DDI A only supports eDP */
		9577	if (found)
		9578	intel_ddi_init(dev, PORT_A);
		9579
		9580	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		9581	* register */
		9582	found = I915_READ(SFUSE_STRAP);
		9583
		9584	if (found & SFUSE_STRAP_DDIB_DETECTED)
		9585	intel_ddi_init(dev, PORT_B);
		9586	if (found & SFUSE_STRAP_DDIC_DETECTED)
		9587	intel_ddi_init(dev, PORT_C);
		9588	if (found & SFUSE_STRAP_DDID_DETECTED)
		9589	intel_ddi_init(dev, PORT_D);
		9590	} else if (HAS_PCH_SPLIT(dev)) {
		9591	int found;
3243	Serge	9592	dpd_is_edp = intel_dpd_is_edp(dev);
3031	serge	9593
3243	Serge	9594	if (has_edp_a(dev))
		9595	intel_dp_init(dev, DP_A, PORT_A);
		9596
3746	Serge	9597	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	9598	/* PCH SDVOB multiplex with HDMIB */
3031	serge	9599	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	9600	if (!found)
3746	Serge	9601	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	9602	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	9603	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	9604	}
2327	Serge	9605
3746	Serge	9606	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		9607	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	9608
3746	Serge	9609	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		9610	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	9611
2330	Serge	9612	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	9613	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	9614
3243	Serge	9615	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	9616	intel_dp_init(dev, PCH_DP_D, PORT_D);
		9617	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	9618	/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
4104	Serge	9619	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
		9620	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
		9621	PORT_C);
3480	Serge	9622	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
4104	Serge	9623	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
		9624	PORT_C);
		9625	}
3243	Serge	9626
3746	Serge	9627	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		9628	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		9629	PORT_B);
3480	Serge	9630	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		9631	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
3031	serge	9632	}
2330	Serge	9633	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		9634	bool found = false;
2327	Serge	9635
3746	Serge	9636	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9637	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	9638	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	9639	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		9640	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	9641	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	9642	}
2327	Serge	9643
4104	Serge	9644	if (!found && SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9645	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	9646	}
2327	Serge	9647
2330	Serge	9648	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	9649
3746	Serge	9650	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9651	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	9652	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	9653	}
2327	Serge	9654
3746	Serge	9655	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	9656
2330	Serge	9657	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		9658	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	9659	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	9660	}
4104	Serge	9661	if (SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9662	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	9663	}
2327	Serge	9664
2330	Serge	9665	if (SUPPORTS_INTEGRATED_DP(dev) &&
4104	Serge	9666	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	9667	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	9668	} else if (IS_GEN2(dev))
		9669	intel_dvo_init(dev);
2327	Serge	9670
2330	Serge	9671	// if (SUPPORTS_TV(dev))
		9672	// intel_tv_init(dev);
2327	Serge	9673
2330	Serge	9674	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9675	encoder->base.possible_crtcs = encoder->crtc_mask;
		9676	encoder->base.possible_clones =
3031	serge	9677	intel_encoder_clones(encoder);
2330	Serge	9678	}
2327	Serge	9679
3243	Serge	9680	intel_init_pch_refclk(dev);
		9681
		9682	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	9683	}
		9684
		9685
		9686
2335	Serge	9687	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		9688	// .destroy = intel_user_framebuffer_destroy,
		9689	// .create_handle = intel_user_framebuffer_create_handle,
		9690	};
2327	Serge	9691
2335	Serge	9692	int intel_framebuffer_init(struct drm_device *dev,
		9693	struct intel_framebuffer *intel_fb,
2342	Serge	9694	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	9695	struct drm_i915_gem_object *obj)
		9696	{
4104	Serge	9697	int pitch_limit;
2335	Serge	9698	int ret;
2327	Serge	9699
3243	Serge	9700	if (obj->tiling_mode == I915_TILING_Y) {
		9701	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	9702	return -EINVAL;
3243	Serge	9703	}
2327	Serge	9704
3243	Serge	9705	if (mode_cmd->pitches[0] & 63) {
		9706	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		9707	mode_cmd->pitches[0]);
		9708	return -EINVAL;
		9709	}
		9710
4104	Serge	9711	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		9712	pitch_limit = 32*1024;
		9713	} else if (INTEL_INFO(dev)->gen >= 4) {
		9714	if (obj->tiling_mode)
		9715	pitch_limit = 16*1024;
		9716	else
		9717	pitch_limit = 32*1024;
		9718	} else if (INTEL_INFO(dev)->gen >= 3) {
		9719	if (obj->tiling_mode)
		9720	pitch_limit = 8*1024;
		9721	else
		9722	pitch_limit = 16*1024;
		9723	} else
		9724	/* XXX DSPC is limited to 4k tiled */
		9725	pitch_limit = 8*1024;
		9726
		9727	if (mode_cmd->pitches[0] > pitch_limit) {
		9728	DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
		9729	obj->tiling_mode ? "tiled" : "linear",
		9730	mode_cmd->pitches[0], pitch_limit);
3243	Serge	9731	return -EINVAL;
		9732	}
		9733
		9734	if (obj->tiling_mode != I915_TILING_NONE &&
		9735	mode_cmd->pitches[0] != obj->stride) {
		9736	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		9737	mode_cmd->pitches[0], obj->stride);
2335	Serge	9738	return -EINVAL;
3243	Serge	9739	}
2327	Serge	9740
3243	Serge	9741	/* Reject formats not supported by any plane early. */
2342	Serge	9742	switch (mode_cmd->pixel_format) {
3243	Serge	9743	case DRM_FORMAT_C8:
2342	Serge	9744	case DRM_FORMAT_RGB565:
		9745	case DRM_FORMAT_XRGB8888:
3243	Serge	9746	case DRM_FORMAT_ARGB8888:
		9747	break;
		9748	case DRM_FORMAT_XRGB1555:
		9749	case DRM_FORMAT_ARGB1555:
		9750	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	9751	DRM_DEBUG("unsupported pixel format: %s\n",
		9752	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9753	return -EINVAL;
		9754	}
		9755	break;
3031	serge	9756	case DRM_FORMAT_XBGR8888:
3243	Serge	9757	case DRM_FORMAT_ABGR8888:
2342	Serge	9758	case DRM_FORMAT_XRGB2101010:
		9759	case DRM_FORMAT_ARGB2101010:
3243	Serge	9760	case DRM_FORMAT_XBGR2101010:
		9761	case DRM_FORMAT_ABGR2101010:
		9762	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	9763	DRM_DEBUG("unsupported pixel format: %s\n",
		9764	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9765	return -EINVAL;
		9766	}
2335	Serge	9767	break;
2342	Serge	9768	case DRM_FORMAT_YUYV:
		9769	case DRM_FORMAT_UYVY:
		9770	case DRM_FORMAT_YVYU:
		9771	case DRM_FORMAT_VYUY:
3243	Serge	9772	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	9773	DRM_DEBUG("unsupported pixel format: %s\n",
		9774	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9775	return -EINVAL;
		9776	}
2342	Serge	9777	break;
2335	Serge	9778	default:
4104	Serge	9779	DRM_DEBUG("unsupported pixel format: %s\n",
		9780	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	9781	return -EINVAL;
		9782	}
2327	Serge	9783
3243	Serge	9784	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		9785	if (mode_cmd->offsets[0] != 0)
		9786	return -EINVAL;
		9787
3480	Serge	9788	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		9789	intel_fb->obj = obj;
		9790
2335	Serge	9791	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		9792	if (ret) {
		9793	DRM_ERROR("framebuffer init failed %d\n", ret);
		9794	return ret;
		9795	}
2327	Serge	9796
2335	Serge	9797	return 0;
		9798	}
2327	Serge	9799
		9800
2360	Serge	9801	static const struct drm_mode_config_funcs intel_mode_funcs = {
		9802	.fb_create = NULL /intel_user_framebuffer_create/,
3480	Serge	9803	.output_poll_changed = intel_fb_output_poll_changed,
2360	Serge	9804	};
2327	Serge	9805
3031	serge	9806	/* Set up chip specific display functions */
		9807	static void intel_init_display(struct drm_device *dev)
		9808	{
		9809	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9810
4104	Serge	9811	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		9812	dev_priv->display.find_dpll = g4x_find_best_dpll;
		9813	else if (IS_VALLEYVIEW(dev))
		9814	dev_priv->display.find_dpll = vlv_find_best_dpll;
		9815	else if (IS_PINEVIEW(dev))
		9816	dev_priv->display.find_dpll = pnv_find_best_dpll;
		9817	else
		9818	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		9819
3480	Serge	9820	if (HAS_DDI(dev)) {
3746	Serge	9821	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
3243	Serge	9822	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		9823	dev_priv->display.crtc_enable = haswell_crtc_enable;
		9824	dev_priv->display.crtc_disable = haswell_crtc_disable;
		9825	dev_priv->display.off = haswell_crtc_off;
		9826	dev_priv->display.update_plane = ironlake_update_plane;
		9827	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	9828	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
4104	Serge	9829	dev_priv->display.get_clock = ironlake_crtc_clock_get;
3031	serge	9830	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		9831	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		9832	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		9833	dev_priv->display.off = ironlake_crtc_off;
		9834	dev_priv->display.update_plane = ironlake_update_plane;
4104	Serge	9835	} else if (IS_VALLEYVIEW(dev)) {
		9836	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
4398	Serge	9837	dev_priv->display.get_clock = vlv_crtc_clock_get;
4104	Serge	9838	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9839	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		9840	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9841	dev_priv->display.off = i9xx_crtc_off;
		9842	dev_priv->display.update_plane = i9xx_update_plane;
3031	serge	9843	} else {
3746	Serge	9844	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
4104	Serge	9845	dev_priv->display.get_clock = i9xx_crtc_clock_get;
3031	serge	9846	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9847	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		9848	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9849	dev_priv->display.off = i9xx_crtc_off;
		9850	dev_priv->display.update_plane = i9xx_update_plane;
		9851	}
2327	Serge	9852
3031	serge	9853	/* Returns the core display clock speed */
		9854	if (IS_VALLEYVIEW(dev))
		9855	dev_priv->display.get_display_clock_speed =
		9856	valleyview_get_display_clock_speed;
		9857	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		9858	dev_priv->display.get_display_clock_speed =
		9859	i945_get_display_clock_speed;
		9860	else if (IS_I915G(dev))
		9861	dev_priv->display.get_display_clock_speed =
		9862	i915_get_display_clock_speed;
4104	Serge	9863	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	9864	dev_priv->display.get_display_clock_speed =
		9865	i9xx_misc_get_display_clock_speed;
4104	Serge	9866	else if (IS_PINEVIEW(dev))
		9867	dev_priv->display.get_display_clock_speed =
		9868	pnv_get_display_clock_speed;
3031	serge	9869	else if (IS_I915GM(dev))
		9870	dev_priv->display.get_display_clock_speed =
		9871	i915gm_get_display_clock_speed;
		9872	else if (IS_I865G(dev))
		9873	dev_priv->display.get_display_clock_speed =
		9874	i865_get_display_clock_speed;
		9875	else if (IS_I85X(dev))
		9876	dev_priv->display.get_display_clock_speed =
		9877	i855_get_display_clock_speed;
		9878	else /* 852, 830 */
		9879	dev_priv->display.get_display_clock_speed =
		9880	i830_get_display_clock_speed;
2327	Serge	9881
3031	serge	9882	if (HAS_PCH_SPLIT(dev)) {
		9883	if (IS_GEN5(dev)) {
		9884	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		9885	dev_priv->display.write_eld = ironlake_write_eld;
		9886	} else if (IS_GEN6(dev)) {
		9887	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		9888	dev_priv->display.write_eld = ironlake_write_eld;
		9889	} else if (IS_IVYBRIDGE(dev)) {
		9890	/* FIXME: detect B0+ stepping and use auto training */
		9891	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		9892	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	9893	dev_priv->display.modeset_global_resources =
		9894	ivb_modeset_global_resources;
3031	serge	9895	} else if (IS_HASWELL(dev)) {
		9896	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		9897	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	9898	dev_priv->display.modeset_global_resources =
		9899	haswell_modeset_global_resources;
		9900	}
3031	serge	9901	} else if (IS_G4X(dev)) {
		9902	dev_priv->display.write_eld = g4x_write_eld;
		9903	}
2327	Serge	9904
3031	serge	9905	/* Default just returns -ENODEV to indicate unsupported */
		9906	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	9907
		9908
		9909
		9910
3031	serge	9911	}
		9912
		9913	/*
		9914	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		9915	* resume, or other times. This quirk makes sure that's the case for
		9916	* affected systems.
		9917	*/
		9918	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	9919	{
		9920	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9921
3031	serge	9922	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		9923	DRM_INFO("applying pipe a force quirk\n");
		9924	}
2327	Serge	9925
3031	serge	9926	/*
		9927	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		9928	*/
		9929	static void quirk_ssc_force_disable(struct drm_device *dev)
		9930	{
		9931	struct drm_i915_private *dev_priv = dev->dev_private;
		9932	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		9933	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	9934	}
2327	Serge	9935
3031	serge	9936	/*
		9937	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		9938	* brightness value
		9939	*/
		9940	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	9941	{
		9942	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9943	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		9944	DRM_INFO("applying inverted panel brightness quirk\n");
		9945	}
2327	Serge	9946
4104	Serge	9947	/*
		9948	* Some machines (Dell XPS13) suffer broken backlight controls if
		9949	* BLM_PCH_PWM_ENABLE is set.
		9950	*/
		9951	static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
		9952	{
		9953	struct drm_i915_private *dev_priv = dev->dev_private;
		9954	dev_priv->quirks \|= QUIRK_NO_PCH_PWM_ENABLE;
		9955	DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
		9956	}
		9957
3031	serge	9958	struct intel_quirk {
		9959	int device;
		9960	int subsystem_vendor;
		9961	int subsystem_device;
		9962	void (hook)(struct drm_device dev);
		9963	};
2327	Serge	9964
3031	serge	9965	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		9966	struct intel_dmi_quirk {
		9967	void (hook)(struct drm_device dev);
		9968	const struct dmi_system_id (*dmi_id_list)[];
		9969	};
2327	Serge	9970
3031	serge	9971	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		9972	{
		9973	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		9974	return 1;
2330	Serge	9975	}
2327	Serge	9976
3031	serge	9977	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		9978	{
		9979	.dmi_id_list = &(const struct dmi_system_id[]) {
		9980	{
		9981	.callback = intel_dmi_reverse_brightness,
		9982	.ident = "NCR Corporation",
		9983	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		9984	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		9985	},
		9986	},
		9987	{ } /* terminating entry */
		9988	},
		9989	.hook = quirk_invert_brightness,
		9990	},
		9991	};
2327	Serge	9992
3031	serge	9993	static struct intel_quirk intel_quirks[] = {
		9994	/* HP Mini needs pipe A force quirk (LP: #322104) */
		9995	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	9996
3031	serge	9997	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		9998	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	9999
3031	serge	10000	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		10001	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	10002
3031	serge	10003	/* 830/845 need to leave pipe A & dpll A up */
		10004	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		10005	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	10006
3031	serge	10007	/* Lenovo U160 cannot use SSC on LVDS */
		10008	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	10009
3031	serge	10010	/* Sony Vaio Y cannot use SSC on LVDS */
		10011	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	10012
3031	serge	10013	/* Acer Aspire 5734Z must invert backlight brightness */
		10014	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	10015
		10016	/* Acer/eMachines G725 */
		10017	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		10018
		10019	/* Acer/eMachines e725 */
		10020	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		10021
		10022	/* Acer/Packard Bell NCL20 */
		10023	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		10024
		10025	/* Acer Aspire 4736Z */
		10026	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
4104	Serge	10027
		10028	/* Dell XPS13 HD Sandy Bridge */
		10029	{ 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
		10030	/* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
		10031	{ 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
3031	serge	10032	};
2327	Serge	10033
3031	serge	10034	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	10035	{
3031	serge	10036	struct pci_dev *d = dev->pdev;
		10037	int i;
2327	Serge	10038
3031	serge	10039	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		10040	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	10041
3031	serge	10042	if (d->device == q->device &&
		10043	(d->subsystem_vendor == q->subsystem_vendor \|\|
		10044	q->subsystem_vendor == PCI_ANY_ID) &&
		10045	(d->subsystem_device == q->subsystem_device \|\|
		10046	q->subsystem_device == PCI_ANY_ID))
		10047	q->hook(dev);
		10048	}
2330	Serge	10049	}
2327	Serge	10050
3031	serge	10051	/* Disable the VGA plane that we never use */
		10052	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	10053	{
		10054	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10055	u8 sr1;
3480	Serge	10056	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	10057
3031	serge	10058	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		10059	out8(SR01, VGA_SR_INDEX);
		10060	sr1 = in8(VGA_SR_DATA);
		10061	out8(sr1 \| 1<<5, VGA_SR_DATA);
		10062	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		10063	udelay(300);
2327	Serge	10064
3031	serge	10065	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		10066	POSTING_READ(vga_reg);
2330	Serge	10067	}
		10068
3031	serge	10069	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	10070	{
4398	Serge	10071	struct drm_i915_private *dev_priv = dev->dev_private;
		10072
3480	Serge	10073	intel_init_power_well(dev);
2342	Serge	10074
3031	serge	10075	intel_prepare_ddi(dev);
2342	Serge	10076
3031	serge	10077	intel_init_clock_gating(dev);
		10078
4398	Serge	10079	/* Enable the CRI clock source so we can get at the display */
		10080	if (IS_VALLEYVIEW(dev))
		10081	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) \|
		10082	DPLL_INTEGRATED_CRI_CLK_VLV);
		10083
3482	Serge	10084	mutex_lock(&dev->struct_mutex);
		10085	intel_enable_gt_powersave(dev);
		10086	mutex_unlock(&dev->struct_mutex);
2342	Serge	10087	}
		10088
4398	Serge	10089	void intel_modeset_suspend_hw(struct drm_device *dev)
		10090	{
		10091	intel_suspend_hw(dev);
		10092	}
		10093
3031	serge	10094	void intel_modeset_init(struct drm_device *dev)
2330	Serge	10095	{
3031	serge	10096	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	10097	int i, j, ret;
2330	Serge	10098
3031	serge	10099	drm_mode_config_init(dev);
2330	Serge	10100
3031	serge	10101	dev->mode_config.min_width = 0;
		10102	dev->mode_config.min_height = 0;
2330	Serge	10103
3031	serge	10104	dev->mode_config.preferred_depth = 24;
		10105	dev->mode_config.prefer_shadow = 1;
2330	Serge	10106
3031	serge	10107	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	10108
3031	serge	10109	intel_init_quirks(dev);
2330	Serge	10110
3031	serge	10111	intel_init_pm(dev);
2330	Serge	10112
3746	Serge	10113	if (INTEL_INFO(dev)->num_pipes == 0)
		10114	return;
		10115
3031	serge	10116	intel_init_display(dev);
2330	Serge	10117
3031	serge	10118	if (IS_GEN2(dev)) {
		10119	dev->mode_config.max_width = 2048;
		10120	dev->mode_config.max_height = 2048;
		10121	} else if (IS_GEN3(dev)) {
		10122	dev->mode_config.max_width = 4096;
		10123	dev->mode_config.max_height = 4096;
		10124	} else {
		10125	dev->mode_config.max_width = 8192;
		10126	dev->mode_config.max_height = 8192;
		10127	}
3480	Serge	10128	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	10129
3031	serge	10130	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	10131	INTEL_INFO(dev)->num_pipes,
		10132	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	10133
4104	Serge	10134	for_each_pipe(i) {
3031	serge	10135	intel_crtc_init(dev, i);
3746	Serge	10136	for (j = 0; j < dev_priv->num_plane; j++) {
		10137	ret = intel_plane_init(dev, i, j);
3031	serge	10138	if (ret)
4104	Serge	10139	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
		10140	pipe_name(i), sprite_name(i, j), ret);
3746	Serge	10141	}
2330	Serge	10142	}
		10143
3243	Serge	10144	intel_cpu_pll_init(dev);
4104	Serge	10145	intel_shared_dpll_init(dev);
2330	Serge	10146
3031	serge	10147	/* Just disable it once at startup */
		10148	i915_disable_vga(dev);
		10149	intel_setup_outputs(dev);
3480	Serge	10150
		10151	/* Just in case the BIOS is doing something questionable. */
		10152	intel_disable_fbc(dev);
3031	serge	10153	}
2330	Serge	10154
3031	serge	10155	static void
		10156	intel_connector_break_all_links(struct intel_connector *connector)
		10157	{
		10158	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10159	connector->base.encoder = NULL;
		10160	connector->encoder->connectors_active = false;
		10161	connector->encoder->base.crtc = NULL;
2330	Serge	10162	}
		10163
3031	serge	10164	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	10165	{
3031	serge	10166	struct intel_connector *connector;
		10167	struct drm_connector *crt = NULL;
		10168	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	10169
3031	serge	10170	/* We can't just switch on the pipe A, we need to set things up with a
		10171	* proper mode and output configuration. As a gross hack, enable pipe A
		10172	* by enabling the load detect pipe once. */
		10173	list_for_each_entry(connector,
		10174	&dev->mode_config.connector_list,
		10175	base.head) {
		10176	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		10177	crt = &connector->base;
		10178	break;
2330	Serge	10179	}
		10180	}
		10181
3031	serge	10182	if (!crt)
		10183	return;
2330	Serge	10184
3031	serge	10185	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		10186	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	10187
		10188
		10189	}
		10190
3031	serge	10191	static bool
		10192	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	10193	{
3746	Serge	10194	struct drm_device *dev = crtc->base.dev;
		10195	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10196	u32 reg, val;
2327	Serge	10197
3746	Serge	10198	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	10199	return true;
2327	Serge	10200
3031	serge	10201	reg = DSPCNTR(!crtc->plane);
		10202	val = I915_READ(reg);
2327	Serge	10203
3031	serge	10204	if ((val & DISPLAY_PLANE_ENABLE) &&
		10205	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		10206	return false;
2327	Serge	10207
3031	serge	10208	return true;
2327	Serge	10209	}
		10210
3031	serge	10211	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	10212	{
3031	serge	10213	struct drm_device *dev = crtc->base.dev;
2327	Serge	10214	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10215	u32 reg;
2327	Serge	10216
3031	serge	10217	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	10218	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	10219	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	10220
3031	serge	10221	/* We need to sanitize the plane -> pipe mapping first because this will
		10222	* disable the crtc (and hence change the state) if it is wrong. Note
		10223	* that gen4+ has a fixed plane -> pipe mapping. */
		10224	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		10225	struct intel_connector *connector;
		10226	bool plane;
2327	Serge	10227
3031	serge	10228	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		10229	crtc->base.base.id);
2327	Serge	10230
3031	serge	10231	/* Pipe has the wrong plane attached and the plane is active.
		10232	* Temporarily change the plane mapping and disable everything
		10233	* ... */
		10234	plane = crtc->plane;
		10235	crtc->plane = !plane;
		10236	dev_priv->display.crtc_disable(&crtc->base);
		10237	crtc->plane = plane;
2342	Serge	10238
3031	serge	10239	/* ... and break all links. */
		10240	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10241	base.head) {
		10242	if (connector->encoder->base.crtc != &crtc->base)
		10243	continue;
2327	Serge	10244
3031	serge	10245	intel_connector_break_all_links(connector);
		10246	}
2327	Serge	10247
3031	serge	10248	WARN_ON(crtc->active);
		10249	crtc->base.enabled = false;
		10250	}
2327	Serge	10251
3031	serge	10252	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		10253	crtc->pipe == PIPE_A && !crtc->active) {
		10254	/* BIOS forgot to enable pipe A, this mostly happens after
		10255	* resume. Force-enable the pipe to fix this, the update_dpms
		10256	* call below we restore the pipe to the right state, but leave
		10257	* the required bits on. */
		10258	intel_enable_pipe_a(dev);
		10259	}
2327	Serge	10260
3031	serge	10261	/* Adjust the state of the output pipe according to whether we
		10262	* have active connectors/encoders. */
		10263	intel_crtc_update_dpms(&crtc->base);
2327	Serge	10264
3031	serge	10265	if (crtc->active != crtc->base.enabled) {
		10266	struct intel_encoder *encoder;
2327	Serge	10267
3031	serge	10268	/* This can happen either due to bugs in the get_hw_state
		10269	* functions or because the pipe is force-enabled due to the
		10270	* pipe A quirk. */
		10271	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		10272	crtc->base.base.id,
		10273	crtc->base.enabled ? "enabled" : "disabled",
		10274	crtc->active ? "enabled" : "disabled");
2327	Serge	10275
3031	serge	10276	crtc->base.enabled = crtc->active;
2327	Serge	10277
3031	serge	10278	/* Because we only establish the connector -> encoder ->
		10279	* crtc links if something is active, this means the
		10280	* crtc is now deactivated. Break the links. connector
		10281	* -> encoder links are only establish when things are
		10282	* actually up, hence no need to break them. */
		10283	WARN_ON(crtc->active);
2327	Serge	10284
3031	serge	10285	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		10286	WARN_ON(encoder->connectors_active);
		10287	encoder->base.crtc = NULL;
		10288	}
		10289	}
2327	Serge	10290	}
		10291
3031	serge	10292	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	10293	{
3031	serge	10294	struct intel_connector *connector;
		10295	struct drm_device *dev = encoder->base.dev;
2327	Serge	10296
3031	serge	10297	/* We need to check both for a crtc link (meaning that the
		10298	* encoder is active and trying to read from a pipe) and the
		10299	* pipe itself being active. */
		10300	bool has_active_crtc = encoder->base.crtc &&
		10301	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	10302
3031	serge	10303	if (encoder->connectors_active && !has_active_crtc) {
		10304	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		10305	encoder->base.base.id,
		10306	drm_get_encoder_name(&encoder->base));
2327	Serge	10307
3031	serge	10308	/* Connector is active, but has no active pipe. This is
		10309	* fallout from our resume register restoring. Disable
		10310	* the encoder manually again. */
		10311	if (encoder->base.crtc) {
		10312	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		10313	encoder->base.base.id,
		10314	drm_get_encoder_name(&encoder->base));
		10315	encoder->disable(encoder);
		10316	}
2327	Serge	10317
3031	serge	10318	/* Inconsistent output/port/pipe state happens presumably due to
		10319	* a bug in one of the get_hw_state functions. Or someplace else
		10320	* in our code, like the register restore mess on resume. Clamp
		10321	* things to off as a safer default. */
		10322	list_for_each_entry(connector,
		10323	&dev->mode_config.connector_list,
		10324	base.head) {
		10325	if (connector->encoder != encoder)
		10326	continue;
2327	Serge	10327
3031	serge	10328	intel_connector_break_all_links(connector);
		10329	}
		10330	}
		10331	/* Enabled encoders without active connectors will be fixed in
		10332	* the crtc fixup. */
2327	Serge	10333	}
		10334
3746	Serge	10335	void i915_redisable_vga(struct drm_device *dev)
		10336	{
		10337	struct drm_i915_private *dev_priv = dev->dev_private;
		10338	u32 vga_reg = i915_vgacntrl_reg(dev);
		10339
4104	Serge	10340	/* This function can be called both from intel_modeset_setup_hw_state or
		10341	* at a very early point in our resume sequence, where the power well
		10342	* structures are not yet restored. Since this function is at a very
		10343	* paranoid "someone might have enabled VGA while we were not looking"
		10344	* level, just check if the power well is enabled instead of trying to
		10345	* follow the "don't touch the power well if we don't need it" policy
		10346	* the rest of the driver uses. */
		10347	if (HAS_POWER_WELL(dev) &&
		10348	(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
		10349	return;
		10350
3746	Serge	10351	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		10352	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		10353	i915_disable_vga(dev);
		10354	}
		10355	}
		10356
4104	Serge	10357	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	10358	{
		10359	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10360	enum pipe pipe;
		10361	struct intel_crtc *crtc;
		10362	struct intel_encoder *encoder;
		10363	struct intel_connector *connector;
4104	Serge	10364	int i;
2327	Serge	10365
3746	Serge	10366	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10367	base.head) {
		10368	memset(&crtc->config, 0, sizeof(crtc->config));
2327	Serge	10369
3746	Serge	10370	crtc->active = dev_priv->display.get_pipe_config(crtc,
		10371	&crtc->config);
2327	Serge	10372
3031	serge	10373	crtc->base.enabled = crtc->active;
2330	Serge	10374
3031	serge	10375	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		10376	crtc->base.base.id,
		10377	crtc->active ? "enabled" : "disabled");
2339	Serge	10378	}
2332	Serge	10379
4104	Serge	10380	/* FIXME: Smash this into the new shared dpll infrastructure. */
3480	Serge	10381	if (HAS_DDI(dev))
3243	Serge	10382	intel_ddi_setup_hw_pll_state(dev);
		10383
4104	Serge	10384	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10385	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10386
		10387	pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		10388	pll->active = 0;
		10389	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10390	base.head) {
		10391	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		10392	pll->active++;
		10393	}
		10394	pll->refcount = pll->active;
		10395
		10396	DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
		10397	pll->name, pll->refcount, pll->on);
		10398	}
		10399
3031	serge	10400	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10401	base.head) {
		10402	pipe = 0;
2332	Serge	10403
3031	serge	10404	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	10405	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10406	encoder->base.crtc = &crtc->base;
		10407	if (encoder->get_config)
		10408	encoder->get_config(encoder, &crtc->config);
3031	serge	10409	} else {
		10410	encoder->base.crtc = NULL;
		10411	}
2332	Serge	10412
3031	serge	10413	encoder->connectors_active = false;
		10414	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		10415	encoder->base.base.id,
		10416	drm_get_encoder_name(&encoder->base),
		10417	encoder->base.crtc ? "enabled" : "disabled",
		10418	pipe);
		10419	}
2332	Serge	10420
4104	Serge	10421	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10422	base.head) {
		10423	if (!crtc->active)
		10424	continue;
		10425	if (dev_priv->display.get_clock)
		10426	dev_priv->display.get_clock(crtc,
		10427	&crtc->config);
		10428	}
		10429
3031	serge	10430	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10431	base.head) {
		10432	if (connector->get_hw_state(connector)) {
		10433	connector->base.dpms = DRM_MODE_DPMS_ON;
		10434	connector->encoder->connectors_active = true;
		10435	connector->base.encoder = &connector->encoder->base;
		10436	} else {
		10437	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10438	connector->base.encoder = NULL;
		10439	}
		10440	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		10441	connector->base.base.id,
		10442	drm_get_connector_name(&connector->base),
		10443	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	10444	}
4104	Serge	10445	}
2332	Serge	10446
4104	Serge	10447	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		10448	* and i915 state tracking structures. */
		10449	void intel_modeset_setup_hw_state(struct drm_device *dev,
		10450	bool force_restore)
		10451	{
		10452	struct drm_i915_private *dev_priv = dev->dev_private;
		10453	enum pipe pipe;
		10454	struct drm_plane *plane;
		10455	struct intel_crtc *crtc;
		10456	struct intel_encoder *encoder;
		10457	int i;
		10458
		10459	intel_modeset_readout_hw_state(dev);
		10460
		10461	/*
		10462	* Now that we have the config, copy it to each CRTC struct
		10463	* Note that this could go away if we move to using crtc_config
		10464	* checking everywhere.
		10465	*/
		10466	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10467	base.head) {
		10468	if (crtc->active && i915_fastboot) {
		10469	intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
		10470
		10471	DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
		10472	crtc->base.base.id);
		10473	drm_mode_debug_printmodeline(&crtc->base.mode);
		10474	}
		10475	}
		10476
3031	serge	10477	/* HW state is read out, now we need to sanitize this mess. */
		10478	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10479	base.head) {
		10480	intel_sanitize_encoder(encoder);
2332	Serge	10481	}
		10482
3031	serge	10483	for_each_pipe(pipe) {
		10484	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10485	intel_sanitize_crtc(crtc);
4104	Serge	10486	intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
2332	Serge	10487	}
		10488
4104	Serge	10489	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10490	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10491
		10492	if (!pll->on \|\| pll->active)
		10493	continue;
		10494
		10495	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		10496
		10497	pll->disable(dev_priv, pll);
		10498	pll->on = false;
		10499	}
		10500
3243	Serge	10501	if (force_restore) {
3746	Serge	10502	/*
		10503	* We need to use raw interfaces for restoring state to avoid
		10504	* checking (bogus) intermediate states.
		10505	*/
3243	Serge	10506	for_each_pipe(pipe) {
3746	Serge	10507	struct drm_crtc *crtc =
		10508	dev_priv->pipe_to_crtc_mapping[pipe];
		10509
		10510	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
		10511	crtc->fb);
3243	Serge	10512	}
3746	Serge	10513	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
		10514	intel_plane_restore(plane);
3243	Serge	10515
3746	Serge	10516	i915_redisable_vga(dev);
3243	Serge	10517	} else {
3031	serge	10518	intel_modeset_update_staged_output_state(dev);
3243	Serge	10519	}
2332	Serge	10520
3031	serge	10521	intel_modeset_check_state(dev);
3243	Serge	10522
		10523	drm_mode_config_reset(dev);
2332	Serge	10524	}
		10525
3031	serge	10526	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	10527	{
3031	serge	10528	intel_modeset_init_hw(dev);
2330	Serge	10529
3031	serge	10530	// intel_setup_overlay(dev);
2330	Serge	10531
4539	Serge	10532	mutex_lock(&dev->mode_config.mutex);
3243	Serge	10533	intel_modeset_setup_hw_state(dev, false);
4539	Serge	10534	mutex_unlock(&dev->mode_config.mutex);
2330	Serge	10535	}
		10536
3031	serge	10537	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	10538	{
3031	serge	10539	#if 0
		10540	struct drm_i915_private *dev_priv = dev->dev_private;
		10541	struct drm_crtc *crtc;
2327	Serge	10542
4104	Serge	10543	/*
		10544	* Interrupts and polling as the first thing to avoid creating havoc.
		10545	* Too much stuff here (turning of rps, connectors, ...) would
		10546	* experience fancy races otherwise.
		10547	*/
		10548	drm_irq_uninstall(dev);
		10549	cancel_work_sync(&dev_priv->hotplug_work);
		10550	/*
		10551	* Due to the hpd irq storm handling the hotplug work can re-arm the
		10552	* poll handlers. Hence disable polling after hpd handling is shut down.
		10553	*/
3031	serge	10554	// drm_kms_helper_poll_fini(dev);
4104	Serge	10555
3031	serge	10556	mutex_lock(&dev->struct_mutex);
2327	Serge	10557
3031	serge	10558	// intel_unregister_dsm_handler();
2327	Serge	10559
3031	serge	10560	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		10561	/* Skip inactive CRTCs */
		10562	if (!crtc->fb)
		10563	continue;
2342	Serge	10564
3031	serge	10565	intel_increase_pllclock(crtc);
		10566	}
2342	Serge	10567
3031	serge	10568	intel_disable_fbc(dev);
2342	Serge	10569
3031	serge	10570	intel_disable_gt_powersave(dev);
2342	Serge	10571
3031	serge	10572	ironlake_teardown_rc6(dev);
2327	Serge	10573
3031	serge	10574	mutex_unlock(&dev->struct_mutex);
2327	Serge	10575
4104	Serge	10576	/* flush any delayed tasks or pending work */
		10577	flush_scheduled_work();
2327	Serge	10578
4280	Serge	10579	/* destroy backlight, if any, before the connectors */
		10580	intel_panel_destroy_backlight(dev);
2327	Serge	10581
3031	serge	10582	drm_mode_config_cleanup(dev);
2327	Serge	10583	#endif
		10584	}
		10585
		10586	/*
3031	serge	10587	* Return which encoder is currently attached for connector.
2327	Serge	10588	*/
3031	serge	10589	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	10590	{
3031	serge	10591	return &intel_attached_encoder(connector)->base;
		10592	}
2327	Serge	10593
3031	serge	10594	void intel_connector_attach_encoder(struct intel_connector *connector,
		10595	struct intel_encoder *encoder)
		10596	{
		10597	connector->encoder = encoder;
		10598	drm_mode_connector_attach_encoder(&connector->base,
		10599	&encoder->base);
2327	Serge	10600	}
		10601
		10602	/*
3031	serge	10603	* set vga decode state - true == enable VGA decode
2327	Serge	10604	*/
3031	serge	10605	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	10606	{
2330	Serge	10607	struct drm_i915_private *dev_priv = dev->dev_private;
4539	Serge	10608	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
3031	serge	10609	u16 gmch_ctrl;
2327	Serge	10610
4539	Serge	10611	pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
3031	serge	10612	if (state)
		10613	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	10614	else
3031	serge	10615	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
4539	Serge	10616	pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
3031	serge	10617	return 0;
2330	Serge	10618	}
		10619
3031	serge	10620	#ifdef CONFIG_DEBUG_FS
		10621	#include
2327	Serge	10622
3031	serge	10623	struct intel_display_error_state {
4104	Serge	10624
		10625	u32 power_well_driver;
		10626
		10627	int num_transcoders;
		10628
3031	serge	10629	struct intel_cursor_error_state {
		10630	u32 control;
		10631	u32 position;
		10632	u32 base;
		10633	u32 size;
		10634	} cursor[I915_MAX_PIPES];
2327	Serge	10635
3031	serge	10636	struct intel_pipe_error_state {
		10637	u32 source;
		10638	} pipe[I915_MAX_PIPES];
2327	Serge	10639
3031	serge	10640	struct intel_plane_error_state {
		10641	u32 control;
		10642	u32 stride;
		10643	u32 size;
		10644	u32 pos;
		10645	u32 addr;
		10646	u32 surface;
		10647	u32 tile_offset;
		10648	} plane[I915_MAX_PIPES];
4104	Serge	10649
		10650	struct intel_transcoder_error_state {
		10651	enum transcoder cpu_transcoder;
		10652
		10653	u32 conf;
		10654
		10655	u32 htotal;
		10656	u32 hblank;
		10657	u32 hsync;
		10658	u32 vtotal;
		10659	u32 vblank;
		10660	u32 vsync;
		10661	} transcoder[4];
3031	serge	10662	};
2327	Serge	10663
3031	serge	10664	struct intel_display_error_state *
		10665	intel_display_capture_error_state(struct drm_device *dev)
		10666	{
		10667	drm_i915_private_t *dev_priv = dev->dev_private;
		10668	struct intel_display_error_state *error;
4104	Serge	10669	int transcoders[] = {
		10670	TRANSCODER_A,
		10671	TRANSCODER_B,
		10672	TRANSCODER_C,
		10673	TRANSCODER_EDP,
		10674	};
3031	serge	10675	int i;
2327	Serge	10676
4104	Serge	10677	if (INTEL_INFO(dev)->num_pipes == 0)
		10678	return NULL;
		10679
3031	serge	10680	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		10681	if (error == NULL)
		10682	return NULL;
2327	Serge	10683
4104	Serge	10684	if (HAS_POWER_WELL(dev))
		10685	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		10686
3031	serge	10687	for_each_pipe(i) {
3746	Serge	10688	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
3031	serge	10689	error->cursor[i].control = I915_READ(CURCNTR(i));
		10690	error->cursor[i].position = I915_READ(CURPOS(i));
		10691	error->cursor[i].base = I915_READ(CURBASE(i));
3746	Serge	10692	} else {
		10693	error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
		10694	error->cursor[i].position = I915_READ(CURPOS_IVB(i));
		10695	error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		10696	}
2327	Serge	10697
3031	serge	10698	error->plane[i].control = I915_READ(DSPCNTR(i));
		10699	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	10700	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	10701	error->plane[i].size = I915_READ(DSPSIZE(i));
		10702	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	10703	}
		10704	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	10705	error->plane[i].addr = I915_READ(DSPADDR(i));
		10706	if (INTEL_INFO(dev)->gen >= 4) {
		10707	error->plane[i].surface = I915_READ(DSPSURF(i));
		10708	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		10709	}
2327	Serge	10710
3031	serge	10711	error->pipe[i].source = I915_READ(PIPESRC(i));
		10712	}
2327	Serge	10713
4104	Serge	10714	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		10715	if (HAS_DDI(dev_priv->dev))
		10716	error->num_transcoders++; /* Account for eDP. */
		10717
		10718	for (i = 0; i < error->num_transcoders; i++) {
		10719	enum transcoder cpu_transcoder = transcoders[i];
		10720
		10721	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		10722
		10723	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		10724	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		10725	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		10726	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		10727	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		10728	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		10729	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		10730	}
		10731
		10732	/* In the code above we read the registers without checking if the power
		10733	* well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
		10734	* prevent the next I915_WRITE from detecting it and printing an error
		10735	* message. */
		10736	intel_uncore_clear_errors(dev);
		10737
3031	serge	10738	return error;
2330	Serge	10739	}
2327	Serge	10740
4104	Serge	10741	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		10742
3031	serge	10743	void
4104	Serge	10744	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	10745	struct drm_device *dev,
		10746	struct intel_display_error_state *error)
2332	Serge	10747	{
3031	serge	10748	int i;
2330	Serge	10749
4104	Serge	10750	if (!error)
		10751	return;
		10752
		10753	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
		10754	if (HAS_POWER_WELL(dev))
		10755	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		10756	error->power_well_driver);
3031	serge	10757	for_each_pipe(i) {
4104	Serge	10758	err_printf(m, "Pipe [%d]:\n", i);
		10759	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
2332	Serge	10760
4104	Serge	10761	err_printf(m, "Plane [%d]:\n", i);
		10762	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		10763	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	10764	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	10765	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		10766	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	10767	}
		10768	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	10769	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	10770	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	10771	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		10772	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	10773	}
2332	Serge	10774
4104	Serge	10775	err_printf(m, "Cursor [%d]:\n", i);
		10776	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		10777	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		10778	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	10779	}
4104	Serge	10780
		10781	for (i = 0; i < error->num_transcoders; i++) {
		10782	err_printf(m, " CPU transcoder: %c\n",
		10783	transcoder_name(error->transcoder[i].cpu_transcoder));
		10784	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		10785	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		10786	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		10787	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		10788	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		10789	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		10790	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		10791	}
2327	Serge	10792	}
3031	serge	10793	#endif

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(root)/drivers/video/drm/i915/intel_display.c – Rev 4539