WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
4104	Serge	44	#define MAX_ERRNO 4095
2327	Serge	45	phys_addr_t get_bus_addr(void);
		46
2342	Serge	47	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	48	static void intel_increase_pllclock(struct drm_crtc *crtc);
3243	Serge	49	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	50
4104	Serge	51	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		52	struct intel_crtc_config *pipe_config);
		53	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		54	struct intel_crtc_config *pipe_config);
2327	Serge	55
4104	Serge	56	static int intel_set_mode(struct drm_crtc crtc, struct drm_display_mode mode,
		57	int x, int y, struct drm_framebuffer *old_fb);
		58
		59
2327	Serge	60	typedef struct {
		61	int min, max;
		62	} intel_range_t;
		63
		64	typedef struct {
		65	int dot_limit;
		66	int p2_slow, p2_fast;
		67	} intel_p2_t;
		68
		69	typedef struct intel_limit intel_limit_t;
		70	struct intel_limit {
		71	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		72	intel_p2_t p2;
		73	};
		74
		75	/* FDI */
		76	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		77
3243	Serge	78	int
		79	intel_pch_rawclk(struct drm_device *dev)
		80	{
		81	struct drm_i915_private *dev_priv = dev->dev_private;
		82
		83	WARN_ON(!HAS_PCH_SPLIT(dev));
		84
		85	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		86	}
		87
2327	Serge	88	static inline u32 /* units of 100MHz */
		89	intel_fdi_link_freq(struct drm_device *dev)
		90	{
		91	if (IS_GEN5(dev)) {
		92	struct drm_i915_private *dev_priv = dev->dev_private;
		93	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		94	} else
		95	return 27;
		96	}
		97
4104	Serge	98	static const intel_limit_t intel_limits_i8xx_dac = {
		99	.dot = { .min = 25000, .max = 350000 },
		100	.vco = { .min = 930000, .max = 1400000 },
		101	.n = { .min = 3, .max = 16 },
		102	.m = { .min = 96, .max = 140 },
		103	.m1 = { .min = 18, .max = 26 },
		104	.m2 = { .min = 6, .max = 16 },
		105	.p = { .min = 4, .max = 128 },
		106	.p1 = { .min = 2, .max = 33 },
		107	.p2 = { .dot_limit = 165000,
		108	.p2_slow = 4, .p2_fast = 2 },
		109	};
		110
2327	Serge	111	static const intel_limit_t intel_limits_i8xx_dvo = {
		112	.dot = { .min = 25000, .max = 350000 },
		113	.vco = { .min = 930000, .max = 1400000 },
		114	.n = { .min = 3, .max = 16 },
		115	.m = { .min = 96, .max = 140 },
		116	.m1 = { .min = 18, .max = 26 },
		117	.m2 = { .min = 6, .max = 16 },
		118	.p = { .min = 4, .max = 128 },
		119	.p1 = { .min = 2, .max = 33 },
		120	.p2 = { .dot_limit = 165000,
4104	Serge	121	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	122	};
		123
		124	static const intel_limit_t intel_limits_i8xx_lvds = {
		125	.dot = { .min = 25000, .max = 350000 },
		126	.vco = { .min = 930000, .max = 1400000 },
		127	.n = { .min = 3, .max = 16 },
		128	.m = { .min = 96, .max = 140 },
		129	.m1 = { .min = 18, .max = 26 },
		130	.m2 = { .min = 6, .max = 16 },
		131	.p = { .min = 4, .max = 128 },
		132	.p1 = { .min = 1, .max = 6 },
		133	.p2 = { .dot_limit = 165000,
		134	.p2_slow = 14, .p2_fast = 7 },
		135	};
		136
		137	static const intel_limit_t intel_limits_i9xx_sdvo = {
		138	.dot = { .min = 20000, .max = 400000 },
		139	.vco = { .min = 1400000, .max = 2800000 },
		140	.n = { .min = 1, .max = 6 },
		141	.m = { .min = 70, .max = 120 },
3480	Serge	142	.m1 = { .min = 8, .max = 18 },
		143	.m2 = { .min = 3, .max = 7 },
2327	Serge	144	.p = { .min = 5, .max = 80 },
		145	.p1 = { .min = 1, .max = 8 },
		146	.p2 = { .dot_limit = 200000,
		147	.p2_slow = 10, .p2_fast = 5 },
		148	};
		149
		150	static const intel_limit_t intel_limits_i9xx_lvds = {
		151	.dot = { .min = 20000, .max = 400000 },
		152	.vco = { .min = 1400000, .max = 2800000 },
		153	.n = { .min = 1, .max = 6 },
		154	.m = { .min = 70, .max = 120 },
3480	Serge	155	.m1 = { .min = 8, .max = 18 },
		156	.m2 = { .min = 3, .max = 7 },
2327	Serge	157	.p = { .min = 7, .max = 98 },
		158	.p1 = { .min = 1, .max = 8 },
		159	.p2 = { .dot_limit = 112000,
		160	.p2_slow = 14, .p2_fast = 7 },
		161	};
		162
		163
		164	static const intel_limit_t intel_limits_g4x_sdvo = {
		165	.dot = { .min = 25000, .max = 270000 },
		166	.vco = { .min = 1750000, .max = 3500000},
		167	.n = { .min = 1, .max = 4 },
		168	.m = { .min = 104, .max = 138 },
		169	.m1 = { .min = 17, .max = 23 },
		170	.m2 = { .min = 5, .max = 11 },
		171	.p = { .min = 10, .max = 30 },
		172	.p1 = { .min = 1, .max = 3},
		173	.p2 = { .dot_limit = 270000,
		174	.p2_slow = 10,
		175	.p2_fast = 10
		176	},
		177	};
		178
		179	static const intel_limit_t intel_limits_g4x_hdmi = {
		180	.dot = { .min = 22000, .max = 400000 },
		181	.vco = { .min = 1750000, .max = 3500000},
		182	.n = { .min = 1, .max = 4 },
		183	.m = { .min = 104, .max = 138 },
		184	.m1 = { .min = 16, .max = 23 },
		185	.m2 = { .min = 5, .max = 11 },
		186	.p = { .min = 5, .max = 80 },
		187	.p1 = { .min = 1, .max = 8},
		188	.p2 = { .dot_limit = 165000,
		189	.p2_slow = 10, .p2_fast = 5 },
		190	};
		191
		192	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		193	.dot = { .min = 20000, .max = 115000 },
		194	.vco = { .min = 1750000, .max = 3500000 },
		195	.n = { .min = 1, .max = 3 },
		196	.m = { .min = 104, .max = 138 },
		197	.m1 = { .min = 17, .max = 23 },
		198	.m2 = { .min = 5, .max = 11 },
		199	.p = { .min = 28, .max = 112 },
		200	.p1 = { .min = 2, .max = 8 },
		201	.p2 = { .dot_limit = 0,
		202	.p2_slow = 14, .p2_fast = 14
		203	},
		204	};
		205
		206	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		207	.dot = { .min = 80000, .max = 224000 },
		208	.vco = { .min = 1750000, .max = 3500000 },
		209	.n = { .min = 1, .max = 3 },
		210	.m = { .min = 104, .max = 138 },
		211	.m1 = { .min = 17, .max = 23 },
		212	.m2 = { .min = 5, .max = 11 },
		213	.p = { .min = 14, .max = 42 },
		214	.p1 = { .min = 2, .max = 6 },
		215	.p2 = { .dot_limit = 0,
		216	.p2_slow = 7, .p2_fast = 7
		217	},
		218	};
		219
		220	static const intel_limit_t intel_limits_pineview_sdvo = {
		221	.dot = { .min = 20000, .max = 400000},
		222	.vco = { .min = 1700000, .max = 3500000 },
		223	/* Pineview's Ncounter is a ring counter */
		224	.n = { .min = 3, .max = 6 },
		225	.m = { .min = 2, .max = 256 },
		226	/* Pineview only has one combined m divider, which we treat as m2. */
		227	.m1 = { .min = 0, .max = 0 },
		228	.m2 = { .min = 0, .max = 254 },
		229	.p = { .min = 5, .max = 80 },
		230	.p1 = { .min = 1, .max = 8 },
		231	.p2 = { .dot_limit = 200000,
		232	.p2_slow = 10, .p2_fast = 5 },
		233	};
		234
		235	static const intel_limit_t intel_limits_pineview_lvds = {
		236	.dot = { .min = 20000, .max = 400000 },
		237	.vco = { .min = 1700000, .max = 3500000 },
		238	.n = { .min = 3, .max = 6 },
		239	.m = { .min = 2, .max = 256 },
		240	.m1 = { .min = 0, .max = 0 },
		241	.m2 = { .min = 0, .max = 254 },
		242	.p = { .min = 7, .max = 112 },
		243	.p1 = { .min = 1, .max = 8 },
		244	.p2 = { .dot_limit = 112000,
		245	.p2_slow = 14, .p2_fast = 14 },
		246	};
		247
		248	/* Ironlake / Sandybridge
		249	*
		250	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		251	* the range value for them is (actual_value - 2).
		252	*/
		253	static const intel_limit_t intel_limits_ironlake_dac = {
		254	.dot = { .min = 25000, .max = 350000 },
		255	.vco = { .min = 1760000, .max = 3510000 },
		256	.n = { .min = 1, .max = 5 },
		257	.m = { .min = 79, .max = 127 },
		258	.m1 = { .min = 12, .max = 22 },
		259	.m2 = { .min = 5, .max = 9 },
		260	.p = { .min = 5, .max = 80 },
		261	.p1 = { .min = 1, .max = 8 },
		262	.p2 = { .dot_limit = 225000,
		263	.p2_slow = 10, .p2_fast = 5 },
		264	};
		265
		266	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		267	.dot = { .min = 25000, .max = 350000 },
		268	.vco = { .min = 1760000, .max = 3510000 },
		269	.n = { .min = 1, .max = 3 },
		270	.m = { .min = 79, .max = 118 },
		271	.m1 = { .min = 12, .max = 22 },
		272	.m2 = { .min = 5, .max = 9 },
		273	.p = { .min = 28, .max = 112 },
		274	.p1 = { .min = 2, .max = 8 },
		275	.p2 = { .dot_limit = 225000,
		276	.p2_slow = 14, .p2_fast = 14 },
		277	};
		278
		279	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		280	.dot = { .min = 25000, .max = 350000 },
		281	.vco = { .min = 1760000, .max = 3510000 },
		282	.n = { .min = 1, .max = 3 },
		283	.m = { .min = 79, .max = 127 },
		284	.m1 = { .min = 12, .max = 22 },
		285	.m2 = { .min = 5, .max = 9 },
		286	.p = { .min = 14, .max = 56 },
		287	.p1 = { .min = 2, .max = 8 },
		288	.p2 = { .dot_limit = 225000,
		289	.p2_slow = 7, .p2_fast = 7 },
		290	};
		291
		292	/* LVDS 100mhz refclk limits. */
		293	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		294	.dot = { .min = 25000, .max = 350000 },
		295	.vco = { .min = 1760000, .max = 3510000 },
		296	.n = { .min = 1, .max = 2 },
		297	.m = { .min = 79, .max = 126 },
		298	.m1 = { .min = 12, .max = 22 },
		299	.m2 = { .min = 5, .max = 9 },
		300	.p = { .min = 28, .max = 112 },
2342	Serge	301	.p1 = { .min = 2, .max = 8 },
2327	Serge	302	.p2 = { .dot_limit = 225000,
		303	.p2_slow = 14, .p2_fast = 14 },
		304	};
		305
		306	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		307	.dot = { .min = 25000, .max = 350000 },
		308	.vco = { .min = 1760000, .max = 3510000 },
		309	.n = { .min = 1, .max = 3 },
		310	.m = { .min = 79, .max = 126 },
		311	.m1 = { .min = 12, .max = 22 },
		312	.m2 = { .min = 5, .max = 9 },
		313	.p = { .min = 14, .max = 42 },
2342	Serge	314	.p1 = { .min = 2, .max = 6 },
2327	Serge	315	.p2 = { .dot_limit = 225000,
		316	.p2_slow = 7, .p2_fast = 7 },
		317	};
		318
3031	serge	319	static const intel_limit_t intel_limits_vlv_dac = {
		320	.dot = { .min = 25000, .max = 270000 },
		321	.vco = { .min = 4000000, .max = 6000000 },
		322	.n = { .min = 1, .max = 7 },
		323	.m = { .min = 22, .max = 450 }, /* guess */
		324	.m1 = { .min = 2, .max = 3 },
		325	.m2 = { .min = 11, .max = 156 },
		326	.p = { .min = 10, .max = 30 },
4104	Serge	327	.p1 = { .min = 1, .max = 3 },
3031	serge	328	.p2 = { .dot_limit = 270000,
		329	.p2_slow = 2, .p2_fast = 20 },
		330	};
		331
		332	static const intel_limit_t intel_limits_vlv_hdmi = {
4104	Serge	333	.dot = { .min = 25000, .max = 270000 },
		334	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	335	.n = { .min = 1, .max = 7 },
		336	.m = { .min = 60, .max = 300 }, /* guess */
		337	.m1 = { .min = 2, .max = 3 },
		338	.m2 = { .min = 11, .max = 156 },
		339	.p = { .min = 10, .max = 30 },
		340	.p1 = { .min = 2, .max = 3 },
		341	.p2 = { .dot_limit = 270000,
		342	.p2_slow = 2, .p2_fast = 20 },
		343	};
		344
		345	static const intel_limit_t intel_limits_vlv_dp = {
3243	Serge	346	.dot = { .min = 25000, .max = 270000 },
		347	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	348	.n = { .min = 1, .max = 7 },
3243	Serge	349	.m = { .min = 22, .max = 450 },
3031	serge	350	.m1 = { .min = 2, .max = 3 },
		351	.m2 = { .min = 11, .max = 156 },
		352	.p = { .min = 10, .max = 30 },
4104	Serge	353	.p1 = { .min = 1, .max = 3 },
3031	serge	354	.p2 = { .dot_limit = 270000,
		355	.p2_slow = 2, .p2_fast = 20 },
		356	};
		357
2327	Serge	358	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		359	int refclk)
		360	{
		361	struct drm_device *dev = crtc->dev;
		362	const intel_limit_t *limit;
		363
		364	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	365	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	366	if (refclk == 100000)
		367	limit = &intel_limits_ironlake_dual_lvds_100m;
		368	else
		369	limit = &intel_limits_ironlake_dual_lvds;
		370	} else {
		371	if (refclk == 100000)
		372	limit = &intel_limits_ironlake_single_lvds_100m;
		373	else
		374	limit = &intel_limits_ironlake_single_lvds;
		375	}
4104	Serge	376	} else
2327	Serge	377	limit = &intel_limits_ironlake_dac;
		378
		379	return limit;
		380	}
		381
		382	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		383	{
		384	struct drm_device *dev = crtc->dev;
		385	const intel_limit_t *limit;
		386
		387	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	388	if (intel_is_dual_link_lvds(dev))
2327	Serge	389	limit = &intel_limits_g4x_dual_channel_lvds;
		390	else
		391	limit = &intel_limits_g4x_single_channel_lvds;
		392	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		393	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		394	limit = &intel_limits_g4x_hdmi;
		395	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		396	limit = &intel_limits_g4x_sdvo;
		397	} else /* The option is for other outputs */
		398	limit = &intel_limits_i9xx_sdvo;
		399
		400	return limit;
		401	}
		402
		403	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		404	{
		405	struct drm_device *dev = crtc->dev;
		406	const intel_limit_t *limit;
		407
		408	if (HAS_PCH_SPLIT(dev))
		409	limit = intel_ironlake_limit(crtc, refclk);
		410	else if (IS_G4X(dev)) {
		411	limit = intel_g4x_limit(crtc);
		412	} else if (IS_PINEVIEW(dev)) {
		413	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		414	limit = &intel_limits_pineview_lvds;
		415	else
		416	limit = &intel_limits_pineview_sdvo;
3031	serge	417	} else if (IS_VALLEYVIEW(dev)) {
		418	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		419	limit = &intel_limits_vlv_dac;
		420	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		421	limit = &intel_limits_vlv_hdmi;
		422	else
		423	limit = &intel_limits_vlv_dp;
2327	Serge	424	} else if (!IS_GEN2(dev)) {
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		426	limit = &intel_limits_i9xx_lvds;
		427	else
		428	limit = &intel_limits_i9xx_sdvo;
		429	} else {
		430	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		431	limit = &intel_limits_i8xx_lvds;
4104	Serge	432	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
		433	limit = &intel_limits_i8xx_dvo;
2327	Serge	434	else
4104	Serge	435	limit = &intel_limits_i8xx_dac;
2327	Serge	436	}
		437	return limit;
		438	}
		439
		440	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		441	static void pineview_clock(int refclk, intel_clock_t *clock)
		442	{
		443	clock->m = clock->m2 + 2;
		444	clock->p = clock->p1 * clock->p2;
		445	clock->vco = refclk * clock->m / clock->n;
		446	clock->dot = clock->vco / clock->p;
		447	}
		448
4104	Serge	449	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	450	{
4104	Serge	451	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		452	}
		453
		454	static void i9xx_clock(int refclk, intel_clock_t *clock)
		455	{
		456	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	457	clock->p = clock->p1 * clock->p2;
		458	clock->vco = refclk * clock->m / (clock->n + 2);
		459	clock->dot = clock->vco / clock->p;
		460	}
		461
		462	/**
		463	* Returns whether any output on the specified pipe is of the specified type
		464	*/
		465	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		466	{
		467	struct drm_device *dev = crtc->dev;
		468	struct intel_encoder *encoder;
		469
3031	serge	470	for_each_encoder_on_crtc(dev, crtc, encoder)
		471	if (encoder->type == type)
2327	Serge	472	return true;
		473
		474	return false;
		475	}
		476
		477	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		478	/**
		479	* Returns whether the given set of divisors are valid for a given refclk with
		480	* the given connectors.
		481	*/
		482
		483	static bool intel_PLL_is_valid(struct drm_device *dev,
		484	const intel_limit_t *limit,
		485	const intel_clock_t *clock)
		486	{
		487	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	488	INTELPllInvalid("p1 out of range\n");
2327	Serge	489	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	490	INTELPllInvalid("p out of range\n");
2327	Serge	491	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	492	INTELPllInvalid("m2 out of range\n");
2327	Serge	493	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	494	INTELPllInvalid("m1 out of range\n");
2327	Serge	495	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	496	INTELPllInvalid("m1 <= m2\n");
2327	Serge	497	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	498	INTELPllInvalid("m out of range\n");
2327	Serge	499	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	500	INTELPllInvalid("n out of range\n");
2327	Serge	501	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	502	INTELPllInvalid("vco out of range\n");
2327	Serge	503	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		504	* connector, etc., rather than just a single range.
		505	*/
		506	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	507	INTELPllInvalid("dot out of range\n");
2327	Serge	508
		509	return true;
		510	}
		511
		512	static bool
4104	Serge	513	i9xx_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	514	int target, int refclk, intel_clock_t *match_clock,
		515	intel_clock_t *best_clock)
2327	Serge	516	{
		517	struct drm_device *dev = crtc->dev;
		518	intel_clock_t clock;
		519	int err = target;
		520
3480	Serge	521	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	522	/*
3480	Serge	523	* For LVDS just rely on its current settings for dual-channel.
		524	* We haven't figured out how to reliably set up different
		525	* single/dual channel state, if we even can.
2327	Serge	526	*/
3480	Serge	527	if (intel_is_dual_link_lvds(dev))
2327	Serge	528	clock.p2 = limit->p2.p2_fast;
		529	else
		530	clock.p2 = limit->p2.p2_slow;
		531	} else {
		532	if (target < limit->p2.dot_limit)
		533	clock.p2 = limit->p2.p2_slow;
		534	else
		535	clock.p2 = limit->p2.p2_fast;
		536	}
		537
2342	Serge	538	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	539
		540	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		541	clock.m1++) {
		542	for (clock.m2 = limit->m2.min;
		543	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	544	if (clock.m2 >= clock.m1)
2327	Serge	545	break;
		546	for (clock.n = limit->n.min;
		547	clock.n <= limit->n.max; clock.n++) {
		548	for (clock.p1 = limit->p1.min;
		549	clock.p1 <= limit->p1.max; clock.p1++) {
		550	int this_err;
		551
4104	Serge	552	i9xx_clock(refclk, &clock);
2327	Serge	553	if (!intel_PLL_is_valid(dev, limit,
		554	&clock))
		555	continue;
3031	serge	556	if (match_clock &&
		557	clock.p != match_clock->p)
		558	continue;
2327	Serge	559
		560	this_err = abs(clock.dot - target);
		561	if (this_err < err) {
		562	*best_clock = clock;
		563	err = this_err;
		564	}
		565	}
		566	}
		567	}
		568	}
		569
		570	return (err != target);
		571	}
		572
		573	static bool
4104	Serge	574	pnv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		575	int target, int refclk, intel_clock_t *match_clock,
		576	intel_clock_t *best_clock)
		577	{
		578	struct drm_device *dev = crtc->dev;
		579	intel_clock_t clock;
		580	int err = target;
		581
		582	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		583	/*
		584	* For LVDS just rely on its current settings for dual-channel.
		585	* We haven't figured out how to reliably set up different
		586	* single/dual channel state, if we even can.
		587	*/
		588	if (intel_is_dual_link_lvds(dev))
		589	clock.p2 = limit->p2.p2_fast;
		590	else
		591	clock.p2 = limit->p2.p2_slow;
		592	} else {
		593	if (target < limit->p2.dot_limit)
		594	clock.p2 = limit->p2.p2_slow;
		595	else
		596	clock.p2 = limit->p2.p2_fast;
		597	}
		598
		599	memset(best_clock, 0, sizeof(*best_clock));
		600
		601	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		602	clock.m1++) {
		603	for (clock.m2 = limit->m2.min;
		604	clock.m2 <= limit->m2.max; clock.m2++) {
		605	for (clock.n = limit->n.min;
		606	clock.n <= limit->n.max; clock.n++) {
		607	for (clock.p1 = limit->p1.min;
		608	clock.p1 <= limit->p1.max; clock.p1++) {
		609	int this_err;
		610
		611	pineview_clock(refclk, &clock);
		612	if (!intel_PLL_is_valid(dev, limit,
		613	&clock))
		614	continue;
		615	if (match_clock &&
		616	clock.p != match_clock->p)
		617	continue;
		618
		619	this_err = abs(clock.dot - target);
		620	if (this_err < err) {
		621	*best_clock = clock;
		622	err = this_err;
		623	}
		624	}
		625	}
		626	}
		627	}
		628
		629	return (err != target);
		630	}
		631
		632	static bool
		633	g4x_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	634	int target, int refclk, intel_clock_t *match_clock,
		635	intel_clock_t *best_clock)
2327	Serge	636	{
		637	struct drm_device *dev = crtc->dev;
		638	intel_clock_t clock;
		639	int max_n;
		640	bool found;
		641	/* approximately equals target * 0.00585 */
		642	int err_most = (target >> 8) + (target >> 9);
		643	found = false;
		644
		645	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	646	if (intel_is_dual_link_lvds(dev))
2327	Serge	647	clock.p2 = limit->p2.p2_fast;
		648	else
		649	clock.p2 = limit->p2.p2_slow;
		650	} else {
		651	if (target < limit->p2.dot_limit)
		652	clock.p2 = limit->p2.p2_slow;
		653	else
		654	clock.p2 = limit->p2.p2_fast;
		655	}
		656
		657	memset(best_clock, 0, sizeof(*best_clock));
		658	max_n = limit->n.max;
		659	/* based on hardware requirement, prefer smaller n to precision */
		660	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		661	/* based on hardware requirement, prefere larger m1,m2 */
		662	for (clock.m1 = limit->m1.max;
		663	clock.m1 >= limit->m1.min; clock.m1--) {
		664	for (clock.m2 = limit->m2.max;
		665	clock.m2 >= limit->m2.min; clock.m2--) {
		666	for (clock.p1 = limit->p1.max;
		667	clock.p1 >= limit->p1.min; clock.p1--) {
		668	int this_err;
		669
4104	Serge	670	i9xx_clock(refclk, &clock);
2327	Serge	671	if (!intel_PLL_is_valid(dev, limit,
		672	&clock))
		673	continue;
		674
		675	this_err = abs(clock.dot - target);
		676	if (this_err < err_most) {
		677	*best_clock = clock;
		678	err_most = this_err;
		679	max_n = clock.n;
		680	found = true;
		681	}
		682	}
		683	}
		684	}
		685	}
		686	return found;
		687	}
		688
		689	static bool
4104	Serge	690	vlv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	691	int target, int refclk, intel_clock_t *match_clock,
		692	intel_clock_t *best_clock)
		693	{
		694	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		695	u32 m, n, fastclk;
4104	Serge	696	u32 updrate, minupdate, p;
3031	serge	697	unsigned long bestppm, ppm, absppm;
		698	int dotclk, flag;
2327	Serge	699
3031	serge	700	flag = 0;
		701	dotclk = target * 1000;
		702	bestppm = 1000000;
		703	ppm = absppm = 0;
		704	fastclk = dotclk / (2*100);
		705	updrate = 0;
		706	minupdate = 19200;
		707	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		708	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		709
		710	/* based on hardware requirement, prefer smaller n to precision */
		711	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		712	updrate = refclk / n;
		713	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		714	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		715	if (p2 > 10)
		716	p2 = p2 - 1;
		717	p = p1 * p2;
		718	/* based on hardware requirement, prefer bigger m1,m2 values */
		719	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		720	m2 = (((2(fastclk p * n / m1 )) +
		721	refclk) / (2*refclk));
		722	m = m1 * m2;
		723	vco = updrate * m;
		724	if (vco >= limit->vco.min && vco < limit->vco.max) {
		725	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		726	absppm = (ppm > 0) ? ppm : (-ppm);
		727	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		728	bestppm = 0;
		729	flag = 1;
		730	}
		731	if (absppm < bestppm - 10) {
		732	bestppm = absppm;
		733	flag = 1;
		734	}
		735	if (flag) {
		736	bestn = n;
		737	bestm1 = m1;
		738	bestm2 = m2;
		739	bestp1 = p1;
		740	bestp2 = p2;
		741	flag = 0;
		742	}
		743	}
		744	}
		745	}
		746	}
		747	}
		748	best_clock->n = bestn;
		749	best_clock->m1 = bestm1;
		750	best_clock->m2 = bestm2;
		751	best_clock->p1 = bestp1;
		752	best_clock->p2 = bestp2;
		753
		754	return true;
		755	}
		756
3243	Serge	757	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		758	enum pipe pipe)
		759	{
		760	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		762
3746	Serge	763	return intel_crtc->config.cpu_transcoder;
3243	Serge	764	}
		765
3031	serge	766	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		767	{
		768	struct drm_i915_private *dev_priv = dev->dev_private;
		769	u32 frame, frame_reg = PIPEFRAME(pipe);
		770
		771	frame = I915_READ(frame_reg);
		772
		773	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		774	DRM_DEBUG_KMS("vblank wait timed out\n");
		775	}
		776
2327	Serge	777	/**
		778	* intel_wait_for_vblank - wait for vblank on a given pipe
		779	* @dev: drm device
		780	* @pipe: pipe to wait for
		781	*
		782	* Wait for vblank to occur on a given pipe. Needed for various bits of
		783	* mode setting code.
		784	*/
		785	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		786	{
		787	struct drm_i915_private *dev_priv = dev->dev_private;
		788	int pipestat_reg = PIPESTAT(pipe);
		789
3031	serge	790	if (INTEL_INFO(dev)->gen >= 5) {
		791	ironlake_wait_for_vblank(dev, pipe);
		792	return;
		793	}
		794
2327	Serge	795	/* Clear existing vblank status. Note this will clear any other
		796	* sticky status fields as well.
		797	*
		798	* This races with i915_driver_irq_handler() with the result
		799	* that either function could miss a vblank event. Here it is not
		800	* fatal, as we will either wait upon the next vblank interrupt or
		801	* timeout. Generally speaking intel_wait_for_vblank() is only
		802	* called during modeset at which time the GPU should be idle and
		803	* should not be performing page flips and thus not waiting on
		804	* vblanks...
		805	* Currently, the result of us stealing a vblank from the irq
		806	* handler is that a single frame will be skipped during swapbuffers.
		807	*/
		808	I915_WRITE(pipestat_reg,
		809	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		810
		811	/* Wait for vblank interrupt bit to set */
		812	if (wait_for(I915_READ(pipestat_reg) &
		813	PIPE_VBLANK_INTERRUPT_STATUS,
		814	50))
		815	DRM_DEBUG_KMS("vblank wait timed out\n");
		816	}
		817
		818	/*
		819	* intel_wait_for_pipe_off - wait for pipe to turn off
		820	* @dev: drm device
		821	* @pipe: pipe to wait for
		822	*
		823	* After disabling a pipe, we can't wait for vblank in the usual way,
		824	* spinning on the vblank interrupt status bit, since we won't actually
		825	* see an interrupt when the pipe is disabled.
		826	*
		827	* On Gen4 and above:
		828	* wait for the pipe register state bit to turn off
		829	*
		830	* Otherwise:
		831	* wait for the display line value to settle (it usually
		832	* ends up stopping at the start of the next frame).
		833	*
		834	*/
		835	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		836	{
		837	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	838	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		839	pipe);
2327	Serge	840
		841	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	842	int reg = PIPECONF(cpu_transcoder);
2327	Serge	843
		844	/* Wait for the Pipe State to go off */
		845	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		846	100))
3031	serge	847	WARN(1, "pipe_off wait timed out\n");
2327	Serge	848	} else {
3031	serge	849	u32 last_line, line_mask;
2327	Serge	850	int reg = PIPEDSL(pipe);
4104	Serge	851	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	852
3031	serge	853	if (IS_GEN2(dev))
		854	line_mask = DSL_LINEMASK_GEN2;
		855	else
		856	line_mask = DSL_LINEMASK_GEN3;
		857
2327	Serge	858	/* Wait for the display line to settle */
		859	do {
3031	serge	860	last_line = I915_READ(reg) & line_mask;
2327	Serge	861	mdelay(5);
3031	serge	862	} while (((I915_READ(reg) & line_mask) != last_line) &&
		863	time_after(timeout, GetTimerTicks()));
		864	if (time_after(GetTimerTicks(), timeout))
		865	WARN(1, "pipe_off wait timed out\n");
2327	Serge	866	}
		867	}
		868
3480	Serge	869	/*
		870	* ibx_digital_port_connected - is the specified port connected?
		871	* @dev_priv: i915 private structure
		872	* @port: the port to test
		873	*
		874	* Returns true if @port is connected, false otherwise.
		875	*/
		876	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		877	struct intel_digital_port *port)
		878	{
		879	u32 bit;
		880
		881	if (HAS_PCH_IBX(dev_priv->dev)) {
		882	switch(port->port) {
		883	case PORT_B:
		884	bit = SDE_PORTB_HOTPLUG;
		885	break;
		886	case PORT_C:
		887	bit = SDE_PORTC_HOTPLUG;
		888	break;
		889	case PORT_D:
		890	bit = SDE_PORTD_HOTPLUG;
		891	break;
		892	default:
		893	return true;
		894	}
		895	} else {
		896	switch(port->port) {
		897	case PORT_B:
		898	bit = SDE_PORTB_HOTPLUG_CPT;
		899	break;
		900	case PORT_C:
		901	bit = SDE_PORTC_HOTPLUG_CPT;
		902	break;
		903	case PORT_D:
		904	bit = SDE_PORTD_HOTPLUG_CPT;
		905	break;
		906	default:
		907	return true;
		908	}
		909	}
		910
		911	return I915_READ(SDEISR) & bit;
		912	}
		913
2327	Serge	914	static const char *state_string(bool enabled)
		915	{
		916	return enabled ? "on" : "off";
		917	}
		918
		919	/* Only for pre-ILK configs */
4104	Serge	920	void assert_pll(struct drm_i915_private *dev_priv,
2327	Serge	921	enum pipe pipe, bool state)
		922	{
		923	int reg;
		924	u32 val;
		925	bool cur_state;
		926
		927	reg = DPLL(pipe);
		928	val = I915_READ(reg);
		929	cur_state = !!(val & DPLL_VCO_ENABLE);
		930	WARN(cur_state != state,
		931	"PLL state assertion failure (expected %s, current %s)\n",
		932	state_string(state), state_string(cur_state));
		933	}
		934
4104	Serge	935	struct intel_shared_dpll *
		936	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		937	{
		938	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		939
		940	if (crtc->config.shared_dpll < 0)
		941	return NULL;
		942
		943	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
		944	}
		945
2327	Serge	946	/* For ILK+ */
4104	Serge	947	void assert_shared_dpll(struct drm_i915_private *dev_priv,
		948	struct intel_shared_dpll *pll,
3031	serge	949	bool state)
2327	Serge	950	{
		951	bool cur_state;
4104	Serge	952	struct intel_dpll_hw_state hw_state;
2327	Serge	953
3031	serge	954	if (HAS_PCH_LPT(dev_priv->dev)) {
		955	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		956	return;
		957	}
2342	Serge	958
3031	serge	959	if (WARN (!pll,
4104	Serge	960	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	961	return;
2342	Serge	962
4104	Serge	963	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
3031	serge	964	WARN(cur_state != state,
4104	Serge	965	"%s assertion failure (expected %s, current %s)\n",
		966	pll->name, state_string(state), state_string(cur_state));
2327	Serge	967	}
		968
		969	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		970	enum pipe pipe, bool state)
		971	{
		972	int reg;
		973	u32 val;
		974	bool cur_state;
3243	Serge	975	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		976	pipe);
2327	Serge	977
3480	Serge	978	if (HAS_DDI(dev_priv->dev)) {
		979	/* DDI does not have a specific FDI_TX register */
3243	Serge	980	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	981	val = I915_READ(reg);
3243	Serge	982	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	983	} else {
2327	Serge	984	reg = FDI_TX_CTL(pipe);
		985	val = I915_READ(reg);
		986	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	987	}
2327	Serge	988	WARN(cur_state != state,
		989	"FDI TX state assertion failure (expected %s, current %s)\n",
		990	state_string(state), state_string(cur_state));
		991	}
		992	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		993	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		994
		995	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		996	enum pipe pipe, bool state)
		997	{
		998	int reg;
		999	u32 val;
		1000	bool cur_state;
		1001
		1002	reg = FDI_RX_CTL(pipe);
		1003	val = I915_READ(reg);
		1004	cur_state = !!(val & FDI_RX_ENABLE);
		1005	WARN(cur_state != state,
		1006	"FDI RX state assertion failure (expected %s, current %s)\n",
		1007	state_string(state), state_string(cur_state));
		1008	}
		1009	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1010	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1011
		1012	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1013	enum pipe pipe)
		1014	{
		1015	int reg;
		1016	u32 val;
		1017
		1018	/* ILK FDI PLL is always enabled */
		1019	if (dev_priv->info->gen == 5)
		1020	return;
		1021
3031	serge	1022	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1023	if (HAS_DDI(dev_priv->dev))
3031	serge	1024	return;
		1025
2327	Serge	1026	reg = FDI_TX_CTL(pipe);
		1027	val = I915_READ(reg);
		1028	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1029	}
		1030
4104	Serge	1031	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1032	enum pipe pipe, bool state)
2327	Serge	1033	{
		1034	int reg;
		1035	u32 val;
4104	Serge	1036	bool cur_state;
2327	Serge	1037
		1038	reg = FDI_RX_CTL(pipe);
		1039	val = I915_READ(reg);
4104	Serge	1040	cur_state = !!(val & FDI_RX_PLL_ENABLE);
		1041	WARN(cur_state != state,
		1042	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1043	state_string(state), state_string(cur_state));
2327	Serge	1044	}
		1045
		1046	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1047	enum pipe pipe)
		1048	{
		1049	int pp_reg, lvds_reg;
		1050	u32 val;
		1051	enum pipe panel_pipe = PIPE_A;
		1052	bool locked = true;
		1053
		1054	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1055	pp_reg = PCH_PP_CONTROL;
		1056	lvds_reg = PCH_LVDS;
		1057	} else {
		1058	pp_reg = PP_CONTROL;
		1059	lvds_reg = LVDS;
		1060	}
		1061
		1062	val = I915_READ(pp_reg);
		1063	if (!(val & PANEL_POWER_ON) \|\|
		1064	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1065	locked = false;
		1066
		1067	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1068	panel_pipe = PIPE_B;
		1069
		1070	WARN(panel_pipe == pipe && locked,
		1071	"panel assertion failure, pipe %c regs locked\n",
		1072	pipe_name(pipe));
		1073	}
		1074
2342	Serge	1075	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1076	enum pipe pipe, bool state)
		1077	{
		1078	int reg;
		1079	u32 val;
		1080	bool cur_state;
3243	Serge	1081	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1082	pipe);
2327	Serge	1083
3031	serge	1084	/* if we need the pipe A quirk it must be always on */
		1085	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1086	state = true;
		1087
4104	Serge	1088	if (!intel_display_power_enabled(dev_priv->dev,
		1089	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1090	cur_state = false;
		1091	} else {
3243	Serge	1092	reg = PIPECONF(cpu_transcoder);
2327	Serge	1093	val = I915_READ(reg);
		1094	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1095	}
		1096
2327	Serge	1097	WARN(cur_state != state,
		1098	"pipe %c assertion failure (expected %s, current %s)\n",
		1099	pipe_name(pipe), state_string(state), state_string(cur_state));
		1100	}
		1101
3031	serge	1102	static void assert_plane(struct drm_i915_private *dev_priv,
		1103	enum plane plane, bool state)
2327	Serge	1104	{
		1105	int reg;
		1106	u32 val;
3031	serge	1107	bool cur_state;
2327	Serge	1108
		1109	reg = DSPCNTR(plane);
		1110	val = I915_READ(reg);
3031	serge	1111	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1112	WARN(cur_state != state,
		1113	"plane %c assertion failure (expected %s, current %s)\n",
		1114	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1115	}
		1116
3031	serge	1117	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1118	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1119
2327	Serge	1120	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1121	enum pipe pipe)
		1122	{
4104	Serge	1123	struct drm_device *dev = dev_priv->dev;
2327	Serge	1124	int reg, i;
		1125	u32 val;
		1126	int cur_pipe;
		1127
4104	Serge	1128	/* Primary planes are fixed to pipes on gen4+ */
		1129	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	1130	reg = DSPCNTR(pipe);
		1131	val = I915_READ(reg);
		1132	WARN((val & DISPLAY_PLANE_ENABLE),
		1133	"plane %c assertion failure, should be disabled but not\n",
		1134	plane_name(pipe));
2327	Serge	1135	return;
3031	serge	1136	}
2327	Serge	1137
		1138	/* Need to check both planes against the pipe */
4104	Serge	1139	for_each_pipe(i) {
2327	Serge	1140	reg = DSPCNTR(i);
		1141	val = I915_READ(reg);
		1142	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1143	DISPPLANE_SEL_PIPE_SHIFT;
		1144	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1145	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1146	plane_name(i), pipe_name(pipe));
		1147	}
		1148	}
		1149
3746	Serge	1150	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1151	enum pipe pipe)
		1152	{
4104	Serge	1153	struct drm_device *dev = dev_priv->dev;
3746	Serge	1154	int reg, i;
		1155	u32 val;
		1156
4104	Serge	1157	if (IS_VALLEYVIEW(dev)) {
3746	Serge	1158	for (i = 0; i < dev_priv->num_plane; i++) {
		1159	reg = SPCNTR(pipe, i);
		1160	val = I915_READ(reg);
		1161	WARN((val & SP_ENABLE),
4104	Serge	1162	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1163	sprite_name(pipe, i), pipe_name(pipe));
		1164	}
		1165	} else if (INTEL_INFO(dev)->gen >= 7) {
		1166	reg = SPRCTL(pipe);
		1167	val = I915_READ(reg);
		1168	WARN((val & SPRITE_ENABLE),
		1169	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1170	plane_name(pipe), pipe_name(pipe));
		1171	} else if (INTEL_INFO(dev)->gen >= 5) {
		1172	reg = DVSCNTR(pipe);
		1173	val = I915_READ(reg);
		1174	WARN((val & DVS_ENABLE),
		1175	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1176	plane_name(pipe), pipe_name(pipe));
3746	Serge	1177	}
		1178	}
		1179
2327	Serge	1180	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1181	{
		1182	u32 val;
		1183	bool enabled;
		1184
3031	serge	1185	if (HAS_PCH_LPT(dev_priv->dev)) {
		1186	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1187	return;
		1188	}
		1189
2327	Serge	1190	val = I915_READ(PCH_DREF_CONTROL);
		1191	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1192	DREF_SUPERSPREAD_SOURCE_MASK));
		1193	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1194	}
		1195
4104	Serge	1196	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
2327	Serge	1197	enum pipe pipe)
		1198	{
		1199	int reg;
		1200	u32 val;
		1201	bool enabled;
		1202
4104	Serge	1203	reg = PCH_TRANSCONF(pipe);
2327	Serge	1204	val = I915_READ(reg);
		1205	enabled = !!(val & TRANS_ENABLE);
		1206	WARN(enabled,
		1207	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1208	pipe_name(pipe));
		1209	}
		1210
		1211	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1212	enum pipe pipe, u32 port_sel, u32 val)
		1213	{
		1214	if ((val & DP_PORT_EN) == 0)
		1215	return false;
		1216
		1217	if (HAS_PCH_CPT(dev_priv->dev)) {
		1218	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1219	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1220	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1221	return false;
		1222	} else {
		1223	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1224	return false;
		1225	}
		1226	return true;
		1227	}
		1228
		1229	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1230	enum pipe pipe, u32 val)
		1231	{
3746	Serge	1232	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1233	return false;
		1234
		1235	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1236	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1237	return false;
		1238	} else {
3746	Serge	1239	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1240	return false;
		1241	}
		1242	return true;
		1243	}
		1244
		1245	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1246	enum pipe pipe, u32 val)
		1247	{
		1248	if ((val & LVDS_PORT_EN) == 0)
		1249	return false;
		1250
		1251	if (HAS_PCH_CPT(dev_priv->dev)) {
		1252	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1253	return false;
		1254	} else {
		1255	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1256	return false;
		1257	}
		1258	return true;
		1259	}
		1260
		1261	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1262	enum pipe pipe, u32 val)
		1263	{
		1264	if ((val & ADPA_DAC_ENABLE) == 0)
		1265	return false;
		1266	if (HAS_PCH_CPT(dev_priv->dev)) {
		1267	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1268	return false;
		1269	} else {
		1270	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1271	return false;
		1272	}
		1273	return true;
		1274	}
		1275
		1276	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1277	enum pipe pipe, int reg, u32 port_sel)
		1278	{
		1279	u32 val = I915_READ(reg);
		1280	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1281	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1282	reg, pipe_name(pipe));
3031	serge	1283
		1284	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1285	&& (val & DP_PIPEB_SELECT),
		1286	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1287	}
		1288
		1289	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1290	enum pipe pipe, int reg)
		1291	{
		1292	u32 val = I915_READ(reg);
3031	serge	1293	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1294	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1295	reg, pipe_name(pipe));
3031	serge	1296
3746	Serge	1297	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1298	&& (val & SDVO_PIPE_B_SELECT),
		1299	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1300	}
		1301
		1302	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1303	enum pipe pipe)
		1304	{
		1305	int reg;
		1306	u32 val;
		1307
		1308	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1309	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1310	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1311
		1312	reg = PCH_ADPA;
		1313	val = I915_READ(reg);
3031	serge	1314	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1315	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1316	pipe_name(pipe));
		1317
		1318	reg = PCH_LVDS;
		1319	val = I915_READ(reg);
3031	serge	1320	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1321	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1322	pipe_name(pipe));
		1323
3746	Serge	1324	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1325	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1326	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1327	}
		1328
4104	Serge	1329	static void vlv_enable_pll(struct intel_crtc *crtc)
2327	Serge	1330	{
4104	Serge	1331	struct drm_device *dev = crtc->base.dev;
		1332	struct drm_i915_private *dev_priv = dev->dev_private;
		1333	int reg = DPLL(crtc->pipe);
		1334	u32 dpll = crtc->config.dpll_hw_state.dpll;
2327	Serge	1335
4104	Serge	1336	assert_pipe_disabled(dev_priv, crtc->pipe);
		1337
2327	Serge	1338	/* No really, not for ILK+ */
4104	Serge	1339	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1340
		1341	/* PLL is protected by panel, make sure we can write it */
		1342	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
4104	Serge	1343	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1344
4104	Serge	1345	I915_WRITE(reg, dpll);
		1346	POSTING_READ(reg);
		1347	udelay(150);
2327	Serge	1348
4104	Serge	1349	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1350	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1351
		1352	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
		1353	POSTING_READ(DPLL_MD(crtc->pipe));
		1354
		1355	/* We do this three times for luck */
		1356	I915_WRITE(reg, dpll);
		1357	POSTING_READ(reg);
		1358	udelay(150); /* wait for warmup */
		1359	I915_WRITE(reg, dpll);
		1360	POSTING_READ(reg);
		1361	udelay(150); /* wait for warmup */
		1362	I915_WRITE(reg, dpll);
		1363	POSTING_READ(reg);
		1364	udelay(150); /* wait for warmup */
		1365	}
		1366
		1367	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1368	{
		1369	struct drm_device *dev = crtc->base.dev;
		1370	struct drm_i915_private *dev_priv = dev->dev_private;
		1371	int reg = DPLL(crtc->pipe);
		1372	u32 dpll = crtc->config.dpll_hw_state.dpll;
		1373
		1374	assert_pipe_disabled(dev_priv, crtc->pipe);
		1375
		1376	/* No really, not for ILK+ */
		1377	BUG_ON(dev_priv->info->gen >= 5);
		1378
		1379	/* PLL is protected by panel, make sure we can write it */
		1380	if (IS_MOBILE(dev) && !IS_I830(dev))
		1381	assert_panel_unlocked(dev_priv, crtc->pipe);
		1382
		1383	I915_WRITE(reg, dpll);
		1384
		1385	/* Wait for the clocks to stabilize. */
		1386	POSTING_READ(reg);
		1387	udelay(150);
		1388
		1389	if (INTEL_INFO(dev)->gen >= 4) {
		1390	I915_WRITE(DPLL_MD(crtc->pipe),
		1391	crtc->config.dpll_hw_state.dpll_md);
		1392	} else {
		1393	/* The pixel multiplier can only be updated once the
		1394	* DPLL is enabled and the clocks are stable.
		1395	*
		1396	* So write it again.
		1397	*/
		1398	I915_WRITE(reg, dpll);
		1399	}
		1400
2327	Serge	1401	/* We do this three times for luck */
4104	Serge	1402	I915_WRITE(reg, dpll);
2327	Serge	1403	POSTING_READ(reg);
		1404	udelay(150); /* wait for warmup */
4104	Serge	1405	I915_WRITE(reg, dpll);
2327	Serge	1406	POSTING_READ(reg);
		1407	udelay(150); /* wait for warmup */
4104	Serge	1408	I915_WRITE(reg, dpll);
2327	Serge	1409	POSTING_READ(reg);
		1410	udelay(150); /* wait for warmup */
		1411	}
		1412
		1413	/**
4104	Serge	1414	* i9xx_disable_pll - disable a PLL
2327	Serge	1415	* @dev_priv: i915 private structure
		1416	* @pipe: pipe PLL to disable
		1417	*
		1418	* Disable the PLL for @pipe, making sure the pipe is off first.
		1419	*
		1420	* Note! This is for pre-ILK only.
		1421	*/
4104	Serge	1422	static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2327	Serge	1423	{
		1424	/* Don't disable pipe A or pipe A PLLs if needed */
		1425	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1426	return;
		1427
		1428	/* Make sure the pipe isn't still relying on us */
		1429	assert_pipe_disabled(dev_priv, pipe);
		1430
4104	Serge	1431	I915_WRITE(DPLL(pipe), 0);
		1432	POSTING_READ(DPLL(pipe));
2327	Serge	1433	}
		1434
4104	Serge	1435	void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
3031	serge	1436	{
4104	Serge	1437	u32 port_mask;
3031	serge	1438
4104	Serge	1439	if (!port)
		1440	port_mask = DPLL_PORTB_READY_MASK;
3243	Serge	1441	else
4104	Serge	1442	port_mask = DPLL_PORTC_READY_MASK;
3243	Serge	1443
4104	Serge	1444	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		1445	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		1446	'B' + port, I915_READ(DPLL(0)));
3031	serge	1447	}
		1448
2327	Serge	1449	/**
4104	Serge	1450	* ironlake_enable_shared_dpll - enable PCH PLL
2327	Serge	1451	* @dev_priv: i915 private structure
		1452	* @pipe: pipe PLL to enable
		1453	*
		1454	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1455	* drives the transcoder clock.
		1456	*/
4104	Serge	1457	static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1458	{
4104	Serge	1459	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1460	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1461
3031	serge	1462	/* PCH PLLs only available on ILK, SNB and IVB */
		1463	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1464	if (WARN_ON(pll == NULL))
2342	Serge	1465	return;
		1466
3031	serge	1467	if (WARN_ON(pll->refcount == 0))
		1468	return;
2327	Serge	1469
4104	Serge	1470	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		1471	pll->name, pll->active, pll->on,
		1472	crtc->base.base.id);
3031	serge	1473
4104	Serge	1474	if (pll->active++) {
		1475	WARN_ON(!pll->on);
		1476	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1477	return;
		1478	}
4104	Serge	1479	WARN_ON(pll->on);
3031	serge	1480
4104	Serge	1481	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1482	pll->enable(dev_priv, pll);
3031	serge	1483	pll->on = true;
2327	Serge	1484	}
		1485
4104	Serge	1486	static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1487	{
4104	Serge	1488	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1489	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1490
		1491	/* PCH only available on ILK+ */
		1492	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1493	if (WARN_ON(pll == NULL))
3031	serge	1494	return;
2327	Serge	1495
3031	serge	1496	if (WARN_ON(pll->refcount == 0))
		1497	return;
2327	Serge	1498
4104	Serge	1499	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1500	pll->name, pll->active, pll->on,
		1501	crtc->base.base.id);
2342	Serge	1502
3031	serge	1503	if (WARN_ON(pll->active == 0)) {
4104	Serge	1504	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1505	return;
		1506	}
2342	Serge	1507
4104	Serge	1508	assert_shared_dpll_enabled(dev_priv, pll);
		1509	WARN_ON(!pll->on);
		1510	if (--pll->active)
2342	Serge	1511	return;
		1512
4104	Serge	1513	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1514	pll->disable(dev_priv, pll);
3031	serge	1515	pll->on = false;
2327	Serge	1516	}
		1517
3243	Serge	1518	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1519	enum pipe pipe)
		1520	{
3243	Serge	1521	struct drm_device *dev = dev_priv->dev;
3031	serge	1522	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1523	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1524	uint32_t reg, val, pipeconf_val;
2327	Serge	1525
		1526	/* PCH only available on ILK+ */
		1527	BUG_ON(dev_priv->info->gen < 5);
		1528
		1529	/* Make sure PCH DPLL is enabled */
4104	Serge	1530	assert_shared_dpll_enabled(dev_priv,
		1531	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1532
		1533	/* FDI must be feeding us bits for PCH ports */
		1534	assert_fdi_tx_enabled(dev_priv, pipe);
		1535	assert_fdi_rx_enabled(dev_priv, pipe);
		1536
3243	Serge	1537	if (HAS_PCH_CPT(dev)) {
		1538	/* Workaround: Set the timing override bit before enabling the
		1539	* pch transcoder. */
		1540	reg = TRANS_CHICKEN2(pipe);
		1541	val = I915_READ(reg);
		1542	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1543	I915_WRITE(reg, val);
3031	serge	1544	}
3243	Serge	1545
4104	Serge	1546	reg = PCH_TRANSCONF(pipe);
2327	Serge	1547	val = I915_READ(reg);
3031	serge	1548	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1549
		1550	if (HAS_PCH_IBX(dev_priv->dev)) {
		1551	/*
		1552	* make the BPC in transcoder be consistent with
		1553	* that in pipeconf reg.
		1554	*/
3480	Serge	1555	val &= ~PIPECONF_BPC_MASK;
		1556	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1557	}
3031	serge	1558
		1559	val &= ~TRANS_INTERLACE_MASK;
		1560	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1561	if (HAS_PCH_IBX(dev_priv->dev) &&
		1562	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1563	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1564	else
		1565	val \|= TRANS_INTERLACED;
		1566	else
		1567	val \|= TRANS_PROGRESSIVE;
		1568
2327	Serge	1569	I915_WRITE(reg, val \| TRANS_ENABLE);
		1570	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	1571	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	1572	}
		1573
3243	Serge	1574	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1575	enum transcoder cpu_transcoder)
		1576	{
		1577	u32 val, pipeconf_val;
		1578
		1579	/* PCH only available on ILK+ */
		1580	BUG_ON(dev_priv->info->gen < 5);
		1581
		1582	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1583	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1584	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1585
		1586	/* Workaround: set timing override bit. */
		1587	val = I915_READ(_TRANSA_CHICKEN2);
		1588	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1589	I915_WRITE(_TRANSA_CHICKEN2, val);
		1590
		1591	val = TRANS_ENABLE;
		1592	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1593
		1594	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1595	PIPECONF_INTERLACED_ILK)
		1596	val \|= TRANS_INTERLACED;
		1597	else
		1598	val \|= TRANS_PROGRESSIVE;
		1599
4104	Serge	1600	I915_WRITE(LPT_TRANSCONF, val);
		1601	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	1602	DRM_ERROR("Failed to enable PCH transcoder\n");
		1603	}
		1604
		1605	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1606	enum pipe pipe)
		1607	{
3243	Serge	1608	struct drm_device *dev = dev_priv->dev;
		1609	uint32_t reg, val;
2327	Serge	1610
		1611	/* FDI relies on the transcoder */
		1612	assert_fdi_tx_disabled(dev_priv, pipe);
		1613	assert_fdi_rx_disabled(dev_priv, pipe);
		1614
		1615	/* Ports must be off as well */
		1616	assert_pch_ports_disabled(dev_priv, pipe);
		1617
4104	Serge	1618	reg = PCH_TRANSCONF(pipe);
2327	Serge	1619	val = I915_READ(reg);
		1620	val &= ~TRANS_ENABLE;
		1621	I915_WRITE(reg, val);
		1622	/* wait for PCH transcoder off, transcoder state */
		1623	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	1624	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	1625
		1626	if (!HAS_PCH_IBX(dev)) {
		1627	/* Workaround: Clear the timing override chicken bit again. */
		1628	reg = TRANS_CHICKEN2(pipe);
		1629	val = I915_READ(reg);
		1630	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1631	I915_WRITE(reg, val);
		1632	}
2327	Serge	1633	}
		1634
3243	Serge	1635	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1636	{
		1637	u32 val;
		1638
4104	Serge	1639	val = I915_READ(LPT_TRANSCONF);
3243	Serge	1640	val &= ~TRANS_ENABLE;
4104	Serge	1641	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	1642	/* wait for PCH transcoder off, transcoder state */
4104	Serge	1643	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	1644	DRM_ERROR("Failed to disable PCH transcoder\n");
		1645
		1646	/* Workaround: clear timing override bit. */
		1647	val = I915_READ(_TRANSA_CHICKEN2);
		1648	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1649	I915_WRITE(_TRANSA_CHICKEN2, val);
		1650	}
		1651
2327	Serge	1652	/**
		1653	* intel_enable_pipe - enable a pipe, asserting requirements
		1654	* @dev_priv: i915 private structure
		1655	* @pipe: pipe to enable
		1656	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1657	*
		1658	* Enable @pipe, making sure that various hardware specific requirements
		1659	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1660	*
		1661	* @pipe should be %PIPE_A or %PIPE_B.
		1662	*
		1663	* Will wait until the pipe is actually running (i.e. first vblank) before
		1664	* returning.
		1665	*/
		1666	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1667	bool pch_port)
		1668	{
3243	Serge	1669	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1670	pipe);
3480	Serge	1671	enum pipe pch_transcoder;
2327	Serge	1672	int reg;
		1673	u32 val;
		1674
4104	Serge	1675	assert_planes_disabled(dev_priv, pipe);
		1676	assert_sprites_disabled(dev_priv, pipe);
		1677
3480	Serge	1678	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	1679	pch_transcoder = TRANSCODER_A;
		1680	else
		1681	pch_transcoder = pipe;
		1682
2327	Serge	1683	/*
		1684	* A pipe without a PLL won't actually be able to drive bits from
		1685	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1686	* need the check.
		1687	*/
		1688	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1689	assert_pll_enabled(dev_priv, pipe);
		1690	else {
		1691	if (pch_port) {
		1692	/* if driving the PCH, we need FDI enabled */
3243	Serge	1693	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	1694	assert_fdi_tx_pll_enabled(dev_priv,
		1695	(enum pipe) cpu_transcoder);
2327	Serge	1696	}
		1697	/* FIXME: assert CPU port conditions for SNB+ */
		1698	}
		1699
3243	Serge	1700	reg = PIPECONF(cpu_transcoder);
2327	Serge	1701	val = I915_READ(reg);
		1702	if (val & PIPECONF_ENABLE)
		1703	return;
		1704
		1705	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1706	intel_wait_for_vblank(dev_priv->dev, pipe);
		1707	}
		1708
		1709	/**
		1710	* intel_disable_pipe - disable a pipe, asserting requirements
		1711	* @dev_priv: i915 private structure
		1712	* @pipe: pipe to disable
		1713	*
		1714	* Disable @pipe, making sure that various hardware specific requirements
		1715	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1716	*
		1717	* @pipe should be %PIPE_A or %PIPE_B.
		1718	*
		1719	* Will wait until the pipe has shut down before returning.
		1720	*/
		1721	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1722	enum pipe pipe)
		1723	{
3243	Serge	1724	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1725	pipe);
2327	Serge	1726	int reg;
		1727	u32 val;
		1728
3031	serge	1729	/*
2327	Serge	1730	* Make sure planes won't keep trying to pump pixels to us,
		1731	* or we might hang the display.
		1732	*/
		1733	assert_planes_disabled(dev_priv, pipe);
3746	Serge	1734	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	1735
		1736	/* Don't disable pipe A or pipe A PLLs if needed */
		1737	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1738	return;
		1739
3243	Serge	1740	reg = PIPECONF(cpu_transcoder);
2327	Serge	1741	val = I915_READ(reg);
		1742	if ((val & PIPECONF_ENABLE) == 0)
		1743	return;
		1744
		1745	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1746	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1747	}
		1748
		1749	/*
		1750	* Plane regs are double buffered, going from enabled->disabled needs a
		1751	* trigger in order to latch. The display address reg provides this.
		1752	*/
3031	serge	1753	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1754	enum plane plane)
		1755	{
3243	Serge	1756	if (dev_priv->info->gen >= 4)
		1757	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1758	else
2327	Serge	1759	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1760	}
		1761
		1762	/**
		1763	* intel_enable_plane - enable a display plane on a given pipe
		1764	* @dev_priv: i915 private structure
		1765	* @plane: plane to enable
		1766	* @pipe: pipe being fed
		1767	*
		1768	* Enable @plane on @pipe, making sure that @pipe is running first.
		1769	*/
		1770	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1771	enum plane plane, enum pipe pipe)
		1772	{
		1773	int reg;
		1774	u32 val;
		1775
		1776	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1777	assert_pipe_enabled(dev_priv, pipe);
		1778
		1779	reg = DSPCNTR(plane);
		1780	val = I915_READ(reg);
		1781	if (val & DISPLAY_PLANE_ENABLE)
		1782	return;
		1783
		1784	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1785	intel_flush_display_plane(dev_priv, plane);
		1786	intel_wait_for_vblank(dev_priv->dev, pipe);
		1787	}
		1788
		1789	/**
		1790	* intel_disable_plane - disable a display plane
		1791	* @dev_priv: i915 private structure
		1792	* @plane: plane to disable
		1793	* @pipe: pipe consuming the data
		1794	*
		1795	* Disable @plane; should be an independent operation.
		1796	*/
		1797	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1798	enum plane plane, enum pipe pipe)
		1799	{
		1800	int reg;
		1801	u32 val;
		1802
		1803	reg = DSPCNTR(plane);
		1804	val = I915_READ(reg);
		1805	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1806	return;
		1807
		1808	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1809	intel_flush_display_plane(dev_priv, plane);
3031	serge	1810	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1811	}
		1812
3746	Serge	1813	static bool need_vtd_wa(struct drm_device *dev)
		1814	{
		1815	#ifdef CONFIG_INTEL_IOMMU
		1816	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		1817	return true;
		1818	#endif
		1819	return false;
		1820	}
		1821
2335	Serge	1822	int
		1823	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1824	struct drm_i915_gem_object *obj,
		1825	struct intel_ring_buffer *pipelined)
		1826	{
		1827	struct drm_i915_private *dev_priv = dev->dev_private;
		1828	u32 alignment;
		1829	int ret;
2327	Serge	1830
2335	Serge	1831	switch (obj->tiling_mode) {
		1832	case I915_TILING_NONE:
		1833	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1834	alignment = 128 * 1024;
		1835	else if (INTEL_INFO(dev)->gen >= 4)
		1836	alignment = 4 * 1024;
		1837	else
		1838	alignment = 64 * 1024;
		1839	break;
		1840	case I915_TILING_X:
		1841	/* pin() will align the object as required by fence */
		1842	alignment = 0;
		1843	break;
		1844	case I915_TILING_Y:
3746	Serge	1845	/* Despite that we check this in framebuffer_init userspace can
		1846	* screw us over and change the tiling after the fact. Only
		1847	* pinned buffers can't change their tiling. */
		1848	DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2335	Serge	1849	return -EINVAL;
		1850	default:
		1851	BUG();
		1852	}
2327	Serge	1853
3746	Serge	1854	/* Note that the w/a also requires 64 PTE of padding following the
		1855	* bo. We currently fill all unused PTE with the shadow page and so
		1856	* we should always have valid PTE following the scanout preventing
		1857	* the VT-d warning.
		1858	*/
		1859	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		1860	alignment = 256 * 1024;
		1861
2335	Serge	1862	dev_priv->mm.interruptible = false;
		1863	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1864	if (ret)
		1865	goto err_interruptible;
2327	Serge	1866
2335	Serge	1867	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1868	* fence, whereas 965+ only requires a fence if using
		1869	* framebuffer compression. For simplicity, we always install
		1870	* a fence as the cost is not that onerous.
		1871	*/
3480	Serge	1872	ret = i915_gem_object_get_fence(obj);
		1873	if (ret)
		1874	goto err_unpin;
2327	Serge	1875
3480	Serge	1876	i915_gem_object_pin_fence(obj);
		1877
2335	Serge	1878	dev_priv->mm.interruptible = true;
		1879	return 0;
2327	Serge	1880
2335	Serge	1881	err_unpin:
4104	Serge	1882	i915_gem_object_unpin_from_display_plane(obj);
2335	Serge	1883	err_interruptible:
		1884	dev_priv->mm.interruptible = true;
		1885	return ret;
		1886	}
2327	Serge	1887
3031	serge	1888	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1889	{
		1890	// i915_gem_object_unpin_fence(obj);
		1891	// i915_gem_object_unpin(obj);
		1892	}
		1893
		1894	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1895	* is assumed to be a power-of-two. */
3480	Serge	1896	unsigned long intel_gen4_compute_page_offset(int x, int y,
		1897	unsigned int tiling_mode,
		1898	unsigned int cpp,
3031	serge	1899	unsigned int pitch)
		1900	{
3480	Serge	1901	if (tiling_mode != I915_TILING_NONE) {
		1902	unsigned int tile_rows, tiles;
3031	serge	1903
		1904	tile_rows = *y / 8;
		1905	*y %= 8;
		1906
3480	Serge	1907	tiles = *x / (512/cpp);
		1908	*x %= 512/cpp;
		1909
3031	serge	1910	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	1911	} else {
		1912	unsigned int offset;
		1913
		1914	offset = y pitch + x cpp;
		1915	*y = 0;
		1916	*x = (offset & 4095) / cpp;
		1917	return offset & -4096;
		1918	}
3031	serge	1919	}
		1920
2327	Serge	1921	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1922	int x, int y)
		1923	{
		1924	struct drm_device *dev = crtc->dev;
		1925	struct drm_i915_private *dev_priv = dev->dev_private;
		1926	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1927	struct intel_framebuffer *intel_fb;
		1928	struct drm_i915_gem_object *obj;
		1929	int plane = intel_crtc->plane;
3031	serge	1930	unsigned long linear_offset;
2327	Serge	1931	u32 dspcntr;
		1932	u32 reg;
		1933
		1934	switch (plane) {
		1935	case 0:
		1936	case 1:
		1937	break;
		1938	default:
4104	Serge	1939	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	1940	return -EINVAL;
		1941	}
		1942
		1943	intel_fb = to_intel_framebuffer(fb);
		1944	obj = intel_fb->obj;
		1945
		1946	reg = DSPCNTR(plane);
		1947	dspcntr = I915_READ(reg);
		1948	/* Mask out pixel format bits in case we change it */
		1949	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	1950	switch (fb->pixel_format) {
		1951	case DRM_FORMAT_C8:
2327	Serge	1952	dspcntr \|= DISPPLANE_8BPP;
		1953	break;
3243	Serge	1954	case DRM_FORMAT_XRGB1555:
		1955	case DRM_FORMAT_ARGB1555:
		1956	dspcntr \|= DISPPLANE_BGRX555;
		1957	break;
		1958	case DRM_FORMAT_RGB565:
		1959	dspcntr \|= DISPPLANE_BGRX565;
		1960	break;
		1961	case DRM_FORMAT_XRGB8888:
		1962	case DRM_FORMAT_ARGB8888:
		1963	dspcntr \|= DISPPLANE_BGRX888;
		1964	break;
		1965	case DRM_FORMAT_XBGR8888:
		1966	case DRM_FORMAT_ABGR8888:
		1967	dspcntr \|= DISPPLANE_RGBX888;
		1968	break;
		1969	case DRM_FORMAT_XRGB2101010:
		1970	case DRM_FORMAT_ARGB2101010:
		1971	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	1972	break;
3243	Serge	1973	case DRM_FORMAT_XBGR2101010:
		1974	case DRM_FORMAT_ABGR2101010:
		1975	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	1976	break;
		1977	default:
3746	Serge	1978	BUG();
2327	Serge	1979	}
3243	Serge	1980
2327	Serge	1981	if (INTEL_INFO(dev)->gen >= 4) {
		1982	if (obj->tiling_mode != I915_TILING_NONE)
		1983	dspcntr \|= DISPPLANE_TILED;
		1984	else
		1985	dspcntr &= ~DISPPLANE_TILED;
		1986	}
		1987
4104	Serge	1988	if (IS_G4X(dev))
		1989	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		1990
2327	Serge	1991	I915_WRITE(reg, dspcntr);
		1992
3031	serge	1993	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	1994
3031	serge	1995	if (INTEL_INFO(dev)->gen >= 4) {
		1996	intel_crtc->dspaddr_offset =
3480	Serge	1997	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	1998	fb->bits_per_pixel / 8,
		1999	fb->pitches[0]);
		2000	linear_offset -= intel_crtc->dspaddr_offset;
		2001	} else {
		2002	intel_crtc->dspaddr_offset = linear_offset;
		2003	}
		2004
4104	Serge	2005	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2006	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2007	fb->pitches[0]);
2342	Serge	2008	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2009	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2010	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2011	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	2012	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2013	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2014	} else
4104	Serge	2015	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2327	Serge	2016	POSTING_READ(reg);
		2017
		2018	return 0;
		2019	}
		2020
		2021	static int ironlake_update_plane(struct drm_crtc *crtc,
		2022	struct drm_framebuffer *fb, int x, int y)
		2023	{
		2024	struct drm_device *dev = crtc->dev;
		2025	struct drm_i915_private *dev_priv = dev->dev_private;
		2026	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2027	struct intel_framebuffer *intel_fb;
		2028	struct drm_i915_gem_object *obj;
		2029	int plane = intel_crtc->plane;
3031	serge	2030	unsigned long linear_offset;
2327	Serge	2031	u32 dspcntr;
		2032	u32 reg;
		2033
		2034	switch (plane) {
		2035	case 0:
		2036	case 1:
2342	Serge	2037	case 2:
2327	Serge	2038	break;
		2039	default:
4104	Serge	2040	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	2041	return -EINVAL;
		2042	}
		2043
		2044	intel_fb = to_intel_framebuffer(fb);
		2045	obj = intel_fb->obj;
		2046
		2047	reg = DSPCNTR(plane);
		2048	dspcntr = I915_READ(reg);
		2049	/* Mask out pixel format bits in case we change it */
		2050	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2051	switch (fb->pixel_format) {
		2052	case DRM_FORMAT_C8:
2327	Serge	2053	dspcntr \|= DISPPLANE_8BPP;
		2054	break;
3243	Serge	2055	case DRM_FORMAT_RGB565:
		2056	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2057	break;
3243	Serge	2058	case DRM_FORMAT_XRGB8888:
		2059	case DRM_FORMAT_ARGB8888:
		2060	dspcntr \|= DISPPLANE_BGRX888;
		2061	break;
		2062	case DRM_FORMAT_XBGR8888:
		2063	case DRM_FORMAT_ABGR8888:
		2064	dspcntr \|= DISPPLANE_RGBX888;
		2065	break;
		2066	case DRM_FORMAT_XRGB2101010:
		2067	case DRM_FORMAT_ARGB2101010:
		2068	dspcntr \|= DISPPLANE_BGRX101010;
		2069	break;
		2070	case DRM_FORMAT_XBGR2101010:
		2071	case DRM_FORMAT_ABGR2101010:
		2072	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2073	break;
		2074	default:
3746	Serge	2075	BUG();
2327	Serge	2076	}
		2077
3480	Serge	2078	if (obj->tiling_mode != I915_TILING_NONE)
		2079	dspcntr \|= DISPPLANE_TILED;
		2080	else
2327	Serge	2081	dspcntr &= ~DISPPLANE_TILED;
		2082
4104	Serge	2083	if (IS_HASWELL(dev))
		2084	dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
		2085	else
2327	Serge	2086	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2087
		2088	I915_WRITE(reg, dspcntr);
		2089
3031	serge	2090	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2091	intel_crtc->dspaddr_offset =
3480	Serge	2092	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2093	fb->bits_per_pixel / 8,
		2094	fb->pitches[0]);
		2095	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2096
4104	Serge	2097	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2098	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2099	fb->pitches[0]);
2342	Serge	2100	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2101	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2102	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3243	Serge	2103	if (IS_HASWELL(dev)) {
		2104	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2105	} else {
2330	Serge	2106	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2107	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2108	}
2330	Serge	2109	POSTING_READ(reg);
2327	Serge	2110
		2111	return 0;
		2112	}
		2113
		2114	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2115	static int
		2116	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2117	int x, int y, enum mode_set_atomic state)
		2118	{
		2119	struct drm_device *dev = crtc->dev;
		2120	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2121
		2122	if (dev_priv->display.disable_fbc)
		2123	dev_priv->display.disable_fbc(dev);
		2124	intel_increase_pllclock(crtc);
		2125
		2126	return dev_priv->display.update_plane(crtc, fb, x, y);
		2127	}
		2128
		2129	#if 0
4104	Serge	2130	void intel_display_handle_reset(struct drm_device *dev)
		2131	{
		2132	struct drm_i915_private *dev_priv = dev->dev_private;
		2133	struct drm_crtc *crtc;
		2134
		2135	/*
		2136	* Flips in the rings have been nuked by the reset,
		2137	* so complete all pending flips so that user space
		2138	* will get its events and not get stuck.
		2139	*
		2140	* Also update the base address of all primary
		2141	* planes to the the last fb to make sure we're
		2142	* showing the correct fb after a reset.
		2143	*
		2144	* Need to make two loops over the crtcs so that we
		2145	* don't try to grab a crtc mutex before the
		2146	* pending_flip_queue really got woken up.
		2147	*/
		2148
		2149	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2150	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2151	enum plane plane = intel_crtc->plane;
		2152
		2153	intel_prepare_page_flip(dev, plane);
		2154	intel_finish_page_flip_plane(dev, plane);
		2155	}
		2156
		2157	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2158	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2159
		2160	mutex_lock(&crtc->mutex);
		2161	if (intel_crtc->active)
		2162	dev_priv->display.update_plane(crtc, crtc->fb,
		2163	crtc->x, crtc->y);
		2164	mutex_unlock(&crtc->mutex);
		2165	}
		2166	}
		2167
3031	serge	2168	static int
		2169	intel_finish_fb(struct drm_framebuffer *old_fb)
		2170	{
		2171	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2172	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2173	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2174	int ret;
		2175
3031	serge	2176	/* Big Hammer, we also need to ensure that any pending
		2177	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2178	* current scanout is retired before unpinning the old
		2179	* framebuffer.
		2180	*
		2181	* This should only fail upon a hung GPU, in which case we
		2182	* can safely continue.
		2183	*/
		2184	dev_priv->mm.interruptible = false;
		2185	ret = i915_gem_object_finish_gpu(obj);
		2186	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2187
3031	serge	2188	return ret;
2327	Serge	2189	}
4104	Serge	2190
		2191	static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
		2192	{
		2193	struct drm_device *dev = crtc->dev;
		2194	struct drm_i915_master_private *master_priv;
		2195	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2196
		2197	if (!dev->primary->master)
		2198	return;
		2199
		2200	master_priv = dev->primary->master->driver_priv;
		2201	if (!master_priv->sarea_priv)
		2202	return;
		2203
		2204	switch (intel_crtc->pipe) {
		2205	case 0:
		2206	master_priv->sarea_priv->pipeA_x = x;
		2207	master_priv->sarea_priv->pipeA_y = y;
		2208	break;
		2209	case 1:
		2210	master_priv->sarea_priv->pipeB_x = x;
		2211	master_priv->sarea_priv->pipeB_y = y;
		2212	break;
		2213	default:
		2214	break;
		2215	}
		2216	}
3031	serge	2217	#endif
2327	Serge	2218
		2219	static int
		2220	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2221	struct drm_framebuffer *fb)
2327	Serge	2222	{
		2223	struct drm_device *dev = crtc->dev;
3031	serge	2224	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2225	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2226	struct drm_framebuffer *old_fb;
2342	Serge	2227	int ret;
2327	Serge	2228
		2229	/* no fb bound */
3031	serge	2230	if (!fb) {
2327	Serge	2231	DRM_ERROR("No FB bound\n");
		2232	return 0;
		2233	}
		2234
3746	Serge	2235	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
4104	Serge	2236	DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
		2237	plane_name(intel_crtc->plane),
3746	Serge	2238	INTEL_INFO(dev)->num_pipes);
2327	Serge	2239	return -EINVAL;
		2240	}
		2241
		2242	mutex_lock(&dev->struct_mutex);
4280	Serge	2243	ret = intel_pin_and_fence_fb_obj(dev,
		2244	to_intel_framebuffer(fb)->obj,
		2245	NULL);
		2246	if (ret != 0) {
		2247	mutex_unlock(&dev->struct_mutex);
		2248	DRM_ERROR("pin & fence failed\n");
		2249	return ret;
		2250	}
2327	Serge	2251
4280	Serge	2252	/* Update pipe size and adjust fitter if needed */
		2253	if (i915_fastboot) {
		2254	I915_WRITE(PIPESRC(intel_crtc->pipe),
		2255	((crtc->mode.hdisplay - 1) << 16) \|
		2256	(crtc->mode.vdisplay - 1));
		2257	if (!intel_crtc->config.pch_pfit.enabled &&
		2258	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\|
		2259	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
		2260	I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
		2261	I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
		2262	I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
		2263	}
		2264	}
3031	serge	2265
		2266	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2267	if (ret) {
3031	serge	2268	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2269	mutex_unlock(&dev->struct_mutex);
		2270	DRM_ERROR("failed to update base address\n");
3243	Serge	2271	return ret;
2327	Serge	2272	}
		2273
3031	serge	2274	old_fb = crtc->fb;
		2275	crtc->fb = fb;
		2276	crtc->x = x;
		2277	crtc->y = y;
		2278
		2279	if (old_fb) {
4104	Serge	2280	if (intel_crtc->active && old_fb != fb)
3031	serge	2281	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2282	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2283	}
		2284
		2285	intel_update_fbc(dev);
4104	Serge	2286	intel_edp_psr_update(dev);
2336	Serge	2287	mutex_unlock(&dev->struct_mutex);
2327	Serge	2288
2336	Serge	2289	return 0;
2327	Serge	2290	}
		2291
		2292	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2293	{
		2294	struct drm_device *dev = crtc->dev;
		2295	struct drm_i915_private *dev_priv = dev->dev_private;
		2296	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2297	int pipe = intel_crtc->pipe;
		2298	u32 reg, temp;
		2299
		2300	/* enable normal train */
		2301	reg = FDI_TX_CTL(pipe);
		2302	temp = I915_READ(reg);
		2303	if (IS_IVYBRIDGE(dev)) {
		2304	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2305	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2306	} else {
		2307	temp &= ~FDI_LINK_TRAIN_NONE;
		2308	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2309	}
		2310	I915_WRITE(reg, temp);
		2311
		2312	reg = FDI_RX_CTL(pipe);
		2313	temp = I915_READ(reg);
		2314	if (HAS_PCH_CPT(dev)) {
		2315	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2316	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2317	} else {
		2318	temp &= ~FDI_LINK_TRAIN_NONE;
		2319	temp \|= FDI_LINK_TRAIN_NONE;
		2320	}
		2321	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2322
		2323	/* wait one idle pattern time */
		2324	POSTING_READ(reg);
		2325	udelay(1000);
		2326
		2327	/* IVB wants error correction enabled */
		2328	if (IS_IVYBRIDGE(dev))
		2329	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2330	FDI_FE_ERRC_ENABLE);
		2331	}
		2332
4280	Serge	2333	static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
4104	Serge	2334	{
4280	Serge	2335	return crtc->base.enabled && crtc->active &&
		2336	crtc->config.has_pch_encoder;
4104	Serge	2337	}
		2338
3243	Serge	2339	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2340	{
		2341	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2342	struct intel_crtc *pipe_B_crtc =
		2343	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2344	struct intel_crtc *pipe_C_crtc =
		2345	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2346	uint32_t temp;
2327	Serge	2347
4104	Serge	2348	/*
		2349	* When everything is off disable fdi C so that we could enable fdi B
		2350	* with all lanes. Note that we don't care about enabled pipes without
		2351	* an enabled pch encoder.
		2352	*/
		2353	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
		2354	!pipe_has_enabled_pch(pipe_C_crtc)) {
3243	Serge	2355	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2356	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2357
		2358	temp = I915_READ(SOUTH_CHICKEN1);
		2359	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2360	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2361	I915_WRITE(SOUTH_CHICKEN1, temp);
		2362	}
2327	Serge	2363	}
		2364
		2365	/* The FDI link training functions for ILK/Ibexpeak. */
		2366	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2367	{
		2368	struct drm_device *dev = crtc->dev;
		2369	struct drm_i915_private *dev_priv = dev->dev_private;
		2370	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2371	int pipe = intel_crtc->pipe;
		2372	int plane = intel_crtc->plane;
		2373	u32 reg, temp, tries;
		2374
		2375	/* FDI needs bits from pipe & plane first */
		2376	assert_pipe_enabled(dev_priv, pipe);
		2377	assert_plane_enabled(dev_priv, plane);
		2378
		2379	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2380	for train result */
		2381	reg = FDI_RX_IMR(pipe);
		2382	temp = I915_READ(reg);
		2383	temp &= ~FDI_RX_SYMBOL_LOCK;
		2384	temp &= ~FDI_RX_BIT_LOCK;
		2385	I915_WRITE(reg, temp);
		2386	I915_READ(reg);
		2387	udelay(150);
		2388
		2389	/* enable CPU FDI TX and PCH FDI RX */
		2390	reg = FDI_TX_CTL(pipe);
		2391	temp = I915_READ(reg);
4104	Serge	2392	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2393	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2394	temp &= ~FDI_LINK_TRAIN_NONE;
		2395	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2396	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2397
		2398	reg = FDI_RX_CTL(pipe);
		2399	temp = I915_READ(reg);
		2400	temp &= ~FDI_LINK_TRAIN_NONE;
		2401	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2402	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2403
		2404	POSTING_READ(reg);
		2405	udelay(150);
		2406
		2407	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2408	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2409	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2410	FDI_RX_PHASE_SYNC_POINTER_EN);
		2411
		2412	reg = FDI_RX_IIR(pipe);
		2413	for (tries = 0; tries < 5; tries++) {
		2414	temp = I915_READ(reg);
		2415	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2416
		2417	if ((temp & FDI_RX_BIT_LOCK)) {
		2418	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2419	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2420	break;
		2421	}
		2422	}
		2423	if (tries == 5)
		2424	DRM_ERROR("FDI train 1 fail!\n");
		2425
		2426	/* Train 2 */
		2427	reg = FDI_TX_CTL(pipe);
		2428	temp = I915_READ(reg);
		2429	temp &= ~FDI_LINK_TRAIN_NONE;
		2430	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2431	I915_WRITE(reg, temp);
		2432
		2433	reg = FDI_RX_CTL(pipe);
		2434	temp = I915_READ(reg);
		2435	temp &= ~FDI_LINK_TRAIN_NONE;
		2436	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2437	I915_WRITE(reg, temp);
		2438
		2439	POSTING_READ(reg);
		2440	udelay(150);
		2441
		2442	reg = FDI_RX_IIR(pipe);
		2443	for (tries = 0; tries < 5; tries++) {
		2444	temp = I915_READ(reg);
		2445	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2446
		2447	if (temp & FDI_RX_SYMBOL_LOCK) {
		2448	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2449	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2450	break;
		2451	}
		2452	}
		2453	if (tries == 5)
		2454	DRM_ERROR("FDI train 2 fail!\n");
		2455
		2456	DRM_DEBUG_KMS("FDI train done\n");
		2457
		2458	}
		2459
2342	Serge	2460	static const int snb_b_fdi_train_param[] = {
2327	Serge	2461	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2462	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2463	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2464	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2465	};
		2466
		2467	/* The FDI link training functions for SNB/Cougarpoint. */
		2468	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2469	{
		2470	struct drm_device *dev = crtc->dev;
		2471	struct drm_i915_private *dev_priv = dev->dev_private;
		2472	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2473	int pipe = intel_crtc->pipe;
3031	serge	2474	u32 reg, temp, i, retry;
2327	Serge	2475
		2476	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2477	for train result */
		2478	reg = FDI_RX_IMR(pipe);
		2479	temp = I915_READ(reg);
		2480	temp &= ~FDI_RX_SYMBOL_LOCK;
		2481	temp &= ~FDI_RX_BIT_LOCK;
		2482	I915_WRITE(reg, temp);
		2483
		2484	POSTING_READ(reg);
		2485	udelay(150);
		2486
		2487	/* enable CPU FDI TX and PCH FDI RX */
		2488	reg = FDI_TX_CTL(pipe);
		2489	temp = I915_READ(reg);
4104	Serge	2490	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2491	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2492	temp &= ~FDI_LINK_TRAIN_NONE;
		2493	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2494	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2495	/* SNB-B */
		2496	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2497	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2498
3243	Serge	2499	I915_WRITE(FDI_RX_MISC(pipe),
		2500	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2501
2327	Serge	2502	reg = FDI_RX_CTL(pipe);
		2503	temp = I915_READ(reg);
		2504	if (HAS_PCH_CPT(dev)) {
		2505	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2506	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2507	} else {
		2508	temp &= ~FDI_LINK_TRAIN_NONE;
		2509	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2510	}
		2511	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2512
		2513	POSTING_READ(reg);
		2514	udelay(150);
		2515
2342	Serge	2516	for (i = 0; i < 4; i++) {
2327	Serge	2517	reg = FDI_TX_CTL(pipe);
		2518	temp = I915_READ(reg);
		2519	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2520	temp \|= snb_b_fdi_train_param[i];
		2521	I915_WRITE(reg, temp);
		2522
		2523	POSTING_READ(reg);
		2524	udelay(500);
		2525
3031	serge	2526	for (retry = 0; retry < 5; retry++) {
2327	Serge	2527	reg = FDI_RX_IIR(pipe);
		2528	temp = I915_READ(reg);
		2529	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2530	if (temp & FDI_RX_BIT_LOCK) {
		2531	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2532	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2533	break;
		2534	}
3031	serge	2535	udelay(50);
		2536	}
		2537	if (retry < 5)
		2538	break;
2327	Serge	2539	}
		2540	if (i == 4)
		2541	DRM_ERROR("FDI train 1 fail!\n");
		2542
		2543	/* Train 2 */
		2544	reg = FDI_TX_CTL(pipe);
		2545	temp = I915_READ(reg);
		2546	temp &= ~FDI_LINK_TRAIN_NONE;
		2547	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2548	if (IS_GEN6(dev)) {
		2549	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2550	/* SNB-B */
		2551	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2552	}
		2553	I915_WRITE(reg, temp);
		2554
		2555	reg = FDI_RX_CTL(pipe);
		2556	temp = I915_READ(reg);
		2557	if (HAS_PCH_CPT(dev)) {
		2558	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2559	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2560	} else {
		2561	temp &= ~FDI_LINK_TRAIN_NONE;
		2562	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2563	}
		2564	I915_WRITE(reg, temp);
		2565
		2566	POSTING_READ(reg);
		2567	udelay(150);
		2568
2342	Serge	2569	for (i = 0; i < 4; i++) {
2327	Serge	2570	reg = FDI_TX_CTL(pipe);
		2571	temp = I915_READ(reg);
		2572	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2573	temp \|= snb_b_fdi_train_param[i];
		2574	I915_WRITE(reg, temp);
		2575
		2576	POSTING_READ(reg);
		2577	udelay(500);
		2578
3031	serge	2579	for (retry = 0; retry < 5; retry++) {
2327	Serge	2580	reg = FDI_RX_IIR(pipe);
		2581	temp = I915_READ(reg);
		2582	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2583	if (temp & FDI_RX_SYMBOL_LOCK) {
		2584	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2585	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2586	break;
		2587	}
3031	serge	2588	udelay(50);
		2589	}
		2590	if (retry < 5)
		2591	break;
2327	Serge	2592	}
		2593	if (i == 4)
		2594	DRM_ERROR("FDI train 2 fail!\n");
		2595
		2596	DRM_DEBUG_KMS("FDI train done.\n");
		2597	}
		2598
		2599	/* Manual link training for Ivy Bridge A0 parts */
		2600	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2601	{
		2602	struct drm_device *dev = crtc->dev;
		2603	struct drm_i915_private *dev_priv = dev->dev_private;
		2604	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2605	int pipe = intel_crtc->pipe;
4104	Serge	2606	u32 reg, temp, i, j;
2327	Serge	2607
		2608	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2609	for train result */
		2610	reg = FDI_RX_IMR(pipe);
		2611	temp = I915_READ(reg);
		2612	temp &= ~FDI_RX_SYMBOL_LOCK;
		2613	temp &= ~FDI_RX_BIT_LOCK;
		2614	I915_WRITE(reg, temp);
		2615
		2616	POSTING_READ(reg);
		2617	udelay(150);
		2618
3243	Serge	2619	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		2620	I915_READ(FDI_RX_IIR(pipe)));
		2621
4104	Serge	2622	/* Try each vswing and preemphasis setting twice before moving on */
		2623	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		2624	/* disable first in case we need to retry */
		2625	reg = FDI_TX_CTL(pipe);
		2626	temp = I915_READ(reg);
		2627	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2628	temp &= ~FDI_TX_ENABLE;
		2629	I915_WRITE(reg, temp);
		2630
		2631	reg = FDI_RX_CTL(pipe);
		2632	temp = I915_READ(reg);
		2633	temp &= ~FDI_LINK_TRAIN_AUTO;
		2634	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2635	temp &= ~FDI_RX_ENABLE;
		2636	I915_WRITE(reg, temp);
		2637
2327	Serge	2638	/* enable CPU FDI TX and PCH FDI RX */
		2639	reg = FDI_TX_CTL(pipe);
		2640	temp = I915_READ(reg);
4104	Serge	2641	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2642	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2643	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2644	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	2645	temp \|= snb_b_fdi_train_param[j/2];
2342	Serge	2646	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2647	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2648
3243	Serge	2649	I915_WRITE(FDI_RX_MISC(pipe),
		2650	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2651
2327	Serge	2652	reg = FDI_RX_CTL(pipe);
		2653	temp = I915_READ(reg);
		2654	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2655	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2656	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2657
		2658	POSTING_READ(reg);
4104	Serge	2659	udelay(1); /* should be 0.5us */
2327	Serge	2660
2342	Serge	2661	for (i = 0; i < 4; i++) {
2327	Serge	2662	reg = FDI_RX_IIR(pipe);
		2663	temp = I915_READ(reg);
		2664	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2665
		2666	if (temp & FDI_RX_BIT_LOCK \|\|
		2667	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2668	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	2669	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		2670	i);
2327	Serge	2671	break;
		2672	}
4104	Serge	2673	udelay(1); /* should be 0.5us */
		2674	}
		2675	if (i == 4) {
		2676	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		2677	continue;
2327	Serge	2678	}
		2679
		2680	/* Train 2 */
		2681	reg = FDI_TX_CTL(pipe);
		2682	temp = I915_READ(reg);
		2683	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2684	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2685	I915_WRITE(reg, temp);
		2686
		2687	reg = FDI_RX_CTL(pipe);
		2688	temp = I915_READ(reg);
		2689	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2690	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2691	I915_WRITE(reg, temp);
		2692
		2693	POSTING_READ(reg);
4104	Serge	2694	udelay(2); /* should be 1.5us */
2327	Serge	2695
2342	Serge	2696	for (i = 0; i < 4; i++) {
2327	Serge	2697	reg = FDI_RX_IIR(pipe);
		2698	temp = I915_READ(reg);
		2699	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2700
4104	Serge	2701	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		2702	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2327	Serge	2703	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	2704	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		2705	i);
		2706	goto train_done;
2327	Serge	2707	}
4104	Serge	2708	udelay(2); /* should be 1.5us */
2327	Serge	2709	}
		2710	if (i == 4)
4104	Serge	2711	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		2712	}
2327	Serge	2713
4104	Serge	2714	train_done:
2327	Serge	2715	DRM_DEBUG_KMS("FDI train done.\n");
		2716	}
		2717
3031	serge	2718	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2719	{
3031	serge	2720	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2721	struct drm_i915_private *dev_priv = dev->dev_private;
		2722	int pipe = intel_crtc->pipe;
		2723	u32 reg, temp;
		2724
		2725
		2726	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2727	reg = FDI_RX_CTL(pipe);
		2728	temp = I915_READ(reg);
4104	Serge	2729	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
		2730	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3480	Serge	2731	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2732	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2733
		2734	POSTING_READ(reg);
		2735	udelay(200);
		2736
		2737	/* Switch from Rawclk to PCDclk */
		2738	temp = I915_READ(reg);
		2739	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2740
		2741	POSTING_READ(reg);
		2742	udelay(200);
		2743
		2744	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2745	reg = FDI_TX_CTL(pipe);
		2746	temp = I915_READ(reg);
		2747	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2748	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2749
		2750	POSTING_READ(reg);
		2751	udelay(100);
		2752	}
		2753	}
		2754
3031	serge	2755	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2756	{
		2757	struct drm_device *dev = intel_crtc->base.dev;
		2758	struct drm_i915_private *dev_priv = dev->dev_private;
		2759	int pipe = intel_crtc->pipe;
		2760	u32 reg, temp;
		2761
		2762	/* Switch from PCDclk to Rawclk */
		2763	reg = FDI_RX_CTL(pipe);
		2764	temp = I915_READ(reg);
		2765	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2766
		2767	/* Disable CPU FDI TX PLL */
		2768	reg = FDI_TX_CTL(pipe);
		2769	temp = I915_READ(reg);
		2770	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2771
		2772	POSTING_READ(reg);
		2773	udelay(100);
		2774
		2775	reg = FDI_RX_CTL(pipe);
		2776	temp = I915_READ(reg);
		2777	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2778
		2779	/* Wait for the clocks to turn off. */
		2780	POSTING_READ(reg);
		2781	udelay(100);
		2782	}
		2783
2327	Serge	2784	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2785	{
		2786	struct drm_device *dev = crtc->dev;
		2787	struct drm_i915_private *dev_priv = dev->dev_private;
		2788	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2789	int pipe = intel_crtc->pipe;
		2790	u32 reg, temp;
		2791
		2792	/* disable CPU FDI tx and PCH FDI rx */
		2793	reg = FDI_TX_CTL(pipe);
		2794	temp = I915_READ(reg);
		2795	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2796	POSTING_READ(reg);
		2797
		2798	reg = FDI_RX_CTL(pipe);
		2799	temp = I915_READ(reg);
		2800	temp &= ~(0x7 << 16);
3480	Serge	2801	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2802	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2803
		2804	POSTING_READ(reg);
		2805	udelay(100);
		2806
		2807	/* Ironlake workaround, disable clock pointer after downing FDI */
		2808	if (HAS_PCH_IBX(dev)) {
		2809	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2810	}
		2811
		2812	/* still set train pattern 1 */
		2813	reg = FDI_TX_CTL(pipe);
		2814	temp = I915_READ(reg);
		2815	temp &= ~FDI_LINK_TRAIN_NONE;
		2816	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2817	I915_WRITE(reg, temp);
		2818
		2819	reg = FDI_RX_CTL(pipe);
		2820	temp = I915_READ(reg);
		2821	if (HAS_PCH_CPT(dev)) {
		2822	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2823	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2824	} else {
		2825	temp &= ~FDI_LINK_TRAIN_NONE;
		2826	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2827	}
		2828	/* BPC in FDI rx is consistent with that in PIPECONF */
		2829	temp &= ~(0x07 << 16);
3480	Serge	2830	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2831	I915_WRITE(reg, temp);
		2832
		2833	POSTING_READ(reg);
		2834	udelay(100);
		2835	}
		2836
3031	serge	2837	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2838	{
3031	serge	2839	struct drm_device *dev = crtc->dev;
2327	Serge	2840	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2841	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2842	unsigned long flags;
		2843	bool pending;
2327	Serge	2844
3480	Serge	2845	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2846	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3031	serge	2847	return false;
2327	Serge	2848
3031	serge	2849	spin_lock_irqsave(&dev->event_lock, flags);
		2850	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2851	spin_unlock_irqrestore(&dev->event_lock, flags);
		2852
		2853	return pending;
2327	Serge	2854	}
		2855
3031	serge	2856	#if 0
2327	Serge	2857	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2858	{
3031	serge	2859	struct drm_device *dev = crtc->dev;
		2860	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2861
		2862	if (crtc->fb == NULL)
		2863	return;
		2864
3480	Serge	2865	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		2866
2360	Serge	2867	wait_event(dev_priv->pending_flip_queue,
3031	serge	2868	!intel_crtc_has_pending_flip(crtc));
		2869
		2870	mutex_lock(&dev->struct_mutex);
		2871	intel_finish_fb(crtc->fb);
		2872	mutex_unlock(&dev->struct_mutex);
2327	Serge	2873	}
3031	serge	2874	#endif
2327	Serge	2875
3031	serge	2876	/* Program iCLKIP clock to the desired frequency */
		2877	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2878	{
		2879	struct drm_device *dev = crtc->dev;
		2880	struct drm_i915_private *dev_priv = dev->dev_private;
		2881	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2882	u32 temp;
		2883
3480	Serge	2884	mutex_lock(&dev_priv->dpio_lock);
		2885
3031	serge	2886	/* It is necessary to ungate the pixclk gate prior to programming
		2887	* the divisors, and gate it back when it is done.
		2888	*/
		2889	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2890
		2891	/* Disable SSCCTL */
		2892	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	2893	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		2894	SBI_SSCCTL_DISABLE,
		2895	SBI_ICLK);
3031	serge	2896
		2897	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2898	if (crtc->mode.clock == 20000) {
		2899	auxdiv = 1;
		2900	divsel = 0x41;
		2901	phaseinc = 0x20;
		2902	} else {
		2903	/* The iCLK virtual clock root frequency is in MHz,
		2904	* but the crtc->mode.clock in in KHz. To get the divisors,
		2905	* it is necessary to divide one by another, so we
		2906	* convert the virtual clock precision to KHz here for higher
		2907	* precision.
		2908	*/
		2909	u32 iclk_virtual_root_freq = 172800 * 1000;
		2910	u32 iclk_pi_range = 64;
		2911	u32 desired_divisor, msb_divisor_value, pi_value;
		2912
		2913	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2914	msb_divisor_value = desired_divisor / iclk_pi_range;
		2915	pi_value = desired_divisor % iclk_pi_range;
		2916
		2917	auxdiv = 0;
		2918	divsel = msb_divisor_value - 2;
		2919	phaseinc = pi_value;
		2920	}
		2921
		2922	/* This should not happen with any sane values */
		2923	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2924	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2925	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2926	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2927
		2928	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2929	crtc->mode.clock,
		2930	auxdiv,
		2931	divsel,
		2932	phasedir,
		2933	phaseinc);
		2934
		2935	/* Program SSCDIVINTPHASE6 */
3243	Serge	2936	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	2937	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2938	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2939	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2940	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2941	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2942	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	2943	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	2944
		2945	/* Program SSCAUXDIV */
3243	Serge	2946	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	2947	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2948	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	2949	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	2950
		2951	/* Enable modulator and associated divider */
3243	Serge	2952	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	2953	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	2954	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	2955
		2956	/* Wait for initialization time */
		2957	udelay(24);
		2958
		2959	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	2960
		2961	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	2962	}
		2963
4104	Serge	2964	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		2965	enum pipe pch_transcoder)
		2966	{
		2967	struct drm_device *dev = crtc->base.dev;
		2968	struct drm_i915_private *dev_priv = dev->dev_private;
		2969	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
		2970
		2971	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		2972	I915_READ(HTOTAL(cpu_transcoder)));
		2973	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		2974	I915_READ(HBLANK(cpu_transcoder)));
		2975	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		2976	I915_READ(HSYNC(cpu_transcoder)));
		2977
		2978	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		2979	I915_READ(VTOTAL(cpu_transcoder)));
		2980	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		2981	I915_READ(VBLANK(cpu_transcoder)));
		2982	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		2983	I915_READ(VSYNC(cpu_transcoder)));
		2984	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		2985	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		2986	}
		2987
4280	Serge	2988	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		2989	{
		2990	struct drm_i915_private *dev_priv = dev->dev_private;
		2991	uint32_t temp;
		2992
		2993	temp = I915_READ(SOUTH_CHICKEN1);
		2994	if (temp & FDI_BC_BIFURCATION_SELECT)
		2995	return;
		2996
		2997	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2998	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2999
		3000	temp \|= FDI_BC_BIFURCATION_SELECT;
		3001	DRM_DEBUG_KMS("enabling fdi C rx\n");
		3002	I915_WRITE(SOUTH_CHICKEN1, temp);
		3003	POSTING_READ(SOUTH_CHICKEN1);
		3004	}
		3005
		3006	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
		3007	{
		3008	struct drm_device *dev = intel_crtc->base.dev;
		3009	struct drm_i915_private *dev_priv = dev->dev_private;
		3010
		3011	switch (intel_crtc->pipe) {
		3012	case PIPE_A:
		3013	break;
		3014	case PIPE_B:
		3015	if (intel_crtc->config.fdi_lanes > 2)
		3016	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		3017	else
		3018	cpt_enable_fdi_bc_bifurcation(dev);
		3019
		3020	break;
		3021	case PIPE_C:
		3022	cpt_enable_fdi_bc_bifurcation(dev);
		3023
		3024	break;
		3025	default:
		3026	BUG();
		3027	}
		3028	}
		3029
2327	Serge	3030	/*
		3031	* Enable PCH resources required for PCH ports:
		3032	* - PCH PLLs
		3033	* - FDI training & RX/TX
		3034	* - update transcoder timings
		3035	* - DP transcoding bits
		3036	* - transcoder
		3037	*/
		3038	static void ironlake_pch_enable(struct drm_crtc *crtc)
		3039	{
		3040	struct drm_device *dev = crtc->dev;
		3041	struct drm_i915_private *dev_priv = dev->dev_private;
		3042	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3043	int pipe = intel_crtc->pipe;
3031	serge	3044	u32 reg, temp;
2327	Serge	3045
4104	Serge	3046	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	3047
4280	Serge	3048	if (IS_IVYBRIDGE(dev))
		3049	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
		3050
3243	Serge	3051	/* Write the TU size bits before fdi link training, so that error
		3052	* detection works. */
		3053	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		3054	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		3055
2327	Serge	3056	/* For PCH output, training FDI link */
		3057	dev_priv->display.fdi_link_train(crtc);
		3058
4104	Serge	3059	/* We need to program the right clock selection before writing the pixel
		3060	* mutliplier into the DPLL. */
3243	Serge	3061	if (HAS_PCH_CPT(dev)) {
3031	serge	3062	u32 sel;
2342	Serge	3063
2327	Serge	3064	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3065	temp \|= TRANS_DPLL_ENABLE(pipe);
		3066	sel = TRANS_DPLLB_SEL(pipe);
		3067	if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	3068	temp \|= sel;
		3069	else
		3070	temp &= ~sel;
2327	Serge	3071	I915_WRITE(PCH_DPLL_SEL, temp);
		3072	}
		3073
4104	Serge	3074	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3075	* transcoder, and we actually should do this to not upset any PCH
		3076	* transcoder that already use the clock when we share it.
		3077	*
		3078	* Note that enable_shared_dpll tries to do the right thing, but
		3079	* get_shared_dpll unconditionally resets the pll - we need that to have
		3080	* the right LVDS enable sequence. */
		3081	ironlake_enable_shared_dpll(intel_crtc);
		3082
2327	Serge	3083	/* set transcoder timing, panel must allow it */
		3084	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	3085	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	3086
		3087	intel_fdi_normal_train(crtc);
		3088
		3089	/* For PCH DP, enable TRANS_DP_CTL */
		3090	if (HAS_PCH_CPT(dev) &&
2342	Serge	3091	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3092	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3093	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3094	reg = TRANS_DP_CTL(pipe);
		3095	temp = I915_READ(reg);
		3096	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3097	TRANS_DP_SYNC_MASK \|
		3098	TRANS_DP_BPC_MASK);
		3099	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3100	TRANS_DP_ENH_FRAMING);
		3101	temp \|= bpc << 9; /* same format but at 11:9 */
		3102
		3103	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3104	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3105	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3106	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3107
		3108	switch (intel_trans_dp_port_sel(crtc)) {
		3109	case PCH_DP_B:
		3110	temp \|= TRANS_DP_PORT_SEL_B;
		3111	break;
		3112	case PCH_DP_C:
		3113	temp \|= TRANS_DP_PORT_SEL_C;
		3114	break;
		3115	case PCH_DP_D:
		3116	temp \|= TRANS_DP_PORT_SEL_D;
		3117	break;
		3118	default:
3243	Serge	3119	BUG();
2327	Serge	3120	}
		3121
		3122	I915_WRITE(reg, temp);
		3123	}
		3124
3243	Serge	3125	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3126	}
		3127
3243	Serge	3128	static void lpt_pch_enable(struct drm_crtc *crtc)
		3129	{
		3130	struct drm_device *dev = crtc->dev;
		3131	struct drm_i915_private *dev_priv = dev->dev_private;
		3132	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3133	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3134
4104	Serge	3135	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	3136
		3137	lpt_program_iclkip(crtc);
		3138
		3139	/* Set transcoder timing. */
4104	Serge	3140	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	3141
		3142	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3143	}
		3144
4104	Serge	3145	static void intel_put_shared_dpll(struct intel_crtc *crtc)
3031	serge	3146	{
4104	Serge	3147	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031	serge	3148
		3149	if (pll == NULL)
		3150	return;
		3151
		3152	if (pll->refcount == 0) {
4104	Serge	3153	WARN(1, "bad %s refcount\n", pll->name);
3031	serge	3154	return;
		3155	}
		3156
4104	Serge	3157	if (--pll->refcount == 0) {
		3158	WARN_ON(pll->on);
		3159	WARN_ON(pll->active);
		3160	}
		3161
		3162	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3031	serge	3163	}
		3164
4104	Serge	3165	static struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc)
3031	serge	3166	{
4104	Serge	3167	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3168	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		3169	enum intel_dpll_id i;
3031	serge	3170
		3171	if (pll) {
4104	Serge	3172	DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
		3173	crtc->base.base.id, pll->name);
		3174	intel_put_shared_dpll(crtc);
3031	serge	3175	}
		3176
		3177	if (HAS_PCH_IBX(dev_priv->dev)) {
		3178	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	3179	i = (enum intel_dpll_id) crtc->pipe;
		3180	pll = &dev_priv->shared_dplls[i];
3031	serge	3181
4104	Serge	3182	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		3183	crtc->base.base.id, pll->name);
3031	serge	3184
		3185	goto found;
		3186	}
		3187
4104	Serge	3188	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3189	pll = &dev_priv->shared_dplls[i];
3031	serge	3190
		3191	/* Only want to check enabled timings first */
		3192	if (pll->refcount == 0)
		3193	continue;
		3194
4104	Serge	3195	if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
		3196	sizeof(pll->hw_state)) == 0) {
		3197	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
		3198	crtc->base.base.id,
		3199	pll->name, pll->refcount, pll->active);
3031	serge	3200
		3201	goto found;
		3202	}
		3203	}
		3204
		3205	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	3206	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3207	pll = &dev_priv->shared_dplls[i];
3031	serge	3208	if (pll->refcount == 0) {
4104	Serge	3209	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		3210	crtc->base.base.id, pll->name);
3031	serge	3211	goto found;
		3212	}
		3213	}
		3214
		3215	return NULL;
		3216
		3217	found:
4104	Serge	3218	crtc->config.shared_dpll = i;
		3219	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		3220	pipe_name(crtc->pipe));
		3221
		3222	if (pll->active == 0) {
		3223	memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
		3224	sizeof(pll->hw_state));
		3225
		3226	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		3227	WARN_ON(pll->on);
		3228	assert_shared_dpll_disabled(dev_priv, pll);
		3229
		3230	pll->mode_set(dev_priv, pll);
		3231	}
3031	serge	3232	pll->refcount++;
		3233
		3234	return pll;
		3235	}
		3236
4104	Serge	3237	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
2342	Serge	3238	{
		3239	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3240	int dslreg = PIPEDSL(pipe);
2342	Serge	3241	u32 temp;
		3242
		3243	temp = I915_READ(dslreg);
		3244	udelay(500);
		3245	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3246	if (wait_for(I915_READ(dslreg) != temp, 5))
4104	Serge	3247	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
2342	Serge	3248	}
		3249	}
		3250
4104	Serge	3251	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		3252	{
		3253	struct drm_device *dev = crtc->base.dev;
		3254	struct drm_i915_private *dev_priv = dev->dev_private;
		3255	int pipe = crtc->pipe;
		3256
		3257	if (crtc->config.pch_pfit.enabled) {
		3258	/* Force use of hard-coded filter coefficients
		3259	* as some pre-programmed values are broken,
		3260	* e.g. x201.
		3261	*/
		3262	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		3263	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3264	PF_PIPE_SEL_IVB(pipe));
		3265	else
		3266	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3267	I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		3268	I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
		3269	}
		3270	}
		3271
		3272	static void intel_enable_planes(struct drm_crtc *crtc)
		3273	{
		3274	struct drm_device *dev = crtc->dev;
		3275	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3276	struct intel_plane *intel_plane;
		3277
		3278	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3279	if (intel_plane->pipe == pipe)
		3280	intel_plane_restore(&intel_plane->base);
		3281	}
		3282
		3283	static void intel_disable_planes(struct drm_crtc *crtc)
		3284	{
		3285	struct drm_device *dev = crtc->dev;
		3286	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3287	struct intel_plane *intel_plane;
		3288
		3289	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3290	if (intel_plane->pipe == pipe)
		3291	intel_plane_disable(&intel_plane->base);
		3292	}
		3293
2327	Serge	3294	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3295	{
		3296	struct drm_device *dev = crtc->dev;
		3297	struct drm_i915_private *dev_priv = dev->dev_private;
		3298	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3299	struct intel_encoder *encoder;
2327	Serge	3300	int pipe = intel_crtc->pipe;
		3301	int plane = intel_crtc->plane;
		3302
3031	serge	3303	WARN_ON(!crtc->enabled);
		3304
2327	Serge	3305	if (intel_crtc->active)
		3306	return;
		3307
		3308	intel_crtc->active = true;
4104	Serge	3309
		3310	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3311	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
		3312
2327	Serge	3313	intel_update_watermarks(dev);
		3314
4104	Serge	3315	for_each_encoder_on_crtc(dev, crtc, encoder)
		3316	if (encoder->pre_enable)
		3317	encoder->pre_enable(encoder);
2327	Serge	3318
3746	Serge	3319	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3320	/* Note: FDI PLL enabling _must_ be done before we enable the
		3321	* cpu pipes, hence this is separate from all the other fdi/pch
		3322	* enabling. */
3031	serge	3323	ironlake_fdi_pll_enable(intel_crtc);
		3324	} else {
		3325	assert_fdi_tx_disabled(dev_priv, pipe);
		3326	assert_fdi_rx_disabled(dev_priv, pipe);
		3327	}
2327	Serge	3328
4104	Serge	3329	ironlake_pfit_enable(intel_crtc);
3031	serge	3330
2327	Serge	3331	/*
		3332	* On ILK+ LUT must be loaded before the pipe is running but with
		3333	* clocks enabled
		3334	*/
		3335	intel_crtc_load_lut(crtc);
		3336
3746	Serge	3337	intel_enable_pipe(dev_priv, pipe,
		3338	intel_crtc->config.has_pch_encoder);
2327	Serge	3339	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3340	intel_enable_planes(crtc);
		3341	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3342
3746	Serge	3343	if (intel_crtc->config.has_pch_encoder)
2327	Serge	3344	ironlake_pch_enable(crtc);
		3345
		3346	mutex_lock(&dev->struct_mutex);
		3347	intel_update_fbc(dev);
		3348	mutex_unlock(&dev->struct_mutex);
		3349
3031	serge	3350	for_each_encoder_on_crtc(dev, crtc, encoder)
		3351	encoder->enable(encoder);
		3352
		3353	if (HAS_PCH_CPT(dev))
4104	Serge	3354	cpt_verify_modeset(dev, intel_crtc->pipe);
3031	serge	3355
		3356	/*
		3357	* There seems to be a race in PCH platform hw (at least on some
		3358	* outputs) where an enabled pipe still completes any pageflip right
		3359	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3360	* as the first vblank happend, everything works as expected. Hence just
		3361	* wait for one vblank before returning to avoid strange things
		3362	* happening.
		3363	*/
		3364	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3365	}
		3366
4104	Serge	3367	/* IPS only exists on ULT machines and is tied to pipe A. */
		3368	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		3369	{
		3370	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		3371	}
		3372
		3373	static void hsw_enable_ips(struct intel_crtc *crtc)
		3374	{
		3375	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3376
		3377	if (!crtc->config.ips_enabled)
		3378	return;
		3379
		3380	/* We can only enable IPS after we enable a plane and wait for a vblank.
		3381	* We guarantee that the plane is enabled by calling intel_enable_ips
		3382	* only after intel_enable_plane. And intel_enable_plane already waits
		3383	* for a vblank, so all we need to do here is to enable the IPS bit. */
		3384	assert_plane_enabled(dev_priv, crtc->plane);
		3385	I915_WRITE(IPS_CTL, IPS_ENABLE);
		3386	}
		3387
		3388	static void hsw_disable_ips(struct intel_crtc *crtc)
		3389	{
		3390	struct drm_device *dev = crtc->base.dev;
		3391	struct drm_i915_private *dev_priv = dev->dev_private;
		3392
		3393	if (!crtc->config.ips_enabled)
		3394	return;
		3395
		3396	assert_plane_enabled(dev_priv, crtc->plane);
		3397	I915_WRITE(IPS_CTL, 0);
		3398
		3399	/* We need to wait for a vblank before we can disable the plane. */
		3400	intel_wait_for_vblank(dev, crtc->pipe);
		3401	}
		3402
3243	Serge	3403	static void haswell_crtc_enable(struct drm_crtc *crtc)
		3404	{
		3405	struct drm_device *dev = crtc->dev;
		3406	struct drm_i915_private *dev_priv = dev->dev_private;
		3407	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3408	struct intel_encoder *encoder;
		3409	int pipe = intel_crtc->pipe;
		3410	int plane = intel_crtc->plane;
		3411
		3412	WARN_ON(!crtc->enabled);
		3413
		3414	if (intel_crtc->active)
		3415	return;
		3416
		3417	intel_crtc->active = true;
4104	Serge	3418
		3419	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3420	if (intel_crtc->config.has_pch_encoder)
		3421	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
		3422
3243	Serge	3423	intel_update_watermarks(dev);
		3424
3746	Serge	3425	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3426	dev_priv->display.fdi_link_train(crtc);
		3427
		3428	for_each_encoder_on_crtc(dev, crtc, encoder)
		3429	if (encoder->pre_enable)
		3430	encoder->pre_enable(encoder);
		3431
		3432	intel_ddi_enable_pipe_clock(intel_crtc);
		3433
4104	Serge	3434	ironlake_pfit_enable(intel_crtc);
3243	Serge	3435
		3436	/*
		3437	* On ILK+ LUT must be loaded before the pipe is running but with
		3438	* clocks enabled
		3439	*/
		3440	intel_crtc_load_lut(crtc);
		3441
		3442	intel_ddi_set_pipe_settings(crtc);
3746	Serge	3443	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	3444
3746	Serge	3445	intel_enable_pipe(dev_priv, pipe,
		3446	intel_crtc->config.has_pch_encoder);
3243	Serge	3447	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3448	intel_enable_planes(crtc);
		3449	// intel_crtc_update_cursor(crtc, true);
3243	Serge	3450
4104	Serge	3451	hsw_enable_ips(intel_crtc);
		3452
3746	Serge	3453	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3454	lpt_pch_enable(crtc);
		3455
		3456	mutex_lock(&dev->struct_mutex);
		3457	intel_update_fbc(dev);
		3458	mutex_unlock(&dev->struct_mutex);
		3459
		3460	for_each_encoder_on_crtc(dev, crtc, encoder)
		3461	encoder->enable(encoder);
		3462
		3463	/*
		3464	* There seems to be a race in PCH platform hw (at least on some
		3465	* outputs) where an enabled pipe still completes any pageflip right
		3466	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3467	* as the first vblank happend, everything works as expected. Hence just
		3468	* wait for one vblank before returning to avoid strange things
		3469	* happening.
		3470	*/
		3471	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3472	}
		3473
4104	Serge	3474	static void ironlake_pfit_disable(struct intel_crtc *crtc)
		3475	{
		3476	struct drm_device *dev = crtc->base.dev;
		3477	struct drm_i915_private *dev_priv = dev->dev_private;
		3478	int pipe = crtc->pipe;
		3479
		3480	/* To avoid upsetting the power well on haswell only disable the pfit if
		3481	* it's in use. The hw state code will make sure we get this right. */
		3482	if (crtc->config.pch_pfit.enabled) {
		3483	I915_WRITE(PF_CTL(pipe), 0);
		3484	I915_WRITE(PF_WIN_POS(pipe), 0);
		3485	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3486	}
		3487	}
		3488
2327	Serge	3489	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3490	{
		3491	struct drm_device *dev = crtc->dev;
		3492	struct drm_i915_private *dev_priv = dev->dev_private;
		3493	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3494	struct intel_encoder *encoder;
2327	Serge	3495	int pipe = intel_crtc->pipe;
		3496	int plane = intel_crtc->plane;
		3497	u32 reg, temp;
		3498
3031	serge	3499
2327	Serge	3500	if (!intel_crtc->active)
		3501	return;
		3502
3031	serge	3503	for_each_encoder_on_crtc(dev, crtc, encoder)
		3504	encoder->disable(encoder);
2336	Serge	3505
3031	serge	3506	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3507	// drm_vblank_off(dev, pipe);
		3508
4104	Serge	3509	if (dev_priv->fbc.plane == plane)
		3510	intel_disable_fbc(dev);
		3511
		3512	// intel_crtc_update_cursor(crtc, false);
		3513	intel_disable_planes(crtc);
2327	Serge	3514	intel_disable_plane(dev_priv, plane, pipe);
		3515
4104	Serge	3516	if (intel_crtc->config.has_pch_encoder)
		3517	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
2327	Serge	3518
		3519	intel_disable_pipe(dev_priv, pipe);
		3520
4104	Serge	3521	ironlake_pfit_disable(intel_crtc);
2327	Serge	3522
3031	serge	3523	for_each_encoder_on_crtc(dev, crtc, encoder)
		3524	if (encoder->post_disable)
		3525	encoder->post_disable(encoder);
		3526
4104	Serge	3527	if (intel_crtc->config.has_pch_encoder) {
2327	Serge	3528	ironlake_fdi_disable(crtc);
		3529
3243	Serge	3530	ironlake_disable_pch_transcoder(dev_priv, pipe);
4104	Serge	3531	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
2327	Serge	3532
		3533	if (HAS_PCH_CPT(dev)) {
		3534	/* disable TRANS_DP_CTL */
		3535	reg = TRANS_DP_CTL(pipe);
		3536	temp = I915_READ(reg);
4104	Serge	3537	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		3538	TRANS_DP_PORT_SEL_MASK);
2327	Serge	3539	temp \|= TRANS_DP_PORT_SEL_NONE;
		3540	I915_WRITE(reg, temp);
		3541
		3542	/* disable DPLL_SEL */
		3543	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3544	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
2327	Serge	3545	I915_WRITE(PCH_DPLL_SEL, temp);
		3546	}
		3547
		3548	/* disable PCH DPLL */
4104	Serge	3549	intel_disable_shared_dpll(intel_crtc);
2327	Serge	3550
3031	serge	3551	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	3552	}
2327	Serge	3553
		3554	intel_crtc->active = false;
		3555	intel_update_watermarks(dev);
		3556
		3557	mutex_lock(&dev->struct_mutex);
		3558	intel_update_fbc(dev);
		3559	mutex_unlock(&dev->struct_mutex);
		3560	}
		3561
3243	Serge	3562	static void haswell_crtc_disable(struct drm_crtc *crtc)
		3563	{
		3564	struct drm_device *dev = crtc->dev;
		3565	struct drm_i915_private *dev_priv = dev->dev_private;
		3566	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3567	struct intel_encoder *encoder;
		3568	int pipe = intel_crtc->pipe;
		3569	int plane = intel_crtc->plane;
3746	Serge	3570	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3571
		3572	if (!intel_crtc->active)
		3573	return;
		3574
		3575	for_each_encoder_on_crtc(dev, crtc, encoder)
		3576	encoder->disable(encoder);
		3577
		3578
4104	Serge	3579	/* FBC must be disabled before disabling the plane on HSW. */
		3580	if (dev_priv->fbc.plane == plane)
		3581	intel_disable_fbc(dev);
		3582
		3583	hsw_disable_ips(intel_crtc);
		3584
		3585	// intel_crtc_update_cursor(crtc, false);
		3586	intel_disable_planes(crtc);
3243	Serge	3587	intel_disable_plane(dev_priv, plane, pipe);
		3588
4104	Serge	3589	if (intel_crtc->config.has_pch_encoder)
		3590	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3243	Serge	3591	intel_disable_pipe(dev_priv, pipe);
		3592
		3593	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		3594
4104	Serge	3595	ironlake_pfit_disable(intel_crtc);
3243	Serge	3596
		3597	intel_ddi_disable_pipe_clock(intel_crtc);
		3598
		3599	for_each_encoder_on_crtc(dev, crtc, encoder)
		3600	if (encoder->post_disable)
		3601	encoder->post_disable(encoder);
		3602
3746	Serge	3603	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3604	lpt_disable_pch_transcoder(dev_priv);
4104	Serge	3605	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3243	Serge	3606	intel_ddi_fdi_disable(crtc);
		3607	}
		3608
		3609	intel_crtc->active = false;
		3610	intel_update_watermarks(dev);
		3611
		3612	mutex_lock(&dev->struct_mutex);
		3613	intel_update_fbc(dev);
		3614	mutex_unlock(&dev->struct_mutex);
		3615	}
		3616
3031	serge	3617	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3618	{
		3619	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	3620	intel_put_shared_dpll(intel_crtc);
2327	Serge	3621	}
		3622
3243	Serge	3623	static void haswell_crtc_off(struct drm_crtc *crtc)
		3624	{
		3625	intel_ddi_put_crtc_pll(crtc);
		3626	}
		3627
2327	Serge	3628	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3629	{
		3630	if (!enable && intel_crtc->overlay) {
		3631	struct drm_device *dev = intel_crtc->base.dev;
		3632	struct drm_i915_private *dev_priv = dev->dev_private;
		3633
		3634	mutex_lock(&dev->struct_mutex);
		3635	dev_priv->mm.interruptible = false;
		3636	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3637	dev_priv->mm.interruptible = true;
		3638	mutex_unlock(&dev->struct_mutex);
		3639	}
		3640
		3641	/* Let userspace switch the overlay on again. In most cases userspace
		3642	* has to recompute where to put it anyway.
		3643	*/
		3644	}
		3645
3480	Serge	3646	/**
		3647	* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
		3648	* cursor plane briefly if not already running after enabling the display
		3649	* plane.
		3650	* This workaround avoids occasional blank screens when self refresh is
		3651	* enabled.
		3652	*/
		3653	static void
		3654	g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
		3655	{
		3656	u32 cntl = I915_READ(CURCNTR(pipe));
		3657
		3658	if ((cntl & CURSOR_MODE) == 0) {
		3659	u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
		3660
		3661	I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		3662	I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		3663	intel_wait_for_vblank(dev_priv->dev, pipe);
		3664	I915_WRITE(CURCNTR(pipe), cntl);
		3665	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		3666	I915_WRITE(FW_BLC_SELF, fw_bcl_self);
		3667	}
		3668	}
		3669
4104	Serge	3670	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		3671	{
		3672	struct drm_device *dev = crtc->base.dev;
		3673	struct drm_i915_private *dev_priv = dev->dev_private;
		3674	struct intel_crtc_config *pipe_config = &crtc->config;
		3675
		3676	if (!crtc->config.gmch_pfit.control)
		3677	return;
		3678
		3679	/*
		3680	* The panel fitter should only be adjusted whilst the pipe is disabled,
		3681	* according to register description and PRM.
		3682	*/
		3683	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		3684	assert_pipe_disabled(dev_priv, crtc->pipe);
		3685
		3686	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		3687	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		3688
		3689	/* Border color in case we don't scale up to the full screen. Black by
		3690	* default, change to something else for debugging. */
		3691	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		3692	}
		3693
		3694	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		3695	{
		3696	struct drm_device *dev = crtc->dev;
		3697	struct drm_i915_private *dev_priv = dev->dev_private;
		3698	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3699	struct intel_encoder *encoder;
		3700	int pipe = intel_crtc->pipe;
		3701	int plane = intel_crtc->plane;
		3702
		3703	WARN_ON(!crtc->enabled);
		3704
		3705	if (intel_crtc->active)
		3706	return;
		3707
		3708	intel_crtc->active = true;
		3709	intel_update_watermarks(dev);
		3710
		3711	for_each_encoder_on_crtc(dev, crtc, encoder)
		3712	if (encoder->pre_pll_enable)
		3713	encoder->pre_pll_enable(encoder);
		3714
		3715	vlv_enable_pll(intel_crtc);
		3716
		3717	for_each_encoder_on_crtc(dev, crtc, encoder)
		3718	if (encoder->pre_enable)
		3719	encoder->pre_enable(encoder);
		3720
		3721	i9xx_pfit_enable(intel_crtc);
		3722
		3723	intel_crtc_load_lut(crtc);
		3724
		3725	intel_enable_pipe(dev_priv, pipe, false);
		3726	intel_enable_plane(dev_priv, plane, pipe);
		3727	intel_enable_planes(crtc);
		3728	// intel_crtc_update_cursor(crtc, true);
		3729
		3730	intel_update_fbc(dev);
		3731
		3732	for_each_encoder_on_crtc(dev, crtc, encoder)
		3733	encoder->enable(encoder);
		3734	}
		3735
2327	Serge	3736	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3737	{
		3738	struct drm_device *dev = crtc->dev;
		3739	struct drm_i915_private *dev_priv = dev->dev_private;
		3740	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3741	struct intel_encoder *encoder;
2327	Serge	3742	int pipe = intel_crtc->pipe;
		3743	int plane = intel_crtc->plane;
		3744
3031	serge	3745	WARN_ON(!crtc->enabled);
		3746
2327	Serge	3747	if (intel_crtc->active)
		3748	return;
		3749
		3750	intel_crtc->active = true;
		3751	intel_update_watermarks(dev);
		3752
3480	Serge	3753	for_each_encoder_on_crtc(dev, crtc, encoder)
		3754	if (encoder->pre_enable)
		3755	encoder->pre_enable(encoder);
		3756
4104	Serge	3757	i9xx_enable_pll(intel_crtc);
		3758
		3759	i9xx_pfit_enable(intel_crtc);
		3760
		3761	intel_crtc_load_lut(crtc);
		3762
2327	Serge	3763	intel_enable_pipe(dev_priv, pipe, false);
		3764	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3765	intel_enable_planes(crtc);
		3766	/* The fixup needs to happen before cursor is enabled */
3480	Serge	3767	if (IS_G4X(dev))
		3768	g4x_fixup_plane(dev_priv, pipe);
4104	Serge	3769	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3770
		3771	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3772	intel_crtc_dpms_overlay(intel_crtc, true);
3031	serge	3773
4104	Serge	3774	intel_update_fbc(dev);
		3775
3031	serge	3776	for_each_encoder_on_crtc(dev, crtc, encoder)
		3777	encoder->enable(encoder);
2327	Serge	3778	}
		3779
3746	Serge	3780	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		3781	{
		3782	struct drm_device *dev = crtc->base.dev;
		3783	struct drm_i915_private *dev_priv = dev->dev_private;
		3784
4104	Serge	3785	if (!crtc->config.gmch_pfit.control)
		3786	return;
		3787
3746	Serge	3788	assert_pipe_disabled(dev_priv, crtc->pipe);
		3789
4104	Serge	3790	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		3791	I915_READ(PFIT_CONTROL));
3746	Serge	3792	I915_WRITE(PFIT_CONTROL, 0);
		3793	}
		3794
2327	Serge	3795	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3796	{
		3797	struct drm_device *dev = crtc->dev;
		3798	struct drm_i915_private *dev_priv = dev->dev_private;
		3799	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3800	struct intel_encoder *encoder;
2327	Serge	3801	int pipe = intel_crtc->pipe;
		3802	int plane = intel_crtc->plane;
		3803
		3804	if (!intel_crtc->active)
		3805	return;
		3806
3031	serge	3807	for_each_encoder_on_crtc(dev, crtc, encoder)
		3808	encoder->disable(encoder);
		3809
2327	Serge	3810	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3811	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3812	// drm_vblank_off(dev, pipe);
		3813
4104	Serge	3814	if (dev_priv->fbc.plane == plane)
2327	Serge	3815	intel_disable_fbc(dev);
		3816
4104	Serge	3817	intel_crtc_dpms_overlay(intel_crtc, false);
		3818	// intel_crtc_update_cursor(crtc, false);
		3819	intel_disable_planes(crtc);
2327	Serge	3820	intel_disable_plane(dev_priv, plane, pipe);
4104	Serge	3821
2327	Serge	3822	intel_disable_pipe(dev_priv, pipe);
3480	Serge	3823
3746	Serge	3824	i9xx_pfit_disable(intel_crtc);
3480	Serge	3825
4104	Serge	3826	for_each_encoder_on_crtc(dev, crtc, encoder)
		3827	if (encoder->post_disable)
		3828	encoder->post_disable(encoder);
2327	Serge	3829
4104	Serge	3830	i9xx_disable_pll(dev_priv, pipe);
		3831
2327	Serge	3832	intel_crtc->active = false;
		3833	intel_update_fbc(dev);
		3834	intel_update_watermarks(dev);
		3835	}
		3836
3031	serge	3837	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3838	{
		3839	}
		3840
3031	serge	3841	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3842	bool enabled)
2330	Serge	3843	{
		3844	struct drm_device *dev = crtc->dev;
		3845	struct drm_i915_master_private *master_priv;
		3846	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3847	int pipe = intel_crtc->pipe;
2327	Serge	3848
		3849
2340	Serge	3850	#if 0
2330	Serge	3851	if (!dev->primary->master)
		3852	return;
2327	Serge	3853
2330	Serge	3854	master_priv = dev->primary->master->driver_priv;
		3855	if (!master_priv->sarea_priv)
		3856	return;
2327	Serge	3857
2330	Serge	3858	switch (pipe) {
		3859	case 0:
		3860	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3861	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3862	break;
		3863	case 1:
		3864	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3865	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3866	break;
		3867	default:
		3868	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3869	break;
		3870	}
2340	Serge	3871	#endif
		3872
2330	Serge	3873	}
2327	Serge	3874
3031	serge	3875	/**
		3876	* Sets the power management mode of the pipe and plane.
		3877	*/
		3878	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3879	{
		3880	struct drm_device *dev = crtc->dev;
		3881	struct drm_i915_private *dev_priv = dev->dev_private;
		3882	struct intel_encoder *intel_encoder;
		3883	bool enable = false;
		3884
		3885	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3886	enable \|= intel_encoder->connectors_active;
		3887
		3888	if (enable)
		3889	dev_priv->display.crtc_enable(crtc);
		3890	else
		3891	dev_priv->display.crtc_disable(crtc);
		3892
		3893	intel_crtc_update_sarea(crtc, enable);
		3894	}
		3895
2330	Serge	3896	static void intel_crtc_disable(struct drm_crtc *crtc)
		3897	{
		3898	struct drm_device *dev = crtc->dev;
3031	serge	3899	struct drm_connector *connector;
		3900	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3901	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	3902
3031	serge	3903	/* crtc should still be enabled when we disable it. */
		3904	WARN_ON(!crtc->enabled);
2327	Serge	3905
4104	Serge	3906	dev_priv->display.crtc_disable(crtc);
3480	Serge	3907	intel_crtc->eld_vld = false;
3031	serge	3908	intel_crtc_update_sarea(crtc, false);
		3909	dev_priv->display.off(crtc);
		3910
		3911	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3912	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3913
4280	Serge	3914	if (crtc->fb) {
		3915	mutex_lock(&dev->struct_mutex);
		3916	intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3917	mutex_unlock(&dev->struct_mutex);
		3918	crtc->fb = NULL;
		3919	}
3031	serge	3920
		3921	/* Update computed state. */
		3922	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3923	if (!connector->encoder \|\| !connector->encoder->crtc)
		3924	continue;
		3925
		3926	if (connector->encoder->crtc != crtc)
		3927	continue;
		3928
		3929	connector->dpms = DRM_MODE_DPMS_OFF;
		3930	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3931	}
		3932	}
2327	Serge	3933
3031	serge	3934	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3935	{
3031	serge	3936	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3937
		3938	drm_encoder_cleanup(encoder);
		3939	kfree(intel_encoder);
2330	Serge	3940	}
2327	Serge	3941
4104	Serge	3942	/* Simple dpms helper for encoders with just one connector, no cloning and only
3031	serge	3943	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3944	* state of the entire output pipe. */
4104	Serge	3945	static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3946	{
3031	serge	3947	if (mode == DRM_MODE_DPMS_ON) {
		3948	encoder->connectors_active = true;
		3949
		3950	intel_crtc_update_dpms(encoder->base.crtc);
		3951	} else {
		3952	encoder->connectors_active = false;
		3953
		3954	intel_crtc_update_dpms(encoder->base.crtc);
		3955	}
2330	Serge	3956	}
2327	Serge	3957
3031	serge	3958	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3959	* internal consistency). */
		3960	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3961	{
3031	serge	3962	if (connector->get_hw_state(connector)) {
		3963	struct intel_encoder *encoder = connector->encoder;
		3964	struct drm_crtc *crtc;
		3965	bool encoder_enabled;
		3966	enum pipe pipe;
		3967
		3968	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3969	connector->base.base.id,
		3970	drm_get_connector_name(&connector->base));
		3971
		3972	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3973	"wrong connector dpms state\n");
		3974	WARN(connector->base.encoder != &encoder->base,
		3975	"active connector not linked to encoder\n");
		3976	WARN(!encoder->connectors_active,
		3977	"encoder->connectors_active not set\n");
		3978
		3979	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3980	WARN(!encoder_enabled, "encoder not enabled\n");
		3981	if (WARN_ON(!encoder->base.crtc))
		3982	return;
		3983
		3984	crtc = encoder->base.crtc;
		3985
		3986	WARN(!crtc->enabled, "crtc not enabled\n");
		3987	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3988	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3989	"encoder active on the wrong pipe\n");
		3990	}
2330	Serge	3991	}
2327	Serge	3992
3031	serge	3993	/* Even simpler default implementation, if there's really no special case to
		3994	* consider. */
		3995	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	3996	{
3031	serge	3997	/* All the simple cases only support two dpms states. */
		3998	if (mode != DRM_MODE_DPMS_ON)
		3999	mode = DRM_MODE_DPMS_OFF;
2342	Serge	4000
3031	serge	4001	if (mode == connector->dpms)
		4002	return;
		4003
		4004	connector->dpms = mode;
		4005
		4006	/* Only need to change hw state when actually enabled */
4104	Serge	4007	if (connector->encoder)
		4008	intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3031	serge	4009
		4010	intel_modeset_check_state(connector->dev);
2330	Serge	4011	}
2327	Serge	4012
3031	serge	4013	/* Simple connector->get_hw_state implementation for encoders that support only
		4014	* one connector and no cloning and hence the encoder state determines the state
		4015	* of the connector. */
		4016	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	4017	{
3031	serge	4018	enum pipe pipe = 0;
		4019	struct intel_encoder *encoder = connector->encoder;
2330	Serge	4020
3031	serge	4021	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	4022	}
		4023
4104	Serge	4024	static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		4025	struct intel_crtc_config *pipe_config)
		4026	{
		4027	struct drm_i915_private *dev_priv = dev->dev_private;
		4028	struct intel_crtc *pipe_B_crtc =
		4029	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		4030
		4031	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		4032	pipe_name(pipe), pipe_config->fdi_lanes);
		4033	if (pipe_config->fdi_lanes > 4) {
		4034	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		4035	pipe_name(pipe), pipe_config->fdi_lanes);
		4036	return false;
		4037	}
		4038
		4039	if (IS_HASWELL(dev)) {
		4040	if (pipe_config->fdi_lanes > 2) {
		4041	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		4042	pipe_config->fdi_lanes);
		4043	return false;
		4044	} else {
		4045	return true;
		4046	}
		4047	}
		4048
		4049	if (INTEL_INFO(dev)->num_pipes == 2)
		4050	return true;
		4051
		4052	/* Ivybridge 3 pipe is really complicated */
		4053	switch (pipe) {
		4054	case PIPE_A:
		4055	return true;
		4056	case PIPE_B:
		4057	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		4058	pipe_config->fdi_lanes > 2) {
		4059	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4060	pipe_name(pipe), pipe_config->fdi_lanes);
		4061	return false;
		4062	}
		4063	return true;
		4064	case PIPE_C:
		4065	if (!pipe_has_enabled_pch(pipe_B_crtc) \|\|
		4066	pipe_B_crtc->config.fdi_lanes <= 2) {
		4067	if (pipe_config->fdi_lanes > 2) {
		4068	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4069	pipe_name(pipe), pipe_config->fdi_lanes);
		4070	return false;
		4071	}
		4072	} else {
		4073	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		4074	return false;
		4075	}
		4076	return true;
		4077	default:
		4078	BUG();
		4079	}
		4080	}
		4081
		4082	#define RETRY 1
		4083	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3746	Serge	4084	struct intel_crtc_config *pipe_config)
2330	Serge	4085	{
4104	Serge	4086	struct drm_device *dev = intel_crtc->base.dev;
3746	Serge	4087	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104	Serge	4088	int lane, link_bw, fdi_dotclock;
		4089	bool setup_ok, needs_recompute = false;
2330	Serge	4090
4104	Serge	4091	retry:
		4092	/* FDI is a binary signal running at ~2.7GHz, encoding
		4093	* each output octet as 10 bits. The actual frequency
		4094	* is stored as a divider into a 100MHz clock, and the
		4095	* mode pixel clock is stored in units of 1KHz.
		4096	* Hence the bw of each lane in terms of the mode signal
		4097	* is:
		4098	*/
		4099	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4100
		4101	fdi_dotclock = adjusted_mode->clock;
		4102	fdi_dotclock /= pipe_config->pixel_multiplier;
		4103
		4104	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		4105	pipe_config->pipe_bpp);
		4106
		4107	pipe_config->fdi_lanes = lane;
		4108
		4109	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		4110	link_bw, &pipe_config->fdi_m_n);
		4111
		4112	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		4113	intel_crtc->pipe, pipe_config);
		4114	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		4115	pipe_config->pipe_bpp -= 2*3;
		4116	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		4117	pipe_config->pipe_bpp);
		4118	needs_recompute = true;
		4119	pipe_config->bw_constrained = true;
		4120
		4121	goto retry;
		4122	}
		4123
		4124	if (needs_recompute)
		4125	return RETRY;
		4126
		4127	return setup_ok ? 0 : -EINVAL;
		4128	}
		4129
		4130	static void hsw_compute_ips_config(struct intel_crtc *crtc,
		4131	struct intel_crtc_config *pipe_config)
		4132	{
		4133	pipe_config->ips_enabled = i915_enable_ips &&
		4134	hsw_crtc_supports_ips(crtc) &&
		4135	pipe_config->pipe_bpp <= 24;
		4136	}
		4137
		4138	static int intel_crtc_compute_config(struct intel_crtc *crtc,
		4139	struct intel_crtc_config *pipe_config)
		4140	{
		4141	struct drm_device *dev = crtc->base.dev;
		4142	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		4143
2330	Serge	4144	if (HAS_PCH_SPLIT(dev)) {
		4145	/* FDI link clock is fixed at 2.7G */
3746	Serge	4146	if (pipe_config->requested_mode.clock * 3
		4147	> IRONLAKE_FDI_FREQ * 4)
4104	Serge	4148	return -EINVAL;
2330	Serge	4149	}
		4150
4104	Serge	4151	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		4152	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	4153	*/
		4154	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		4155	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104	Serge	4156	return -EINVAL;
3031	serge	4157
3746	Serge	4158	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		4159	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		4160	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		4161	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		4162	* for lvds. */
		4163	pipe_config->pipe_bpp = 8*3;
		4164	}
		4165
4104	Serge	4166	if (HAS_IPS(dev))
		4167	hsw_compute_ips_config(crtc, pipe_config);
		4168
		4169	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
		4170	* clock survives for now. */
		4171	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		4172	pipe_config->shared_dpll = crtc->config.shared_dpll;
		4173
		4174	if (pipe_config->has_pch_encoder)
		4175	return ironlake_fdi_compute_config(crtc, pipe_config);
		4176
		4177	return 0;
2330	Serge	4178	}
		4179
3031	serge	4180	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		4181	{
		4182	return 400000; /* FIXME */
		4183	}
		4184
2327	Serge	4185	static int i945_get_display_clock_speed(struct drm_device *dev)
		4186	{
		4187	return 400000;
		4188	}
		4189
		4190	static int i915_get_display_clock_speed(struct drm_device *dev)
		4191	{
		4192	return 333000;
		4193	}
		4194
		4195	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		4196	{
		4197	return 200000;
		4198	}
		4199
4104	Serge	4200	static int pnv_get_display_clock_speed(struct drm_device *dev)
		4201	{
		4202	u16 gcfgc = 0;
		4203
		4204	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4205
		4206	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4207	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		4208	return 267000;
		4209	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		4210	return 333000;
		4211	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		4212	return 444000;
		4213	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		4214	return 200000;
		4215	default:
		4216	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		4217	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		4218	return 133000;
		4219	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		4220	return 167000;
		4221	}
		4222	}
		4223
2327	Serge	4224	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		4225	{
		4226	u16 gcfgc = 0;
		4227
		4228	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4229
		4230	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		4231	return 133000;
		4232	else {
		4233	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4234	case GC_DISPLAY_CLOCK_333_MHZ:
		4235	return 333000;
		4236	default:
		4237	case GC_DISPLAY_CLOCK_190_200_MHZ:
		4238	return 190000;
		4239	}
		4240	}
		4241	}
		4242
		4243	static int i865_get_display_clock_speed(struct drm_device *dev)
		4244	{
		4245	return 266000;
		4246	}
		4247
		4248	static int i855_get_display_clock_speed(struct drm_device *dev)
		4249	{
		4250	u16 hpllcc = 0;
		4251	/* Assume that the hardware is in the high speed state. This
		4252	* should be the default.
		4253	*/
		4254	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		4255	case GC_CLOCK_133_200:
		4256	case GC_CLOCK_100_200:
		4257	return 200000;
		4258	case GC_CLOCK_166_250:
		4259	return 250000;
		4260	case GC_CLOCK_100_133:
		4261	return 133000;
		4262	}
		4263
		4264	/* Shouldn't happen */
		4265	return 0;
		4266	}
		4267
		4268	static int i830_get_display_clock_speed(struct drm_device *dev)
		4269	{
		4270	return 133000;
		4271	}
		4272
		4273	static void
3746	Serge	4274	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	4275	{
3746	Serge	4276	while (*num > DATA_LINK_M_N_MASK \|\|
		4277	*den > DATA_LINK_M_N_MASK) {
2327	Serge	4278	*num >>= 1;
		4279	*den >>= 1;
		4280	}
		4281	}
		4282
3746	Serge	4283	static void compute_m_n(unsigned int m, unsigned int n,
		4284	uint32_t ret_m, uint32_t ret_n)
		4285	{
		4286	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		4287	ret_m = div_u64((uint64_t) m *ret_n, n);
		4288	intel_reduce_m_n_ratio(ret_m, ret_n);
		4289	}
		4290
3480	Serge	4291	void
		4292	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		4293	int pixel_clock, int link_clock,
		4294	struct intel_link_m_n *m_n)
2327	Serge	4295	{
3480	Serge	4296	m_n->tu = 64;
3746	Serge	4297
		4298	compute_m_n(bits_per_pixel * pixel_clock,
		4299	link_clock * nlanes * 8,
		4300	&m_n->gmch_m, &m_n->gmch_n);
		4301
		4302	compute_m_n(pixel_clock, link_clock,
		4303	&m_n->link_m, &m_n->link_n);
2327	Serge	4304	}
		4305
		4306	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4307	{
2342	Serge	4308	if (i915_panel_use_ssc >= 0)
		4309	return i915_panel_use_ssc != 0;
4104	Serge	4310	return dev_priv->vbt.lvds_use_ssc
2327	Serge	4311	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4312	}
		4313
3031	serge	4314	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	4315	{
3031	serge	4316	struct drm_device *dev = crtc->dev;
		4317	struct drm_i915_private *dev_priv = dev->dev_private;
		4318	int refclk = 27000; /* for DP & HDMI */
2327	Serge	4319
3031	serge	4320	return 100000; /* only one validated so far */
2327	Serge	4321
3031	serge	4322	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		4323	refclk = 96000;
		4324	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4325	if (intel_panel_use_ssc(dev_priv))
		4326	refclk = 100000;
		4327	else
		4328	refclk = 96000;
		4329	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		4330	refclk = 100000;
		4331	}
2327	Serge	4332
3031	serge	4333	return refclk;
		4334	}
2327	Serge	4335
3031	serge	4336	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		4337	{
		4338	struct drm_device *dev = crtc->dev;
		4339	struct drm_i915_private *dev_priv = dev->dev_private;
		4340	int refclk;
2327	Serge	4341
3031	serge	4342	if (IS_VALLEYVIEW(dev)) {
		4343	refclk = vlv_get_refclk(crtc);
		4344	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4345	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4104	Serge	4346	refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
3031	serge	4347	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4348	refclk / 1000);
		4349	} else if (!IS_GEN2(dev)) {
		4350	refclk = 96000;
		4351	} else {
		4352	refclk = 48000;
		4353	}
2327	Serge	4354
3031	serge	4355	return refclk;
		4356	}
2327	Serge	4357
4104	Serge	4358	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	4359	{
4104	Serge	4360	return (1 << dpll->n) << 16 \| dpll->m2;
		4361	}
3746	Serge	4362
4104	Serge	4363	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		4364	{
		4365	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	4366	}
2327	Serge	4367
3746	Serge	4368	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	4369	intel_clock_t *reduced_clock)
		4370	{
3746	Serge	4371	struct drm_device *dev = crtc->base.dev;
3031	serge	4372	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4373	int pipe = crtc->pipe;
3031	serge	4374	u32 fp, fp2 = 0;
2327	Serge	4375
3031	serge	4376	if (IS_PINEVIEW(dev)) {
4104	Serge	4377	fp = pnv_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4378	if (reduced_clock)
4104	Serge	4379	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	4380	} else {
4104	Serge	4381	fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4382	if (reduced_clock)
4104	Serge	4383	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	4384	}
2327	Serge	4385
3031	serge	4386	I915_WRITE(FP0(pipe), fp);
4104	Serge	4387	crtc->config.dpll_hw_state.fp0 = fp;
2327	Serge	4388
3746	Serge	4389	crtc->lowfreq_avail = false;
		4390	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4391	reduced_clock && i915_powersave) {
		4392	I915_WRITE(FP1(pipe), fp2);
4104	Serge	4393	crtc->config.dpll_hw_state.fp1 = fp2;
3746	Serge	4394	crtc->lowfreq_avail = true;
3031	serge	4395	} else {
		4396	I915_WRITE(FP1(pipe), fp);
4104	Serge	4397	crtc->config.dpll_hw_state.fp1 = fp;
3031	serge	4398	}
		4399	}
2327	Serge	4400
4104	Serge	4401	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
		4402	{
		4403	u32 reg_val;
		4404
		4405	/*
		4406	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		4407	* and set it to a reasonable value instead.
		4408	*/
		4409	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4410	reg_val &= 0xffffff00;
		4411	reg_val \|= 0x00000030;
		4412	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4413
		4414	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4415	reg_val &= 0x8cffffff;
		4416	reg_val = 0x8c000000;
		4417	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4418
		4419	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4420	reg_val &= 0xffffff00;
		4421	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4422
		4423	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4424	reg_val &= 0x00ffffff;
		4425	reg_val \|= 0xb0000000;
		4426	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4427	}
		4428
		4429	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		4430	struct intel_link_m_n *m_n)
		4431	{
		4432	struct drm_device *dev = crtc->base.dev;
		4433	struct drm_i915_private *dev_priv = dev->dev_private;
		4434	int pipe = crtc->pipe;
		4435
		4436	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4437	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		4438	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		4439	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		4440	}
		4441
		4442	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		4443	struct intel_link_m_n *m_n)
		4444	{
		4445	struct drm_device *dev = crtc->base.dev;
		4446	struct drm_i915_private *dev_priv = dev->dev_private;
		4447	int pipe = crtc->pipe;
		4448	enum transcoder transcoder = crtc->config.cpu_transcoder;
		4449
		4450	if (INTEL_INFO(dev)->gen >= 5) {
		4451	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4452	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		4453	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		4454	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		4455	} else {
		4456	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4457	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		4458	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		4459	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		4460	}
		4461	}
		4462
3746	Serge	4463	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	4464	{
3746	Serge	4465	if (crtc->config.has_pch_encoder)
		4466	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4467	else
		4468	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4469	}
		4470
		4471	static void vlv_update_pll(struct intel_crtc *crtc)
		4472	{
		4473	struct drm_device *dev = crtc->base.dev;
3031	serge	4474	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4475	int pipe = crtc->pipe;
4104	Serge	4476	u32 dpll, mdiv;
3031	serge	4477	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4104	Serge	4478	u32 coreclk, reg_val, dpll_md;
2327	Serge	4479
3480	Serge	4480	mutex_lock(&dev_priv->dpio_lock);
		4481
3746	Serge	4482	bestn = crtc->config.dpll.n;
		4483	bestm1 = crtc->config.dpll.m1;
		4484	bestm2 = crtc->config.dpll.m2;
		4485	bestp1 = crtc->config.dpll.p1;
		4486	bestp2 = crtc->config.dpll.p2;
3031	serge	4487
4104	Serge	4488	/* See eDP HDMI DPIO driver vbios notes doc */
		4489
		4490	/* PLL B needs special handling */
		4491	if (pipe)
		4492	vlv_pllb_recal_opamp(dev_priv);
		4493
		4494	/* Set up Tx target for periodic Rcomp update */
		4495	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
		4496
		4497	/* Disable target IRef on PLL */
		4498	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
		4499	reg_val &= 0x00ffffff;
		4500	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
		4501
		4502	/* Disable fast lock */
		4503	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
		4504
		4505	/* Set idtafcrecal before PLL is enabled */
3031	serge	4506	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4507	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4508	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4509	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	4510
		4511	/*
		4512	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		4513	* but we don't support that).
		4514	* Note: don't use the DAC post divider as it seems unstable.
		4515	*/
		4516	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
		4517	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4518
3031	serge	4519	mdiv \|= DPIO_ENABLE_CALIBRATION;
4104	Serge	4520	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
3031	serge	4521
4104	Serge	4522	/* Set HBR and RBR LPF coefficients */
		4523	if (crtc->config.port_clock == 162000 \|\|
		4524	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) \|\|
		4525	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
		4526	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4527	0x009f0003);
		4528	else
		4529	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4530	0x00d0000f);
3031	serge	4531
4104	Serge	4532	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) \|\|
		4533	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		4534	/* Use SSC source */
		4535	if (!pipe)
		4536	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4537	0x0df40000);
		4538	else
		4539	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4540	0x0df70000);
		4541	} else { /* HDMI or VGA */
		4542	/* Use bend source */
		4543	if (!pipe)
		4544	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4545	0x0df70000);
		4546	else
		4547	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4548	0x0df40000);
		4549	}
3031	serge	4550
4104	Serge	4551	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
		4552	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
		4553	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) \|\|
		4554	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		4555	coreclk \|= 0x01000000;
		4556	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
3031	serge	4557
4104	Serge	4558	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
		4559
		4560	/* Enable DPIO clock input */
		4561	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4562	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		4563	if (pipe)
		4564	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		4565
3031	serge	4566	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4567	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4568
4104	Serge	4569	dpll_md = (crtc->config.pixel_multiplier - 1)
		4570	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4571	crtc->config.dpll_hw_state.dpll_md = dpll_md;
3031	serge	4572
3746	Serge	4573	if (crtc->config.has_dp_encoder)
		4574	intel_dp_set_m_n(crtc);
3243	Serge	4575
3480	Serge	4576	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	4577	}
		4578
3746	Serge	4579	static void i9xx_update_pll(struct intel_crtc *crtc,
		4580	intel_clock_t *reduced_clock,
3031	serge	4581	int num_connectors)
		4582	{
3746	Serge	4583	struct drm_device *dev = crtc->base.dev;
3031	serge	4584	struct drm_i915_private *dev_priv = dev->dev_private;
		4585	u32 dpll;
		4586	bool is_sdvo;
3746	Serge	4587	struct dpll *clock = &crtc->config.dpll;
3031	serge	4588
3746	Serge	4589	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4590
3746	Serge	4591	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4592	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	4593
		4594	dpll = DPLL_VGA_MODE_DIS;
		4595
3746	Serge	4596	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	4597	dpll \|= DPLLB_MODE_LVDS;
		4598	else
		4599	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	4600
4104	Serge	4601	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
3746	Serge	4602	dpll \|= (crtc->config.pixel_multiplier - 1)
		4603	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4604	}
4104	Serge	4605
		4606	if (is_sdvo)
		4607	dpll \|= DPLL_SDVO_HIGH_SPEED;
		4608
3746	Serge	4609	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4104	Serge	4610	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	4611
3031	serge	4612	/* compute bitmask from p1 value */
		4613	if (IS_PINEVIEW(dev))
		4614	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4615	else {
		4616	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4617	if (IS_G4X(dev) && reduced_clock)
		4618	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4619	}
		4620	switch (clock->p2) {
		4621	case 5:
		4622	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4623	break;
		4624	case 7:
		4625	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4626	break;
		4627	case 10:
		4628	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4629	break;
		4630	case 14:
		4631	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4632	break;
		4633	}
		4634	if (INTEL_INFO(dev)->gen >= 4)
		4635	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4636
4104	Serge	4637	if (crtc->config.sdvo_tv_clock)
3031	serge	4638	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	4639	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4640	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4641	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4642	else
		4643	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4644
3031	serge	4645	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4646	crtc->config.dpll_hw_state.dpll = dpll;
2327	Serge	4647
4104	Serge	4648	if (INTEL_INFO(dev)->gen >= 4) {
		4649	u32 dpll_md = (crtc->config.pixel_multiplier - 1)
		4650	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4651	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		4652	}
2327	Serge	4653
3746	Serge	4654	if (crtc->config.has_dp_encoder)
		4655	intel_dp_set_m_n(crtc);
3031	serge	4656	}
2327	Serge	4657
3746	Serge	4658	static void i8xx_update_pll(struct intel_crtc *crtc,
		4659	intel_clock_t *reduced_clock,
3031	serge	4660	int num_connectors)
		4661	{
3746	Serge	4662	struct drm_device *dev = crtc->base.dev;
3031	serge	4663	struct drm_i915_private *dev_priv = dev->dev_private;
		4664	u32 dpll;
3746	Serge	4665	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4666
3746	Serge	4667	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4668
3031	serge	4669	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4670
3746	Serge	4671	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	4672	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4673	} else {
		4674	if (clock->p1 == 2)
		4675	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4676	else
		4677	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4678	if (clock->p2 == 4)
		4679	dpll \|= PLL_P2_DIVIDE_BY_4;
		4680	}
2327	Serge	4681
4104	Serge	4682	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		4683	dpll \|= DPLL_DVO_2X_MODE;
		4684
3746	Serge	4685	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4686	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4687	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4688	else
		4689	dpll \|= PLL_REF_INPUT_DREFCLK;
		4690
		4691	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4692	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4693	}
		4694
4104	Serge	4695	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	4696	{
		4697	struct drm_device *dev = intel_crtc->base.dev;
		4698	struct drm_i915_private *dev_priv = dev->dev_private;
		4699	enum pipe pipe = intel_crtc->pipe;
3746	Serge	4700	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4104	Serge	4701	struct drm_display_mode *adjusted_mode =
		4702	&intel_crtc->config.adjusted_mode;
		4703	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
		4704	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
3243	Serge	4705
4104	Serge	4706	/* We need to be careful not to changed the adjusted mode, for otherwise
		4707	* the hw state checker will get angry at the mismatch. */
		4708	crtc_vtotal = adjusted_mode->crtc_vtotal;
		4709	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		4710
3243	Serge	4711	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4712	/* the chip adds 2 halflines automatically */
4104	Serge	4713	crtc_vtotal -= 1;
		4714	crtc_vblank_end -= 1;
3243	Serge	4715	vsyncshift = adjusted_mode->crtc_hsync_start
		4716	- adjusted_mode->crtc_htotal / 2;
		4717	} else {
		4718	vsyncshift = 0;
		4719	}
		4720
		4721	if (INTEL_INFO(dev)->gen > 3)
		4722	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		4723
		4724	I915_WRITE(HTOTAL(cpu_transcoder),
		4725	(adjusted_mode->crtc_hdisplay - 1) \|
		4726	((adjusted_mode->crtc_htotal - 1) << 16));
		4727	I915_WRITE(HBLANK(cpu_transcoder),
		4728	(adjusted_mode->crtc_hblank_start - 1) \|
		4729	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4730	I915_WRITE(HSYNC(cpu_transcoder),
		4731	(adjusted_mode->crtc_hsync_start - 1) \|
		4732	((adjusted_mode->crtc_hsync_end - 1) << 16));
		4733
		4734	I915_WRITE(VTOTAL(cpu_transcoder),
		4735	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	4736	((crtc_vtotal - 1) << 16));
3243	Serge	4737	I915_WRITE(VBLANK(cpu_transcoder),
		4738	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	4739	((crtc_vblank_end - 1) << 16));
3243	Serge	4740	I915_WRITE(VSYNC(cpu_transcoder),
		4741	(adjusted_mode->crtc_vsync_start - 1) \|
		4742	((adjusted_mode->crtc_vsync_end - 1) << 16));
		4743
		4744	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		4745	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		4746	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		4747	* bits. */
		4748	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		4749	(pipe == PIPE_B \|\| pipe == PIPE_C))
		4750	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		4751
		4752	/* pipesrc controls the size that is scaled from, which should
		4753	* always be the user's requested size.
		4754	*/
		4755	I915_WRITE(PIPESRC(pipe),
		4756	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		4757	}
		4758
4104	Serge	4759	static void intel_get_pipe_timings(struct intel_crtc *crtc,
		4760	struct intel_crtc_config *pipe_config)
		4761	{
		4762	struct drm_device *dev = crtc->base.dev;
		4763	struct drm_i915_private *dev_priv = dev->dev_private;
		4764	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		4765	uint32_t tmp;
		4766
		4767	tmp = I915_READ(HTOTAL(cpu_transcoder));
		4768	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		4769	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
		4770	tmp = I915_READ(HBLANK(cpu_transcoder));
		4771	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		4772	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
		4773	tmp = I915_READ(HSYNC(cpu_transcoder));
		4774	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		4775	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
		4776
		4777	tmp = I915_READ(VTOTAL(cpu_transcoder));
		4778	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		4779	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
		4780	tmp = I915_READ(VBLANK(cpu_transcoder));
		4781	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		4782	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
		4783	tmp = I915_READ(VSYNC(cpu_transcoder));
		4784	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		4785	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
		4786
		4787	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		4788	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		4789	pipe_config->adjusted_mode.crtc_vtotal += 1;
		4790	pipe_config->adjusted_mode.crtc_vblank_end += 1;
		4791	}
		4792
		4793	tmp = I915_READ(PIPESRC(crtc->pipe));
		4794	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
		4795	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
		4796	}
		4797
		4798	static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
		4799	struct intel_crtc_config *pipe_config)
		4800	{
		4801	struct drm_crtc *crtc = &intel_crtc->base;
		4802
		4803	crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
		4804	crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
		4805	crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
		4806	crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
		4807
		4808	crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
		4809	crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
		4810	crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
		4811	crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
		4812
		4813	crtc->mode.flags = pipe_config->adjusted_mode.flags;
		4814
		4815	crtc->mode.clock = pipe_config->adjusted_mode.clock;
		4816	crtc->mode.flags \|= pipe_config->adjusted_mode.flags;
		4817	}
		4818
3746	Serge	4819	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		4820	{
		4821	struct drm_device *dev = intel_crtc->base.dev;
		4822	struct drm_i915_private *dev_priv = dev->dev_private;
		4823	uint32_t pipeconf;
		4824
4104	Serge	4825	pipeconf = 0;
3746	Serge	4826
4104	Serge	4827	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		4828	I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
		4829	pipeconf \|= PIPECONF_ENABLE;
		4830
3746	Serge	4831	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4832	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4833	* core speed.
		4834	*
		4835	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4836	* pipe == 0 check?
		4837	*/
		4838	if (intel_crtc->config.requested_mode.clock >
		4839	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4840	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4841	}
		4842
4104	Serge	4843	/* only g4x and later have fancy bpc/dither controls */
		4844	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		4845	/* Bspec claims that we can't use dithering for 30bpp pipes. */
		4846	if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
		4847	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	4848	PIPECONF_DITHER_TYPE_SP;
		4849
4104	Serge	4850	switch (intel_crtc->config.pipe_bpp) {
		4851	case 18:
		4852	pipeconf \|= PIPECONF_6BPC;
		4853	break;
		4854	case 24:
		4855	pipeconf \|= PIPECONF_8BPC;
		4856	break;
		4857	case 30:
		4858	pipeconf \|= PIPECONF_10BPC;
		4859	break;
		4860	default:
		4861	/* Case prevented by intel_choose_pipe_bpp_dither. */
		4862	BUG();
3746	Serge	4863	}
		4864	}
		4865
		4866	if (HAS_PIPE_CXSR(dev)) {
		4867	if (intel_crtc->lowfreq_avail) {
		4868	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4869	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4870	} else {
		4871	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4872	}
		4873	}
		4874
		4875	if (!IS_GEN2(dev) &&
		4876	intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		4877	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4878	else
		4879	pipeconf \|= PIPECONF_PROGRESSIVE;
		4880
4104	Serge	4881	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
3746	Serge	4882	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		4883
		4884	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		4885	POSTING_READ(PIPECONF(intel_crtc->pipe));
		4886	}
		4887
3031	serge	4888	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4889	int x, int y,
		4890	struct drm_framebuffer *fb)
		4891	{
		4892	struct drm_device *dev = crtc->dev;
		4893	struct drm_i915_private *dev_priv = dev->dev_private;
		4894	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	4895	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3031	serge	4896	int pipe = intel_crtc->pipe;
		4897	int plane = intel_crtc->plane;
		4898	int refclk, num_connectors = 0;
		4899	intel_clock_t clock, reduced_clock;
3746	Serge	4900	u32 dspcntr;
4104	Serge	4901	bool ok, has_reduced_clock = false;
		4902	bool is_lvds = false;
3031	serge	4903	struct intel_encoder *encoder;
		4904	const intel_limit_t *limit;
		4905	int ret;
		4906
		4907	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4908	switch (encoder->type) {
		4909	case INTEL_OUTPUT_LVDS:
		4910	is_lvds = true;
		4911	break;
		4912	}
		4913
		4914	num_connectors++;
		4915	}
		4916
		4917	refclk = i9xx_get_refclk(crtc, num_connectors);
		4918
		4919	/*
		4920	* Returns a set of divisors for the desired target clock with the given
		4921	* refclk, or FALSE. The returned values represent the clock equation:
		4922	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4923	*/
		4924	limit = intel_limit(crtc, refclk);
4104	Serge	4925	ok = dev_priv->display.find_dpll(limit, crtc,
		4926	intel_crtc->config.port_clock,
		4927	refclk, NULL, &clock);
		4928	if (!ok && !intel_crtc->config.clock_set) {
3031	serge	4929	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4930	return -EINVAL;
		4931	}
		4932
		4933	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4934	/*
		4935	* Ensure we match the reduced clock's P to the target clock.
		4936	* If the clocks don't match, we can't switch the display clock
		4937	* by using the FP0/FP1. In such case we will disable the LVDS
		4938	* downclock feature.
		4939	*/
4104	Serge	4940	has_reduced_clock =
		4941	dev_priv->display.find_dpll(limit, crtc,
3031	serge	4942	dev_priv->lvds_downclock,
4104	Serge	4943	refclk, &clock,
3031	serge	4944	&reduced_clock);
		4945	}
3746	Serge	4946	/* Compat-code for transition, will disappear. */
		4947	if (!intel_crtc->config.clock_set) {
		4948	intel_crtc->config.dpll.n = clock.n;
		4949	intel_crtc->config.dpll.m1 = clock.m1;
		4950	intel_crtc->config.dpll.m2 = clock.m2;
		4951	intel_crtc->config.dpll.p1 = clock.p1;
		4952	intel_crtc->config.dpll.p2 = clock.p2;
		4953	}
3031	serge	4954
		4955	if (IS_GEN2(dev))
4104	Serge	4956	i8xx_update_pll(intel_crtc,
3243	Serge	4957	has_reduced_clock ? &reduced_clock : NULL,
		4958	num_connectors);
3031	serge	4959	else if (IS_VALLEYVIEW(dev))
3746	Serge	4960	vlv_update_pll(intel_crtc);
3031	serge	4961	else
3746	Serge	4962	i9xx_update_pll(intel_crtc,
3031	serge	4963	has_reduced_clock ? &reduced_clock : NULL,
		4964	num_connectors);
		4965
		4966	/* Set up the display plane register */
		4967	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4968
3746	Serge	4969	if (!IS_VALLEYVIEW(dev)) {
3031	serge	4970	if (pipe == 0)
		4971	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4972	else
		4973	dspcntr \|= DISPPLANE_SEL_PIPE_B;
3243	Serge	4974	}
		4975
4104	Serge	4976	intel_set_pipe_timings(intel_crtc);
3031	serge	4977
		4978	/* pipesrc and dspsize control the size that is scaled from,
		4979	* which should always be the user's requested size.
		4980	*/
		4981	I915_WRITE(DSPSIZE(plane),
		4982	((mode->vdisplay - 1) << 16) \|
		4983	(mode->hdisplay - 1));
		4984	I915_WRITE(DSPPOS(plane), 0);
2327	Serge	4985
3746	Serge	4986	i9xx_set_pipeconf(intel_crtc);
		4987
3031	serge	4988	I915_WRITE(DSPCNTR(plane), dspcntr);
		4989	POSTING_READ(DSPCNTR(plane));
2327	Serge	4990
3031	serge	4991	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4992
3031	serge	4993	intel_update_watermarks(dev);
		4994
2327	Serge	4995	return ret;
		4996	}
		4997
4104	Serge	4998	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
		4999	struct intel_crtc_config *pipe_config)
		5000	{
		5001	struct drm_device *dev = crtc->base.dev;
		5002	struct drm_i915_private *dev_priv = dev->dev_private;
		5003	uint32_t tmp;
		5004
		5005	tmp = I915_READ(PFIT_CONTROL);
		5006	if (!(tmp & PFIT_ENABLE))
		5007	return;
		5008
		5009	/* Check whether the pfit is attached to our pipe. */
		5010	if (INTEL_INFO(dev)->gen < 4) {
		5011	if (crtc->pipe != PIPE_B)
		5012	return;
		5013	} else {
		5014	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		5015	return;
		5016	}
		5017
		5018	pipe_config->gmch_pfit.control = tmp;
		5019	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		5020	if (INTEL_INFO(dev)->gen < 5)
		5021	pipe_config->gmch_pfit.lvds_border_bits =
		5022	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		5023	}
		5024
3746	Serge	5025	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		5026	struct intel_crtc_config *pipe_config)
		5027	{
		5028	struct drm_device *dev = crtc->base.dev;
		5029	struct drm_i915_private *dev_priv = dev->dev_private;
		5030	uint32_t tmp;
		5031
4104	Serge	5032	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5033	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5034
3746	Serge	5035	tmp = I915_READ(PIPECONF(crtc->pipe));
		5036	if (!(tmp & PIPECONF_ENABLE))
		5037	return false;
		5038
4280	Serge	5039	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		5040	switch (tmp & PIPECONF_BPC_MASK) {
		5041	case PIPECONF_6BPC:
		5042	pipe_config->pipe_bpp = 18;
		5043	break;
		5044	case PIPECONF_8BPC:
		5045	pipe_config->pipe_bpp = 24;
		5046	break;
		5047	case PIPECONF_10BPC:
		5048	pipe_config->pipe_bpp = 30;
		5049	break;
		5050	default:
		5051	break;
		5052	}
		5053	}
		5054
4104	Serge	5055	intel_get_pipe_timings(crtc, pipe_config);
		5056
		5057	i9xx_get_pfit_config(crtc, pipe_config);
		5058
		5059	if (INTEL_INFO(dev)->gen >= 4) {
		5060	tmp = I915_READ(DPLL_MD(crtc->pipe));
		5061	pipe_config->pixel_multiplier =
		5062	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		5063	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		5064	pipe_config->dpll_hw_state.dpll_md = tmp;
		5065	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		5066	tmp = I915_READ(DPLL(crtc->pipe));
		5067	pipe_config->pixel_multiplier =
		5068	((tmp & SDVO_MULTIPLIER_MASK)
		5069	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		5070	} else {
		5071	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		5072	* port and will be fixed up in the encoder->get_config
		5073	* function. */
		5074	pipe_config->pixel_multiplier = 1;
		5075	}
		5076	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		5077	if (!IS_VALLEYVIEW(dev)) {
		5078	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		5079	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		5080	} else {
		5081	/* Mask out read-only status bits. */
		5082	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		5083	DPLL_PORTC_READY_MASK \|
		5084	DPLL_PORTB_READY_MASK);
		5085	}
		5086
3746	Serge	5087	return true;
		5088	}
		5089
3243	Serge	5090	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	5091	{
		5092	struct drm_i915_private *dev_priv = dev->dev_private;
		5093	struct drm_mode_config *mode_config = &dev->mode_config;
		5094	struct intel_encoder *encoder;
3746	Serge	5095	u32 val, final;
2327	Serge	5096	bool has_lvds = false;
2342	Serge	5097	bool has_cpu_edp = false;
		5098	bool has_panel = false;
		5099	bool has_ck505 = false;
		5100	bool can_ssc = false;
2327	Serge	5101
		5102	/* We need to take the global config into account */
		5103	list_for_each_entry(encoder, &mode_config->encoder_list,
		5104	base.head) {
		5105	switch (encoder->type) {
		5106	case INTEL_OUTPUT_LVDS:
2342	Serge	5107	has_panel = true;
2327	Serge	5108	has_lvds = true;
2342	Serge	5109	break;
2327	Serge	5110	case INTEL_OUTPUT_EDP:
2342	Serge	5111	has_panel = true;
4104	Serge	5112	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	5113	has_cpu_edp = true;
2327	Serge	5114	break;
		5115	}
		5116	}
2342	Serge	5117
		5118	if (HAS_PCH_IBX(dev)) {
4104	Serge	5119	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	5120	can_ssc = has_ck505;
		5121	} else {
		5122	has_ck505 = false;
		5123	can_ssc = true;
2327	Serge	5124	}
		5125
4104	Serge	5126	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		5127	has_panel, has_lvds, has_ck505);
2342	Serge	5128
2327	Serge	5129	/* Ironlake: try to setup display ref clock before DPLL
		5130	* enabling. This is only under driver's control after
		5131	* PCH B stepping, previous chipset stepping should be
		5132	* ignoring this setting.
		5133	*/
3746	Serge	5134	val = I915_READ(PCH_DREF_CONTROL);
		5135
		5136	/* As we must carefully and slowly disable/enable each source in turn,
		5137	* compute the final state we want first and check if we need to
		5138	* make any changes at all.
		5139	*/
		5140	final = val;
		5141	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		5142	if (has_ck505)
		5143	final \|= DREF_NONSPREAD_CK505_ENABLE;
		5144	else
		5145	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5146
		5147	final &= ~DREF_SSC_SOURCE_MASK;
		5148	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5149	final &= ~DREF_SSC1_ENABLE;
		5150
		5151	if (has_panel) {
		5152	final \|= DREF_SSC_SOURCE_ENABLE;
		5153
		5154	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5155	final \|= DREF_SSC1_ENABLE;
		5156
		5157	if (has_cpu_edp) {
		5158	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5159	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5160	else
		5161	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5162	} else
		5163	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5164	} else {
		5165	final \|= DREF_SSC_SOURCE_DISABLE;
		5166	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5167	}
		5168
		5169	if (final == val)
		5170	return;
		5171
2327	Serge	5172	/* Always enable nonspread source */
3746	Serge	5173	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	5174
		5175	if (has_ck505)
3746	Serge	5176	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	5177	else
3746	Serge	5178	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	5179
		5180	if (has_panel) {
3746	Serge	5181	val &= ~DREF_SSC_SOURCE_MASK;
		5182	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	5183
2342	Serge	5184	/* SSC must be turned on before enabling the CPU output */
		5185	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5186	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	5187	val \|= DREF_SSC1_ENABLE;
3031	serge	5188	} else
3746	Serge	5189	val &= ~DREF_SSC1_ENABLE;
2327	Serge	5190
2342	Serge	5191	/* Get SSC going before enabling the outputs */
3746	Serge	5192	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5193	POSTING_READ(PCH_DREF_CONTROL);
		5194	udelay(200);
2342	Serge	5195
3746	Serge	5196	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	5197
		5198	/* Enable CPU source on CPU attached eDP */
2342	Serge	5199	if (has_cpu_edp) {
		5200	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5201	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	5202	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	5203	}
2327	Serge	5204	else
3746	Serge	5205	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	5206	} else
3746	Serge	5207	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5208
3746	Serge	5209	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5210	POSTING_READ(PCH_DREF_CONTROL);
		5211	udelay(200);
2327	Serge	5212	} else {
2342	Serge	5213	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		5214
3746	Serge	5215	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	5216
		5217	/* Turn off CPU output */
3746	Serge	5218	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5219
3746	Serge	5220	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5221	POSTING_READ(PCH_DREF_CONTROL);
		5222	udelay(200);
2342	Serge	5223
		5224	/* Turn off the SSC source */
3746	Serge	5225	val &= ~DREF_SSC_SOURCE_MASK;
		5226	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	5227
		5228	/* Turn off SSC1 */
3746	Serge	5229	val &= ~DREF_SSC1_ENABLE;
2342	Serge	5230
3746	Serge	5231	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5232	POSTING_READ(PCH_DREF_CONTROL);
		5233	udelay(200);
2327	Serge	5234	}
3746	Serge	5235
		5236	BUG_ON(val != final);
2327	Serge	5237	}
		5238
4104	Serge	5239	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	5240	{
4104	Serge	5241	uint32_t tmp;
3243	Serge	5242
		5243	tmp = I915_READ(SOUTH_CHICKEN2);
		5244	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		5245	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5246
		5247	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		5248	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		5249	DRM_ERROR("FDI mPHY reset assert timeout\n");
		5250
		5251	tmp = I915_READ(SOUTH_CHICKEN2);
		5252	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		5253	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5254
		5255	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	5256	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
3243	Serge	5257	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
		5258	}
		5259
4104	Serge	5260	/* WaMPhyProgramming:hsw */
		5261	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		5262	{
		5263	uint32_t tmp;
		5264
3243	Serge	5265	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		5266	tmp &= ~(0xFF << 24);
		5267	tmp \|= (0x12 << 24);
		5268	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		5269
		5270	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		5271	tmp \|= (1 << 11);
		5272	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		5273
		5274	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		5275	tmp \|= (1 << 11);
		5276	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		5277
		5278	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		5279	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5280	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		5281
		5282	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		5283	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5284	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		5285
		5286	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		5287	tmp &= ~(7 << 13);
		5288	tmp \|= (5 << 13);
		5289	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		5290
		5291	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		5292	tmp &= ~(7 << 13);
		5293	tmp \|= (5 << 13);
		5294	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		5295
		5296	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		5297	tmp &= ~0xFF;
		5298	tmp \|= 0x1C;
		5299	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		5300
		5301	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		5302	tmp &= ~0xFF;
		5303	tmp \|= 0x1C;
		5304	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		5305
		5306	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		5307	tmp &= ~(0xFF << 16);
		5308	tmp \|= (0x1C << 16);
		5309	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		5310
		5311	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		5312	tmp &= ~(0xFF << 16);
		5313	tmp \|= (0x1C << 16);
		5314	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		5315
		5316	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		5317	tmp \|= (1 << 27);
		5318	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		5319
		5320	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		5321	tmp \|= (1 << 27);
		5322	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		5323
		5324	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		5325	tmp &= ~(0xF << 28);
		5326	tmp \|= (4 << 28);
		5327	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		5328
		5329	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		5330	tmp &= ~(0xF << 28);
		5331	tmp \|= (4 << 28);
		5332	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
		5333	}
		5334
4104	Serge	5335	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		5336	* Programming" based on the parameters passed:
		5337	* - Sequence to enable CLKOUT_DP
		5338	* - Sequence to enable CLKOUT_DP without spread
		5339	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		5340	*/
		5341	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		5342	bool with_fdi)
		5343	{
		5344	struct drm_i915_private *dev_priv = dev->dev_private;
		5345	uint32_t reg, tmp;
3480	Serge	5346
4104	Serge	5347	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		5348	with_spread = true;
		5349	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		5350	with_fdi, "LP PCH doesn't have FDI\n"))
		5351	with_fdi = false;
		5352
		5353	mutex_lock(&dev_priv->dpio_lock);
		5354
		5355	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5356	tmp &= ~SBI_SSCCTL_DISABLE;
		5357	tmp \|= SBI_SSCCTL_PATHALT;
		5358	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5359
		5360	udelay(24);
		5361
		5362	if (with_spread) {
		5363	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5364	tmp &= ~SBI_SSCCTL_PATHALT;
		5365	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5366
		5367	if (with_fdi) {
		5368	lpt_reset_fdi_mphy(dev_priv);
		5369	lpt_program_fdi_mphy(dev_priv);
		5370	}
		5371	}
		5372
		5373	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5374	SBI_GEN0 : SBI_DBUFF0;
		5375	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5376	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5377	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5378
3480	Serge	5379	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	5380	}
		5381
4104	Serge	5382	/* Sequence to disable CLKOUT_DP */
		5383	static void lpt_disable_clkout_dp(struct drm_device *dev)
		5384	{
		5385	struct drm_i915_private *dev_priv = dev->dev_private;
		5386	uint32_t reg, tmp;
		5387
		5388	mutex_lock(&dev_priv->dpio_lock);
		5389
		5390	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5391	SBI_GEN0 : SBI_DBUFF0;
		5392	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5393	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5394	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5395
		5396	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5397	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		5398	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		5399	tmp \|= SBI_SSCCTL_PATHALT;
		5400	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5401	udelay(32);
		5402	}
		5403	tmp \|= SBI_SSCCTL_DISABLE;
		5404	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5405	}
		5406
		5407	mutex_unlock(&dev_priv->dpio_lock);
		5408	}
		5409
		5410	static void lpt_init_pch_refclk(struct drm_device *dev)
		5411	{
		5412	struct drm_mode_config *mode_config = &dev->mode_config;
		5413	struct intel_encoder *encoder;
		5414	bool has_vga = false;
		5415
		5416	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5417	switch (encoder->type) {
		5418	case INTEL_OUTPUT_ANALOG:
		5419	has_vga = true;
		5420	break;
		5421	}
		5422	}
		5423
		5424	if (has_vga)
		5425	lpt_enable_clkout_dp(dev, true, true);
		5426	else
		5427	lpt_disable_clkout_dp(dev);
		5428	}
		5429
3243	Serge	5430	/*
		5431	* Initialize reference clocks when the driver loads
		5432	*/
		5433	void intel_init_pch_refclk(struct drm_device *dev)
		5434	{
		5435	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		5436	ironlake_init_pch_refclk(dev);
		5437	else if (HAS_PCH_LPT(dev))
		5438	lpt_init_pch_refclk(dev);
		5439	}
		5440
2342	Serge	5441	static int ironlake_get_refclk(struct drm_crtc *crtc)
		5442	{
		5443	struct drm_device *dev = crtc->dev;
		5444	struct drm_i915_private *dev_priv = dev->dev_private;
		5445	struct intel_encoder *encoder;
		5446	int num_connectors = 0;
		5447	bool is_lvds = false;
		5448
3031	serge	5449	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	5450	switch (encoder->type) {
		5451	case INTEL_OUTPUT_LVDS:
		5452	is_lvds = true;
		5453	break;
		5454	}
		5455	num_connectors++;
		5456	}
		5457
		5458	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5459	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4104	Serge	5460	dev_priv->vbt.lvds_ssc_freq);
		5461	return dev_priv->vbt.lvds_ssc_freq * 1000;
2342	Serge	5462	}
		5463
		5464	return 120000;
		5465	}
		5466
4104	Serge	5467	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	5468	{
		5469	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5470	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5471	int pipe = intel_crtc->pipe;
		5472	uint32_t val;
		5473
4104	Serge	5474	val = 0;
3031	serge	5475
3746	Serge	5476	switch (intel_crtc->config.pipe_bpp) {
3031	serge	5477	case 18:
3480	Serge	5478	val \|= PIPECONF_6BPC;
3031	serge	5479	break;
		5480	case 24:
3480	Serge	5481	val \|= PIPECONF_8BPC;
3031	serge	5482	break;
		5483	case 30:
3480	Serge	5484	val \|= PIPECONF_10BPC;
3031	serge	5485	break;
		5486	case 36:
3480	Serge	5487	val \|= PIPECONF_12BPC;
3031	serge	5488	break;
		5489	default:
3243	Serge	5490	/* Case prevented by intel_choose_pipe_bpp_dither. */
		5491	BUG();
3031	serge	5492	}
		5493
4104	Serge	5494	if (intel_crtc->config.dither)
3031	serge	5495	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5496
4104	Serge	5497	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	5498	val \|= PIPECONF_INTERLACED_ILK;
		5499	else
		5500	val \|= PIPECONF_PROGRESSIVE;
		5501
3746	Serge	5502	if (intel_crtc->config.limited_color_range)
3480	Serge	5503	val \|= PIPECONF_COLOR_RANGE_SELECT;
		5504
3031	serge	5505	I915_WRITE(PIPECONF(pipe), val);
		5506	POSTING_READ(PIPECONF(pipe));
		5507	}
		5508
3480	Serge	5509	/*
		5510	* Set up the pipe CSC unit.
		5511	*
		5512	* Currently only full range RGB to limited range RGB conversion
		5513	* is supported, but eventually this should handle various
		5514	* RGB<->YCbCr scenarios as well.
		5515	*/
3746	Serge	5516	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	5517	{
		5518	struct drm_device *dev = crtc->dev;
		5519	struct drm_i915_private *dev_priv = dev->dev_private;
		5520	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5521	int pipe = intel_crtc->pipe;
		5522	uint16_t coeff = 0x7800; /* 1.0 */
		5523
		5524	/*
		5525	* TODO: Check what kind of values actually come out of the pipe
		5526	* with these coeff/postoff values and adjust to get the best
		5527	* accuracy. Perhaps we even need to take the bpc value into
		5528	* consideration.
		5529	*/
		5530
3746	Serge	5531	if (intel_crtc->config.limited_color_range)
3480	Serge	5532	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		5533
		5534	/*
		5535	* GY/GU and RY/RU should be the other way around according
		5536	* to BSpec, but reality doesn't agree. Just set them up in
		5537	* a way that results in the correct picture.
		5538	*/
		5539	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		5540	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		5541
		5542	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		5543	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		5544
		5545	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		5546	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		5547
		5548	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		5549	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		5550	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		5551
		5552	if (INTEL_INFO(dev)->gen > 6) {
		5553	uint16_t postoff = 0;
		5554
3746	Serge	5555	if (intel_crtc->config.limited_color_range)
3480	Serge	5556	postoff = (16 * (1 << 13) / 255) & 0x1fff;
		5557
		5558	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		5559	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		5560	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		5561
		5562	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		5563	} else {
		5564	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		5565
3746	Serge	5566	if (intel_crtc->config.limited_color_range)
3480	Serge	5567	mode \|= CSC_BLACK_SCREEN_OFFSET;
		5568
		5569	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		5570	}
		5571	}
		5572
4104	Serge	5573	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	5574	{
		5575	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5576	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5577	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	5578	uint32_t val;
		5579
4104	Serge	5580	val = 0;
3243	Serge	5581
4104	Serge	5582	if (intel_crtc->config.dither)
3243	Serge	5583	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5584
4104	Serge	5585	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	5586	val \|= PIPECONF_INTERLACED_ILK;
		5587	else
		5588	val \|= PIPECONF_PROGRESSIVE;
		5589
		5590	I915_WRITE(PIPECONF(cpu_transcoder), val);
		5591	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	5592
		5593	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		5594	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
3243	Serge	5595	}
		5596
3031	serge	5597	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		5598	intel_clock_t *clock,
		5599	bool *has_reduced_clock,
		5600	intel_clock_t *reduced_clock)
		5601	{
		5602	struct drm_device *dev = crtc->dev;
		5603	struct drm_i915_private *dev_priv = dev->dev_private;
		5604	struct intel_encoder *intel_encoder;
		5605	int refclk;
		5606	const intel_limit_t *limit;
4104	Serge	5607	bool ret, is_lvds = false;
3031	serge	5608
		5609	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5610	switch (intel_encoder->type) {
		5611	case INTEL_OUTPUT_LVDS:
		5612	is_lvds = true;
		5613	break;
		5614	}
		5615	}
		5616
		5617	refclk = ironlake_get_refclk(crtc);
		5618
		5619	/*
		5620	* Returns a set of divisors for the desired target clock with the given
		5621	* refclk, or FALSE. The returned values represent the clock equation:
		5622	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5623	*/
		5624	limit = intel_limit(crtc, refclk);
4104	Serge	5625	ret = dev_priv->display.find_dpll(limit, crtc,
		5626	to_intel_crtc(crtc)->config.port_clock,
		5627	refclk, NULL, clock);
3031	serge	5628	if (!ret)
		5629	return false;
		5630
		5631	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5632	/*
		5633	* Ensure we match the reduced clock's P to the target clock.
		5634	* If the clocks don't match, we can't switch the display clock
		5635	* by using the FP0/FP1. In such case we will disable the LVDS
		5636	* downclock feature.
		5637	*/
4104	Serge	5638	*has_reduced_clock =
		5639	dev_priv->display.find_dpll(limit, crtc,
3031	serge	5640	dev_priv->lvds_downclock,
4104	Serge	5641	refclk, clock,
3031	serge	5642	reduced_clock);
		5643	}
		5644
		5645	return true;
		5646	}
		5647
3243	Serge	5648	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		5649	{
		5650	/*
		5651	* Account for spread spectrum to avoid
		5652	* oversubscribing the link. Max center spread
		5653	* is 2.5%; use 5% for safety's sake.
		5654	*/
		5655	u32 bps = target_clock * bpp * 21 / 20;
		5656	return bps / (link_bw * 8) + 1;
		5657	}
		5658
4104	Serge	5659	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	5660	{
4104	Serge	5661	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	5662	}
		5663
3243	Serge	5664	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4104	Serge	5665	u32 *fp,
3746	Serge	5666	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	5667	{
		5668	struct drm_crtc *crtc = &intel_crtc->base;
		5669	struct drm_device *dev = crtc->dev;
		5670	struct drm_i915_private *dev_priv = dev->dev_private;
		5671	struct intel_encoder *intel_encoder;
		5672	uint32_t dpll;
3746	Serge	5673	int factor, num_connectors = 0;
4104	Serge	5674	bool is_lvds = false, is_sdvo = false;
3243	Serge	5675
		5676	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5677	switch (intel_encoder->type) {
		5678	case INTEL_OUTPUT_LVDS:
		5679	is_lvds = true;
		5680	break;
		5681	case INTEL_OUTPUT_SDVO:
		5682	case INTEL_OUTPUT_HDMI:
		5683	is_sdvo = true;
		5684	break;
		5685	}
		5686
		5687	num_connectors++;
		5688	}
		5689
2327	Serge	5690	/* Enable autotuning of the PLL clock (if permissible) */
		5691	factor = 21;
		5692	if (is_lvds) {
		5693	if ((intel_panel_use_ssc(dev_priv) &&
4104	Serge	5694	dev_priv->vbt.lvds_ssc_freq == 100) \|\|
3746	Serge	5695	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	5696	factor = 25;
4104	Serge	5697	} else if (intel_crtc->config.sdvo_tv_clock)
2327	Serge	5698	factor = 20;
		5699
4104	Serge	5700	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
3746	Serge	5701	*fp \|= FP_CB_TUNE;
2327	Serge	5702
3746	Serge	5703	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		5704	*fp2 \|= FP_CB_TUNE;
		5705
2327	Serge	5706	dpll = 0;
		5707
		5708	if (is_lvds)
		5709	dpll \|= DPLLB_MODE_LVDS;
		5710	else
		5711	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	5712
3746	Serge	5713	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		5714	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	5715
4104	Serge	5716	if (is_sdvo)
		5717	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5718	if (intel_crtc->config.has_dp_encoder)
		5719	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5720
2327	Serge	5721	/* compute bitmask from p1 value */
4104	Serge	5722	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	5723	/* also FPA1 */
4104	Serge	5724	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	5725
4104	Serge	5726	switch (intel_crtc->config.dpll.p2) {
2327	Serge	5727	case 5:
		5728	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5729	break;
		5730	case 7:
		5731	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5732	break;
		5733	case 10:
		5734	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5735	break;
		5736	case 14:
		5737	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5738	break;
		5739	}
		5740
4104	Serge	5741	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
2327	Serge	5742	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5743	else
		5744	dpll \|= PLL_REF_INPUT_DREFCLK;
		5745
4104	Serge	5746	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	5747	}
		5748
		5749	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5750	int x, int y,
		5751	struct drm_framebuffer *fb)
		5752	{
		5753	struct drm_device *dev = crtc->dev;
		5754	struct drm_i915_private *dev_priv = dev->dev_private;
		5755	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5756	int pipe = intel_crtc->pipe;
		5757	int plane = intel_crtc->plane;
		5758	int num_connectors = 0;
		5759	intel_clock_t clock, reduced_clock;
4104	Serge	5760	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	5761	bool ok, has_reduced_clock = false;
3746	Serge	5762	bool is_lvds = false;
3243	Serge	5763	struct intel_encoder *encoder;
4104	Serge	5764	struct intel_shared_dpll *pll;
3243	Serge	5765	int ret;
		5766
		5767	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5768	switch (encoder->type) {
		5769	case INTEL_OUTPUT_LVDS:
		5770	is_lvds = true;
		5771	break;
		5772	}
		5773
		5774	num_connectors++;
		5775	}
		5776
		5777	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		5778	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		5779
4104	Serge	5780	ok = ironlake_compute_clocks(crtc, &clock,
3243	Serge	5781	&has_reduced_clock, &reduced_clock);
4104	Serge	5782	if (!ok && !intel_crtc->config.clock_set) {
3243	Serge	5783	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5784	return -EINVAL;
		5785	}
3746	Serge	5786	/* Compat-code for transition, will disappear. */
		5787	if (!intel_crtc->config.clock_set) {
		5788	intel_crtc->config.dpll.n = clock.n;
		5789	intel_crtc->config.dpll.m1 = clock.m1;
		5790	intel_crtc->config.dpll.m2 = clock.m2;
		5791	intel_crtc->config.dpll.p1 = clock.p1;
		5792	intel_crtc->config.dpll.p2 = clock.p2;
		5793	}
3243	Serge	5794
4104	Serge	5795	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
		5796	if (intel_crtc->config.has_pch_encoder) {
		5797	fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
3243	Serge	5798	if (has_reduced_clock)
4104	Serge	5799	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	5800
4104	Serge	5801	dpll = ironlake_compute_dpll(intel_crtc,
		5802	&fp, &reduced_clock,
3746	Serge	5803	has_reduced_clock ? &fp2 : NULL);
3243	Serge	5804
4104	Serge	5805	intel_crtc->config.dpll_hw_state.dpll = dpll;
		5806	intel_crtc->config.dpll_hw_state.fp0 = fp;
		5807	if (has_reduced_clock)
		5808	intel_crtc->config.dpll_hw_state.fp1 = fp2;
		5809	else
		5810	intel_crtc->config.dpll_hw_state.fp1 = fp;
2327	Serge	5811
4104	Serge	5812	pll = intel_get_shared_dpll(intel_crtc);
3031	serge	5813	if (pll == NULL) {
4104	Serge	5814	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		5815	pipe_name(pipe));
2342	Serge	5816	return -EINVAL;
2327	Serge	5817	}
3031	serge	5818	} else
4104	Serge	5819	intel_put_shared_dpll(intel_crtc);
2327	Serge	5820
3746	Serge	5821	if (intel_crtc->config.has_dp_encoder)
		5822	intel_dp_set_m_n(intel_crtc);
2342	Serge	5823
4104	Serge	5824	if (is_lvds && has_reduced_clock && i915_powersave)
		5825	intel_crtc->lowfreq_avail = true;
		5826	else
		5827	intel_crtc->lowfreq_avail = false;
2327	Serge	5828
4104	Serge	5829	if (intel_crtc->config.has_pch_encoder) {
		5830	pll = intel_crtc_to_shared_dpll(intel_crtc);
2327	Serge	5831
4104	Serge	5832	}
2327	Serge	5833
4104	Serge	5834	intel_set_pipe_timings(intel_crtc);
2327	Serge	5835
4104	Serge	5836	if (intel_crtc->config.has_pch_encoder) {
		5837	intel_cpu_transcoder_set_m_n(intel_crtc,
		5838	&intel_crtc->config.fdi_m_n);
2342	Serge	5839	}
2327	Serge	5840
4104	Serge	5841	ironlake_set_pipeconf(crtc);
3243	Serge	5842
		5843	/* Set up the display plane register */
		5844	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		5845	POSTING_READ(DSPCNTR(plane));
		5846
		5847	ret = intel_pipe_set_base(crtc, x, y, fb);
		5848
		5849	intel_update_watermarks(dev);
		5850
4104	Serge	5851	return ret;
		5852	}
3243	Serge	5853
4104	Serge	5854	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
		5855	struct intel_crtc_config *pipe_config)
		5856	{
		5857	struct drm_device *dev = crtc->base.dev;
		5858	struct drm_i915_private *dev_priv = dev->dev_private;
		5859	enum transcoder transcoder = pipe_config->cpu_transcoder;
		5860
		5861	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
		5862	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
		5863	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
		5864	& ~TU_SIZE_MASK;
		5865	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		5866	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
		5867	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3243	Serge	5868	}
		5869
4104	Serge	5870	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
		5871	struct intel_crtc_config *pipe_config)
		5872	{
		5873	struct drm_device *dev = crtc->base.dev;
		5874	struct drm_i915_private *dev_priv = dev->dev_private;
		5875	uint32_t tmp;
		5876
		5877	tmp = I915_READ(PF_CTL(crtc->pipe));
		5878
		5879	if (tmp & PF_ENABLE) {
		5880	pipe_config->pch_pfit.enabled = true;
		5881	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		5882	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		5883
		5884	/* We currently do not free assignements of panel fitters on
		5885	* ivb/hsw (since we don't use the higher upscaling modes which
		5886	* differentiates them) so just WARN about this case for now. */
		5887	if (IS_GEN7(dev)) {
		5888	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		5889	PF_PIPE_SEL_IVB(crtc->pipe));
		5890	}
		5891	}
		5892	}
		5893
3746	Serge	5894	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		5895	struct intel_crtc_config *pipe_config)
		5896	{
		5897	struct drm_device *dev = crtc->base.dev;
		5898	struct drm_i915_private *dev_priv = dev->dev_private;
		5899	uint32_t tmp;
		5900
4104	Serge	5901	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5902	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5903
3746	Serge	5904	tmp = I915_READ(PIPECONF(crtc->pipe));
		5905	if (!(tmp & PIPECONF_ENABLE))
		5906	return false;
		5907
4280	Serge	5908	switch (tmp & PIPECONF_BPC_MASK) {
		5909	case PIPECONF_6BPC:
		5910	pipe_config->pipe_bpp = 18;
		5911	break;
		5912	case PIPECONF_8BPC:
		5913	pipe_config->pipe_bpp = 24;
		5914	break;
		5915	case PIPECONF_10BPC:
		5916	pipe_config->pipe_bpp = 30;
		5917	break;
		5918	case PIPECONF_12BPC:
		5919	pipe_config->pipe_bpp = 36;
		5920	break;
		5921	default:
		5922	break;
		5923	}
		5924
4104	Serge	5925	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		5926	struct intel_shared_dpll *pll;
		5927
3746	Serge	5928	pipe_config->has_pch_encoder = true;
		5929
4104	Serge	5930	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		5931	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		5932	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		5933
		5934	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		5935
		5936	if (HAS_PCH_IBX(dev_priv->dev)) {
		5937	pipe_config->shared_dpll =
		5938	(enum intel_dpll_id) crtc->pipe;
		5939	} else {
		5940	tmp = I915_READ(PCH_DPLL_SEL);
		5941	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		5942	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		5943	else
		5944	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		5945	}
		5946
		5947	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		5948
		5949	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		5950	&pipe_config->dpll_hw_state));
		5951
		5952	tmp = pipe_config->dpll_hw_state.dpll;
		5953	pipe_config->pixel_multiplier =
		5954	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		5955	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
		5956	} else {
		5957	pipe_config->pixel_multiplier = 1;
		5958	}
		5959
		5960	intel_get_pipe_timings(crtc, pipe_config);
		5961
		5962	ironlake_get_pfit_config(crtc, pipe_config);
		5963
3746	Serge	5964	return true;
		5965	}
		5966
4104	Serge	5967	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		5968	{
		5969	struct drm_device *dev = dev_priv->dev;
		5970	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		5971	struct intel_crtc *crtc;
		5972	unsigned long irqflags;
		5973	uint32_t val;
		5974
		5975	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		5976	WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
		5977	pipe_name(crtc->pipe));
		5978
		5979	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
		5980	WARN(plls->spll_refcount, "SPLL enabled\n");
		5981	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
		5982	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
		5983	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		5984	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
		5985	"CPU PWM1 enabled\n");
		5986	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		5987	"CPU PWM2 enabled\n");
		5988	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
		5989	"PCH PWM1 enabled\n");
		5990	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
		5991	"Utility pin enabled\n");
		5992	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
		5993
		5994	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		5995	val = I915_READ(DEIMR);
		5996	WARN((val & ~DE_PCH_EVENT_IVB) != val,
		5997	"Unexpected DEIMR bits enabled: 0x%x\n", val);
		5998	val = I915_READ(SDEIMR);
		5999	WARN((val \| SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
		6000	"Unexpected SDEIMR bits enabled: 0x%x\n", val);
		6001	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
		6002	}
		6003
		6004	/*
		6005	* This function implements pieces of two sequences from BSpec:
		6006	* - Sequence for display software to disable LCPLL
		6007	* - Sequence for display software to allow package C8+
		6008	* The steps implemented here are just the steps that actually touch the LCPLL
		6009	* register. Callers should take care of disabling all the display engine
		6010	* functions, doing the mode unset, fixing interrupts, etc.
		6011	*/
		6012	void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
		6013	bool switch_to_fclk, bool allow_power_down)
		6014	{
		6015	uint32_t val;
		6016
		6017	assert_can_disable_lcpll(dev_priv);
		6018
		6019	val = I915_READ(LCPLL_CTL);
		6020
		6021	if (switch_to_fclk) {
		6022	val \|= LCPLL_CD_SOURCE_FCLK;
		6023	I915_WRITE(LCPLL_CTL, val);
		6024
		6025	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		6026	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		6027	DRM_ERROR("Switching to FCLK failed\n");
		6028
		6029	val = I915_READ(LCPLL_CTL);
		6030	}
		6031
		6032	val \|= LCPLL_PLL_DISABLE;
		6033	I915_WRITE(LCPLL_CTL, val);
		6034	POSTING_READ(LCPLL_CTL);
		6035
		6036	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		6037	DRM_ERROR("LCPLL still locked\n");
		6038
		6039	val = I915_READ(D_COMP);
		6040	val \|= D_COMP_COMP_DISABLE;
		6041	I915_WRITE(D_COMP, val);
		6042	POSTING_READ(D_COMP);
		6043	udelay(100);
		6044
		6045	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
		6046	DRM_ERROR("D_COMP RCOMP still in progress\n");
		6047
		6048	if (allow_power_down) {
		6049	val = I915_READ(LCPLL_CTL);
		6050	val \|= LCPLL_POWER_DOWN_ALLOW;
		6051	I915_WRITE(LCPLL_CTL, val);
		6052	POSTING_READ(LCPLL_CTL);
		6053	}
		6054	}
		6055
		6056	/*
		6057	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		6058	* source.
		6059	*/
		6060	void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
		6061	{
		6062	uint32_t val;
		6063
		6064	val = I915_READ(LCPLL_CTL);
		6065
		6066	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		6067	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		6068	return;
		6069
		6070	/* Make sure we're not on PC8 state before disabling PC8, otherwise
		6071	* we'll hang the machine! */
		6072	dev_priv->uncore.funcs.force_wake_get(dev_priv);
		6073
		6074	if (val & LCPLL_POWER_DOWN_ALLOW) {
		6075	val &= ~LCPLL_POWER_DOWN_ALLOW;
		6076	I915_WRITE(LCPLL_CTL, val);
		6077	POSTING_READ(LCPLL_CTL);
		6078	}
		6079
		6080	val = I915_READ(D_COMP);
		6081	val \|= D_COMP_COMP_FORCE;
		6082	val &= ~D_COMP_COMP_DISABLE;
		6083	I915_WRITE(D_COMP, val);
		6084	POSTING_READ(D_COMP);
		6085
		6086	val = I915_READ(LCPLL_CTL);
		6087	val &= ~LCPLL_PLL_DISABLE;
		6088	I915_WRITE(LCPLL_CTL, val);
		6089
		6090	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		6091	DRM_ERROR("LCPLL not locked yet\n");
		6092
		6093	if (val & LCPLL_CD_SOURCE_FCLK) {
		6094	val = I915_READ(LCPLL_CTL);
		6095	val &= ~LCPLL_CD_SOURCE_FCLK;
		6096	I915_WRITE(LCPLL_CTL, val);
		6097
		6098	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		6099	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		6100	DRM_ERROR("Switching back to LCPLL failed\n");
		6101	}
		6102
		6103	dev_priv->uncore.funcs.force_wake_put(dev_priv);
		6104	}
		6105
		6106	void hsw_enable_pc8_work(struct work_struct *__work)
		6107	{
		6108	struct drm_i915_private *dev_priv =
		6109	container_of(to_delayed_work(__work), struct drm_i915_private,
		6110	pc8.enable_work);
		6111	struct drm_device *dev = dev_priv->dev;
		6112	uint32_t val;
		6113
		6114	if (dev_priv->pc8.enabled)
		6115	return;
		6116
		6117	DRM_DEBUG_KMS("Enabling package C8+\n");
		6118
		6119	dev_priv->pc8.enabled = true;
		6120
		6121	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6122	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6123	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		6124	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6125	}
		6126
		6127	lpt_disable_clkout_dp(dev);
		6128	hsw_pc8_disable_interrupts(dev);
		6129	hsw_disable_lcpll(dev_priv, true, true);
		6130	}
		6131
		6132	static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6133	{
		6134	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6135	WARN(dev_priv->pc8.disable_count < 1,
		6136	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6137
		6138	dev_priv->pc8.disable_count--;
		6139	if (dev_priv->pc8.disable_count != 0)
		6140	return;
		6141
		6142	schedule_delayed_work(&dev_priv->pc8.enable_work,
		6143	msecs_to_jiffies(i915_pc8_timeout));
		6144	}
		6145
		6146	static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6147	{
		6148	struct drm_device *dev = dev_priv->dev;
		6149	uint32_t val;
		6150
		6151	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6152	WARN(dev_priv->pc8.disable_count < 0,
		6153	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6154
		6155	dev_priv->pc8.disable_count++;
		6156	if (dev_priv->pc8.disable_count != 1)
		6157	return;
		6158
4293	Serge	6159	cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
4104	Serge	6160	if (!dev_priv->pc8.enabled)
		6161	return;
		6162
		6163	DRM_DEBUG_KMS("Disabling package C8+\n");
		6164
		6165	hsw_restore_lcpll(dev_priv);
		6166	hsw_pc8_restore_interrupts(dev);
		6167	lpt_init_pch_refclk(dev);
		6168
		6169	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6170	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6171	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		6172	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6173	}
		6174
		6175	intel_prepare_ddi(dev);
		6176	i915_gem_init_swizzling(dev);
		6177	mutex_lock(&dev_priv->rps.hw_lock);
		6178	gen6_update_ring_freq(dev);
		6179	mutex_unlock(&dev_priv->rps.hw_lock);
		6180	dev_priv->pc8.enabled = false;
		6181	}
		6182
		6183	void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6184	{
		6185	mutex_lock(&dev_priv->pc8.lock);
		6186	__hsw_enable_package_c8(dev_priv);
		6187	mutex_unlock(&dev_priv->pc8.lock);
		6188	}
		6189
		6190	void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6191	{
		6192	mutex_lock(&dev_priv->pc8.lock);
		6193	__hsw_disable_package_c8(dev_priv);
		6194	mutex_unlock(&dev_priv->pc8.lock);
		6195	}
		6196
		6197	static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
		6198	{
		6199	struct drm_device *dev = dev_priv->dev;
		6200	struct intel_crtc *crtc;
		6201	uint32_t val;
		6202
		6203	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		6204	if (crtc->base.enabled)
		6205	return false;
		6206
		6207	/* This case is still possible since we have the i915.disable_power_well
		6208	* parameter and also the KVMr or something else might be requesting the
		6209	* power well. */
		6210	val = I915_READ(HSW_PWR_WELL_DRIVER);
		6211	if (val != 0) {
		6212	DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
		6213	return false;
		6214	}
		6215
		6216	return true;
		6217	}
		6218
		6219	/* Since we're called from modeset_global_resources there's no way to
		6220	* symmetrically increase and decrease the refcount, so we use
		6221	* dev_priv->pc8.requirements_met to track whether we already have the refcount
		6222	* or not.
		6223	*/
		6224	static void hsw_update_package_c8(struct drm_device *dev)
		6225	{
		6226	struct drm_i915_private *dev_priv = dev->dev_private;
		6227	bool allow;
		6228
		6229	if (!i915_enable_pc8)
		6230	return;
		6231
		6232	mutex_lock(&dev_priv->pc8.lock);
		6233
		6234	allow = hsw_can_enable_package_c8(dev_priv);
		6235
		6236	if (allow == dev_priv->pc8.requirements_met)
		6237	goto done;
		6238
		6239	dev_priv->pc8.requirements_met = allow;
		6240
		6241	if (allow)
		6242	__hsw_enable_package_c8(dev_priv);
		6243	else
		6244	__hsw_disable_package_c8(dev_priv);
		6245
		6246	done:
		6247	mutex_unlock(&dev_priv->pc8.lock);
		6248	}
		6249
		6250	static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
		6251	{
		6252	if (!dev_priv->pc8.gpu_idle) {
		6253	dev_priv->pc8.gpu_idle = true;
		6254	hsw_enable_package_c8(dev_priv);
		6255	}
		6256	}
		6257
		6258	static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
		6259	{
		6260	if (dev_priv->pc8.gpu_idle) {
		6261	dev_priv->pc8.gpu_idle = false;
		6262	hsw_disable_package_c8(dev_priv);
		6263	}
		6264	}
		6265
3480	Serge	6266	static void haswell_modeset_global_resources(struct drm_device *dev)
		6267	{
		6268	bool enable = false;
		6269	struct intel_crtc *crtc;
		6270
		6271	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4104	Serge	6272	if (!crtc->base.enabled)
		6273	continue;
3480	Serge	6274
4104	Serge	6275	if (crtc->pipe != PIPE_A \|\| crtc->config.pch_pfit.enabled \|\|
		6276	crtc->config.cpu_transcoder != TRANSCODER_EDP)
3480	Serge	6277	enable = true;
		6278	}
		6279
4104	Serge	6280	intel_set_power_well(dev, enable);
3480	Serge	6281
4104	Serge	6282	hsw_update_package_c8(dev);
3480	Serge	6283	}
		6284
3243	Serge	6285	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		6286	int x, int y,
		6287	struct drm_framebuffer *fb)
		6288	{
		6289	struct drm_device *dev = crtc->dev;
		6290	struct drm_i915_private *dev_priv = dev->dev_private;
		6291	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6292	int plane = intel_crtc->plane;
		6293	int ret;
		6294
4104	Serge	6295	if (!intel_ddi_pll_mode_set(crtc))
3243	Serge	6296	return -EINVAL;
		6297
3746	Serge	6298	if (intel_crtc->config.has_dp_encoder)
		6299	intel_dp_set_m_n(intel_crtc);
2327	Serge	6300
3243	Serge	6301	intel_crtc->lowfreq_avail = false;
2327	Serge	6302
4104	Serge	6303	intel_set_pipe_timings(intel_crtc);
3243	Serge	6304
4104	Serge	6305	if (intel_crtc->config.has_pch_encoder) {
		6306	intel_cpu_transcoder_set_m_n(intel_crtc,
		6307	&intel_crtc->config.fdi_m_n);
		6308	}
3243	Serge	6309
4104	Serge	6310	haswell_set_pipeconf(crtc);
2327	Serge	6311
3746	Serge	6312	intel_set_pipe_csc(crtc);
3480	Serge	6313
3031	serge	6314	/* Set up the display plane register */
3480	Serge	6315	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
2327	Serge	6316	POSTING_READ(DSPCNTR(plane));
		6317
3031	serge	6318	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	6319
		6320	intel_update_watermarks(dev);
		6321
		6322	return ret;
		6323	}
		6324
3746	Serge	6325	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		6326	struct intel_crtc_config *pipe_config)
		6327	{
		6328	struct drm_device *dev = crtc->base.dev;
		6329	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	6330	enum intel_display_power_domain pfit_domain;
3746	Serge	6331	uint32_t tmp;
		6332
4104	Serge	6333	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		6334	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		6335
		6336	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		6337	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		6338	enum pipe trans_edp_pipe;
		6339	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		6340	default:
		6341	WARN(1, "unknown pipe linked to edp transcoder\n");
		6342	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		6343	case TRANS_DDI_EDP_INPUT_A_ON:
		6344	trans_edp_pipe = PIPE_A;
		6345	break;
		6346	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		6347	trans_edp_pipe = PIPE_B;
		6348	break;
		6349	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		6350	trans_edp_pipe = PIPE_C;
		6351	break;
		6352	}
		6353
		6354	if (trans_edp_pipe == crtc->pipe)
		6355	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		6356	}
		6357
		6358	if (!intel_display_power_enabled(dev,
		6359	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		6360	return false;
		6361
		6362	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	6363	if (!(tmp & PIPECONF_ENABLE))
		6364	return false;
		6365
		6366	/*
4104	Serge	6367	* Haswell has only FDI/PCH transcoder A. It is which is connected to
3746	Serge	6368	* DDI E. So just check whether this pipe is wired to DDI E and whether
		6369	* the PCH transcoder is on.
		6370	*/
4104	Serge	6371	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3746	Serge	6372	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
4104	Serge	6373	I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
3746	Serge	6374	pipe_config->has_pch_encoder = true;
		6375
4104	Serge	6376	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		6377	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		6378	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3746	Serge	6379
4104	Serge	6380	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		6381	}
		6382
		6383	intel_get_pipe_timings(crtc, pipe_config);
		6384
		6385	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
		6386	if (intel_display_power_enabled(dev, pfit_domain))
		6387	ironlake_get_pfit_config(crtc, pipe_config);
		6388
		6389	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		6390	(I915_READ(IPS_CTL) & IPS_ENABLE);
		6391
		6392	pipe_config->pixel_multiplier = 1;
		6393
3746	Serge	6394	return true;
		6395	}
		6396
2330	Serge	6397	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		6398	int x, int y,
3031	serge	6399	struct drm_framebuffer *fb)
2330	Serge	6400	{
		6401	struct drm_device *dev = crtc->dev;
		6402	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	6403	struct intel_encoder *encoder;
2330	Serge	6404	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	6405	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
2330	Serge	6406	int pipe = intel_crtc->pipe;
		6407	int ret;
2327	Serge	6408
3031	serge	6409	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	6410
3746	Serge	6411	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
		6412
3031	serge	6413	drm_vblank_post_modeset(dev, pipe);
2327	Serge	6414
3243	Serge	6415	if (ret != 0)
2330	Serge	6416	return ret;
3243	Serge	6417
		6418	for_each_encoder_on_crtc(dev, crtc, encoder) {
		6419	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		6420	encoder->base.base.id,
		6421	drm_get_encoder_name(&encoder->base),
		6422	mode->base.id, mode->name);
3746	Serge	6423	encoder->mode_set(encoder);
3243	Serge	6424	}
		6425
		6426	return 0;
2330	Serge	6427	}
2327	Serge	6428
2342	Serge	6429	static bool intel_eld_uptodate(struct drm_connector *connector,
		6430	int reg_eldv, uint32_t bits_eldv,
		6431	int reg_elda, uint32_t bits_elda,
		6432	int reg_edid)
		6433	{
		6434	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6435	uint8_t *eld = connector->eld;
		6436	uint32_t i;
		6437
		6438	i = I915_READ(reg_eldv);
		6439	i &= bits_eldv;
		6440
		6441	if (!eld[0])
		6442	return !i;
		6443
		6444	if (!i)
		6445	return false;
		6446
		6447	i = I915_READ(reg_elda);
		6448	i &= ~bits_elda;
		6449	I915_WRITE(reg_elda, i);
		6450
		6451	for (i = 0; i < eld[2]; i++)
		6452	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		6453	return false;
		6454
		6455	return true;
		6456	}
		6457
		6458	static void g4x_write_eld(struct drm_connector *connector,
		6459	struct drm_crtc *crtc)
		6460	{
		6461	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6462	uint8_t *eld = connector->eld;
		6463	uint32_t eldv;
		6464	uint32_t len;
		6465	uint32_t i;
		6466
		6467	i = I915_READ(G4X_AUD_VID_DID);
		6468
		6469	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		6470	eldv = G4X_ELDV_DEVCL_DEVBLC;
		6471	else
		6472	eldv = G4X_ELDV_DEVCTG;
		6473
		6474	if (intel_eld_uptodate(connector,
		6475	G4X_AUD_CNTL_ST, eldv,
		6476	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		6477	G4X_HDMIW_HDMIEDID))
		6478	return;
		6479
		6480	i = I915_READ(G4X_AUD_CNTL_ST);
		6481	i &= ~(eldv \| G4X_ELD_ADDR);
		6482	len = (i >> 9) & 0x1f; /* ELD buffer size */
		6483	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6484
		6485	if (!eld[0])
		6486	return;
		6487
		6488	len = min_t(uint8_t, eld[2], len);
		6489	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6490	for (i = 0; i < len; i++)
		6491	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		6492
		6493	i = I915_READ(G4X_AUD_CNTL_ST);
		6494	i \|= eldv;
		6495	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6496	}
		6497
3031	serge	6498	static void haswell_write_eld(struct drm_connector *connector,
		6499	struct drm_crtc *crtc)
		6500	{
		6501	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6502	uint8_t *eld = connector->eld;
		6503	struct drm_device *dev = crtc->dev;
3480	Serge	6504	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6505	uint32_t eldv;
		6506	uint32_t i;
		6507	int len;
		6508	int pipe = to_intel_crtc(crtc)->pipe;
		6509	int tmp;
		6510
		6511	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		6512	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		6513	int aud_config = HSW_AUD_CFG(pipe);
		6514	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		6515
		6516
		6517	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		6518
		6519	/* Audio output enable */
		6520	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		6521	tmp = I915_READ(aud_cntrl_st2);
		6522	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		6523	I915_WRITE(aud_cntrl_st2, tmp);
		6524
		6525	/* Wait for 1 vertical blank */
		6526	intel_wait_for_vblank(dev, pipe);
		6527
		6528	/* Set ELD valid state */
		6529	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6530	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
3031	serge	6531	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		6532	I915_WRITE(aud_cntrl_st2, tmp);
		6533	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6534	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
3031	serge	6535
		6536	/* Enable HDMI mode */
		6537	tmp = I915_READ(aud_config);
4104	Serge	6538	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
3031	serge	6539	/* clear N_programing_enable and N_value_index */
		6540	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		6541	I915_WRITE(aud_config, tmp);
		6542
		6543	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		6544
		6545	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
3480	Serge	6546	intel_crtc->eld_vld = true;
3031	serge	6547
		6548	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6549	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6550	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		6551	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6552	} else
		6553	I915_WRITE(aud_config, 0);
		6554
		6555	if (intel_eld_uptodate(connector,
		6556	aud_cntrl_st2, eldv,
		6557	aud_cntl_st, IBX_ELD_ADDRESS,
		6558	hdmiw_hdmiedid))
		6559	return;
		6560
		6561	i = I915_READ(aud_cntrl_st2);
		6562	i &= ~eldv;
		6563	I915_WRITE(aud_cntrl_st2, i);
		6564
		6565	if (!eld[0])
		6566	return;
		6567
		6568	i = I915_READ(aud_cntl_st);
		6569	i &= ~IBX_ELD_ADDRESS;
		6570	I915_WRITE(aud_cntl_st, i);
		6571	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		6572	DRM_DEBUG_DRIVER("port num:%d\n", i);
		6573
		6574	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6575	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6576	for (i = 0; i < len; i++)
		6577	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6578
		6579	i = I915_READ(aud_cntrl_st2);
		6580	i \|= eldv;
		6581	I915_WRITE(aud_cntrl_st2, i);
		6582
		6583	}
		6584
2342	Serge	6585	static void ironlake_write_eld(struct drm_connector *connector,
		6586	struct drm_crtc *crtc)
		6587	{
		6588	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6589	uint8_t *eld = connector->eld;
		6590	uint32_t eldv;
		6591	uint32_t i;
		6592	int len;
		6593	int hdmiw_hdmiedid;
3031	serge	6594	int aud_config;
2342	Serge	6595	int aud_cntl_st;
		6596	int aud_cntrl_st2;
3031	serge	6597	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	6598
		6599	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	6600	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		6601	aud_config = IBX_AUD_CFG(pipe);
		6602	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	6603	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		6604	} else {
3031	serge	6605	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		6606	aud_config = CPT_AUD_CFG(pipe);
		6607	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	6608	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		6609	}
		6610
3031	serge	6611	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	6612
		6613	i = I915_READ(aud_cntl_st);
3031	serge	6614	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	6615	if (!i) {
		6616	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		6617	/* operate blindly on all ports */
		6618	eldv = IBX_ELD_VALIDB;
		6619	eldv \|= IBX_ELD_VALIDB << 4;
		6620	eldv \|= IBX_ELD_VALIDB << 8;
		6621	} else {
4104	Serge	6622	DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
2342	Serge	6623	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		6624	}
		6625
		6626	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6627	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6628	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	6629	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6630	} else
		6631	I915_WRITE(aud_config, 0);
2342	Serge	6632
		6633	if (intel_eld_uptodate(connector,
		6634	aud_cntrl_st2, eldv,
		6635	aud_cntl_st, IBX_ELD_ADDRESS,
		6636	hdmiw_hdmiedid))
		6637	return;
		6638
		6639	i = I915_READ(aud_cntrl_st2);
		6640	i &= ~eldv;
		6641	I915_WRITE(aud_cntrl_st2, i);
		6642
		6643	if (!eld[0])
		6644	return;
		6645
		6646	i = I915_READ(aud_cntl_st);
		6647	i &= ~IBX_ELD_ADDRESS;
		6648	I915_WRITE(aud_cntl_st, i);
		6649
		6650	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6651	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6652	for (i = 0; i < len; i++)
		6653	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6654
		6655	i = I915_READ(aud_cntrl_st2);
		6656	i \|= eldv;
		6657	I915_WRITE(aud_cntrl_st2, i);
		6658	}
		6659
		6660	void intel_write_eld(struct drm_encoder *encoder,
		6661	struct drm_display_mode *mode)
		6662	{
		6663	struct drm_crtc *crtc = encoder->crtc;
		6664	struct drm_connector *connector;
		6665	struct drm_device *dev = encoder->dev;
		6666	struct drm_i915_private *dev_priv = dev->dev_private;
		6667
		6668	connector = drm_select_eld(encoder, mode);
		6669	if (!connector)
		6670	return;
		6671
		6672	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6673	connector->base.id,
		6674	drm_get_connector_name(connector),
		6675	connector->encoder->base.id,
		6676	drm_get_encoder_name(connector->encoder));
		6677
		6678	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		6679
		6680	if (dev_priv->display.write_eld)
		6681	dev_priv->display.write_eld(connector, crtc);
		6682	}
		6683
2327	Serge	6684	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		6685	void intel_crtc_load_lut(struct drm_crtc *crtc)
		6686	{
		6687	struct drm_device *dev = crtc->dev;
		6688	struct drm_i915_private *dev_priv = dev->dev_private;
		6689	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	6690	enum pipe pipe = intel_crtc->pipe;
		6691	int palreg = PALETTE(pipe);
2327	Serge	6692	int i;
4104	Serge	6693	bool reenable_ips = false;
2327	Serge	6694
		6695	/* The clocks have to be on to load the palette. */
3031	serge	6696	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	6697	return;
		6698
4104	Serge	6699	if (!HAS_PCH_SPLIT(dev_priv->dev))
		6700	assert_pll_enabled(dev_priv, pipe);
		6701
2327	Serge	6702	/* use legacy palette for Ironlake */
		6703	if (HAS_PCH_SPLIT(dev))
4104	Serge	6704	palreg = LGC_PALETTE(pipe);
2327	Serge	6705
4104	Serge	6706	/* Workaround : Do not read or write the pipe palette/gamma data while
		6707	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		6708	*/
		6709	if (intel_crtc->config.ips_enabled &&
		6710	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		6711	GAMMA_MODE_MODE_SPLIT)) {
		6712	hsw_disable_ips(intel_crtc);
		6713	reenable_ips = true;
		6714	}
		6715
2327	Serge	6716	for (i = 0; i < 256; i++) {
		6717	I915_WRITE(palreg + 4 * i,
		6718	(intel_crtc->lut_r[i] << 16) \|
		6719	(intel_crtc->lut_g[i] << 8) \|
		6720	intel_crtc->lut_b[i]);
		6721	}
4104	Serge	6722
		6723	if (reenable_ips)
		6724	hsw_enable_ips(intel_crtc);
2327	Serge	6725	}
		6726
3031	serge	6727	#if 0
		6728	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		6729	{
		6730	struct drm_device *dev = crtc->dev;
		6731	struct drm_i915_private *dev_priv = dev->dev_private;
		6732	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6733	bool visible = base != 0;
		6734	u32 cntl;
2327	Serge	6735
3031	serge	6736	if (intel_crtc->cursor_visible == visible)
		6737	return;
2327	Serge	6738
3031	serge	6739	cntl = I915_READ(_CURACNTR);
		6740	if (visible) {
		6741	/* On these chipsets we can only modify the base whilst
		6742	* the cursor is disabled.
		6743	*/
		6744	I915_WRITE(_CURABASE, base);
2327	Serge	6745
3031	serge	6746	cntl &= ~(CURSOR_FORMAT_MASK);
		6747	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		6748	cntl \|= CURSOR_ENABLE \|
		6749	CURSOR_GAMMA_ENABLE \|
		6750	CURSOR_FORMAT_ARGB;
		6751	} else
		6752	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		6753	I915_WRITE(_CURACNTR, cntl);
2327	Serge	6754
3031	serge	6755	intel_crtc->cursor_visible = visible;
		6756	}
2327	Serge	6757
3031	serge	6758	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		6759	{
		6760	struct drm_device *dev = crtc->dev;
		6761	struct drm_i915_private *dev_priv = dev->dev_private;
		6762	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6763	int pipe = intel_crtc->pipe;
		6764	bool visible = base != 0;
2327	Serge	6765
3031	serge	6766	if (intel_crtc->cursor_visible != visible) {
		6767	uint32_t cntl = I915_READ(CURCNTR(pipe));
		6768	if (base) {
		6769	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		6770	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6771	cntl \|= pipe << 28; /* Connect to correct pipe */
		6772	} else {
		6773	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6774	cntl \|= CURSOR_MODE_DISABLE;
		6775	}
		6776	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	6777
3031	serge	6778	intel_crtc->cursor_visible = visible;
		6779	}
		6780	/* and commit changes on next vblank */
4371	Serge	6781	POSTING_READ(CURCNTR(pipe));
3031	serge	6782	I915_WRITE(CURBASE(pipe), base);
4371	Serge	6783	POSTING_READ(CURBASE(pipe));
3031	serge	6784	}
2327	Serge	6785
3031	serge	6786	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		6787	{
		6788	struct drm_device *dev = crtc->dev;
		6789	struct drm_i915_private *dev_priv = dev->dev_private;
		6790	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6791	int pipe = intel_crtc->pipe;
		6792	bool visible = base != 0;
2327	Serge	6793
3031	serge	6794	if (intel_crtc->cursor_visible != visible) {
		6795	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		6796	if (base) {
		6797	cntl &= ~CURSOR_MODE;
		6798	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6799	} else {
		6800	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6801	cntl \|= CURSOR_MODE_DISABLE;
		6802	}
4104	Serge	6803	if (IS_HASWELL(dev)) {
3480	Serge	6804	cntl \|= CURSOR_PIPE_CSC_ENABLE;
4104	Serge	6805	cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
		6806	}
3031	serge	6807	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	6808
3031	serge	6809	intel_crtc->cursor_visible = visible;
		6810	}
		6811	/* and commit changes on next vblank */
4371	Serge	6812	POSTING_READ(CURCNTR_IVB(pipe));
3031	serge	6813	I915_WRITE(CURBASE_IVB(pipe), base);
4371	Serge	6814	POSTING_READ(CURBASE_IVB(pipe));
3031	serge	6815	}
2327	Serge	6816
3031	serge	6817	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		6818	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		6819	bool on)
		6820	{
		6821	struct drm_device *dev = crtc->dev;
		6822	struct drm_i915_private *dev_priv = dev->dev_private;
		6823	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6824	int pipe = intel_crtc->pipe;
		6825	int x = intel_crtc->cursor_x;
		6826	int y = intel_crtc->cursor_y;
		6827	u32 base, pos;
		6828	bool visible;
2327	Serge	6829
3031	serge	6830	pos = 0;
2327	Serge	6831
3031	serge	6832	if (on && crtc->enabled && crtc->fb) {
		6833	base = intel_crtc->cursor_addr;
		6834	if (x > (int) crtc->fb->width)
		6835	base = 0;
2327	Serge	6836
3031	serge	6837	if (y > (int) crtc->fb->height)
		6838	base = 0;
		6839	} else
		6840	base = 0;
2327	Serge	6841
3031	serge	6842	if (x < 0) {
		6843	if (x + intel_crtc->cursor_width < 0)
		6844	base = 0;
2327	Serge	6845
3031	serge	6846	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		6847	x = -x;
		6848	}
		6849	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	6850
3031	serge	6851	if (y < 0) {
		6852	if (y + intel_crtc->cursor_height < 0)
		6853	base = 0;
2327	Serge	6854
3031	serge	6855	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		6856	y = -y;
		6857	}
		6858	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	6859
3031	serge	6860	visible = base != 0;
		6861	if (!visible && !intel_crtc->cursor_visible)
		6862	return;
2327	Serge	6863
3031	serge	6864	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		6865	I915_WRITE(CURPOS_IVB(pipe), pos);
		6866	ivb_update_cursor(crtc, base);
		6867	} else {
		6868	I915_WRITE(CURPOS(pipe), pos);
		6869	if (IS_845G(dev) \|\| IS_I865G(dev))
		6870	i845_update_cursor(crtc, base);
		6871	else
		6872	i9xx_update_cursor(crtc, base);
		6873	}
		6874	}
2327	Serge	6875
3031	serge	6876	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		6877	struct drm_file *file,
		6878	uint32_t handle,
		6879	uint32_t width, uint32_t height)
		6880	{
		6881	struct drm_device *dev = crtc->dev;
		6882	struct drm_i915_private *dev_priv = dev->dev_private;
		6883	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6884	struct drm_i915_gem_object *obj;
		6885	uint32_t addr;
		6886	int ret;
2327	Serge	6887
3031	serge	6888	/* if we want to turn off the cursor ignore width and height */
		6889	if (!handle) {
		6890	DRM_DEBUG_KMS("cursor off\n");
		6891	addr = 0;
		6892	obj = NULL;
		6893	mutex_lock(&dev->struct_mutex);
		6894	goto finish;
		6895	}
2327	Serge	6896
3031	serge	6897	/* Currently we only support 64x64 cursors */
		6898	if (width != 64 \|\| height != 64) {
		6899	DRM_ERROR("we currently only support 64x64 cursors\n");
		6900	return -EINVAL;
		6901	}
2327	Serge	6902
3031	serge	6903	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		6904	if (&obj->base == NULL)
		6905	return -ENOENT;
2327	Serge	6906
3031	serge	6907	if (obj->base.size < width * height * 4) {
		6908	DRM_ERROR("buffer is to small\n");
		6909	ret = -ENOMEM;
		6910	goto fail;
		6911	}
2327	Serge	6912
3031	serge	6913	/* we only need to pin inside GTT if cursor is non-phy */
		6914	mutex_lock(&dev->struct_mutex);
		6915	if (!dev_priv->info->cursor_needs_physical) {
3746	Serge	6916	unsigned alignment;
		6917
3031	serge	6918	if (obj->tiling_mode) {
		6919	DRM_ERROR("cursor cannot be tiled\n");
		6920	ret = -EINVAL;
		6921	goto fail_locked;
		6922	}
2327	Serge	6923
3746	Serge	6924	/* Note that the w/a also requires 2 PTE of padding following
		6925	* the bo. We currently fill all unused PTE with the shadow
		6926	* page and so we should always have valid PTE following the
		6927	* cursor preventing the VT-d warning.
		6928	*/
		6929	alignment = 0;
		6930	if (need_vtd_wa(dev))
		6931	alignment = 64*1024;
		6932
		6933	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	6934	if (ret) {
		6935	DRM_ERROR("failed to move cursor bo into the GTT\n");
		6936	goto fail_locked;
		6937	}
2327	Serge	6938
3031	serge	6939	ret = i915_gem_object_put_fence(obj);
		6940	if (ret) {
		6941	DRM_ERROR("failed to release fence for cursor");
		6942	goto fail_unpin;
		6943	}
2327	Serge	6944
4104	Serge	6945	addr = i915_gem_obj_ggtt_offset(obj);
3031	serge	6946	} else {
		6947	int align = IS_I830(dev) ? 16 * 1024 : 256;
		6948	ret = i915_gem_attach_phys_object(dev, obj,
		6949	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		6950	align);
		6951	if (ret) {
		6952	DRM_ERROR("failed to attach phys object\n");
		6953	goto fail_locked;
		6954	}
		6955	addr = obj->phys_obj->handle->busaddr;
		6956	}
2327	Serge	6957
3031	serge	6958	if (IS_GEN2(dev))
		6959	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	6960
3031	serge	6961	finish:
		6962	if (intel_crtc->cursor_bo) {
		6963	if (dev_priv->info->cursor_needs_physical) {
		6964	if (intel_crtc->cursor_bo != obj)
		6965	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		6966	} else
4104	Serge	6967	i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
3031	serge	6968	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		6969	}
2327	Serge	6970
3031	serge	6971	mutex_unlock(&dev->struct_mutex);
2327	Serge	6972
3031	serge	6973	intel_crtc->cursor_addr = addr;
		6974	intel_crtc->cursor_bo = obj;
		6975	intel_crtc->cursor_width = width;
		6976	intel_crtc->cursor_height = height;
2327	Serge	6977
4104	Serge	6978	if (intel_crtc->active)
		6979	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
2327	Serge	6980
3031	serge	6981	return 0;
		6982	fail_unpin:
4104	Serge	6983	i915_gem_object_unpin_from_display_plane(obj);
3031	serge	6984	fail_locked:
		6985	mutex_unlock(&dev->struct_mutex);
		6986	fail:
		6987	drm_gem_object_unreference_unlocked(&obj->base);
		6988	return ret;
		6989	}
2327	Serge	6990
3031	serge	6991	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		6992	{
		6993	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6994
		6995	intel_crtc->cursor_x = x;
		6996	intel_crtc->cursor_y = y;
		6997
4104	Serge	6998	if (intel_crtc->active)
		6999	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3031	serge	7000
		7001	return 0;
		7002	}
		7003	#endif
		7004
2332	Serge	7005	/** Sets the color ramps on behalf of RandR */
		7006	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		7007	u16 blue, int regno)
		7008	{
		7009	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7010
2332	Serge	7011	intel_crtc->lut_r[regno] = red >> 8;
		7012	intel_crtc->lut_g[regno] = green >> 8;
		7013	intel_crtc->lut_b[regno] = blue >> 8;
		7014	}
2327	Serge	7015
2332	Serge	7016	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		7017	u16 *blue, int regno)
		7018	{
		7019	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7020
2332	Serge	7021	*red = intel_crtc->lut_r[regno] << 8;
		7022	*green = intel_crtc->lut_g[regno] << 8;
		7023	*blue = intel_crtc->lut_b[regno] << 8;
		7024	}
2327	Serge	7025
2330	Serge	7026	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		7027	u16 *blue, uint32_t start, uint32_t size)
		7028	{
		7029	int end = (start + size > 256) ? 256 : start + size, i;
		7030	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7031
2330	Serge	7032	for (i = start; i < end; i++) {
		7033	intel_crtc->lut_r[i] = red[i] >> 8;
		7034	intel_crtc->lut_g[i] = green[i] >> 8;
		7035	intel_crtc->lut_b[i] = blue[i] >> 8;
		7036	}
2327	Serge	7037
2330	Serge	7038	intel_crtc_load_lut(crtc);
		7039	}
2327	Serge	7040
2330	Serge	7041	/* VESA 640x480x72Hz mode to set on the pipe */
		7042	static struct drm_display_mode load_detect_mode = {
		7043	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		7044	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		7045	};
2327	Serge	7046
3031	serge	7047	static struct drm_framebuffer *
		7048	intel_framebuffer_create(struct drm_device *dev,
		7049	struct drm_mode_fb_cmd2 *mode_cmd,
		7050	struct drm_i915_gem_object *obj)
		7051	{
		7052	struct intel_framebuffer *intel_fb;
		7053	int ret;
2327	Serge	7054
3031	serge	7055	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		7056	if (!intel_fb) {
		7057	drm_gem_object_unreference_unlocked(&obj->base);
		7058	return ERR_PTR(-ENOMEM);
		7059	}
2327	Serge	7060
3031	serge	7061	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		7062	if (ret) {
		7063	drm_gem_object_unreference_unlocked(&obj->base);
		7064	kfree(intel_fb);
		7065	return ERR_PTR(ret);
		7066	}
2327	Serge	7067
3031	serge	7068	return &intel_fb->base;
		7069	}
2327	Serge	7070
2330	Serge	7071	static u32
		7072	intel_framebuffer_pitch_for_width(int width, int bpp)
		7073	{
		7074	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		7075	return ALIGN(pitch, 64);
		7076	}
2327	Serge	7077
2330	Serge	7078	static u32
		7079	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		7080	{
		7081	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		7082	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		7083	}
2327	Serge	7084
2330	Serge	7085	static struct drm_framebuffer *
		7086	intel_framebuffer_create_for_mode(struct drm_device *dev,
		7087	struct drm_display_mode *mode,
		7088	int depth, int bpp)
		7089	{
		7090	struct drm_i915_gem_object *obj;
3243	Serge	7091	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	7092
4104	Serge	7093	return NULL;
2330	Serge	7094	}
2327	Serge	7095
2330	Serge	7096	static struct drm_framebuffer *
		7097	mode_fits_in_fbdev(struct drm_device *dev,
		7098	struct drm_display_mode *mode)
		7099	{
		7100	struct drm_i915_private *dev_priv = dev->dev_private;
		7101	struct drm_i915_gem_object *obj;
		7102	struct drm_framebuffer *fb;
2327	Serge	7103
4280	Serge	7104	if (dev_priv->fbdev == NULL)
		7105	return NULL;
2327	Serge	7106
4280	Serge	7107	obj = dev_priv->fbdev->ifb.obj;
		7108	if (obj == NULL)
2330	Serge	7109	return NULL;
2327	Serge	7110
4280	Serge	7111	fb = &dev_priv->fbdev->ifb.base;
3031	serge	7112	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		7113	fb->bits_per_pixel))
4280	Serge	7114	return NULL;
2327	Serge	7115
3031	serge	7116	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		7117	return NULL;
		7118
4280	Serge	7119	return fb;
2330	Serge	7120	}
2327	Serge	7121
3031	serge	7122	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7123	struct drm_display_mode *mode,
		7124	struct intel_load_detect_pipe *old)
		7125	{
		7126	struct intel_crtc *intel_crtc;
3031	serge	7127	struct intel_encoder *intel_encoder =
		7128	intel_attached_encoder(connector);
2330	Serge	7129	struct drm_crtc *possible_crtc;
		7130	struct drm_encoder *encoder = &intel_encoder->base;
		7131	struct drm_crtc *crtc = NULL;
		7132	struct drm_device *dev = encoder->dev;
3031	serge	7133	struct drm_framebuffer *fb;
2330	Serge	7134	int i = -1;
2327	Serge	7135
2330	Serge	7136	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7137	connector->base.id, drm_get_connector_name(connector),
		7138	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7139
2330	Serge	7140	/*
		7141	* Algorithm gets a little messy:
		7142	*
		7143	* - if the connector already has an assigned crtc, use it (but make
		7144	* sure it's on first)
		7145	*
		7146	* - try to find the first unused crtc that can drive this connector,
		7147	* and use that if we find one
		7148	*/
2327	Serge	7149
2330	Serge	7150	/* See if we already have a CRTC for this connector */
		7151	if (encoder->crtc) {
		7152	crtc = encoder->crtc;
2327	Serge	7153
3480	Serge	7154	mutex_lock(&crtc->mutex);
		7155
3031	serge	7156	old->dpms_mode = connector->dpms;
2330	Serge	7157	old->load_detect_temp = false;
2327	Serge	7158
2330	Serge	7159	/* Make sure the crtc and connector are running */
3031	serge	7160	if (connector->dpms != DRM_MODE_DPMS_ON)
		7161	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	7162
2330	Serge	7163	return true;
		7164	}
2327	Serge	7165
2330	Serge	7166	/* Find an unused one (if possible) */
		7167	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		7168	i++;
		7169	if (!(encoder->possible_crtcs & (1 << i)))
		7170	continue;
		7171	if (!possible_crtc->enabled) {
		7172	crtc = possible_crtc;
		7173	break;
		7174	}
		7175	}
2327	Serge	7176
2330	Serge	7177	/*
		7178	* If we didn't find an unused CRTC, don't use any.
		7179	*/
		7180	if (!crtc) {
		7181	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		7182	return false;
		7183	}
2327	Serge	7184
3480	Serge	7185	mutex_lock(&crtc->mutex);
3031	serge	7186	intel_encoder->new_crtc = to_intel_crtc(crtc);
		7187	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	7188
2330	Serge	7189	intel_crtc = to_intel_crtc(crtc);
3031	serge	7190	old->dpms_mode = connector->dpms;
2330	Serge	7191	old->load_detect_temp = true;
		7192	old->release_fb = NULL;
2327	Serge	7193
2330	Serge	7194	if (!mode)
		7195	mode = &load_detect_mode;
2327	Serge	7196
2330	Serge	7197	/* We need a framebuffer large enough to accommodate all accesses
		7198	* that the plane may generate whilst we perform load detection.
		7199	* We can not rely on the fbcon either being present (we get called
		7200	* during its initialisation to detect all boot displays, or it may
		7201	* not even exist) or that it is large enough to satisfy the
		7202	* requested mode.
		7203	*/
3031	serge	7204	fb = mode_fits_in_fbdev(dev, mode);
		7205	if (fb == NULL) {
2330	Serge	7206	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	7207	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		7208	old->release_fb = fb;
2330	Serge	7209	} else
		7210	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	7211	if (IS_ERR(fb)) {
2330	Serge	7212	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3480	Serge	7213	mutex_unlock(&crtc->mutex);
3243	Serge	7214	return false;
2330	Serge	7215	}
2327	Serge	7216
3480	Serge	7217	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	7218	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		7219	if (old->release_fb)
		7220	old->release_fb->funcs->destroy(old->release_fb);
3480	Serge	7221	mutex_unlock(&crtc->mutex);
3243	Serge	7222	return false;
2330	Serge	7223	}
2327	Serge	7224
2330	Serge	7225	/* let the connector get through one full cycle before testing */
		7226	intel_wait_for_vblank(dev, intel_crtc->pipe);
		7227	return true;
		7228	}
2327	Serge	7229
3031	serge	7230	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7231	struct intel_load_detect_pipe *old)
		7232	{
3031	serge	7233	struct intel_encoder *intel_encoder =
		7234	intel_attached_encoder(connector);
2330	Serge	7235	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	7236	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	7237
2330	Serge	7238	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7239	connector->base.id, drm_get_connector_name(connector),
		7240	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7241
2330	Serge	7242	if (old->load_detect_temp) {
3031	serge	7243	to_intel_connector(connector)->new_encoder = NULL;
		7244	intel_encoder->new_crtc = NULL;
		7245	intel_set_mode(crtc, NULL, 0, 0, NULL);
		7246
3480	Serge	7247	if (old->release_fb) {
		7248	drm_framebuffer_unregister_private(old->release_fb);
		7249	drm_framebuffer_unreference(old->release_fb);
		7250	}
2327	Serge	7251
3480	Serge	7252	mutex_unlock(&crtc->mutex);
2330	Serge	7253	return;
		7254	}
2327	Serge	7255
2330	Serge	7256	/* Switch crtc and encoder back off if necessary */
3031	serge	7257	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		7258	connector->funcs->dpms(connector, old->dpms_mode);
3480	Serge	7259
		7260	mutex_unlock(&crtc->mutex);
2330	Serge	7261	}
2327	Serge	7262
2330	Serge	7263	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	7264	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		7265	struct intel_crtc_config *pipe_config)
2330	Serge	7266	{
4104	Serge	7267	struct drm_device *dev = crtc->base.dev;
2330	Serge	7268	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	7269	int pipe = pipe_config->cpu_transcoder;
2330	Serge	7270	u32 dpll = I915_READ(DPLL(pipe));
		7271	u32 fp;
		7272	intel_clock_t clock;
2327	Serge	7273
2330	Serge	7274	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		7275	fp = I915_READ(FP0(pipe));
		7276	else
		7277	fp = I915_READ(FP1(pipe));
2327	Serge	7278
2330	Serge	7279	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		7280	if (IS_PINEVIEW(dev)) {
		7281	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		7282	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7283	} else {
		7284	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		7285	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7286	}
2327	Serge	7287
2330	Serge	7288	if (!IS_GEN2(dev)) {
		7289	if (IS_PINEVIEW(dev))
		7290	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		7291	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		7292	else
		7293	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		7294	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	7295
2330	Serge	7296	switch (dpll & DPLL_MODE_MASK) {
		7297	case DPLLB_MODE_DAC_SERIAL:
		7298	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		7299	5 : 10;
		7300	break;
		7301	case DPLLB_MODE_LVDS:
		7302	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		7303	7 : 14;
		7304	break;
		7305	default:
		7306	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		7307	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	7308	pipe_config->adjusted_mode.clock = 0;
		7309	return;
2330	Serge	7310	}
2327	Serge	7311
4104	Serge	7312	if (IS_PINEVIEW(dev))
		7313	pineview_clock(96000, &clock);
		7314	else
		7315	i9xx_clock(96000, &clock);
2330	Serge	7316	} else {
		7317	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	7318
2330	Serge	7319	if (is_lvds) {
		7320	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		7321	DPLL_FPA01_P1_POST_DIV_SHIFT);
		7322	clock.p2 = 14;
2327	Serge	7323
2330	Serge	7324	if ((dpll & PLL_REF_INPUT_MASK) ==
		7325	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		7326	/* XXX: might not be 66MHz */
4104	Serge	7327	i9xx_clock(66000, &clock);
2330	Serge	7328	} else
4104	Serge	7329	i9xx_clock(48000, &clock);
2330	Serge	7330	} else {
		7331	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		7332	clock.p1 = 2;
		7333	else {
		7334	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		7335	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		7336	}
		7337	if (dpll & PLL_P2_DIVIDE_BY_4)
		7338	clock.p2 = 4;
		7339	else
		7340	clock.p2 = 2;
2327	Serge	7341
4104	Serge	7342	i9xx_clock(48000, &clock);
2330	Serge	7343	}
		7344	}
2327	Serge	7345
4104	Serge	7346	pipe_config->adjusted_mode.clock = clock.dot;
		7347	}
		7348
		7349	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		7350	struct intel_crtc_config *pipe_config)
		7351	{
		7352	struct drm_device *dev = crtc->base.dev;
		7353	struct drm_i915_private *dev_priv = dev->dev_private;
		7354	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		7355	int link_freq, repeat;
		7356	u64 clock;
		7357	u32 link_m, link_n;
		7358
		7359	repeat = pipe_config->pixel_multiplier;
		7360
		7361	/*
		7362	* The calculation for the data clock is:
		7363	* pixel_clock = ((m/n)(link_clock nr_lanes * repeat))/bpp
		7364	* But we want to avoid losing precison if possible, so:
		7365	* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
		7366	*
		7367	* and the link clock is simpler:
		7368	* link_clock = (m * link_clock * repeat) / n
2330	Serge	7369	*/
2327	Serge	7370
4104	Serge	7371	/*
		7372	* We need to get the FDI or DP link clock here to derive
		7373	* the M/N dividers.
		7374	*
		7375	* For FDI, we read it from the BIOS or use a fixed 2.7GHz.
		7376	* For DP, it's either 1.62GHz or 2.7GHz.
		7377	* We do our calculations in 10*MHz since we don't need much precison.
		7378	*/
		7379	if (pipe_config->has_pch_encoder)
		7380	link_freq = intel_fdi_link_freq(dev) * 10000;
		7381	else
		7382	link_freq = pipe_config->port_clock;
		7383
		7384	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
		7385	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
		7386
		7387	if (!link_m \|\| !link_n)
		7388	return;
		7389
		7390	clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
		7391	do_div(clock, link_n);
		7392
		7393	pipe_config->adjusted_mode.clock = clock;
2330	Serge	7394	}
2327	Serge	7395
2330	Serge	7396	/** Returns the currently programmed mode of the given pipe. */
		7397	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		7398	struct drm_crtc *crtc)
		7399	{
		7400	struct drm_i915_private *dev_priv = dev->dev_private;
		7401	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	7402	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	7403	struct drm_display_mode *mode;
4104	Serge	7404	struct intel_crtc_config pipe_config;
3243	Serge	7405	int htot = I915_READ(HTOTAL(cpu_transcoder));
		7406	int hsync = I915_READ(HSYNC(cpu_transcoder));
		7407	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		7408	int vsync = I915_READ(VSYNC(cpu_transcoder));
2327	Serge	7409
2330	Serge	7410	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		7411	if (!mode)
		7412	return NULL;
		7413
4104	Serge	7414	/*
		7415	* Construct a pipe_config sufficient for getting the clock info
		7416	* back out of crtc_clock_get.
		7417	*
		7418	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		7419	* to use a real value here instead.
		7420	*/
		7421	pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
		7422	pipe_config.pixel_multiplier = 1;
		7423	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		7424
		7425	mode->clock = pipe_config.adjusted_mode.clock;
2330	Serge	7426	mode->hdisplay = (htot & 0xffff) + 1;
		7427	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		7428	mode->hsync_start = (hsync & 0xffff) + 1;
		7429	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		7430	mode->vdisplay = (vtot & 0xffff) + 1;
		7431	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		7432	mode->vsync_start = (vsync & 0xffff) + 1;
		7433	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		7434
		7435	drm_mode_set_name(mode);
		7436
		7437	return mode;
		7438	}
		7439
2327	Serge	7440	static void intel_increase_pllclock(struct drm_crtc *crtc)
		7441	{
		7442	struct drm_device *dev = crtc->dev;
		7443	drm_i915_private_t *dev_priv = dev->dev_private;
		7444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7445	int pipe = intel_crtc->pipe;
		7446	int dpll_reg = DPLL(pipe);
		7447	int dpll;
		7448
		7449	if (HAS_PCH_SPLIT(dev))
		7450	return;
		7451
		7452	if (!dev_priv->lvds_downclock_avail)
		7453	return;
		7454
		7455	dpll = I915_READ(dpll_reg);
		7456	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		7457	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		7458
3031	serge	7459	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7460
		7461	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		7462	I915_WRITE(dpll_reg, dpll);
		7463	intel_wait_for_vblank(dev, pipe);
		7464
		7465	dpll = I915_READ(dpll_reg);
		7466	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		7467	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		7468	}
		7469	}
		7470
3031	serge	7471	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		7472	{
		7473	struct drm_device *dev = crtc->dev;
		7474	drm_i915_private_t *dev_priv = dev->dev_private;
		7475	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7476
3031	serge	7477	if (HAS_PCH_SPLIT(dev))
		7478	return;
2327	Serge	7479
3031	serge	7480	if (!dev_priv->lvds_downclock_avail)
		7481	return;
2327	Serge	7482
3031	serge	7483	/*
		7484	* Since this is called by a timer, we should never get here in
		7485	* the manual case.
		7486	*/
		7487	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		7488	int pipe = intel_crtc->pipe;
		7489	int dpll_reg = DPLL(pipe);
		7490	int dpll;
2327	Serge	7491
3031	serge	7492	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	7493
3031	serge	7494	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7495
3031	serge	7496	dpll = I915_READ(dpll_reg);
		7497	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		7498	I915_WRITE(dpll_reg, dpll);
		7499	intel_wait_for_vblank(dev, pipe);
		7500	dpll = I915_READ(dpll_reg);
		7501	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		7502	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		7503	}
2327	Serge	7504
3031	serge	7505	}
2327	Serge	7506
3031	serge	7507	void intel_mark_busy(struct drm_device *dev)
		7508	{
4104	Serge	7509	struct drm_i915_private *dev_priv = dev->dev_private;
		7510
		7511	hsw_package_c8_gpu_busy(dev_priv);
		7512	i915_update_gfx_val(dev_priv);
3031	serge	7513	}
2327	Serge	7514
3031	serge	7515	void intel_mark_idle(struct drm_device *dev)
		7516	{
4104	Serge	7517	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7518	struct drm_crtc *crtc;
2327	Serge	7519
4104	Serge	7520	hsw_package_c8_gpu_idle(dev_priv);
		7521
3031	serge	7522	if (!i915_powersave)
		7523	return;
2327	Serge	7524
3031	serge	7525	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7526	if (!crtc->fb)
		7527	continue;
2327	Serge	7528
3480	Serge	7529	intel_decrease_pllclock(crtc);
3031	serge	7530	}
		7531	}
2327	Serge	7532
4104	Serge	7533	void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
		7534	struct intel_ring_buffer *ring)
3031	serge	7535	{
		7536	struct drm_device *dev = obj->base.dev;
		7537	struct drm_crtc *crtc;
2327	Serge	7538
3031	serge	7539	if (!i915_powersave)
		7540	return;
2327	Serge	7541
3031	serge	7542	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7543	if (!crtc->fb)
		7544	continue;
2327	Serge	7545
4104	Serge	7546	if (to_intel_framebuffer(crtc->fb)->obj != obj)
		7547	continue;
		7548
3480	Serge	7549	intel_increase_pllclock(crtc);
4104	Serge	7550	if (ring && intel_fbc_enabled(dev))
		7551	ring->fbc_dirty = true;
3031	serge	7552	}
		7553	}
2327	Serge	7554
2330	Serge	7555	static void intel_crtc_destroy(struct drm_crtc *crtc)
		7556	{
		7557	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7558	struct drm_device *dev = crtc->dev;
		7559	struct intel_unpin_work *work;
		7560	unsigned long flags;
2327	Serge	7561
2330	Serge	7562	spin_lock_irqsave(&dev->event_lock, flags);
		7563	work = intel_crtc->unpin_work;
		7564	intel_crtc->unpin_work = NULL;
		7565	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7566
2330	Serge	7567	if (work) {
4293	Serge	7568	cancel_work_sync(&work->work);
2330	Serge	7569	kfree(work);
		7570	}
2327	Serge	7571
2330	Serge	7572	drm_crtc_cleanup(crtc);
2327	Serge	7573
2330	Serge	7574	kfree(intel_crtc);
		7575	}
2327	Serge	7576
3031	serge	7577	#if 0
		7578	static void intel_unpin_work_fn(struct work_struct *__work)
		7579	{
		7580	struct intel_unpin_work *work =
		7581	container_of(__work, struct intel_unpin_work, work);
3243	Serge	7582	struct drm_device *dev = work->crtc->dev;
2327	Serge	7583
3243	Serge	7584	mutex_lock(&dev->struct_mutex);
3031	serge	7585	intel_unpin_fb_obj(work->old_fb_obj);
		7586	drm_gem_object_unreference(&work->pending_flip_obj->base);
		7587	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	7588
3243	Serge	7589	intel_update_fbc(dev);
		7590	mutex_unlock(&dev->struct_mutex);
		7591
		7592	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		7593	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		7594
3031	serge	7595	kfree(work);
		7596	}
2327	Serge	7597
3031	serge	7598	static void do_intel_finish_page_flip(struct drm_device *dev,
		7599	struct drm_crtc *crtc)
		7600	{
		7601	drm_i915_private_t *dev_priv = dev->dev_private;
		7602	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7603	struct intel_unpin_work *work;
		7604	unsigned long flags;
2327	Serge	7605
3031	serge	7606	/* Ignore early vblank irqs */
		7607	if (intel_crtc == NULL)
		7608	return;
2327	Serge	7609
3031	serge	7610	spin_lock_irqsave(&dev->event_lock, flags);
		7611	work = intel_crtc->unpin_work;
3243	Serge	7612
		7613	/* Ensure we don't miss a work->pending update ... */
		7614	smp_rmb();
		7615
		7616	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	7617	spin_unlock_irqrestore(&dev->event_lock, flags);
		7618	return;
		7619	}
2327	Serge	7620
3243	Serge	7621	/* and that the unpin work is consistent wrt ->pending. */
		7622	smp_rmb();
		7623
3031	serge	7624	intel_crtc->unpin_work = NULL;
2327	Serge	7625
3243	Serge	7626	if (work->event)
		7627	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	7628
3031	serge	7629	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7630
3031	serge	7631	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7632
3480	Serge	7633	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	7634
3243	Serge	7635	queue_work(dev_priv->wq, &work->work);
		7636
3031	serge	7637	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		7638	}
2327	Serge	7639
3031	serge	7640	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		7641	{
		7642	drm_i915_private_t *dev_priv = dev->dev_private;
		7643	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	7644
3031	serge	7645	do_intel_finish_page_flip(dev, crtc);
		7646	}
2327	Serge	7647
3031	serge	7648	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		7649	{
		7650	drm_i915_private_t *dev_priv = dev->dev_private;
		7651	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	7652
3031	serge	7653	do_intel_finish_page_flip(dev, crtc);
		7654	}
2327	Serge	7655
3031	serge	7656	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		7657	{
		7658	drm_i915_private_t *dev_priv = dev->dev_private;
		7659	struct intel_crtc *intel_crtc =
		7660	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		7661	unsigned long flags;
2327	Serge	7662
3243	Serge	7663	/* NB: An MMIO update of the plane base pointer will also
		7664	* generate a page-flip completion irq, i.e. every modeset
		7665	* is also accompanied by a spurious intel_prepare_page_flip().
		7666	*/
3031	serge	7667	spin_lock_irqsave(&dev->event_lock, flags);
3243	Serge	7668	if (intel_crtc->unpin_work)
		7669	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	7670	spin_unlock_irqrestore(&dev->event_lock, flags);
		7671	}
2327	Serge	7672
3243	Serge	7673	inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
		7674	{
		7675	/* Ensure that the work item is consistent when activating it ... */
		7676	smp_wmb();
		7677	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		7678	/* and that it is marked active as soon as the irq could fire. */
		7679	smp_wmb();
		7680	}
		7681
3031	serge	7682	static int intel_gen2_queue_flip(struct drm_device *dev,
		7683	struct drm_crtc *crtc,
		7684	struct drm_framebuffer *fb,
4104	Serge	7685	struct drm_i915_gem_object *obj,
		7686	uint32_t flags)
3031	serge	7687	{
		7688	struct drm_i915_private *dev_priv = dev->dev_private;
		7689	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7690	u32 flip_mask;
		7691	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7692	int ret;
2327	Serge	7693
3031	serge	7694	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7695	if (ret)
		7696	goto err;
2327	Serge	7697
3031	serge	7698	ret = intel_ring_begin(ring, 6);
		7699	if (ret)
		7700	goto err_unpin;
2327	Serge	7701
3031	serge	7702	/* Can't queue multiple flips, so wait for the previous
		7703	* one to finish before executing the next.
		7704	*/
		7705	if (intel_crtc->plane)
		7706	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7707	else
		7708	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7709	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7710	intel_ring_emit(ring, MI_NOOP);
		7711	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7712	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7713	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7714	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7715	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	7716
		7717	intel_mark_page_flip_active(intel_crtc);
3031	serge	7718	intel_ring_advance(ring);
		7719	return 0;
2327	Serge	7720
3031	serge	7721	err_unpin:
		7722	intel_unpin_fb_obj(obj);
		7723	err:
		7724	return ret;
		7725	}
2327	Serge	7726
3031	serge	7727	static int intel_gen3_queue_flip(struct drm_device *dev,
		7728	struct drm_crtc *crtc,
		7729	struct drm_framebuffer *fb,
4104	Serge	7730	struct drm_i915_gem_object *obj,
		7731	uint32_t flags)
3031	serge	7732	{
		7733	struct drm_i915_private *dev_priv = dev->dev_private;
		7734	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7735	u32 flip_mask;
		7736	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7737	int ret;
2327	Serge	7738
3031	serge	7739	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7740	if (ret)
		7741	goto err;
2327	Serge	7742
3031	serge	7743	ret = intel_ring_begin(ring, 6);
		7744	if (ret)
		7745	goto err_unpin;
2327	Serge	7746
3031	serge	7747	if (intel_crtc->plane)
		7748	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7749	else
		7750	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7751	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7752	intel_ring_emit(ring, MI_NOOP);
		7753	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		7754	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7755	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7756	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7757	intel_ring_emit(ring, MI_NOOP);
2327	Serge	7758
3243	Serge	7759	intel_mark_page_flip_active(intel_crtc);
3031	serge	7760	intel_ring_advance(ring);
		7761	return 0;
2327	Serge	7762
3031	serge	7763	err_unpin:
		7764	intel_unpin_fb_obj(obj);
		7765	err:
		7766	return ret;
		7767	}
2327	Serge	7768
3031	serge	7769	static int intel_gen4_queue_flip(struct drm_device *dev,
		7770	struct drm_crtc *crtc,
		7771	struct drm_framebuffer *fb,
4104	Serge	7772	struct drm_i915_gem_object *obj,
		7773	uint32_t flags)
3031	serge	7774	{
		7775	struct drm_i915_private *dev_priv = dev->dev_private;
		7776	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7777	uint32_t pf, pipesrc;
		7778	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7779	int ret;
2327	Serge	7780
3031	serge	7781	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7782	if (ret)
		7783	goto err;
2327	Serge	7784
3031	serge	7785	ret = intel_ring_begin(ring, 4);
		7786	if (ret)
		7787	goto err_unpin;
2327	Serge	7788
3031	serge	7789	/* i965+ uses the linear or tiled offsets from the
		7790	* Display Registers (which do not change across a page-flip)
		7791	* so we need only reprogram the base address.
		7792	*/
		7793	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7794	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7795	intel_ring_emit(ring, fb->pitches[0]);
		7796	intel_ring_emit(ring,
4104	Serge	7797	(i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) \|
3031	serge	7798	obj->tiling_mode);
2327	Serge	7799
3031	serge	7800	/* XXX Enabling the panel-fitter across page-flip is so far
		7801	* untested on non-native modes, so ignore it for now.
		7802	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		7803	*/
		7804	pf = 0;
		7805	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7806	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7807
		7808	intel_mark_page_flip_active(intel_crtc);
3031	serge	7809	intel_ring_advance(ring);
		7810	return 0;
2327	Serge	7811
3031	serge	7812	err_unpin:
		7813	intel_unpin_fb_obj(obj);
		7814	err:
		7815	return ret;
		7816	}
2327	Serge	7817
3031	serge	7818	static int intel_gen6_queue_flip(struct drm_device *dev,
		7819	struct drm_crtc *crtc,
		7820	struct drm_framebuffer *fb,
4104	Serge	7821	struct drm_i915_gem_object *obj,
		7822	uint32_t flags)
3031	serge	7823	{
		7824	struct drm_i915_private *dev_priv = dev->dev_private;
		7825	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7826	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7827	uint32_t pf, pipesrc;
		7828	int ret;
2327	Serge	7829
3031	serge	7830	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7831	if (ret)
		7832	goto err;
2327	Serge	7833
3031	serge	7834	ret = intel_ring_begin(ring, 4);
		7835	if (ret)
		7836	goto err_unpin;
2327	Serge	7837
3031	serge	7838	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7839	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7840	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
4104	Serge	7841	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	7842
3031	serge	7843	/* Contrary to the suggestions in the documentation,
		7844	* "Enable Panel Fitter" does not seem to be required when page
		7845	* flipping with a non-native mode, and worse causes a normal
		7846	* modeset to fail.
		7847	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		7848	*/
		7849	pf = 0;
		7850	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7851	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7852
		7853	intel_mark_page_flip_active(intel_crtc);
3031	serge	7854	intel_ring_advance(ring);
		7855	return 0;
2327	Serge	7856
3031	serge	7857	err_unpin:
		7858	intel_unpin_fb_obj(obj);
		7859	err:
		7860	return ret;
		7861	}
2327	Serge	7862
3031	serge	7863	static int intel_gen7_queue_flip(struct drm_device *dev,
		7864	struct drm_crtc *crtc,
		7865	struct drm_framebuffer *fb,
4104	Serge	7866	struct drm_i915_gem_object *obj,
		7867	uint32_t flags)
3031	serge	7868	{
		7869	struct drm_i915_private *dev_priv = dev->dev_private;
		7870	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	7871	struct intel_ring_buffer *ring;
3031	serge	7872	uint32_t plane_bit = 0;
4104	Serge	7873	int len, ret;
2327	Serge	7874
4104	Serge	7875	ring = obj->ring;
		7876	if (IS_VALLEYVIEW(dev) \|\| ring == NULL \|\| ring->id != RCS)
		7877	ring = &dev_priv->ring[BCS];
		7878
3031	serge	7879	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7880	if (ret)
		7881	goto err;
2327	Serge	7882
3031	serge	7883	switch(intel_crtc->plane) {
		7884	case PLANE_A:
		7885	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		7886	break;
		7887	case PLANE_B:
		7888	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		7889	break;
		7890	case PLANE_C:
		7891	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		7892	break;
		7893	default:
		7894	WARN_ONCE(1, "unknown plane in flip command\n");
		7895	ret = -ENODEV;
		7896	goto err_unpin;
		7897	}
2327	Serge	7898
4104	Serge	7899	len = 4;
		7900	if (ring->id == RCS)
		7901	len += 6;
		7902
		7903	ret = intel_ring_begin(ring, len);
3031	serge	7904	if (ret)
		7905	goto err_unpin;
2327	Serge	7906
4104	Serge	7907	/* Unmask the flip-done completion message. Note that the bspec says that
		7908	* we should do this for both the BCS and RCS, and that we must not unmask
		7909	* more than one flip event at any time (or ensure that one flip message
		7910	* can be sent by waiting for flip-done prior to queueing new flips).
		7911	* Experimentation says that BCS works despite DERRMR masking all
		7912	* flip-done completion events and that unmasking all planes at once
		7913	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		7914	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		7915	*/
		7916	if (ring->id == RCS) {
		7917	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		7918	intel_ring_emit(ring, DERRMR);
		7919	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		7920	DERRMR_PIPEB_PRI_FLIP_DONE \|
		7921	DERRMR_PIPEC_PRI_FLIP_DONE));
		7922	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
		7923	intel_ring_emit(ring, DERRMR);
		7924	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
		7925	}
		7926
3031	serge	7927	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		7928	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
4104	Serge	7929	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7930	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	7931
		7932	intel_mark_page_flip_active(intel_crtc);
3031	serge	7933	intel_ring_advance(ring);
		7934	return 0;
2327	Serge	7935
3031	serge	7936	err_unpin:
		7937	intel_unpin_fb_obj(obj);
		7938	err:
		7939	return ret;
		7940	}
2327	Serge	7941
3031	serge	7942	static int intel_default_queue_flip(struct drm_device *dev,
		7943	struct drm_crtc *crtc,
		7944	struct drm_framebuffer *fb,
4104	Serge	7945	struct drm_i915_gem_object *obj,
		7946	uint32_t flags)
3031	serge	7947	{
		7948	return -ENODEV;
		7949	}
2327	Serge	7950
3031	serge	7951	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		7952	struct drm_framebuffer *fb,
4104	Serge	7953	struct drm_pending_vblank_event *event,
		7954	uint32_t page_flip_flags)
3031	serge	7955	{
		7956	struct drm_device *dev = crtc->dev;
		7957	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	7958	struct drm_framebuffer *old_fb = crtc->fb;
		7959	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
3031	serge	7960	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7961	struct intel_unpin_work *work;
		7962	unsigned long flags;
		7963	int ret;
2327	Serge	7964
3031	serge	7965	/* Can't change pixel format via MI display flips. */
		7966	if (fb->pixel_format != crtc->fb->pixel_format)
		7967	return -EINVAL;
2327	Serge	7968
3031	serge	7969	/*
		7970	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		7971	* Note that pitch changes could also affect these register.
		7972	*/
		7973	if (INTEL_INFO(dev)->gen > 3 &&
		7974	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		7975	fb->pitches[0] != crtc->fb->pitches[0]))
		7976	return -EINVAL;
2327	Serge	7977
3031	serge	7978	work = kzalloc(sizeof *work, GFP_KERNEL);
		7979	if (work == NULL)
		7980	return -ENOMEM;
2327	Serge	7981
3031	serge	7982	work->event = event;
3243	Serge	7983	work->crtc = crtc;
3480	Serge	7984	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
3031	serge	7985	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	7986
3031	serge	7987	ret = drm_vblank_get(dev, intel_crtc->pipe);
		7988	if (ret)
		7989	goto free_work;
2327	Serge	7990
3031	serge	7991	/* We borrow the event spin lock for protecting unpin_work */
		7992	spin_lock_irqsave(&dev->event_lock, flags);
		7993	if (intel_crtc->unpin_work) {
		7994	spin_unlock_irqrestore(&dev->event_lock, flags);
		7995	kfree(work);
		7996	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7997
3031	serge	7998	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		7999	return -EBUSY;
		8000	}
		8001	intel_crtc->unpin_work = work;
		8002	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	8003
3243	Serge	8004	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		8005	flush_workqueue(dev_priv->wq);
		8006
3031	serge	8007	ret = i915_mutex_lock_interruptible(dev);
		8008	if (ret)
		8009	goto cleanup;
2327	Serge	8010
3031	serge	8011	/* Reference the objects for the scheduled work. */
		8012	drm_gem_object_reference(&work->old_fb_obj->base);
		8013	drm_gem_object_reference(&obj->base);
2327	Serge	8014
3031	serge	8015	crtc->fb = fb;
2327	Serge	8016
3031	serge	8017	work->pending_flip_obj = obj;
2327	Serge	8018
3031	serge	8019	work->enable_stall_check = true;
		8020
3243	Serge	8021	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	8022	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	8023
4104	Serge	8024	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
3031	serge	8025	if (ret)
		8026	goto cleanup_pending;
		8027
		8028	intel_disable_fbc(dev);
4104	Serge	8029	intel_mark_fb_busy(obj, NULL);
3031	serge	8030	mutex_unlock(&dev->struct_mutex);
		8031
		8032	trace_i915_flip_request(intel_crtc->plane, obj);
		8033
		8034	return 0;
		8035
		8036	cleanup_pending:
3243	Serge	8037	atomic_dec(&intel_crtc->unpin_work_count);
3480	Serge	8038	crtc->fb = old_fb;
3031	serge	8039	drm_gem_object_unreference(&work->old_fb_obj->base);
		8040	drm_gem_object_unreference(&obj->base);
		8041	mutex_unlock(&dev->struct_mutex);
		8042
		8043	cleanup:
		8044	spin_lock_irqsave(&dev->event_lock, flags);
		8045	intel_crtc->unpin_work = NULL;
		8046	spin_unlock_irqrestore(&dev->event_lock, flags);
		8047
		8048	drm_vblank_put(dev, intel_crtc->pipe);
		8049	free_work:
		8050	kfree(work);
		8051
		8052	return ret;
		8053	}
		8054	#endif
		8055
		8056	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		8057	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		8058	.load_lut = intel_crtc_load_lut,
		8059	};
		8060
		8061	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		8062	struct drm_crtc *crtc)
		8063	{
		8064	struct drm_device *dev;
		8065	struct drm_crtc *tmp;
		8066	int crtc_mask = 1;
		8067
		8068	WARN(!crtc, "checking null crtc?\n");
		8069
		8070	dev = crtc->dev;
		8071
		8072	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		8073	if (tmp == crtc)
		8074	break;
		8075	crtc_mask <<= 1;
		8076	}
		8077
		8078	if (encoder->possible_crtcs & crtc_mask)
		8079	return true;
		8080	return false;
		8081	}
		8082
		8083	/**
		8084	* intel_modeset_update_staged_output_state
		8085	*
		8086	* Updates the staged output configuration state, e.g. after we've read out the
		8087	* current hw state.
		8088	*/
		8089	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		8090	{
		8091	struct intel_encoder *encoder;
		8092	struct intel_connector *connector;
		8093
		8094	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8095	base.head) {
		8096	connector->new_encoder =
		8097	to_intel_encoder(connector->base.encoder);
		8098	}
		8099
		8100	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8101	base.head) {
		8102	encoder->new_crtc =
		8103	to_intel_crtc(encoder->base.crtc);
		8104	}
		8105	}
		8106
		8107	/**
		8108	* intel_modeset_commit_output_state
		8109	*
		8110	* This function copies the stage display pipe configuration to the real one.
		8111	*/
		8112	static void intel_modeset_commit_output_state(struct drm_device *dev)
		8113	{
		8114	struct intel_encoder *encoder;
		8115	struct intel_connector *connector;
		8116
		8117	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8118	base.head) {
		8119	connector->base.encoder = &connector->new_encoder->base;
		8120	}
		8121
		8122	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8123	base.head) {
		8124	encoder->base.crtc = &encoder->new_crtc->base;
		8125	}
		8126	}
		8127
4104	Serge	8128	static void
		8129	connected_sink_compute_bpp(struct intel_connector * connector,
		8130	struct intel_crtc_config *pipe_config)
		8131	{
		8132	int bpp = pipe_config->pipe_bpp;
		8133
		8134	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		8135	connector->base.base.id,
		8136	drm_get_connector_name(&connector->base));
		8137
		8138	/* Don't use an invalid EDID bpc value */
		8139	if (connector->base.display_info.bpc &&
		8140	connector->base.display_info.bpc * 3 < bpp) {
		8141	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		8142	bpp, connector->base.display_info.bpc*3);
		8143	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		8144	}
		8145
		8146	/* Clamp bpp to 8 on screens without EDID 1.4 */
		8147	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		8148	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
		8149	bpp);
		8150	pipe_config->pipe_bpp = 24;
		8151	}
		8152	}
		8153
3746	Serge	8154	static int
4104	Serge	8155	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
3746	Serge	8156	struct drm_framebuffer *fb,
		8157	struct intel_crtc_config *pipe_config)
		8158	{
4104	Serge	8159	struct drm_device *dev = crtc->base.dev;
		8160	struct intel_connector *connector;
3746	Serge	8161	int bpp;
		8162
		8163	switch (fb->pixel_format) {
		8164	case DRM_FORMAT_C8:
		8165	bpp = 83; / since we go through a colormap */
		8166	break;
		8167	case DRM_FORMAT_XRGB1555:
		8168	case DRM_FORMAT_ARGB1555:
		8169	/* checked in intel_framebuffer_init already */
		8170	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		8171	return -EINVAL;
		8172	case DRM_FORMAT_RGB565:
		8173	bpp = 63; / min is 18bpp */
		8174	break;
		8175	case DRM_FORMAT_XBGR8888:
		8176	case DRM_FORMAT_ABGR8888:
		8177	/* checked in intel_framebuffer_init already */
		8178	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8179	return -EINVAL;
		8180	case DRM_FORMAT_XRGB8888:
		8181	case DRM_FORMAT_ARGB8888:
		8182	bpp = 8*3;
		8183	break;
		8184	case DRM_FORMAT_XRGB2101010:
		8185	case DRM_FORMAT_ARGB2101010:
		8186	case DRM_FORMAT_XBGR2101010:
		8187	case DRM_FORMAT_ABGR2101010:
		8188	/* checked in intel_framebuffer_init already */
		8189	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8190	return -EINVAL;
		8191	bpp = 10*3;
		8192	break;
		8193	/* TODO: gen4+ supports 16 bpc floating point, too. */
		8194	default:
		8195	DRM_DEBUG_KMS("unsupported depth\n");
		8196	return -EINVAL;
		8197	}
		8198
		8199	pipe_config->pipe_bpp = bpp;
		8200
		8201	/* Clamp display bpp to EDID value */
		8202	list_for_each_entry(connector, &dev->mode_config.connector_list,
4104	Serge	8203	base.head) {
		8204	if (!connector->new_encoder \|\|
		8205	connector->new_encoder->new_crtc != crtc)
3746	Serge	8206	continue;
		8207
4104	Serge	8208	connected_sink_compute_bpp(connector, pipe_config);
3746	Serge	8209	}
		8210
		8211	return bpp;
		8212	}
		8213
4104	Serge	8214	static void intel_dump_pipe_config(struct intel_crtc *crtc,
		8215	struct intel_crtc_config *pipe_config,
		8216	const char *context)
		8217	{
		8218	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		8219	context, pipe_name(crtc->pipe));
		8220
		8221	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		8222	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		8223	pipe_config->pipe_bpp, pipe_config->dither);
		8224	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		8225	pipe_config->has_pch_encoder,
		8226	pipe_config->fdi_lanes,
		8227	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		8228	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		8229	pipe_config->fdi_m_n.tu);
		8230	DRM_DEBUG_KMS("requested mode:\n");
		8231	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
		8232	DRM_DEBUG_KMS("adjusted mode:\n");
		8233	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
		8234	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		8235	pipe_config->gmch_pfit.control,
		8236	pipe_config->gmch_pfit.pgm_ratios,
		8237	pipe_config->gmch_pfit.lvds_border_bits);
		8238	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		8239	pipe_config->pch_pfit.pos,
		8240	pipe_config->pch_pfit.size,
		8241	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		8242	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
		8243	}
		8244
		8245	static bool check_encoder_cloning(struct drm_crtc *crtc)
		8246	{
		8247	int num_encoders = 0;
		8248	bool uncloneable_encoders = false;
		8249	struct intel_encoder *encoder;
		8250
		8251	list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
		8252	base.head) {
		8253	if (&encoder->new_crtc->base != crtc)
		8254	continue;
		8255
		8256	num_encoders++;
		8257	if (!encoder->cloneable)
		8258	uncloneable_encoders = true;
		8259	}
		8260
		8261	return !(num_encoders > 1 && uncloneable_encoders);
		8262	}
		8263
3746	Serge	8264	static struct intel_crtc_config *
		8265	intel_modeset_pipe_config(struct drm_crtc *crtc,
		8266	struct drm_framebuffer *fb,
3031	serge	8267	struct drm_display_mode *mode)
		8268	{
		8269	struct drm_device *dev = crtc->dev;
		8270	struct intel_encoder *encoder;
3746	Serge	8271	struct intel_crtc_config *pipe_config;
4104	Serge	8272	int plane_bpp, ret = -EINVAL;
		8273	bool retry = true;
3031	serge	8274
4104	Serge	8275	if (!check_encoder_cloning(crtc)) {
		8276	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		8277	return ERR_PTR(-EINVAL);
		8278	}
		8279
3746	Serge	8280	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		8281	if (!pipe_config)
3031	serge	8282	return ERR_PTR(-ENOMEM);
		8283
3746	Serge	8284	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		8285	drm_mode_copy(&pipe_config->requested_mode, mode);
4104	Serge	8286	pipe_config->cpu_transcoder =
		8287	(enum transcoder) to_intel_crtc(crtc)->pipe;
		8288	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
3746	Serge	8289
4104	Serge	8290	/*
		8291	* Sanitize sync polarity flags based on requested ones. If neither
		8292	* positive or negative polarity is requested, treat this as meaning
		8293	* negative polarity.
		8294	*/
		8295	if (!(pipe_config->adjusted_mode.flags &
		8296	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
		8297	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		8298
		8299	if (!(pipe_config->adjusted_mode.flags &
		8300	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
		8301	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		8302
		8303	/* Compute a starting value for pipe_config->pipe_bpp taking the source
		8304	* plane pixel format and any sink constraints into account. Returns the
		8305	* source plane bpp so that dithering can be selected on mismatches
		8306	* after encoders and crtc also have had their say. */
		8307	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		8308	fb, pipe_config);
3746	Serge	8309	if (plane_bpp < 0)
		8310	goto fail;
		8311
4104	Serge	8312	encoder_retry:
		8313	/* Ensure the port clock defaults are reset when retrying. */
		8314	pipe_config->port_clock = 0;
		8315	pipe_config->pixel_multiplier = 1;
		8316
		8317	/* Fill in default crtc timings, allow encoders to overwrite them. */
		8318	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
		8319
3031	serge	8320	/* Pass our mode to the connectors and the CRTC to give them a chance to
		8321	* adjust it according to limitations or connector properties, and also
		8322	* a chance to reject the mode entirely.
2330	Serge	8323	*/
3031	serge	8324	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8325	base.head) {
2327	Serge	8326
3031	serge	8327	if (&encoder->new_crtc->base != crtc)
		8328	continue;
3746	Serge	8329
		8330	if (!(encoder->compute_config(encoder, pipe_config))) {
		8331	DRM_DEBUG_KMS("Encoder config failure\n");
		8332	goto fail;
		8333	}
		8334	}
		8335
4104	Serge	8336	/* Set default port clock if not overwritten by the encoder. Needs to be
		8337	* done afterwards in case the encoder adjusts the mode. */
		8338	if (!pipe_config->port_clock)
		8339	pipe_config->port_clock = pipe_config->adjusted_mode.clock;
2327	Serge	8340
4104	Serge	8341	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		8342	if (ret < 0) {
3031	serge	8343	DRM_DEBUG_KMS("CRTC fixup failed\n");
		8344	goto fail;
		8345	}
2327	Serge	8346
4104	Serge	8347	if (ret == RETRY) {
		8348	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		8349	ret = -EINVAL;
		8350	goto fail;
		8351	}
		8352
		8353	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		8354	retry = false;
		8355	goto encoder_retry;
		8356	}
		8357
3746	Serge	8358	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		8359	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		8360	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		8361
		8362	return pipe_config;
3031	serge	8363	fail:
3746	Serge	8364	kfree(pipe_config);
4104	Serge	8365	return ERR_PTR(ret);
3031	serge	8366	}
2327	Serge	8367
3031	serge	8368	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		8369	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		8370	static void
		8371	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		8372	unsigned prepare_pipes, unsigned disable_pipes)
		8373	{
		8374	struct intel_crtc *intel_crtc;
		8375	struct drm_device *dev = crtc->dev;
		8376	struct intel_encoder *encoder;
		8377	struct intel_connector *connector;
		8378	struct drm_crtc *tmp_crtc;
		8379
		8380	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		8381
		8382	/* Check which crtcs have changed outputs connected to them, these need
		8383	* to be part of the prepare_pipes mask. We don't (yet) support global
		8384	* modeset across multiple crtcs, so modeset_pipes will only have one
		8385	* bit set at most. */
		8386	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8387	base.head) {
		8388	if (connector->base.encoder == &connector->new_encoder->base)
		8389	continue;
		8390
		8391	if (connector->base.encoder) {
		8392	tmp_crtc = connector->base.encoder->crtc;
		8393
		8394	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8395	}
		8396
		8397	if (connector->new_encoder)
		8398	*prepare_pipes \|=
		8399	1 << connector->new_encoder->new_crtc->pipe;
		8400	}
		8401
		8402	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8403	base.head) {
		8404	if (encoder->base.crtc == &encoder->new_crtc->base)
		8405	continue;
		8406
		8407	if (encoder->base.crtc) {
		8408	tmp_crtc = encoder->base.crtc;
		8409
		8410	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8411	}
		8412
		8413	if (encoder->new_crtc)
		8414	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		8415	}
		8416
		8417	/* Check for any pipes that will be fully disabled ... */
		8418	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8419	base.head) {
		8420	bool used = false;
		8421
		8422	/* Don't try to disable disabled crtcs. */
		8423	if (!intel_crtc->base.enabled)
		8424	continue;
		8425
		8426	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8427	base.head) {
		8428	if (encoder->new_crtc == intel_crtc)
		8429	used = true;
		8430	}
		8431
		8432	if (!used)
		8433	*disable_pipes \|= 1 << intel_crtc->pipe;
		8434	}
		8435
		8436
		8437	/* set_mode is also used to update properties on life display pipes. */
		8438	intel_crtc = to_intel_crtc(crtc);
		8439	if (crtc->enabled)
		8440	*prepare_pipes \|= 1 << intel_crtc->pipe;
		8441
3746	Serge	8442	/*
		8443	* For simplicity do a full modeset on any pipe where the output routing
		8444	* changed. We could be more clever, but that would require us to be
		8445	* more careful with calling the relevant encoder->mode_set functions.
		8446	*/
3031	serge	8447	if (*prepare_pipes)
		8448	modeset_pipes = prepare_pipes;
		8449
		8450	/* ... and mask these out. */
		8451	modeset_pipes &= ~(disable_pipes);
		8452	prepare_pipes &= ~(disable_pipes);
3746	Serge	8453
		8454	/*
		8455	* HACK: We don't (yet) fully support global modesets. intel_set_config
		8456	* obies this rule, but the modeset restore mode of
		8457	* intel_modeset_setup_hw_state does not.
		8458	*/
		8459	*modeset_pipes &= 1 << intel_crtc->pipe;
		8460	*prepare_pipes &= 1 << intel_crtc->pipe;
4104	Serge	8461
		8462	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		8463	modeset_pipes, prepare_pipes, *disable_pipes);
2330	Serge	8464	}
2327	Serge	8465
3031	serge	8466	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	8467	{
3031	serge	8468	struct drm_encoder *encoder;
2330	Serge	8469	struct drm_device *dev = crtc->dev;
2327	Serge	8470
3031	serge	8471	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		8472	if (encoder->crtc == crtc)
		8473	return true;
		8474
		8475	return false;
		8476	}
		8477
		8478	static void
		8479	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		8480	{
		8481	struct intel_encoder *intel_encoder;
		8482	struct intel_crtc *intel_crtc;
		8483	struct drm_connector *connector;
		8484
		8485	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		8486	base.head) {
		8487	if (!intel_encoder->base.crtc)
		8488	continue;
		8489
		8490	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		8491
		8492	if (prepare_pipes & (1 << intel_crtc->pipe))
		8493	intel_encoder->connectors_active = false;
		8494	}
		8495
		8496	intel_modeset_commit_output_state(dev);
		8497
		8498	/* Update computed state. */
		8499	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8500	base.head) {
		8501	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		8502	}
		8503
		8504	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8505	if (!connector->encoder \|\| !connector->encoder->crtc)
		8506	continue;
		8507
		8508	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		8509
		8510	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		8511	struct drm_property *dpms_property =
		8512	dev->mode_config.dpms_property;
		8513
		8514	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	8515	drm_object_property_set_value(&connector->base,
3031	serge	8516	dpms_property,
		8517	DRM_MODE_DPMS_ON);
		8518
		8519	intel_encoder = to_intel_encoder(connector->encoder);
		8520	intel_encoder->connectors_active = true;
		8521	}
		8522	}
		8523
		8524	}
		8525
4104	Serge	8526	static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
		8527	struct intel_crtc_config *new)
		8528	{
		8529	int clock1, clock2, diff;
		8530
		8531	clock1 = cur->adjusted_mode.clock;
		8532	clock2 = new->adjusted_mode.clock;
		8533
		8534	if (clock1 == clock2)
		8535	return true;
		8536
		8537	if (!clock1 \|\| !clock2)
		8538	return false;
		8539
		8540	diff = abs(clock1 - clock2);
		8541
		8542	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		8543	return true;
		8544
		8545	return false;
		8546	}
		8547
3031	serge	8548	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		8549	list_for_each_entry((intel_crtc), \
		8550	&(dev)->mode_config.crtc_list, \
		8551	base.head) \
4104	Serge	8552	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	8553
3746	Serge	8554	static bool
4104	Serge	8555	intel_pipe_config_compare(struct drm_device *dev,
		8556	struct intel_crtc_config *current_config,
3746	Serge	8557	struct intel_crtc_config *pipe_config)
		8558	{
4104	Serge	8559	#define PIPE_CONF_CHECK_X(name) \
		8560	if (current_config->name != pipe_config->name) { \
		8561	DRM_ERROR("mismatch in " #name " " \
		8562	"(expected 0x%08x, found 0x%08x)\n", \
		8563	current_config->name, \
		8564	pipe_config->name); \
		8565	return false; \
3746	Serge	8566	}
		8567
4104	Serge	8568	#define PIPE_CONF_CHECK_I(name) \
		8569	if (current_config->name != pipe_config->name) { \
		8570	DRM_ERROR("mismatch in " #name " " \
		8571	"(expected %i, found %i)\n", \
		8572	current_config->name, \
		8573	pipe_config->name); \
		8574	return false; \
		8575	}
		8576
		8577	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		8578	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		8579	DRM_ERROR("mismatch in " #name "(" #mask ") " \
		8580	"(expected %i, found %i)\n", \
		8581	current_config->name & (mask), \
		8582	pipe_config->name & (mask)); \
		8583	return false; \
		8584	}
		8585
		8586	#define PIPE_CONF_QUIRK(quirk) \
		8587	((current_config->quirks \| pipe_config->quirks) & (quirk))
		8588
		8589	PIPE_CONF_CHECK_I(cpu_transcoder);
		8590
		8591	PIPE_CONF_CHECK_I(has_pch_encoder);
		8592	PIPE_CONF_CHECK_I(fdi_lanes);
		8593	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
		8594	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
		8595	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
		8596	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
		8597	PIPE_CONF_CHECK_I(fdi_m_n.tu);
		8598
		8599	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
		8600	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
		8601	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
		8602	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
		8603	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
		8604	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
		8605
		8606	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
		8607	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
		8608	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
		8609	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
		8610	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
		8611	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
		8612
		8613	PIPE_CONF_CHECK_I(pixel_multiplier);
		8614
		8615	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8616	DRM_MODE_FLAG_INTERLACE);
		8617
		8618	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		8619	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8620	DRM_MODE_FLAG_PHSYNC);
		8621	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8622	DRM_MODE_FLAG_NHSYNC);
		8623	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8624	DRM_MODE_FLAG_PVSYNC);
		8625	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8626	DRM_MODE_FLAG_NVSYNC);
		8627	}
		8628
		8629	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
		8630	PIPE_CONF_CHECK_I(requested_mode.vdisplay);
		8631
		8632	PIPE_CONF_CHECK_I(gmch_pfit.control);
		8633	/* pfit ratios are autocomputed by the hw on gen4+ */
		8634	if (INTEL_INFO(dev)->gen < 4)
		8635	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
		8636	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
		8637	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		8638	if (current_config->pch_pfit.enabled) {
		8639	PIPE_CONF_CHECK_I(pch_pfit.pos);
		8640	PIPE_CONF_CHECK_I(pch_pfit.size);
		8641	}
		8642
		8643	PIPE_CONF_CHECK_I(ips_enabled);
		8644
		8645	PIPE_CONF_CHECK_I(shared_dpll);
		8646	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		8647	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		8648	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		8649	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
		8650
4280	Serge	8651	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5)
		8652	PIPE_CONF_CHECK_I(pipe_bpp);
		8653
4104	Serge	8654	#undef PIPE_CONF_CHECK_X
		8655	#undef PIPE_CONF_CHECK_I
		8656	#undef PIPE_CONF_CHECK_FLAGS
		8657	#undef PIPE_CONF_QUIRK
		8658
		8659	if (!IS_HASWELL(dev)) {
		8660	if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
		8661	DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
		8662	current_config->adjusted_mode.clock,
		8663	pipe_config->adjusted_mode.clock);
		8664	return false;
		8665	}
		8666	}
		8667
3746	Serge	8668	return true;
		8669	}
		8670
4104	Serge	8671	static void
		8672	check_connector_state(struct drm_device *dev)
3031	serge	8673	{
		8674	struct intel_connector *connector;
		8675
		8676	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8677	base.head) {
		8678	/* This also checks the encoder/connector hw state with the
		8679	* ->get_hw_state callbacks. */
		8680	intel_connector_check_state(connector);
		8681
		8682	WARN(&connector->new_encoder->base != connector->base.encoder,
		8683	"connector's staged encoder doesn't match current encoder\n");
		8684	}
4104	Serge	8685	}
3031	serge	8686
4104	Serge	8687	static void
		8688	check_encoder_state(struct drm_device *dev)
		8689	{
		8690	struct intel_encoder *encoder;
		8691	struct intel_connector *connector;
		8692
3031	serge	8693	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8694	base.head) {
		8695	bool enabled = false;
		8696	bool active = false;
		8697	enum pipe pipe, tracked_pipe;
		8698
		8699	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		8700	encoder->base.base.id,
		8701	drm_get_encoder_name(&encoder->base));
		8702
		8703	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		8704	"encoder's stage crtc doesn't match current crtc\n");
		8705	WARN(encoder->connectors_active && !encoder->base.crtc,
		8706	"encoder's active_connectors set, but no crtc\n");
		8707
		8708	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8709	base.head) {
		8710	if (connector->base.encoder != &encoder->base)
		8711	continue;
		8712	enabled = true;
		8713	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		8714	active = true;
		8715	}
		8716	WARN(!!encoder->base.crtc != enabled,
		8717	"encoder's enabled state mismatch "
		8718	"(expected %i, found %i)\n",
		8719	!!encoder->base.crtc, enabled);
		8720	WARN(active && !encoder->base.crtc,
		8721	"active encoder with no crtc\n");
		8722
		8723	WARN(encoder->connectors_active != active,
		8724	"encoder's computed active state doesn't match tracked active state "
		8725	"(expected %i, found %i)\n", active, encoder->connectors_active);
		8726
		8727	active = encoder->get_hw_state(encoder, &pipe);
		8728	WARN(active != encoder->connectors_active,
		8729	"encoder's hw state doesn't match sw tracking "
		8730	"(expected %i, found %i)\n",
		8731	encoder->connectors_active, active);
		8732
		8733	if (!encoder->base.crtc)
		8734	continue;
		8735
		8736	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		8737	WARN(active && pipe != tracked_pipe,
		8738	"active encoder's pipe doesn't match"
		8739	"(expected %i, found %i)\n",
		8740	tracked_pipe, pipe);
		8741
		8742	}
4104	Serge	8743	}
3031	serge	8744
4104	Serge	8745	static void
		8746	check_crtc_state(struct drm_device *dev)
		8747	{
		8748	drm_i915_private_t *dev_priv = dev->dev_private;
		8749	struct intel_crtc *crtc;
		8750	struct intel_encoder *encoder;
		8751	struct intel_crtc_config pipe_config;
		8752
3031	serge	8753	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8754	base.head) {
		8755	bool enabled = false;
		8756	bool active = false;
		8757
4104	Serge	8758	memset(&pipe_config, 0, sizeof(pipe_config));
		8759
3031	serge	8760	DRM_DEBUG_KMS("[CRTC:%d]\n",
		8761	crtc->base.base.id);
		8762
		8763	WARN(crtc->active && !crtc->base.enabled,
		8764	"active crtc, but not enabled in sw tracking\n");
		8765
		8766	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8767	base.head) {
		8768	if (encoder->base.crtc != &crtc->base)
		8769	continue;
		8770	enabled = true;
		8771	if (encoder->connectors_active)
		8772	active = true;
		8773	}
4104	Serge	8774
3031	serge	8775	WARN(active != crtc->active,
		8776	"crtc's computed active state doesn't match tracked active state "
		8777	"(expected %i, found %i)\n", active, crtc->active);
		8778	WARN(enabled != crtc->base.enabled,
		8779	"crtc's computed enabled state doesn't match tracked enabled state "
		8780	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		8781
3746	Serge	8782	active = dev_priv->display.get_pipe_config(crtc,
		8783	&pipe_config);
		8784
		8785	/* hw state is inconsistent with the pipe A quirk */
		8786	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		8787	active = crtc->active;
		8788
4104	Serge	8789	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8790	base.head) {
		8791	enum pipe pipe;
		8792	if (encoder->base.crtc != &crtc->base)
		8793	continue;
		8794	if (encoder->get_config &&
		8795	encoder->get_hw_state(encoder, &pipe))
		8796	encoder->get_config(encoder, &pipe_config);
		8797	}
		8798
		8799	if (dev_priv->display.get_clock)
		8800	dev_priv->display.get_clock(crtc, &pipe_config);
		8801
3746	Serge	8802	WARN(crtc->active != active,
		8803	"crtc active state doesn't match with hw state "
		8804	"(expected %i, found %i)\n", crtc->active, active);
		8805
4104	Serge	8806	if (active &&
		8807	!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
		8808	WARN(1, "pipe state doesn't match!\n");
		8809	intel_dump_pipe_config(crtc, &pipe_config,
		8810	"[hw state]");
		8811	intel_dump_pipe_config(crtc, &crtc->config,
		8812	"[sw state]");
		8813	}
3031	serge	8814	}
		8815	}
		8816
4104	Serge	8817	static void
		8818	check_shared_dpll_state(struct drm_device *dev)
		8819	{
		8820	drm_i915_private_t *dev_priv = dev->dev_private;
		8821	struct intel_crtc *crtc;
		8822	struct intel_dpll_hw_state dpll_hw_state;
		8823	int i;
		8824
		8825	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		8826	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		8827	int enabled_crtcs = 0, active_crtcs = 0;
		8828	bool active;
		8829
		8830	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		8831
		8832	DRM_DEBUG_KMS("%s\n", pll->name);
		8833
		8834	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		8835
		8836	WARN(pll->active > pll->refcount,
		8837	"more active pll users than references: %i vs %i\n",
		8838	pll->active, pll->refcount);
		8839	WARN(pll->active && !pll->on,
		8840	"pll in active use but not on in sw tracking\n");
		8841	WARN(pll->on && !pll->active,
		8842	"pll in on but not on in use in sw tracking\n");
		8843	WARN(pll->on != active,
		8844	"pll on state mismatch (expected %i, found %i)\n",
		8845	pll->on, active);
		8846
		8847	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8848	base.head) {
		8849	if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
		8850	enabled_crtcs++;
		8851	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		8852	active_crtcs++;
		8853	}
		8854	WARN(pll->active != active_crtcs,
		8855	"pll active crtcs mismatch (expected %i, found %i)\n",
		8856	pll->active, active_crtcs);
		8857	WARN(pll->refcount != enabled_crtcs,
		8858	"pll enabled crtcs mismatch (expected %i, found %i)\n",
		8859	pll->refcount, enabled_crtcs);
		8860
		8861	WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
		8862	sizeof(dpll_hw_state)),
		8863	"pll hw state mismatch\n");
		8864	}
		8865	}
		8866
		8867	void
		8868	intel_modeset_check_state(struct drm_device *dev)
		8869	{
		8870	check_connector_state(dev);
		8871	check_encoder_state(dev);
		8872	check_crtc_state(dev);
		8873	check_shared_dpll_state(dev);
		8874	}
		8875
3746	Serge	8876	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	8877	struct drm_display_mode *mode,
		8878	int x, int y, struct drm_framebuffer *fb)
		8879	{
		8880	struct drm_device *dev = crtc->dev;
		8881	drm_i915_private_t *dev_priv = dev->dev_private;
3746	Serge	8882	struct drm_display_mode saved_mode, saved_hwmode;
		8883	struct intel_crtc_config *pipe_config = NULL;
3031	serge	8884	struct intel_crtc *intel_crtc;
		8885	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	8886	int ret = 0;
3031	serge	8887
3480	Serge	8888	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
		8889	if (!saved_mode)
		8890	return -ENOMEM;
		8891	saved_hwmode = saved_mode + 1;
		8892
3031	serge	8893	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		8894	&prepare_pipes, &disable_pipes);
		8895
3480	Serge	8896	*saved_hwmode = crtc->hwmode;
		8897	*saved_mode = crtc->mode;
3031	serge	8898
		8899	/* Hack: Because we don't (yet) support global modeset on multiple
		8900	* crtcs, we don't keep track of the new mode for more than one crtc.
		8901	* Hence simply check whether any bit is set in modeset_pipes in all the
		8902	* pieces of code that are not yet converted to deal with mutliple crtcs
		8903	* changing their mode at the same time. */
		8904	if (modeset_pipes) {
3746	Serge	8905	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		8906	if (IS_ERR(pipe_config)) {
		8907	ret = PTR_ERR(pipe_config);
		8908	pipe_config = NULL;
		8909
3480	Serge	8910	goto out;
3031	serge	8911	}
4104	Serge	8912	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		8913	"[modeset]");
3031	serge	8914	}
		8915
3746	Serge	8916	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		8917	intel_crtc_disable(&intel_crtc->base);
		8918
3031	serge	8919	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		8920	if (intel_crtc->base.enabled)
		8921	dev_priv->display.crtc_disable(&intel_crtc->base);
		8922	}
		8923
		8924	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		8925	* to set it here already despite that we pass it down the callchain.
2330	Serge	8926	*/
3746	Serge	8927	if (modeset_pipes) {
3031	serge	8928	crtc->mode = *mode;
3746	Serge	8929	/* mode_set/enable/disable functions rely on a correct pipe
		8930	* config. */
		8931	to_intel_crtc(crtc)->config = *pipe_config;
		8932	}
2327	Serge	8933
3031	serge	8934	/* Only after disabling all output pipelines that will be changed can we
		8935	* update the the output configuration. */
		8936	intel_modeset_update_state(dev, prepare_pipes);
		8937
3243	Serge	8938	if (dev_priv->display.modeset_global_resources)
		8939	dev_priv->display.modeset_global_resources(dev);
		8940
3031	serge	8941	/* Set up the DPLL and any encoders state that needs to adjust or depend
		8942	* on the DPLL.
2330	Serge	8943	*/
3031	serge	8944	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
3480	Serge	8945	ret = intel_crtc_mode_set(&intel_crtc->base,
3031	serge	8946	x, y, fb);
3480	Serge	8947	if (ret)
3031	serge	8948	goto done;
		8949	}
		8950
		8951	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		8952	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		8953	dev_priv->display.crtc_enable(&intel_crtc->base);
		8954
		8955	if (modeset_pipes) {
		8956	/* Store real post-adjustment hardware mode. */
3746	Serge	8957	crtc->hwmode = pipe_config->adjusted_mode;
3031	serge	8958
		8959	/* Calculate and store various constants which
		8960	* are later needed by vblank and swap-completion
		8961	* timestamping. They are derived from true hwmode.
		8962	*/
		8963	drm_calc_timestamping_constants(crtc);
		8964	}
		8965
		8966	/* FIXME: add subpixel order */
		8967	done:
3480	Serge	8968	if (ret && crtc->enabled) {
		8969	crtc->hwmode = *saved_hwmode;
		8970	crtc->mode = *saved_mode;
3031	serge	8971	}
		8972
3480	Serge	8973	out:
3746	Serge	8974	kfree(pipe_config);
3480	Serge	8975	kfree(saved_mode);
3031	serge	8976	return ret;
2330	Serge	8977	}
2327	Serge	8978
4104	Serge	8979	static int intel_set_mode(struct drm_crtc *crtc,
3746	Serge	8980	struct drm_display_mode *mode,
		8981	int x, int y, struct drm_framebuffer *fb)
		8982	{
		8983	int ret;
		8984
		8985	ret = __intel_set_mode(crtc, mode, x, y, fb);
		8986
		8987	if (ret == 0)
		8988	intel_modeset_check_state(crtc->dev);
		8989
		8990	return ret;
		8991	}
		8992
3480	Serge	8993	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		8994	{
		8995	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
		8996	}
		8997
3031	serge	8998	#undef for_each_intel_crtc_masked
2327	Serge	8999
3031	serge	9000	static void intel_set_config_free(struct intel_set_config *config)
		9001	{
		9002	if (!config)
		9003	return;
		9004
		9005	kfree(config->save_connector_encoders);
		9006	kfree(config->save_encoder_crtcs);
		9007	kfree(config);
		9008	}
		9009
		9010	static int intel_set_config_save_state(struct drm_device *dev,
		9011	struct intel_set_config *config)
		9012	{
		9013	struct drm_encoder *encoder;
		9014	struct drm_connector *connector;
		9015	int count;
		9016
		9017	config->save_encoder_crtcs =
		9018	kcalloc(dev->mode_config.num_encoder,
		9019	sizeof(struct drm_crtc *), GFP_KERNEL);
		9020	if (!config->save_encoder_crtcs)
		9021	return -ENOMEM;
		9022
		9023	config->save_connector_encoders =
		9024	kcalloc(dev->mode_config.num_connector,
		9025	sizeof(struct drm_encoder *), GFP_KERNEL);
		9026	if (!config->save_connector_encoders)
		9027	return -ENOMEM;
		9028
		9029	/* Copy data. Note that driver private data is not affected.
		9030	* Should anything bad happen only the expected state is
		9031	* restored, not the drivers personal bookkeeping.
		9032	*/
		9033	count = 0;
		9034	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		9035	config->save_encoder_crtcs[count++] = encoder->crtc;
		9036	}
		9037
		9038	count = 0;
		9039	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		9040	config->save_connector_encoders[count++] = connector->encoder;
		9041	}
		9042
		9043	return 0;
		9044	}
		9045
		9046	static void intel_set_config_restore_state(struct drm_device *dev,
		9047	struct intel_set_config *config)
		9048	{
		9049	struct intel_encoder *encoder;
		9050	struct intel_connector *connector;
		9051	int count;
		9052
		9053	count = 0;
		9054	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9055	encoder->new_crtc =
		9056	to_intel_crtc(config->save_encoder_crtcs[count++]);
		9057	}
		9058
		9059	count = 0;
		9060	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		9061	connector->new_encoder =
		9062	to_intel_encoder(config->save_connector_encoders[count++]);
		9063	}
		9064	}
		9065
3746	Serge	9066	static bool
4104	Serge	9067	is_crtc_connector_off(struct drm_mode_set *set)
3746	Serge	9068	{
		9069	int i;
		9070
4104	Serge	9071	if (set->num_connectors == 0)
		9072	return false;
		9073
		9074	if (WARN_ON(set->connectors == NULL))
		9075	return false;
		9076
		9077	for (i = 0; i < set->num_connectors; i++)
		9078	if (set->connectors[i]->encoder &&
		9079	set->connectors[i]->encoder->crtc == set->crtc &&
		9080	set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
3746	Serge	9081	return true;
		9082
		9083	return false;
		9084	}
		9085
3031	serge	9086	static void
		9087	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		9088	struct intel_set_config *config)
		9089	{
		9090
		9091	/* We should be able to check here if the fb has the same properties
		9092	* and then just flip_or_move it */
4104	Serge	9093	if (is_crtc_connector_off(set)) {
3746	Serge	9094	config->mode_changed = true;
		9095	} else if (set->crtc->fb != set->fb) {
3031	serge	9096	/* If we have no fb then treat it as a full mode set */
		9097	if (set->crtc->fb == NULL) {
4104	Serge	9098	struct intel_crtc *intel_crtc =
		9099	to_intel_crtc(set->crtc);
		9100
		9101	if (intel_crtc->active && i915_fastboot) {
		9102	DRM_DEBUG_KMS("crtc has no fb, will flip\n");
		9103	config->fb_changed = true;
		9104	} else {
		9105	DRM_DEBUG_KMS("inactive crtc, full mode set\n");
3031	serge	9106	config->mode_changed = true;
4104	Serge	9107	}
3031	serge	9108	} else if (set->fb == NULL) {
		9109	config->mode_changed = true;
3746	Serge	9110	} else if (set->fb->pixel_format !=
		9111	set->crtc->fb->pixel_format) {
3031	serge	9112	config->mode_changed = true;
3746	Serge	9113	} else {
3031	serge	9114	config->fb_changed = true;
		9115	}
3746	Serge	9116	}
3031	serge	9117
		9118	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		9119	config->fb_changed = true;
		9120
		9121	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		9122	DRM_DEBUG_KMS("modes are different, full mode set\n");
		9123	drm_mode_debug_printmodeline(&set->crtc->mode);
		9124	drm_mode_debug_printmodeline(set->mode);
		9125	config->mode_changed = true;
		9126	}
4104	Serge	9127
		9128	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
		9129	set->crtc->base.id, config->mode_changed, config->fb_changed);
3031	serge	9130	}
		9131
		9132	static int
		9133	intel_modeset_stage_output_state(struct drm_device *dev,
		9134	struct drm_mode_set *set,
		9135	struct intel_set_config *config)
		9136	{
		9137	struct drm_crtc *new_crtc;
		9138	struct intel_connector *connector;
		9139	struct intel_encoder *encoder;
4104	Serge	9140	int ro;
3031	serge	9141
3480	Serge	9142	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	9143	* of connectors. For paranoia, double-check this. */
		9144	WARN_ON(!set->fb && (set->num_connectors != 0));
		9145	WARN_ON(set->fb && (set->num_connectors == 0));
		9146
		9147	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9148	base.head) {
		9149	/* Otherwise traverse passed in connector list and get encoders
		9150	* for them. */
		9151	for (ro = 0; ro < set->num_connectors; ro++) {
		9152	if (set->connectors[ro] == &connector->base) {
		9153	connector->new_encoder = connector->encoder;
		9154	break;
		9155	}
		9156	}
		9157
		9158	/* If we disable the crtc, disable all its connectors. Also, if
		9159	* the connector is on the changing crtc but not on the new
		9160	* connector list, disable it. */
		9161	if ((!set->fb \|\| ro == set->num_connectors) &&
		9162	connector->base.encoder &&
		9163	connector->base.encoder->crtc == set->crtc) {
		9164	connector->new_encoder = NULL;
		9165
		9166	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		9167	connector->base.base.id,
		9168	drm_get_connector_name(&connector->base));
		9169	}
		9170
		9171
		9172	if (&connector->new_encoder->base != connector->base.encoder) {
		9173	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		9174	config->mode_changed = true;
		9175	}
		9176	}
		9177	/* connector->new_encoder is now updated for all connectors. */
		9178
		9179	/* Update crtc of enabled connectors. */
		9180	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9181	base.head) {
		9182	if (!connector->new_encoder)
		9183	continue;
		9184
		9185	new_crtc = connector->new_encoder->base.crtc;
		9186
		9187	for (ro = 0; ro < set->num_connectors; ro++) {
		9188	if (set->connectors[ro] == &connector->base)
		9189	new_crtc = set->crtc;
		9190	}
		9191
		9192	/* Make sure the new CRTC will work with the encoder */
		9193	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		9194	new_crtc)) {
		9195	return -EINVAL;
		9196	}
		9197	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		9198
		9199	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		9200	connector->base.base.id,
		9201	drm_get_connector_name(&connector->base),
		9202	new_crtc->base.id);
		9203	}
		9204
		9205	/* Check for any encoders that needs to be disabled. */
		9206	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9207	base.head) {
		9208	list_for_each_entry(connector,
		9209	&dev->mode_config.connector_list,
		9210	base.head) {
		9211	if (connector->new_encoder == encoder) {
		9212	WARN_ON(!connector->new_encoder->new_crtc);
		9213
		9214	goto next_encoder;
		9215	}
		9216	}
		9217	encoder->new_crtc = NULL;
		9218	next_encoder:
		9219	/* Only now check for crtc changes so we don't miss encoders
		9220	* that will be disabled. */
		9221	if (&encoder->new_crtc->base != encoder->base.crtc) {
		9222	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		9223	config->mode_changed = true;
		9224	}
		9225	}
		9226	/* Now we've also updated encoder->new_crtc for all encoders. */
		9227
		9228	return 0;
		9229	}
		9230
		9231	static int intel_crtc_set_config(struct drm_mode_set *set)
		9232	{
		9233	struct drm_device *dev;
		9234	struct drm_mode_set save_set;
		9235	struct intel_set_config *config;
		9236	int ret;
		9237
		9238	BUG_ON(!set);
		9239	BUG_ON(!set->crtc);
		9240	BUG_ON(!set->crtc->helper_private);
		9241
3480	Serge	9242	/* Enforce sane interface api - has been abused by the fb helper. */
		9243	BUG_ON(!set->mode && set->fb);
		9244	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	9245
		9246	if (set->fb) {
		9247	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		9248	set->crtc->base.id, set->fb->base.id,
		9249	(int)set->num_connectors, set->x, set->y);
		9250	} else {
		9251	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		9252	}
		9253
		9254	dev = set->crtc->dev;
		9255
		9256	ret = -ENOMEM;
		9257	config = kzalloc(sizeof(*config), GFP_KERNEL);
		9258	if (!config)
		9259	goto out_config;
		9260
		9261	ret = intel_set_config_save_state(dev, config);
		9262	if (ret)
		9263	goto out_config;
		9264
		9265	save_set.crtc = set->crtc;
		9266	save_set.mode = &set->crtc->mode;
		9267	save_set.x = set->crtc->x;
		9268	save_set.y = set->crtc->y;
		9269	save_set.fb = set->crtc->fb;
		9270
		9271	/* Compute whether we need a full modeset, only an fb base update or no
		9272	* change at all. In the future we might also check whether only the
		9273	* mode changed, e.g. for LVDS where we only change the panel fitter in
		9274	* such cases. */
		9275	intel_set_config_compute_mode_changes(set, config);
		9276
		9277	ret = intel_modeset_stage_output_state(dev, set, config);
		9278	if (ret)
		9279	goto fail;
		9280
		9281	if (config->mode_changed) {
3480	Serge	9282	ret = intel_set_mode(set->crtc, set->mode,
		9283	set->x, set->y, set->fb);
3031	serge	9284	} else if (config->fb_changed) {
3746	Serge	9285	// intel_crtc_wait_for_pending_flips(set->crtc);
		9286
3031	serge	9287	ret = intel_pipe_set_base(set->crtc,
		9288	set->x, set->y, set->fb);
		9289	}
		9290
3746	Serge	9291	if (ret) {
4104	Serge	9292	DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
3746	Serge	9293	set->crtc->base.id, ret);
3031	serge	9294	fail:
		9295	intel_set_config_restore_state(dev, config);
		9296
		9297	/* Try to restore the config */
		9298	if (config->mode_changed &&
3480	Serge	9299	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	9300	save_set.x, save_set.y, save_set.fb))
		9301	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	9302	}
3031	serge	9303
		9304	out_config:
		9305	intel_set_config_free(config);
		9306	return ret;
		9307	}
		9308
2330	Serge	9309	static const struct drm_crtc_funcs intel_crtc_funcs = {
		9310	// .cursor_set = intel_crtc_cursor_set,
		9311	// .cursor_move = intel_crtc_cursor_move,
		9312	.gamma_set = intel_crtc_gamma_set,
3031	serge	9313	.set_config = intel_crtc_set_config,
2330	Serge	9314	.destroy = intel_crtc_destroy,
		9315	// .page_flip = intel_crtc_page_flip,
		9316	};
2327	Serge	9317
3243	Serge	9318	static void intel_cpu_pll_init(struct drm_device *dev)
		9319	{
3480	Serge	9320	if (HAS_DDI(dev))
3243	Serge	9321	intel_ddi_pll_init(dev);
		9322	}
		9323
4104	Serge	9324	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		9325	struct intel_shared_dpll *pll,
		9326	struct intel_dpll_hw_state *hw_state)
3031	serge	9327	{
4104	Serge	9328	uint32_t val;
3031	serge	9329
4104	Serge	9330	val = I915_READ(PCH_DPLL(pll->id));
		9331	hw_state->dpll = val;
		9332	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		9333	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		9334
		9335	return val & DPLL_VCO_ENABLE;
		9336	}
		9337
		9338	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		9339	struct intel_shared_dpll *pll)
		9340	{
		9341	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
		9342	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
		9343	}
		9344
		9345	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		9346	struct intel_shared_dpll *pll)
		9347	{
		9348	/* PCH refclock must be enabled first */
		9349	assert_pch_refclk_enabled(dev_priv);
		9350
		9351	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9352
		9353	/* Wait for the clocks to stabilize. */
		9354	POSTING_READ(PCH_DPLL(pll->id));
		9355	udelay(150);
		9356
		9357	/* The pixel multiplier can only be updated once the
		9358	* DPLL is enabled and the clocks are stable.
		9359	*
		9360	* So write it again.
		9361	*/
		9362	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9363	POSTING_READ(PCH_DPLL(pll->id));
		9364	udelay(200);
		9365	}
		9366
		9367	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		9368	struct intel_shared_dpll *pll)
		9369	{
		9370	struct drm_device *dev = dev_priv->dev;
		9371	struct intel_crtc *crtc;
		9372
		9373	/* Make sure no transcoder isn't still depending on us. */
		9374	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		9375	if (intel_crtc_to_shared_dpll(crtc) == pll)
		9376	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	9377	}
		9378
4104	Serge	9379	I915_WRITE(PCH_DPLL(pll->id), 0);
		9380	POSTING_READ(PCH_DPLL(pll->id));
		9381	udelay(200);
		9382	}
		9383
		9384	static char *ibx_pch_dpll_names[] = {
		9385	"PCH DPLL A",
		9386	"PCH DPLL B",
		9387	};
		9388
		9389	static void ibx_pch_dpll_init(struct drm_device *dev)
		9390	{
		9391	struct drm_i915_private *dev_priv = dev->dev_private;
		9392	int i;
		9393
		9394	dev_priv->num_shared_dpll = 2;
		9395
		9396	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		9397	dev_priv->shared_dplls[i].id = i;
		9398	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		9399	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		9400	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		9401	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		9402	dev_priv->shared_dplls[i].get_hw_state =
		9403	ibx_pch_dpll_get_hw_state;
3031	serge	9404	}
		9405	}
		9406
4104	Serge	9407	static void intel_shared_dpll_init(struct drm_device *dev)
		9408	{
		9409	struct drm_i915_private *dev_priv = dev->dev_private;
		9410
		9411	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		9412	ibx_pch_dpll_init(dev);
		9413	else
		9414	dev_priv->num_shared_dpll = 0;
		9415
		9416	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		9417	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
		9418	dev_priv->num_shared_dpll);
		9419	}
		9420
2330	Serge	9421	static void intel_crtc_init(struct drm_device *dev, int pipe)
		9422	{
		9423	drm_i915_private_t *dev_priv = dev->dev_private;
		9424	struct intel_crtc *intel_crtc;
		9425	int i;
2327	Serge	9426
2330	Serge	9427	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		9428	if (intel_crtc == NULL)
		9429	return;
2327	Serge	9430
2330	Serge	9431	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	9432
2330	Serge	9433	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		9434	for (i = 0; i < 256; i++) {
		9435	intel_crtc->lut_r[i] = i;
		9436	intel_crtc->lut_g[i] = i;
		9437	intel_crtc->lut_b[i] = i;
		9438	}
2327	Serge	9439
2330	Serge	9440	/* Swap pipes & planes for FBC on pre-965 */
		9441	intel_crtc->pipe = pipe;
		9442	intel_crtc->plane = pipe;
		9443	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		9444	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		9445	intel_crtc->plane = !pipe;
		9446	}
2327	Serge	9447
2330	Serge	9448	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		9449	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		9450	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		9451	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	9452
2330	Serge	9453	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
		9454	}
2327	Serge	9455
3031	serge	9456	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		9457	struct drm_file *file)
		9458	{
		9459	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		9460	struct drm_mode_object *drmmode_obj;
		9461	struct intel_crtc *crtc;
2327	Serge	9462
3482	Serge	9463	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		9464	return -ENODEV;
		9465
3031	serge	9466	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		9467	DRM_MODE_OBJECT_CRTC);
2327	Serge	9468
3031	serge	9469	if (!drmmode_obj) {
		9470	DRM_ERROR("no such CRTC id\n");
		9471	return -EINVAL;
		9472	}
2327	Serge	9473
3031	serge	9474	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		9475	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	9476
3031	serge	9477	return 0;
		9478	}
2327	Serge	9479
3031	serge	9480	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	9481	{
3031	serge	9482	struct drm_device *dev = encoder->base.dev;
		9483	struct intel_encoder *source_encoder;
2330	Serge	9484	int index_mask = 0;
		9485	int entry = 0;
2327	Serge	9486
3031	serge	9487	list_for_each_entry(source_encoder,
		9488	&dev->mode_config.encoder_list, base.head) {
		9489
		9490	if (encoder == source_encoder)
2330	Serge	9491	index_mask \|= (1 << entry);
3031	serge	9492
		9493	/* Intel hw has only one MUX where enocoders could be cloned. */
		9494	if (encoder->cloneable && source_encoder->cloneable)
		9495	index_mask \|= (1 << entry);
		9496
2330	Serge	9497	entry++;
		9498	}
2327	Serge	9499
2330	Serge	9500	return index_mask;
		9501	}
2327	Serge	9502
2330	Serge	9503	static bool has_edp_a(struct drm_device *dev)
		9504	{
		9505	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9506
2330	Serge	9507	if (!IS_MOBILE(dev))
		9508	return false;
2327	Serge	9509
2330	Serge	9510	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		9511	return false;
2327	Serge	9512
2330	Serge	9513	if (IS_GEN5(dev) &&
		9514	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		9515	return false;
2327	Serge	9516
2330	Serge	9517	return true;
		9518	}
2327	Serge	9519
2330	Serge	9520	static void intel_setup_outputs(struct drm_device *dev)
		9521	{
		9522	struct drm_i915_private *dev_priv = dev->dev_private;
		9523	struct intel_encoder *encoder;
		9524	bool dpd_is_edp = false;
2327	Serge	9525
4104	Serge	9526	intel_lvds_init(dev);
2327	Serge	9527
3746	Serge	9528	if (!IS_ULT(dev))
2330	Serge	9529	intel_crt_init(dev);
2327	Serge	9530
3480	Serge	9531	if (HAS_DDI(dev)) {
2330	Serge	9532	int found;
2327	Serge	9533
3031	serge	9534	/* Haswell uses DDI functions to detect digital outputs */
		9535	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		9536	/* DDI A only supports eDP */
		9537	if (found)
		9538	intel_ddi_init(dev, PORT_A);
		9539
		9540	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		9541	* register */
		9542	found = I915_READ(SFUSE_STRAP);
		9543
		9544	if (found & SFUSE_STRAP_DDIB_DETECTED)
		9545	intel_ddi_init(dev, PORT_B);
		9546	if (found & SFUSE_STRAP_DDIC_DETECTED)
		9547	intel_ddi_init(dev, PORT_C);
		9548	if (found & SFUSE_STRAP_DDID_DETECTED)
		9549	intel_ddi_init(dev, PORT_D);
		9550	} else if (HAS_PCH_SPLIT(dev)) {
		9551	int found;
3243	Serge	9552	dpd_is_edp = intel_dpd_is_edp(dev);
3031	serge	9553
3243	Serge	9554	if (has_edp_a(dev))
		9555	intel_dp_init(dev, DP_A, PORT_A);
		9556
3746	Serge	9557	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	9558	/* PCH SDVOB multiplex with HDMIB */
3031	serge	9559	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	9560	if (!found)
3746	Serge	9561	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	9562	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	9563	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	9564	}
2327	Serge	9565
3746	Serge	9566	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		9567	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	9568
3746	Serge	9569	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		9570	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	9571
2330	Serge	9572	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	9573	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	9574
3243	Serge	9575	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	9576	intel_dp_init(dev, PCH_DP_D, PORT_D);
		9577	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	9578	/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
4104	Serge	9579	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
		9580	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
		9581	PORT_C);
3480	Serge	9582	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
4104	Serge	9583	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
		9584	PORT_C);
		9585	}
3243	Serge	9586
3746	Serge	9587	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		9588	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		9589	PORT_B);
3480	Serge	9590	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		9591	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
3031	serge	9592	}
2330	Serge	9593	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		9594	bool found = false;
2327	Serge	9595
3746	Serge	9596	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9597	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	9598	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	9599	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		9600	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	9601	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	9602	}
2327	Serge	9603
4104	Serge	9604	if (!found && SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9605	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	9606	}
2327	Serge	9607
2330	Serge	9608	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	9609
3746	Serge	9610	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9611	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	9612	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	9613	}
2327	Serge	9614
3746	Serge	9615	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	9616
2330	Serge	9617	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		9618	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	9619	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	9620	}
4104	Serge	9621	if (SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9622	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	9623	}
2327	Serge	9624
2330	Serge	9625	if (SUPPORTS_INTEGRATED_DP(dev) &&
4104	Serge	9626	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	9627	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	9628	} else if (IS_GEN2(dev))
		9629	intel_dvo_init(dev);
2327	Serge	9630
2330	Serge	9631	// if (SUPPORTS_TV(dev))
		9632	// intel_tv_init(dev);
2327	Serge	9633
2330	Serge	9634	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9635	encoder->base.possible_crtcs = encoder->crtc_mask;
		9636	encoder->base.possible_clones =
3031	serge	9637	intel_encoder_clones(encoder);
2330	Serge	9638	}
2327	Serge	9639
3243	Serge	9640	intel_init_pch_refclk(dev);
		9641
		9642	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	9643	}
		9644
		9645
		9646
2335	Serge	9647	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		9648	// .destroy = intel_user_framebuffer_destroy,
		9649	// .create_handle = intel_user_framebuffer_create_handle,
		9650	};
2327	Serge	9651
2335	Serge	9652	int intel_framebuffer_init(struct drm_device *dev,
		9653	struct intel_framebuffer *intel_fb,
2342	Serge	9654	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	9655	struct drm_i915_gem_object *obj)
		9656	{
4104	Serge	9657	int pitch_limit;
2335	Serge	9658	int ret;
2327	Serge	9659
3243	Serge	9660	if (obj->tiling_mode == I915_TILING_Y) {
		9661	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	9662	return -EINVAL;
3243	Serge	9663	}
2327	Serge	9664
3243	Serge	9665	if (mode_cmd->pitches[0] & 63) {
		9666	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		9667	mode_cmd->pitches[0]);
		9668	return -EINVAL;
		9669	}
		9670
4104	Serge	9671	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		9672	pitch_limit = 32*1024;
		9673	} else if (INTEL_INFO(dev)->gen >= 4) {
		9674	if (obj->tiling_mode)
		9675	pitch_limit = 16*1024;
		9676	else
		9677	pitch_limit = 32*1024;
		9678	} else if (INTEL_INFO(dev)->gen >= 3) {
		9679	if (obj->tiling_mode)
		9680	pitch_limit = 8*1024;
		9681	else
		9682	pitch_limit = 16*1024;
		9683	} else
		9684	/* XXX DSPC is limited to 4k tiled */
		9685	pitch_limit = 8*1024;
		9686
		9687	if (mode_cmd->pitches[0] > pitch_limit) {
		9688	DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
		9689	obj->tiling_mode ? "tiled" : "linear",
		9690	mode_cmd->pitches[0], pitch_limit);
3243	Serge	9691	return -EINVAL;
		9692	}
		9693
		9694	if (obj->tiling_mode != I915_TILING_NONE &&
		9695	mode_cmd->pitches[0] != obj->stride) {
		9696	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		9697	mode_cmd->pitches[0], obj->stride);
2335	Serge	9698	return -EINVAL;
3243	Serge	9699	}
2327	Serge	9700
3243	Serge	9701	/* Reject formats not supported by any plane early. */
2342	Serge	9702	switch (mode_cmd->pixel_format) {
3243	Serge	9703	case DRM_FORMAT_C8:
2342	Serge	9704	case DRM_FORMAT_RGB565:
		9705	case DRM_FORMAT_XRGB8888:
3243	Serge	9706	case DRM_FORMAT_ARGB8888:
		9707	break;
		9708	case DRM_FORMAT_XRGB1555:
		9709	case DRM_FORMAT_ARGB1555:
		9710	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	9711	DRM_DEBUG("unsupported pixel format: %s\n",
		9712	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9713	return -EINVAL;
		9714	}
		9715	break;
3031	serge	9716	case DRM_FORMAT_XBGR8888:
3243	Serge	9717	case DRM_FORMAT_ABGR8888:
2342	Serge	9718	case DRM_FORMAT_XRGB2101010:
		9719	case DRM_FORMAT_ARGB2101010:
3243	Serge	9720	case DRM_FORMAT_XBGR2101010:
		9721	case DRM_FORMAT_ABGR2101010:
		9722	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	9723	DRM_DEBUG("unsupported pixel format: %s\n",
		9724	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9725	return -EINVAL;
		9726	}
2335	Serge	9727	break;
2342	Serge	9728	case DRM_FORMAT_YUYV:
		9729	case DRM_FORMAT_UYVY:
		9730	case DRM_FORMAT_YVYU:
		9731	case DRM_FORMAT_VYUY:
3243	Serge	9732	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	9733	DRM_DEBUG("unsupported pixel format: %s\n",
		9734	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9735	return -EINVAL;
		9736	}
2342	Serge	9737	break;
2335	Serge	9738	default:
4104	Serge	9739	DRM_DEBUG("unsupported pixel format: %s\n",
		9740	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	9741	return -EINVAL;
		9742	}
2327	Serge	9743
3243	Serge	9744	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		9745	if (mode_cmd->offsets[0] != 0)
		9746	return -EINVAL;
		9747
3480	Serge	9748	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		9749	intel_fb->obj = obj;
		9750
2335	Serge	9751	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		9752	if (ret) {
		9753	DRM_ERROR("framebuffer init failed %d\n", ret);
		9754	return ret;
		9755	}
2327	Serge	9756
2335	Serge	9757	return 0;
		9758	}
2327	Serge	9759
		9760
2360	Serge	9761	static const struct drm_mode_config_funcs intel_mode_funcs = {
		9762	.fb_create = NULL /intel_user_framebuffer_create/,
3480	Serge	9763	.output_poll_changed = intel_fb_output_poll_changed,
2360	Serge	9764	};
2327	Serge	9765
3031	serge	9766	/* Set up chip specific display functions */
		9767	static void intel_init_display(struct drm_device *dev)
		9768	{
		9769	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9770
4104	Serge	9771	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		9772	dev_priv->display.find_dpll = g4x_find_best_dpll;
		9773	else if (IS_VALLEYVIEW(dev))
		9774	dev_priv->display.find_dpll = vlv_find_best_dpll;
		9775	else if (IS_PINEVIEW(dev))
		9776	dev_priv->display.find_dpll = pnv_find_best_dpll;
		9777	else
		9778	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		9779
3480	Serge	9780	if (HAS_DDI(dev)) {
3746	Serge	9781	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
3243	Serge	9782	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		9783	dev_priv->display.crtc_enable = haswell_crtc_enable;
		9784	dev_priv->display.crtc_disable = haswell_crtc_disable;
		9785	dev_priv->display.off = haswell_crtc_off;
		9786	dev_priv->display.update_plane = ironlake_update_plane;
		9787	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	9788	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
4104	Serge	9789	dev_priv->display.get_clock = ironlake_crtc_clock_get;
3031	serge	9790	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		9791	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		9792	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		9793	dev_priv->display.off = ironlake_crtc_off;
		9794	dev_priv->display.update_plane = ironlake_update_plane;
4104	Serge	9795	} else if (IS_VALLEYVIEW(dev)) {
		9796	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
		9797	dev_priv->display.get_clock = i9xx_crtc_clock_get;
		9798	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9799	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		9800	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9801	dev_priv->display.off = i9xx_crtc_off;
		9802	dev_priv->display.update_plane = i9xx_update_plane;
3031	serge	9803	} else {
3746	Serge	9804	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
4104	Serge	9805	dev_priv->display.get_clock = i9xx_crtc_clock_get;
3031	serge	9806	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9807	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		9808	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9809	dev_priv->display.off = i9xx_crtc_off;
		9810	dev_priv->display.update_plane = i9xx_update_plane;
		9811	}
2327	Serge	9812
3031	serge	9813	/* Returns the core display clock speed */
		9814	if (IS_VALLEYVIEW(dev))
		9815	dev_priv->display.get_display_clock_speed =
		9816	valleyview_get_display_clock_speed;
		9817	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		9818	dev_priv->display.get_display_clock_speed =
		9819	i945_get_display_clock_speed;
		9820	else if (IS_I915G(dev))
		9821	dev_priv->display.get_display_clock_speed =
		9822	i915_get_display_clock_speed;
4104	Serge	9823	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	9824	dev_priv->display.get_display_clock_speed =
		9825	i9xx_misc_get_display_clock_speed;
4104	Serge	9826	else if (IS_PINEVIEW(dev))
		9827	dev_priv->display.get_display_clock_speed =
		9828	pnv_get_display_clock_speed;
3031	serge	9829	else if (IS_I915GM(dev))
		9830	dev_priv->display.get_display_clock_speed =
		9831	i915gm_get_display_clock_speed;
		9832	else if (IS_I865G(dev))
		9833	dev_priv->display.get_display_clock_speed =
		9834	i865_get_display_clock_speed;
		9835	else if (IS_I85X(dev))
		9836	dev_priv->display.get_display_clock_speed =
		9837	i855_get_display_clock_speed;
		9838	else /* 852, 830 */
		9839	dev_priv->display.get_display_clock_speed =
		9840	i830_get_display_clock_speed;
2327	Serge	9841
3031	serge	9842	if (HAS_PCH_SPLIT(dev)) {
		9843	if (IS_GEN5(dev)) {
		9844	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		9845	dev_priv->display.write_eld = ironlake_write_eld;
		9846	} else if (IS_GEN6(dev)) {
		9847	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		9848	dev_priv->display.write_eld = ironlake_write_eld;
		9849	} else if (IS_IVYBRIDGE(dev)) {
		9850	/* FIXME: detect B0+ stepping and use auto training */
		9851	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		9852	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	9853	dev_priv->display.modeset_global_resources =
		9854	ivb_modeset_global_resources;
3031	serge	9855	} else if (IS_HASWELL(dev)) {
		9856	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		9857	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	9858	dev_priv->display.modeset_global_resources =
		9859	haswell_modeset_global_resources;
		9860	}
3031	serge	9861	} else if (IS_G4X(dev)) {
		9862	dev_priv->display.write_eld = g4x_write_eld;
		9863	}
2327	Serge	9864
3031	serge	9865	/* Default just returns -ENODEV to indicate unsupported */
		9866	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	9867
		9868
		9869
		9870
3031	serge	9871	}
		9872
		9873	/*
		9874	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		9875	* resume, or other times. This quirk makes sure that's the case for
		9876	* affected systems.
		9877	*/
		9878	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	9879	{
		9880	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9881
3031	serge	9882	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		9883	DRM_INFO("applying pipe a force quirk\n");
		9884	}
2327	Serge	9885
3031	serge	9886	/*
		9887	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		9888	*/
		9889	static void quirk_ssc_force_disable(struct drm_device *dev)
		9890	{
		9891	struct drm_i915_private *dev_priv = dev->dev_private;
		9892	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		9893	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	9894	}
2327	Serge	9895
3031	serge	9896	/*
		9897	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		9898	* brightness value
		9899	*/
		9900	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	9901	{
		9902	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9903	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		9904	DRM_INFO("applying inverted panel brightness quirk\n");
		9905	}
2327	Serge	9906
4104	Serge	9907	/*
		9908	* Some machines (Dell XPS13) suffer broken backlight controls if
		9909	* BLM_PCH_PWM_ENABLE is set.
		9910	*/
		9911	static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
		9912	{
		9913	struct drm_i915_private *dev_priv = dev->dev_private;
		9914	dev_priv->quirks \|= QUIRK_NO_PCH_PWM_ENABLE;
		9915	DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
		9916	}
		9917
3031	serge	9918	struct intel_quirk {
		9919	int device;
		9920	int subsystem_vendor;
		9921	int subsystem_device;
		9922	void (hook)(struct drm_device dev);
		9923	};
2327	Serge	9924
3031	serge	9925	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		9926	struct intel_dmi_quirk {
		9927	void (hook)(struct drm_device dev);
		9928	const struct dmi_system_id (*dmi_id_list)[];
		9929	};
2327	Serge	9930
3031	serge	9931	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		9932	{
		9933	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		9934	return 1;
2330	Serge	9935	}
2327	Serge	9936
3031	serge	9937	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		9938	{
		9939	.dmi_id_list = &(const struct dmi_system_id[]) {
		9940	{
		9941	.callback = intel_dmi_reverse_brightness,
		9942	.ident = "NCR Corporation",
		9943	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		9944	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		9945	},
		9946	},
		9947	{ } /* terminating entry */
		9948	},
		9949	.hook = quirk_invert_brightness,
		9950	},
		9951	};
2327	Serge	9952
3031	serge	9953	static struct intel_quirk intel_quirks[] = {
		9954	/* HP Mini needs pipe A force quirk (LP: #322104) */
		9955	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	9956
3031	serge	9957	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		9958	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	9959
3031	serge	9960	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		9961	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	9962
3031	serge	9963	/* 830/845 need to leave pipe A & dpll A up */
		9964	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		9965	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	9966
3031	serge	9967	/* Lenovo U160 cannot use SSC on LVDS */
		9968	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	9969
3031	serge	9970	/* Sony Vaio Y cannot use SSC on LVDS */
		9971	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	9972
3031	serge	9973	/* Acer Aspire 5734Z must invert backlight brightness */
		9974	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	9975
		9976	/* Acer/eMachines G725 */
		9977	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		9978
		9979	/* Acer/eMachines e725 */
		9980	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		9981
		9982	/* Acer/Packard Bell NCL20 */
		9983	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		9984
		9985	/* Acer Aspire 4736Z */
		9986	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
4104	Serge	9987
		9988	/* Dell XPS13 HD Sandy Bridge */
		9989	{ 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
		9990	/* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
		9991	{ 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
3031	serge	9992	};
2327	Serge	9993
3031	serge	9994	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	9995	{
3031	serge	9996	struct pci_dev *d = dev->pdev;
		9997	int i;
2327	Serge	9998
3031	serge	9999	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		10000	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	10001
3031	serge	10002	if (d->device == q->device &&
		10003	(d->subsystem_vendor == q->subsystem_vendor \|\|
		10004	q->subsystem_vendor == PCI_ANY_ID) &&
		10005	(d->subsystem_device == q->subsystem_device \|\|
		10006	q->subsystem_device == PCI_ANY_ID))
		10007	q->hook(dev);
		10008	}
2330	Serge	10009	}
2327	Serge	10010
3031	serge	10011	/* Disable the VGA plane that we never use */
		10012	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	10013	{
		10014	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10015	u8 sr1;
3480	Serge	10016	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	10017
3031	serge	10018	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		10019	out8(SR01, VGA_SR_INDEX);
		10020	sr1 = in8(VGA_SR_DATA);
		10021	out8(sr1 \| 1<<5, VGA_SR_DATA);
		10022	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		10023	udelay(300);
2327	Serge	10024
3031	serge	10025	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		10026	POSTING_READ(vga_reg);
2330	Serge	10027	}
		10028
3031	serge	10029	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	10030	{
3480	Serge	10031	intel_init_power_well(dev);
2342	Serge	10032
3031	serge	10033	intel_prepare_ddi(dev);
2342	Serge	10034
3031	serge	10035	intel_init_clock_gating(dev);
		10036
3482	Serge	10037	mutex_lock(&dev->struct_mutex);
		10038	intel_enable_gt_powersave(dev);
		10039	mutex_unlock(&dev->struct_mutex);
2342	Serge	10040	}
		10041
3031	serge	10042	void intel_modeset_init(struct drm_device *dev)
2330	Serge	10043	{
3031	serge	10044	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	10045	int i, j, ret;
2330	Serge	10046
3031	serge	10047	drm_mode_config_init(dev);
2330	Serge	10048
3031	serge	10049	dev->mode_config.min_width = 0;
		10050	dev->mode_config.min_height = 0;
2330	Serge	10051
3031	serge	10052	dev->mode_config.preferred_depth = 24;
		10053	dev->mode_config.prefer_shadow = 1;
2330	Serge	10054
3031	serge	10055	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	10056
3031	serge	10057	intel_init_quirks(dev);
2330	Serge	10058
3031	serge	10059	intel_init_pm(dev);
2330	Serge	10060
3746	Serge	10061	if (INTEL_INFO(dev)->num_pipes == 0)
		10062	return;
		10063
3031	serge	10064	intel_init_display(dev);
2330	Serge	10065
3031	serge	10066	if (IS_GEN2(dev)) {
		10067	dev->mode_config.max_width = 2048;
		10068	dev->mode_config.max_height = 2048;
		10069	} else if (IS_GEN3(dev)) {
		10070	dev->mode_config.max_width = 4096;
		10071	dev->mode_config.max_height = 4096;
		10072	} else {
		10073	dev->mode_config.max_width = 8192;
		10074	dev->mode_config.max_height = 8192;
		10075	}
3480	Serge	10076	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	10077
3031	serge	10078	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	10079	INTEL_INFO(dev)->num_pipes,
		10080	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	10081
4104	Serge	10082	for_each_pipe(i) {
3031	serge	10083	intel_crtc_init(dev, i);
3746	Serge	10084	for (j = 0; j < dev_priv->num_plane; j++) {
		10085	ret = intel_plane_init(dev, i, j);
3031	serge	10086	if (ret)
4104	Serge	10087	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
		10088	pipe_name(i), sprite_name(i, j), ret);
3746	Serge	10089	}
2330	Serge	10090	}
		10091
3243	Serge	10092	intel_cpu_pll_init(dev);
4104	Serge	10093	intel_shared_dpll_init(dev);
2330	Serge	10094
3031	serge	10095	/* Just disable it once at startup */
		10096	i915_disable_vga(dev);
		10097	intel_setup_outputs(dev);
3480	Serge	10098
		10099	/* Just in case the BIOS is doing something questionable. */
		10100	intel_disable_fbc(dev);
3031	serge	10101	}
2330	Serge	10102
3031	serge	10103	static void
		10104	intel_connector_break_all_links(struct intel_connector *connector)
		10105	{
		10106	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10107	connector->base.encoder = NULL;
		10108	connector->encoder->connectors_active = false;
		10109	connector->encoder->base.crtc = NULL;
2330	Serge	10110	}
		10111
3031	serge	10112	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	10113	{
3031	serge	10114	struct intel_connector *connector;
		10115	struct drm_connector *crt = NULL;
		10116	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	10117
3031	serge	10118	/* We can't just switch on the pipe A, we need to set things up with a
		10119	* proper mode and output configuration. As a gross hack, enable pipe A
		10120	* by enabling the load detect pipe once. */
		10121	list_for_each_entry(connector,
		10122	&dev->mode_config.connector_list,
		10123	base.head) {
		10124	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		10125	crt = &connector->base;
		10126	break;
2330	Serge	10127	}
		10128	}
		10129
3031	serge	10130	if (!crt)
		10131	return;
2330	Serge	10132
3031	serge	10133	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		10134	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	10135
		10136
		10137	}
		10138
3031	serge	10139	static bool
		10140	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	10141	{
3746	Serge	10142	struct drm_device *dev = crtc->base.dev;
		10143	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10144	u32 reg, val;
2327	Serge	10145
3746	Serge	10146	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	10147	return true;
2327	Serge	10148
3031	serge	10149	reg = DSPCNTR(!crtc->plane);
		10150	val = I915_READ(reg);
2327	Serge	10151
3031	serge	10152	if ((val & DISPLAY_PLANE_ENABLE) &&
		10153	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		10154	return false;
2327	Serge	10155
3031	serge	10156	return true;
2327	Serge	10157	}
		10158
3031	serge	10159	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	10160	{
3031	serge	10161	struct drm_device *dev = crtc->base.dev;
2327	Serge	10162	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10163	u32 reg;
2327	Serge	10164
3031	serge	10165	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	10166	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	10167	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	10168
3031	serge	10169	/* We need to sanitize the plane -> pipe mapping first because this will
		10170	* disable the crtc (and hence change the state) if it is wrong. Note
		10171	* that gen4+ has a fixed plane -> pipe mapping. */
		10172	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		10173	struct intel_connector *connector;
		10174	bool plane;
2327	Serge	10175
3031	serge	10176	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		10177	crtc->base.base.id);
2327	Serge	10178
3031	serge	10179	/* Pipe has the wrong plane attached and the plane is active.
		10180	* Temporarily change the plane mapping and disable everything
		10181	* ... */
		10182	plane = crtc->plane;
		10183	crtc->plane = !plane;
		10184	dev_priv->display.crtc_disable(&crtc->base);
		10185	crtc->plane = plane;
2342	Serge	10186
3031	serge	10187	/* ... and break all links. */
		10188	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10189	base.head) {
		10190	if (connector->encoder->base.crtc != &crtc->base)
		10191	continue;
2327	Serge	10192
3031	serge	10193	intel_connector_break_all_links(connector);
		10194	}
2327	Serge	10195
3031	serge	10196	WARN_ON(crtc->active);
		10197	crtc->base.enabled = false;
		10198	}
2327	Serge	10199
3031	serge	10200	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		10201	crtc->pipe == PIPE_A && !crtc->active) {
		10202	/* BIOS forgot to enable pipe A, this mostly happens after
		10203	* resume. Force-enable the pipe to fix this, the update_dpms
		10204	* call below we restore the pipe to the right state, but leave
		10205	* the required bits on. */
		10206	intel_enable_pipe_a(dev);
		10207	}
2327	Serge	10208
3031	serge	10209	/* Adjust the state of the output pipe according to whether we
		10210	* have active connectors/encoders. */
		10211	intel_crtc_update_dpms(&crtc->base);
2327	Serge	10212
3031	serge	10213	if (crtc->active != crtc->base.enabled) {
		10214	struct intel_encoder *encoder;
2327	Serge	10215
3031	serge	10216	/* This can happen either due to bugs in the get_hw_state
		10217	* functions or because the pipe is force-enabled due to the
		10218	* pipe A quirk. */
		10219	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		10220	crtc->base.base.id,
		10221	crtc->base.enabled ? "enabled" : "disabled",
		10222	crtc->active ? "enabled" : "disabled");
2327	Serge	10223
3031	serge	10224	crtc->base.enabled = crtc->active;
2327	Serge	10225
3031	serge	10226	/* Because we only establish the connector -> encoder ->
		10227	* crtc links if something is active, this means the
		10228	* crtc is now deactivated. Break the links. connector
		10229	* -> encoder links are only establish when things are
		10230	* actually up, hence no need to break them. */
		10231	WARN_ON(crtc->active);
2327	Serge	10232
3031	serge	10233	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		10234	WARN_ON(encoder->connectors_active);
		10235	encoder->base.crtc = NULL;
		10236	}
		10237	}
2327	Serge	10238	}
		10239
3031	serge	10240	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	10241	{
3031	serge	10242	struct intel_connector *connector;
		10243	struct drm_device *dev = encoder->base.dev;
2327	Serge	10244
3031	serge	10245	/* We need to check both for a crtc link (meaning that the
		10246	* encoder is active and trying to read from a pipe) and the
		10247	* pipe itself being active. */
		10248	bool has_active_crtc = encoder->base.crtc &&
		10249	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	10250
3031	serge	10251	if (encoder->connectors_active && !has_active_crtc) {
		10252	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		10253	encoder->base.base.id,
		10254	drm_get_encoder_name(&encoder->base));
2327	Serge	10255
3031	serge	10256	/* Connector is active, but has no active pipe. This is
		10257	* fallout from our resume register restoring. Disable
		10258	* the encoder manually again. */
		10259	if (encoder->base.crtc) {
		10260	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		10261	encoder->base.base.id,
		10262	drm_get_encoder_name(&encoder->base));
		10263	encoder->disable(encoder);
		10264	}
2327	Serge	10265
3031	serge	10266	/* Inconsistent output/port/pipe state happens presumably due to
		10267	* a bug in one of the get_hw_state functions. Or someplace else
		10268	* in our code, like the register restore mess on resume. Clamp
		10269	* things to off as a safer default. */
		10270	list_for_each_entry(connector,
		10271	&dev->mode_config.connector_list,
		10272	base.head) {
		10273	if (connector->encoder != encoder)
		10274	continue;
2327	Serge	10275
3031	serge	10276	intel_connector_break_all_links(connector);
		10277	}
		10278	}
		10279	/* Enabled encoders without active connectors will be fixed in
		10280	* the crtc fixup. */
2327	Serge	10281	}
		10282
3746	Serge	10283	void i915_redisable_vga(struct drm_device *dev)
		10284	{
		10285	struct drm_i915_private *dev_priv = dev->dev_private;
		10286	u32 vga_reg = i915_vgacntrl_reg(dev);
		10287
4104	Serge	10288	/* This function can be called both from intel_modeset_setup_hw_state or
		10289	* at a very early point in our resume sequence, where the power well
		10290	* structures are not yet restored. Since this function is at a very
		10291	* paranoid "someone might have enabled VGA while we were not looking"
		10292	* level, just check if the power well is enabled instead of trying to
		10293	* follow the "don't touch the power well if we don't need it" policy
		10294	* the rest of the driver uses. */
		10295	if (HAS_POWER_WELL(dev) &&
		10296	(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
		10297	return;
		10298
3746	Serge	10299	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		10300	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		10301	i915_disable_vga(dev);
		10302	}
		10303	}
		10304
4104	Serge	10305	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	10306	{
		10307	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10308	enum pipe pipe;
		10309	struct intel_crtc *crtc;
		10310	struct intel_encoder *encoder;
		10311	struct intel_connector *connector;
4104	Serge	10312	int i;
2327	Serge	10313
3746	Serge	10314	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10315	base.head) {
		10316	memset(&crtc->config, 0, sizeof(crtc->config));
2327	Serge	10317
3746	Serge	10318	crtc->active = dev_priv->display.get_pipe_config(crtc,
		10319	&crtc->config);
2327	Serge	10320
3031	serge	10321	crtc->base.enabled = crtc->active;
2330	Serge	10322
3031	serge	10323	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		10324	crtc->base.base.id,
		10325	crtc->active ? "enabled" : "disabled");
2339	Serge	10326	}
2332	Serge	10327
4104	Serge	10328	/* FIXME: Smash this into the new shared dpll infrastructure. */
3480	Serge	10329	if (HAS_DDI(dev))
3243	Serge	10330	intel_ddi_setup_hw_pll_state(dev);
		10331
4104	Serge	10332	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10333	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10334
		10335	pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		10336	pll->active = 0;
		10337	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10338	base.head) {
		10339	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		10340	pll->active++;
		10341	}
		10342	pll->refcount = pll->active;
		10343
		10344	DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
		10345	pll->name, pll->refcount, pll->on);
		10346	}
		10347
3031	serge	10348	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10349	base.head) {
		10350	pipe = 0;
2332	Serge	10351
3031	serge	10352	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	10353	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10354	encoder->base.crtc = &crtc->base;
		10355	if (encoder->get_config)
		10356	encoder->get_config(encoder, &crtc->config);
3031	serge	10357	} else {
		10358	encoder->base.crtc = NULL;
		10359	}
2332	Serge	10360
3031	serge	10361	encoder->connectors_active = false;
		10362	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		10363	encoder->base.base.id,
		10364	drm_get_encoder_name(&encoder->base),
		10365	encoder->base.crtc ? "enabled" : "disabled",
		10366	pipe);
		10367	}
2332	Serge	10368
4104	Serge	10369	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10370	base.head) {
		10371	if (!crtc->active)
		10372	continue;
		10373	if (dev_priv->display.get_clock)
		10374	dev_priv->display.get_clock(crtc,
		10375	&crtc->config);
		10376	}
		10377
3031	serge	10378	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10379	base.head) {
		10380	if (connector->get_hw_state(connector)) {
		10381	connector->base.dpms = DRM_MODE_DPMS_ON;
		10382	connector->encoder->connectors_active = true;
		10383	connector->base.encoder = &connector->encoder->base;
		10384	} else {
		10385	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10386	connector->base.encoder = NULL;
		10387	}
		10388	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		10389	connector->base.base.id,
		10390	drm_get_connector_name(&connector->base),
		10391	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	10392	}
4104	Serge	10393	}
2332	Serge	10394
4104	Serge	10395	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		10396	* and i915 state tracking structures. */
		10397	void intel_modeset_setup_hw_state(struct drm_device *dev,
		10398	bool force_restore)
		10399	{
		10400	struct drm_i915_private *dev_priv = dev->dev_private;
		10401	enum pipe pipe;
		10402	struct drm_plane *plane;
		10403	struct intel_crtc *crtc;
		10404	struct intel_encoder *encoder;
		10405	int i;
		10406
		10407	intel_modeset_readout_hw_state(dev);
		10408
		10409	/*
		10410	* Now that we have the config, copy it to each CRTC struct
		10411	* Note that this could go away if we move to using crtc_config
		10412	* checking everywhere.
		10413	*/
		10414	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10415	base.head) {
		10416	if (crtc->active && i915_fastboot) {
		10417	intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
		10418
		10419	DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
		10420	crtc->base.base.id);
		10421	drm_mode_debug_printmodeline(&crtc->base.mode);
		10422	}
		10423	}
		10424
3031	serge	10425	/* HW state is read out, now we need to sanitize this mess. */
		10426	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10427	base.head) {
		10428	intel_sanitize_encoder(encoder);
2332	Serge	10429	}
		10430
3031	serge	10431	for_each_pipe(pipe) {
		10432	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10433	intel_sanitize_crtc(crtc);
4104	Serge	10434	intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
2332	Serge	10435	}
		10436
4104	Serge	10437	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10438	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10439
		10440	if (!pll->on \|\| pll->active)
		10441	continue;
		10442
		10443	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		10444
		10445	pll->disable(dev_priv, pll);
		10446	pll->on = false;
		10447	}
		10448
3243	Serge	10449	if (force_restore) {
3746	Serge	10450	/*
		10451	* We need to use raw interfaces for restoring state to avoid
		10452	* checking (bogus) intermediate states.
		10453	*/
3243	Serge	10454	for_each_pipe(pipe) {
3746	Serge	10455	struct drm_crtc *crtc =
		10456	dev_priv->pipe_to_crtc_mapping[pipe];
		10457
		10458	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
		10459	crtc->fb);
3243	Serge	10460	}
3746	Serge	10461	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
		10462	intel_plane_restore(plane);
3243	Serge	10463
3746	Serge	10464	i915_redisable_vga(dev);
3243	Serge	10465	} else {
3031	serge	10466	intel_modeset_update_staged_output_state(dev);
3243	Serge	10467	}
2332	Serge	10468
3031	serge	10469	intel_modeset_check_state(dev);
3243	Serge	10470
		10471	drm_mode_config_reset(dev);
2332	Serge	10472	}
		10473
3031	serge	10474	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	10475	{
3031	serge	10476	intel_modeset_init_hw(dev);
2330	Serge	10477
3031	serge	10478	// intel_setup_overlay(dev);
2330	Serge	10479
3243	Serge	10480	intel_modeset_setup_hw_state(dev, false);
2330	Serge	10481	}
		10482
3031	serge	10483	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	10484	{
3031	serge	10485	#if 0
		10486	struct drm_i915_private *dev_priv = dev->dev_private;
		10487	struct drm_crtc *crtc;
2327	Serge	10488
4104	Serge	10489	/*
		10490	* Interrupts and polling as the first thing to avoid creating havoc.
		10491	* Too much stuff here (turning of rps, connectors, ...) would
		10492	* experience fancy races otherwise.
		10493	*/
		10494	drm_irq_uninstall(dev);
		10495	cancel_work_sync(&dev_priv->hotplug_work);
		10496	/*
		10497	* Due to the hpd irq storm handling the hotplug work can re-arm the
		10498	* poll handlers. Hence disable polling after hpd handling is shut down.
		10499	*/
3031	serge	10500	// drm_kms_helper_poll_fini(dev);
4104	Serge	10501
3031	serge	10502	mutex_lock(&dev->struct_mutex);
2327	Serge	10503
3031	serge	10504	// intel_unregister_dsm_handler();
2327	Serge	10505
3031	serge	10506	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		10507	/* Skip inactive CRTCs */
		10508	if (!crtc->fb)
		10509	continue;
2342	Serge	10510
3031	serge	10511	intel_increase_pllclock(crtc);
		10512	}
2342	Serge	10513
3031	serge	10514	intel_disable_fbc(dev);
2342	Serge	10515
3031	serge	10516	intel_disable_gt_powersave(dev);
2342	Serge	10517
3031	serge	10518	ironlake_teardown_rc6(dev);
2327	Serge	10519
3031	serge	10520	mutex_unlock(&dev->struct_mutex);
2327	Serge	10521
4104	Serge	10522	/* flush any delayed tasks or pending work */
		10523	flush_scheduled_work();
2327	Serge	10524
4280	Serge	10525	/* destroy backlight, if any, before the connectors */
		10526	intel_panel_destroy_backlight(dev);
2327	Serge	10527
3031	serge	10528	drm_mode_config_cleanup(dev);
2327	Serge	10529	#endif
		10530	}
		10531
		10532	/*
3031	serge	10533	* Return which encoder is currently attached for connector.
2327	Serge	10534	*/
3031	serge	10535	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	10536	{
3031	serge	10537	return &intel_attached_encoder(connector)->base;
		10538	}
2327	Serge	10539
3031	serge	10540	void intel_connector_attach_encoder(struct intel_connector *connector,
		10541	struct intel_encoder *encoder)
		10542	{
		10543	connector->encoder = encoder;
		10544	drm_mode_connector_attach_encoder(&connector->base,
		10545	&encoder->base);
2327	Serge	10546	}
		10547
		10548	/*
3031	serge	10549	* set vga decode state - true == enable VGA decode
2327	Serge	10550	*/
3031	serge	10551	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	10552	{
2330	Serge	10553	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10554	u16 gmch_ctrl;
2327	Serge	10555
3031	serge	10556	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		10557	if (state)
		10558	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	10559	else
3031	serge	10560	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		10561	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		10562	return 0;
2330	Serge	10563	}
		10564
3031	serge	10565	#ifdef CONFIG_DEBUG_FS
		10566	#include
2327	Serge	10567
3031	serge	10568	struct intel_display_error_state {
4104	Serge	10569
		10570	u32 power_well_driver;
		10571
		10572	int num_transcoders;
		10573
3031	serge	10574	struct intel_cursor_error_state {
		10575	u32 control;
		10576	u32 position;
		10577	u32 base;
		10578	u32 size;
		10579	} cursor[I915_MAX_PIPES];
2327	Serge	10580
3031	serge	10581	struct intel_pipe_error_state {
		10582	u32 source;
		10583	} pipe[I915_MAX_PIPES];
2327	Serge	10584
3031	serge	10585	struct intel_plane_error_state {
		10586	u32 control;
		10587	u32 stride;
		10588	u32 size;
		10589	u32 pos;
		10590	u32 addr;
		10591	u32 surface;
		10592	u32 tile_offset;
		10593	} plane[I915_MAX_PIPES];
4104	Serge	10594
		10595	struct intel_transcoder_error_state {
		10596	enum transcoder cpu_transcoder;
		10597
		10598	u32 conf;
		10599
		10600	u32 htotal;
		10601	u32 hblank;
		10602	u32 hsync;
		10603	u32 vtotal;
		10604	u32 vblank;
		10605	u32 vsync;
		10606	} transcoder[4];
3031	serge	10607	};
2327	Serge	10608
3031	serge	10609	struct intel_display_error_state *
		10610	intel_display_capture_error_state(struct drm_device *dev)
		10611	{
		10612	drm_i915_private_t *dev_priv = dev->dev_private;
		10613	struct intel_display_error_state *error;
4104	Serge	10614	int transcoders[] = {
		10615	TRANSCODER_A,
		10616	TRANSCODER_B,
		10617	TRANSCODER_C,
		10618	TRANSCODER_EDP,
		10619	};
3031	serge	10620	int i;
2327	Serge	10621
4104	Serge	10622	if (INTEL_INFO(dev)->num_pipes == 0)
		10623	return NULL;
		10624
3031	serge	10625	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		10626	if (error == NULL)
		10627	return NULL;
2327	Serge	10628
4104	Serge	10629	if (HAS_POWER_WELL(dev))
		10630	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		10631
3031	serge	10632	for_each_pipe(i) {
3746	Serge	10633	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
3031	serge	10634	error->cursor[i].control = I915_READ(CURCNTR(i));
		10635	error->cursor[i].position = I915_READ(CURPOS(i));
		10636	error->cursor[i].base = I915_READ(CURBASE(i));
3746	Serge	10637	} else {
		10638	error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
		10639	error->cursor[i].position = I915_READ(CURPOS_IVB(i));
		10640	error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		10641	}
2327	Serge	10642
3031	serge	10643	error->plane[i].control = I915_READ(DSPCNTR(i));
		10644	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	10645	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	10646	error->plane[i].size = I915_READ(DSPSIZE(i));
		10647	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	10648	}
		10649	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	10650	error->plane[i].addr = I915_READ(DSPADDR(i));
		10651	if (INTEL_INFO(dev)->gen >= 4) {
		10652	error->plane[i].surface = I915_READ(DSPSURF(i));
		10653	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		10654	}
2327	Serge	10655
3031	serge	10656	error->pipe[i].source = I915_READ(PIPESRC(i));
		10657	}
2327	Serge	10658
4104	Serge	10659	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		10660	if (HAS_DDI(dev_priv->dev))
		10661	error->num_transcoders++; /* Account for eDP. */
		10662
		10663	for (i = 0; i < error->num_transcoders; i++) {
		10664	enum transcoder cpu_transcoder = transcoders[i];
		10665
		10666	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		10667
		10668	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		10669	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		10670	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		10671	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		10672	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		10673	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		10674	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		10675	}
		10676
		10677	/* In the code above we read the registers without checking if the power
		10678	* well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
		10679	* prevent the next I915_WRITE from detecting it and printing an error
		10680	* message. */
		10681	intel_uncore_clear_errors(dev);
		10682
3031	serge	10683	return error;
2330	Serge	10684	}
2327	Serge	10685
4104	Serge	10686	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		10687
3031	serge	10688	void
4104	Serge	10689	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	10690	struct drm_device *dev,
		10691	struct intel_display_error_state *error)
2332	Serge	10692	{
3031	serge	10693	int i;
2330	Serge	10694
4104	Serge	10695	if (!error)
		10696	return;
		10697
		10698	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
		10699	if (HAS_POWER_WELL(dev))
		10700	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		10701	error->power_well_driver);
3031	serge	10702	for_each_pipe(i) {
4104	Serge	10703	err_printf(m, "Pipe [%d]:\n", i);
		10704	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
2332	Serge	10705
4104	Serge	10706	err_printf(m, "Plane [%d]:\n", i);
		10707	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		10708	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	10709	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	10710	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		10711	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	10712	}
		10713	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	10714	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	10715	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	10716	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		10717	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	10718	}
2332	Serge	10719
4104	Serge	10720	err_printf(m, "Cursor [%d]:\n", i);
		10721	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		10722	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		10723	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	10724	}
4104	Serge	10725
		10726	for (i = 0; i < error->num_transcoders; i++) {
		10727	err_printf(m, " CPU transcoder: %c\n",
		10728	transcoder_name(error->transcoder[i].cpu_transcoder));
		10729	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		10730	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		10731	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		10732	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		10733	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		10734	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		10735	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		10736	}
2327	Serge	10737	}
3031	serge	10738	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 4392