WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
3746	Serge	27	//#include
2327	Serge	28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
3746	Serge	33	#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
4104	Serge	44	#define MAX_ERRNO 4095
2327	Serge	45	phys_addr_t get_bus_addr(void);
		46
2342	Serge	47	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	48	static void intel_increase_pllclock(struct drm_crtc *crtc);
3243	Serge	49	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	50
4104	Serge	51	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		52	struct intel_crtc_config *pipe_config);
		53	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		54	struct intel_crtc_config *pipe_config);
2327	Serge	55
4104	Serge	56	static int intel_set_mode(struct drm_crtc crtc, struct drm_display_mode mode,
		57	int x, int y, struct drm_framebuffer *old_fb);
		58
		59
2327	Serge	60	typedef struct {
		61	int min, max;
		62	} intel_range_t;
		63
		64	typedef struct {
		65	int dot_limit;
		66	int p2_slow, p2_fast;
		67	} intel_p2_t;
		68
		69	typedef struct intel_limit intel_limit_t;
		70	struct intel_limit {
		71	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		72	intel_p2_t p2;
		73	};
		74
		75	/* FDI */
		76	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		77
3243	Serge	78	int
		79	intel_pch_rawclk(struct drm_device *dev)
		80	{
		81	struct drm_i915_private *dev_priv = dev->dev_private;
		82
		83	WARN_ON(!HAS_PCH_SPLIT(dev));
		84
		85	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
		86	}
		87
2327	Serge	88	static inline u32 /* units of 100MHz */
		89	intel_fdi_link_freq(struct drm_device *dev)
		90	{
		91	if (IS_GEN5(dev)) {
		92	struct drm_i915_private *dev_priv = dev->dev_private;
		93	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		94	} else
		95	return 27;
		96	}
		97
4104	Serge	98	static const intel_limit_t intel_limits_i8xx_dac = {
		99	.dot = { .min = 25000, .max = 350000 },
		100	.vco = { .min = 930000, .max = 1400000 },
		101	.n = { .min = 3, .max = 16 },
		102	.m = { .min = 96, .max = 140 },
		103	.m1 = { .min = 18, .max = 26 },
		104	.m2 = { .min = 6, .max = 16 },
		105	.p = { .min = 4, .max = 128 },
		106	.p1 = { .min = 2, .max = 33 },
		107	.p2 = { .dot_limit = 165000,
		108	.p2_slow = 4, .p2_fast = 2 },
		109	};
		110
2327	Serge	111	static const intel_limit_t intel_limits_i8xx_dvo = {
		112	.dot = { .min = 25000, .max = 350000 },
		113	.vco = { .min = 930000, .max = 1400000 },
		114	.n = { .min = 3, .max = 16 },
		115	.m = { .min = 96, .max = 140 },
		116	.m1 = { .min = 18, .max = 26 },
		117	.m2 = { .min = 6, .max = 16 },
		118	.p = { .min = 4, .max = 128 },
		119	.p1 = { .min = 2, .max = 33 },
		120	.p2 = { .dot_limit = 165000,
4104	Serge	121	.p2_slow = 4, .p2_fast = 4 },
2327	Serge	122	};
		123
		124	static const intel_limit_t intel_limits_i8xx_lvds = {
		125	.dot = { .min = 25000, .max = 350000 },
		126	.vco = { .min = 930000, .max = 1400000 },
		127	.n = { .min = 3, .max = 16 },
		128	.m = { .min = 96, .max = 140 },
		129	.m1 = { .min = 18, .max = 26 },
		130	.m2 = { .min = 6, .max = 16 },
		131	.p = { .min = 4, .max = 128 },
		132	.p1 = { .min = 1, .max = 6 },
		133	.p2 = { .dot_limit = 165000,
		134	.p2_slow = 14, .p2_fast = 7 },
		135	};
		136
		137	static const intel_limit_t intel_limits_i9xx_sdvo = {
		138	.dot = { .min = 20000, .max = 400000 },
		139	.vco = { .min = 1400000, .max = 2800000 },
		140	.n = { .min = 1, .max = 6 },
		141	.m = { .min = 70, .max = 120 },
3480	Serge	142	.m1 = { .min = 8, .max = 18 },
		143	.m2 = { .min = 3, .max = 7 },
2327	Serge	144	.p = { .min = 5, .max = 80 },
		145	.p1 = { .min = 1, .max = 8 },
		146	.p2 = { .dot_limit = 200000,
		147	.p2_slow = 10, .p2_fast = 5 },
		148	};
		149
		150	static const intel_limit_t intel_limits_i9xx_lvds = {
		151	.dot = { .min = 20000, .max = 400000 },
		152	.vco = { .min = 1400000, .max = 2800000 },
		153	.n = { .min = 1, .max = 6 },
		154	.m = { .min = 70, .max = 120 },
3480	Serge	155	.m1 = { .min = 8, .max = 18 },
		156	.m2 = { .min = 3, .max = 7 },
2327	Serge	157	.p = { .min = 7, .max = 98 },
		158	.p1 = { .min = 1, .max = 8 },
		159	.p2 = { .dot_limit = 112000,
		160	.p2_slow = 14, .p2_fast = 7 },
		161	};
		162
		163
		164	static const intel_limit_t intel_limits_g4x_sdvo = {
		165	.dot = { .min = 25000, .max = 270000 },
		166	.vco = { .min = 1750000, .max = 3500000},
		167	.n = { .min = 1, .max = 4 },
		168	.m = { .min = 104, .max = 138 },
		169	.m1 = { .min = 17, .max = 23 },
		170	.m2 = { .min = 5, .max = 11 },
		171	.p = { .min = 10, .max = 30 },
		172	.p1 = { .min = 1, .max = 3},
		173	.p2 = { .dot_limit = 270000,
		174	.p2_slow = 10,
		175	.p2_fast = 10
		176	},
		177	};
		178
		179	static const intel_limit_t intel_limits_g4x_hdmi = {
		180	.dot = { .min = 22000, .max = 400000 },
		181	.vco = { .min = 1750000, .max = 3500000},
		182	.n = { .min = 1, .max = 4 },
		183	.m = { .min = 104, .max = 138 },
		184	.m1 = { .min = 16, .max = 23 },
		185	.m2 = { .min = 5, .max = 11 },
		186	.p = { .min = 5, .max = 80 },
		187	.p1 = { .min = 1, .max = 8},
		188	.p2 = { .dot_limit = 165000,
		189	.p2_slow = 10, .p2_fast = 5 },
		190	};
		191
		192	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		193	.dot = { .min = 20000, .max = 115000 },
		194	.vco = { .min = 1750000, .max = 3500000 },
		195	.n = { .min = 1, .max = 3 },
		196	.m = { .min = 104, .max = 138 },
		197	.m1 = { .min = 17, .max = 23 },
		198	.m2 = { .min = 5, .max = 11 },
		199	.p = { .min = 28, .max = 112 },
		200	.p1 = { .min = 2, .max = 8 },
		201	.p2 = { .dot_limit = 0,
		202	.p2_slow = 14, .p2_fast = 14
		203	},
		204	};
		205
		206	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		207	.dot = { .min = 80000, .max = 224000 },
		208	.vco = { .min = 1750000, .max = 3500000 },
		209	.n = { .min = 1, .max = 3 },
		210	.m = { .min = 104, .max = 138 },
		211	.m1 = { .min = 17, .max = 23 },
		212	.m2 = { .min = 5, .max = 11 },
		213	.p = { .min = 14, .max = 42 },
		214	.p1 = { .min = 2, .max = 6 },
		215	.p2 = { .dot_limit = 0,
		216	.p2_slow = 7, .p2_fast = 7
		217	},
		218	};
		219
		220	static const intel_limit_t intel_limits_pineview_sdvo = {
		221	.dot = { .min = 20000, .max = 400000},
		222	.vco = { .min = 1700000, .max = 3500000 },
		223	/* Pineview's Ncounter is a ring counter */
		224	.n = { .min = 3, .max = 6 },
		225	.m = { .min = 2, .max = 256 },
		226	/* Pineview only has one combined m divider, which we treat as m2. */
		227	.m1 = { .min = 0, .max = 0 },
		228	.m2 = { .min = 0, .max = 254 },
		229	.p = { .min = 5, .max = 80 },
		230	.p1 = { .min = 1, .max = 8 },
		231	.p2 = { .dot_limit = 200000,
		232	.p2_slow = 10, .p2_fast = 5 },
		233	};
		234
		235	static const intel_limit_t intel_limits_pineview_lvds = {
		236	.dot = { .min = 20000, .max = 400000 },
		237	.vco = { .min = 1700000, .max = 3500000 },
		238	.n = { .min = 3, .max = 6 },
		239	.m = { .min = 2, .max = 256 },
		240	.m1 = { .min = 0, .max = 0 },
		241	.m2 = { .min = 0, .max = 254 },
		242	.p = { .min = 7, .max = 112 },
		243	.p1 = { .min = 1, .max = 8 },
		244	.p2 = { .dot_limit = 112000,
		245	.p2_slow = 14, .p2_fast = 14 },
		246	};
		247
		248	/* Ironlake / Sandybridge
		249	*
		250	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		251	* the range value for them is (actual_value - 2).
		252	*/
		253	static const intel_limit_t intel_limits_ironlake_dac = {
		254	.dot = { .min = 25000, .max = 350000 },
		255	.vco = { .min = 1760000, .max = 3510000 },
		256	.n = { .min = 1, .max = 5 },
		257	.m = { .min = 79, .max = 127 },
		258	.m1 = { .min = 12, .max = 22 },
		259	.m2 = { .min = 5, .max = 9 },
		260	.p = { .min = 5, .max = 80 },
		261	.p1 = { .min = 1, .max = 8 },
		262	.p2 = { .dot_limit = 225000,
		263	.p2_slow = 10, .p2_fast = 5 },
		264	};
		265
		266	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		267	.dot = { .min = 25000, .max = 350000 },
		268	.vco = { .min = 1760000, .max = 3510000 },
		269	.n = { .min = 1, .max = 3 },
		270	.m = { .min = 79, .max = 118 },
		271	.m1 = { .min = 12, .max = 22 },
		272	.m2 = { .min = 5, .max = 9 },
		273	.p = { .min = 28, .max = 112 },
		274	.p1 = { .min = 2, .max = 8 },
		275	.p2 = { .dot_limit = 225000,
		276	.p2_slow = 14, .p2_fast = 14 },
		277	};
		278
		279	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		280	.dot = { .min = 25000, .max = 350000 },
		281	.vco = { .min = 1760000, .max = 3510000 },
		282	.n = { .min = 1, .max = 3 },
		283	.m = { .min = 79, .max = 127 },
		284	.m1 = { .min = 12, .max = 22 },
		285	.m2 = { .min = 5, .max = 9 },
		286	.p = { .min = 14, .max = 56 },
		287	.p1 = { .min = 2, .max = 8 },
		288	.p2 = { .dot_limit = 225000,
		289	.p2_slow = 7, .p2_fast = 7 },
		290	};
		291
		292	/* LVDS 100mhz refclk limits. */
		293	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		294	.dot = { .min = 25000, .max = 350000 },
		295	.vco = { .min = 1760000, .max = 3510000 },
		296	.n = { .min = 1, .max = 2 },
		297	.m = { .min = 79, .max = 126 },
		298	.m1 = { .min = 12, .max = 22 },
		299	.m2 = { .min = 5, .max = 9 },
		300	.p = { .min = 28, .max = 112 },
2342	Serge	301	.p1 = { .min = 2, .max = 8 },
2327	Serge	302	.p2 = { .dot_limit = 225000,
		303	.p2_slow = 14, .p2_fast = 14 },
		304	};
		305
		306	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		307	.dot = { .min = 25000, .max = 350000 },
		308	.vco = { .min = 1760000, .max = 3510000 },
		309	.n = { .min = 1, .max = 3 },
		310	.m = { .min = 79, .max = 126 },
		311	.m1 = { .min = 12, .max = 22 },
		312	.m2 = { .min = 5, .max = 9 },
		313	.p = { .min = 14, .max = 42 },
2342	Serge	314	.p1 = { .min = 2, .max = 6 },
2327	Serge	315	.p2 = { .dot_limit = 225000,
		316	.p2_slow = 7, .p2_fast = 7 },
		317	};
		318
3031	serge	319	static const intel_limit_t intel_limits_vlv_dac = {
		320	.dot = { .min = 25000, .max = 270000 },
		321	.vco = { .min = 4000000, .max = 6000000 },
		322	.n = { .min = 1, .max = 7 },
		323	.m = { .min = 22, .max = 450 }, /* guess */
		324	.m1 = { .min = 2, .max = 3 },
		325	.m2 = { .min = 11, .max = 156 },
		326	.p = { .min = 10, .max = 30 },
4104	Serge	327	.p1 = { .min = 1, .max = 3 },
3031	serge	328	.p2 = { .dot_limit = 270000,
		329	.p2_slow = 2, .p2_fast = 20 },
		330	};
		331
		332	static const intel_limit_t intel_limits_vlv_hdmi = {
4104	Serge	333	.dot = { .min = 25000, .max = 270000 },
		334	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	335	.n = { .min = 1, .max = 7 },
		336	.m = { .min = 60, .max = 300 }, /* guess */
		337	.m1 = { .min = 2, .max = 3 },
		338	.m2 = { .min = 11, .max = 156 },
		339	.p = { .min = 10, .max = 30 },
		340	.p1 = { .min = 2, .max = 3 },
		341	.p2 = { .dot_limit = 270000,
		342	.p2_slow = 2, .p2_fast = 20 },
		343	};
		344
		345	static const intel_limit_t intel_limits_vlv_dp = {
3243	Serge	346	.dot = { .min = 25000, .max = 270000 },
		347	.vco = { .min = 4000000, .max = 6000000 },
3031	serge	348	.n = { .min = 1, .max = 7 },
3243	Serge	349	.m = { .min = 22, .max = 450 },
3031	serge	350	.m1 = { .min = 2, .max = 3 },
		351	.m2 = { .min = 11, .max = 156 },
		352	.p = { .min = 10, .max = 30 },
4104	Serge	353	.p1 = { .min = 1, .max = 3 },
3031	serge	354	.p2 = { .dot_limit = 270000,
		355	.p2_slow = 2, .p2_fast = 20 },
		356	};
		357
2327	Serge	358	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		359	int refclk)
		360	{
		361	struct drm_device *dev = crtc->dev;
		362	const intel_limit_t *limit;
		363
		364	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	365	if (intel_is_dual_link_lvds(dev)) {
2327	Serge	366	if (refclk == 100000)
		367	limit = &intel_limits_ironlake_dual_lvds_100m;
		368	else
		369	limit = &intel_limits_ironlake_dual_lvds;
		370	} else {
		371	if (refclk == 100000)
		372	limit = &intel_limits_ironlake_single_lvds_100m;
		373	else
		374	limit = &intel_limits_ironlake_single_lvds;
		375	}
4104	Serge	376	} else
2327	Serge	377	limit = &intel_limits_ironlake_dac;
		378
		379	return limit;
		380	}
		381
		382	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		383	{
		384	struct drm_device *dev = crtc->dev;
		385	const intel_limit_t *limit;
		386
		387	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	388	if (intel_is_dual_link_lvds(dev))
2327	Serge	389	limit = &intel_limits_g4x_dual_channel_lvds;
		390	else
		391	limit = &intel_limits_g4x_single_channel_lvds;
		392	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		393	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		394	limit = &intel_limits_g4x_hdmi;
		395	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		396	limit = &intel_limits_g4x_sdvo;
		397	} else /* The option is for other outputs */
		398	limit = &intel_limits_i9xx_sdvo;
		399
		400	return limit;
		401	}
		402
		403	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		404	{
		405	struct drm_device *dev = crtc->dev;
		406	const intel_limit_t *limit;
		407
		408	if (HAS_PCH_SPLIT(dev))
		409	limit = intel_ironlake_limit(crtc, refclk);
		410	else if (IS_G4X(dev)) {
		411	limit = intel_g4x_limit(crtc);
		412	} else if (IS_PINEVIEW(dev)) {
		413	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		414	limit = &intel_limits_pineview_lvds;
		415	else
		416	limit = &intel_limits_pineview_sdvo;
3031	serge	417	} else if (IS_VALLEYVIEW(dev)) {
		418	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		419	limit = &intel_limits_vlv_dac;
		420	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		421	limit = &intel_limits_vlv_hdmi;
		422	else
		423	limit = &intel_limits_vlv_dp;
2327	Serge	424	} else if (!IS_GEN2(dev)) {
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		426	limit = &intel_limits_i9xx_lvds;
		427	else
		428	limit = &intel_limits_i9xx_sdvo;
		429	} else {
		430	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		431	limit = &intel_limits_i8xx_lvds;
4104	Serge	432	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
		433	limit = &intel_limits_i8xx_dvo;
2327	Serge	434	else
4104	Serge	435	limit = &intel_limits_i8xx_dac;
2327	Serge	436	}
		437	return limit;
		438	}
		439
		440	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		441	static void pineview_clock(int refclk, intel_clock_t *clock)
		442	{
		443	clock->m = clock->m2 + 2;
		444	clock->p = clock->p1 * clock->p2;
		445	clock->vco = refclk * clock->m / clock->n;
		446	clock->dot = clock->vco / clock->p;
		447	}
		448
4104	Serge	449	static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
2327	Serge	450	{
4104	Serge	451	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
		452	}
		453
		454	static void i9xx_clock(int refclk, intel_clock_t *clock)
		455	{
		456	clock->m = i9xx_dpll_compute_m(clock);
2327	Serge	457	clock->p = clock->p1 * clock->p2;
		458	clock->vco = refclk * clock->m / (clock->n + 2);
		459	clock->dot = clock->vco / clock->p;
		460	}
		461
		462	/**
		463	* Returns whether any output on the specified pipe is of the specified type
		464	*/
		465	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		466	{
		467	struct drm_device *dev = crtc->dev;
		468	struct intel_encoder *encoder;
		469
3031	serge	470	for_each_encoder_on_crtc(dev, crtc, encoder)
		471	if (encoder->type == type)
2327	Serge	472	return true;
		473
		474	return false;
		475	}
		476
		477	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		478	/**
		479	* Returns whether the given set of divisors are valid for a given refclk with
		480	* the given connectors.
		481	*/
		482
		483	static bool intel_PLL_is_valid(struct drm_device *dev,
		484	const intel_limit_t *limit,
		485	const intel_clock_t *clock)
		486	{
		487	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	488	INTELPllInvalid("p1 out of range\n");
2327	Serge	489	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	490	INTELPllInvalid("p out of range\n");
2327	Serge	491	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	492	INTELPllInvalid("m2 out of range\n");
2327	Serge	493	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	494	INTELPllInvalid("m1 out of range\n");
2327	Serge	495	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	496	INTELPllInvalid("m1 <= m2\n");
2327	Serge	497	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	498	INTELPllInvalid("m out of range\n");
2327	Serge	499	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	500	INTELPllInvalid("n out of range\n");
2327	Serge	501	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	502	INTELPllInvalid("vco out of range\n");
2327	Serge	503	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		504	* connector, etc., rather than just a single range.
		505	*/
		506	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	507	INTELPllInvalid("dot out of range\n");
2327	Serge	508
		509	return true;
		510	}
		511
		512	static bool
4104	Serge	513	i9xx_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	514	int target, int refclk, intel_clock_t *match_clock,
		515	intel_clock_t *best_clock)
2327	Serge	516	{
		517	struct drm_device *dev = crtc->dev;
		518	intel_clock_t clock;
		519	int err = target;
		520
3480	Serge	521	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2327	Serge	522	/*
3480	Serge	523	* For LVDS just rely on its current settings for dual-channel.
		524	* We haven't figured out how to reliably set up different
		525	* single/dual channel state, if we even can.
2327	Serge	526	*/
3480	Serge	527	if (intel_is_dual_link_lvds(dev))
2327	Serge	528	clock.p2 = limit->p2.p2_fast;
		529	else
		530	clock.p2 = limit->p2.p2_slow;
		531	} else {
		532	if (target < limit->p2.dot_limit)
		533	clock.p2 = limit->p2.p2_slow;
		534	else
		535	clock.p2 = limit->p2.p2_fast;
		536	}
		537
2342	Serge	538	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	539
		540	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		541	clock.m1++) {
		542	for (clock.m2 = limit->m2.min;
		543	clock.m2 <= limit->m2.max; clock.m2++) {
4104	Serge	544	if (clock.m2 >= clock.m1)
2327	Serge	545	break;
		546	for (clock.n = limit->n.min;
		547	clock.n <= limit->n.max; clock.n++) {
		548	for (clock.p1 = limit->p1.min;
		549	clock.p1 <= limit->p1.max; clock.p1++) {
		550	int this_err;
		551
4104	Serge	552	i9xx_clock(refclk, &clock);
2327	Serge	553	if (!intel_PLL_is_valid(dev, limit,
		554	&clock))
		555	continue;
3031	serge	556	if (match_clock &&
		557	clock.p != match_clock->p)
		558	continue;
2327	Serge	559
		560	this_err = abs(clock.dot - target);
		561	if (this_err < err) {
		562	*best_clock = clock;
		563	err = this_err;
		564	}
		565	}
		566	}
		567	}
		568	}
		569
		570	return (err != target);
		571	}
		572
		573	static bool
4104	Serge	574	pnv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
		575	int target, int refclk, intel_clock_t *match_clock,
		576	intel_clock_t *best_clock)
		577	{
		578	struct drm_device *dev = crtc->dev;
		579	intel_clock_t clock;
		580	int err = target;
		581
		582	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		583	/*
		584	* For LVDS just rely on its current settings for dual-channel.
		585	* We haven't figured out how to reliably set up different
		586	* single/dual channel state, if we even can.
		587	*/
		588	if (intel_is_dual_link_lvds(dev))
		589	clock.p2 = limit->p2.p2_fast;
		590	else
		591	clock.p2 = limit->p2.p2_slow;
		592	} else {
		593	if (target < limit->p2.dot_limit)
		594	clock.p2 = limit->p2.p2_slow;
		595	else
		596	clock.p2 = limit->p2.p2_fast;
		597	}
		598
		599	memset(best_clock, 0, sizeof(*best_clock));
		600
		601	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		602	clock.m1++) {
		603	for (clock.m2 = limit->m2.min;
		604	clock.m2 <= limit->m2.max; clock.m2++) {
		605	for (clock.n = limit->n.min;
		606	clock.n <= limit->n.max; clock.n++) {
		607	for (clock.p1 = limit->p1.min;
		608	clock.p1 <= limit->p1.max; clock.p1++) {
		609	int this_err;
		610
		611	pineview_clock(refclk, &clock);
		612	if (!intel_PLL_is_valid(dev, limit,
		613	&clock))
		614	continue;
		615	if (match_clock &&
		616	clock.p != match_clock->p)
		617	continue;
		618
		619	this_err = abs(clock.dot - target);
		620	if (this_err < err) {
		621	*best_clock = clock;
		622	err = this_err;
		623	}
		624	}
		625	}
		626	}
		627	}
		628
		629	return (err != target);
		630	}
		631
		632	static bool
		633	g4x_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	634	int target, int refclk, intel_clock_t *match_clock,
		635	intel_clock_t *best_clock)
2327	Serge	636	{
		637	struct drm_device *dev = crtc->dev;
		638	intel_clock_t clock;
		639	int max_n;
		640	bool found;
		641	/* approximately equals target * 0.00585 */
		642	int err_most = (target >> 8) + (target >> 9);
		643	found = false;
		644
		645	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3480	Serge	646	if (intel_is_dual_link_lvds(dev))
2327	Serge	647	clock.p2 = limit->p2.p2_fast;
		648	else
		649	clock.p2 = limit->p2.p2_slow;
		650	} else {
		651	if (target < limit->p2.dot_limit)
		652	clock.p2 = limit->p2.p2_slow;
		653	else
		654	clock.p2 = limit->p2.p2_fast;
		655	}
		656
		657	memset(best_clock, 0, sizeof(*best_clock));
		658	max_n = limit->n.max;
		659	/* based on hardware requirement, prefer smaller n to precision */
		660	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		661	/* based on hardware requirement, prefere larger m1,m2 */
		662	for (clock.m1 = limit->m1.max;
		663	clock.m1 >= limit->m1.min; clock.m1--) {
		664	for (clock.m2 = limit->m2.max;
		665	clock.m2 >= limit->m2.min; clock.m2--) {
		666	for (clock.p1 = limit->p1.max;
		667	clock.p1 >= limit->p1.min; clock.p1--) {
		668	int this_err;
		669
4104	Serge	670	i9xx_clock(refclk, &clock);
2327	Serge	671	if (!intel_PLL_is_valid(dev, limit,
		672	&clock))
		673	continue;
		674
		675	this_err = abs(clock.dot - target);
		676	if (this_err < err_most) {
		677	*best_clock = clock;
		678	err_most = this_err;
		679	max_n = clock.n;
		680	found = true;
		681	}
		682	}
		683	}
		684	}
		685	}
		686	return found;
		687	}
		688
		689	static bool
4104	Serge	690	vlv_find_best_dpll(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	691	int target, int refclk, intel_clock_t *match_clock,
		692	intel_clock_t *best_clock)
		693	{
		694	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		695	u32 m, n, fastclk;
4104	Serge	696	u32 updrate, minupdate, p;
3031	serge	697	unsigned long bestppm, ppm, absppm;
		698	int dotclk, flag;
2327	Serge	699
3031	serge	700	flag = 0;
		701	dotclk = target * 1000;
		702	bestppm = 1000000;
		703	ppm = absppm = 0;
		704	fastclk = dotclk / (2*100);
		705	updrate = 0;
		706	minupdate = 19200;
		707	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		708	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		709
		710	/* based on hardware requirement, prefer smaller n to precision */
		711	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		712	updrate = refclk / n;
		713	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		714	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		715	if (p2 > 10)
		716	p2 = p2 - 1;
		717	p = p1 * p2;
		718	/* based on hardware requirement, prefer bigger m1,m2 values */
		719	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		720	m2 = (((2(fastclk p * n / m1 )) +
		721	refclk) / (2*refclk));
		722	m = m1 * m2;
		723	vco = updrate * m;
		724	if (vco >= limit->vco.min && vco < limit->vco.max) {
		725	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		726	absppm = (ppm > 0) ? ppm : (-ppm);
		727	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		728	bestppm = 0;
		729	flag = 1;
		730	}
		731	if (absppm < bestppm - 10) {
		732	bestppm = absppm;
		733	flag = 1;
		734	}
		735	if (flag) {
		736	bestn = n;
		737	bestm1 = m1;
		738	bestm2 = m2;
		739	bestp1 = p1;
		740	bestp2 = p2;
		741	flag = 0;
		742	}
		743	}
		744	}
		745	}
		746	}
		747	}
		748	best_clock->n = bestn;
		749	best_clock->m1 = bestm1;
		750	best_clock->m2 = bestm2;
		751	best_clock->p1 = bestp1;
		752	best_clock->p2 = bestp2;
		753
		754	return true;
		755	}
		756
3243	Serge	757	enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
		758	enum pipe pipe)
		759	{
		760	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		762
3746	Serge	763	return intel_crtc->config.cpu_transcoder;
3243	Serge	764	}
		765
3031	serge	766	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		767	{
		768	struct drm_i915_private *dev_priv = dev->dev_private;
		769	u32 frame, frame_reg = PIPEFRAME(pipe);
		770
		771	frame = I915_READ(frame_reg);
		772
		773	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		774	DRM_DEBUG_KMS("vblank wait timed out\n");
		775	}
		776
2327	Serge	777	/**
		778	* intel_wait_for_vblank - wait for vblank on a given pipe
		779	* @dev: drm device
		780	* @pipe: pipe to wait for
		781	*
		782	* Wait for vblank to occur on a given pipe. Needed for various bits of
		783	* mode setting code.
		784	*/
		785	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		786	{
		787	struct drm_i915_private *dev_priv = dev->dev_private;
		788	int pipestat_reg = PIPESTAT(pipe);
		789
3031	serge	790	if (INTEL_INFO(dev)->gen >= 5) {
		791	ironlake_wait_for_vblank(dev, pipe);
		792	return;
		793	}
		794
2327	Serge	795	/* Clear existing vblank status. Note this will clear any other
		796	* sticky status fields as well.
		797	*
		798	* This races with i915_driver_irq_handler() with the result
		799	* that either function could miss a vblank event. Here it is not
		800	* fatal, as we will either wait upon the next vblank interrupt or
		801	* timeout. Generally speaking intel_wait_for_vblank() is only
		802	* called during modeset at which time the GPU should be idle and
		803	* should not be performing page flips and thus not waiting on
		804	* vblanks...
		805	* Currently, the result of us stealing a vblank from the irq
		806	* handler is that a single frame will be skipped during swapbuffers.
		807	*/
		808	I915_WRITE(pipestat_reg,
		809	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		810
		811	/* Wait for vblank interrupt bit to set */
		812	if (wait_for(I915_READ(pipestat_reg) &
		813	PIPE_VBLANK_INTERRUPT_STATUS,
		814	50))
		815	DRM_DEBUG_KMS("vblank wait timed out\n");
		816	}
		817
		818	/*
		819	* intel_wait_for_pipe_off - wait for pipe to turn off
		820	* @dev: drm device
		821	* @pipe: pipe to wait for
		822	*
		823	* After disabling a pipe, we can't wait for vblank in the usual way,
		824	* spinning on the vblank interrupt status bit, since we won't actually
		825	* see an interrupt when the pipe is disabled.
		826	*
		827	* On Gen4 and above:
		828	* wait for the pipe register state bit to turn off
		829	*
		830	* Otherwise:
		831	* wait for the display line value to settle (it usually
		832	* ends up stopping at the start of the next frame).
		833	*
		834	*/
		835	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		836	{
		837	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	838	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		839	pipe);
2327	Serge	840
		841	if (INTEL_INFO(dev)->gen >= 4) {
3243	Serge	842	int reg = PIPECONF(cpu_transcoder);
2327	Serge	843
		844	/* Wait for the Pipe State to go off */
		845	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		846	100))
3031	serge	847	WARN(1, "pipe_off wait timed out\n");
2327	Serge	848	} else {
3031	serge	849	u32 last_line, line_mask;
2327	Serge	850	int reg = PIPEDSL(pipe);
4104	Serge	851	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	852
3031	serge	853	if (IS_GEN2(dev))
		854	line_mask = DSL_LINEMASK_GEN2;
		855	else
		856	line_mask = DSL_LINEMASK_GEN3;
		857
2327	Serge	858	/* Wait for the display line to settle */
		859	do {
3031	serge	860	last_line = I915_READ(reg) & line_mask;
2327	Serge	861	mdelay(5);
3031	serge	862	} while (((I915_READ(reg) & line_mask) != last_line) &&
		863	time_after(timeout, GetTimerTicks()));
		864	if (time_after(GetTimerTicks(), timeout))
		865	WARN(1, "pipe_off wait timed out\n");
2327	Serge	866	}
		867	}
		868
3480	Serge	869	/*
		870	* ibx_digital_port_connected - is the specified port connected?
		871	* @dev_priv: i915 private structure
		872	* @port: the port to test
		873	*
		874	* Returns true if @port is connected, false otherwise.
		875	*/
		876	bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
		877	struct intel_digital_port *port)
		878	{
		879	u32 bit;
		880
		881	if (HAS_PCH_IBX(dev_priv->dev)) {
		882	switch(port->port) {
		883	case PORT_B:
		884	bit = SDE_PORTB_HOTPLUG;
		885	break;
		886	case PORT_C:
		887	bit = SDE_PORTC_HOTPLUG;
		888	break;
		889	case PORT_D:
		890	bit = SDE_PORTD_HOTPLUG;
		891	break;
		892	default:
		893	return true;
		894	}
		895	} else {
		896	switch(port->port) {
		897	case PORT_B:
		898	bit = SDE_PORTB_HOTPLUG_CPT;
		899	break;
		900	case PORT_C:
		901	bit = SDE_PORTC_HOTPLUG_CPT;
		902	break;
		903	case PORT_D:
		904	bit = SDE_PORTD_HOTPLUG_CPT;
		905	break;
		906	default:
		907	return true;
		908	}
		909	}
		910
		911	return I915_READ(SDEISR) & bit;
		912	}
		913
2327	Serge	914	static const char *state_string(bool enabled)
		915	{
		916	return enabled ? "on" : "off";
		917	}
		918
		919	/* Only for pre-ILK configs */
4104	Serge	920	void assert_pll(struct drm_i915_private *dev_priv,
2327	Serge	921	enum pipe pipe, bool state)
		922	{
		923	int reg;
		924	u32 val;
		925	bool cur_state;
		926
		927	reg = DPLL(pipe);
		928	val = I915_READ(reg);
		929	cur_state = !!(val & DPLL_VCO_ENABLE);
		930	WARN(cur_state != state,
		931	"PLL state assertion failure (expected %s, current %s)\n",
		932	state_string(state), state_string(cur_state));
		933	}
		934
4104	Serge	935	struct intel_shared_dpll *
		936	intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
		937	{
		938	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		939
		940	if (crtc->config.shared_dpll < 0)
		941	return NULL;
		942
		943	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
		944	}
		945
2327	Serge	946	/* For ILK+ */
4104	Serge	947	void assert_shared_dpll(struct drm_i915_private *dev_priv,
		948	struct intel_shared_dpll *pll,
3031	serge	949	bool state)
2327	Serge	950	{
		951	bool cur_state;
4104	Serge	952	struct intel_dpll_hw_state hw_state;
2327	Serge	953
3031	serge	954	if (HAS_PCH_LPT(dev_priv->dev)) {
		955	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		956	return;
		957	}
2342	Serge	958
3031	serge	959	if (WARN (!pll,
4104	Serge	960	"asserting DPLL %s with no DPLL\n", state_string(state)))
3031	serge	961	return;
2342	Serge	962
4104	Serge	963	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
3031	serge	964	WARN(cur_state != state,
4104	Serge	965	"%s assertion failure (expected %s, current %s)\n",
		966	pll->name, state_string(state), state_string(cur_state));
2327	Serge	967	}
		968
		969	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		970	enum pipe pipe, bool state)
		971	{
		972	int reg;
		973	u32 val;
		974	bool cur_state;
3243	Serge	975	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		976	pipe);
2327	Serge	977
3480	Serge	978	if (HAS_DDI(dev_priv->dev)) {
		979	/* DDI does not have a specific FDI_TX register */
3243	Serge	980	reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3031	serge	981	val = I915_READ(reg);
3243	Serge	982	cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
3031	serge	983	} else {
2327	Serge	984	reg = FDI_TX_CTL(pipe);
		985	val = I915_READ(reg);
		986	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	987	}
2327	Serge	988	WARN(cur_state != state,
		989	"FDI TX state assertion failure (expected %s, current %s)\n",
		990	state_string(state), state_string(cur_state));
		991	}
		992	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		993	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		994
		995	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		996	enum pipe pipe, bool state)
		997	{
		998	int reg;
		999	u32 val;
		1000	bool cur_state;
		1001
		1002	reg = FDI_RX_CTL(pipe);
		1003	val = I915_READ(reg);
		1004	cur_state = !!(val & FDI_RX_ENABLE);
		1005	WARN(cur_state != state,
		1006	"FDI RX state assertion failure (expected %s, current %s)\n",
		1007	state_string(state), state_string(cur_state));
		1008	}
		1009	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1010	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1011
		1012	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1013	enum pipe pipe)
		1014	{
		1015	int reg;
		1016	u32 val;
		1017
		1018	/* ILK FDI PLL is always enabled */
		1019	if (dev_priv->info->gen == 5)
		1020	return;
		1021
3031	serge	1022	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
3480	Serge	1023	if (HAS_DDI(dev_priv->dev))
3031	serge	1024	return;
		1025
2327	Serge	1026	reg = FDI_TX_CTL(pipe);
		1027	val = I915_READ(reg);
		1028	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1029	}
		1030
4104	Serge	1031	void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		1032	enum pipe pipe, bool state)
2327	Serge	1033	{
		1034	int reg;
		1035	u32 val;
4104	Serge	1036	bool cur_state;
2327	Serge	1037
		1038	reg = FDI_RX_CTL(pipe);
		1039	val = I915_READ(reg);
4104	Serge	1040	cur_state = !!(val & FDI_RX_PLL_ENABLE);
		1041	WARN(cur_state != state,
		1042	"FDI RX PLL assertion failure (expected %s, current %s)\n",
		1043	state_string(state), state_string(cur_state));
2327	Serge	1044	}
		1045
		1046	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1047	enum pipe pipe)
		1048	{
		1049	int pp_reg, lvds_reg;
		1050	u32 val;
		1051	enum pipe panel_pipe = PIPE_A;
		1052	bool locked = true;
		1053
		1054	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1055	pp_reg = PCH_PP_CONTROL;
		1056	lvds_reg = PCH_LVDS;
		1057	} else {
		1058	pp_reg = PP_CONTROL;
		1059	lvds_reg = LVDS;
		1060	}
		1061
		1062	val = I915_READ(pp_reg);
		1063	if (!(val & PANEL_POWER_ON) \|\|
		1064	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1065	locked = false;
		1066
		1067	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1068	panel_pipe = PIPE_B;
		1069
		1070	WARN(panel_pipe == pipe && locked,
		1071	"panel assertion failure, pipe %c regs locked\n",
		1072	pipe_name(pipe));
		1073	}
		1074
2342	Serge	1075	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1076	enum pipe pipe, bool state)
		1077	{
		1078	int reg;
		1079	u32 val;
		1080	bool cur_state;
3243	Serge	1081	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1082	pipe);
2327	Serge	1083
3031	serge	1084	/* if we need the pipe A quirk it must be always on */
		1085	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1086	state = true;
		1087
4104	Serge	1088	if (!intel_display_power_enabled(dev_priv->dev,
		1089	POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
3480	Serge	1090	cur_state = false;
		1091	} else {
3243	Serge	1092	reg = PIPECONF(cpu_transcoder);
2327	Serge	1093	val = I915_READ(reg);
		1094	cur_state = !!(val & PIPECONF_ENABLE);
3480	Serge	1095	}
		1096
2327	Serge	1097	WARN(cur_state != state,
		1098	"pipe %c assertion failure (expected %s, current %s)\n",
		1099	pipe_name(pipe), state_string(state), state_string(cur_state));
		1100	}
		1101
3031	serge	1102	static void assert_plane(struct drm_i915_private *dev_priv,
		1103	enum plane plane, bool state)
2327	Serge	1104	{
		1105	int reg;
		1106	u32 val;
3031	serge	1107	bool cur_state;
2327	Serge	1108
		1109	reg = DSPCNTR(plane);
		1110	val = I915_READ(reg);
3031	serge	1111	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1112	WARN(cur_state != state,
		1113	"plane %c assertion failure (expected %s, current %s)\n",
		1114	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1115	}
		1116
3031	serge	1117	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1118	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1119
2327	Serge	1120	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1121	enum pipe pipe)
		1122	{
4104	Serge	1123	struct drm_device *dev = dev_priv->dev;
2327	Serge	1124	int reg, i;
		1125	u32 val;
		1126	int cur_pipe;
		1127
4104	Serge	1128	/* Primary planes are fixed to pipes on gen4+ */
		1129	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	1130	reg = DSPCNTR(pipe);
		1131	val = I915_READ(reg);
		1132	WARN((val & DISPLAY_PLANE_ENABLE),
		1133	"plane %c assertion failure, should be disabled but not\n",
		1134	plane_name(pipe));
2327	Serge	1135	return;
3031	serge	1136	}
2327	Serge	1137
		1138	/* Need to check both planes against the pipe */
4104	Serge	1139	for_each_pipe(i) {
2327	Serge	1140	reg = DSPCNTR(i);
		1141	val = I915_READ(reg);
		1142	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1143	DISPPLANE_SEL_PIPE_SHIFT;
		1144	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1145	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1146	plane_name(i), pipe_name(pipe));
		1147	}
		1148	}
		1149
3746	Serge	1150	static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
		1151	enum pipe pipe)
		1152	{
4104	Serge	1153	struct drm_device *dev = dev_priv->dev;
3746	Serge	1154	int reg, i;
		1155	u32 val;
		1156
4104	Serge	1157	if (IS_VALLEYVIEW(dev)) {
3746	Serge	1158	for (i = 0; i < dev_priv->num_plane; i++) {
		1159	reg = SPCNTR(pipe, i);
		1160	val = I915_READ(reg);
		1161	WARN((val & SP_ENABLE),
4104	Serge	1162	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1163	sprite_name(pipe, i), pipe_name(pipe));
		1164	}
		1165	} else if (INTEL_INFO(dev)->gen >= 7) {
		1166	reg = SPRCTL(pipe);
		1167	val = I915_READ(reg);
		1168	WARN((val & SPRITE_ENABLE),
		1169	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1170	plane_name(pipe), pipe_name(pipe));
		1171	} else if (INTEL_INFO(dev)->gen >= 5) {
		1172	reg = DVSCNTR(pipe);
		1173	val = I915_READ(reg);
		1174	WARN((val & DVS_ENABLE),
		1175	"sprite %c assertion failure, should be off on pipe %c but is still active\n",
		1176	plane_name(pipe), pipe_name(pipe));
3746	Serge	1177	}
		1178	}
		1179
2327	Serge	1180	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1181	{
		1182	u32 val;
		1183	bool enabled;
		1184
3031	serge	1185	if (HAS_PCH_LPT(dev_priv->dev)) {
		1186	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1187	return;
		1188	}
		1189
2327	Serge	1190	val = I915_READ(PCH_DREF_CONTROL);
		1191	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1192	DREF_SUPERSPREAD_SOURCE_MASK));
		1193	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1194	}
		1195
4104	Serge	1196	static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
2327	Serge	1197	enum pipe pipe)
		1198	{
		1199	int reg;
		1200	u32 val;
		1201	bool enabled;
		1202
4104	Serge	1203	reg = PCH_TRANSCONF(pipe);
2327	Serge	1204	val = I915_READ(reg);
		1205	enabled = !!(val & TRANS_ENABLE);
		1206	WARN(enabled,
		1207	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1208	pipe_name(pipe));
		1209	}
		1210
		1211	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1212	enum pipe pipe, u32 port_sel, u32 val)
		1213	{
		1214	if ((val & DP_PORT_EN) == 0)
		1215	return false;
		1216
		1217	if (HAS_PCH_CPT(dev_priv->dev)) {
		1218	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1219	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1220	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1221	return false;
		1222	} else {
		1223	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1224	return false;
		1225	}
		1226	return true;
		1227	}
		1228
		1229	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1230	enum pipe pipe, u32 val)
		1231	{
3746	Serge	1232	if ((val & SDVO_ENABLE) == 0)
2327	Serge	1233	return false;
		1234
		1235	if (HAS_PCH_CPT(dev_priv->dev)) {
3746	Serge	1236	if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
2327	Serge	1237	return false;
		1238	} else {
3746	Serge	1239	if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
2327	Serge	1240	return false;
		1241	}
		1242	return true;
		1243	}
		1244
		1245	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1246	enum pipe pipe, u32 val)
		1247	{
		1248	if ((val & LVDS_PORT_EN) == 0)
		1249	return false;
		1250
		1251	if (HAS_PCH_CPT(dev_priv->dev)) {
		1252	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1253	return false;
		1254	} else {
		1255	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1256	return false;
		1257	}
		1258	return true;
		1259	}
		1260
		1261	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1262	enum pipe pipe, u32 val)
		1263	{
		1264	if ((val & ADPA_DAC_ENABLE) == 0)
		1265	return false;
		1266	if (HAS_PCH_CPT(dev_priv->dev)) {
		1267	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1268	return false;
		1269	} else {
		1270	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1271	return false;
		1272	}
		1273	return true;
		1274	}
		1275
		1276	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1277	enum pipe pipe, int reg, u32 port_sel)
		1278	{
		1279	u32 val = I915_READ(reg);
		1280	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1281	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1282	reg, pipe_name(pipe));
3031	serge	1283
		1284	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1285	&& (val & DP_PIPEB_SELECT),
		1286	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1287	}
		1288
		1289	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1290	enum pipe pipe, int reg)
		1291	{
		1292	u32 val = I915_READ(reg);
3031	serge	1293	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1294	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1295	reg, pipe_name(pipe));
3031	serge	1296
3746	Serge	1297	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
3031	serge	1298	&& (val & SDVO_PIPE_B_SELECT),
		1299	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1300	}
		1301
		1302	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1303	enum pipe pipe)
		1304	{
		1305	int reg;
		1306	u32 val;
		1307
		1308	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1309	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1310	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1311
		1312	reg = PCH_ADPA;
		1313	val = I915_READ(reg);
3031	serge	1314	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1315	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1316	pipe_name(pipe));
		1317
		1318	reg = PCH_LVDS;
		1319	val = I915_READ(reg);
3031	serge	1320	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1321	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1322	pipe_name(pipe));
		1323
3746	Serge	1324	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
		1325	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
		1326	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
2327	Serge	1327	}
		1328
4104	Serge	1329	static void vlv_enable_pll(struct intel_crtc *crtc)
2327	Serge	1330	{
4104	Serge	1331	struct drm_device *dev = crtc->base.dev;
		1332	struct drm_i915_private *dev_priv = dev->dev_private;
		1333	int reg = DPLL(crtc->pipe);
		1334	u32 dpll = crtc->config.dpll_hw_state.dpll;
2327	Serge	1335
4104	Serge	1336	assert_pipe_disabled(dev_priv, crtc->pipe);
		1337
2327	Serge	1338	/* No really, not for ILK+ */
4104	Serge	1339	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
2327	Serge	1340
		1341	/* PLL is protected by panel, make sure we can write it */
		1342	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
4104	Serge	1343	assert_panel_unlocked(dev_priv, crtc->pipe);
2327	Serge	1344
4104	Serge	1345	I915_WRITE(reg, dpll);
		1346	POSTING_READ(reg);
		1347	udelay(150);
2327	Serge	1348
4104	Serge	1349	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		1350	DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
		1351
		1352	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
		1353	POSTING_READ(DPLL_MD(crtc->pipe));
		1354
		1355	/* We do this three times for luck */
		1356	I915_WRITE(reg, dpll);
		1357	POSTING_READ(reg);
		1358	udelay(150); /* wait for warmup */
		1359	I915_WRITE(reg, dpll);
		1360	POSTING_READ(reg);
		1361	udelay(150); /* wait for warmup */
		1362	I915_WRITE(reg, dpll);
		1363	POSTING_READ(reg);
		1364	udelay(150); /* wait for warmup */
		1365	}
		1366
		1367	static void i9xx_enable_pll(struct intel_crtc *crtc)
		1368	{
		1369	struct drm_device *dev = crtc->base.dev;
		1370	struct drm_i915_private *dev_priv = dev->dev_private;
		1371	int reg = DPLL(crtc->pipe);
		1372	u32 dpll = crtc->config.dpll_hw_state.dpll;
		1373
		1374	assert_pipe_disabled(dev_priv, crtc->pipe);
		1375
		1376	/* No really, not for ILK+ */
		1377	BUG_ON(dev_priv->info->gen >= 5);
		1378
		1379	/* PLL is protected by panel, make sure we can write it */
		1380	if (IS_MOBILE(dev) && !IS_I830(dev))
		1381	assert_panel_unlocked(dev_priv, crtc->pipe);
		1382
		1383	I915_WRITE(reg, dpll);
		1384
		1385	/* Wait for the clocks to stabilize. */
		1386	POSTING_READ(reg);
		1387	udelay(150);
		1388
		1389	if (INTEL_INFO(dev)->gen >= 4) {
		1390	I915_WRITE(DPLL_MD(crtc->pipe),
		1391	crtc->config.dpll_hw_state.dpll_md);
		1392	} else {
		1393	/* The pixel multiplier can only be updated once the
		1394	* DPLL is enabled and the clocks are stable.
		1395	*
		1396	* So write it again.
		1397	*/
		1398	I915_WRITE(reg, dpll);
		1399	}
		1400
2327	Serge	1401	/* We do this three times for luck */
4104	Serge	1402	I915_WRITE(reg, dpll);
2327	Serge	1403	POSTING_READ(reg);
		1404	udelay(150); /* wait for warmup */
4104	Serge	1405	I915_WRITE(reg, dpll);
2327	Serge	1406	POSTING_READ(reg);
		1407	udelay(150); /* wait for warmup */
4104	Serge	1408	I915_WRITE(reg, dpll);
2327	Serge	1409	POSTING_READ(reg);
		1410	udelay(150); /* wait for warmup */
		1411	}
		1412
		1413	/**
4104	Serge	1414	* i9xx_disable_pll - disable a PLL
2327	Serge	1415	* @dev_priv: i915 private structure
		1416	* @pipe: pipe PLL to disable
		1417	*
		1418	* Disable the PLL for @pipe, making sure the pipe is off first.
		1419	*
		1420	* Note! This is for pre-ILK only.
		1421	*/
4104	Serge	1422	static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2327	Serge	1423	{
		1424	/* Don't disable pipe A or pipe A PLLs if needed */
		1425	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1426	return;
		1427
		1428	/* Make sure the pipe isn't still relying on us */
		1429	assert_pipe_disabled(dev_priv, pipe);
		1430
4104	Serge	1431	I915_WRITE(DPLL(pipe), 0);
		1432	POSTING_READ(DPLL(pipe));
2327	Serge	1433	}
		1434
4104	Serge	1435	void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
3031	serge	1436	{
4104	Serge	1437	u32 port_mask;
3031	serge	1438
4104	Serge	1439	if (!port)
		1440	port_mask = DPLL_PORTB_READY_MASK;
3243	Serge	1441	else
4104	Serge	1442	port_mask = DPLL_PORTC_READY_MASK;
3243	Serge	1443
4104	Serge	1444	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		1445	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		1446	'B' + port, I915_READ(DPLL(0)));
3031	serge	1447	}
		1448
2327	Serge	1449	/**
4104	Serge	1450	* ironlake_enable_shared_dpll - enable PCH PLL
2327	Serge	1451	* @dev_priv: i915 private structure
		1452	* @pipe: pipe PLL to enable
		1453	*
		1454	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1455	* drives the transcoder clock.
		1456	*/
4104	Serge	1457	static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1458	{
4104	Serge	1459	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1460	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1461
3031	serge	1462	/* PCH PLLs only available on ILK, SNB and IVB */
		1463	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1464	if (WARN_ON(pll == NULL))
2342	Serge	1465	return;
		1466
3031	serge	1467	if (WARN_ON(pll->refcount == 0))
		1468	return;
2327	Serge	1469
4104	Serge	1470	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		1471	pll->name, pll->active, pll->on,
		1472	crtc->base.base.id);
3031	serge	1473
4104	Serge	1474	if (pll->active++) {
		1475	WARN_ON(!pll->on);
		1476	assert_shared_dpll_enabled(dev_priv, pll);
3031	serge	1477	return;
		1478	}
4104	Serge	1479	WARN_ON(pll->on);
3031	serge	1480
4104	Serge	1481	DRM_DEBUG_KMS("enabling %s\n", pll->name);
		1482	pll->enable(dev_priv, pll);
3031	serge	1483	pll->on = true;
2327	Serge	1484	}
		1485
4104	Serge	1486	static void intel_disable_shared_dpll(struct intel_crtc *crtc)
2327	Serge	1487	{
4104	Serge	1488	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		1489	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
2327	Serge	1490
		1491	/* PCH only available on ILK+ */
		1492	BUG_ON(dev_priv->info->gen < 5);
4104	Serge	1493	if (WARN_ON(pll == NULL))
3031	serge	1494	return;
2327	Serge	1495
3031	serge	1496	if (WARN_ON(pll->refcount == 0))
		1497	return;
2327	Serge	1498
4104	Serge	1499	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		1500	pll->name, pll->active, pll->on,
		1501	crtc->base.base.id);
2342	Serge	1502
3031	serge	1503	if (WARN_ON(pll->active == 0)) {
4104	Serge	1504	assert_shared_dpll_disabled(dev_priv, pll);
3031	serge	1505	return;
		1506	}
2342	Serge	1507
4104	Serge	1508	assert_shared_dpll_enabled(dev_priv, pll);
		1509	WARN_ON(!pll->on);
		1510	if (--pll->active)
2342	Serge	1511	return;
		1512
4104	Serge	1513	DRM_DEBUG_KMS("disabling %s\n", pll->name);
		1514	pll->disable(dev_priv, pll);
3031	serge	1515	pll->on = false;
2327	Serge	1516	}
		1517
3243	Serge	1518	static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1519	enum pipe pipe)
		1520	{
3243	Serge	1521	struct drm_device *dev = dev_priv->dev;
3031	serge	1522	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4104	Serge	1523	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	1524	uint32_t reg, val, pipeconf_val;
2327	Serge	1525
		1526	/* PCH only available on ILK+ */
		1527	BUG_ON(dev_priv->info->gen < 5);
		1528
		1529	/* Make sure PCH DPLL is enabled */
4104	Serge	1530	assert_shared_dpll_enabled(dev_priv,
		1531	intel_crtc_to_shared_dpll(intel_crtc));
2327	Serge	1532
		1533	/* FDI must be feeding us bits for PCH ports */
		1534	assert_fdi_tx_enabled(dev_priv, pipe);
		1535	assert_fdi_rx_enabled(dev_priv, pipe);
		1536
3243	Serge	1537	if (HAS_PCH_CPT(dev)) {
		1538	/* Workaround: Set the timing override bit before enabling the
		1539	* pch transcoder. */
		1540	reg = TRANS_CHICKEN2(pipe);
		1541	val = I915_READ(reg);
		1542	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1543	I915_WRITE(reg, val);
3031	serge	1544	}
3243	Serge	1545
4104	Serge	1546	reg = PCH_TRANSCONF(pipe);
2327	Serge	1547	val = I915_READ(reg);
3031	serge	1548	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1549
		1550	if (HAS_PCH_IBX(dev_priv->dev)) {
		1551	/*
		1552	* make the BPC in transcoder be consistent with
		1553	* that in pipeconf reg.
		1554	*/
3480	Serge	1555	val &= ~PIPECONF_BPC_MASK;
		1556	val \|= pipeconf_val & PIPECONF_BPC_MASK;
2327	Serge	1557	}
3031	serge	1558
		1559	val &= ~TRANS_INTERLACE_MASK;
		1560	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1561	if (HAS_PCH_IBX(dev_priv->dev) &&
		1562	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1563	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1564	else
		1565	val \|= TRANS_INTERLACED;
		1566	else
		1567	val \|= TRANS_PROGRESSIVE;
		1568
2327	Serge	1569	I915_WRITE(reg, val \| TRANS_ENABLE);
		1570	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4104	Serge	1571	DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2327	Serge	1572	}
		1573
3243	Serge	1574	static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
		1575	enum transcoder cpu_transcoder)
		1576	{
		1577	u32 val, pipeconf_val;
		1578
		1579	/* PCH only available on ILK+ */
		1580	BUG_ON(dev_priv->info->gen < 5);
		1581
		1582	/* FDI must be feeding us bits for PCH ports */
3480	Serge	1583	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
3243	Serge	1584	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
		1585
		1586	/* Workaround: set timing override bit. */
		1587	val = I915_READ(_TRANSA_CHICKEN2);
		1588	val \|= TRANS_CHICKEN2_TIMING_OVERRIDE;
		1589	I915_WRITE(_TRANSA_CHICKEN2, val);
		1590
		1591	val = TRANS_ENABLE;
		1592	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
		1593
		1594	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
		1595	PIPECONF_INTERLACED_ILK)
		1596	val \|= TRANS_INTERLACED;
		1597	else
		1598	val \|= TRANS_PROGRESSIVE;
		1599
4104	Serge	1600	I915_WRITE(LPT_TRANSCONF, val);
		1601	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
3243	Serge	1602	DRM_ERROR("Failed to enable PCH transcoder\n");
		1603	}
		1604
		1605	static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2327	Serge	1606	enum pipe pipe)
		1607	{
3243	Serge	1608	struct drm_device *dev = dev_priv->dev;
		1609	uint32_t reg, val;
2327	Serge	1610
		1611	/* FDI relies on the transcoder */
		1612	assert_fdi_tx_disabled(dev_priv, pipe);
		1613	assert_fdi_rx_disabled(dev_priv, pipe);
		1614
		1615	/* Ports must be off as well */
		1616	assert_pch_ports_disabled(dev_priv, pipe);
		1617
4104	Serge	1618	reg = PCH_TRANSCONF(pipe);
2327	Serge	1619	val = I915_READ(reg);
		1620	val &= ~TRANS_ENABLE;
		1621	I915_WRITE(reg, val);
		1622	/* wait for PCH transcoder off, transcoder state */
		1623	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4104	Serge	1624	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
3243	Serge	1625
		1626	if (!HAS_PCH_IBX(dev)) {
		1627	/* Workaround: Clear the timing override chicken bit again. */
		1628	reg = TRANS_CHICKEN2(pipe);
		1629	val = I915_READ(reg);
		1630	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1631	I915_WRITE(reg, val);
		1632	}
2327	Serge	1633	}
		1634
3243	Serge	1635	static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
		1636	{
		1637	u32 val;
		1638
4104	Serge	1639	val = I915_READ(LPT_TRANSCONF);
3243	Serge	1640	val &= ~TRANS_ENABLE;
4104	Serge	1641	I915_WRITE(LPT_TRANSCONF, val);
3243	Serge	1642	/* wait for PCH transcoder off, transcoder state */
4104	Serge	1643	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
3243	Serge	1644	DRM_ERROR("Failed to disable PCH transcoder\n");
		1645
		1646	/* Workaround: clear timing override bit. */
		1647	val = I915_READ(_TRANSA_CHICKEN2);
		1648	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		1649	I915_WRITE(_TRANSA_CHICKEN2, val);
		1650	}
		1651
2327	Serge	1652	/**
		1653	* intel_enable_pipe - enable a pipe, asserting requirements
		1654	* @dev_priv: i915 private structure
		1655	* @pipe: pipe to enable
		1656	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1657	*
		1658	* Enable @pipe, making sure that various hardware specific requirements
		1659	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1660	*
		1661	* @pipe should be %PIPE_A or %PIPE_B.
		1662	*
		1663	* Will wait until the pipe is actually running (i.e. first vblank) before
		1664	* returning.
		1665	*/
		1666	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1667	bool pch_port)
		1668	{
3243	Serge	1669	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1670	pipe);
3480	Serge	1671	enum pipe pch_transcoder;
2327	Serge	1672	int reg;
		1673	u32 val;
		1674
4104	Serge	1675	assert_planes_disabled(dev_priv, pipe);
		1676	assert_sprites_disabled(dev_priv, pipe);
		1677
3480	Serge	1678	if (HAS_PCH_LPT(dev_priv->dev))
3243	Serge	1679	pch_transcoder = TRANSCODER_A;
		1680	else
		1681	pch_transcoder = pipe;
		1682
2327	Serge	1683	/*
		1684	* A pipe without a PLL won't actually be able to drive bits from
		1685	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1686	* need the check.
		1687	*/
		1688	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1689	assert_pll_enabled(dev_priv, pipe);
		1690	else {
		1691	if (pch_port) {
		1692	/* if driving the PCH, we need FDI enabled */
3243	Serge	1693	assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
3480	Serge	1694	assert_fdi_tx_pll_enabled(dev_priv,
		1695	(enum pipe) cpu_transcoder);
2327	Serge	1696	}
		1697	/* FIXME: assert CPU port conditions for SNB+ */
		1698	}
		1699
3243	Serge	1700	reg = PIPECONF(cpu_transcoder);
2327	Serge	1701	val = I915_READ(reg);
		1702	if (val & PIPECONF_ENABLE)
		1703	return;
		1704
		1705	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1706	intel_wait_for_vblank(dev_priv->dev, pipe);
		1707	}
		1708
		1709	/**
		1710	* intel_disable_pipe - disable a pipe, asserting requirements
		1711	* @dev_priv: i915 private structure
		1712	* @pipe: pipe to disable
		1713	*
		1714	* Disable @pipe, making sure that various hardware specific requirements
		1715	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1716	*
		1717	* @pipe should be %PIPE_A or %PIPE_B.
		1718	*
		1719	* Will wait until the pipe has shut down before returning.
		1720	*/
		1721	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1722	enum pipe pipe)
		1723	{
3243	Serge	1724	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
		1725	pipe);
2327	Serge	1726	int reg;
		1727	u32 val;
		1728
3031	serge	1729	/*
2327	Serge	1730	* Make sure planes won't keep trying to pump pixels to us,
		1731	* or we might hang the display.
		1732	*/
		1733	assert_planes_disabled(dev_priv, pipe);
3746	Serge	1734	assert_sprites_disabled(dev_priv, pipe);
2327	Serge	1735
		1736	/* Don't disable pipe A or pipe A PLLs if needed */
		1737	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1738	return;
		1739
3243	Serge	1740	reg = PIPECONF(cpu_transcoder);
2327	Serge	1741	val = I915_READ(reg);
		1742	if ((val & PIPECONF_ENABLE) == 0)
		1743	return;
		1744
		1745	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1746	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1747	}
		1748
		1749	/*
		1750	* Plane regs are double buffered, going from enabled->disabled needs a
		1751	* trigger in order to latch. The display address reg provides this.
		1752	*/
3031	serge	1753	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1754	enum plane plane)
		1755	{
3243	Serge	1756	if (dev_priv->info->gen >= 4)
		1757	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1758	else
2327	Serge	1759	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1760	}
		1761
		1762	/**
		1763	* intel_enable_plane - enable a display plane on a given pipe
		1764	* @dev_priv: i915 private structure
		1765	* @plane: plane to enable
		1766	* @pipe: pipe being fed
		1767	*
		1768	* Enable @plane on @pipe, making sure that @pipe is running first.
		1769	*/
		1770	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1771	enum plane plane, enum pipe pipe)
		1772	{
		1773	int reg;
		1774	u32 val;
		1775
		1776	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1777	assert_pipe_enabled(dev_priv, pipe);
		1778
		1779	reg = DSPCNTR(plane);
		1780	val = I915_READ(reg);
		1781	if (val & DISPLAY_PLANE_ENABLE)
		1782	return;
		1783
		1784	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1785	intel_flush_display_plane(dev_priv, plane);
		1786	intel_wait_for_vblank(dev_priv->dev, pipe);
		1787	}
		1788
		1789	/**
		1790	* intel_disable_plane - disable a display plane
		1791	* @dev_priv: i915 private structure
		1792	* @plane: plane to disable
		1793	* @pipe: pipe consuming the data
		1794	*
		1795	* Disable @plane; should be an independent operation.
		1796	*/
		1797	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1798	enum plane plane, enum pipe pipe)
		1799	{
		1800	int reg;
		1801	u32 val;
		1802
		1803	reg = DSPCNTR(plane);
		1804	val = I915_READ(reg);
		1805	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1806	return;
		1807
		1808	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1809	intel_flush_display_plane(dev_priv, plane);
3031	serge	1810	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1811	}
		1812
3746	Serge	1813	static bool need_vtd_wa(struct drm_device *dev)
		1814	{
		1815	#ifdef CONFIG_INTEL_IOMMU
		1816	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		1817	return true;
		1818	#endif
		1819	return false;
		1820	}
		1821
2335	Serge	1822	int
		1823	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1824	struct drm_i915_gem_object *obj,
		1825	struct intel_ring_buffer *pipelined)
		1826	{
		1827	struct drm_i915_private *dev_priv = dev->dev_private;
		1828	u32 alignment;
		1829	int ret;
2327	Serge	1830
4280	Serge	1831	ENTER();
		1832
2335	Serge	1833	switch (obj->tiling_mode) {
		1834	case I915_TILING_NONE:
		1835	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1836	alignment = 128 * 1024;
		1837	else if (INTEL_INFO(dev)->gen >= 4)
		1838	alignment = 4 * 1024;
		1839	else
		1840	alignment = 64 * 1024;
		1841	break;
		1842	case I915_TILING_X:
		1843	/* pin() will align the object as required by fence */
		1844	alignment = 0;
		1845	break;
		1846	case I915_TILING_Y:
3746	Serge	1847	/* Despite that we check this in framebuffer_init userspace can
		1848	* screw us over and change the tiling after the fact. Only
		1849	* pinned buffers can't change their tiling. */
		1850	DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2335	Serge	1851	return -EINVAL;
		1852	default:
		1853	BUG();
		1854	}
2327	Serge	1855
3746	Serge	1856	/* Note that the w/a also requires 64 PTE of padding following the
		1857	* bo. We currently fill all unused PTE with the shadow page and so
		1858	* we should always have valid PTE following the scanout preventing
		1859	* the VT-d warning.
		1860	*/
		1861	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		1862	alignment = 256 * 1024;
		1863
2335	Serge	1864	dev_priv->mm.interruptible = false;
		1865	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1866	if (ret)
		1867	goto err_interruptible;
2327	Serge	1868
2335	Serge	1869	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1870	* fence, whereas 965+ only requires a fence if using
		1871	* framebuffer compression. For simplicity, we always install
		1872	* a fence as the cost is not that onerous.
		1873	*/
3480	Serge	1874	ret = i915_gem_object_get_fence(obj);
		1875	if (ret)
		1876	goto err_unpin;
2327	Serge	1877
3480	Serge	1878	i915_gem_object_pin_fence(obj);
		1879
2335	Serge	1880	dev_priv->mm.interruptible = true;
4280	Serge	1881
		1882	LEAVE();
		1883
2335	Serge	1884	return 0;
2327	Serge	1885
2335	Serge	1886	err_unpin:
4104	Serge	1887	i915_gem_object_unpin_from_display_plane(obj);
2335	Serge	1888	err_interruptible:
		1889	dev_priv->mm.interruptible = true;
		1890	return ret;
		1891	}
2327	Serge	1892
3031	serge	1893	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1894	{
		1895	// i915_gem_object_unpin_fence(obj);
		1896	// i915_gem_object_unpin(obj);
		1897	}
		1898
		1899	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1900	* is assumed to be a power-of-two. */
3480	Serge	1901	unsigned long intel_gen4_compute_page_offset(int x, int y,
		1902	unsigned int tiling_mode,
		1903	unsigned int cpp,
3031	serge	1904	unsigned int pitch)
		1905	{
3480	Serge	1906	if (tiling_mode != I915_TILING_NONE) {
		1907	unsigned int tile_rows, tiles;
3031	serge	1908
		1909	tile_rows = *y / 8;
		1910	*y %= 8;
		1911
3480	Serge	1912	tiles = *x / (512/cpp);
		1913	*x %= 512/cpp;
		1914
3031	serge	1915	return tile_rows * pitch * 8 + tiles * 4096;
3480	Serge	1916	} else {
		1917	unsigned int offset;
		1918
		1919	offset = y pitch + x cpp;
		1920	*y = 0;
		1921	*x = (offset & 4095) / cpp;
		1922	return offset & -4096;
		1923	}
3031	serge	1924	}
		1925
2327	Serge	1926	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1927	int x, int y)
		1928	{
		1929	struct drm_device *dev = crtc->dev;
		1930	struct drm_i915_private *dev_priv = dev->dev_private;
		1931	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1932	struct intel_framebuffer *intel_fb;
		1933	struct drm_i915_gem_object *obj;
		1934	int plane = intel_crtc->plane;
3031	serge	1935	unsigned long linear_offset;
2327	Serge	1936	u32 dspcntr;
		1937	u32 reg;
		1938
		1939	switch (plane) {
		1940	case 0:
		1941	case 1:
		1942	break;
		1943	default:
4104	Serge	1944	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	1945	return -EINVAL;
		1946	}
		1947
		1948	intel_fb = to_intel_framebuffer(fb);
		1949	obj = intel_fb->obj;
		1950
		1951	reg = DSPCNTR(plane);
		1952	dspcntr = I915_READ(reg);
		1953	/* Mask out pixel format bits in case we change it */
		1954	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	1955	switch (fb->pixel_format) {
		1956	case DRM_FORMAT_C8:
2327	Serge	1957	dspcntr \|= DISPPLANE_8BPP;
		1958	break;
3243	Serge	1959	case DRM_FORMAT_XRGB1555:
		1960	case DRM_FORMAT_ARGB1555:
		1961	dspcntr \|= DISPPLANE_BGRX555;
		1962	break;
		1963	case DRM_FORMAT_RGB565:
		1964	dspcntr \|= DISPPLANE_BGRX565;
		1965	break;
		1966	case DRM_FORMAT_XRGB8888:
		1967	case DRM_FORMAT_ARGB8888:
		1968	dspcntr \|= DISPPLANE_BGRX888;
		1969	break;
		1970	case DRM_FORMAT_XBGR8888:
		1971	case DRM_FORMAT_ABGR8888:
		1972	dspcntr \|= DISPPLANE_RGBX888;
		1973	break;
		1974	case DRM_FORMAT_XRGB2101010:
		1975	case DRM_FORMAT_ARGB2101010:
		1976	dspcntr \|= DISPPLANE_BGRX101010;
2327	Serge	1977	break;
3243	Serge	1978	case DRM_FORMAT_XBGR2101010:
		1979	case DRM_FORMAT_ABGR2101010:
		1980	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	1981	break;
		1982	default:
3746	Serge	1983	BUG();
2327	Serge	1984	}
3243	Serge	1985
2327	Serge	1986	if (INTEL_INFO(dev)->gen >= 4) {
		1987	if (obj->tiling_mode != I915_TILING_NONE)
		1988	dspcntr \|= DISPPLANE_TILED;
		1989	else
		1990	dspcntr &= ~DISPPLANE_TILED;
		1991	}
		1992
4104	Serge	1993	if (IS_G4X(dev))
		1994	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		1995
2327	Serge	1996	I915_WRITE(reg, dspcntr);
		1997
3031	serge	1998	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	1999
3031	serge	2000	if (INTEL_INFO(dev)->gen >= 4) {
		2001	intel_crtc->dspaddr_offset =
3480	Serge	2002	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2003	fb->bits_per_pixel / 8,
		2004	fb->pitches[0]);
		2005	linear_offset -= intel_crtc->dspaddr_offset;
		2006	} else {
		2007	intel_crtc->dspaddr_offset = linear_offset;
		2008	}
		2009
4104	Serge	2010	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2011	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2012	fb->pitches[0]);
2342	Serge	2013	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2014	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2015	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2016	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	2017	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2018	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2019	} else
4104	Serge	2020	I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2327	Serge	2021	POSTING_READ(reg);
		2022
		2023	return 0;
		2024	}
		2025
		2026	static int ironlake_update_plane(struct drm_crtc *crtc,
		2027	struct drm_framebuffer *fb, int x, int y)
		2028	{
		2029	struct drm_device *dev = crtc->dev;
		2030	struct drm_i915_private *dev_priv = dev->dev_private;
		2031	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2032	struct intel_framebuffer *intel_fb;
		2033	struct drm_i915_gem_object *obj;
		2034	int plane = intel_crtc->plane;
3031	serge	2035	unsigned long linear_offset;
2327	Serge	2036	u32 dspcntr;
		2037	u32 reg;
		2038
		2039	switch (plane) {
		2040	case 0:
		2041	case 1:
2342	Serge	2042	case 2:
2327	Serge	2043	break;
		2044	default:
4104	Serge	2045	DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2327	Serge	2046	return -EINVAL;
		2047	}
		2048
		2049	intel_fb = to_intel_framebuffer(fb);
		2050	obj = intel_fb->obj;
		2051
		2052	reg = DSPCNTR(plane);
		2053	dspcntr = I915_READ(reg);
		2054	/* Mask out pixel format bits in case we change it */
		2055	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
3243	Serge	2056	switch (fb->pixel_format) {
		2057	case DRM_FORMAT_C8:
2327	Serge	2058	dspcntr \|= DISPPLANE_8BPP;
		2059	break;
3243	Serge	2060	case DRM_FORMAT_RGB565:
		2061	dspcntr \|= DISPPLANE_BGRX565;
2327	Serge	2062	break;
3243	Serge	2063	case DRM_FORMAT_XRGB8888:
		2064	case DRM_FORMAT_ARGB8888:
		2065	dspcntr \|= DISPPLANE_BGRX888;
		2066	break;
		2067	case DRM_FORMAT_XBGR8888:
		2068	case DRM_FORMAT_ABGR8888:
		2069	dspcntr \|= DISPPLANE_RGBX888;
		2070	break;
		2071	case DRM_FORMAT_XRGB2101010:
		2072	case DRM_FORMAT_ARGB2101010:
		2073	dspcntr \|= DISPPLANE_BGRX101010;
		2074	break;
		2075	case DRM_FORMAT_XBGR2101010:
		2076	case DRM_FORMAT_ABGR2101010:
		2077	dspcntr \|= DISPPLANE_RGBX101010;
2327	Serge	2078	break;
		2079	default:
3746	Serge	2080	BUG();
2327	Serge	2081	}
		2082
3480	Serge	2083	if (obj->tiling_mode != I915_TILING_NONE)
		2084	dspcntr \|= DISPPLANE_TILED;
		2085	else
2327	Serge	2086	dspcntr &= ~DISPPLANE_TILED;
		2087
4104	Serge	2088	if (IS_HASWELL(dev))
		2089	dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
		2090	else
2327	Serge	2091	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2092
		2093	I915_WRITE(reg, dspcntr);
		2094
3031	serge	2095	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2096	intel_crtc->dspaddr_offset =
3480	Serge	2097	intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
3031	serge	2098	fb->bits_per_pixel / 8,
		2099	fb->pitches[0]);
		2100	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2101
4104	Serge	2102	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2103	i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		2104	fb->pitches[0]);
2342	Serge	2105	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2106	I915_MODIFY_DISPBASE(DSPSURF(plane),
4104	Serge	2107	i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3243	Serge	2108	if (IS_HASWELL(dev)) {
		2109	I915_WRITE(DSPOFFSET(plane), (y << 16) \| x);
		2110	} else {
2330	Serge	2111	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2112	I915_WRITE(DSPLINOFF(plane), linear_offset);
3243	Serge	2113	}
2330	Serge	2114	POSTING_READ(reg);
2327	Serge	2115
		2116	return 0;
		2117	}
		2118
		2119	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2120	static int
		2121	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2122	int x, int y, enum mode_set_atomic state)
		2123	{
		2124	struct drm_device *dev = crtc->dev;
		2125	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2126
		2127	if (dev_priv->display.disable_fbc)
		2128	dev_priv->display.disable_fbc(dev);
		2129	intel_increase_pllclock(crtc);
		2130
		2131	return dev_priv->display.update_plane(crtc, fb, x, y);
		2132	}
		2133
		2134	#if 0
4104	Serge	2135	void intel_display_handle_reset(struct drm_device *dev)
		2136	{
		2137	struct drm_i915_private *dev_priv = dev->dev_private;
		2138	struct drm_crtc *crtc;
		2139
		2140	/*
		2141	* Flips in the rings have been nuked by the reset,
		2142	* so complete all pending flips so that user space
		2143	* will get its events and not get stuck.
		2144	*
		2145	* Also update the base address of all primary
		2146	* planes to the the last fb to make sure we're
		2147	* showing the correct fb after a reset.
		2148	*
		2149	* Need to make two loops over the crtcs so that we
		2150	* don't try to grab a crtc mutex before the
		2151	* pending_flip_queue really got woken up.
		2152	*/
		2153
		2154	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2155	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2156	enum plane plane = intel_crtc->plane;
		2157
		2158	intel_prepare_page_flip(dev, plane);
		2159	intel_finish_page_flip_plane(dev, plane);
		2160	}
		2161
		2162	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		2163	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2164
		2165	mutex_lock(&crtc->mutex);
		2166	if (intel_crtc->active)
		2167	dev_priv->display.update_plane(crtc, crtc->fb,
		2168	crtc->x, crtc->y);
		2169	mutex_unlock(&crtc->mutex);
		2170	}
		2171	}
		2172
3031	serge	2173	static int
		2174	intel_finish_fb(struct drm_framebuffer *old_fb)
		2175	{
		2176	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2177	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2178	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2179	int ret;
		2180
3031	serge	2181	/* Big Hammer, we also need to ensure that any pending
		2182	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2183	* current scanout is retired before unpinning the old
		2184	* framebuffer.
		2185	*
		2186	* This should only fail upon a hung GPU, in which case we
		2187	* can safely continue.
		2188	*/
		2189	dev_priv->mm.interruptible = false;
		2190	ret = i915_gem_object_finish_gpu(obj);
		2191	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2192
3031	serge	2193	return ret;
2327	Serge	2194	}
4104	Serge	2195
		2196	static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
		2197	{
		2198	struct drm_device *dev = crtc->dev;
		2199	struct drm_i915_master_private *master_priv;
		2200	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2201
		2202	if (!dev->primary->master)
		2203	return;
		2204
		2205	master_priv = dev->primary->master->driver_priv;
		2206	if (!master_priv->sarea_priv)
		2207	return;
		2208
		2209	switch (intel_crtc->pipe) {
		2210	case 0:
		2211	master_priv->sarea_priv->pipeA_x = x;
		2212	master_priv->sarea_priv->pipeA_y = y;
		2213	break;
		2214	case 1:
		2215	master_priv->sarea_priv->pipeB_x = x;
		2216	master_priv->sarea_priv->pipeB_y = y;
		2217	break;
		2218	default:
		2219	break;
		2220	}
		2221	}
3031	serge	2222	#endif
2327	Serge	2223
		2224	static int
		2225	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2226	struct drm_framebuffer *fb)
2327	Serge	2227	{
		2228	struct drm_device *dev = crtc->dev;
3031	serge	2229	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2230	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2231	struct drm_framebuffer *old_fb;
2342	Serge	2232	int ret;
2327	Serge	2233
		2234	/* no fb bound */
3031	serge	2235	if (!fb) {
2327	Serge	2236	DRM_ERROR("No FB bound\n");
		2237	return 0;
		2238	}
		2239
3746	Serge	2240	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
4104	Serge	2241	DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
		2242	plane_name(intel_crtc->plane),
3746	Serge	2243	INTEL_INFO(dev)->num_pipes);
2327	Serge	2244	return -EINVAL;
		2245	}
		2246
		2247	mutex_lock(&dev->struct_mutex);
4280	Serge	2248	ret = intel_pin_and_fence_fb_obj(dev,
		2249	to_intel_framebuffer(fb)->obj,
		2250	NULL);
		2251	if (ret != 0) {
		2252	mutex_unlock(&dev->struct_mutex);
		2253	DRM_ERROR("pin & fence failed\n");
		2254	return ret;
		2255	}
2327	Serge	2256
4280	Serge	2257	/* Update pipe size and adjust fitter if needed */
		2258	if (i915_fastboot) {
		2259	I915_WRITE(PIPESRC(intel_crtc->pipe),
		2260	((crtc->mode.hdisplay - 1) << 16) \|
		2261	(crtc->mode.vdisplay - 1));
		2262	if (!intel_crtc->config.pch_pfit.enabled &&
		2263	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\|
		2264	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
		2265	I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
		2266	I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
		2267	I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
		2268	}
		2269	}
3031	serge	2270
		2271	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2272	if (ret) {
3031	serge	2273	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2274	mutex_unlock(&dev->struct_mutex);
		2275	DRM_ERROR("failed to update base address\n");
3243	Serge	2276	return ret;
2327	Serge	2277	}
		2278
3031	serge	2279	old_fb = crtc->fb;
		2280	crtc->fb = fb;
		2281	crtc->x = x;
		2282	crtc->y = y;
		2283
		2284	if (old_fb) {
4104	Serge	2285	if (intel_crtc->active && old_fb != fb)
3031	serge	2286	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2287	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2288	}
		2289
		2290	intel_update_fbc(dev);
4104	Serge	2291	intel_edp_psr_update(dev);
2336	Serge	2292	mutex_unlock(&dev->struct_mutex);
2327	Serge	2293
2336	Serge	2294	return 0;
2327	Serge	2295	}
		2296
		2297	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2298	{
		2299	struct drm_device *dev = crtc->dev;
		2300	struct drm_i915_private *dev_priv = dev->dev_private;
		2301	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2302	int pipe = intel_crtc->pipe;
		2303	u32 reg, temp;
		2304
		2305	/* enable normal train */
		2306	reg = FDI_TX_CTL(pipe);
		2307	temp = I915_READ(reg);
		2308	if (IS_IVYBRIDGE(dev)) {
		2309	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2310	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2311	} else {
		2312	temp &= ~FDI_LINK_TRAIN_NONE;
		2313	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2314	}
		2315	I915_WRITE(reg, temp);
		2316
		2317	reg = FDI_RX_CTL(pipe);
		2318	temp = I915_READ(reg);
		2319	if (HAS_PCH_CPT(dev)) {
		2320	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2321	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2322	} else {
		2323	temp &= ~FDI_LINK_TRAIN_NONE;
		2324	temp \|= FDI_LINK_TRAIN_NONE;
		2325	}
		2326	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2327
		2328	/* wait one idle pattern time */
		2329	POSTING_READ(reg);
		2330	udelay(1000);
		2331
		2332	/* IVB wants error correction enabled */
		2333	if (IS_IVYBRIDGE(dev))
		2334	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2335	FDI_FE_ERRC_ENABLE);
		2336	}
		2337
4280	Serge	2338	static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
4104	Serge	2339	{
4280	Serge	2340	return crtc->base.enabled && crtc->active &&
		2341	crtc->config.has_pch_encoder;
4104	Serge	2342	}
		2343
3243	Serge	2344	static void ivb_modeset_global_resources(struct drm_device *dev)
2327	Serge	2345	{
		2346	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2347	struct intel_crtc *pipe_B_crtc =
		2348	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		2349	struct intel_crtc *pipe_C_crtc =
		2350	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
		2351	uint32_t temp;
2327	Serge	2352
4104	Serge	2353	/*
		2354	* When everything is off disable fdi C so that we could enable fdi B
		2355	* with all lanes. Note that we don't care about enabled pipes without
		2356	* an enabled pch encoder.
		2357	*/
		2358	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
		2359	!pipe_has_enabled_pch(pipe_C_crtc)) {
3243	Serge	2360	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		2361	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		2362
		2363	temp = I915_READ(SOUTH_CHICKEN1);
		2364	temp &= ~FDI_BC_BIFURCATION_SELECT;
		2365	DRM_DEBUG_KMS("disabling fdi C rx\n");
		2366	I915_WRITE(SOUTH_CHICKEN1, temp);
		2367	}
2327	Serge	2368	}
		2369
		2370	/* The FDI link training functions for ILK/Ibexpeak. */
		2371	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2372	{
		2373	struct drm_device *dev = crtc->dev;
		2374	struct drm_i915_private *dev_priv = dev->dev_private;
		2375	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2376	int pipe = intel_crtc->pipe;
		2377	int plane = intel_crtc->plane;
		2378	u32 reg, temp, tries;
		2379
		2380	/* FDI needs bits from pipe & plane first */
		2381	assert_pipe_enabled(dev_priv, pipe);
		2382	assert_plane_enabled(dev_priv, plane);
		2383
		2384	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2385	for train result */
		2386	reg = FDI_RX_IMR(pipe);
		2387	temp = I915_READ(reg);
		2388	temp &= ~FDI_RX_SYMBOL_LOCK;
		2389	temp &= ~FDI_RX_BIT_LOCK;
		2390	I915_WRITE(reg, temp);
		2391	I915_READ(reg);
		2392	udelay(150);
		2393
		2394	/* enable CPU FDI TX and PCH FDI RX */
		2395	reg = FDI_TX_CTL(pipe);
		2396	temp = I915_READ(reg);
4104	Serge	2397	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2398	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2399	temp &= ~FDI_LINK_TRAIN_NONE;
		2400	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2401	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2402
		2403	reg = FDI_RX_CTL(pipe);
		2404	temp = I915_READ(reg);
		2405	temp &= ~FDI_LINK_TRAIN_NONE;
		2406	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2407	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2408
		2409	POSTING_READ(reg);
		2410	udelay(150);
		2411
		2412	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2413	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2414	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2415	FDI_RX_PHASE_SYNC_POINTER_EN);
		2416
		2417	reg = FDI_RX_IIR(pipe);
		2418	for (tries = 0; tries < 5; tries++) {
		2419	temp = I915_READ(reg);
		2420	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2421
		2422	if ((temp & FDI_RX_BIT_LOCK)) {
		2423	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2424	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2425	break;
		2426	}
		2427	}
		2428	if (tries == 5)
		2429	DRM_ERROR("FDI train 1 fail!\n");
		2430
		2431	/* Train 2 */
		2432	reg = FDI_TX_CTL(pipe);
		2433	temp = I915_READ(reg);
		2434	temp &= ~FDI_LINK_TRAIN_NONE;
		2435	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2436	I915_WRITE(reg, temp);
		2437
		2438	reg = FDI_RX_CTL(pipe);
		2439	temp = I915_READ(reg);
		2440	temp &= ~FDI_LINK_TRAIN_NONE;
		2441	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2442	I915_WRITE(reg, temp);
		2443
		2444	POSTING_READ(reg);
		2445	udelay(150);
		2446
		2447	reg = FDI_RX_IIR(pipe);
		2448	for (tries = 0; tries < 5; tries++) {
		2449	temp = I915_READ(reg);
		2450	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2451
		2452	if (temp & FDI_RX_SYMBOL_LOCK) {
		2453	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2454	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2455	break;
		2456	}
		2457	}
		2458	if (tries == 5)
		2459	DRM_ERROR("FDI train 2 fail!\n");
		2460
		2461	DRM_DEBUG_KMS("FDI train done\n");
		2462
		2463	}
		2464
2342	Serge	2465	static const int snb_b_fdi_train_param[] = {
2327	Serge	2466	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2467	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2468	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2469	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2470	};
		2471
		2472	/* The FDI link training functions for SNB/Cougarpoint. */
		2473	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2474	{
		2475	struct drm_device *dev = crtc->dev;
		2476	struct drm_i915_private *dev_priv = dev->dev_private;
		2477	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2478	int pipe = intel_crtc->pipe;
3031	serge	2479	u32 reg, temp, i, retry;
2327	Serge	2480
		2481	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2482	for train result */
		2483	reg = FDI_RX_IMR(pipe);
		2484	temp = I915_READ(reg);
		2485	temp &= ~FDI_RX_SYMBOL_LOCK;
		2486	temp &= ~FDI_RX_BIT_LOCK;
		2487	I915_WRITE(reg, temp);
		2488
		2489	POSTING_READ(reg);
		2490	udelay(150);
		2491
		2492	/* enable CPU FDI TX and PCH FDI RX */
		2493	reg = FDI_TX_CTL(pipe);
		2494	temp = I915_READ(reg);
4104	Serge	2495	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2496	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2497	temp &= ~FDI_LINK_TRAIN_NONE;
		2498	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2499	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2500	/* SNB-B */
		2501	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2502	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2503
3243	Serge	2504	I915_WRITE(FDI_RX_MISC(pipe),
		2505	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2506
2327	Serge	2507	reg = FDI_RX_CTL(pipe);
		2508	temp = I915_READ(reg);
		2509	if (HAS_PCH_CPT(dev)) {
		2510	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2511	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2512	} else {
		2513	temp &= ~FDI_LINK_TRAIN_NONE;
		2514	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2515	}
		2516	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2517
		2518	POSTING_READ(reg);
		2519	udelay(150);
		2520
2342	Serge	2521	for (i = 0; i < 4; i++) {
2327	Serge	2522	reg = FDI_TX_CTL(pipe);
		2523	temp = I915_READ(reg);
		2524	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2525	temp \|= snb_b_fdi_train_param[i];
		2526	I915_WRITE(reg, temp);
		2527
		2528	POSTING_READ(reg);
		2529	udelay(500);
		2530
3031	serge	2531	for (retry = 0; retry < 5; retry++) {
2327	Serge	2532	reg = FDI_RX_IIR(pipe);
		2533	temp = I915_READ(reg);
		2534	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2535	if (temp & FDI_RX_BIT_LOCK) {
		2536	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2537	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2538	break;
		2539	}
3031	serge	2540	udelay(50);
		2541	}
		2542	if (retry < 5)
		2543	break;
2327	Serge	2544	}
		2545	if (i == 4)
		2546	DRM_ERROR("FDI train 1 fail!\n");
		2547
		2548	/* Train 2 */
		2549	reg = FDI_TX_CTL(pipe);
		2550	temp = I915_READ(reg);
		2551	temp &= ~FDI_LINK_TRAIN_NONE;
		2552	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2553	if (IS_GEN6(dev)) {
		2554	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2555	/* SNB-B */
		2556	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2557	}
		2558	I915_WRITE(reg, temp);
		2559
		2560	reg = FDI_RX_CTL(pipe);
		2561	temp = I915_READ(reg);
		2562	if (HAS_PCH_CPT(dev)) {
		2563	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2564	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2565	} else {
		2566	temp &= ~FDI_LINK_TRAIN_NONE;
		2567	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2568	}
		2569	I915_WRITE(reg, temp);
		2570
		2571	POSTING_READ(reg);
		2572	udelay(150);
		2573
2342	Serge	2574	for (i = 0; i < 4; i++) {
2327	Serge	2575	reg = FDI_TX_CTL(pipe);
		2576	temp = I915_READ(reg);
		2577	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2578	temp \|= snb_b_fdi_train_param[i];
		2579	I915_WRITE(reg, temp);
		2580
		2581	POSTING_READ(reg);
		2582	udelay(500);
		2583
3031	serge	2584	for (retry = 0; retry < 5; retry++) {
2327	Serge	2585	reg = FDI_RX_IIR(pipe);
		2586	temp = I915_READ(reg);
		2587	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2588	if (temp & FDI_RX_SYMBOL_LOCK) {
		2589	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2590	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2591	break;
		2592	}
3031	serge	2593	udelay(50);
		2594	}
		2595	if (retry < 5)
		2596	break;
2327	Serge	2597	}
		2598	if (i == 4)
		2599	DRM_ERROR("FDI train 2 fail!\n");
		2600
		2601	DRM_DEBUG_KMS("FDI train done.\n");
		2602	}
		2603
		2604	/* Manual link training for Ivy Bridge A0 parts */
		2605	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2606	{
		2607	struct drm_device *dev = crtc->dev;
		2608	struct drm_i915_private *dev_priv = dev->dev_private;
		2609	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2610	int pipe = intel_crtc->pipe;
4104	Serge	2611	u32 reg, temp, i, j;
2327	Serge	2612
		2613	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2614	for train result */
		2615	reg = FDI_RX_IMR(pipe);
		2616	temp = I915_READ(reg);
		2617	temp &= ~FDI_RX_SYMBOL_LOCK;
		2618	temp &= ~FDI_RX_BIT_LOCK;
		2619	I915_WRITE(reg, temp);
		2620
		2621	POSTING_READ(reg);
		2622	udelay(150);
		2623
3243	Serge	2624	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		2625	I915_READ(FDI_RX_IIR(pipe)));
		2626
4104	Serge	2627	/* Try each vswing and preemphasis setting twice before moving on */
		2628	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		2629	/* disable first in case we need to retry */
		2630	reg = FDI_TX_CTL(pipe);
		2631	temp = I915_READ(reg);
		2632	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2633	temp &= ~FDI_TX_ENABLE;
		2634	I915_WRITE(reg, temp);
		2635
		2636	reg = FDI_RX_CTL(pipe);
		2637	temp = I915_READ(reg);
		2638	temp &= ~FDI_LINK_TRAIN_AUTO;
		2639	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2640	temp &= ~FDI_RX_ENABLE;
		2641	I915_WRITE(reg, temp);
		2642
2327	Serge	2643	/* enable CPU FDI TX and PCH FDI RX */
		2644	reg = FDI_TX_CTL(pipe);
		2645	temp = I915_READ(reg);
4104	Serge	2646	temp &= ~FDI_DP_PORT_WIDTH_MASK;
		2647	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2327	Serge	2648	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2649	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4104	Serge	2650	temp \|= snb_b_fdi_train_param[j/2];
2342	Serge	2651	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2652	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2653
3243	Serge	2654	I915_WRITE(FDI_RX_MISC(pipe),
		2655	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
		2656
2327	Serge	2657	reg = FDI_RX_CTL(pipe);
		2658	temp = I915_READ(reg);
		2659	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2660	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2661	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2662
		2663	POSTING_READ(reg);
4104	Serge	2664	udelay(1); /* should be 0.5us */
2327	Serge	2665
2342	Serge	2666	for (i = 0; i < 4; i++) {
2327	Serge	2667	reg = FDI_RX_IIR(pipe);
		2668	temp = I915_READ(reg);
		2669	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2670
		2671	if (temp & FDI_RX_BIT_LOCK \|\|
		2672	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2673	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
4104	Serge	2674	DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
		2675	i);
2327	Serge	2676	break;
		2677	}
4104	Serge	2678	udelay(1); /* should be 0.5us */
		2679	}
		2680	if (i == 4) {
		2681	DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
		2682	continue;
2327	Serge	2683	}
		2684
		2685	/* Train 2 */
		2686	reg = FDI_TX_CTL(pipe);
		2687	temp = I915_READ(reg);
		2688	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2689	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2690	I915_WRITE(reg, temp);
		2691
		2692	reg = FDI_RX_CTL(pipe);
		2693	temp = I915_READ(reg);
		2694	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2695	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2696	I915_WRITE(reg, temp);
		2697
		2698	POSTING_READ(reg);
4104	Serge	2699	udelay(2); /* should be 1.5us */
2327	Serge	2700
2342	Serge	2701	for (i = 0; i < 4; i++) {
2327	Serge	2702	reg = FDI_RX_IIR(pipe);
		2703	temp = I915_READ(reg);
		2704	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2705
4104	Serge	2706	if (temp & FDI_RX_SYMBOL_LOCK \|\|
		2707	(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2327	Serge	2708	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
4104	Serge	2709	DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
		2710	i);
		2711	goto train_done;
2327	Serge	2712	}
4104	Serge	2713	udelay(2); /* should be 1.5us */
2327	Serge	2714	}
		2715	if (i == 4)
4104	Serge	2716	DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
		2717	}
2327	Serge	2718
4104	Serge	2719	train_done:
2327	Serge	2720	DRM_DEBUG_KMS("FDI train done.\n");
		2721	}
		2722
3031	serge	2723	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2724	{
3031	serge	2725	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2726	struct drm_i915_private *dev_priv = dev->dev_private;
		2727	int pipe = intel_crtc->pipe;
		2728	u32 reg, temp;
		2729
		2730
		2731	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2732	reg = FDI_RX_CTL(pipe);
		2733	temp = I915_READ(reg);
4104	Serge	2734	temp &= ~(FDI_DP_PORT_WIDTH_MASK \| (0x7 << 16));
		2735	temp \|= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3480	Serge	2736	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2737	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2738
		2739	POSTING_READ(reg);
		2740	udelay(200);
		2741
		2742	/* Switch from Rawclk to PCDclk */
		2743	temp = I915_READ(reg);
		2744	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2745
		2746	POSTING_READ(reg);
		2747	udelay(200);
		2748
		2749	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2750	reg = FDI_TX_CTL(pipe);
		2751	temp = I915_READ(reg);
		2752	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2753	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2754
		2755	POSTING_READ(reg);
		2756	udelay(100);
		2757	}
		2758	}
		2759
3031	serge	2760	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2761	{
		2762	struct drm_device *dev = intel_crtc->base.dev;
		2763	struct drm_i915_private *dev_priv = dev->dev_private;
		2764	int pipe = intel_crtc->pipe;
		2765	u32 reg, temp;
		2766
		2767	/* Switch from PCDclk to Rawclk */
		2768	reg = FDI_RX_CTL(pipe);
		2769	temp = I915_READ(reg);
		2770	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2771
		2772	/* Disable CPU FDI TX PLL */
		2773	reg = FDI_TX_CTL(pipe);
		2774	temp = I915_READ(reg);
		2775	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2776
		2777	POSTING_READ(reg);
		2778	udelay(100);
		2779
		2780	reg = FDI_RX_CTL(pipe);
		2781	temp = I915_READ(reg);
		2782	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2783
		2784	/* Wait for the clocks to turn off. */
		2785	POSTING_READ(reg);
		2786	udelay(100);
		2787	}
		2788
2327	Serge	2789	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2790	{
		2791	struct drm_device *dev = crtc->dev;
		2792	struct drm_i915_private *dev_priv = dev->dev_private;
		2793	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2794	int pipe = intel_crtc->pipe;
		2795	u32 reg, temp;
		2796
		2797	/* disable CPU FDI tx and PCH FDI rx */
		2798	reg = FDI_TX_CTL(pipe);
		2799	temp = I915_READ(reg);
		2800	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2801	POSTING_READ(reg);
		2802
		2803	reg = FDI_RX_CTL(pipe);
		2804	temp = I915_READ(reg);
		2805	temp &= ~(0x7 << 16);
3480	Serge	2806	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2807	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2808
		2809	POSTING_READ(reg);
		2810	udelay(100);
		2811
		2812	/* Ironlake workaround, disable clock pointer after downing FDI */
		2813	if (HAS_PCH_IBX(dev)) {
		2814	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2815	}
		2816
		2817	/* still set train pattern 1 */
		2818	reg = FDI_TX_CTL(pipe);
		2819	temp = I915_READ(reg);
		2820	temp &= ~FDI_LINK_TRAIN_NONE;
		2821	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2822	I915_WRITE(reg, temp);
		2823
		2824	reg = FDI_RX_CTL(pipe);
		2825	temp = I915_READ(reg);
		2826	if (HAS_PCH_CPT(dev)) {
		2827	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2828	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2829	} else {
		2830	temp &= ~FDI_LINK_TRAIN_NONE;
		2831	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2832	}
		2833	/* BPC in FDI rx is consistent with that in PIPECONF */
		2834	temp &= ~(0x07 << 16);
3480	Serge	2835	temp \|= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2327	Serge	2836	I915_WRITE(reg, temp);
		2837
		2838	POSTING_READ(reg);
		2839	udelay(100);
		2840	}
		2841
3031	serge	2842	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2843	{
3031	serge	2844	struct drm_device *dev = crtc->dev;
2327	Serge	2845	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	2846	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2847	unsigned long flags;
		2848	bool pending;
2327	Serge	2849
3480	Serge	2850	if (i915_reset_in_progress(&dev_priv->gpu_error) \|\|
		2851	intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3031	serge	2852	return false;
2327	Serge	2853
3031	serge	2854	spin_lock_irqsave(&dev->event_lock, flags);
		2855	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2856	spin_unlock_irqrestore(&dev->event_lock, flags);
		2857
		2858	return pending;
2327	Serge	2859	}
		2860
3031	serge	2861	#if 0
2327	Serge	2862	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2863	{
3031	serge	2864	struct drm_device *dev = crtc->dev;
		2865	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2866
		2867	if (crtc->fb == NULL)
		2868	return;
		2869
3480	Serge	2870	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
		2871
2360	Serge	2872	wait_event(dev_priv->pending_flip_queue,
3031	serge	2873	!intel_crtc_has_pending_flip(crtc));
		2874
		2875	mutex_lock(&dev->struct_mutex);
		2876	intel_finish_fb(crtc->fb);
		2877	mutex_unlock(&dev->struct_mutex);
2327	Serge	2878	}
3031	serge	2879	#endif
2327	Serge	2880
3031	serge	2881	/* Program iCLKIP clock to the desired frequency */
		2882	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2883	{
		2884	struct drm_device *dev = crtc->dev;
		2885	struct drm_i915_private *dev_priv = dev->dev_private;
		2886	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2887	u32 temp;
		2888
3480	Serge	2889	mutex_lock(&dev_priv->dpio_lock);
		2890
3031	serge	2891	/* It is necessary to ungate the pixclk gate prior to programming
		2892	* the divisors, and gate it back when it is done.
		2893	*/
		2894	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2895
		2896	/* Disable SSCCTL */
		2897	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3243	Serge	2898	intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) \|
		2899	SBI_SSCCTL_DISABLE,
		2900	SBI_ICLK);
3031	serge	2901
		2902	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2903	if (crtc->mode.clock == 20000) {
		2904	auxdiv = 1;
		2905	divsel = 0x41;
		2906	phaseinc = 0x20;
		2907	} else {
		2908	/* The iCLK virtual clock root frequency is in MHz,
		2909	* but the crtc->mode.clock in in KHz. To get the divisors,
		2910	* it is necessary to divide one by another, so we
		2911	* convert the virtual clock precision to KHz here for higher
		2912	* precision.
		2913	*/
		2914	u32 iclk_virtual_root_freq = 172800 * 1000;
		2915	u32 iclk_pi_range = 64;
		2916	u32 desired_divisor, msb_divisor_value, pi_value;
		2917
		2918	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2919	msb_divisor_value = desired_divisor / iclk_pi_range;
		2920	pi_value = desired_divisor % iclk_pi_range;
		2921
		2922	auxdiv = 0;
		2923	divsel = msb_divisor_value - 2;
		2924	phaseinc = pi_value;
		2925	}
		2926
		2927	/* This should not happen with any sane values */
		2928	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2929	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2930	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2931	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2932
		2933	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2934	crtc->mode.clock,
		2935	auxdiv,
		2936	divsel,
		2937	phasedir,
		2938	phaseinc);
		2939
		2940	/* Program SSCDIVINTPHASE6 */
3243	Serge	2941	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3031	serge	2942	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2943	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2944	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2945	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2946	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2947	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
3243	Serge	2948	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031	serge	2949
		2950	/* Program SSCAUXDIV */
3243	Serge	2951	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3031	serge	2952	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2953	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3243	Serge	2954	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3031	serge	2955
		2956	/* Enable modulator and associated divider */
3243	Serge	2957	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3031	serge	2958	temp &= ~SBI_SSCCTL_DISABLE;
3243	Serge	2959	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3031	serge	2960
		2961	/* Wait for initialization time */
		2962	udelay(24);
		2963
		2964	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3480	Serge	2965
		2966	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	2967	}
		2968
4104	Serge	2969	static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
		2970	enum pipe pch_transcoder)
		2971	{
		2972	struct drm_device *dev = crtc->base.dev;
		2973	struct drm_i915_private *dev_priv = dev->dev_private;
		2974	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
		2975
		2976	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		2977	I915_READ(HTOTAL(cpu_transcoder)));
		2978	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		2979	I915_READ(HBLANK(cpu_transcoder)));
		2980	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		2981	I915_READ(HSYNC(cpu_transcoder)));
		2982
		2983	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		2984	I915_READ(VTOTAL(cpu_transcoder)));
		2985	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		2986	I915_READ(VBLANK(cpu_transcoder)));
		2987	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		2988	I915_READ(VSYNC(cpu_transcoder)));
		2989	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		2990	I915_READ(VSYNCSHIFT(cpu_transcoder)));
		2991	}
		2992
4280	Serge	2993	static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
		2994	{
		2995	struct drm_i915_private *dev_priv = dev->dev_private;
		2996	uint32_t temp;
		2997
		2998	temp = I915_READ(SOUTH_CHICKEN1);
		2999	if (temp & FDI_BC_BIFURCATION_SELECT)
		3000	return;
		3001
		3002	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		3003	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
		3004
		3005	temp \|= FDI_BC_BIFURCATION_SELECT;
		3006	DRM_DEBUG_KMS("enabling fdi C rx\n");
		3007	I915_WRITE(SOUTH_CHICKEN1, temp);
		3008	POSTING_READ(SOUTH_CHICKEN1);
		3009	}
		3010
		3011	static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
		3012	{
		3013	struct drm_device *dev = intel_crtc->base.dev;
		3014	struct drm_i915_private *dev_priv = dev->dev_private;
		3015
		3016	switch (intel_crtc->pipe) {
		3017	case PIPE_A:
		3018	break;
		3019	case PIPE_B:
		3020	if (intel_crtc->config.fdi_lanes > 2)
		3021	WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		3022	else
		3023	cpt_enable_fdi_bc_bifurcation(dev);
		3024
		3025	break;
		3026	case PIPE_C:
		3027	cpt_enable_fdi_bc_bifurcation(dev);
		3028
		3029	break;
		3030	default:
		3031	BUG();
		3032	}
		3033	}
		3034
2327	Serge	3035	/*
		3036	* Enable PCH resources required for PCH ports:
		3037	* - PCH PLLs
		3038	* - FDI training & RX/TX
		3039	* - update transcoder timings
		3040	* - DP transcoding bits
		3041	* - transcoder
		3042	*/
		3043	static void ironlake_pch_enable(struct drm_crtc *crtc)
		3044	{
		3045	struct drm_device *dev = crtc->dev;
		3046	struct drm_i915_private *dev_priv = dev->dev_private;
		3047	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3048	int pipe = intel_crtc->pipe;
3031	serge	3049	u32 reg, temp;
2327	Serge	3050
4104	Serge	3051	assert_pch_transcoder_disabled(dev_priv, pipe);
3031	serge	3052
4280	Serge	3053	if (IS_IVYBRIDGE(dev))
		3054	ivybridge_update_fdi_bc_bifurcation(intel_crtc);
		3055
3243	Serge	3056	/* Write the TU size bits before fdi link training, so that error
		3057	* detection works. */
		3058	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		3059	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		3060
2327	Serge	3061	/* For PCH output, training FDI link */
		3062	dev_priv->display.fdi_link_train(crtc);
		3063
4104	Serge	3064	/* We need to program the right clock selection before writing the pixel
		3065	* mutliplier into the DPLL. */
3243	Serge	3066	if (HAS_PCH_CPT(dev)) {
3031	serge	3067	u32 sel;
2342	Serge	3068
2327	Serge	3069	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3070	temp \|= TRANS_DPLL_ENABLE(pipe);
		3071	sel = TRANS_DPLLB_SEL(pipe);
		3072	if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3031	serge	3073	temp \|= sel;
		3074	else
		3075	temp &= ~sel;
2327	Serge	3076	I915_WRITE(PCH_DPLL_SEL, temp);
		3077	}
		3078
4104	Serge	3079	/* XXX: pch pll's can be enabled any time before we enable the PCH
		3080	* transcoder, and we actually should do this to not upset any PCH
		3081	* transcoder that already use the clock when we share it.
		3082	*
		3083	* Note that enable_shared_dpll tries to do the right thing, but
		3084	* get_shared_dpll unconditionally resets the pll - we need that to have
		3085	* the right LVDS enable sequence. */
		3086	ironlake_enable_shared_dpll(intel_crtc);
		3087
2327	Serge	3088	/* set transcoder timing, panel must allow it */
		3089	assert_panel_unlocked(dev_priv, pipe);
4104	Serge	3090	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2327	Serge	3091
		3092	intel_fdi_normal_train(crtc);
		3093
		3094	/* For PCH DP, enable TRANS_DP_CTL */
		3095	if (HAS_PCH_CPT(dev) &&
2342	Serge	3096	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3097	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3480	Serge	3098	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2327	Serge	3099	reg = TRANS_DP_CTL(pipe);
		3100	temp = I915_READ(reg);
		3101	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3102	TRANS_DP_SYNC_MASK \|
		3103	TRANS_DP_BPC_MASK);
		3104	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3105	TRANS_DP_ENH_FRAMING);
		3106	temp \|= bpc << 9; /* same format but at 11:9 */
		3107
		3108	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3109	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3110	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3111	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3112
		3113	switch (intel_trans_dp_port_sel(crtc)) {
		3114	case PCH_DP_B:
		3115	temp \|= TRANS_DP_PORT_SEL_B;
		3116	break;
		3117	case PCH_DP_C:
		3118	temp \|= TRANS_DP_PORT_SEL_C;
		3119	break;
		3120	case PCH_DP_D:
		3121	temp \|= TRANS_DP_PORT_SEL_D;
		3122	break;
		3123	default:
3243	Serge	3124	BUG();
2327	Serge	3125	}
		3126
		3127	I915_WRITE(reg, temp);
		3128	}
		3129
3243	Serge	3130	ironlake_enable_pch_transcoder(dev_priv, pipe);
2327	Serge	3131	}
		3132
3243	Serge	3133	static void lpt_pch_enable(struct drm_crtc *crtc)
		3134	{
		3135	struct drm_device *dev = crtc->dev;
		3136	struct drm_i915_private *dev_priv = dev->dev_private;
		3137	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	3138	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3139
4104	Serge	3140	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3243	Serge	3141
		3142	lpt_program_iclkip(crtc);
		3143
		3144	/* Set transcoder timing. */
4104	Serge	3145	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3243	Serge	3146
		3147	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
		3148	}
		3149
4104	Serge	3150	static void intel_put_shared_dpll(struct intel_crtc *crtc)
3031	serge	3151	{
4104	Serge	3152	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031	serge	3153
		3154	if (pll == NULL)
		3155	return;
		3156
		3157	if (pll->refcount == 0) {
4104	Serge	3158	WARN(1, "bad %s refcount\n", pll->name);
3031	serge	3159	return;
		3160	}
		3161
4104	Serge	3162	if (--pll->refcount == 0) {
		3163	WARN_ON(pll->on);
		3164	WARN_ON(pll->active);
		3165	}
		3166
		3167	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3031	serge	3168	}
		3169
4104	Serge	3170	static struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc)
3031	serge	3171	{
4104	Serge	3172	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3173	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
		3174	enum intel_dpll_id i;
3031	serge	3175
		3176	if (pll) {
4104	Serge	3177	DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
		3178	crtc->base.base.id, pll->name);
		3179	intel_put_shared_dpll(crtc);
3031	serge	3180	}
		3181
		3182	if (HAS_PCH_IBX(dev_priv->dev)) {
		3183	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4104	Serge	3184	i = (enum intel_dpll_id) crtc->pipe;
		3185	pll = &dev_priv->shared_dplls[i];
3031	serge	3186
4104	Serge	3187	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
		3188	crtc->base.base.id, pll->name);
3031	serge	3189
		3190	goto found;
		3191	}
		3192
4104	Serge	3193	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3194	pll = &dev_priv->shared_dplls[i];
3031	serge	3195
		3196	/* Only want to check enabled timings first */
		3197	if (pll->refcount == 0)
		3198	continue;
		3199
4104	Serge	3200	if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
		3201	sizeof(pll->hw_state)) == 0) {
		3202	DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
		3203	crtc->base.base.id,
		3204	pll->name, pll->refcount, pll->active);
3031	serge	3205
		3206	goto found;
		3207	}
		3208	}
		3209
		3210	/* Ok no matching timings, maybe there's a free one? */
4104	Serge	3211	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3212	pll = &dev_priv->shared_dplls[i];
3031	serge	3213	if (pll->refcount == 0) {
4104	Serge	3214	DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
		3215	crtc->base.base.id, pll->name);
3031	serge	3216	goto found;
		3217	}
		3218	}
		3219
		3220	return NULL;
		3221
		3222	found:
4104	Serge	3223	crtc->config.shared_dpll = i;
		3224	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
		3225	pipe_name(crtc->pipe));
		3226
		3227	if (pll->active == 0) {
		3228	memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
		3229	sizeof(pll->hw_state));
		3230
		3231	DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
		3232	WARN_ON(pll->on);
		3233	assert_shared_dpll_disabled(dev_priv, pll);
		3234
		3235	pll->mode_set(dev_priv, pll);
		3236	}
3031	serge	3237	pll->refcount++;
		3238
		3239	return pll;
		3240	}
		3241
4104	Serge	3242	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
2342	Serge	3243	{
		3244	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3245	int dslreg = PIPEDSL(pipe);
2342	Serge	3246	u32 temp;
		3247
		3248	temp = I915_READ(dslreg);
		3249	udelay(500);
		3250	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3251	if (wait_for(I915_READ(dslreg) != temp, 5))
4104	Serge	3252	DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
2342	Serge	3253	}
		3254	}
		3255
4104	Serge	3256	static void ironlake_pfit_enable(struct intel_crtc *crtc)
		3257	{
		3258	struct drm_device *dev = crtc->base.dev;
		3259	struct drm_i915_private *dev_priv = dev->dev_private;
		3260	int pipe = crtc->pipe;
		3261
		3262	if (crtc->config.pch_pfit.enabled) {
		3263	/* Force use of hard-coded filter coefficients
		3264	* as some pre-programmed values are broken,
		3265	* e.g. x201.
		3266	*/
		3267	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		3268	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3 \|
		3269	PF_PIPE_SEL_IVB(pipe));
		3270	else
		3271	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3272	I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		3273	I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
		3274	}
		3275	}
		3276
		3277	static void intel_enable_planes(struct drm_crtc *crtc)
		3278	{
		3279	struct drm_device *dev = crtc->dev;
		3280	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3281	struct intel_plane *intel_plane;
		3282
		3283	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3284	if (intel_plane->pipe == pipe)
		3285	intel_plane_restore(&intel_plane->base);
		3286	}
		3287
		3288	static void intel_disable_planes(struct drm_crtc *crtc)
		3289	{
		3290	struct drm_device *dev = crtc->dev;
		3291	enum pipe pipe = to_intel_crtc(crtc)->pipe;
		3292	struct intel_plane *intel_plane;
		3293
		3294	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		3295	if (intel_plane->pipe == pipe)
		3296	intel_plane_disable(&intel_plane->base);
		3297	}
		3298
2327	Serge	3299	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3300	{
		3301	struct drm_device *dev = crtc->dev;
		3302	struct drm_i915_private *dev_priv = dev->dev_private;
		3303	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3304	struct intel_encoder *encoder;
2327	Serge	3305	int pipe = intel_crtc->pipe;
		3306	int plane = intel_crtc->plane;
		3307
3031	serge	3308	WARN_ON(!crtc->enabled);
		3309
2327	Serge	3310	if (intel_crtc->active)
		3311	return;
		3312
		3313	intel_crtc->active = true;
4104	Serge	3314
		3315	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3316	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
		3317
2327	Serge	3318	intel_update_watermarks(dev);
		3319
4104	Serge	3320	for_each_encoder_on_crtc(dev, crtc, encoder)
		3321	if (encoder->pre_enable)
		3322	encoder->pre_enable(encoder);
2327	Serge	3323
3746	Serge	3324	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3325	/* Note: FDI PLL enabling _must_ be done before we enable the
		3326	* cpu pipes, hence this is separate from all the other fdi/pch
		3327	* enabling. */
3031	serge	3328	ironlake_fdi_pll_enable(intel_crtc);
		3329	} else {
		3330	assert_fdi_tx_disabled(dev_priv, pipe);
		3331	assert_fdi_rx_disabled(dev_priv, pipe);
		3332	}
2327	Serge	3333
4104	Serge	3334	ironlake_pfit_enable(intel_crtc);
3031	serge	3335
2327	Serge	3336	/*
		3337	* On ILK+ LUT must be loaded before the pipe is running but with
		3338	* clocks enabled
		3339	*/
		3340	intel_crtc_load_lut(crtc);
		3341
3746	Serge	3342	intel_enable_pipe(dev_priv, pipe,
		3343	intel_crtc->config.has_pch_encoder);
2327	Serge	3344	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3345	intel_enable_planes(crtc);
		3346	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3347
3746	Serge	3348	if (intel_crtc->config.has_pch_encoder)
2327	Serge	3349	ironlake_pch_enable(crtc);
		3350
		3351	mutex_lock(&dev->struct_mutex);
		3352	intel_update_fbc(dev);
		3353	mutex_unlock(&dev->struct_mutex);
		3354
3031	serge	3355	for_each_encoder_on_crtc(dev, crtc, encoder)
		3356	encoder->enable(encoder);
		3357
		3358	if (HAS_PCH_CPT(dev))
4104	Serge	3359	cpt_verify_modeset(dev, intel_crtc->pipe);
3031	serge	3360
		3361	/*
		3362	* There seems to be a race in PCH platform hw (at least on some
		3363	* outputs) where an enabled pipe still completes any pageflip right
		3364	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3365	* as the first vblank happend, everything works as expected. Hence just
		3366	* wait for one vblank before returning to avoid strange things
		3367	* happening.
		3368	*/
		3369	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3370	}
		3371
4104	Serge	3372	/* IPS only exists on ULT machines and is tied to pipe A. */
		3373	static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
		3374	{
		3375	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
		3376	}
		3377
		3378	static void hsw_enable_ips(struct intel_crtc *crtc)
		3379	{
		3380	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		3381
		3382	if (!crtc->config.ips_enabled)
		3383	return;
		3384
		3385	/* We can only enable IPS after we enable a plane and wait for a vblank.
		3386	* We guarantee that the plane is enabled by calling intel_enable_ips
		3387	* only after intel_enable_plane. And intel_enable_plane already waits
		3388	* for a vblank, so all we need to do here is to enable the IPS bit. */
		3389	assert_plane_enabled(dev_priv, crtc->plane);
		3390	I915_WRITE(IPS_CTL, IPS_ENABLE);
		3391	}
		3392
		3393	static void hsw_disable_ips(struct intel_crtc *crtc)
		3394	{
		3395	struct drm_device *dev = crtc->base.dev;
		3396	struct drm_i915_private *dev_priv = dev->dev_private;
		3397
		3398	if (!crtc->config.ips_enabled)
		3399	return;
		3400
		3401	assert_plane_enabled(dev_priv, crtc->plane);
		3402	I915_WRITE(IPS_CTL, 0);
		3403
		3404	/* We need to wait for a vblank before we can disable the plane. */
		3405	intel_wait_for_vblank(dev, crtc->pipe);
		3406	}
		3407
3243	Serge	3408	static void haswell_crtc_enable(struct drm_crtc *crtc)
		3409	{
		3410	struct drm_device *dev = crtc->dev;
		3411	struct drm_i915_private *dev_priv = dev->dev_private;
		3412	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3413	struct intel_encoder *encoder;
		3414	int pipe = intel_crtc->pipe;
		3415	int plane = intel_crtc->plane;
		3416
		3417	WARN_ON(!crtc->enabled);
		3418
		3419	if (intel_crtc->active)
		3420	return;
		3421
		3422	intel_crtc->active = true;
4104	Serge	3423
		3424	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
		3425	if (intel_crtc->config.has_pch_encoder)
		3426	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
		3427
3243	Serge	3428	intel_update_watermarks(dev);
		3429
3746	Serge	3430	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3431	dev_priv->display.fdi_link_train(crtc);
		3432
		3433	for_each_encoder_on_crtc(dev, crtc, encoder)
		3434	if (encoder->pre_enable)
		3435	encoder->pre_enable(encoder);
		3436
		3437	intel_ddi_enable_pipe_clock(intel_crtc);
		3438
4104	Serge	3439	ironlake_pfit_enable(intel_crtc);
3243	Serge	3440
		3441	/*
		3442	* On ILK+ LUT must be loaded before the pipe is running but with
		3443	* clocks enabled
		3444	*/
		3445	intel_crtc_load_lut(crtc);
		3446
		3447	intel_ddi_set_pipe_settings(crtc);
3746	Serge	3448	intel_ddi_enable_transcoder_func(crtc);
3243	Serge	3449
3746	Serge	3450	intel_enable_pipe(dev_priv, pipe,
		3451	intel_crtc->config.has_pch_encoder);
3243	Serge	3452	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3453	intel_enable_planes(crtc);
		3454	// intel_crtc_update_cursor(crtc, true);
3243	Serge	3455
4104	Serge	3456	hsw_enable_ips(intel_crtc);
		3457
3746	Serge	3458	if (intel_crtc->config.has_pch_encoder)
3243	Serge	3459	lpt_pch_enable(crtc);
		3460
		3461	mutex_lock(&dev->struct_mutex);
		3462	intel_update_fbc(dev);
		3463	mutex_unlock(&dev->struct_mutex);
		3464
		3465	for_each_encoder_on_crtc(dev, crtc, encoder)
		3466	encoder->enable(encoder);
		3467
		3468	/*
		3469	* There seems to be a race in PCH platform hw (at least on some
		3470	* outputs) where an enabled pipe still completes any pageflip right
		3471	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3472	* as the first vblank happend, everything works as expected. Hence just
		3473	* wait for one vblank before returning to avoid strange things
		3474	* happening.
		3475	*/
		3476	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3477	}
		3478
4104	Serge	3479	static void ironlake_pfit_disable(struct intel_crtc *crtc)
		3480	{
		3481	struct drm_device *dev = crtc->base.dev;
		3482	struct drm_i915_private *dev_priv = dev->dev_private;
		3483	int pipe = crtc->pipe;
		3484
		3485	/* To avoid upsetting the power well on haswell only disable the pfit if
		3486	* it's in use. The hw state code will make sure we get this right. */
		3487	if (crtc->config.pch_pfit.enabled) {
		3488	I915_WRITE(PF_CTL(pipe), 0);
		3489	I915_WRITE(PF_WIN_POS(pipe), 0);
		3490	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3491	}
		3492	}
		3493
2327	Serge	3494	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3495	{
		3496	struct drm_device *dev = crtc->dev;
		3497	struct drm_i915_private *dev_priv = dev->dev_private;
		3498	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3499	struct intel_encoder *encoder;
2327	Serge	3500	int pipe = intel_crtc->pipe;
		3501	int plane = intel_crtc->plane;
		3502	u32 reg, temp;
		3503
3031	serge	3504
2327	Serge	3505	if (!intel_crtc->active)
		3506	return;
		3507
3031	serge	3508	for_each_encoder_on_crtc(dev, crtc, encoder)
		3509	encoder->disable(encoder);
2336	Serge	3510
3031	serge	3511	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3512	// drm_vblank_off(dev, pipe);
		3513
4104	Serge	3514	if (dev_priv->fbc.plane == plane)
		3515	intel_disable_fbc(dev);
		3516
		3517	// intel_crtc_update_cursor(crtc, false);
		3518	intel_disable_planes(crtc);
2327	Serge	3519	intel_disable_plane(dev_priv, plane, pipe);
		3520
4104	Serge	3521	if (intel_crtc->config.has_pch_encoder)
		3522	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
2327	Serge	3523
		3524	intel_disable_pipe(dev_priv, pipe);
		3525
4104	Serge	3526	ironlake_pfit_disable(intel_crtc);
2327	Serge	3527
3031	serge	3528	for_each_encoder_on_crtc(dev, crtc, encoder)
		3529	if (encoder->post_disable)
		3530	encoder->post_disable(encoder);
		3531
4104	Serge	3532	if (intel_crtc->config.has_pch_encoder) {
2327	Serge	3533	ironlake_fdi_disable(crtc);
		3534
3243	Serge	3535	ironlake_disable_pch_transcoder(dev_priv, pipe);
4104	Serge	3536	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
2327	Serge	3537
		3538	if (HAS_PCH_CPT(dev)) {
		3539	/* disable TRANS_DP_CTL */
		3540	reg = TRANS_DP_CTL(pipe);
		3541	temp = I915_READ(reg);
4104	Serge	3542	temp &= ~(TRANS_DP_OUTPUT_ENABLE \|
		3543	TRANS_DP_PORT_SEL_MASK);
2327	Serge	3544	temp \|= TRANS_DP_PORT_SEL_NONE;
		3545	I915_WRITE(reg, temp);
		3546
		3547	/* disable DPLL_SEL */
		3548	temp = I915_READ(PCH_DPLL_SEL);
4104	Serge	3549	temp &= ~(TRANS_DPLL_ENABLE(pipe) \| TRANS_DPLLB_SEL(pipe));
2327	Serge	3550	I915_WRITE(PCH_DPLL_SEL, temp);
		3551	}
		3552
		3553	/* disable PCH DPLL */
4104	Serge	3554	intel_disable_shared_dpll(intel_crtc);
2327	Serge	3555
3031	serge	3556	ironlake_fdi_pll_disable(intel_crtc);
4104	Serge	3557	}
2327	Serge	3558
		3559	intel_crtc->active = false;
		3560	intel_update_watermarks(dev);
		3561
		3562	mutex_lock(&dev->struct_mutex);
		3563	intel_update_fbc(dev);
		3564	mutex_unlock(&dev->struct_mutex);
		3565	}
		3566
3243	Serge	3567	static void haswell_crtc_disable(struct drm_crtc *crtc)
		3568	{
		3569	struct drm_device *dev = crtc->dev;
		3570	struct drm_i915_private *dev_priv = dev->dev_private;
		3571	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3572	struct intel_encoder *encoder;
		3573	int pipe = intel_crtc->pipe;
		3574	int plane = intel_crtc->plane;
3746	Serge	3575	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	3576
		3577	if (!intel_crtc->active)
		3578	return;
		3579
		3580	for_each_encoder_on_crtc(dev, crtc, encoder)
		3581	encoder->disable(encoder);
		3582
		3583
4104	Serge	3584	/* FBC must be disabled before disabling the plane on HSW. */
		3585	if (dev_priv->fbc.plane == plane)
		3586	intel_disable_fbc(dev);
		3587
		3588	hsw_disable_ips(intel_crtc);
		3589
		3590	// intel_crtc_update_cursor(crtc, false);
		3591	intel_disable_planes(crtc);
3243	Serge	3592	intel_disable_plane(dev_priv, plane, pipe);
		3593
4104	Serge	3594	if (intel_crtc->config.has_pch_encoder)
		3595	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3243	Serge	3596	intel_disable_pipe(dev_priv, pipe);
		3597
		3598	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
		3599
4104	Serge	3600	ironlake_pfit_disable(intel_crtc);
3243	Serge	3601
		3602	intel_ddi_disable_pipe_clock(intel_crtc);
		3603
		3604	for_each_encoder_on_crtc(dev, crtc, encoder)
		3605	if (encoder->post_disable)
		3606	encoder->post_disable(encoder);
		3607
3746	Serge	3608	if (intel_crtc->config.has_pch_encoder) {
3243	Serge	3609	lpt_disable_pch_transcoder(dev_priv);
4104	Serge	3610	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3243	Serge	3611	intel_ddi_fdi_disable(crtc);
		3612	}
		3613
		3614	intel_crtc->active = false;
		3615	intel_update_watermarks(dev);
		3616
		3617	mutex_lock(&dev->struct_mutex);
		3618	intel_update_fbc(dev);
		3619	mutex_unlock(&dev->struct_mutex);
		3620	}
		3621
3031	serge	3622	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3623	{
		3624	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	3625	intel_put_shared_dpll(intel_crtc);
2327	Serge	3626	}
		3627
3243	Serge	3628	static void haswell_crtc_off(struct drm_crtc *crtc)
		3629	{
		3630	intel_ddi_put_crtc_pll(crtc);
		3631	}
		3632
2327	Serge	3633	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3634	{
		3635	if (!enable && intel_crtc->overlay) {
		3636	struct drm_device *dev = intel_crtc->base.dev;
		3637	struct drm_i915_private *dev_priv = dev->dev_private;
		3638
		3639	mutex_lock(&dev->struct_mutex);
		3640	dev_priv->mm.interruptible = false;
		3641	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3642	dev_priv->mm.interruptible = true;
		3643	mutex_unlock(&dev->struct_mutex);
		3644	}
		3645
		3646	/* Let userspace switch the overlay on again. In most cases userspace
		3647	* has to recompute where to put it anyway.
		3648	*/
		3649	}
		3650
3480	Serge	3651	/**
		3652	* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
		3653	* cursor plane briefly if not already running after enabling the display
		3654	* plane.
		3655	* This workaround avoids occasional blank screens when self refresh is
		3656	* enabled.
		3657	*/
		3658	static void
		3659	g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
		3660	{
		3661	u32 cntl = I915_READ(CURCNTR(pipe));
		3662
		3663	if ((cntl & CURSOR_MODE) == 0) {
		3664	u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
		3665
		3666	I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		3667	I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		3668	intel_wait_for_vblank(dev_priv->dev, pipe);
		3669	I915_WRITE(CURCNTR(pipe), cntl);
		3670	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		3671	I915_WRITE(FW_BLC_SELF, fw_bcl_self);
		3672	}
		3673	}
		3674
4104	Serge	3675	static void i9xx_pfit_enable(struct intel_crtc *crtc)
		3676	{
		3677	struct drm_device *dev = crtc->base.dev;
		3678	struct drm_i915_private *dev_priv = dev->dev_private;
		3679	struct intel_crtc_config *pipe_config = &crtc->config;
		3680
		3681	if (!crtc->config.gmch_pfit.control)
		3682	return;
		3683
		3684	/*
		3685	* The panel fitter should only be adjusted whilst the pipe is disabled,
		3686	* according to register description and PRM.
		3687	*/
		3688	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
		3689	assert_pipe_disabled(dev_priv, crtc->pipe);
		3690
		3691	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
		3692	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
		3693
		3694	/* Border color in case we don't scale up to the full screen. Black by
		3695	* default, change to something else for debugging. */
		3696	I915_WRITE(BCLRPAT(crtc->pipe), 0);
		3697	}
		3698
		3699	static void valleyview_crtc_enable(struct drm_crtc *crtc)
		3700	{
		3701	struct drm_device *dev = crtc->dev;
		3702	struct drm_i915_private *dev_priv = dev->dev_private;
		3703	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3704	struct intel_encoder *encoder;
		3705	int pipe = intel_crtc->pipe;
		3706	int plane = intel_crtc->plane;
		3707
		3708	WARN_ON(!crtc->enabled);
		3709
		3710	if (intel_crtc->active)
		3711	return;
		3712
		3713	intel_crtc->active = true;
		3714	intel_update_watermarks(dev);
		3715
		3716	for_each_encoder_on_crtc(dev, crtc, encoder)
		3717	if (encoder->pre_pll_enable)
		3718	encoder->pre_pll_enable(encoder);
		3719
		3720	vlv_enable_pll(intel_crtc);
		3721
		3722	for_each_encoder_on_crtc(dev, crtc, encoder)
		3723	if (encoder->pre_enable)
		3724	encoder->pre_enable(encoder);
		3725
		3726	i9xx_pfit_enable(intel_crtc);
		3727
		3728	intel_crtc_load_lut(crtc);
		3729
		3730	intel_enable_pipe(dev_priv, pipe, false);
		3731	intel_enable_plane(dev_priv, plane, pipe);
		3732	intel_enable_planes(crtc);
		3733	// intel_crtc_update_cursor(crtc, true);
		3734
		3735	intel_update_fbc(dev);
		3736
		3737	for_each_encoder_on_crtc(dev, crtc, encoder)
		3738	encoder->enable(encoder);
		3739	}
		3740
2327	Serge	3741	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3742	{
		3743	struct drm_device *dev = crtc->dev;
		3744	struct drm_i915_private *dev_priv = dev->dev_private;
		3745	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3746	struct intel_encoder *encoder;
2327	Serge	3747	int pipe = intel_crtc->pipe;
		3748	int plane = intel_crtc->plane;
		3749
3031	serge	3750	WARN_ON(!crtc->enabled);
		3751
2327	Serge	3752	if (intel_crtc->active)
		3753	return;
		3754
		3755	intel_crtc->active = true;
		3756	intel_update_watermarks(dev);
		3757
3480	Serge	3758	for_each_encoder_on_crtc(dev, crtc, encoder)
		3759	if (encoder->pre_enable)
		3760	encoder->pre_enable(encoder);
		3761
4104	Serge	3762	i9xx_enable_pll(intel_crtc);
		3763
		3764	i9xx_pfit_enable(intel_crtc);
		3765
		3766	intel_crtc_load_lut(crtc);
		3767
2327	Serge	3768	intel_enable_pipe(dev_priv, pipe, false);
		3769	intel_enable_plane(dev_priv, plane, pipe);
4104	Serge	3770	intel_enable_planes(crtc);
		3771	/* The fixup needs to happen before cursor is enabled */
3480	Serge	3772	if (IS_G4X(dev))
		3773	g4x_fixup_plane(dev_priv, pipe);
4104	Serge	3774	// intel_crtc_update_cursor(crtc, true);
2327	Serge	3775
		3776	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3777	intel_crtc_dpms_overlay(intel_crtc, true);
3031	serge	3778
4104	Serge	3779	intel_update_fbc(dev);
		3780
3031	serge	3781	for_each_encoder_on_crtc(dev, crtc, encoder)
		3782	encoder->enable(encoder);
2327	Serge	3783	}
		3784
3746	Serge	3785	static void i9xx_pfit_disable(struct intel_crtc *crtc)
		3786	{
		3787	struct drm_device *dev = crtc->base.dev;
		3788	struct drm_i915_private *dev_priv = dev->dev_private;
		3789
4104	Serge	3790	if (!crtc->config.gmch_pfit.control)
		3791	return;
		3792
3746	Serge	3793	assert_pipe_disabled(dev_priv, crtc->pipe);
		3794
4104	Serge	3795	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
		3796	I915_READ(PFIT_CONTROL));
3746	Serge	3797	I915_WRITE(PFIT_CONTROL, 0);
		3798	}
		3799
2327	Serge	3800	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3801	{
		3802	struct drm_device *dev = crtc->dev;
		3803	struct drm_i915_private *dev_priv = dev->dev_private;
		3804	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3805	struct intel_encoder *encoder;
2327	Serge	3806	int pipe = intel_crtc->pipe;
		3807	int plane = intel_crtc->plane;
		3808
		3809	if (!intel_crtc->active)
		3810	return;
		3811
3031	serge	3812	for_each_encoder_on_crtc(dev, crtc, encoder)
		3813	encoder->disable(encoder);
		3814
2327	Serge	3815	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3816	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3817	// drm_vblank_off(dev, pipe);
		3818
4104	Serge	3819	if (dev_priv->fbc.plane == plane)
2327	Serge	3820	intel_disable_fbc(dev);
		3821
4104	Serge	3822	intel_crtc_dpms_overlay(intel_crtc, false);
		3823	// intel_crtc_update_cursor(crtc, false);
		3824	intel_disable_planes(crtc);
2327	Serge	3825	intel_disable_plane(dev_priv, plane, pipe);
4104	Serge	3826
2327	Serge	3827	intel_disable_pipe(dev_priv, pipe);
3480	Serge	3828
3746	Serge	3829	i9xx_pfit_disable(intel_crtc);
3480	Serge	3830
4104	Serge	3831	for_each_encoder_on_crtc(dev, crtc, encoder)
		3832	if (encoder->post_disable)
		3833	encoder->post_disable(encoder);
2327	Serge	3834
4104	Serge	3835	i9xx_disable_pll(dev_priv, pipe);
		3836
2327	Serge	3837	intel_crtc->active = false;
		3838	intel_update_fbc(dev);
		3839	intel_update_watermarks(dev);
		3840	}
		3841
3031	serge	3842	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3843	{
		3844	}
		3845
3031	serge	3846	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3847	bool enabled)
2330	Serge	3848	{
		3849	struct drm_device *dev = crtc->dev;
		3850	struct drm_i915_master_private *master_priv;
		3851	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3852	int pipe = intel_crtc->pipe;
2327	Serge	3853
		3854
2340	Serge	3855	#if 0
2330	Serge	3856	if (!dev->primary->master)
		3857	return;
2327	Serge	3858
2330	Serge	3859	master_priv = dev->primary->master->driver_priv;
		3860	if (!master_priv->sarea_priv)
		3861	return;
2327	Serge	3862
2330	Serge	3863	switch (pipe) {
		3864	case 0:
		3865	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3866	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3867	break;
		3868	case 1:
		3869	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3870	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3871	break;
		3872	default:
		3873	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3874	break;
		3875	}
2340	Serge	3876	#endif
		3877
2330	Serge	3878	}
2327	Serge	3879
3031	serge	3880	/**
		3881	* Sets the power management mode of the pipe and plane.
		3882	*/
		3883	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3884	{
		3885	struct drm_device *dev = crtc->dev;
		3886	struct drm_i915_private *dev_priv = dev->dev_private;
		3887	struct intel_encoder *intel_encoder;
		3888	bool enable = false;
		3889
		3890	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3891	enable \|= intel_encoder->connectors_active;
		3892
		3893	if (enable)
		3894	dev_priv->display.crtc_enable(crtc);
		3895	else
		3896	dev_priv->display.crtc_disable(crtc);
		3897
		3898	intel_crtc_update_sarea(crtc, enable);
		3899	}
		3900
2330	Serge	3901	static void intel_crtc_disable(struct drm_crtc *crtc)
		3902	{
		3903	struct drm_device *dev = crtc->dev;
3031	serge	3904	struct drm_connector *connector;
		3905	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	3906	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	3907
3031	serge	3908	/* crtc should still be enabled when we disable it. */
		3909	WARN_ON(!crtc->enabled);
2327	Serge	3910
4104	Serge	3911	dev_priv->display.crtc_disable(crtc);
3480	Serge	3912	intel_crtc->eld_vld = false;
3031	serge	3913	intel_crtc_update_sarea(crtc, false);
		3914	dev_priv->display.off(crtc);
		3915
		3916	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3917	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3918
4280	Serge	3919	if (crtc->fb) {
		3920	mutex_lock(&dev->struct_mutex);
		3921	intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3922	mutex_unlock(&dev->struct_mutex);
		3923	crtc->fb = NULL;
		3924	}
3031	serge	3925
		3926	/* Update computed state. */
		3927	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3928	if (!connector->encoder \|\| !connector->encoder->crtc)
		3929	continue;
		3930
		3931	if (connector->encoder->crtc != crtc)
		3932	continue;
		3933
		3934	connector->dpms = DRM_MODE_DPMS_OFF;
		3935	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3936	}
		3937	}
2327	Serge	3938
3031	serge	3939	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3940	{
3031	serge	3941	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3942
		3943	drm_encoder_cleanup(encoder);
		3944	kfree(intel_encoder);
2330	Serge	3945	}
2327	Serge	3946
4104	Serge	3947	/* Simple dpms helper for encoders with just one connector, no cloning and only
3031	serge	3948	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3949	* state of the entire output pipe. */
4104	Serge	3950	static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3951	{
3031	serge	3952	if (mode == DRM_MODE_DPMS_ON) {
		3953	encoder->connectors_active = true;
		3954
		3955	intel_crtc_update_dpms(encoder->base.crtc);
		3956	} else {
		3957	encoder->connectors_active = false;
		3958
		3959	intel_crtc_update_dpms(encoder->base.crtc);
		3960	}
2330	Serge	3961	}
2327	Serge	3962
3031	serge	3963	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3964	* internal consistency). */
		3965	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3966	{
3031	serge	3967	if (connector->get_hw_state(connector)) {
		3968	struct intel_encoder *encoder = connector->encoder;
		3969	struct drm_crtc *crtc;
		3970	bool encoder_enabled;
		3971	enum pipe pipe;
		3972
		3973	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3974	connector->base.base.id,
		3975	drm_get_connector_name(&connector->base));
		3976
		3977	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3978	"wrong connector dpms state\n");
		3979	WARN(connector->base.encoder != &encoder->base,
		3980	"active connector not linked to encoder\n");
		3981	WARN(!encoder->connectors_active,
		3982	"encoder->connectors_active not set\n");
		3983
		3984	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3985	WARN(!encoder_enabled, "encoder not enabled\n");
		3986	if (WARN_ON(!encoder->base.crtc))
		3987	return;
		3988
		3989	crtc = encoder->base.crtc;
		3990
		3991	WARN(!crtc->enabled, "crtc not enabled\n");
		3992	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3993	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3994	"encoder active on the wrong pipe\n");
		3995	}
2330	Serge	3996	}
2327	Serge	3997
3031	serge	3998	/* Even simpler default implementation, if there's really no special case to
		3999	* consider. */
		4000	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	4001	{
3031	serge	4002	/* All the simple cases only support two dpms states. */
		4003	if (mode != DRM_MODE_DPMS_ON)
		4004	mode = DRM_MODE_DPMS_OFF;
2342	Serge	4005
3031	serge	4006	if (mode == connector->dpms)
		4007	return;
		4008
		4009	connector->dpms = mode;
		4010
		4011	/* Only need to change hw state when actually enabled */
4104	Serge	4012	if (connector->encoder)
		4013	intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3031	serge	4014
		4015	intel_modeset_check_state(connector->dev);
2330	Serge	4016	}
2327	Serge	4017
3031	serge	4018	/* Simple connector->get_hw_state implementation for encoders that support only
		4019	* one connector and no cloning and hence the encoder state determines the state
		4020	* of the connector. */
		4021	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	4022	{
3031	serge	4023	enum pipe pipe = 0;
		4024	struct intel_encoder *encoder = connector->encoder;
2330	Serge	4025
3031	serge	4026	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	4027	}
		4028
4104	Serge	4029	static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
		4030	struct intel_crtc_config *pipe_config)
		4031	{
		4032	struct drm_i915_private *dev_priv = dev->dev_private;
		4033	struct intel_crtc *pipe_B_crtc =
		4034	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
		4035
		4036	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		4037	pipe_name(pipe), pipe_config->fdi_lanes);
		4038	if (pipe_config->fdi_lanes > 4) {
		4039	DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
		4040	pipe_name(pipe), pipe_config->fdi_lanes);
		4041	return false;
		4042	}
		4043
		4044	if (IS_HASWELL(dev)) {
		4045	if (pipe_config->fdi_lanes > 2) {
		4046	DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
		4047	pipe_config->fdi_lanes);
		4048	return false;
		4049	} else {
		4050	return true;
		4051	}
		4052	}
		4053
		4054	if (INTEL_INFO(dev)->num_pipes == 2)
		4055	return true;
		4056
		4057	/* Ivybridge 3 pipe is really complicated */
		4058	switch (pipe) {
		4059	case PIPE_A:
		4060	return true;
		4061	case PIPE_B:
		4062	if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		4063	pipe_config->fdi_lanes > 2) {
		4064	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4065	pipe_name(pipe), pipe_config->fdi_lanes);
		4066	return false;
		4067	}
		4068	return true;
		4069	case PIPE_C:
		4070	if (!pipe_has_enabled_pch(pipe_B_crtc) \|\|
		4071	pipe_B_crtc->config.fdi_lanes <= 2) {
		4072	if (pipe_config->fdi_lanes > 2) {
		4073	DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
		4074	pipe_name(pipe), pipe_config->fdi_lanes);
		4075	return false;
		4076	}
		4077	} else {
		4078	DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
		4079	return false;
		4080	}
		4081	return true;
		4082	default:
		4083	BUG();
		4084	}
		4085	}
		4086
		4087	#define RETRY 1
		4088	static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3746	Serge	4089	struct intel_crtc_config *pipe_config)
2330	Serge	4090	{
4104	Serge	4091	struct drm_device *dev = intel_crtc->base.dev;
3746	Serge	4092	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104	Serge	4093	int lane, link_bw, fdi_dotclock;
		4094	bool setup_ok, needs_recompute = false;
2330	Serge	4095
4104	Serge	4096	retry:
		4097	/* FDI is a binary signal running at ~2.7GHz, encoding
		4098	* each output octet as 10 bits. The actual frequency
		4099	* is stored as a divider into a 100MHz clock, and the
		4100	* mode pixel clock is stored in units of 1KHz.
		4101	* Hence the bw of each lane in terms of the mode signal
		4102	* is:
		4103	*/
		4104	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4105
		4106	fdi_dotclock = adjusted_mode->clock;
		4107	fdi_dotclock /= pipe_config->pixel_multiplier;
		4108
		4109	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
		4110	pipe_config->pipe_bpp);
		4111
		4112	pipe_config->fdi_lanes = lane;
		4113
		4114	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
		4115	link_bw, &pipe_config->fdi_m_n);
		4116
		4117	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
		4118	intel_crtc->pipe, pipe_config);
		4119	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		4120	pipe_config->pipe_bpp -= 2*3;
		4121	DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
		4122	pipe_config->pipe_bpp);
		4123	needs_recompute = true;
		4124	pipe_config->bw_constrained = true;
		4125
		4126	goto retry;
		4127	}
		4128
		4129	if (needs_recompute)
		4130	return RETRY;
		4131
		4132	return setup_ok ? 0 : -EINVAL;
		4133	}
		4134
		4135	static void hsw_compute_ips_config(struct intel_crtc *crtc,
		4136	struct intel_crtc_config *pipe_config)
		4137	{
		4138	pipe_config->ips_enabled = i915_enable_ips &&
		4139	hsw_crtc_supports_ips(crtc) &&
		4140	pipe_config->pipe_bpp <= 24;
		4141	}
		4142
		4143	static int intel_crtc_compute_config(struct intel_crtc *crtc,
		4144	struct intel_crtc_config *pipe_config)
		4145	{
		4146	struct drm_device *dev = crtc->base.dev;
		4147	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
		4148
2330	Serge	4149	if (HAS_PCH_SPLIT(dev)) {
		4150	/* FDI link clock is fixed at 2.7G */
3746	Serge	4151	if (pipe_config->requested_mode.clock * 3
		4152	> IRONLAKE_FDI_FREQ * 4)
4104	Serge	4153	return -EINVAL;
2330	Serge	4154	}
		4155
4104	Serge	4156	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
		4157	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
3031	serge	4158	*/
		4159	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		4160	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104	Serge	4161	return -EINVAL;
3031	serge	4162
3746	Serge	4163	if ((IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
		4164	pipe_config->pipe_bpp = 103; / 12bpc is gen5+ */
		4165	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
		4166	/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		4167	* for lvds. */
		4168	pipe_config->pipe_bpp = 8*3;
		4169	}
		4170
4104	Serge	4171	if (HAS_IPS(dev))
		4172	hsw_compute_ips_config(crtc, pipe_config);
		4173
		4174	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
		4175	* clock survives for now. */
		4176	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		4177	pipe_config->shared_dpll = crtc->config.shared_dpll;
		4178
		4179	if (pipe_config->has_pch_encoder)
		4180	return ironlake_fdi_compute_config(crtc, pipe_config);
		4181
		4182	return 0;
2330	Serge	4183	}
		4184
3031	serge	4185	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		4186	{
		4187	return 400000; /* FIXME */
		4188	}
		4189
2327	Serge	4190	static int i945_get_display_clock_speed(struct drm_device *dev)
		4191	{
		4192	return 400000;
		4193	}
		4194
		4195	static int i915_get_display_clock_speed(struct drm_device *dev)
		4196	{
		4197	return 333000;
		4198	}
		4199
		4200	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		4201	{
		4202	return 200000;
		4203	}
		4204
4104	Serge	4205	static int pnv_get_display_clock_speed(struct drm_device *dev)
		4206	{
		4207	u16 gcfgc = 0;
		4208
		4209	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4210
		4211	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4212	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		4213	return 267000;
		4214	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		4215	return 333000;
		4216	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		4217	return 444000;
		4218	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		4219	return 200000;
		4220	default:
		4221	DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
		4222	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		4223	return 133000;
		4224	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		4225	return 167000;
		4226	}
		4227	}
		4228
2327	Serge	4229	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		4230	{
		4231	u16 gcfgc = 0;
		4232
		4233	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		4234
		4235	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		4236	return 133000;
		4237	else {
		4238	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		4239	case GC_DISPLAY_CLOCK_333_MHZ:
		4240	return 333000;
		4241	default:
		4242	case GC_DISPLAY_CLOCK_190_200_MHZ:
		4243	return 190000;
		4244	}
		4245	}
		4246	}
		4247
		4248	static int i865_get_display_clock_speed(struct drm_device *dev)
		4249	{
		4250	return 266000;
		4251	}
		4252
		4253	static int i855_get_display_clock_speed(struct drm_device *dev)
		4254	{
		4255	u16 hpllcc = 0;
		4256	/* Assume that the hardware is in the high speed state. This
		4257	* should be the default.
		4258	*/
		4259	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		4260	case GC_CLOCK_133_200:
		4261	case GC_CLOCK_100_200:
		4262	return 200000;
		4263	case GC_CLOCK_166_250:
		4264	return 250000;
		4265	case GC_CLOCK_100_133:
		4266	return 133000;
		4267	}
		4268
		4269	/* Shouldn't happen */
		4270	return 0;
		4271	}
		4272
		4273	static int i830_get_display_clock_speed(struct drm_device *dev)
		4274	{
		4275	return 133000;
		4276	}
		4277
		4278	static void
3746	Serge	4279	intel_reduce_m_n_ratio(uint32_t num, uint32_t den)
2327	Serge	4280	{
3746	Serge	4281	while (*num > DATA_LINK_M_N_MASK \|\|
		4282	*den > DATA_LINK_M_N_MASK) {
2327	Serge	4283	*num >>= 1;
		4284	*den >>= 1;
		4285	}
		4286	}
		4287
3746	Serge	4288	static void compute_m_n(unsigned int m, unsigned int n,
		4289	uint32_t ret_m, uint32_t ret_n)
		4290	{
		4291	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
		4292	ret_m = div_u64((uint64_t) m *ret_n, n);
		4293	intel_reduce_m_n_ratio(ret_m, ret_n);
		4294	}
		4295
3480	Serge	4296	void
		4297	intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		4298	int pixel_clock, int link_clock,
		4299	struct intel_link_m_n *m_n)
2327	Serge	4300	{
3480	Serge	4301	m_n->tu = 64;
3746	Serge	4302
		4303	compute_m_n(bits_per_pixel * pixel_clock,
		4304	link_clock * nlanes * 8,
		4305	&m_n->gmch_m, &m_n->gmch_n);
		4306
		4307	compute_m_n(pixel_clock, link_clock,
		4308	&m_n->link_m, &m_n->link_n);
2327	Serge	4309	}
		4310
		4311	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4312	{
2342	Serge	4313	if (i915_panel_use_ssc >= 0)
		4314	return i915_panel_use_ssc != 0;
4104	Serge	4315	return dev_priv->vbt.lvds_use_ssc
2327	Serge	4316	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4317	}
		4318
3031	serge	4319	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	4320	{
3031	serge	4321	struct drm_device *dev = crtc->dev;
		4322	struct drm_i915_private *dev_priv = dev->dev_private;
		4323	int refclk = 27000; /* for DP & HDMI */
2327	Serge	4324
3031	serge	4325	return 100000; /* only one validated so far */
2327	Serge	4326
3031	serge	4327	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		4328	refclk = 96000;
		4329	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4330	if (intel_panel_use_ssc(dev_priv))
		4331	refclk = 100000;
		4332	else
		4333	refclk = 96000;
		4334	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		4335	refclk = 100000;
		4336	}
2327	Serge	4337
3031	serge	4338	return refclk;
		4339	}
2327	Serge	4340
3031	serge	4341	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		4342	{
		4343	struct drm_device *dev = crtc->dev;
		4344	struct drm_i915_private *dev_priv = dev->dev_private;
		4345	int refclk;
2327	Serge	4346
3031	serge	4347	if (IS_VALLEYVIEW(dev)) {
		4348	refclk = vlv_get_refclk(crtc);
		4349	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4350	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4104	Serge	4351	refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
3031	serge	4352	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4353	refclk / 1000);
		4354	} else if (!IS_GEN2(dev)) {
		4355	refclk = 96000;
		4356	} else {
		4357	refclk = 48000;
		4358	}
2327	Serge	4359
3031	serge	4360	return refclk;
		4361	}
2327	Serge	4362
4104	Serge	4363	static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
3031	serge	4364	{
4104	Serge	4365	return (1 << dpll->n) << 16 \| dpll->m2;
		4366	}
3746	Serge	4367
4104	Serge	4368	static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
		4369	{
		4370	return dpll->n << 16 \| dpll->m1 << 8 \| dpll->m2;
3031	serge	4371	}
2327	Serge	4372
3746	Serge	4373	static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
3031	serge	4374	intel_clock_t *reduced_clock)
		4375	{
3746	Serge	4376	struct drm_device *dev = crtc->base.dev;
3031	serge	4377	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4378	int pipe = crtc->pipe;
3031	serge	4379	u32 fp, fp2 = 0;
2327	Serge	4380
3031	serge	4381	if (IS_PINEVIEW(dev)) {
4104	Serge	4382	fp = pnv_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4383	if (reduced_clock)
4104	Serge	4384	fp2 = pnv_dpll_compute_fp(reduced_clock);
3031	serge	4385	} else {
4104	Serge	4386	fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
3031	serge	4387	if (reduced_clock)
4104	Serge	4388	fp2 = i9xx_dpll_compute_fp(reduced_clock);
3031	serge	4389	}
2327	Serge	4390
3031	serge	4391	I915_WRITE(FP0(pipe), fp);
4104	Serge	4392	crtc->config.dpll_hw_state.fp0 = fp;
2327	Serge	4393
3746	Serge	4394	crtc->lowfreq_avail = false;
		4395	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4396	reduced_clock && i915_powersave) {
		4397	I915_WRITE(FP1(pipe), fp2);
4104	Serge	4398	crtc->config.dpll_hw_state.fp1 = fp2;
3746	Serge	4399	crtc->lowfreq_avail = true;
3031	serge	4400	} else {
		4401	I915_WRITE(FP1(pipe), fp);
4104	Serge	4402	crtc->config.dpll_hw_state.fp1 = fp;
3031	serge	4403	}
		4404	}
2327	Serge	4405
4104	Serge	4406	static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
		4407	{
		4408	u32 reg_val;
		4409
		4410	/*
		4411	* PLLB opamp always calibrates to max value of 0x3f, force enable it
		4412	* and set it to a reasonable value instead.
		4413	*/
		4414	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4415	reg_val &= 0xffffff00;
		4416	reg_val \|= 0x00000030;
		4417	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4418
		4419	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4420	reg_val &= 0x8cffffff;
		4421	reg_val = 0x8c000000;
		4422	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4423
		4424	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
		4425	reg_val &= 0xffffff00;
		4426	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
		4427
		4428	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
		4429	reg_val &= 0x00ffffff;
		4430	reg_val \|= 0xb0000000;
		4431	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
		4432	}
		4433
		4434	static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
		4435	struct intel_link_m_n *m_n)
		4436	{
		4437	struct drm_device *dev = crtc->base.dev;
		4438	struct drm_i915_private *dev_priv = dev->dev_private;
		4439	int pipe = crtc->pipe;
		4440
		4441	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4442	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
		4443	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
		4444	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
		4445	}
		4446
		4447	static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
		4448	struct intel_link_m_n *m_n)
		4449	{
		4450	struct drm_device *dev = crtc->base.dev;
		4451	struct drm_i915_private *dev_priv = dev->dev_private;
		4452	int pipe = crtc->pipe;
		4453	enum transcoder transcoder = crtc->config.cpu_transcoder;
		4454
		4455	if (INTEL_INFO(dev)->gen >= 5) {
		4456	I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4457	I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		4458	I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		4459	I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
		4460	} else {
		4461	I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) \| m_n->gmch_m);
		4462	I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		4463	I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		4464	I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
		4465	}
		4466	}
		4467
3746	Serge	4468	static void intel_dp_set_m_n(struct intel_crtc *crtc)
3031	serge	4469	{
3746	Serge	4470	if (crtc->config.has_pch_encoder)
		4471	intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4472	else
		4473	intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
		4474	}
		4475
		4476	static void vlv_update_pll(struct intel_crtc *crtc)
		4477	{
		4478	struct drm_device *dev = crtc->base.dev;
3031	serge	4479	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	4480	int pipe = crtc->pipe;
4104	Serge	4481	u32 dpll, mdiv;
3031	serge	4482	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4104	Serge	4483	u32 coreclk, reg_val, dpll_md;
2327	Serge	4484
3480	Serge	4485	mutex_lock(&dev_priv->dpio_lock);
		4486
3746	Serge	4487	bestn = crtc->config.dpll.n;
		4488	bestm1 = crtc->config.dpll.m1;
		4489	bestm2 = crtc->config.dpll.m2;
		4490	bestp1 = crtc->config.dpll.p1;
		4491	bestp2 = crtc->config.dpll.p2;
3031	serge	4492
4104	Serge	4493	/* See eDP HDMI DPIO driver vbios notes doc */
		4494
		4495	/* PLL B needs special handling */
		4496	if (pipe)
		4497	vlv_pllb_recal_opamp(dev_priv);
		4498
		4499	/* Set up Tx target for periodic Rcomp update */
		4500	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
		4501
		4502	/* Disable target IRef on PLL */
		4503	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
		4504	reg_val &= 0x00ffffff;
		4505	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
		4506
		4507	/* Disable fast lock */
		4508	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
		4509
		4510	/* Set idtafcrecal before PLL is enabled */
3031	serge	4511	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4512	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4513	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4514	mdiv \|= (1 << DPIO_K_SHIFT);
4104	Serge	4515
		4516	/*
		4517	* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
		4518	* but we don't support that).
		4519	* Note: don't use the DAC post divider as it seems unstable.
		4520	*/
		4521	mdiv \|= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
		4522	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4523
3031	serge	4524	mdiv \|= DPIO_ENABLE_CALIBRATION;
4104	Serge	4525	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
3031	serge	4526
4104	Serge	4527	/* Set HBR and RBR LPF coefficients */
		4528	if (crtc->config.port_clock == 162000 \|\|
		4529	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) \|\|
		4530	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
		4531	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4532	0x009f0003);
		4533	else
		4534	vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
		4535	0x00d0000f);
3031	serge	4536
4104	Serge	4537	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) \|\|
		4538	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		4539	/* Use SSC source */
		4540	if (!pipe)
		4541	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4542	0x0df40000);
		4543	else
		4544	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4545	0x0df70000);
		4546	} else { /* HDMI or VGA */
		4547	/* Use bend source */
		4548	if (!pipe)
		4549	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4550	0x0df70000);
		4551	else
		4552	vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
		4553	0x0df40000);
		4554	}
3031	serge	4555
4104	Serge	4556	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
		4557	coreclk = (coreclk & 0x0000ff00) \| 0x01c00000;
		4558	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) \|\|
		4559	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		4560	coreclk \|= 0x01000000;
		4561	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
3031	serge	4562
4104	Serge	4563	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
		4564
		4565	/* Enable DPIO clock input */
		4566	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4567	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		4568	if (pipe)
		4569	dpll \|= DPLL_INTEGRATED_CRI_CLK_VLV;
		4570
3031	serge	4571	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4572	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4573
4104	Serge	4574	dpll_md = (crtc->config.pixel_multiplier - 1)
		4575	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4576	crtc->config.dpll_hw_state.dpll_md = dpll_md;
3031	serge	4577
3746	Serge	4578	if (crtc->config.has_dp_encoder)
		4579	intel_dp_set_m_n(crtc);
3243	Serge	4580
3480	Serge	4581	mutex_unlock(&dev_priv->dpio_lock);
3031	serge	4582	}
		4583
3746	Serge	4584	static void i9xx_update_pll(struct intel_crtc *crtc,
		4585	intel_clock_t *reduced_clock,
3031	serge	4586	int num_connectors)
		4587	{
3746	Serge	4588	struct drm_device *dev = crtc->base.dev;
3031	serge	4589	struct drm_i915_private *dev_priv = dev->dev_private;
		4590	u32 dpll;
		4591	bool is_sdvo;
3746	Serge	4592	struct dpll *clock = &crtc->config.dpll;
3031	serge	4593
3746	Serge	4594	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4595
3746	Serge	4596	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) \|\|
		4597	intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
3031	serge	4598
		4599	dpll = DPLL_VGA_MODE_DIS;
		4600
3746	Serge	4601	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
3031	serge	4602	dpll \|= DPLLB_MODE_LVDS;
		4603	else
		4604	dpll \|= DPLLB_MODE_DAC_SERIAL;
3746	Serge	4605
4104	Serge	4606	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
3746	Serge	4607	dpll \|= (crtc->config.pixel_multiplier - 1)
		4608	<< SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4609	}
4104	Serge	4610
		4611	if (is_sdvo)
		4612	dpll \|= DPLL_SDVO_HIGH_SPEED;
		4613
3746	Serge	4614	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4104	Serge	4615	dpll \|= DPLL_SDVO_HIGH_SPEED;
2342	Serge	4616
3031	serge	4617	/* compute bitmask from p1 value */
		4618	if (IS_PINEVIEW(dev))
		4619	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4620	else {
		4621	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4622	if (IS_G4X(dev) && reduced_clock)
		4623	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4624	}
		4625	switch (clock->p2) {
		4626	case 5:
		4627	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4628	break;
		4629	case 7:
		4630	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4631	break;
		4632	case 10:
		4633	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4634	break;
		4635	case 14:
		4636	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4637	break;
		4638	}
		4639	if (INTEL_INFO(dev)->gen >= 4)
		4640	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4641
4104	Serge	4642	if (crtc->config.sdvo_tv_clock)
3031	serge	4643	dpll \|= PLL_REF_INPUT_TVCLKINBC;
3746	Serge	4644	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4645	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4646	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4647	else
		4648	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4649
3031	serge	4650	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4651	crtc->config.dpll_hw_state.dpll = dpll;
2327	Serge	4652
4104	Serge	4653	if (INTEL_INFO(dev)->gen >= 4) {
		4654	u32 dpll_md = (crtc->config.pixel_multiplier - 1)
		4655	<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4656	crtc->config.dpll_hw_state.dpll_md = dpll_md;
		4657	}
2327	Serge	4658
3746	Serge	4659	if (crtc->config.has_dp_encoder)
		4660	intel_dp_set_m_n(crtc);
3031	serge	4661	}
2327	Serge	4662
3746	Serge	4663	static void i8xx_update_pll(struct intel_crtc *crtc,
		4664	intel_clock_t *reduced_clock,
3031	serge	4665	int num_connectors)
		4666	{
3746	Serge	4667	struct drm_device *dev = crtc->base.dev;
3031	serge	4668	struct drm_i915_private *dev_priv = dev->dev_private;
		4669	u32 dpll;
3746	Serge	4670	struct dpll *clock = &crtc->config.dpll;
2327	Serge	4671
3746	Serge	4672	i9xx_update_pll_dividers(crtc, reduced_clock);
3243	Serge	4673
3031	serge	4674	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4675
3746	Serge	4676	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
3031	serge	4677	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4678	} else {
		4679	if (clock->p1 == 2)
		4680	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4681	else
		4682	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4683	if (clock->p2 == 4)
		4684	dpll \|= PLL_P2_DIVIDE_BY_4;
		4685	}
2327	Serge	4686
4104	Serge	4687	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		4688	dpll \|= DPLL_DVO_2X_MODE;
		4689
3746	Serge	4690	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
3031	serge	4691	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4692	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4693	else
		4694	dpll \|= PLL_REF_INPUT_DREFCLK;
		4695
		4696	dpll \|= DPLL_VCO_ENABLE;
4104	Serge	4697	crtc->config.dpll_hw_state.dpll = dpll;
3031	serge	4698	}
		4699
4104	Serge	4700	static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
3243	Serge	4701	{
		4702	struct drm_device *dev = intel_crtc->base.dev;
		4703	struct drm_i915_private *dev_priv = dev->dev_private;
		4704	enum pipe pipe = intel_crtc->pipe;
3746	Serge	4705	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4104	Serge	4706	struct drm_display_mode *adjusted_mode =
		4707	&intel_crtc->config.adjusted_mode;
		4708	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
		4709	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
3243	Serge	4710
4104	Serge	4711	/* We need to be careful not to changed the adjusted mode, for otherwise
		4712	* the hw state checker will get angry at the mismatch. */
		4713	crtc_vtotal = adjusted_mode->crtc_vtotal;
		4714	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
		4715
3243	Serge	4716	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4717	/* the chip adds 2 halflines automatically */
4104	Serge	4718	crtc_vtotal -= 1;
		4719	crtc_vblank_end -= 1;
3243	Serge	4720	vsyncshift = adjusted_mode->crtc_hsync_start
		4721	- adjusted_mode->crtc_htotal / 2;
		4722	} else {
		4723	vsyncshift = 0;
		4724	}
		4725
		4726	if (INTEL_INFO(dev)->gen > 3)
		4727	I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
		4728
		4729	I915_WRITE(HTOTAL(cpu_transcoder),
		4730	(adjusted_mode->crtc_hdisplay - 1) \|
		4731	((adjusted_mode->crtc_htotal - 1) << 16));
		4732	I915_WRITE(HBLANK(cpu_transcoder),
		4733	(adjusted_mode->crtc_hblank_start - 1) \|
		4734	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4735	I915_WRITE(HSYNC(cpu_transcoder),
		4736	(adjusted_mode->crtc_hsync_start - 1) \|
		4737	((adjusted_mode->crtc_hsync_end - 1) << 16));
		4738
		4739	I915_WRITE(VTOTAL(cpu_transcoder),
		4740	(adjusted_mode->crtc_vdisplay - 1) \|
4104	Serge	4741	((crtc_vtotal - 1) << 16));
3243	Serge	4742	I915_WRITE(VBLANK(cpu_transcoder),
		4743	(adjusted_mode->crtc_vblank_start - 1) \|
4104	Serge	4744	((crtc_vblank_end - 1) << 16));
3243	Serge	4745	I915_WRITE(VSYNC(cpu_transcoder),
		4746	(adjusted_mode->crtc_vsync_start - 1) \|
		4747	((adjusted_mode->crtc_vsync_end - 1) << 16));
		4748
		4749	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
		4750	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
		4751	* documented on the DDI_FUNC_CTL register description, EDP Input Select
		4752	* bits. */
		4753	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
		4754	(pipe == PIPE_B \|\| pipe == PIPE_C))
		4755	I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
		4756
		4757	/* pipesrc controls the size that is scaled from, which should
		4758	* always be the user's requested size.
		4759	*/
		4760	I915_WRITE(PIPESRC(pipe),
		4761	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		4762	}
		4763
4104	Serge	4764	static void intel_get_pipe_timings(struct intel_crtc *crtc,
		4765	struct intel_crtc_config *pipe_config)
		4766	{
		4767	struct drm_device *dev = crtc->base.dev;
		4768	struct drm_i915_private *dev_priv = dev->dev_private;
		4769	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		4770	uint32_t tmp;
		4771
		4772	tmp = I915_READ(HTOTAL(cpu_transcoder));
		4773	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
		4774	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
		4775	tmp = I915_READ(HBLANK(cpu_transcoder));
		4776	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
		4777	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
		4778	tmp = I915_READ(HSYNC(cpu_transcoder));
		4779	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
		4780	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
		4781
		4782	tmp = I915_READ(VTOTAL(cpu_transcoder));
		4783	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
		4784	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
		4785	tmp = I915_READ(VBLANK(cpu_transcoder));
		4786	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
		4787	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
		4788	tmp = I915_READ(VSYNC(cpu_transcoder));
		4789	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
		4790	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
		4791
		4792	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		4793	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		4794	pipe_config->adjusted_mode.crtc_vtotal += 1;
		4795	pipe_config->adjusted_mode.crtc_vblank_end += 1;
		4796	}
		4797
		4798	tmp = I915_READ(PIPESRC(crtc->pipe));
		4799	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
		4800	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
		4801	}
		4802
		4803	static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
		4804	struct intel_crtc_config *pipe_config)
		4805	{
		4806	struct drm_crtc *crtc = &intel_crtc->base;
		4807
		4808	crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
		4809	crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
		4810	crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
		4811	crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
		4812
		4813	crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
		4814	crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
		4815	crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
		4816	crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
		4817
		4818	crtc->mode.flags = pipe_config->adjusted_mode.flags;
		4819
		4820	crtc->mode.clock = pipe_config->adjusted_mode.clock;
		4821	crtc->mode.flags \|= pipe_config->adjusted_mode.flags;
		4822	}
		4823
3746	Serge	4824	static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
		4825	{
		4826	struct drm_device *dev = intel_crtc->base.dev;
		4827	struct drm_i915_private *dev_priv = dev->dev_private;
		4828	uint32_t pipeconf;
		4829
4104	Serge	4830	pipeconf = 0;
3746	Serge	4831
4104	Serge	4832	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		4833	I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
		4834	pipeconf \|= PIPECONF_ENABLE;
		4835
3746	Serge	4836	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4837	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4838	* core speed.
		4839	*
		4840	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4841	* pipe == 0 check?
		4842	*/
		4843	if (intel_crtc->config.requested_mode.clock >
		4844	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4845	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4846	}
		4847
4104	Serge	4848	/* only g4x and later have fancy bpc/dither controls */
		4849	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		4850	/* Bspec claims that we can't use dithering for 30bpp pipes. */
		4851	if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
		4852	pipeconf \|= PIPECONF_DITHER_EN \|
3746	Serge	4853	PIPECONF_DITHER_TYPE_SP;
		4854
4104	Serge	4855	switch (intel_crtc->config.pipe_bpp) {
		4856	case 18:
		4857	pipeconf \|= PIPECONF_6BPC;
		4858	break;
		4859	case 24:
		4860	pipeconf \|= PIPECONF_8BPC;
		4861	break;
		4862	case 30:
		4863	pipeconf \|= PIPECONF_10BPC;
		4864	break;
		4865	default:
		4866	/* Case prevented by intel_choose_pipe_bpp_dither. */
		4867	BUG();
3746	Serge	4868	}
		4869	}
		4870
		4871	if (HAS_PIPE_CXSR(dev)) {
		4872	if (intel_crtc->lowfreq_avail) {
		4873	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4874	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4875	} else {
		4876	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4877	}
		4878	}
		4879
		4880	if (!IS_GEN2(dev) &&
		4881	intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		4882	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4883	else
		4884	pipeconf \|= PIPECONF_PROGRESSIVE;
		4885
4104	Serge	4886	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
3746	Serge	4887	pipeconf \|= PIPECONF_COLOR_RANGE_SELECT;
		4888
		4889	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
		4890	POSTING_READ(PIPECONF(intel_crtc->pipe));
		4891	}
		4892
3031	serge	4893	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4894	int x, int y,
		4895	struct drm_framebuffer *fb)
		4896	{
		4897	struct drm_device *dev = crtc->dev;
		4898	struct drm_i915_private *dev_priv = dev->dev_private;
		4899	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	4900	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
3031	serge	4901	int pipe = intel_crtc->pipe;
		4902	int plane = intel_crtc->plane;
		4903	int refclk, num_connectors = 0;
		4904	intel_clock_t clock, reduced_clock;
3746	Serge	4905	u32 dspcntr;
4104	Serge	4906	bool ok, has_reduced_clock = false;
		4907	bool is_lvds = false;
3031	serge	4908	struct intel_encoder *encoder;
		4909	const intel_limit_t *limit;
		4910	int ret;
		4911
		4912	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4913	switch (encoder->type) {
		4914	case INTEL_OUTPUT_LVDS:
		4915	is_lvds = true;
		4916	break;
		4917	}
		4918
		4919	num_connectors++;
		4920	}
		4921
		4922	refclk = i9xx_get_refclk(crtc, num_connectors);
		4923
		4924	/*
		4925	* Returns a set of divisors for the desired target clock with the given
		4926	* refclk, or FALSE. The returned values represent the clock equation:
		4927	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4928	*/
		4929	limit = intel_limit(crtc, refclk);
4104	Serge	4930	ok = dev_priv->display.find_dpll(limit, crtc,
		4931	intel_crtc->config.port_clock,
		4932	refclk, NULL, &clock);
		4933	if (!ok && !intel_crtc->config.clock_set) {
3031	serge	4934	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4935	return -EINVAL;
		4936	}
		4937
		4938	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4939	/*
		4940	* Ensure we match the reduced clock's P to the target clock.
		4941	* If the clocks don't match, we can't switch the display clock
		4942	* by using the FP0/FP1. In such case we will disable the LVDS
		4943	* downclock feature.
		4944	*/
4104	Serge	4945	has_reduced_clock =
		4946	dev_priv->display.find_dpll(limit, crtc,
3031	serge	4947	dev_priv->lvds_downclock,
4104	Serge	4948	refclk, &clock,
3031	serge	4949	&reduced_clock);
		4950	}
3746	Serge	4951	/* Compat-code for transition, will disappear. */
		4952	if (!intel_crtc->config.clock_set) {
		4953	intel_crtc->config.dpll.n = clock.n;
		4954	intel_crtc->config.dpll.m1 = clock.m1;
		4955	intel_crtc->config.dpll.m2 = clock.m2;
		4956	intel_crtc->config.dpll.p1 = clock.p1;
		4957	intel_crtc->config.dpll.p2 = clock.p2;
		4958	}
3031	serge	4959
		4960	if (IS_GEN2(dev))
4104	Serge	4961	i8xx_update_pll(intel_crtc,
3243	Serge	4962	has_reduced_clock ? &reduced_clock : NULL,
		4963	num_connectors);
3031	serge	4964	else if (IS_VALLEYVIEW(dev))
3746	Serge	4965	vlv_update_pll(intel_crtc);
3031	serge	4966	else
3746	Serge	4967	i9xx_update_pll(intel_crtc,
3031	serge	4968	has_reduced_clock ? &reduced_clock : NULL,
		4969	num_connectors);
		4970
		4971	/* Set up the display plane register */
		4972	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4973
3746	Serge	4974	if (!IS_VALLEYVIEW(dev)) {
3031	serge	4975	if (pipe == 0)
		4976	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4977	else
		4978	dspcntr \|= DISPPLANE_SEL_PIPE_B;
3243	Serge	4979	}
		4980
4104	Serge	4981	intel_set_pipe_timings(intel_crtc);
3031	serge	4982
		4983	/* pipesrc and dspsize control the size that is scaled from,
		4984	* which should always be the user's requested size.
		4985	*/
		4986	I915_WRITE(DSPSIZE(plane),
		4987	((mode->vdisplay - 1) << 16) \|
		4988	(mode->hdisplay - 1));
		4989	I915_WRITE(DSPPOS(plane), 0);
2327	Serge	4990
3746	Serge	4991	i9xx_set_pipeconf(intel_crtc);
		4992
3031	serge	4993	I915_WRITE(DSPCNTR(plane), dspcntr);
		4994	POSTING_READ(DSPCNTR(plane));
2327	Serge	4995
3031	serge	4996	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4997
3031	serge	4998	intel_update_watermarks(dev);
		4999
2327	Serge	5000	return ret;
		5001	}
		5002
4104	Serge	5003	static void i9xx_get_pfit_config(struct intel_crtc *crtc,
		5004	struct intel_crtc_config *pipe_config)
		5005	{
		5006	struct drm_device *dev = crtc->base.dev;
		5007	struct drm_i915_private *dev_priv = dev->dev_private;
		5008	uint32_t tmp;
		5009
		5010	tmp = I915_READ(PFIT_CONTROL);
		5011	if (!(tmp & PFIT_ENABLE))
		5012	return;
		5013
		5014	/* Check whether the pfit is attached to our pipe. */
		5015	if (INTEL_INFO(dev)->gen < 4) {
		5016	if (crtc->pipe != PIPE_B)
		5017	return;
		5018	} else {
		5019	if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
		5020	return;
		5021	}
		5022
		5023	pipe_config->gmch_pfit.control = tmp;
		5024	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
		5025	if (INTEL_INFO(dev)->gen < 5)
		5026	pipe_config->gmch_pfit.lvds_border_bits =
		5027	I915_READ(LVDS) & LVDS_BORDER_ENABLE;
		5028	}
		5029
3746	Serge	5030	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
		5031	struct intel_crtc_config *pipe_config)
		5032	{
		5033	struct drm_device *dev = crtc->base.dev;
		5034	struct drm_i915_private *dev_priv = dev->dev_private;
		5035	uint32_t tmp;
		5036
4104	Serge	5037	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5038	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5039
3746	Serge	5040	tmp = I915_READ(PIPECONF(crtc->pipe));
		5041	if (!(tmp & PIPECONF_ENABLE))
		5042	return false;
		5043
4280	Serge	5044	if (IS_G4X(dev) \|\| IS_VALLEYVIEW(dev)) {
		5045	switch (tmp & PIPECONF_BPC_MASK) {
		5046	case PIPECONF_6BPC:
		5047	pipe_config->pipe_bpp = 18;
		5048	break;
		5049	case PIPECONF_8BPC:
		5050	pipe_config->pipe_bpp = 24;
		5051	break;
		5052	case PIPECONF_10BPC:
		5053	pipe_config->pipe_bpp = 30;
		5054	break;
		5055	default:
		5056	break;
		5057	}
		5058	}
		5059
4104	Serge	5060	intel_get_pipe_timings(crtc, pipe_config);
		5061
		5062	i9xx_get_pfit_config(crtc, pipe_config);
		5063
		5064	if (INTEL_INFO(dev)->gen >= 4) {
		5065	tmp = I915_READ(DPLL_MD(crtc->pipe));
		5066	pipe_config->pixel_multiplier =
		5067	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
		5068	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
		5069	pipe_config->dpll_hw_state.dpll_md = tmp;
		5070	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		5071	tmp = I915_READ(DPLL(crtc->pipe));
		5072	pipe_config->pixel_multiplier =
		5073	((tmp & SDVO_MULTIPLIER_MASK)
		5074	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
		5075	} else {
		5076	/* Note that on i915G/GM the pixel multiplier is in the sdvo
		5077	* port and will be fixed up in the encoder->get_config
		5078	* function. */
		5079	pipe_config->pixel_multiplier = 1;
		5080	}
		5081	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
		5082	if (!IS_VALLEYVIEW(dev)) {
		5083	pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		5084	pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
		5085	} else {
		5086	/* Mask out read-only status bits. */
		5087	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV \|
		5088	DPLL_PORTC_READY_MASK \|
		5089	DPLL_PORTB_READY_MASK);
		5090	}
		5091
3746	Serge	5092	return true;
		5093	}
		5094
3243	Serge	5095	static void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	5096	{
		5097	struct drm_i915_private *dev_priv = dev->dev_private;
		5098	struct drm_mode_config *mode_config = &dev->mode_config;
		5099	struct intel_encoder *encoder;
3746	Serge	5100	u32 val, final;
2327	Serge	5101	bool has_lvds = false;
2342	Serge	5102	bool has_cpu_edp = false;
		5103	bool has_panel = false;
		5104	bool has_ck505 = false;
		5105	bool can_ssc = false;
2327	Serge	5106
		5107	/* We need to take the global config into account */
		5108	list_for_each_entry(encoder, &mode_config->encoder_list,
		5109	base.head) {
		5110	switch (encoder->type) {
		5111	case INTEL_OUTPUT_LVDS:
2342	Serge	5112	has_panel = true;
2327	Serge	5113	has_lvds = true;
2342	Serge	5114	break;
2327	Serge	5115	case INTEL_OUTPUT_EDP:
2342	Serge	5116	has_panel = true;
4104	Serge	5117	if (enc_to_dig_port(&encoder->base)->port == PORT_A)
2342	Serge	5118	has_cpu_edp = true;
2327	Serge	5119	break;
		5120	}
		5121	}
2342	Serge	5122
		5123	if (HAS_PCH_IBX(dev)) {
4104	Serge	5124	has_ck505 = dev_priv->vbt.display_clock_mode;
2342	Serge	5125	can_ssc = has_ck505;
		5126	} else {
		5127	has_ck505 = false;
		5128	can_ssc = true;
2327	Serge	5129	}
		5130
4104	Serge	5131	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		5132	has_panel, has_lvds, has_ck505);
2342	Serge	5133
2327	Serge	5134	/* Ironlake: try to setup display ref clock before DPLL
		5135	* enabling. This is only under driver's control after
		5136	* PCH B stepping, previous chipset stepping should be
		5137	* ignoring this setting.
		5138	*/
3746	Serge	5139	val = I915_READ(PCH_DREF_CONTROL);
		5140
		5141	/* As we must carefully and slowly disable/enable each source in turn,
		5142	* compute the final state we want first and check if we need to
		5143	* make any changes at all.
		5144	*/
		5145	final = val;
		5146	final &= ~DREF_NONSPREAD_SOURCE_MASK;
		5147	if (has_ck505)
		5148	final \|= DREF_NONSPREAD_CK505_ENABLE;
		5149	else
		5150	final \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5151
		5152	final &= ~DREF_SSC_SOURCE_MASK;
		5153	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5154	final &= ~DREF_SSC1_ENABLE;
		5155
		5156	if (has_panel) {
		5157	final \|= DREF_SSC_SOURCE_ENABLE;
		5158
		5159	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5160	final \|= DREF_SSC1_ENABLE;
		5161
		5162	if (has_cpu_edp) {
		5163	if (intel_panel_use_ssc(dev_priv) && can_ssc)
		5164	final \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5165	else
		5166	final \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5167	} else
		5168	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5169	} else {
		5170	final \|= DREF_SSC_SOURCE_DISABLE;
		5171	final \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		5172	}
		5173
		5174	if (final == val)
		5175	return;
		5176
2327	Serge	5177	/* Always enable nonspread source */
3746	Serge	5178	val &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	5179
		5180	if (has_ck505)
3746	Serge	5181	val \|= DREF_NONSPREAD_CK505_ENABLE;
2342	Serge	5182	else
3746	Serge	5183	val \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	5184
		5185	if (has_panel) {
3746	Serge	5186	val &= ~DREF_SSC_SOURCE_MASK;
		5187	val \|= DREF_SSC_SOURCE_ENABLE;
2327	Serge	5188
2342	Serge	5189	/* SSC must be turned on before enabling the CPU output */
		5190	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5191	DRM_DEBUG_KMS("Using SSC on panel\n");
3746	Serge	5192	val \|= DREF_SSC1_ENABLE;
3031	serge	5193	} else
3746	Serge	5194	val &= ~DREF_SSC1_ENABLE;
2327	Serge	5195
2342	Serge	5196	/* Get SSC going before enabling the outputs */
3746	Serge	5197	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5198	POSTING_READ(PCH_DREF_CONTROL);
		5199	udelay(200);
2342	Serge	5200
3746	Serge	5201	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2327	Serge	5202
		5203	/* Enable CPU source on CPU attached eDP */
2342	Serge	5204	if (has_cpu_edp) {
		5205	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		5206	DRM_DEBUG_KMS("Using SSC on eDP\n");
3746	Serge	5207	val \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	5208	}
2327	Serge	5209	else
3746	Serge	5210	val \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	5211	} else
3746	Serge	5212	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5213
3746	Serge	5214	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5215	POSTING_READ(PCH_DREF_CONTROL);
		5216	udelay(200);
2327	Serge	5217	} else {
2342	Serge	5218	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		5219
3746	Serge	5220	val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2342	Serge	5221
		5222	/* Turn off CPU output */
3746	Serge	5223	val \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2342	Serge	5224
3746	Serge	5225	I915_WRITE(PCH_DREF_CONTROL, val);
2327	Serge	5226	POSTING_READ(PCH_DREF_CONTROL);
		5227	udelay(200);
2342	Serge	5228
		5229	/* Turn off the SSC source */
3746	Serge	5230	val &= ~DREF_SSC_SOURCE_MASK;
		5231	val \|= DREF_SSC_SOURCE_DISABLE;
2342	Serge	5232
		5233	/* Turn off SSC1 */
3746	Serge	5234	val &= ~DREF_SSC1_ENABLE;
2342	Serge	5235
3746	Serge	5236	I915_WRITE(PCH_DREF_CONTROL, val);
2342	Serge	5237	POSTING_READ(PCH_DREF_CONTROL);
		5238	udelay(200);
2327	Serge	5239	}
3746	Serge	5240
		5241	BUG_ON(val != final);
2327	Serge	5242	}
		5243
4104	Serge	5244	static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
3243	Serge	5245	{
4104	Serge	5246	uint32_t tmp;
3243	Serge	5247
		5248	tmp = I915_READ(SOUTH_CHICKEN2);
		5249	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
		5250	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5251
		5252	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
		5253	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		5254	DRM_ERROR("FDI mPHY reset assert timeout\n");
		5255
		5256	tmp = I915_READ(SOUTH_CHICKEN2);
		5257	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		5258	I915_WRITE(SOUTH_CHICKEN2, tmp);
		5259
		5260	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4104	Serge	5261	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
3243	Serge	5262	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
		5263	}
		5264
4104	Serge	5265	/* WaMPhyProgramming:hsw */
		5266	static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
		5267	{
		5268	uint32_t tmp;
		5269
3243	Serge	5270	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
		5271	tmp &= ~(0xFF << 24);
		5272	tmp \|= (0x12 << 24);
		5273	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
		5274
		5275	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
		5276	tmp \|= (1 << 11);
		5277	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
		5278
		5279	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
		5280	tmp \|= (1 << 11);
		5281	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
		5282
		5283	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
		5284	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5285	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
		5286
		5287	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
		5288	tmp \|= (1 << 24) \| (1 << 21) \| (1 << 18);
		5289	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
		5290
		5291	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		5292	tmp &= ~(7 << 13);
		5293	tmp \|= (5 << 13);
		5294	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
		5295
		5296	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		5297	tmp &= ~(7 << 13);
		5298	tmp \|= (5 << 13);
		5299	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
		5300
		5301	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
		5302	tmp &= ~0xFF;
		5303	tmp \|= 0x1C;
		5304	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
		5305
		5306	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
		5307	tmp &= ~0xFF;
		5308	tmp \|= 0x1C;
		5309	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
		5310
		5311	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
		5312	tmp &= ~(0xFF << 16);
		5313	tmp \|= (0x1C << 16);
		5314	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
		5315
		5316	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
		5317	tmp &= ~(0xFF << 16);
		5318	tmp \|= (0x1C << 16);
		5319	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
		5320
		5321	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		5322	tmp \|= (1 << 27);
		5323	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
		5324
		5325	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		5326	tmp \|= (1 << 27);
		5327	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
		5328
		5329	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		5330	tmp &= ~(0xF << 28);
		5331	tmp \|= (4 << 28);
		5332	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
		5333
		5334	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		5335	tmp &= ~(0xF << 28);
		5336	tmp \|= (4 << 28);
		5337	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
		5338	}
		5339
4104	Serge	5340	/* Implements 3 different sequences from BSpec chapter "Display iCLK
		5341	* Programming" based on the parameters passed:
		5342	* - Sequence to enable CLKOUT_DP
		5343	* - Sequence to enable CLKOUT_DP without spread
		5344	* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
		5345	*/
		5346	static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
		5347	bool with_fdi)
		5348	{
		5349	struct drm_i915_private *dev_priv = dev->dev_private;
		5350	uint32_t reg, tmp;
3480	Serge	5351
4104	Serge	5352	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		5353	with_spread = true;
		5354	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		5355	with_fdi, "LP PCH doesn't have FDI\n"))
		5356	with_fdi = false;
		5357
		5358	mutex_lock(&dev_priv->dpio_lock);
		5359
		5360	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5361	tmp &= ~SBI_SSCCTL_DISABLE;
		5362	tmp \|= SBI_SSCCTL_PATHALT;
		5363	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5364
		5365	udelay(24);
		5366
		5367	if (with_spread) {
		5368	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5369	tmp &= ~SBI_SSCCTL_PATHALT;
		5370	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5371
		5372	if (with_fdi) {
		5373	lpt_reset_fdi_mphy(dev_priv);
		5374	lpt_program_fdi_mphy(dev_priv);
		5375	}
		5376	}
		5377
		5378	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5379	SBI_GEN0 : SBI_DBUFF0;
		5380	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5381	tmp \|= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5382	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5383
3480	Serge	5384	mutex_unlock(&dev_priv->dpio_lock);
3243	Serge	5385	}
		5386
4104	Serge	5387	/* Sequence to disable CLKOUT_DP */
		5388	static void lpt_disable_clkout_dp(struct drm_device *dev)
		5389	{
		5390	struct drm_i915_private *dev_priv = dev->dev_private;
		5391	uint32_t reg, tmp;
		5392
		5393	mutex_lock(&dev_priv->dpio_lock);
		5394
		5395	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
		5396	SBI_GEN0 : SBI_DBUFF0;
		5397	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
		5398	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
		5399	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
		5400
		5401	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		5402	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		5403	if (!(tmp & SBI_SSCCTL_PATHALT)) {
		5404	tmp \|= SBI_SSCCTL_PATHALT;
		5405	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5406	udelay(32);
		5407	}
		5408	tmp \|= SBI_SSCCTL_DISABLE;
		5409	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
		5410	}
		5411
		5412	mutex_unlock(&dev_priv->dpio_lock);
		5413	}
		5414
		5415	static void lpt_init_pch_refclk(struct drm_device *dev)
		5416	{
		5417	struct drm_mode_config *mode_config = &dev->mode_config;
		5418	struct intel_encoder *encoder;
		5419	bool has_vga = false;
		5420
		5421	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5422	switch (encoder->type) {
		5423	case INTEL_OUTPUT_ANALOG:
		5424	has_vga = true;
		5425	break;
		5426	}
		5427	}
		5428
		5429	if (has_vga)
		5430	lpt_enable_clkout_dp(dev, true, true);
		5431	else
		5432	lpt_disable_clkout_dp(dev);
		5433	}
		5434
3243	Serge	5435	/*
		5436	* Initialize reference clocks when the driver loads
		5437	*/
		5438	void intel_init_pch_refclk(struct drm_device *dev)
		5439	{
		5440	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		5441	ironlake_init_pch_refclk(dev);
		5442	else if (HAS_PCH_LPT(dev))
		5443	lpt_init_pch_refclk(dev);
		5444	}
		5445
2342	Serge	5446	static int ironlake_get_refclk(struct drm_crtc *crtc)
		5447	{
		5448	struct drm_device *dev = crtc->dev;
		5449	struct drm_i915_private *dev_priv = dev->dev_private;
		5450	struct intel_encoder *encoder;
		5451	int num_connectors = 0;
		5452	bool is_lvds = false;
		5453
3031	serge	5454	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	5455	switch (encoder->type) {
		5456	case INTEL_OUTPUT_LVDS:
		5457	is_lvds = true;
		5458	break;
		5459	}
		5460	num_connectors++;
		5461	}
		5462
		5463	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5464	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4104	Serge	5465	dev_priv->vbt.lvds_ssc_freq);
		5466	return dev_priv->vbt.lvds_ssc_freq * 1000;
2342	Serge	5467	}
		5468
		5469	return 120000;
		5470	}
		5471
4104	Serge	5472	static void ironlake_set_pipeconf(struct drm_crtc *crtc)
3031	serge	5473	{
		5474	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5475	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5476	int pipe = intel_crtc->pipe;
		5477	uint32_t val;
		5478
4104	Serge	5479	val = 0;
3031	serge	5480
3746	Serge	5481	switch (intel_crtc->config.pipe_bpp) {
3031	serge	5482	case 18:
3480	Serge	5483	val \|= PIPECONF_6BPC;
3031	serge	5484	break;
		5485	case 24:
3480	Serge	5486	val \|= PIPECONF_8BPC;
3031	serge	5487	break;
		5488	case 30:
3480	Serge	5489	val \|= PIPECONF_10BPC;
3031	serge	5490	break;
		5491	case 36:
3480	Serge	5492	val \|= PIPECONF_12BPC;
3031	serge	5493	break;
		5494	default:
3243	Serge	5495	/* Case prevented by intel_choose_pipe_bpp_dither. */
		5496	BUG();
3031	serge	5497	}
		5498
4104	Serge	5499	if (intel_crtc->config.dither)
3031	serge	5500	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5501
4104	Serge	5502	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3031	serge	5503	val \|= PIPECONF_INTERLACED_ILK;
		5504	else
		5505	val \|= PIPECONF_PROGRESSIVE;
		5506
3746	Serge	5507	if (intel_crtc->config.limited_color_range)
3480	Serge	5508	val \|= PIPECONF_COLOR_RANGE_SELECT;
		5509
3031	serge	5510	I915_WRITE(PIPECONF(pipe), val);
		5511	POSTING_READ(PIPECONF(pipe));
		5512	}
		5513
3480	Serge	5514	/*
		5515	* Set up the pipe CSC unit.
		5516	*
		5517	* Currently only full range RGB to limited range RGB conversion
		5518	* is supported, but eventually this should handle various
		5519	* RGB<->YCbCr scenarios as well.
		5520	*/
3746	Serge	5521	static void intel_set_pipe_csc(struct drm_crtc *crtc)
3480	Serge	5522	{
		5523	struct drm_device *dev = crtc->dev;
		5524	struct drm_i915_private *dev_priv = dev->dev_private;
		5525	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5526	int pipe = intel_crtc->pipe;
		5527	uint16_t coeff = 0x7800; /* 1.0 */
		5528
		5529	/*
		5530	* TODO: Check what kind of values actually come out of the pipe
		5531	* with these coeff/postoff values and adjust to get the best
		5532	* accuracy. Perhaps we even need to take the bpc value into
		5533	* consideration.
		5534	*/
		5535
3746	Serge	5536	if (intel_crtc->config.limited_color_range)
3480	Serge	5537	coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
		5538
		5539	/*
		5540	* GY/GU and RY/RU should be the other way around according
		5541	* to BSpec, but reality doesn't agree. Just set them up in
		5542	* a way that results in the correct picture.
		5543	*/
		5544	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
		5545	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
		5546
		5547	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
		5548	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
		5549
		5550	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
		5551	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
		5552
		5553	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
		5554	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
		5555	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
		5556
		5557	if (INTEL_INFO(dev)->gen > 6) {
		5558	uint16_t postoff = 0;
		5559
3746	Serge	5560	if (intel_crtc->config.limited_color_range)
3480	Serge	5561	postoff = (16 * (1 << 13) / 255) & 0x1fff;
		5562
		5563	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		5564	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		5565	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
		5566
		5567	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
		5568	} else {
		5569	uint32_t mode = CSC_MODE_YUV_TO_RGB;
		5570
3746	Serge	5571	if (intel_crtc->config.limited_color_range)
3480	Serge	5572	mode \|= CSC_BLACK_SCREEN_OFFSET;
		5573
		5574	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
		5575	}
		5576	}
		5577
4104	Serge	5578	static void haswell_set_pipeconf(struct drm_crtc *crtc)
3243	Serge	5579	{
		5580	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		5581	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	5582	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243	Serge	5583	uint32_t val;
		5584
4104	Serge	5585	val = 0;
3243	Serge	5586
4104	Serge	5587	if (intel_crtc->config.dither)
3243	Serge	5588	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		5589
4104	Serge	5590	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3243	Serge	5591	val \|= PIPECONF_INTERLACED_ILK;
		5592	else
		5593	val \|= PIPECONF_PROGRESSIVE;
		5594
		5595	I915_WRITE(PIPECONF(cpu_transcoder), val);
		5596	POSTING_READ(PIPECONF(cpu_transcoder));
4104	Serge	5597
		5598	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
		5599	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
3243	Serge	5600	}
		5601
3031	serge	5602	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		5603	intel_clock_t *clock,
		5604	bool *has_reduced_clock,
		5605	intel_clock_t *reduced_clock)
		5606	{
		5607	struct drm_device *dev = crtc->dev;
		5608	struct drm_i915_private *dev_priv = dev->dev_private;
		5609	struct intel_encoder *intel_encoder;
		5610	int refclk;
		5611	const intel_limit_t *limit;
4104	Serge	5612	bool ret, is_lvds = false;
3031	serge	5613
		5614	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5615	switch (intel_encoder->type) {
		5616	case INTEL_OUTPUT_LVDS:
		5617	is_lvds = true;
		5618	break;
		5619	}
		5620	}
		5621
		5622	refclk = ironlake_get_refclk(crtc);
		5623
		5624	/*
		5625	* Returns a set of divisors for the desired target clock with the given
		5626	* refclk, or FALSE. The returned values represent the clock equation:
		5627	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5628	*/
		5629	limit = intel_limit(crtc, refclk);
4104	Serge	5630	ret = dev_priv->display.find_dpll(limit, crtc,
		5631	to_intel_crtc(crtc)->config.port_clock,
		5632	refclk, NULL, clock);
3031	serge	5633	if (!ret)
		5634	return false;
		5635
		5636	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5637	/*
		5638	* Ensure we match the reduced clock's P to the target clock.
		5639	* If the clocks don't match, we can't switch the display clock
		5640	* by using the FP0/FP1. In such case we will disable the LVDS
		5641	* downclock feature.
		5642	*/
4104	Serge	5643	*has_reduced_clock =
		5644	dev_priv->display.find_dpll(limit, crtc,
3031	serge	5645	dev_priv->lvds_downclock,
4104	Serge	5646	refclk, clock,
3031	serge	5647	reduced_clock);
		5648	}
		5649
		5650	return true;
		5651	}
		5652
3243	Serge	5653	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
		5654	{
		5655	/*
		5656	* Account for spread spectrum to avoid
		5657	* oversubscribing the link. Max center spread
		5658	* is 2.5%; use 5% for safety's sake.
		5659	*/
		5660	u32 bps = target_clock * bpp * 21 / 20;
		5661	return bps / (link_bw * 8) + 1;
		5662	}
		5663
4104	Serge	5664	static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
2327	Serge	5665	{
4104	Serge	5666	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
3746	Serge	5667	}
		5668
3243	Serge	5669	static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4104	Serge	5670	u32 *fp,
3746	Serge	5671	intel_clock_t reduced_clock, u32 fp2)
3243	Serge	5672	{
		5673	struct drm_crtc *crtc = &intel_crtc->base;
		5674	struct drm_device *dev = crtc->dev;
		5675	struct drm_i915_private *dev_priv = dev->dev_private;
		5676	struct intel_encoder *intel_encoder;
		5677	uint32_t dpll;
3746	Serge	5678	int factor, num_connectors = 0;
4104	Serge	5679	bool is_lvds = false, is_sdvo = false;
3243	Serge	5680
		5681	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		5682	switch (intel_encoder->type) {
		5683	case INTEL_OUTPUT_LVDS:
		5684	is_lvds = true;
		5685	break;
		5686	case INTEL_OUTPUT_SDVO:
		5687	case INTEL_OUTPUT_HDMI:
		5688	is_sdvo = true;
		5689	break;
		5690	}
		5691
		5692	num_connectors++;
		5693	}
		5694
2327	Serge	5695	/* Enable autotuning of the PLL clock (if permissible) */
		5696	factor = 21;
		5697	if (is_lvds) {
		5698	if ((intel_panel_use_ssc(dev_priv) &&
4104	Serge	5699	dev_priv->vbt.lvds_ssc_freq == 100) \|\|
3746	Serge	5700	(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
2327	Serge	5701	factor = 25;
4104	Serge	5702	} else if (intel_crtc->config.sdvo_tv_clock)
2327	Serge	5703	factor = 20;
		5704
4104	Serge	5705	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
3746	Serge	5706	*fp \|= FP_CB_TUNE;
2327	Serge	5707
3746	Serge	5708	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		5709	*fp2 \|= FP_CB_TUNE;
		5710
2327	Serge	5711	dpll = 0;
		5712
		5713	if (is_lvds)
		5714	dpll \|= DPLLB_MODE_LVDS;
		5715	else
		5716	dpll \|= DPLLB_MODE_DAC_SERIAL;
4104	Serge	5717
3746	Serge	5718	dpll \|= (intel_crtc->config.pixel_multiplier - 1)
		5719	<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2327	Serge	5720
4104	Serge	5721	if (is_sdvo)
		5722	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5723	if (intel_crtc->config.has_dp_encoder)
		5724	dpll \|= DPLL_SDVO_HIGH_SPEED;
		5725
2327	Serge	5726	/* compute bitmask from p1 value */
4104	Serge	5727	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2327	Serge	5728	/* also FPA1 */
4104	Serge	5729	dpll \|= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2327	Serge	5730
4104	Serge	5731	switch (intel_crtc->config.dpll.p2) {
2327	Serge	5732	case 5:
		5733	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5734	break;
		5735	case 7:
		5736	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5737	break;
		5738	case 10:
		5739	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5740	break;
		5741	case 14:
		5742	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5743	break;
		5744	}
		5745
4104	Serge	5746	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
2327	Serge	5747	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5748	else
		5749	dpll \|= PLL_REF_INPUT_DREFCLK;
		5750
4104	Serge	5751	return dpll \| DPLL_VCO_ENABLE;
3243	Serge	5752	}
		5753
		5754	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5755	int x, int y,
		5756	struct drm_framebuffer *fb)
		5757	{
		5758	struct drm_device *dev = crtc->dev;
		5759	struct drm_i915_private *dev_priv = dev->dev_private;
		5760	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5761	int pipe = intel_crtc->pipe;
		5762	int plane = intel_crtc->plane;
		5763	int num_connectors = 0;
		5764	intel_clock_t clock, reduced_clock;
4104	Serge	5765	u32 dpll = 0, fp = 0, fp2 = 0;
3243	Serge	5766	bool ok, has_reduced_clock = false;
3746	Serge	5767	bool is_lvds = false;
3243	Serge	5768	struct intel_encoder *encoder;
4104	Serge	5769	struct intel_shared_dpll *pll;
3243	Serge	5770	int ret;
		5771
		5772	for_each_encoder_on_crtc(dev, crtc, encoder) {
		5773	switch (encoder->type) {
		5774	case INTEL_OUTPUT_LVDS:
		5775	is_lvds = true;
		5776	break;
		5777	}
		5778
		5779	num_connectors++;
		5780	}
		5781
		5782	WARN(!(HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev)),
		5783	"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
		5784
4104	Serge	5785	ok = ironlake_compute_clocks(crtc, &clock,
3243	Serge	5786	&has_reduced_clock, &reduced_clock);
4104	Serge	5787	if (!ok && !intel_crtc->config.clock_set) {
3243	Serge	5788	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5789	return -EINVAL;
		5790	}
3746	Serge	5791	/* Compat-code for transition, will disappear. */
		5792	if (!intel_crtc->config.clock_set) {
		5793	intel_crtc->config.dpll.n = clock.n;
		5794	intel_crtc->config.dpll.m1 = clock.m1;
		5795	intel_crtc->config.dpll.m2 = clock.m2;
		5796	intel_crtc->config.dpll.p1 = clock.p1;
		5797	intel_crtc->config.dpll.p2 = clock.p2;
		5798	}
3243	Serge	5799
4104	Serge	5800	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
		5801	if (intel_crtc->config.has_pch_encoder) {
		5802	fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
3243	Serge	5803	if (has_reduced_clock)
4104	Serge	5804	fp2 = i9xx_dpll_compute_fp(&reduced_clock);
3243	Serge	5805
4104	Serge	5806	dpll = ironlake_compute_dpll(intel_crtc,
		5807	&fp, &reduced_clock,
3746	Serge	5808	has_reduced_clock ? &fp2 : NULL);
3243	Serge	5809
4104	Serge	5810	intel_crtc->config.dpll_hw_state.dpll = dpll;
		5811	intel_crtc->config.dpll_hw_state.fp0 = fp;
		5812	if (has_reduced_clock)
		5813	intel_crtc->config.dpll_hw_state.fp1 = fp2;
		5814	else
		5815	intel_crtc->config.dpll_hw_state.fp1 = fp;
2327	Serge	5816
4104	Serge	5817	pll = intel_get_shared_dpll(intel_crtc);
3031	serge	5818	if (pll == NULL) {
4104	Serge	5819	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		5820	pipe_name(pipe));
2342	Serge	5821	return -EINVAL;
2327	Serge	5822	}
3031	serge	5823	} else
4104	Serge	5824	intel_put_shared_dpll(intel_crtc);
2327	Serge	5825
3746	Serge	5826	if (intel_crtc->config.has_dp_encoder)
		5827	intel_dp_set_m_n(intel_crtc);
2342	Serge	5828
4104	Serge	5829	if (is_lvds && has_reduced_clock && i915_powersave)
		5830	intel_crtc->lowfreq_avail = true;
		5831	else
		5832	intel_crtc->lowfreq_avail = false;
2327	Serge	5833
4104	Serge	5834	if (intel_crtc->config.has_pch_encoder) {
		5835	pll = intel_crtc_to_shared_dpll(intel_crtc);
2327	Serge	5836
4104	Serge	5837	}
2327	Serge	5838
4104	Serge	5839	intel_set_pipe_timings(intel_crtc);
2327	Serge	5840
4104	Serge	5841	if (intel_crtc->config.has_pch_encoder) {
		5842	intel_cpu_transcoder_set_m_n(intel_crtc,
		5843	&intel_crtc->config.fdi_m_n);
2342	Serge	5844	}
2327	Serge	5845
4104	Serge	5846	ironlake_set_pipeconf(crtc);
3243	Serge	5847
		5848	/* Set up the display plane register */
		5849	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
		5850	POSTING_READ(DSPCNTR(plane));
		5851
		5852	ret = intel_pipe_set_base(crtc, x, y, fb);
		5853
		5854	intel_update_watermarks(dev);
		5855
4104	Serge	5856	return ret;
		5857	}
3243	Serge	5858
4104	Serge	5859	static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
		5860	struct intel_crtc_config *pipe_config)
		5861	{
		5862	struct drm_device *dev = crtc->base.dev;
		5863	struct drm_i915_private *dev_priv = dev->dev_private;
		5864	enum transcoder transcoder = pipe_config->cpu_transcoder;
		5865
		5866	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
		5867	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
		5868	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
		5869	& ~TU_SIZE_MASK;
		5870	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
		5871	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
		5872	& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3243	Serge	5873	}
		5874
4104	Serge	5875	static void ironlake_get_pfit_config(struct intel_crtc *crtc,
		5876	struct intel_crtc_config *pipe_config)
		5877	{
		5878	struct drm_device *dev = crtc->base.dev;
		5879	struct drm_i915_private *dev_priv = dev->dev_private;
		5880	uint32_t tmp;
		5881
		5882	tmp = I915_READ(PF_CTL(crtc->pipe));
		5883
		5884	if (tmp & PF_ENABLE) {
		5885	pipe_config->pch_pfit.enabled = true;
		5886	pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		5887	pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
		5888
		5889	/* We currently do not free assignements of panel fitters on
		5890	* ivb/hsw (since we don't use the higher upscaling modes which
		5891	* differentiates them) so just WARN about this case for now. */
		5892	if (IS_GEN7(dev)) {
		5893	WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
		5894	PF_PIPE_SEL_IVB(crtc->pipe));
		5895	}
		5896	}
		5897	}
		5898
3746	Serge	5899	static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
		5900	struct intel_crtc_config *pipe_config)
		5901	{
		5902	struct drm_device *dev = crtc->base.dev;
		5903	struct drm_i915_private *dev_priv = dev->dev_private;
		5904	uint32_t tmp;
		5905
4104	Serge	5906	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		5907	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		5908
3746	Serge	5909	tmp = I915_READ(PIPECONF(crtc->pipe));
		5910	if (!(tmp & PIPECONF_ENABLE))
		5911	return false;
		5912
4280	Serge	5913	switch (tmp & PIPECONF_BPC_MASK) {
		5914	case PIPECONF_6BPC:
		5915	pipe_config->pipe_bpp = 18;
		5916	break;
		5917	case PIPECONF_8BPC:
		5918	pipe_config->pipe_bpp = 24;
		5919	break;
		5920	case PIPECONF_10BPC:
		5921	pipe_config->pipe_bpp = 30;
		5922	break;
		5923	case PIPECONF_12BPC:
		5924	pipe_config->pipe_bpp = 36;
		5925	break;
		5926	default:
		5927	break;
		5928	}
		5929
4104	Serge	5930	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
		5931	struct intel_shared_dpll *pll;
		5932
3746	Serge	5933	pipe_config->has_pch_encoder = true;
		5934
4104	Serge	5935	tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		5936	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		5937	FDI_DP_PORT_WIDTH_SHIFT) + 1;
		5938
		5939	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		5940
		5941	if (HAS_PCH_IBX(dev_priv->dev)) {
		5942	pipe_config->shared_dpll =
		5943	(enum intel_dpll_id) crtc->pipe;
		5944	} else {
		5945	tmp = I915_READ(PCH_DPLL_SEL);
		5946	if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
		5947	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
		5948	else
		5949	pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		5950	}
		5951
		5952	pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
		5953
		5954	WARN_ON(!pll->get_hw_state(dev_priv, pll,
		5955	&pipe_config->dpll_hw_state));
		5956
		5957	tmp = pipe_config->dpll_hw_state.dpll;
		5958	pipe_config->pixel_multiplier =
		5959	((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
		5960	>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
		5961	} else {
		5962	pipe_config->pixel_multiplier = 1;
		5963	}
		5964
		5965	intel_get_pipe_timings(crtc, pipe_config);
		5966
		5967	ironlake_get_pfit_config(crtc, pipe_config);
		5968
3746	Serge	5969	return true;
		5970	}
		5971
4104	Serge	5972	static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
		5973	{
		5974	struct drm_device *dev = dev_priv->dev;
		5975	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
		5976	struct intel_crtc *crtc;
		5977	unsigned long irqflags;
		5978	uint32_t val;
		5979
		5980	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		5981	WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
		5982	pipe_name(crtc->pipe));
		5983
		5984	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
		5985	WARN(plls->spll_refcount, "SPLL enabled\n");
		5986	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
		5987	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
		5988	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
		5989	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
		5990	"CPU PWM1 enabled\n");
		5991	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
		5992	"CPU PWM2 enabled\n");
		5993	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
		5994	"PCH PWM1 enabled\n");
		5995	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
		5996	"Utility pin enabled\n");
		5997	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
		5998
		5999	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		6000	val = I915_READ(DEIMR);
		6001	WARN((val & ~DE_PCH_EVENT_IVB) != val,
		6002	"Unexpected DEIMR bits enabled: 0x%x\n", val);
		6003	val = I915_READ(SDEIMR);
		6004	WARN((val \| SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
		6005	"Unexpected SDEIMR bits enabled: 0x%x\n", val);
		6006	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
		6007	}
		6008
		6009	/*
		6010	* This function implements pieces of two sequences from BSpec:
		6011	* - Sequence for display software to disable LCPLL
		6012	* - Sequence for display software to allow package C8+
		6013	* The steps implemented here are just the steps that actually touch the LCPLL
		6014	* register. Callers should take care of disabling all the display engine
		6015	* functions, doing the mode unset, fixing interrupts, etc.
		6016	*/
		6017	void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
		6018	bool switch_to_fclk, bool allow_power_down)
		6019	{
		6020	uint32_t val;
		6021
		6022	assert_can_disable_lcpll(dev_priv);
		6023
		6024	val = I915_READ(LCPLL_CTL);
		6025
		6026	if (switch_to_fclk) {
		6027	val \|= LCPLL_CD_SOURCE_FCLK;
		6028	I915_WRITE(LCPLL_CTL, val);
		6029
		6030	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
		6031	LCPLL_CD_SOURCE_FCLK_DONE, 1))
		6032	DRM_ERROR("Switching to FCLK failed\n");
		6033
		6034	val = I915_READ(LCPLL_CTL);
		6035	}
		6036
		6037	val \|= LCPLL_PLL_DISABLE;
		6038	I915_WRITE(LCPLL_CTL, val);
		6039	POSTING_READ(LCPLL_CTL);
		6040
		6041	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		6042	DRM_ERROR("LCPLL still locked\n");
		6043
		6044	val = I915_READ(D_COMP);
		6045	val \|= D_COMP_COMP_DISABLE;
		6046	I915_WRITE(D_COMP, val);
		6047	POSTING_READ(D_COMP);
		6048	udelay(100);
		6049
		6050	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
		6051	DRM_ERROR("D_COMP RCOMP still in progress\n");
		6052
		6053	if (allow_power_down) {
		6054	val = I915_READ(LCPLL_CTL);
		6055	val \|= LCPLL_POWER_DOWN_ALLOW;
		6056	I915_WRITE(LCPLL_CTL, val);
		6057	POSTING_READ(LCPLL_CTL);
		6058	}
		6059	}
		6060
		6061	/*
		6062	* Fully restores LCPLL, disallowing power down and switching back to LCPLL
		6063	* source.
		6064	*/
		6065	void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
		6066	{
		6067	uint32_t val;
		6068
		6069	val = I915_READ(LCPLL_CTL);
		6070
		6071	if ((val & (LCPLL_PLL_LOCK \| LCPLL_PLL_DISABLE \| LCPLL_CD_SOURCE_FCLK \|
		6072	LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		6073	return;
		6074
		6075	/* Make sure we're not on PC8 state before disabling PC8, otherwise
		6076	* we'll hang the machine! */
		6077	dev_priv->uncore.funcs.force_wake_get(dev_priv);
		6078
		6079	if (val & LCPLL_POWER_DOWN_ALLOW) {
		6080	val &= ~LCPLL_POWER_DOWN_ALLOW;
		6081	I915_WRITE(LCPLL_CTL, val);
		6082	POSTING_READ(LCPLL_CTL);
		6083	}
		6084
		6085	val = I915_READ(D_COMP);
		6086	val \|= D_COMP_COMP_FORCE;
		6087	val &= ~D_COMP_COMP_DISABLE;
		6088	I915_WRITE(D_COMP, val);
		6089	POSTING_READ(D_COMP);
		6090
		6091	val = I915_READ(LCPLL_CTL);
		6092	val &= ~LCPLL_PLL_DISABLE;
		6093	I915_WRITE(LCPLL_CTL, val);
		6094
		6095	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		6096	DRM_ERROR("LCPLL not locked yet\n");
		6097
		6098	if (val & LCPLL_CD_SOURCE_FCLK) {
		6099	val = I915_READ(LCPLL_CTL);
		6100	val &= ~LCPLL_CD_SOURCE_FCLK;
		6101	I915_WRITE(LCPLL_CTL, val);
		6102
		6103	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
		6104	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
		6105	DRM_ERROR("Switching back to LCPLL failed\n");
		6106	}
		6107
		6108	dev_priv->uncore.funcs.force_wake_put(dev_priv);
		6109	}
		6110
		6111	void hsw_enable_pc8_work(struct work_struct *__work)
		6112	{
		6113	struct drm_i915_private *dev_priv =
		6114	container_of(to_delayed_work(__work), struct drm_i915_private,
		6115	pc8.enable_work);
		6116	struct drm_device *dev = dev_priv->dev;
		6117	uint32_t val;
		6118
		6119	if (dev_priv->pc8.enabled)
		6120	return;
		6121
		6122	DRM_DEBUG_KMS("Enabling package C8+\n");
		6123
		6124	dev_priv->pc8.enabled = true;
		6125
		6126	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6127	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6128	val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		6129	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6130	}
		6131
		6132	lpt_disable_clkout_dp(dev);
		6133	hsw_pc8_disable_interrupts(dev);
		6134	hsw_disable_lcpll(dev_priv, true, true);
		6135	}
		6136
		6137	static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6138	{
		6139	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6140	WARN(dev_priv->pc8.disable_count < 1,
		6141	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6142
		6143	dev_priv->pc8.disable_count--;
		6144	if (dev_priv->pc8.disable_count != 0)
		6145	return;
		6146
		6147	schedule_delayed_work(&dev_priv->pc8.enable_work,
		6148	msecs_to_jiffies(i915_pc8_timeout));
		6149	}
		6150
		6151	static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6152	{
		6153	struct drm_device *dev = dev_priv->dev;
		6154	uint32_t val;
		6155
		6156	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
		6157	WARN(dev_priv->pc8.disable_count < 0,
		6158	"pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
		6159
		6160	dev_priv->pc8.disable_count++;
		6161	if (dev_priv->pc8.disable_count != 1)
		6162	return;
		6163
4293	Serge	6164	cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
4104	Serge	6165	if (!dev_priv->pc8.enabled)
		6166	return;
		6167
		6168	DRM_DEBUG_KMS("Disabling package C8+\n");
		6169
		6170	hsw_restore_lcpll(dev_priv);
		6171	hsw_pc8_restore_interrupts(dev);
		6172	lpt_init_pch_refclk(dev);
		6173
		6174	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		6175	val = I915_READ(SOUTH_DSPCLK_GATE_D);
		6176	val \|= PCH_LP_PARTITION_LEVEL_DISABLE;
		6177	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
		6178	}
		6179
		6180	intel_prepare_ddi(dev);
		6181	i915_gem_init_swizzling(dev);
		6182	mutex_lock(&dev_priv->rps.hw_lock);
		6183	gen6_update_ring_freq(dev);
		6184	mutex_unlock(&dev_priv->rps.hw_lock);
		6185	dev_priv->pc8.enabled = false;
		6186	}
		6187
		6188	void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
		6189	{
		6190	mutex_lock(&dev_priv->pc8.lock);
		6191	__hsw_enable_package_c8(dev_priv);
		6192	mutex_unlock(&dev_priv->pc8.lock);
		6193	}
		6194
		6195	void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
		6196	{
		6197	mutex_lock(&dev_priv->pc8.lock);
		6198	__hsw_disable_package_c8(dev_priv);
		6199	mutex_unlock(&dev_priv->pc8.lock);
		6200	}
		6201
		6202	static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
		6203	{
		6204	struct drm_device *dev = dev_priv->dev;
		6205	struct intel_crtc *crtc;
		6206	uint32_t val;
		6207
		6208	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		6209	if (crtc->base.enabled)
		6210	return false;
		6211
		6212	/* This case is still possible since we have the i915.disable_power_well
		6213	* parameter and also the KVMr or something else might be requesting the
		6214	* power well. */
		6215	val = I915_READ(HSW_PWR_WELL_DRIVER);
		6216	if (val != 0) {
		6217	DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
		6218	return false;
		6219	}
		6220
		6221	return true;
		6222	}
		6223
		6224	/* Since we're called from modeset_global_resources there's no way to
		6225	* symmetrically increase and decrease the refcount, so we use
		6226	* dev_priv->pc8.requirements_met to track whether we already have the refcount
		6227	* or not.
		6228	*/
		6229	static void hsw_update_package_c8(struct drm_device *dev)
		6230	{
		6231	struct drm_i915_private *dev_priv = dev->dev_private;
		6232	bool allow;
		6233
		6234	if (!i915_enable_pc8)
		6235	return;
		6236
		6237	mutex_lock(&dev_priv->pc8.lock);
		6238
		6239	allow = hsw_can_enable_package_c8(dev_priv);
		6240
		6241	if (allow == dev_priv->pc8.requirements_met)
		6242	goto done;
		6243
		6244	dev_priv->pc8.requirements_met = allow;
		6245
		6246	if (allow)
		6247	__hsw_enable_package_c8(dev_priv);
		6248	else
		6249	__hsw_disable_package_c8(dev_priv);
		6250
		6251	done:
		6252	mutex_unlock(&dev_priv->pc8.lock);
		6253	}
		6254
		6255	static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
		6256	{
		6257	if (!dev_priv->pc8.gpu_idle) {
		6258	dev_priv->pc8.gpu_idle = true;
		6259	hsw_enable_package_c8(dev_priv);
		6260	}
		6261	}
		6262
		6263	static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
		6264	{
		6265	if (dev_priv->pc8.gpu_idle) {
		6266	dev_priv->pc8.gpu_idle = false;
		6267	hsw_disable_package_c8(dev_priv);
		6268	}
		6269	}
		6270
3480	Serge	6271	static void haswell_modeset_global_resources(struct drm_device *dev)
		6272	{
		6273	bool enable = false;
		6274	struct intel_crtc *crtc;
		6275
		6276	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4104	Serge	6277	if (!crtc->base.enabled)
		6278	continue;
3480	Serge	6279
4104	Serge	6280	if (crtc->pipe != PIPE_A \|\| crtc->config.pch_pfit.enabled \|\|
		6281	crtc->config.cpu_transcoder != TRANSCODER_EDP)
3480	Serge	6282	enable = true;
		6283	}
		6284
4104	Serge	6285	intel_set_power_well(dev, enable);
3480	Serge	6286
4104	Serge	6287	hsw_update_package_c8(dev);
3480	Serge	6288	}
		6289
3243	Serge	6290	static int haswell_crtc_mode_set(struct drm_crtc *crtc,
		6291	int x, int y,
		6292	struct drm_framebuffer *fb)
		6293	{
		6294	struct drm_device *dev = crtc->dev;
		6295	struct drm_i915_private *dev_priv = dev->dev_private;
		6296	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6297	int plane = intel_crtc->plane;
		6298	int ret;
		6299
4104	Serge	6300	if (!intel_ddi_pll_mode_set(crtc))
3243	Serge	6301	return -EINVAL;
		6302
3746	Serge	6303	if (intel_crtc->config.has_dp_encoder)
		6304	intel_dp_set_m_n(intel_crtc);
2327	Serge	6305
3243	Serge	6306	intel_crtc->lowfreq_avail = false;
2327	Serge	6307
4104	Serge	6308	intel_set_pipe_timings(intel_crtc);
3243	Serge	6309
4104	Serge	6310	if (intel_crtc->config.has_pch_encoder) {
		6311	intel_cpu_transcoder_set_m_n(intel_crtc,
		6312	&intel_crtc->config.fdi_m_n);
		6313	}
3243	Serge	6314
4104	Serge	6315	haswell_set_pipeconf(crtc);
2327	Serge	6316
3746	Serge	6317	intel_set_pipe_csc(crtc);
3480	Serge	6318
3031	serge	6319	/* Set up the display plane register */
3480	Serge	6320	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE \| DISPPLANE_PIPE_CSC_ENABLE);
2327	Serge	6321	POSTING_READ(DSPCNTR(plane));
		6322
3031	serge	6323	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	6324
		6325	intel_update_watermarks(dev);
		6326
		6327	return ret;
		6328	}
		6329
3746	Serge	6330	static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		6331	struct intel_crtc_config *pipe_config)
		6332	{
		6333	struct drm_device *dev = crtc->base.dev;
		6334	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	6335	enum intel_display_power_domain pfit_domain;
3746	Serge	6336	uint32_t tmp;
		6337
4104	Serge	6338	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
		6339	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
		6340
		6341	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
		6342	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		6343	enum pipe trans_edp_pipe;
		6344	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		6345	default:
		6346	WARN(1, "unknown pipe linked to edp transcoder\n");
		6347	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		6348	case TRANS_DDI_EDP_INPUT_A_ON:
		6349	trans_edp_pipe = PIPE_A;
		6350	break;
		6351	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		6352	trans_edp_pipe = PIPE_B;
		6353	break;
		6354	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		6355	trans_edp_pipe = PIPE_C;
		6356	break;
		6357	}
		6358
		6359	if (trans_edp_pipe == crtc->pipe)
		6360	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		6361	}
		6362
		6363	if (!intel_display_power_enabled(dev,
		6364	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
		6365	return false;
		6366
		6367	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
3746	Serge	6368	if (!(tmp & PIPECONF_ENABLE))
		6369	return false;
		6370
		6371	/*
4104	Serge	6372	* Haswell has only FDI/PCH transcoder A. It is which is connected to
3746	Serge	6373	* DDI E. So just check whether this pipe is wired to DDI E and whether
		6374	* the PCH transcoder is on.
		6375	*/
4104	Serge	6376	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3746	Serge	6377	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
4104	Serge	6378	I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
3746	Serge	6379	pipe_config->has_pch_encoder = true;
		6380
4104	Serge	6381	tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		6382	pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
		6383	FDI_DP_PORT_WIDTH_SHIFT) + 1;
3746	Serge	6384
4104	Serge	6385	ironlake_get_fdi_m_n_config(crtc, pipe_config);
		6386	}
		6387
		6388	intel_get_pipe_timings(crtc, pipe_config);
		6389
		6390	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
		6391	if (intel_display_power_enabled(dev, pfit_domain))
		6392	ironlake_get_pfit_config(crtc, pipe_config);
		6393
		6394	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
		6395	(I915_READ(IPS_CTL) & IPS_ENABLE);
		6396
		6397	pipe_config->pixel_multiplier = 1;
		6398
3746	Serge	6399	return true;
		6400	}
		6401
2330	Serge	6402	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		6403	int x, int y,
3031	serge	6404	struct drm_framebuffer *fb)
2330	Serge	6405	{
		6406	struct drm_device *dev = crtc->dev;
		6407	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	6408	struct intel_encoder *encoder;
2330	Serge	6409	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	6410	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
2330	Serge	6411	int pipe = intel_crtc->pipe;
		6412	int ret;
2327	Serge	6413
3031	serge	6414	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	6415
3746	Serge	6416	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
		6417
3031	serge	6418	drm_vblank_post_modeset(dev, pipe);
2327	Serge	6419
3243	Serge	6420	if (ret != 0)
2330	Serge	6421	return ret;
3243	Serge	6422
		6423	for_each_encoder_on_crtc(dev, crtc, encoder) {
		6424	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		6425	encoder->base.base.id,
		6426	drm_get_encoder_name(&encoder->base),
		6427	mode->base.id, mode->name);
3746	Serge	6428	encoder->mode_set(encoder);
3243	Serge	6429	}
		6430
		6431	return 0;
2330	Serge	6432	}
2327	Serge	6433
2342	Serge	6434	static bool intel_eld_uptodate(struct drm_connector *connector,
		6435	int reg_eldv, uint32_t bits_eldv,
		6436	int reg_elda, uint32_t bits_elda,
		6437	int reg_edid)
		6438	{
		6439	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6440	uint8_t *eld = connector->eld;
		6441	uint32_t i;
		6442
		6443	i = I915_READ(reg_eldv);
		6444	i &= bits_eldv;
		6445
		6446	if (!eld[0])
		6447	return !i;
		6448
		6449	if (!i)
		6450	return false;
		6451
		6452	i = I915_READ(reg_elda);
		6453	i &= ~bits_elda;
		6454	I915_WRITE(reg_elda, i);
		6455
		6456	for (i = 0; i < eld[2]; i++)
		6457	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		6458	return false;
		6459
		6460	return true;
		6461	}
		6462
		6463	static void g4x_write_eld(struct drm_connector *connector,
		6464	struct drm_crtc *crtc)
		6465	{
		6466	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6467	uint8_t *eld = connector->eld;
		6468	uint32_t eldv;
		6469	uint32_t len;
		6470	uint32_t i;
		6471
		6472	i = I915_READ(G4X_AUD_VID_DID);
		6473
		6474	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		6475	eldv = G4X_ELDV_DEVCL_DEVBLC;
		6476	else
		6477	eldv = G4X_ELDV_DEVCTG;
		6478
		6479	if (intel_eld_uptodate(connector,
		6480	G4X_AUD_CNTL_ST, eldv,
		6481	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		6482	G4X_HDMIW_HDMIEDID))
		6483	return;
		6484
		6485	i = I915_READ(G4X_AUD_CNTL_ST);
		6486	i &= ~(eldv \| G4X_ELD_ADDR);
		6487	len = (i >> 9) & 0x1f; /* ELD buffer size */
		6488	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6489
		6490	if (!eld[0])
		6491	return;
		6492
		6493	len = min_t(uint8_t, eld[2], len);
		6494	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6495	for (i = 0; i < len; i++)
		6496	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		6497
		6498	i = I915_READ(G4X_AUD_CNTL_ST);
		6499	i \|= eldv;
		6500	I915_WRITE(G4X_AUD_CNTL_ST, i);
		6501	}
		6502
3031	serge	6503	static void haswell_write_eld(struct drm_connector *connector,
		6504	struct drm_crtc *crtc)
		6505	{
		6506	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6507	uint8_t *eld = connector->eld;
		6508	struct drm_device *dev = crtc->dev;
3480	Serge	6509	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	6510	uint32_t eldv;
		6511	uint32_t i;
		6512	int len;
		6513	int pipe = to_intel_crtc(crtc)->pipe;
		6514	int tmp;
		6515
		6516	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		6517	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		6518	int aud_config = HSW_AUD_CFG(pipe);
		6519	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		6520
		6521
		6522	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		6523
		6524	/* Audio output enable */
		6525	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		6526	tmp = I915_READ(aud_cntrl_st2);
		6527	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		6528	I915_WRITE(aud_cntrl_st2, tmp);
		6529
		6530	/* Wait for 1 vertical blank */
		6531	intel_wait_for_vblank(dev, pipe);
		6532
		6533	/* Set ELD valid state */
		6534	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6535	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
3031	serge	6536	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		6537	I915_WRITE(aud_cntrl_st2, tmp);
		6538	tmp = I915_READ(aud_cntrl_st2);
4104	Serge	6539	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
3031	serge	6540
		6541	/* Enable HDMI mode */
		6542	tmp = I915_READ(aud_config);
4104	Serge	6543	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
3031	serge	6544	/* clear N_programing_enable and N_value_index */
		6545	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		6546	I915_WRITE(aud_config, tmp);
		6547
		6548	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		6549
		6550	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
3480	Serge	6551	intel_crtc->eld_vld = true;
3031	serge	6552
		6553	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6554	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6555	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		6556	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6557	} else
		6558	I915_WRITE(aud_config, 0);
		6559
		6560	if (intel_eld_uptodate(connector,
		6561	aud_cntrl_st2, eldv,
		6562	aud_cntl_st, IBX_ELD_ADDRESS,
		6563	hdmiw_hdmiedid))
		6564	return;
		6565
		6566	i = I915_READ(aud_cntrl_st2);
		6567	i &= ~eldv;
		6568	I915_WRITE(aud_cntrl_st2, i);
		6569
		6570	if (!eld[0])
		6571	return;
		6572
		6573	i = I915_READ(aud_cntl_st);
		6574	i &= ~IBX_ELD_ADDRESS;
		6575	I915_WRITE(aud_cntl_st, i);
		6576	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		6577	DRM_DEBUG_DRIVER("port num:%d\n", i);
		6578
		6579	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6580	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6581	for (i = 0; i < len; i++)
		6582	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6583
		6584	i = I915_READ(aud_cntrl_st2);
		6585	i \|= eldv;
		6586	I915_WRITE(aud_cntrl_st2, i);
		6587
		6588	}
		6589
2342	Serge	6590	static void ironlake_write_eld(struct drm_connector *connector,
		6591	struct drm_crtc *crtc)
		6592	{
		6593	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		6594	uint8_t *eld = connector->eld;
		6595	uint32_t eldv;
		6596	uint32_t i;
		6597	int len;
		6598	int hdmiw_hdmiedid;
3031	serge	6599	int aud_config;
2342	Serge	6600	int aud_cntl_st;
		6601	int aud_cntrl_st2;
3031	serge	6602	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	6603
		6604	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	6605	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		6606	aud_config = IBX_AUD_CFG(pipe);
		6607	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	6608	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		6609	} else {
3031	serge	6610	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		6611	aud_config = CPT_AUD_CFG(pipe);
		6612	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	6613	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		6614	}
		6615
3031	serge	6616	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	6617
		6618	i = I915_READ(aud_cntl_st);
3031	serge	6619	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	6620	if (!i) {
		6621	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		6622	/* operate blindly on all ports */
		6623	eldv = IBX_ELD_VALIDB;
		6624	eldv \|= IBX_ELD_VALIDB << 4;
		6625	eldv \|= IBX_ELD_VALIDB << 8;
		6626	} else {
4104	Serge	6627	DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
2342	Serge	6628	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		6629	}
		6630
		6631	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		6632	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		6633	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	6634	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		6635	} else
		6636	I915_WRITE(aud_config, 0);
2342	Serge	6637
		6638	if (intel_eld_uptodate(connector,
		6639	aud_cntrl_st2, eldv,
		6640	aud_cntl_st, IBX_ELD_ADDRESS,
		6641	hdmiw_hdmiedid))
		6642	return;
		6643
		6644	i = I915_READ(aud_cntrl_st2);
		6645	i &= ~eldv;
		6646	I915_WRITE(aud_cntrl_st2, i);
		6647
		6648	if (!eld[0])
		6649	return;
		6650
		6651	i = I915_READ(aud_cntl_st);
		6652	i &= ~IBX_ELD_ADDRESS;
		6653	I915_WRITE(aud_cntl_st, i);
		6654
		6655	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		6656	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		6657	for (i = 0; i < len; i++)
		6658	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		6659
		6660	i = I915_READ(aud_cntrl_st2);
		6661	i \|= eldv;
		6662	I915_WRITE(aud_cntrl_st2, i);
		6663	}
		6664
		6665	void intel_write_eld(struct drm_encoder *encoder,
		6666	struct drm_display_mode *mode)
		6667	{
		6668	struct drm_crtc *crtc = encoder->crtc;
		6669	struct drm_connector *connector;
		6670	struct drm_device *dev = encoder->dev;
		6671	struct drm_i915_private *dev_priv = dev->dev_private;
		6672
		6673	connector = drm_select_eld(encoder, mode);
		6674	if (!connector)
		6675	return;
		6676
		6677	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		6678	connector->base.id,
		6679	drm_get_connector_name(connector),
		6680	connector->encoder->base.id,
		6681	drm_get_encoder_name(connector->encoder));
		6682
		6683	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		6684
		6685	if (dev_priv->display.write_eld)
		6686	dev_priv->display.write_eld(connector, crtc);
		6687	}
		6688
2327	Serge	6689	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		6690	void intel_crtc_load_lut(struct drm_crtc *crtc)
		6691	{
		6692	struct drm_device *dev = crtc->dev;
		6693	struct drm_i915_private *dev_priv = dev->dev_private;
		6694	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	6695	enum pipe pipe = intel_crtc->pipe;
		6696	int palreg = PALETTE(pipe);
2327	Serge	6697	int i;
4104	Serge	6698	bool reenable_ips = false;
2327	Serge	6699
		6700	/* The clocks have to be on to load the palette. */
3031	serge	6701	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	6702	return;
		6703
4104	Serge	6704	if (!HAS_PCH_SPLIT(dev_priv->dev))
		6705	assert_pll_enabled(dev_priv, pipe);
		6706
2327	Serge	6707	/* use legacy palette for Ironlake */
		6708	if (HAS_PCH_SPLIT(dev))
4104	Serge	6709	palreg = LGC_PALETTE(pipe);
2327	Serge	6710
4104	Serge	6711	/* Workaround : Do not read or write the pipe palette/gamma data while
		6712	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
		6713	*/
		6714	if (intel_crtc->config.ips_enabled &&
		6715	((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
		6716	GAMMA_MODE_MODE_SPLIT)) {
		6717	hsw_disable_ips(intel_crtc);
		6718	reenable_ips = true;
		6719	}
		6720
2327	Serge	6721	for (i = 0; i < 256; i++) {
		6722	I915_WRITE(palreg + 4 * i,
		6723	(intel_crtc->lut_r[i] << 16) \|
		6724	(intel_crtc->lut_g[i] << 8) \|
		6725	intel_crtc->lut_b[i]);
		6726	}
4104	Serge	6727
		6728	if (reenable_ips)
		6729	hsw_enable_ips(intel_crtc);
2327	Serge	6730	}
		6731
3031	serge	6732	#if 0
		6733	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		6734	{
		6735	struct drm_device *dev = crtc->dev;
		6736	struct drm_i915_private *dev_priv = dev->dev_private;
		6737	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6738	bool visible = base != 0;
		6739	u32 cntl;
2327	Serge	6740
3031	serge	6741	if (intel_crtc->cursor_visible == visible)
		6742	return;
2327	Serge	6743
3031	serge	6744	cntl = I915_READ(_CURACNTR);
		6745	if (visible) {
		6746	/* On these chipsets we can only modify the base whilst
		6747	* the cursor is disabled.
		6748	*/
		6749	I915_WRITE(_CURABASE, base);
2327	Serge	6750
3031	serge	6751	cntl &= ~(CURSOR_FORMAT_MASK);
		6752	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		6753	cntl \|= CURSOR_ENABLE \|
		6754	CURSOR_GAMMA_ENABLE \|
		6755	CURSOR_FORMAT_ARGB;
		6756	} else
		6757	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		6758	I915_WRITE(_CURACNTR, cntl);
2327	Serge	6759
3031	serge	6760	intel_crtc->cursor_visible = visible;
		6761	}
2327	Serge	6762
3031	serge	6763	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		6764	{
		6765	struct drm_device *dev = crtc->dev;
		6766	struct drm_i915_private *dev_priv = dev->dev_private;
		6767	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6768	int pipe = intel_crtc->pipe;
		6769	bool visible = base != 0;
2327	Serge	6770
3031	serge	6771	if (intel_crtc->cursor_visible != visible) {
		6772	uint32_t cntl = I915_READ(CURCNTR(pipe));
		6773	if (base) {
		6774	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		6775	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6776	cntl \|= pipe << 28; /* Connect to correct pipe */
		6777	} else {
		6778	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6779	cntl \|= CURSOR_MODE_DISABLE;
		6780	}
		6781	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	6782
3031	serge	6783	intel_crtc->cursor_visible = visible;
		6784	}
		6785	/* and commit changes on next vblank */
		6786	I915_WRITE(CURBASE(pipe), base);
		6787	}
2327	Serge	6788
3031	serge	6789	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		6790	{
		6791	struct drm_device *dev = crtc->dev;
		6792	struct drm_i915_private *dev_priv = dev->dev_private;
		6793	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6794	int pipe = intel_crtc->pipe;
		6795	bool visible = base != 0;
2327	Serge	6796
3031	serge	6797	if (intel_crtc->cursor_visible != visible) {
		6798	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		6799	if (base) {
		6800	cntl &= ~CURSOR_MODE;
		6801	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		6802	} else {
		6803	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		6804	cntl \|= CURSOR_MODE_DISABLE;
		6805	}
4104	Serge	6806	if (IS_HASWELL(dev)) {
3480	Serge	6807	cntl \|= CURSOR_PIPE_CSC_ENABLE;
4104	Serge	6808	cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
		6809	}
3031	serge	6810	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	6811
3031	serge	6812	intel_crtc->cursor_visible = visible;
		6813	}
		6814	/* and commit changes on next vblank */
		6815	I915_WRITE(CURBASE_IVB(pipe), base);
		6816	}
2327	Serge	6817
3031	serge	6818	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		6819	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		6820	bool on)
		6821	{
		6822	struct drm_device *dev = crtc->dev;
		6823	struct drm_i915_private *dev_priv = dev->dev_private;
		6824	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6825	int pipe = intel_crtc->pipe;
		6826	int x = intel_crtc->cursor_x;
		6827	int y = intel_crtc->cursor_y;
		6828	u32 base, pos;
		6829	bool visible;
2327	Serge	6830
3031	serge	6831	pos = 0;
2327	Serge	6832
3031	serge	6833	if (on && crtc->enabled && crtc->fb) {
		6834	base = intel_crtc->cursor_addr;
		6835	if (x > (int) crtc->fb->width)
		6836	base = 0;
2327	Serge	6837
3031	serge	6838	if (y > (int) crtc->fb->height)
		6839	base = 0;
		6840	} else
		6841	base = 0;
2327	Serge	6842
3031	serge	6843	if (x < 0) {
		6844	if (x + intel_crtc->cursor_width < 0)
		6845	base = 0;
2327	Serge	6846
3031	serge	6847	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		6848	x = -x;
		6849	}
		6850	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	6851
3031	serge	6852	if (y < 0) {
		6853	if (y + intel_crtc->cursor_height < 0)
		6854	base = 0;
2327	Serge	6855
3031	serge	6856	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		6857	y = -y;
		6858	}
		6859	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	6860
3031	serge	6861	visible = base != 0;
		6862	if (!visible && !intel_crtc->cursor_visible)
		6863	return;
2327	Serge	6864
3031	serge	6865	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		6866	I915_WRITE(CURPOS_IVB(pipe), pos);
		6867	ivb_update_cursor(crtc, base);
		6868	} else {
		6869	I915_WRITE(CURPOS(pipe), pos);
		6870	if (IS_845G(dev) \|\| IS_I865G(dev))
		6871	i845_update_cursor(crtc, base);
		6872	else
		6873	i9xx_update_cursor(crtc, base);
		6874	}
		6875	}
2327	Serge	6876
3031	serge	6877	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		6878	struct drm_file *file,
		6879	uint32_t handle,
		6880	uint32_t width, uint32_t height)
		6881	{
		6882	struct drm_device *dev = crtc->dev;
		6883	struct drm_i915_private *dev_priv = dev->dev_private;
		6884	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6885	struct drm_i915_gem_object *obj;
		6886	uint32_t addr;
		6887	int ret;
2327	Serge	6888
3031	serge	6889	/* if we want to turn off the cursor ignore width and height */
		6890	if (!handle) {
		6891	DRM_DEBUG_KMS("cursor off\n");
		6892	addr = 0;
		6893	obj = NULL;
		6894	mutex_lock(&dev->struct_mutex);
		6895	goto finish;
		6896	}
2327	Serge	6897
3031	serge	6898	/* Currently we only support 64x64 cursors */
		6899	if (width != 64 \|\| height != 64) {
		6900	DRM_ERROR("we currently only support 64x64 cursors\n");
		6901	return -EINVAL;
		6902	}
2327	Serge	6903
3031	serge	6904	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		6905	if (&obj->base == NULL)
		6906	return -ENOENT;
2327	Serge	6907
3031	serge	6908	if (obj->base.size < width * height * 4) {
		6909	DRM_ERROR("buffer is to small\n");
		6910	ret = -ENOMEM;
		6911	goto fail;
		6912	}
2327	Serge	6913
3031	serge	6914	/* we only need to pin inside GTT if cursor is non-phy */
		6915	mutex_lock(&dev->struct_mutex);
		6916	if (!dev_priv->info->cursor_needs_physical) {
3746	Serge	6917	unsigned alignment;
		6918
3031	serge	6919	if (obj->tiling_mode) {
		6920	DRM_ERROR("cursor cannot be tiled\n");
		6921	ret = -EINVAL;
		6922	goto fail_locked;
		6923	}
2327	Serge	6924
3746	Serge	6925	/* Note that the w/a also requires 2 PTE of padding following
		6926	* the bo. We currently fill all unused PTE with the shadow
		6927	* page and so we should always have valid PTE following the
		6928	* cursor preventing the VT-d warning.
		6929	*/
		6930	alignment = 0;
		6931	if (need_vtd_wa(dev))
		6932	alignment = 64*1024;
		6933
		6934	ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
3031	serge	6935	if (ret) {
		6936	DRM_ERROR("failed to move cursor bo into the GTT\n");
		6937	goto fail_locked;
		6938	}
2327	Serge	6939
3031	serge	6940	ret = i915_gem_object_put_fence(obj);
		6941	if (ret) {
		6942	DRM_ERROR("failed to release fence for cursor");
		6943	goto fail_unpin;
		6944	}
2327	Serge	6945
4104	Serge	6946	addr = i915_gem_obj_ggtt_offset(obj);
3031	serge	6947	} else {
		6948	int align = IS_I830(dev) ? 16 * 1024 : 256;
		6949	ret = i915_gem_attach_phys_object(dev, obj,
		6950	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		6951	align);
		6952	if (ret) {
		6953	DRM_ERROR("failed to attach phys object\n");
		6954	goto fail_locked;
		6955	}
		6956	addr = obj->phys_obj->handle->busaddr;
		6957	}
2327	Serge	6958
3031	serge	6959	if (IS_GEN2(dev))
		6960	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	6961
3031	serge	6962	finish:
		6963	if (intel_crtc->cursor_bo) {
		6964	if (dev_priv->info->cursor_needs_physical) {
		6965	if (intel_crtc->cursor_bo != obj)
		6966	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		6967	} else
4104	Serge	6968	i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
3031	serge	6969	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		6970	}
2327	Serge	6971
3031	serge	6972	mutex_unlock(&dev->struct_mutex);
2327	Serge	6973
3031	serge	6974	intel_crtc->cursor_addr = addr;
		6975	intel_crtc->cursor_bo = obj;
		6976	intel_crtc->cursor_width = width;
		6977	intel_crtc->cursor_height = height;
2327	Serge	6978
4104	Serge	6979	if (intel_crtc->active)
		6980	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
2327	Serge	6981
3031	serge	6982	return 0;
		6983	fail_unpin:
4104	Serge	6984	i915_gem_object_unpin_from_display_plane(obj);
3031	serge	6985	fail_locked:
		6986	mutex_unlock(&dev->struct_mutex);
		6987	fail:
		6988	drm_gem_object_unreference_unlocked(&obj->base);
		6989	return ret;
		6990	}
2327	Serge	6991
3031	serge	6992	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		6993	{
		6994	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6995
		6996	intel_crtc->cursor_x = x;
		6997	intel_crtc->cursor_y = y;
		6998
4104	Serge	6999	if (intel_crtc->active)
		7000	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3031	serge	7001
		7002	return 0;
		7003	}
		7004	#endif
		7005
2332	Serge	7006	/** Sets the color ramps on behalf of RandR */
		7007	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		7008	u16 blue, int regno)
		7009	{
		7010	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7011
2332	Serge	7012	intel_crtc->lut_r[regno] = red >> 8;
		7013	intel_crtc->lut_g[regno] = green >> 8;
		7014	intel_crtc->lut_b[regno] = blue >> 8;
		7015	}
2327	Serge	7016
2332	Serge	7017	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		7018	u16 *blue, int regno)
		7019	{
		7020	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7021
2332	Serge	7022	*red = intel_crtc->lut_r[regno] << 8;
		7023	*green = intel_crtc->lut_g[regno] << 8;
		7024	*blue = intel_crtc->lut_b[regno] << 8;
		7025	}
2327	Serge	7026
2330	Serge	7027	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		7028	u16 *blue, uint32_t start, uint32_t size)
		7029	{
		7030	int end = (start + size > 256) ? 256 : start + size, i;
		7031	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7032
2330	Serge	7033	for (i = start; i < end; i++) {
		7034	intel_crtc->lut_r[i] = red[i] >> 8;
		7035	intel_crtc->lut_g[i] = green[i] >> 8;
		7036	intel_crtc->lut_b[i] = blue[i] >> 8;
		7037	}
2327	Serge	7038
2330	Serge	7039	intel_crtc_load_lut(crtc);
		7040	}
2327	Serge	7041
2330	Serge	7042	/* VESA 640x480x72Hz mode to set on the pipe */
		7043	static struct drm_display_mode load_detect_mode = {
		7044	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		7045	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		7046	};
2327	Serge	7047
3031	serge	7048	static struct drm_framebuffer *
		7049	intel_framebuffer_create(struct drm_device *dev,
		7050	struct drm_mode_fb_cmd2 *mode_cmd,
		7051	struct drm_i915_gem_object *obj)
		7052	{
		7053	struct intel_framebuffer *intel_fb;
		7054	int ret;
2327	Serge	7055
3031	serge	7056	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		7057	if (!intel_fb) {
		7058	drm_gem_object_unreference_unlocked(&obj->base);
		7059	return ERR_PTR(-ENOMEM);
		7060	}
2327	Serge	7061
3031	serge	7062	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		7063	if (ret) {
		7064	drm_gem_object_unreference_unlocked(&obj->base);
		7065	kfree(intel_fb);
		7066	return ERR_PTR(ret);
		7067	}
2327	Serge	7068
3031	serge	7069	return &intel_fb->base;
		7070	}
2327	Serge	7071
2330	Serge	7072	static u32
		7073	intel_framebuffer_pitch_for_width(int width, int bpp)
		7074	{
		7075	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		7076	return ALIGN(pitch, 64);
		7077	}
2327	Serge	7078
2330	Serge	7079	static u32
		7080	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		7081	{
		7082	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		7083	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		7084	}
2327	Serge	7085
2330	Serge	7086	static struct drm_framebuffer *
		7087	intel_framebuffer_create_for_mode(struct drm_device *dev,
		7088	struct drm_display_mode *mode,
		7089	int depth, int bpp)
		7090	{
		7091	struct drm_i915_gem_object *obj;
3243	Serge	7092	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327	Serge	7093
4104	Serge	7094	return NULL;
2330	Serge	7095	}
2327	Serge	7096
2330	Serge	7097	static struct drm_framebuffer *
		7098	mode_fits_in_fbdev(struct drm_device *dev,
		7099	struct drm_display_mode *mode)
		7100	{
		7101	struct drm_i915_private *dev_priv = dev->dev_private;
		7102	struct drm_i915_gem_object *obj;
		7103	struct drm_framebuffer *fb;
2327	Serge	7104
4280	Serge	7105	if (dev_priv->fbdev == NULL)
		7106	return NULL;
2327	Serge	7107
4280	Serge	7108	obj = dev_priv->fbdev->ifb.obj;
		7109	if (obj == NULL)
2330	Serge	7110	return NULL;
2327	Serge	7111
4280	Serge	7112	fb = &dev_priv->fbdev->ifb.base;
3031	serge	7113	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		7114	fb->bits_per_pixel))
4280	Serge	7115	return NULL;
2327	Serge	7116
3031	serge	7117	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		7118	return NULL;
		7119
4280	Serge	7120	return fb;
2330	Serge	7121	}
2327	Serge	7122
3031	serge	7123	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7124	struct drm_display_mode *mode,
		7125	struct intel_load_detect_pipe *old)
		7126	{
		7127	struct intel_crtc *intel_crtc;
3031	serge	7128	struct intel_encoder *intel_encoder =
		7129	intel_attached_encoder(connector);
2330	Serge	7130	struct drm_crtc *possible_crtc;
		7131	struct drm_encoder *encoder = &intel_encoder->base;
		7132	struct drm_crtc *crtc = NULL;
		7133	struct drm_device *dev = encoder->dev;
3031	serge	7134	struct drm_framebuffer *fb;
2330	Serge	7135	int i = -1;
2327	Serge	7136
2330	Serge	7137	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7138	connector->base.id, drm_get_connector_name(connector),
		7139	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7140
2330	Serge	7141	/*
		7142	* Algorithm gets a little messy:
		7143	*
		7144	* - if the connector already has an assigned crtc, use it (but make
		7145	* sure it's on first)
		7146	*
		7147	* - try to find the first unused crtc that can drive this connector,
		7148	* and use that if we find one
		7149	*/
2327	Serge	7150
2330	Serge	7151	/* See if we already have a CRTC for this connector */
		7152	if (encoder->crtc) {
		7153	crtc = encoder->crtc;
2327	Serge	7154
3480	Serge	7155	mutex_lock(&crtc->mutex);
		7156
3031	serge	7157	old->dpms_mode = connector->dpms;
2330	Serge	7158	old->load_detect_temp = false;
2327	Serge	7159
2330	Serge	7160	/* Make sure the crtc and connector are running */
3031	serge	7161	if (connector->dpms != DRM_MODE_DPMS_ON)
		7162	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	7163
2330	Serge	7164	return true;
		7165	}
2327	Serge	7166
2330	Serge	7167	/* Find an unused one (if possible) */
		7168	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		7169	i++;
		7170	if (!(encoder->possible_crtcs & (1 << i)))
		7171	continue;
		7172	if (!possible_crtc->enabled) {
		7173	crtc = possible_crtc;
		7174	break;
		7175	}
		7176	}
2327	Serge	7177
2330	Serge	7178	/*
		7179	* If we didn't find an unused CRTC, don't use any.
		7180	*/
		7181	if (!crtc) {
		7182	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		7183	return false;
		7184	}
2327	Serge	7185
3480	Serge	7186	mutex_lock(&crtc->mutex);
3031	serge	7187	intel_encoder->new_crtc = to_intel_crtc(crtc);
		7188	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	7189
2330	Serge	7190	intel_crtc = to_intel_crtc(crtc);
3031	serge	7191	old->dpms_mode = connector->dpms;
2330	Serge	7192	old->load_detect_temp = true;
		7193	old->release_fb = NULL;
2327	Serge	7194
2330	Serge	7195	if (!mode)
		7196	mode = &load_detect_mode;
2327	Serge	7197
2330	Serge	7198	/* We need a framebuffer large enough to accommodate all accesses
		7199	* that the plane may generate whilst we perform load detection.
		7200	* We can not rely on the fbcon either being present (we get called
		7201	* during its initialisation to detect all boot displays, or it may
		7202	* not even exist) or that it is large enough to satisfy the
		7203	* requested mode.
		7204	*/
3031	serge	7205	fb = mode_fits_in_fbdev(dev, mode);
		7206	if (fb == NULL) {
2330	Serge	7207	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	7208	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		7209	old->release_fb = fb;
2330	Serge	7210	} else
		7211	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	7212	if (IS_ERR(fb)) {
2330	Serge	7213	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3480	Serge	7214	mutex_unlock(&crtc->mutex);
3243	Serge	7215	return false;
2330	Serge	7216	}
2327	Serge	7217
3480	Serge	7218	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	7219	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		7220	if (old->release_fb)
		7221	old->release_fb->funcs->destroy(old->release_fb);
3480	Serge	7222	mutex_unlock(&crtc->mutex);
3243	Serge	7223	return false;
2330	Serge	7224	}
2327	Serge	7225
2330	Serge	7226	/* let the connector get through one full cycle before testing */
		7227	intel_wait_for_vblank(dev, intel_crtc->pipe);
		7228	return true;
		7229	}
2327	Serge	7230
3031	serge	7231	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	7232	struct intel_load_detect_pipe *old)
		7233	{
3031	serge	7234	struct intel_encoder *intel_encoder =
		7235	intel_attached_encoder(connector);
2330	Serge	7236	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	7237	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	7238
2330	Serge	7239	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		7240	connector->base.id, drm_get_connector_name(connector),
		7241	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	7242
2330	Serge	7243	if (old->load_detect_temp) {
3031	serge	7244	to_intel_connector(connector)->new_encoder = NULL;
		7245	intel_encoder->new_crtc = NULL;
		7246	intel_set_mode(crtc, NULL, 0, 0, NULL);
		7247
3480	Serge	7248	if (old->release_fb) {
		7249	drm_framebuffer_unregister_private(old->release_fb);
		7250	drm_framebuffer_unreference(old->release_fb);
		7251	}
2327	Serge	7252
3480	Serge	7253	mutex_unlock(&crtc->mutex);
2330	Serge	7254	return;
		7255	}
2327	Serge	7256
2330	Serge	7257	/* Switch crtc and encoder back off if necessary */
3031	serge	7258	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		7259	connector->funcs->dpms(connector, old->dpms_mode);
3480	Serge	7260
		7261	mutex_unlock(&crtc->mutex);
2330	Serge	7262	}
2327	Serge	7263
2330	Serge	7264	/* Returns the clock of the currently programmed mode of the given pipe. */
4104	Serge	7265	static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
		7266	struct intel_crtc_config *pipe_config)
2330	Serge	7267	{
4104	Serge	7268	struct drm_device *dev = crtc->base.dev;
2330	Serge	7269	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	7270	int pipe = pipe_config->cpu_transcoder;
2330	Serge	7271	u32 dpll = I915_READ(DPLL(pipe));
		7272	u32 fp;
		7273	intel_clock_t clock;
2327	Serge	7274
2330	Serge	7275	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		7276	fp = I915_READ(FP0(pipe));
		7277	else
		7278	fp = I915_READ(FP1(pipe));
2327	Serge	7279
2330	Serge	7280	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		7281	if (IS_PINEVIEW(dev)) {
		7282	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		7283	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7284	} else {
		7285	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		7286	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		7287	}
2327	Serge	7288
2330	Serge	7289	if (!IS_GEN2(dev)) {
		7290	if (IS_PINEVIEW(dev))
		7291	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		7292	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		7293	else
		7294	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		7295	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	7296
2330	Serge	7297	switch (dpll & DPLL_MODE_MASK) {
		7298	case DPLLB_MODE_DAC_SERIAL:
		7299	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		7300	5 : 10;
		7301	break;
		7302	case DPLLB_MODE_LVDS:
		7303	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		7304	7 : 14;
		7305	break;
		7306	default:
		7307	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		7308	"mode\n", (int)(dpll & DPLL_MODE_MASK));
4104	Serge	7309	pipe_config->adjusted_mode.clock = 0;
		7310	return;
2330	Serge	7311	}
2327	Serge	7312
4104	Serge	7313	if (IS_PINEVIEW(dev))
		7314	pineview_clock(96000, &clock);
		7315	else
		7316	i9xx_clock(96000, &clock);
2330	Serge	7317	} else {
		7318	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	7319
2330	Serge	7320	if (is_lvds) {
		7321	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		7322	DPLL_FPA01_P1_POST_DIV_SHIFT);
		7323	clock.p2 = 14;
2327	Serge	7324
2330	Serge	7325	if ((dpll & PLL_REF_INPUT_MASK) ==
		7326	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		7327	/* XXX: might not be 66MHz */
4104	Serge	7328	i9xx_clock(66000, &clock);
2330	Serge	7329	} else
4104	Serge	7330	i9xx_clock(48000, &clock);
2330	Serge	7331	} else {
		7332	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		7333	clock.p1 = 2;
		7334	else {
		7335	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		7336	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		7337	}
		7338	if (dpll & PLL_P2_DIVIDE_BY_4)
		7339	clock.p2 = 4;
		7340	else
		7341	clock.p2 = 2;
2327	Serge	7342
4104	Serge	7343	i9xx_clock(48000, &clock);
2330	Serge	7344	}
		7345	}
2327	Serge	7346
4104	Serge	7347	pipe_config->adjusted_mode.clock = clock.dot;
		7348	}
		7349
		7350	static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
		7351	struct intel_crtc_config *pipe_config)
		7352	{
		7353	struct drm_device *dev = crtc->base.dev;
		7354	struct drm_i915_private *dev_priv = dev->dev_private;
		7355	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
		7356	int link_freq, repeat;
		7357	u64 clock;
		7358	u32 link_m, link_n;
		7359
		7360	repeat = pipe_config->pixel_multiplier;
		7361
		7362	/*
		7363	* The calculation for the data clock is:
		7364	* pixel_clock = ((m/n)(link_clock nr_lanes * repeat))/bpp
		7365	* But we want to avoid losing precison if possible, so:
		7366	* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
		7367	*
		7368	* and the link clock is simpler:
		7369	* link_clock = (m * link_clock * repeat) / n
2330	Serge	7370	*/
2327	Serge	7371
4104	Serge	7372	/*
		7373	* We need to get the FDI or DP link clock here to derive
		7374	* the M/N dividers.
		7375	*
		7376	* For FDI, we read it from the BIOS or use a fixed 2.7GHz.
		7377	* For DP, it's either 1.62GHz or 2.7GHz.
		7378	* We do our calculations in 10*MHz since we don't need much precison.
		7379	*/
		7380	if (pipe_config->has_pch_encoder)
		7381	link_freq = intel_fdi_link_freq(dev) * 10000;
		7382	else
		7383	link_freq = pipe_config->port_clock;
		7384
		7385	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
		7386	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
		7387
		7388	if (!link_m \|\| !link_n)
		7389	return;
		7390
		7391	clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
		7392	do_div(clock, link_n);
		7393
		7394	pipe_config->adjusted_mode.clock = clock;
2330	Serge	7395	}
2327	Serge	7396
2330	Serge	7397	/** Returns the currently programmed mode of the given pipe. */
		7398	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		7399	struct drm_crtc *crtc)
		7400	{
		7401	struct drm_i915_private *dev_priv = dev->dev_private;
		7402	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746	Serge	7403	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2330	Serge	7404	struct drm_display_mode *mode;
4104	Serge	7405	struct intel_crtc_config pipe_config;
3243	Serge	7406	int htot = I915_READ(HTOTAL(cpu_transcoder));
		7407	int hsync = I915_READ(HSYNC(cpu_transcoder));
		7408	int vtot = I915_READ(VTOTAL(cpu_transcoder));
		7409	int vsync = I915_READ(VSYNC(cpu_transcoder));
2327	Serge	7410
2330	Serge	7411	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		7412	if (!mode)
		7413	return NULL;
		7414
4104	Serge	7415	/*
		7416	* Construct a pipe_config sufficient for getting the clock info
		7417	* back out of crtc_clock_get.
		7418	*
		7419	* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
		7420	* to use a real value here instead.
		7421	*/
		7422	pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
		7423	pipe_config.pixel_multiplier = 1;
		7424	i9xx_crtc_clock_get(intel_crtc, &pipe_config);
		7425
		7426	mode->clock = pipe_config.adjusted_mode.clock;
2330	Serge	7427	mode->hdisplay = (htot & 0xffff) + 1;
		7428	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		7429	mode->hsync_start = (hsync & 0xffff) + 1;
		7430	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		7431	mode->vdisplay = (vtot & 0xffff) + 1;
		7432	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		7433	mode->vsync_start = (vsync & 0xffff) + 1;
		7434	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		7435
		7436	drm_mode_set_name(mode);
		7437
		7438	return mode;
		7439	}
		7440
2327	Serge	7441	static void intel_increase_pllclock(struct drm_crtc *crtc)
		7442	{
		7443	struct drm_device *dev = crtc->dev;
		7444	drm_i915_private_t *dev_priv = dev->dev_private;
		7445	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7446	int pipe = intel_crtc->pipe;
		7447	int dpll_reg = DPLL(pipe);
		7448	int dpll;
		7449
		7450	if (HAS_PCH_SPLIT(dev))
		7451	return;
		7452
		7453	if (!dev_priv->lvds_downclock_avail)
		7454	return;
		7455
		7456	dpll = I915_READ(dpll_reg);
		7457	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		7458	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		7459
3031	serge	7460	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7461
		7462	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		7463	I915_WRITE(dpll_reg, dpll);
		7464	intel_wait_for_vblank(dev, pipe);
		7465
		7466	dpll = I915_READ(dpll_reg);
		7467	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		7468	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		7469	}
		7470	}
		7471
3031	serge	7472	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		7473	{
		7474	struct drm_device *dev = crtc->dev;
		7475	drm_i915_private_t *dev_priv = dev->dev_private;
		7476	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	7477
3031	serge	7478	if (HAS_PCH_SPLIT(dev))
		7479	return;
2327	Serge	7480
3031	serge	7481	if (!dev_priv->lvds_downclock_avail)
		7482	return;
2327	Serge	7483
3031	serge	7484	/*
		7485	* Since this is called by a timer, we should never get here in
		7486	* the manual case.
		7487	*/
		7488	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		7489	int pipe = intel_crtc->pipe;
		7490	int dpll_reg = DPLL(pipe);
		7491	int dpll;
2327	Serge	7492
3031	serge	7493	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	7494
3031	serge	7495	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	7496
3031	serge	7497	dpll = I915_READ(dpll_reg);
		7498	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		7499	I915_WRITE(dpll_reg, dpll);
		7500	intel_wait_for_vblank(dev, pipe);
		7501	dpll = I915_READ(dpll_reg);
		7502	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		7503	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		7504	}
2327	Serge	7505
3031	serge	7506	}
2327	Serge	7507
3031	serge	7508	void intel_mark_busy(struct drm_device *dev)
		7509	{
4104	Serge	7510	struct drm_i915_private *dev_priv = dev->dev_private;
		7511
		7512	hsw_package_c8_gpu_busy(dev_priv);
		7513	i915_update_gfx_val(dev_priv);
3031	serge	7514	}
2327	Serge	7515
3031	serge	7516	void intel_mark_idle(struct drm_device *dev)
		7517	{
4104	Serge	7518	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7519	struct drm_crtc *crtc;
2327	Serge	7520
4104	Serge	7521	hsw_package_c8_gpu_idle(dev_priv);
		7522
3031	serge	7523	if (!i915_powersave)
		7524	return;
2327	Serge	7525
3031	serge	7526	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7527	if (!crtc->fb)
		7528	continue;
2327	Serge	7529
3480	Serge	7530	intel_decrease_pllclock(crtc);
3031	serge	7531	}
		7532	}
2327	Serge	7533
4104	Serge	7534	void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
		7535	struct intel_ring_buffer *ring)
3031	serge	7536	{
		7537	struct drm_device *dev = obj->base.dev;
		7538	struct drm_crtc *crtc;
2327	Serge	7539
3031	serge	7540	if (!i915_powersave)
		7541	return;
2327	Serge	7542
3031	serge	7543	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		7544	if (!crtc->fb)
		7545	continue;
2327	Serge	7546
4104	Serge	7547	if (to_intel_framebuffer(crtc->fb)->obj != obj)
		7548	continue;
		7549
3480	Serge	7550	intel_increase_pllclock(crtc);
4104	Serge	7551	if (ring && intel_fbc_enabled(dev))
		7552	ring->fbc_dirty = true;
3031	serge	7553	}
		7554	}
2327	Serge	7555
2330	Serge	7556	static void intel_crtc_destroy(struct drm_crtc *crtc)
		7557	{
		7558	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7559	struct drm_device *dev = crtc->dev;
		7560	struct intel_unpin_work *work;
		7561	unsigned long flags;
2327	Serge	7562
2330	Serge	7563	spin_lock_irqsave(&dev->event_lock, flags);
		7564	work = intel_crtc->unpin_work;
		7565	intel_crtc->unpin_work = NULL;
		7566	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7567
2330	Serge	7568	if (work) {
4293	Serge	7569	cancel_work_sync(&work->work);
2330	Serge	7570	kfree(work);
		7571	}
2327	Serge	7572
2330	Serge	7573	drm_crtc_cleanup(crtc);
2327	Serge	7574
2330	Serge	7575	kfree(intel_crtc);
		7576	}
2327	Serge	7577
3031	serge	7578	#if 0
		7579	static void intel_unpin_work_fn(struct work_struct *__work)
		7580	{
		7581	struct intel_unpin_work *work =
		7582	container_of(__work, struct intel_unpin_work, work);
3243	Serge	7583	struct drm_device *dev = work->crtc->dev;
2327	Serge	7584
3243	Serge	7585	mutex_lock(&dev->struct_mutex);
3031	serge	7586	intel_unpin_fb_obj(work->old_fb_obj);
		7587	drm_gem_object_unreference(&work->pending_flip_obj->base);
		7588	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	7589
3243	Serge	7590	intel_update_fbc(dev);
		7591	mutex_unlock(&dev->struct_mutex);
		7592
		7593	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
		7594	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
		7595
3031	serge	7596	kfree(work);
		7597	}
2327	Serge	7598
3031	serge	7599	static void do_intel_finish_page_flip(struct drm_device *dev,
		7600	struct drm_crtc *crtc)
		7601	{
		7602	drm_i915_private_t *dev_priv = dev->dev_private;
		7603	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7604	struct intel_unpin_work *work;
		7605	unsigned long flags;
2327	Serge	7606
3031	serge	7607	/* Ignore early vblank irqs */
		7608	if (intel_crtc == NULL)
		7609	return;
2327	Serge	7610
3031	serge	7611	spin_lock_irqsave(&dev->event_lock, flags);
		7612	work = intel_crtc->unpin_work;
3243	Serge	7613
		7614	/* Ensure we don't miss a work->pending update ... */
		7615	smp_rmb();
		7616
		7617	if (work == NULL \|\| atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
3031	serge	7618	spin_unlock_irqrestore(&dev->event_lock, flags);
		7619	return;
		7620	}
2327	Serge	7621
3243	Serge	7622	/* and that the unpin work is consistent wrt ->pending. */
		7623	smp_rmb();
		7624
3031	serge	7625	intel_crtc->unpin_work = NULL;
2327	Serge	7626
3243	Serge	7627	if (work->event)
		7628	drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
2327	Serge	7629
3031	serge	7630	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7631
3031	serge	7632	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	7633
3480	Serge	7634	wake_up_all(&dev_priv->pending_flip_queue);
2327	Serge	7635
3243	Serge	7636	queue_work(dev_priv->wq, &work->work);
		7637
3031	serge	7638	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		7639	}
2327	Serge	7640
3031	serge	7641	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		7642	{
		7643	drm_i915_private_t *dev_priv = dev->dev_private;
		7644	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	7645
3031	serge	7646	do_intel_finish_page_flip(dev, crtc);
		7647	}
2327	Serge	7648
3031	serge	7649	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		7650	{
		7651	drm_i915_private_t *dev_priv = dev->dev_private;
		7652	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	7653
3031	serge	7654	do_intel_finish_page_flip(dev, crtc);
		7655	}
2327	Serge	7656
3031	serge	7657	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		7658	{
		7659	drm_i915_private_t *dev_priv = dev->dev_private;
		7660	struct intel_crtc *intel_crtc =
		7661	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		7662	unsigned long flags;
2327	Serge	7663
3243	Serge	7664	/* NB: An MMIO update of the plane base pointer will also
		7665	* generate a page-flip completion irq, i.e. every modeset
		7666	* is also accompanied by a spurious intel_prepare_page_flip().
		7667	*/
3031	serge	7668	spin_lock_irqsave(&dev->event_lock, flags);
3243	Serge	7669	if (intel_crtc->unpin_work)
		7670	atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
3031	serge	7671	spin_unlock_irqrestore(&dev->event_lock, flags);
		7672	}
2327	Serge	7673
3243	Serge	7674	inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
		7675	{
		7676	/* Ensure that the work item is consistent when activating it ... */
		7677	smp_wmb();
		7678	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
		7679	/* and that it is marked active as soon as the irq could fire. */
		7680	smp_wmb();
		7681	}
		7682
3031	serge	7683	static int intel_gen2_queue_flip(struct drm_device *dev,
		7684	struct drm_crtc *crtc,
		7685	struct drm_framebuffer *fb,
4104	Serge	7686	struct drm_i915_gem_object *obj,
		7687	uint32_t flags)
3031	serge	7688	{
		7689	struct drm_i915_private *dev_priv = dev->dev_private;
		7690	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7691	u32 flip_mask;
		7692	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7693	int ret;
2327	Serge	7694
3031	serge	7695	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7696	if (ret)
		7697	goto err;
2327	Serge	7698
3031	serge	7699	ret = intel_ring_begin(ring, 6);
		7700	if (ret)
		7701	goto err_unpin;
2327	Serge	7702
3031	serge	7703	/* Can't queue multiple flips, so wait for the previous
		7704	* one to finish before executing the next.
		7705	*/
		7706	if (intel_crtc->plane)
		7707	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7708	else
		7709	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7710	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7711	intel_ring_emit(ring, MI_NOOP);
		7712	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7713	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7714	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7715	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7716	intel_ring_emit(ring, 0); /* aux display base address, unused */
3243	Serge	7717
		7718	intel_mark_page_flip_active(intel_crtc);
3031	serge	7719	intel_ring_advance(ring);
		7720	return 0;
2327	Serge	7721
3031	serge	7722	err_unpin:
		7723	intel_unpin_fb_obj(obj);
		7724	err:
		7725	return ret;
		7726	}
2327	Serge	7727
3031	serge	7728	static int intel_gen3_queue_flip(struct drm_device *dev,
		7729	struct drm_crtc *crtc,
		7730	struct drm_framebuffer *fb,
4104	Serge	7731	struct drm_i915_gem_object *obj,
		7732	uint32_t flags)
3031	serge	7733	{
		7734	struct drm_i915_private *dev_priv = dev->dev_private;
		7735	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7736	u32 flip_mask;
		7737	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7738	int ret;
2327	Serge	7739
3031	serge	7740	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7741	if (ret)
		7742	goto err;
2327	Serge	7743
3031	serge	7744	ret = intel_ring_begin(ring, 6);
		7745	if (ret)
		7746	goto err_unpin;
2327	Serge	7747
3031	serge	7748	if (intel_crtc->plane)
		7749	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		7750	else
		7751	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		7752	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		7753	intel_ring_emit(ring, MI_NOOP);
		7754	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		7755	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7756	intel_ring_emit(ring, fb->pitches[0]);
4104	Serge	7757	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7758	intel_ring_emit(ring, MI_NOOP);
2327	Serge	7759
3243	Serge	7760	intel_mark_page_flip_active(intel_crtc);
3031	serge	7761	intel_ring_advance(ring);
		7762	return 0;
2327	Serge	7763
3031	serge	7764	err_unpin:
		7765	intel_unpin_fb_obj(obj);
		7766	err:
		7767	return ret;
		7768	}
2327	Serge	7769
3031	serge	7770	static int intel_gen4_queue_flip(struct drm_device *dev,
		7771	struct drm_crtc *crtc,
		7772	struct drm_framebuffer *fb,
4104	Serge	7773	struct drm_i915_gem_object *obj,
		7774	uint32_t flags)
3031	serge	7775	{
		7776	struct drm_i915_private *dev_priv = dev->dev_private;
		7777	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7778	uint32_t pf, pipesrc;
		7779	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7780	int ret;
2327	Serge	7781
3031	serge	7782	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7783	if (ret)
		7784	goto err;
2327	Serge	7785
3031	serge	7786	ret = intel_ring_begin(ring, 4);
		7787	if (ret)
		7788	goto err_unpin;
2327	Serge	7789
3031	serge	7790	/* i965+ uses the linear or tiled offsets from the
		7791	* Display Registers (which do not change across a page-flip)
		7792	* so we need only reprogram the base address.
		7793	*/
		7794	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7795	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7796	intel_ring_emit(ring, fb->pitches[0]);
		7797	intel_ring_emit(ring,
4104	Serge	7798	(i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) \|
3031	serge	7799	obj->tiling_mode);
2327	Serge	7800
3031	serge	7801	/* XXX Enabling the panel-fitter across page-flip is so far
		7802	* untested on non-native modes, so ignore it for now.
		7803	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		7804	*/
		7805	pf = 0;
		7806	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7807	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7808
		7809	intel_mark_page_flip_active(intel_crtc);
3031	serge	7810	intel_ring_advance(ring);
		7811	return 0;
2327	Serge	7812
3031	serge	7813	err_unpin:
		7814	intel_unpin_fb_obj(obj);
		7815	err:
		7816	return ret;
		7817	}
2327	Serge	7818
3031	serge	7819	static int intel_gen6_queue_flip(struct drm_device *dev,
		7820	struct drm_crtc *crtc,
		7821	struct drm_framebuffer *fb,
4104	Serge	7822	struct drm_i915_gem_object *obj,
		7823	uint32_t flags)
3031	serge	7824	{
		7825	struct drm_i915_private *dev_priv = dev->dev_private;
		7826	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7827	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		7828	uint32_t pf, pipesrc;
		7829	int ret;
2327	Serge	7830
3031	serge	7831	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7832	if (ret)
		7833	goto err;
2327	Serge	7834
3031	serge	7835	ret = intel_ring_begin(ring, 4);
		7836	if (ret)
		7837	goto err_unpin;
2327	Serge	7838
3031	serge	7839	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		7840	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		7841	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
4104	Serge	7842	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327	Serge	7843
3031	serge	7844	/* Contrary to the suggestions in the documentation,
		7845	* "Enable Panel Fitter" does not seem to be required when page
		7846	* flipping with a non-native mode, and worse causes a normal
		7847	* modeset to fail.
		7848	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		7849	*/
		7850	pf = 0;
		7851	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		7852	intel_ring_emit(ring, pf \| pipesrc);
3243	Serge	7853
		7854	intel_mark_page_flip_active(intel_crtc);
3031	serge	7855	intel_ring_advance(ring);
		7856	return 0;
2327	Serge	7857
3031	serge	7858	err_unpin:
		7859	intel_unpin_fb_obj(obj);
		7860	err:
		7861	return ret;
		7862	}
2327	Serge	7863
3031	serge	7864	static int intel_gen7_queue_flip(struct drm_device *dev,
		7865	struct drm_crtc *crtc,
		7866	struct drm_framebuffer *fb,
4104	Serge	7867	struct drm_i915_gem_object *obj,
		7868	uint32_t flags)
3031	serge	7869	{
		7870	struct drm_i915_private *dev_priv = dev->dev_private;
		7871	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104	Serge	7872	struct intel_ring_buffer *ring;
3031	serge	7873	uint32_t plane_bit = 0;
4104	Serge	7874	int len, ret;
2327	Serge	7875
4104	Serge	7876	ring = obj->ring;
		7877	if (IS_VALLEYVIEW(dev) \|\| ring == NULL \|\| ring->id != RCS)
		7878	ring = &dev_priv->ring[BCS];
		7879
3031	serge	7880	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		7881	if (ret)
		7882	goto err;
2327	Serge	7883
3031	serge	7884	switch(intel_crtc->plane) {
		7885	case PLANE_A:
		7886	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		7887	break;
		7888	case PLANE_B:
		7889	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		7890	break;
		7891	case PLANE_C:
		7892	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		7893	break;
		7894	default:
		7895	WARN_ONCE(1, "unknown plane in flip command\n");
		7896	ret = -ENODEV;
		7897	goto err_unpin;
		7898	}
2327	Serge	7899
4104	Serge	7900	len = 4;
		7901	if (ring->id == RCS)
		7902	len += 6;
		7903
		7904	ret = intel_ring_begin(ring, len);
3031	serge	7905	if (ret)
		7906	goto err_unpin;
2327	Serge	7907
4104	Serge	7908	/* Unmask the flip-done completion message. Note that the bspec says that
		7909	* we should do this for both the BCS and RCS, and that we must not unmask
		7910	* more than one flip event at any time (or ensure that one flip message
		7911	* can be sent by waiting for flip-done prior to queueing new flips).
		7912	* Experimentation says that BCS works despite DERRMR masking all
		7913	* flip-done completion events and that unmasking all planes at once
		7914	* for the RCS also doesn't appear to drop events. Setting the DERRMR
		7915	* to zero does lead to lockups within MI_DISPLAY_FLIP.
		7916	*/
		7917	if (ring->id == RCS) {
		7918	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		7919	intel_ring_emit(ring, DERRMR);
		7920	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
		7921	DERRMR_PIPEB_PRI_FLIP_DONE \|
		7922	DERRMR_PIPEC_PRI_FLIP_DONE));
		7923	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
		7924	intel_ring_emit(ring, DERRMR);
		7925	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
		7926	}
		7927
3031	serge	7928	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		7929	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
4104	Serge	7930	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
3031	serge	7931	intel_ring_emit(ring, (MI_NOOP));
3243	Serge	7932
		7933	intel_mark_page_flip_active(intel_crtc);
3031	serge	7934	intel_ring_advance(ring);
		7935	return 0;
2327	Serge	7936
3031	serge	7937	err_unpin:
		7938	intel_unpin_fb_obj(obj);
		7939	err:
		7940	return ret;
		7941	}
2327	Serge	7942
3031	serge	7943	static int intel_default_queue_flip(struct drm_device *dev,
		7944	struct drm_crtc *crtc,
		7945	struct drm_framebuffer *fb,
4104	Serge	7946	struct drm_i915_gem_object *obj,
		7947	uint32_t flags)
3031	serge	7948	{
		7949	return -ENODEV;
		7950	}
2327	Serge	7951
3031	serge	7952	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		7953	struct drm_framebuffer *fb,
4104	Serge	7954	struct drm_pending_vblank_event *event,
		7955	uint32_t page_flip_flags)
3031	serge	7956	{
		7957	struct drm_device *dev = crtc->dev;
		7958	struct drm_i915_private *dev_priv = dev->dev_private;
3480	Serge	7959	struct drm_framebuffer *old_fb = crtc->fb;
		7960	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
3031	serge	7961	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		7962	struct intel_unpin_work *work;
		7963	unsigned long flags;
		7964	int ret;
2327	Serge	7965
3031	serge	7966	/* Can't change pixel format via MI display flips. */
		7967	if (fb->pixel_format != crtc->fb->pixel_format)
		7968	return -EINVAL;
2327	Serge	7969
3031	serge	7970	/*
		7971	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		7972	* Note that pitch changes could also affect these register.
		7973	*/
		7974	if (INTEL_INFO(dev)->gen > 3 &&
		7975	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		7976	fb->pitches[0] != crtc->fb->pitches[0]))
		7977	return -EINVAL;
2327	Serge	7978
3031	serge	7979	work = kzalloc(sizeof *work, GFP_KERNEL);
		7980	if (work == NULL)
		7981	return -ENOMEM;
2327	Serge	7982
3031	serge	7983	work->event = event;
3243	Serge	7984	work->crtc = crtc;
3480	Serge	7985	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
3031	serge	7986	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	7987
3031	serge	7988	ret = drm_vblank_get(dev, intel_crtc->pipe);
		7989	if (ret)
		7990	goto free_work;
2327	Serge	7991
3031	serge	7992	/* We borrow the event spin lock for protecting unpin_work */
		7993	spin_lock_irqsave(&dev->event_lock, flags);
		7994	if (intel_crtc->unpin_work) {
		7995	spin_unlock_irqrestore(&dev->event_lock, flags);
		7996	kfree(work);
		7997	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	7998
3031	serge	7999	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		8000	return -EBUSY;
		8001	}
		8002	intel_crtc->unpin_work = work;
		8003	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	8004
3243	Serge	8005	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		8006	flush_workqueue(dev_priv->wq);
		8007
3031	serge	8008	ret = i915_mutex_lock_interruptible(dev);
		8009	if (ret)
		8010	goto cleanup;
2327	Serge	8011
3031	serge	8012	/* Reference the objects for the scheduled work. */
		8013	drm_gem_object_reference(&work->old_fb_obj->base);
		8014	drm_gem_object_reference(&obj->base);
2327	Serge	8015
3031	serge	8016	crtc->fb = fb;
2327	Serge	8017
3031	serge	8018	work->pending_flip_obj = obj;
2327	Serge	8019
3031	serge	8020	work->enable_stall_check = true;
		8021
3243	Serge	8022	atomic_inc(&intel_crtc->unpin_work_count);
3480	Serge	8023	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3031	serge	8024
4104	Serge	8025	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
3031	serge	8026	if (ret)
		8027	goto cleanup_pending;
		8028
		8029	intel_disable_fbc(dev);
4104	Serge	8030	intel_mark_fb_busy(obj, NULL);
3031	serge	8031	mutex_unlock(&dev->struct_mutex);
		8032
		8033	trace_i915_flip_request(intel_crtc->plane, obj);
		8034
		8035	return 0;
		8036
		8037	cleanup_pending:
3243	Serge	8038	atomic_dec(&intel_crtc->unpin_work_count);
3480	Serge	8039	crtc->fb = old_fb;
3031	serge	8040	drm_gem_object_unreference(&work->old_fb_obj->base);
		8041	drm_gem_object_unreference(&obj->base);
		8042	mutex_unlock(&dev->struct_mutex);
		8043
		8044	cleanup:
		8045	spin_lock_irqsave(&dev->event_lock, flags);
		8046	intel_crtc->unpin_work = NULL;
		8047	spin_unlock_irqrestore(&dev->event_lock, flags);
		8048
		8049	drm_vblank_put(dev, intel_crtc->pipe);
		8050	free_work:
		8051	kfree(work);
		8052
		8053	return ret;
		8054	}
		8055	#endif
		8056
		8057	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		8058	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		8059	.load_lut = intel_crtc_load_lut,
		8060	};
		8061
		8062	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		8063	struct drm_crtc *crtc)
		8064	{
		8065	struct drm_device *dev;
		8066	struct drm_crtc *tmp;
		8067	int crtc_mask = 1;
		8068
		8069	WARN(!crtc, "checking null crtc?\n");
		8070
		8071	dev = crtc->dev;
		8072
		8073	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		8074	if (tmp == crtc)
		8075	break;
		8076	crtc_mask <<= 1;
		8077	}
		8078
		8079	if (encoder->possible_crtcs & crtc_mask)
		8080	return true;
		8081	return false;
		8082	}
		8083
		8084	/**
		8085	* intel_modeset_update_staged_output_state
		8086	*
		8087	* Updates the staged output configuration state, e.g. after we've read out the
		8088	* current hw state.
		8089	*/
		8090	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		8091	{
		8092	struct intel_encoder *encoder;
		8093	struct intel_connector *connector;
		8094
		8095	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8096	base.head) {
		8097	connector->new_encoder =
		8098	to_intel_encoder(connector->base.encoder);
		8099	}
		8100
		8101	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8102	base.head) {
		8103	encoder->new_crtc =
		8104	to_intel_crtc(encoder->base.crtc);
		8105	}
		8106	}
		8107
		8108	/**
		8109	* intel_modeset_commit_output_state
		8110	*
		8111	* This function copies the stage display pipe configuration to the real one.
		8112	*/
		8113	static void intel_modeset_commit_output_state(struct drm_device *dev)
		8114	{
		8115	struct intel_encoder *encoder;
		8116	struct intel_connector *connector;
		8117
		8118	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8119	base.head) {
		8120	connector->base.encoder = &connector->new_encoder->base;
		8121	}
		8122
		8123	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8124	base.head) {
		8125	encoder->base.crtc = &encoder->new_crtc->base;
		8126	}
		8127	}
		8128
4104	Serge	8129	static void
		8130	connected_sink_compute_bpp(struct intel_connector * connector,
		8131	struct intel_crtc_config *pipe_config)
		8132	{
		8133	int bpp = pipe_config->pipe_bpp;
		8134
		8135	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		8136	connector->base.base.id,
		8137	drm_get_connector_name(&connector->base));
		8138
		8139	/* Don't use an invalid EDID bpc value */
		8140	if (connector->base.display_info.bpc &&
		8141	connector->base.display_info.bpc * 3 < bpp) {
		8142	DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
		8143	bpp, connector->base.display_info.bpc*3);
		8144	pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
		8145	}
		8146
		8147	/* Clamp bpp to 8 on screens without EDID 1.4 */
		8148	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		8149	DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
		8150	bpp);
		8151	pipe_config->pipe_bpp = 24;
		8152	}
		8153	}
		8154
3746	Serge	8155	static int
4104	Serge	8156	compute_baseline_pipe_bpp(struct intel_crtc *crtc,
3746	Serge	8157	struct drm_framebuffer *fb,
		8158	struct intel_crtc_config *pipe_config)
		8159	{
4104	Serge	8160	struct drm_device *dev = crtc->base.dev;
		8161	struct intel_connector *connector;
3746	Serge	8162	int bpp;
		8163
		8164	switch (fb->pixel_format) {
		8165	case DRM_FORMAT_C8:
		8166	bpp = 83; / since we go through a colormap */
		8167	break;
		8168	case DRM_FORMAT_XRGB1555:
		8169	case DRM_FORMAT_ARGB1555:
		8170	/* checked in intel_framebuffer_init already */
		8171	if (WARN_ON(INTEL_INFO(dev)->gen > 3))
		8172	return -EINVAL;
		8173	case DRM_FORMAT_RGB565:
		8174	bpp = 63; / min is 18bpp */
		8175	break;
		8176	case DRM_FORMAT_XBGR8888:
		8177	case DRM_FORMAT_ABGR8888:
		8178	/* checked in intel_framebuffer_init already */
		8179	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8180	return -EINVAL;
		8181	case DRM_FORMAT_XRGB8888:
		8182	case DRM_FORMAT_ARGB8888:
		8183	bpp = 8*3;
		8184	break;
		8185	case DRM_FORMAT_XRGB2101010:
		8186	case DRM_FORMAT_ARGB2101010:
		8187	case DRM_FORMAT_XBGR2101010:
		8188	case DRM_FORMAT_ABGR2101010:
		8189	/* checked in intel_framebuffer_init already */
		8190	if (WARN_ON(INTEL_INFO(dev)->gen < 4))
		8191	return -EINVAL;
		8192	bpp = 10*3;
		8193	break;
		8194	/* TODO: gen4+ supports 16 bpc floating point, too. */
		8195	default:
		8196	DRM_DEBUG_KMS("unsupported depth\n");
		8197	return -EINVAL;
		8198	}
		8199
		8200	pipe_config->pipe_bpp = bpp;
		8201
		8202	/* Clamp display bpp to EDID value */
		8203	list_for_each_entry(connector, &dev->mode_config.connector_list,
4104	Serge	8204	base.head) {
		8205	if (!connector->new_encoder \|\|
		8206	connector->new_encoder->new_crtc != crtc)
3746	Serge	8207	continue;
		8208
4104	Serge	8209	connected_sink_compute_bpp(connector, pipe_config);
3746	Serge	8210	}
		8211
		8212	return bpp;
		8213	}
		8214
4104	Serge	8215	static void intel_dump_pipe_config(struct intel_crtc *crtc,
		8216	struct intel_crtc_config *pipe_config,
		8217	const char *context)
		8218	{
		8219	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		8220	context, pipe_name(crtc->pipe));
		8221
		8222	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
		8223	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		8224	pipe_config->pipe_bpp, pipe_config->dither);
		8225	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		8226	pipe_config->has_pch_encoder,
		8227	pipe_config->fdi_lanes,
		8228	pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		8229	pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		8230	pipe_config->fdi_m_n.tu);
		8231	DRM_DEBUG_KMS("requested mode:\n");
		8232	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
		8233	DRM_DEBUG_KMS("adjusted mode:\n");
		8234	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
		8235	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		8236	pipe_config->gmch_pfit.control,
		8237	pipe_config->gmch_pfit.pgm_ratios,
		8238	pipe_config->gmch_pfit.lvds_border_bits);
		8239	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
		8240	pipe_config->pch_pfit.pos,
		8241	pipe_config->pch_pfit.size,
		8242	pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
		8243	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
		8244	}
		8245
		8246	static bool check_encoder_cloning(struct drm_crtc *crtc)
		8247	{
		8248	int num_encoders = 0;
		8249	bool uncloneable_encoders = false;
		8250	struct intel_encoder *encoder;
		8251
		8252	list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
		8253	base.head) {
		8254	if (&encoder->new_crtc->base != crtc)
		8255	continue;
		8256
		8257	num_encoders++;
		8258	if (!encoder->cloneable)
		8259	uncloneable_encoders = true;
		8260	}
		8261
		8262	return !(num_encoders > 1 && uncloneable_encoders);
		8263	}
		8264
3746	Serge	8265	static struct intel_crtc_config *
		8266	intel_modeset_pipe_config(struct drm_crtc *crtc,
		8267	struct drm_framebuffer *fb,
3031	serge	8268	struct drm_display_mode *mode)
		8269	{
		8270	struct drm_device *dev = crtc->dev;
		8271	struct intel_encoder *encoder;
3746	Serge	8272	struct intel_crtc_config *pipe_config;
4104	Serge	8273	int plane_bpp, ret = -EINVAL;
		8274	bool retry = true;
3031	serge	8275
4104	Serge	8276	if (!check_encoder_cloning(crtc)) {
		8277	DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		8278	return ERR_PTR(-EINVAL);
		8279	}
		8280
3746	Serge	8281	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
		8282	if (!pipe_config)
3031	serge	8283	return ERR_PTR(-ENOMEM);
		8284
3746	Serge	8285	drm_mode_copy(&pipe_config->adjusted_mode, mode);
		8286	drm_mode_copy(&pipe_config->requested_mode, mode);
4104	Serge	8287	pipe_config->cpu_transcoder =
		8288	(enum transcoder) to_intel_crtc(crtc)->pipe;
		8289	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
3746	Serge	8290
4104	Serge	8291	/*
		8292	* Sanitize sync polarity flags based on requested ones. If neither
		8293	* positive or negative polarity is requested, treat this as meaning
		8294	* negative polarity.
		8295	*/
		8296	if (!(pipe_config->adjusted_mode.flags &
		8297	(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NHSYNC)))
		8298	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		8299
		8300	if (!(pipe_config->adjusted_mode.flags &
		8301	(DRM_MODE_FLAG_PVSYNC \| DRM_MODE_FLAG_NVSYNC)))
		8302	pipe_config->adjusted_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		8303
		8304	/* Compute a starting value for pipe_config->pipe_bpp taking the source
		8305	* plane pixel format and any sink constraints into account. Returns the
		8306	* source plane bpp so that dithering can be selected on mismatches
		8307	* after encoders and crtc also have had their say. */
		8308	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
		8309	fb, pipe_config);
3746	Serge	8310	if (plane_bpp < 0)
		8311	goto fail;
		8312
4104	Serge	8313	encoder_retry:
		8314	/* Ensure the port clock defaults are reset when retrying. */
		8315	pipe_config->port_clock = 0;
		8316	pipe_config->pixel_multiplier = 1;
		8317
		8318	/* Fill in default crtc timings, allow encoders to overwrite them. */
		8319	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
		8320
3031	serge	8321	/* Pass our mode to the connectors and the CRTC to give them a chance to
		8322	* adjust it according to limitations or connector properties, and also
		8323	* a chance to reject the mode entirely.
2330	Serge	8324	*/
3031	serge	8325	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8326	base.head) {
2327	Serge	8327
3031	serge	8328	if (&encoder->new_crtc->base != crtc)
		8329	continue;
3746	Serge	8330
		8331	if (!(encoder->compute_config(encoder, pipe_config))) {
		8332	DRM_DEBUG_KMS("Encoder config failure\n");
		8333	goto fail;
		8334	}
		8335	}
		8336
4104	Serge	8337	/* Set default port clock if not overwritten by the encoder. Needs to be
		8338	* done afterwards in case the encoder adjusts the mode. */
		8339	if (!pipe_config->port_clock)
		8340	pipe_config->port_clock = pipe_config->adjusted_mode.clock;
2327	Serge	8341
4104	Serge	8342	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
		8343	if (ret < 0) {
3031	serge	8344	DRM_DEBUG_KMS("CRTC fixup failed\n");
		8345	goto fail;
		8346	}
2327	Serge	8347
4104	Serge	8348	if (ret == RETRY) {
		8349	if (WARN(!retry, "loop in pipe configuration computation\n")) {
		8350	ret = -EINVAL;
		8351	goto fail;
		8352	}
		8353
		8354	DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		8355	retry = false;
		8356	goto encoder_retry;
		8357	}
		8358
3746	Serge	8359	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
		8360	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		8361	plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
		8362
		8363	return pipe_config;
3031	serge	8364	fail:
3746	Serge	8365	kfree(pipe_config);
4104	Serge	8366	return ERR_PTR(ret);
3031	serge	8367	}
2327	Serge	8368
3031	serge	8369	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		8370	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		8371	static void
		8372	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		8373	unsigned prepare_pipes, unsigned disable_pipes)
		8374	{
		8375	struct intel_crtc *intel_crtc;
		8376	struct drm_device *dev = crtc->dev;
		8377	struct intel_encoder *encoder;
		8378	struct intel_connector *connector;
		8379	struct drm_crtc *tmp_crtc;
		8380
		8381	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		8382
		8383	/* Check which crtcs have changed outputs connected to them, these need
		8384	* to be part of the prepare_pipes mask. We don't (yet) support global
		8385	* modeset across multiple crtcs, so modeset_pipes will only have one
		8386	* bit set at most. */
		8387	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8388	base.head) {
		8389	if (connector->base.encoder == &connector->new_encoder->base)
		8390	continue;
		8391
		8392	if (connector->base.encoder) {
		8393	tmp_crtc = connector->base.encoder->crtc;
		8394
		8395	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8396	}
		8397
		8398	if (connector->new_encoder)
		8399	*prepare_pipes \|=
		8400	1 << connector->new_encoder->new_crtc->pipe;
		8401	}
		8402
		8403	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8404	base.head) {
		8405	if (encoder->base.crtc == &encoder->new_crtc->base)
		8406	continue;
		8407
		8408	if (encoder->base.crtc) {
		8409	tmp_crtc = encoder->base.crtc;
		8410
		8411	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		8412	}
		8413
		8414	if (encoder->new_crtc)
		8415	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		8416	}
		8417
		8418	/* Check for any pipes that will be fully disabled ... */
		8419	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8420	base.head) {
		8421	bool used = false;
		8422
		8423	/* Don't try to disable disabled crtcs. */
		8424	if (!intel_crtc->base.enabled)
		8425	continue;
		8426
		8427	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8428	base.head) {
		8429	if (encoder->new_crtc == intel_crtc)
		8430	used = true;
		8431	}
		8432
		8433	if (!used)
		8434	*disable_pipes \|= 1 << intel_crtc->pipe;
		8435	}
		8436
		8437
		8438	/* set_mode is also used to update properties on life display pipes. */
		8439	intel_crtc = to_intel_crtc(crtc);
		8440	if (crtc->enabled)
		8441	*prepare_pipes \|= 1 << intel_crtc->pipe;
		8442
3746	Serge	8443	/*
		8444	* For simplicity do a full modeset on any pipe where the output routing
		8445	* changed. We could be more clever, but that would require us to be
		8446	* more careful with calling the relevant encoder->mode_set functions.
		8447	*/
3031	serge	8448	if (*prepare_pipes)
		8449	modeset_pipes = prepare_pipes;
		8450
		8451	/* ... and mask these out. */
		8452	modeset_pipes &= ~(disable_pipes);
		8453	prepare_pipes &= ~(disable_pipes);
3746	Serge	8454
		8455	/*
		8456	* HACK: We don't (yet) fully support global modesets. intel_set_config
		8457	* obies this rule, but the modeset restore mode of
		8458	* intel_modeset_setup_hw_state does not.
		8459	*/
		8460	*modeset_pipes &= 1 << intel_crtc->pipe;
		8461	*prepare_pipes &= 1 << intel_crtc->pipe;
4104	Serge	8462
		8463	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		8464	modeset_pipes, prepare_pipes, *disable_pipes);
2330	Serge	8465	}
2327	Serge	8466
3031	serge	8467	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	8468	{
3031	serge	8469	struct drm_encoder *encoder;
2330	Serge	8470	struct drm_device *dev = crtc->dev;
2327	Serge	8471
3031	serge	8472	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		8473	if (encoder->crtc == crtc)
		8474	return true;
		8475
		8476	return false;
		8477	}
		8478
		8479	static void
		8480	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		8481	{
		8482	struct intel_encoder *intel_encoder;
		8483	struct intel_crtc *intel_crtc;
		8484	struct drm_connector *connector;
		8485
		8486	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		8487	base.head) {
		8488	if (!intel_encoder->base.crtc)
		8489	continue;
		8490
		8491	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		8492
		8493	if (prepare_pipes & (1 << intel_crtc->pipe))
		8494	intel_encoder->connectors_active = false;
		8495	}
		8496
		8497	intel_modeset_commit_output_state(dev);
		8498
		8499	/* Update computed state. */
		8500	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		8501	base.head) {
		8502	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		8503	}
		8504
		8505	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		8506	if (!connector->encoder \|\| !connector->encoder->crtc)
		8507	continue;
		8508
		8509	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		8510
		8511	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		8512	struct drm_property *dpms_property =
		8513	dev->mode_config.dpms_property;
		8514
		8515	connector->dpms = DRM_MODE_DPMS_ON;
3243	Serge	8516	drm_object_property_set_value(&connector->base,
3031	serge	8517	dpms_property,
		8518	DRM_MODE_DPMS_ON);
		8519
		8520	intel_encoder = to_intel_encoder(connector->encoder);
		8521	intel_encoder->connectors_active = true;
		8522	}
		8523	}
		8524
		8525	}
		8526
4104	Serge	8527	static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
		8528	struct intel_crtc_config *new)
		8529	{
		8530	int clock1, clock2, diff;
		8531
		8532	clock1 = cur->adjusted_mode.clock;
		8533	clock2 = new->adjusted_mode.clock;
		8534
		8535	if (clock1 == clock2)
		8536	return true;
		8537
		8538	if (!clock1 \|\| !clock2)
		8539	return false;
		8540
		8541	diff = abs(clock1 - clock2);
		8542
		8543	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		8544	return true;
		8545
		8546	return false;
		8547	}
		8548
3031	serge	8549	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		8550	list_for_each_entry((intel_crtc), \
		8551	&(dev)->mode_config.crtc_list, \
		8552	base.head) \
4104	Serge	8553	if (mask & (1 <<(intel_crtc)->pipe))
3031	serge	8554
3746	Serge	8555	static bool
4104	Serge	8556	intel_pipe_config_compare(struct drm_device *dev,
		8557	struct intel_crtc_config *current_config,
3746	Serge	8558	struct intel_crtc_config *pipe_config)
		8559	{
4104	Serge	8560	#define PIPE_CONF_CHECK_X(name) \
		8561	if (current_config->name != pipe_config->name) { \
		8562	DRM_ERROR("mismatch in " #name " " \
		8563	"(expected 0x%08x, found 0x%08x)\n", \
		8564	current_config->name, \
		8565	pipe_config->name); \
		8566	return false; \
3746	Serge	8567	}
		8568
4104	Serge	8569	#define PIPE_CONF_CHECK_I(name) \
		8570	if (current_config->name != pipe_config->name) { \
		8571	DRM_ERROR("mismatch in " #name " " \
		8572	"(expected %i, found %i)\n", \
		8573	current_config->name, \
		8574	pipe_config->name); \
		8575	return false; \
		8576	}
		8577
		8578	#define PIPE_CONF_CHECK_FLAGS(name, mask) \
		8579	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		8580	DRM_ERROR("mismatch in " #name "(" #mask ") " \
		8581	"(expected %i, found %i)\n", \
		8582	current_config->name & (mask), \
		8583	pipe_config->name & (mask)); \
		8584	return false; \
		8585	}
		8586
		8587	#define PIPE_CONF_QUIRK(quirk) \
		8588	((current_config->quirks \| pipe_config->quirks) & (quirk))
		8589
		8590	PIPE_CONF_CHECK_I(cpu_transcoder);
		8591
		8592	PIPE_CONF_CHECK_I(has_pch_encoder);
		8593	PIPE_CONF_CHECK_I(fdi_lanes);
		8594	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
		8595	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
		8596	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
		8597	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
		8598	PIPE_CONF_CHECK_I(fdi_m_n.tu);
		8599
		8600	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
		8601	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
		8602	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
		8603	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
		8604	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
		8605	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
		8606
		8607	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
		8608	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
		8609	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
		8610	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
		8611	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
		8612	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
		8613
		8614	PIPE_CONF_CHECK_I(pixel_multiplier);
		8615
		8616	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8617	DRM_MODE_FLAG_INTERLACE);
		8618
		8619	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		8620	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8621	DRM_MODE_FLAG_PHSYNC);
		8622	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8623	DRM_MODE_FLAG_NHSYNC);
		8624	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8625	DRM_MODE_FLAG_PVSYNC);
		8626	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
		8627	DRM_MODE_FLAG_NVSYNC);
		8628	}
		8629
		8630	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
		8631	PIPE_CONF_CHECK_I(requested_mode.vdisplay);
		8632
		8633	PIPE_CONF_CHECK_I(gmch_pfit.control);
		8634	/* pfit ratios are autocomputed by the hw on gen4+ */
		8635	if (INTEL_INFO(dev)->gen < 4)
		8636	PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
		8637	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
		8638	PIPE_CONF_CHECK_I(pch_pfit.enabled);
		8639	if (current_config->pch_pfit.enabled) {
		8640	PIPE_CONF_CHECK_I(pch_pfit.pos);
		8641	PIPE_CONF_CHECK_I(pch_pfit.size);
		8642	}
		8643
		8644	PIPE_CONF_CHECK_I(ips_enabled);
		8645
		8646	PIPE_CONF_CHECK_I(shared_dpll);
		8647	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
		8648	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
		8649	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
		8650	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
		8651
4280	Serge	8652	if (IS_G4X(dev) \|\| INTEL_INFO(dev)->gen >= 5)
		8653	PIPE_CONF_CHECK_I(pipe_bpp);
		8654
4104	Serge	8655	#undef PIPE_CONF_CHECK_X
		8656	#undef PIPE_CONF_CHECK_I
		8657	#undef PIPE_CONF_CHECK_FLAGS
		8658	#undef PIPE_CONF_QUIRK
		8659
		8660	if (!IS_HASWELL(dev)) {
		8661	if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
		8662	DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
		8663	current_config->adjusted_mode.clock,
		8664	pipe_config->adjusted_mode.clock);
		8665	return false;
		8666	}
		8667	}
		8668
3746	Serge	8669	return true;
		8670	}
		8671
4104	Serge	8672	static void
		8673	check_connector_state(struct drm_device *dev)
3031	serge	8674	{
		8675	struct intel_connector *connector;
		8676
		8677	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8678	base.head) {
		8679	/* This also checks the encoder/connector hw state with the
		8680	* ->get_hw_state callbacks. */
		8681	intel_connector_check_state(connector);
		8682
		8683	WARN(&connector->new_encoder->base != connector->base.encoder,
		8684	"connector's staged encoder doesn't match current encoder\n");
		8685	}
4104	Serge	8686	}
3031	serge	8687
4104	Serge	8688	static void
		8689	check_encoder_state(struct drm_device *dev)
		8690	{
		8691	struct intel_encoder *encoder;
		8692	struct intel_connector *connector;
		8693
3031	serge	8694	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8695	base.head) {
		8696	bool enabled = false;
		8697	bool active = false;
		8698	enum pipe pipe, tracked_pipe;
		8699
		8700	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		8701	encoder->base.base.id,
		8702	drm_get_encoder_name(&encoder->base));
		8703
		8704	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		8705	"encoder's stage crtc doesn't match current crtc\n");
		8706	WARN(encoder->connectors_active && !encoder->base.crtc,
		8707	"encoder's active_connectors set, but no crtc\n");
		8708
		8709	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8710	base.head) {
		8711	if (connector->base.encoder != &encoder->base)
		8712	continue;
		8713	enabled = true;
		8714	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		8715	active = true;
		8716	}
		8717	WARN(!!encoder->base.crtc != enabled,
		8718	"encoder's enabled state mismatch "
		8719	"(expected %i, found %i)\n",
		8720	!!encoder->base.crtc, enabled);
		8721	WARN(active && !encoder->base.crtc,
		8722	"active encoder with no crtc\n");
		8723
		8724	WARN(encoder->connectors_active != active,
		8725	"encoder's computed active state doesn't match tracked active state "
		8726	"(expected %i, found %i)\n", active, encoder->connectors_active);
		8727
		8728	active = encoder->get_hw_state(encoder, &pipe);
		8729	WARN(active != encoder->connectors_active,
		8730	"encoder's hw state doesn't match sw tracking "
		8731	"(expected %i, found %i)\n",
		8732	encoder->connectors_active, active);
		8733
		8734	if (!encoder->base.crtc)
		8735	continue;
		8736
		8737	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		8738	WARN(active && pipe != tracked_pipe,
		8739	"active encoder's pipe doesn't match"
		8740	"(expected %i, found %i)\n",
		8741	tracked_pipe, pipe);
		8742
		8743	}
4104	Serge	8744	}
3031	serge	8745
4104	Serge	8746	static void
		8747	check_crtc_state(struct drm_device *dev)
		8748	{
		8749	drm_i915_private_t *dev_priv = dev->dev_private;
		8750	struct intel_crtc *crtc;
		8751	struct intel_encoder *encoder;
		8752	struct intel_crtc_config pipe_config;
		8753
3031	serge	8754	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8755	base.head) {
		8756	bool enabled = false;
		8757	bool active = false;
		8758
4104	Serge	8759	memset(&pipe_config, 0, sizeof(pipe_config));
		8760
3031	serge	8761	DRM_DEBUG_KMS("[CRTC:%d]\n",
		8762	crtc->base.base.id);
		8763
		8764	WARN(crtc->active && !crtc->base.enabled,
		8765	"active crtc, but not enabled in sw tracking\n");
		8766
		8767	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8768	base.head) {
		8769	if (encoder->base.crtc != &crtc->base)
		8770	continue;
		8771	enabled = true;
		8772	if (encoder->connectors_active)
		8773	active = true;
		8774	}
4104	Serge	8775
3031	serge	8776	WARN(active != crtc->active,
		8777	"crtc's computed active state doesn't match tracked active state "
		8778	"(expected %i, found %i)\n", active, crtc->active);
		8779	WARN(enabled != crtc->base.enabled,
		8780	"crtc's computed enabled state doesn't match tracked enabled state "
		8781	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		8782
3746	Serge	8783	active = dev_priv->display.get_pipe_config(crtc,
		8784	&pipe_config);
		8785
		8786	/* hw state is inconsistent with the pipe A quirk */
		8787	if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		8788	active = crtc->active;
		8789
4104	Serge	8790	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8791	base.head) {
		8792	enum pipe pipe;
		8793	if (encoder->base.crtc != &crtc->base)
		8794	continue;
		8795	if (encoder->get_config &&
		8796	encoder->get_hw_state(encoder, &pipe))
		8797	encoder->get_config(encoder, &pipe_config);
		8798	}
		8799
		8800	if (dev_priv->display.get_clock)
		8801	dev_priv->display.get_clock(crtc, &pipe_config);
		8802
3746	Serge	8803	WARN(crtc->active != active,
		8804	"crtc active state doesn't match with hw state "
		8805	"(expected %i, found %i)\n", crtc->active, active);
		8806
4104	Serge	8807	if (active &&
		8808	!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
		8809	WARN(1, "pipe state doesn't match!\n");
		8810	intel_dump_pipe_config(crtc, &pipe_config,
		8811	"[hw state]");
		8812	intel_dump_pipe_config(crtc, &crtc->config,
		8813	"[sw state]");
		8814	}
3031	serge	8815	}
		8816	}
		8817
4104	Serge	8818	static void
		8819	check_shared_dpll_state(struct drm_device *dev)
		8820	{
		8821	drm_i915_private_t *dev_priv = dev->dev_private;
		8822	struct intel_crtc *crtc;
		8823	struct intel_dpll_hw_state dpll_hw_state;
		8824	int i;
		8825
		8826	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		8827	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		8828	int enabled_crtcs = 0, active_crtcs = 0;
		8829	bool active;
		8830
		8831	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
		8832
		8833	DRM_DEBUG_KMS("%s\n", pll->name);
		8834
		8835	active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
		8836
		8837	WARN(pll->active > pll->refcount,
		8838	"more active pll users than references: %i vs %i\n",
		8839	pll->active, pll->refcount);
		8840	WARN(pll->active && !pll->on,
		8841	"pll in active use but not on in sw tracking\n");
		8842	WARN(pll->on && !pll->active,
		8843	"pll in on but not on in use in sw tracking\n");
		8844	WARN(pll->on != active,
		8845	"pll on state mismatch (expected %i, found %i)\n",
		8846	pll->on, active);
		8847
		8848	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		8849	base.head) {
		8850	if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
		8851	enabled_crtcs++;
		8852	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		8853	active_crtcs++;
		8854	}
		8855	WARN(pll->active != active_crtcs,
		8856	"pll active crtcs mismatch (expected %i, found %i)\n",
		8857	pll->active, active_crtcs);
		8858	WARN(pll->refcount != enabled_crtcs,
		8859	"pll enabled crtcs mismatch (expected %i, found %i)\n",
		8860	pll->refcount, enabled_crtcs);
		8861
		8862	WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
		8863	sizeof(dpll_hw_state)),
		8864	"pll hw state mismatch\n");
		8865	}
		8866	}
		8867
		8868	void
		8869	intel_modeset_check_state(struct drm_device *dev)
		8870	{
		8871	check_connector_state(dev);
		8872	check_encoder_state(dev);
		8873	check_crtc_state(dev);
		8874	check_shared_dpll_state(dev);
		8875	}
		8876
3746	Serge	8877	static int __intel_set_mode(struct drm_crtc *crtc,
3031	serge	8878	struct drm_display_mode *mode,
		8879	int x, int y, struct drm_framebuffer *fb)
		8880	{
		8881	struct drm_device *dev = crtc->dev;
		8882	drm_i915_private_t *dev_priv = dev->dev_private;
3746	Serge	8883	struct drm_display_mode saved_mode, saved_hwmode;
		8884	struct intel_crtc_config *pipe_config = NULL;
3031	serge	8885	struct intel_crtc *intel_crtc;
		8886	unsigned disable_pipes, prepare_pipes, modeset_pipes;
3480	Serge	8887	int ret = 0;
3031	serge	8888
3480	Serge	8889	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
		8890	if (!saved_mode)
		8891	return -ENOMEM;
		8892	saved_hwmode = saved_mode + 1;
		8893
3031	serge	8894	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		8895	&prepare_pipes, &disable_pipes);
		8896
3480	Serge	8897	*saved_hwmode = crtc->hwmode;
		8898	*saved_mode = crtc->mode;
3031	serge	8899
		8900	/* Hack: Because we don't (yet) support global modeset on multiple
		8901	* crtcs, we don't keep track of the new mode for more than one crtc.
		8902	* Hence simply check whether any bit is set in modeset_pipes in all the
		8903	* pieces of code that are not yet converted to deal with mutliple crtcs
		8904	* changing their mode at the same time. */
		8905	if (modeset_pipes) {
3746	Serge	8906	pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
		8907	if (IS_ERR(pipe_config)) {
		8908	ret = PTR_ERR(pipe_config);
		8909	pipe_config = NULL;
		8910
3480	Serge	8911	goto out;
3031	serge	8912	}
4104	Serge	8913	intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
		8914	"[modeset]");
3031	serge	8915	}
		8916
3746	Serge	8917	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		8918	intel_crtc_disable(&intel_crtc->base);
		8919
3031	serge	8920	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		8921	if (intel_crtc->base.enabled)
		8922	dev_priv->display.crtc_disable(&intel_crtc->base);
		8923	}
		8924
		8925	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		8926	* to set it here already despite that we pass it down the callchain.
2330	Serge	8927	*/
3746	Serge	8928	if (modeset_pipes) {
3031	serge	8929	crtc->mode = *mode;
3746	Serge	8930	/* mode_set/enable/disable functions rely on a correct pipe
		8931	* config. */
		8932	to_intel_crtc(crtc)->config = *pipe_config;
		8933	}
2327	Serge	8934
3031	serge	8935	/* Only after disabling all output pipelines that will be changed can we
		8936	* update the the output configuration. */
		8937	intel_modeset_update_state(dev, prepare_pipes);
		8938
3243	Serge	8939	if (dev_priv->display.modeset_global_resources)
		8940	dev_priv->display.modeset_global_resources(dev);
		8941
3031	serge	8942	/* Set up the DPLL and any encoders state that needs to adjust or depend
		8943	* on the DPLL.
2330	Serge	8944	*/
3031	serge	8945	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
3480	Serge	8946	ret = intel_crtc_mode_set(&intel_crtc->base,
3031	serge	8947	x, y, fb);
3480	Serge	8948	if (ret)
3031	serge	8949	goto done;
		8950	}
		8951
		8952	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		8953	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		8954	dev_priv->display.crtc_enable(&intel_crtc->base);
		8955
		8956	if (modeset_pipes) {
		8957	/* Store real post-adjustment hardware mode. */
3746	Serge	8958	crtc->hwmode = pipe_config->adjusted_mode;
3031	serge	8959
		8960	/* Calculate and store various constants which
		8961	* are later needed by vblank and swap-completion
		8962	* timestamping. They are derived from true hwmode.
		8963	*/
		8964	drm_calc_timestamping_constants(crtc);
		8965	}
		8966
		8967	/* FIXME: add subpixel order */
		8968	done:
3480	Serge	8969	if (ret && crtc->enabled) {
		8970	crtc->hwmode = *saved_hwmode;
		8971	crtc->mode = *saved_mode;
3031	serge	8972	}
		8973
3480	Serge	8974	out:
3746	Serge	8975	kfree(pipe_config);
3480	Serge	8976	kfree(saved_mode);
3031	serge	8977	return ret;
2330	Serge	8978	}
2327	Serge	8979
4104	Serge	8980	static int intel_set_mode(struct drm_crtc *crtc,
3746	Serge	8981	struct drm_display_mode *mode,
		8982	int x, int y, struct drm_framebuffer *fb)
		8983	{
		8984	int ret;
		8985
		8986	ret = __intel_set_mode(crtc, mode, x, y, fb);
		8987
		8988	if (ret == 0)
		8989	intel_modeset_check_state(crtc->dev);
		8990
		8991	return ret;
		8992	}
		8993
3480	Serge	8994	void intel_crtc_restore_mode(struct drm_crtc *crtc)
		8995	{
		8996	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
		8997	}
		8998
3031	serge	8999	#undef for_each_intel_crtc_masked
2327	Serge	9000
3031	serge	9001	static void intel_set_config_free(struct intel_set_config *config)
		9002	{
		9003	if (!config)
		9004	return;
		9005
		9006	kfree(config->save_connector_encoders);
		9007	kfree(config->save_encoder_crtcs);
		9008	kfree(config);
		9009	}
		9010
		9011	static int intel_set_config_save_state(struct drm_device *dev,
		9012	struct intel_set_config *config)
		9013	{
		9014	struct drm_encoder *encoder;
		9015	struct drm_connector *connector;
		9016	int count;
		9017
		9018	config->save_encoder_crtcs =
		9019	kcalloc(dev->mode_config.num_encoder,
		9020	sizeof(struct drm_crtc *), GFP_KERNEL);
		9021	if (!config->save_encoder_crtcs)
		9022	return -ENOMEM;
		9023
		9024	config->save_connector_encoders =
		9025	kcalloc(dev->mode_config.num_connector,
		9026	sizeof(struct drm_encoder *), GFP_KERNEL);
		9027	if (!config->save_connector_encoders)
		9028	return -ENOMEM;
		9029
		9030	/* Copy data. Note that driver private data is not affected.
		9031	* Should anything bad happen only the expected state is
		9032	* restored, not the drivers personal bookkeeping.
		9033	*/
		9034	count = 0;
		9035	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		9036	config->save_encoder_crtcs[count++] = encoder->crtc;
		9037	}
		9038
		9039	count = 0;
		9040	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		9041	config->save_connector_encoders[count++] = connector->encoder;
		9042	}
		9043
		9044	return 0;
		9045	}
		9046
		9047	static void intel_set_config_restore_state(struct drm_device *dev,
		9048	struct intel_set_config *config)
		9049	{
		9050	struct intel_encoder *encoder;
		9051	struct intel_connector *connector;
		9052	int count;
		9053
		9054	count = 0;
		9055	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9056	encoder->new_crtc =
		9057	to_intel_crtc(config->save_encoder_crtcs[count++]);
		9058	}
		9059
		9060	count = 0;
		9061	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		9062	connector->new_encoder =
		9063	to_intel_encoder(config->save_connector_encoders[count++]);
		9064	}
		9065	}
		9066
3746	Serge	9067	static bool
4104	Serge	9068	is_crtc_connector_off(struct drm_mode_set *set)
3746	Serge	9069	{
		9070	int i;
		9071
4104	Serge	9072	if (set->num_connectors == 0)
		9073	return false;
		9074
		9075	if (WARN_ON(set->connectors == NULL))
		9076	return false;
		9077
		9078	for (i = 0; i < set->num_connectors; i++)
		9079	if (set->connectors[i]->encoder &&
		9080	set->connectors[i]->encoder->crtc == set->crtc &&
		9081	set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
3746	Serge	9082	return true;
		9083
		9084	return false;
		9085	}
		9086
3031	serge	9087	static void
		9088	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		9089	struct intel_set_config *config)
		9090	{
		9091
		9092	/* We should be able to check here if the fb has the same properties
		9093	* and then just flip_or_move it */
4104	Serge	9094	if (is_crtc_connector_off(set)) {
3746	Serge	9095	config->mode_changed = true;
		9096	} else if (set->crtc->fb != set->fb) {
3031	serge	9097	/* If we have no fb then treat it as a full mode set */
		9098	if (set->crtc->fb == NULL) {
4104	Serge	9099	struct intel_crtc *intel_crtc =
		9100	to_intel_crtc(set->crtc);
		9101
		9102	if (intel_crtc->active && i915_fastboot) {
		9103	DRM_DEBUG_KMS("crtc has no fb, will flip\n");
		9104	config->fb_changed = true;
		9105	} else {
		9106	DRM_DEBUG_KMS("inactive crtc, full mode set\n");
3031	serge	9107	config->mode_changed = true;
4104	Serge	9108	}
3031	serge	9109	} else if (set->fb == NULL) {
		9110	config->mode_changed = true;
3746	Serge	9111	} else if (set->fb->pixel_format !=
		9112	set->crtc->fb->pixel_format) {
3031	serge	9113	config->mode_changed = true;
3746	Serge	9114	} else {
3031	serge	9115	config->fb_changed = true;
		9116	}
3746	Serge	9117	}
3031	serge	9118
		9119	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		9120	config->fb_changed = true;
		9121
		9122	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		9123	DRM_DEBUG_KMS("modes are different, full mode set\n");
		9124	drm_mode_debug_printmodeline(&set->crtc->mode);
		9125	drm_mode_debug_printmodeline(set->mode);
		9126	config->mode_changed = true;
		9127	}
4104	Serge	9128
		9129	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
		9130	set->crtc->base.id, config->mode_changed, config->fb_changed);
3031	serge	9131	}
		9132
		9133	static int
		9134	intel_modeset_stage_output_state(struct drm_device *dev,
		9135	struct drm_mode_set *set,
		9136	struct intel_set_config *config)
		9137	{
		9138	struct drm_crtc *new_crtc;
		9139	struct intel_connector *connector;
		9140	struct intel_encoder *encoder;
4104	Serge	9141	int ro;
3031	serge	9142
3480	Serge	9143	/* The upper layers ensure that we either disable a crtc or have a list
3031	serge	9144	* of connectors. For paranoia, double-check this. */
		9145	WARN_ON(!set->fb && (set->num_connectors != 0));
		9146	WARN_ON(set->fb && (set->num_connectors == 0));
		9147
		9148	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9149	base.head) {
		9150	/* Otherwise traverse passed in connector list and get encoders
		9151	* for them. */
		9152	for (ro = 0; ro < set->num_connectors; ro++) {
		9153	if (set->connectors[ro] == &connector->base) {
		9154	connector->new_encoder = connector->encoder;
		9155	break;
		9156	}
		9157	}
		9158
		9159	/* If we disable the crtc, disable all its connectors. Also, if
		9160	* the connector is on the changing crtc but not on the new
		9161	* connector list, disable it. */
		9162	if ((!set->fb \|\| ro == set->num_connectors) &&
		9163	connector->base.encoder &&
		9164	connector->base.encoder->crtc == set->crtc) {
		9165	connector->new_encoder = NULL;
		9166
		9167	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		9168	connector->base.base.id,
		9169	drm_get_connector_name(&connector->base));
		9170	}
		9171
		9172
		9173	if (&connector->new_encoder->base != connector->base.encoder) {
		9174	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		9175	config->mode_changed = true;
		9176	}
		9177	}
		9178	/* connector->new_encoder is now updated for all connectors. */
		9179
		9180	/* Update crtc of enabled connectors. */
		9181	list_for_each_entry(connector, &dev->mode_config.connector_list,
		9182	base.head) {
		9183	if (!connector->new_encoder)
		9184	continue;
		9185
		9186	new_crtc = connector->new_encoder->base.crtc;
		9187
		9188	for (ro = 0; ro < set->num_connectors; ro++) {
		9189	if (set->connectors[ro] == &connector->base)
		9190	new_crtc = set->crtc;
		9191	}
		9192
		9193	/* Make sure the new CRTC will work with the encoder */
		9194	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		9195	new_crtc)) {
		9196	return -EINVAL;
		9197	}
		9198	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		9199
		9200	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		9201	connector->base.base.id,
		9202	drm_get_connector_name(&connector->base),
		9203	new_crtc->base.id);
		9204	}
		9205
		9206	/* Check for any encoders that needs to be disabled. */
		9207	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		9208	base.head) {
		9209	list_for_each_entry(connector,
		9210	&dev->mode_config.connector_list,
		9211	base.head) {
		9212	if (connector->new_encoder == encoder) {
		9213	WARN_ON(!connector->new_encoder->new_crtc);
		9214
		9215	goto next_encoder;
		9216	}
		9217	}
		9218	encoder->new_crtc = NULL;
		9219	next_encoder:
		9220	/* Only now check for crtc changes so we don't miss encoders
		9221	* that will be disabled. */
		9222	if (&encoder->new_crtc->base != encoder->base.crtc) {
		9223	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		9224	config->mode_changed = true;
		9225	}
		9226	}
		9227	/* Now we've also updated encoder->new_crtc for all encoders. */
		9228
		9229	return 0;
		9230	}
		9231
		9232	static int intel_crtc_set_config(struct drm_mode_set *set)
		9233	{
		9234	struct drm_device *dev;
		9235	struct drm_mode_set save_set;
		9236	struct intel_set_config *config;
		9237	int ret;
		9238
		9239	BUG_ON(!set);
		9240	BUG_ON(!set->crtc);
		9241	BUG_ON(!set->crtc->helper_private);
		9242
3480	Serge	9243	/* Enforce sane interface api - has been abused by the fb helper. */
		9244	BUG_ON(!set->mode && set->fb);
		9245	BUG_ON(set->fb && set->num_connectors == 0);
3031	serge	9246
		9247	if (set->fb) {
		9248	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		9249	set->crtc->base.id, set->fb->base.id,
		9250	(int)set->num_connectors, set->x, set->y);
		9251	} else {
		9252	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		9253	}
		9254
		9255	dev = set->crtc->dev;
		9256
		9257	ret = -ENOMEM;
		9258	config = kzalloc(sizeof(*config), GFP_KERNEL);
		9259	if (!config)
		9260	goto out_config;
		9261
		9262	ret = intel_set_config_save_state(dev, config);
		9263	if (ret)
		9264	goto out_config;
		9265
		9266	save_set.crtc = set->crtc;
		9267	save_set.mode = &set->crtc->mode;
		9268	save_set.x = set->crtc->x;
		9269	save_set.y = set->crtc->y;
		9270	save_set.fb = set->crtc->fb;
		9271
		9272	/* Compute whether we need a full modeset, only an fb base update or no
		9273	* change at all. In the future we might also check whether only the
		9274	* mode changed, e.g. for LVDS where we only change the panel fitter in
		9275	* such cases. */
		9276	intel_set_config_compute_mode_changes(set, config);
		9277
		9278	ret = intel_modeset_stage_output_state(dev, set, config);
		9279	if (ret)
		9280	goto fail;
		9281
		9282	if (config->mode_changed) {
3480	Serge	9283	ret = intel_set_mode(set->crtc, set->mode,
		9284	set->x, set->y, set->fb);
3031	serge	9285	} else if (config->fb_changed) {
3746	Serge	9286	// intel_crtc_wait_for_pending_flips(set->crtc);
		9287
3031	serge	9288	ret = intel_pipe_set_base(set->crtc,
		9289	set->x, set->y, set->fb);
		9290	}
		9291
3746	Serge	9292	if (ret) {
4104	Serge	9293	DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
3746	Serge	9294	set->crtc->base.id, ret);
3031	serge	9295	fail:
		9296	intel_set_config_restore_state(dev, config);
		9297
		9298	/* Try to restore the config */
		9299	if (config->mode_changed &&
3480	Serge	9300	intel_set_mode(save_set.crtc, save_set.mode,
3031	serge	9301	save_set.x, save_set.y, save_set.fb))
		9302	DRM_ERROR("failed to restore config after modeset failure\n");
3746	Serge	9303	}
3031	serge	9304
		9305	out_config:
		9306	intel_set_config_free(config);
		9307	return ret;
		9308	}
		9309
2330	Serge	9310	static const struct drm_crtc_funcs intel_crtc_funcs = {
		9311	// .cursor_set = intel_crtc_cursor_set,
		9312	// .cursor_move = intel_crtc_cursor_move,
		9313	.gamma_set = intel_crtc_gamma_set,
3031	serge	9314	.set_config = intel_crtc_set_config,
2330	Serge	9315	.destroy = intel_crtc_destroy,
		9316	// .page_flip = intel_crtc_page_flip,
		9317	};
2327	Serge	9318
3243	Serge	9319	static void intel_cpu_pll_init(struct drm_device *dev)
		9320	{
3480	Serge	9321	if (HAS_DDI(dev))
3243	Serge	9322	intel_ddi_pll_init(dev);
		9323	}
		9324
4104	Serge	9325	static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
		9326	struct intel_shared_dpll *pll,
		9327	struct intel_dpll_hw_state *hw_state)
3031	serge	9328	{
4104	Serge	9329	uint32_t val;
3031	serge	9330
4104	Serge	9331	val = I915_READ(PCH_DPLL(pll->id));
		9332	hw_state->dpll = val;
		9333	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
		9334	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
		9335
		9336	return val & DPLL_VCO_ENABLE;
		9337	}
		9338
		9339	static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
		9340	struct intel_shared_dpll *pll)
		9341	{
		9342	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
		9343	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
		9344	}
		9345
		9346	static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
		9347	struct intel_shared_dpll *pll)
		9348	{
		9349	/* PCH refclock must be enabled first */
		9350	assert_pch_refclk_enabled(dev_priv);
		9351
		9352	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9353
		9354	/* Wait for the clocks to stabilize. */
		9355	POSTING_READ(PCH_DPLL(pll->id));
		9356	udelay(150);
		9357
		9358	/* The pixel multiplier can only be updated once the
		9359	* DPLL is enabled and the clocks are stable.
		9360	*
		9361	* So write it again.
		9362	*/
		9363	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
		9364	POSTING_READ(PCH_DPLL(pll->id));
		9365	udelay(200);
		9366	}
		9367
		9368	static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
		9369	struct intel_shared_dpll *pll)
		9370	{
		9371	struct drm_device *dev = dev_priv->dev;
		9372	struct intel_crtc *crtc;
		9373
		9374	/* Make sure no transcoder isn't still depending on us. */
		9375	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		9376	if (intel_crtc_to_shared_dpll(crtc) == pll)
		9377	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
3031	serge	9378	}
		9379
4104	Serge	9380	I915_WRITE(PCH_DPLL(pll->id), 0);
		9381	POSTING_READ(PCH_DPLL(pll->id));
		9382	udelay(200);
		9383	}
		9384
		9385	static char *ibx_pch_dpll_names[] = {
		9386	"PCH DPLL A",
		9387	"PCH DPLL B",
		9388	};
		9389
		9390	static void ibx_pch_dpll_init(struct drm_device *dev)
		9391	{
		9392	struct drm_i915_private *dev_priv = dev->dev_private;
		9393	int i;
		9394
		9395	dev_priv->num_shared_dpll = 2;
		9396
		9397	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		9398	dev_priv->shared_dplls[i].id = i;
		9399	dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
		9400	dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
		9401	dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		9402	dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
		9403	dev_priv->shared_dplls[i].get_hw_state =
		9404	ibx_pch_dpll_get_hw_state;
3031	serge	9405	}
		9406	}
		9407
4104	Serge	9408	static void intel_shared_dpll_init(struct drm_device *dev)
		9409	{
		9410	struct drm_i915_private *dev_priv = dev->dev_private;
		9411
		9412	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
		9413	ibx_pch_dpll_init(dev);
		9414	else
		9415	dev_priv->num_shared_dpll = 0;
		9416
		9417	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
		9418	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
		9419	dev_priv->num_shared_dpll);
		9420	}
		9421
2330	Serge	9422	static void intel_crtc_init(struct drm_device *dev, int pipe)
		9423	{
		9424	drm_i915_private_t *dev_priv = dev->dev_private;
		9425	struct intel_crtc *intel_crtc;
		9426	int i;
2327	Serge	9427
2330	Serge	9428	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		9429	if (intel_crtc == NULL)
		9430	return;
2327	Serge	9431
2330	Serge	9432	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	9433
2330	Serge	9434	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		9435	for (i = 0; i < 256; i++) {
		9436	intel_crtc->lut_r[i] = i;
		9437	intel_crtc->lut_g[i] = i;
		9438	intel_crtc->lut_b[i] = i;
		9439	}
2327	Serge	9440
2330	Serge	9441	/* Swap pipes & planes for FBC on pre-965 */
		9442	intel_crtc->pipe = pipe;
		9443	intel_crtc->plane = pipe;
		9444	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		9445	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		9446	intel_crtc->plane = !pipe;
		9447	}
2327	Serge	9448
2330	Serge	9449	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		9450	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		9451	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		9452	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	9453
2330	Serge	9454	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
		9455	}
2327	Serge	9456
3031	serge	9457	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		9458	struct drm_file *file)
		9459	{
		9460	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		9461	struct drm_mode_object *drmmode_obj;
		9462	struct intel_crtc *crtc;
2327	Serge	9463
3482	Serge	9464	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		9465	return -ENODEV;
		9466
3031	serge	9467	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		9468	DRM_MODE_OBJECT_CRTC);
2327	Serge	9469
3031	serge	9470	if (!drmmode_obj) {
		9471	DRM_ERROR("no such CRTC id\n");
		9472	return -EINVAL;
		9473	}
2327	Serge	9474
3031	serge	9475	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		9476	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	9477
3031	serge	9478	return 0;
		9479	}
2327	Serge	9480
3031	serge	9481	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	9482	{
3031	serge	9483	struct drm_device *dev = encoder->base.dev;
		9484	struct intel_encoder *source_encoder;
2330	Serge	9485	int index_mask = 0;
		9486	int entry = 0;
2327	Serge	9487
3031	serge	9488	list_for_each_entry(source_encoder,
		9489	&dev->mode_config.encoder_list, base.head) {
		9490
		9491	if (encoder == source_encoder)
2330	Serge	9492	index_mask \|= (1 << entry);
3031	serge	9493
		9494	/* Intel hw has only one MUX where enocoders could be cloned. */
		9495	if (encoder->cloneable && source_encoder->cloneable)
		9496	index_mask \|= (1 << entry);
		9497
2330	Serge	9498	entry++;
		9499	}
2327	Serge	9500
2330	Serge	9501	return index_mask;
		9502	}
2327	Serge	9503
2330	Serge	9504	static bool has_edp_a(struct drm_device *dev)
		9505	{
		9506	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9507
2330	Serge	9508	if (!IS_MOBILE(dev))
		9509	return false;
2327	Serge	9510
2330	Serge	9511	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		9512	return false;
2327	Serge	9513
2330	Serge	9514	if (IS_GEN5(dev) &&
		9515	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		9516	return false;
2327	Serge	9517
2330	Serge	9518	return true;
		9519	}
2327	Serge	9520
2330	Serge	9521	static void intel_setup_outputs(struct drm_device *dev)
		9522	{
		9523	struct drm_i915_private *dev_priv = dev->dev_private;
		9524	struct intel_encoder *encoder;
		9525	bool dpd_is_edp = false;
2327	Serge	9526
4104	Serge	9527	intel_lvds_init(dev);
2327	Serge	9528
3746	Serge	9529	if (!IS_ULT(dev))
2330	Serge	9530	intel_crt_init(dev);
2327	Serge	9531
3480	Serge	9532	if (HAS_DDI(dev)) {
2330	Serge	9533	int found;
2327	Serge	9534
3031	serge	9535	/* Haswell uses DDI functions to detect digital outputs */
		9536	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		9537	/* DDI A only supports eDP */
		9538	if (found)
		9539	intel_ddi_init(dev, PORT_A);
		9540
		9541	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		9542	* register */
		9543	found = I915_READ(SFUSE_STRAP);
		9544
		9545	if (found & SFUSE_STRAP_DDIB_DETECTED)
		9546	intel_ddi_init(dev, PORT_B);
		9547	if (found & SFUSE_STRAP_DDIC_DETECTED)
		9548	intel_ddi_init(dev, PORT_C);
		9549	if (found & SFUSE_STRAP_DDID_DETECTED)
		9550	intel_ddi_init(dev, PORT_D);
		9551	} else if (HAS_PCH_SPLIT(dev)) {
		9552	int found;
3243	Serge	9553	dpd_is_edp = intel_dpd_is_edp(dev);
3031	serge	9554
3243	Serge	9555	if (has_edp_a(dev))
		9556	intel_dp_init(dev, DP_A, PORT_A);
		9557
3746	Serge	9558	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
2330	Serge	9559	/* PCH SDVOB multiplex with HDMIB */
3031	serge	9560	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	9561	if (!found)
3746	Serge	9562	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
2330	Serge	9563	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	9564	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	9565	}
2327	Serge	9566
3746	Serge	9567	if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
		9568	intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
2327	Serge	9569
3746	Serge	9570	if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
		9571	intel_hdmi_init(dev, PCH_HDMID, PORT_D);
2327	Serge	9572
2330	Serge	9573	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	9574	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	9575
3243	Serge	9576	if (I915_READ(PCH_DP_D) & DP_DETECTED)
3031	serge	9577	intel_dp_init(dev, PCH_DP_D, PORT_D);
		9578	} else if (IS_VALLEYVIEW(dev)) {
3243	Serge	9579	/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
4104	Serge	9580	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
		9581	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
		9582	PORT_C);
3480	Serge	9583	if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
4104	Serge	9584	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
		9585	PORT_C);
		9586	}
3243	Serge	9587
3746	Serge	9588	if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
		9589	intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
		9590	PORT_B);
3480	Serge	9591	if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
		9592	intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
3031	serge	9593	}
2330	Serge	9594	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		9595	bool found = false;
2327	Serge	9596
3746	Serge	9597	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9598	DRM_DEBUG_KMS("probing SDVOB\n");
3746	Serge	9599	found = intel_sdvo_init(dev, GEN3_SDVOB, true);
2330	Serge	9600	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		9601	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3746	Serge	9602	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
2330	Serge	9603	}
2327	Serge	9604
4104	Serge	9605	if (!found && SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9606	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	9607	}
2327	Serge	9608
2330	Serge	9609	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	9610
3746	Serge	9611	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
2330	Serge	9612	DRM_DEBUG_KMS("probing SDVOC\n");
3746	Serge	9613	found = intel_sdvo_init(dev, GEN3_SDVOC, false);
2330	Serge	9614	}
2327	Serge	9615
3746	Serge	9616	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
2327	Serge	9617
2330	Serge	9618	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		9619	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3746	Serge	9620	intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
2330	Serge	9621	}
4104	Serge	9622	if (SUPPORTS_INTEGRATED_DP(dev))
3031	serge	9623	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	9624	}
2327	Serge	9625
2330	Serge	9626	if (SUPPORTS_INTEGRATED_DP(dev) &&
4104	Serge	9627	(I915_READ(DP_D) & DP_DETECTED))
3031	serge	9628	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	9629	} else if (IS_GEN2(dev))
		9630	intel_dvo_init(dev);
2327	Serge	9631
2330	Serge	9632	// if (SUPPORTS_TV(dev))
		9633	// intel_tv_init(dev);
2327	Serge	9634
2330	Serge	9635	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		9636	encoder->base.possible_crtcs = encoder->crtc_mask;
		9637	encoder->base.possible_clones =
3031	serge	9638	intel_encoder_clones(encoder);
2330	Serge	9639	}
2327	Serge	9640
3243	Serge	9641	intel_init_pch_refclk(dev);
		9642
		9643	drm_helper_move_panel_connectors_to_head(dev);
2330	Serge	9644	}
		9645
		9646
		9647
2335	Serge	9648	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		9649	// .destroy = intel_user_framebuffer_destroy,
		9650	// .create_handle = intel_user_framebuffer_create_handle,
		9651	};
2327	Serge	9652
2335	Serge	9653	int intel_framebuffer_init(struct drm_device *dev,
		9654	struct intel_framebuffer *intel_fb,
2342	Serge	9655	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	9656	struct drm_i915_gem_object *obj)
		9657	{
4104	Serge	9658	int pitch_limit;
2335	Serge	9659	int ret;
2327	Serge	9660
3243	Serge	9661	if (obj->tiling_mode == I915_TILING_Y) {
		9662	DRM_DEBUG("hardware does not support tiling Y\n");
2335	Serge	9663	return -EINVAL;
3243	Serge	9664	}
2327	Serge	9665
3243	Serge	9666	if (mode_cmd->pitches[0] & 63) {
		9667	DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
		9668	mode_cmd->pitches[0]);
		9669	return -EINVAL;
		9670	}
		9671
4104	Serge	9672	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		9673	pitch_limit = 32*1024;
		9674	} else if (INTEL_INFO(dev)->gen >= 4) {
		9675	if (obj->tiling_mode)
		9676	pitch_limit = 16*1024;
		9677	else
		9678	pitch_limit = 32*1024;
		9679	} else if (INTEL_INFO(dev)->gen >= 3) {
		9680	if (obj->tiling_mode)
		9681	pitch_limit = 8*1024;
		9682	else
		9683	pitch_limit = 16*1024;
		9684	} else
		9685	/* XXX DSPC is limited to 4k tiled */
		9686	pitch_limit = 8*1024;
		9687
		9688	if (mode_cmd->pitches[0] > pitch_limit) {
		9689	DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
		9690	obj->tiling_mode ? "tiled" : "linear",
		9691	mode_cmd->pitches[0], pitch_limit);
3243	Serge	9692	return -EINVAL;
		9693	}
		9694
		9695	if (obj->tiling_mode != I915_TILING_NONE &&
		9696	mode_cmd->pitches[0] != obj->stride) {
		9697	DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
		9698	mode_cmd->pitches[0], obj->stride);
2335	Serge	9699	return -EINVAL;
3243	Serge	9700	}
2327	Serge	9701
3243	Serge	9702	/* Reject formats not supported by any plane early. */
2342	Serge	9703	switch (mode_cmd->pixel_format) {
3243	Serge	9704	case DRM_FORMAT_C8:
2342	Serge	9705	case DRM_FORMAT_RGB565:
		9706	case DRM_FORMAT_XRGB8888:
3243	Serge	9707	case DRM_FORMAT_ARGB8888:
		9708	break;
		9709	case DRM_FORMAT_XRGB1555:
		9710	case DRM_FORMAT_ARGB1555:
		9711	if (INTEL_INFO(dev)->gen > 3) {
4104	Serge	9712	DRM_DEBUG("unsupported pixel format: %s\n",
		9713	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9714	return -EINVAL;
		9715	}
		9716	break;
3031	serge	9717	case DRM_FORMAT_XBGR8888:
3243	Serge	9718	case DRM_FORMAT_ABGR8888:
2342	Serge	9719	case DRM_FORMAT_XRGB2101010:
		9720	case DRM_FORMAT_ARGB2101010:
3243	Serge	9721	case DRM_FORMAT_XBGR2101010:
		9722	case DRM_FORMAT_ABGR2101010:
		9723	if (INTEL_INFO(dev)->gen < 4) {
4104	Serge	9724	DRM_DEBUG("unsupported pixel format: %s\n",
		9725	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9726	return -EINVAL;
		9727	}
2335	Serge	9728	break;
2342	Serge	9729	case DRM_FORMAT_YUYV:
		9730	case DRM_FORMAT_UYVY:
		9731	case DRM_FORMAT_YVYU:
		9732	case DRM_FORMAT_VYUY:
3243	Serge	9733	if (INTEL_INFO(dev)->gen < 5) {
4104	Serge	9734	DRM_DEBUG("unsupported pixel format: %s\n",
		9735	drm_get_format_name(mode_cmd->pixel_format));
3243	Serge	9736	return -EINVAL;
		9737	}
2342	Serge	9738	break;
2335	Serge	9739	default:
4104	Serge	9740	DRM_DEBUG("unsupported pixel format: %s\n",
		9741	drm_get_format_name(mode_cmd->pixel_format));
2335	Serge	9742	return -EINVAL;
		9743	}
2327	Serge	9744
3243	Serge	9745	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
		9746	if (mode_cmd->offsets[0] != 0)
		9747	return -EINVAL;
		9748
3480	Serge	9749	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		9750	intel_fb->obj = obj;
		9751
2335	Serge	9752	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		9753	if (ret) {
		9754	DRM_ERROR("framebuffer init failed %d\n", ret);
		9755	return ret;
		9756	}
2327	Serge	9757
2335	Serge	9758	return 0;
		9759	}
2327	Serge	9760
		9761
2360	Serge	9762	static const struct drm_mode_config_funcs intel_mode_funcs = {
		9763	.fb_create = NULL /intel_user_framebuffer_create/,
3480	Serge	9764	.output_poll_changed = intel_fb_output_poll_changed,
2360	Serge	9765	};
2327	Serge	9766
3031	serge	9767	/* Set up chip specific display functions */
		9768	static void intel_init_display(struct drm_device *dev)
		9769	{
		9770	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9771
4104	Serge	9772	if (HAS_PCH_SPLIT(dev) \|\| IS_G4X(dev))
		9773	dev_priv->display.find_dpll = g4x_find_best_dpll;
		9774	else if (IS_VALLEYVIEW(dev))
		9775	dev_priv->display.find_dpll = vlv_find_best_dpll;
		9776	else if (IS_PINEVIEW(dev))
		9777	dev_priv->display.find_dpll = pnv_find_best_dpll;
		9778	else
		9779	dev_priv->display.find_dpll = i9xx_find_best_dpll;
		9780
3480	Serge	9781	if (HAS_DDI(dev)) {
3746	Serge	9782	dev_priv->display.get_pipe_config = haswell_get_pipe_config;
3243	Serge	9783	dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		9784	dev_priv->display.crtc_enable = haswell_crtc_enable;
		9785	dev_priv->display.crtc_disable = haswell_crtc_disable;
		9786	dev_priv->display.off = haswell_crtc_off;
		9787	dev_priv->display.update_plane = ironlake_update_plane;
		9788	} else if (HAS_PCH_SPLIT(dev)) {
3746	Serge	9789	dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
4104	Serge	9790	dev_priv->display.get_clock = ironlake_crtc_clock_get;
3031	serge	9791	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		9792	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		9793	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		9794	dev_priv->display.off = ironlake_crtc_off;
		9795	dev_priv->display.update_plane = ironlake_update_plane;
4104	Serge	9796	} else if (IS_VALLEYVIEW(dev)) {
		9797	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
		9798	dev_priv->display.get_clock = i9xx_crtc_clock_get;
		9799	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9800	dev_priv->display.crtc_enable = valleyview_crtc_enable;
		9801	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9802	dev_priv->display.off = i9xx_crtc_off;
		9803	dev_priv->display.update_plane = i9xx_update_plane;
3031	serge	9804	} else {
3746	Serge	9805	dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
4104	Serge	9806	dev_priv->display.get_clock = i9xx_crtc_clock_get;
3031	serge	9807	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		9808	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		9809	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		9810	dev_priv->display.off = i9xx_crtc_off;
		9811	dev_priv->display.update_plane = i9xx_update_plane;
		9812	}
2327	Serge	9813
3031	serge	9814	/* Returns the core display clock speed */
		9815	if (IS_VALLEYVIEW(dev))
		9816	dev_priv->display.get_display_clock_speed =
		9817	valleyview_get_display_clock_speed;
		9818	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		9819	dev_priv->display.get_display_clock_speed =
		9820	i945_get_display_clock_speed;
		9821	else if (IS_I915G(dev))
		9822	dev_priv->display.get_display_clock_speed =
		9823	i915_get_display_clock_speed;
4104	Serge	9824	else if (IS_I945GM(dev) \|\| IS_845G(dev))
3031	serge	9825	dev_priv->display.get_display_clock_speed =
		9826	i9xx_misc_get_display_clock_speed;
4104	Serge	9827	else if (IS_PINEVIEW(dev))
		9828	dev_priv->display.get_display_clock_speed =
		9829	pnv_get_display_clock_speed;
3031	serge	9830	else if (IS_I915GM(dev))
		9831	dev_priv->display.get_display_clock_speed =
		9832	i915gm_get_display_clock_speed;
		9833	else if (IS_I865G(dev))
		9834	dev_priv->display.get_display_clock_speed =
		9835	i865_get_display_clock_speed;
		9836	else if (IS_I85X(dev))
		9837	dev_priv->display.get_display_clock_speed =
		9838	i855_get_display_clock_speed;
		9839	else /* 852, 830 */
		9840	dev_priv->display.get_display_clock_speed =
		9841	i830_get_display_clock_speed;
2327	Serge	9842
3031	serge	9843	if (HAS_PCH_SPLIT(dev)) {
		9844	if (IS_GEN5(dev)) {
		9845	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		9846	dev_priv->display.write_eld = ironlake_write_eld;
		9847	} else if (IS_GEN6(dev)) {
		9848	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		9849	dev_priv->display.write_eld = ironlake_write_eld;
		9850	} else if (IS_IVYBRIDGE(dev)) {
		9851	/* FIXME: detect B0+ stepping and use auto training */
		9852	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		9853	dev_priv->display.write_eld = ironlake_write_eld;
3243	Serge	9854	dev_priv->display.modeset_global_resources =
		9855	ivb_modeset_global_resources;
3031	serge	9856	} else if (IS_HASWELL(dev)) {
		9857	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		9858	dev_priv->display.write_eld = haswell_write_eld;
3480	Serge	9859	dev_priv->display.modeset_global_resources =
		9860	haswell_modeset_global_resources;
		9861	}
3031	serge	9862	} else if (IS_G4X(dev)) {
		9863	dev_priv->display.write_eld = g4x_write_eld;
		9864	}
2327	Serge	9865
3031	serge	9866	/* Default just returns -ENODEV to indicate unsupported */
		9867	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	9868
		9869
		9870
		9871
3031	serge	9872	}
		9873
		9874	/*
		9875	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		9876	* resume, or other times. This quirk makes sure that's the case for
		9877	* affected systems.
		9878	*/
		9879	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	9880	{
		9881	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	9882
3031	serge	9883	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		9884	DRM_INFO("applying pipe a force quirk\n");
		9885	}
2327	Serge	9886
3031	serge	9887	/*
		9888	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		9889	*/
		9890	static void quirk_ssc_force_disable(struct drm_device *dev)
		9891	{
		9892	struct drm_i915_private *dev_priv = dev->dev_private;
		9893	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		9894	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	9895	}
2327	Serge	9896
3031	serge	9897	/*
		9898	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		9899	* brightness value
		9900	*/
		9901	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	9902	{
		9903	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	9904	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		9905	DRM_INFO("applying inverted panel brightness quirk\n");
		9906	}
2327	Serge	9907
4104	Serge	9908	/*
		9909	* Some machines (Dell XPS13) suffer broken backlight controls if
		9910	* BLM_PCH_PWM_ENABLE is set.
		9911	*/
		9912	static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
		9913	{
		9914	struct drm_i915_private *dev_priv = dev->dev_private;
		9915	dev_priv->quirks \|= QUIRK_NO_PCH_PWM_ENABLE;
		9916	DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
		9917	}
		9918
3031	serge	9919	struct intel_quirk {
		9920	int device;
		9921	int subsystem_vendor;
		9922	int subsystem_device;
		9923	void (hook)(struct drm_device dev);
		9924	};
2327	Serge	9925
3031	serge	9926	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		9927	struct intel_dmi_quirk {
		9928	void (hook)(struct drm_device dev);
		9929	const struct dmi_system_id (*dmi_id_list)[];
		9930	};
2327	Serge	9931
3031	serge	9932	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		9933	{
		9934	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		9935	return 1;
2330	Serge	9936	}
2327	Serge	9937
3031	serge	9938	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		9939	{
		9940	.dmi_id_list = &(const struct dmi_system_id[]) {
		9941	{
		9942	.callback = intel_dmi_reverse_brightness,
		9943	.ident = "NCR Corporation",
		9944	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		9945	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		9946	},
		9947	},
		9948	{ } /* terminating entry */
		9949	},
		9950	.hook = quirk_invert_brightness,
		9951	},
		9952	};
2327	Serge	9953
3031	serge	9954	static struct intel_quirk intel_quirks[] = {
		9955	/* HP Mini needs pipe A force quirk (LP: #322104) */
		9956	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	9957
3031	serge	9958	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		9959	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	9960
3031	serge	9961	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		9962	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	9963
3031	serge	9964	/* 830/845 need to leave pipe A & dpll A up */
		9965	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		9966	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	9967
3031	serge	9968	/* Lenovo U160 cannot use SSC on LVDS */
		9969	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	9970
3031	serge	9971	/* Sony Vaio Y cannot use SSC on LVDS */
		9972	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	9973
3031	serge	9974	/* Acer Aspire 5734Z must invert backlight brightness */
		9975	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
3480	Serge	9976
		9977	/* Acer/eMachines G725 */
		9978	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
		9979
		9980	/* Acer/eMachines e725 */
		9981	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
		9982
		9983	/* Acer/Packard Bell NCL20 */
		9984	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
		9985
		9986	/* Acer Aspire 4736Z */
		9987	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
4104	Serge	9988
		9989	/* Dell XPS13 HD Sandy Bridge */
		9990	{ 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
		9991	/* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
		9992	{ 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
3031	serge	9993	};
2327	Serge	9994
3031	serge	9995	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	9996	{
3031	serge	9997	struct pci_dev *d = dev->pdev;
		9998	int i;
2327	Serge	9999
3031	serge	10000	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		10001	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	10002
3031	serge	10003	if (d->device == q->device &&
		10004	(d->subsystem_vendor == q->subsystem_vendor \|\|
		10005	q->subsystem_vendor == PCI_ANY_ID) &&
		10006	(d->subsystem_device == q->subsystem_device \|\|
		10007	q->subsystem_device == PCI_ANY_ID))
		10008	q->hook(dev);
		10009	}
2330	Serge	10010	}
2327	Serge	10011
3031	serge	10012	/* Disable the VGA plane that we never use */
		10013	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	10014	{
		10015	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10016	u8 sr1;
3480	Serge	10017	u32 vga_reg = i915_vgacntrl_reg(dev);
2327	Serge	10018
3031	serge	10019	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		10020	out8(SR01, VGA_SR_INDEX);
		10021	sr1 = in8(VGA_SR_DATA);
		10022	out8(sr1 \| 1<<5, VGA_SR_DATA);
		10023	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		10024	udelay(300);
2327	Serge	10025
3031	serge	10026	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		10027	POSTING_READ(vga_reg);
2330	Serge	10028	}
		10029
3031	serge	10030	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	10031	{
3480	Serge	10032	intel_init_power_well(dev);
2342	Serge	10033
3031	serge	10034	intel_prepare_ddi(dev);
2342	Serge	10035
3031	serge	10036	intel_init_clock_gating(dev);
		10037
3482	Serge	10038	mutex_lock(&dev->struct_mutex);
		10039	intel_enable_gt_powersave(dev);
		10040	mutex_unlock(&dev->struct_mutex);
2342	Serge	10041	}
		10042
3031	serge	10043	void intel_modeset_init(struct drm_device *dev)
2330	Serge	10044	{
3031	serge	10045	struct drm_i915_private *dev_priv = dev->dev_private;
3746	Serge	10046	int i, j, ret;
2330	Serge	10047
3031	serge	10048	drm_mode_config_init(dev);
2330	Serge	10049
3031	serge	10050	dev->mode_config.min_width = 0;
		10051	dev->mode_config.min_height = 0;
2330	Serge	10052
3031	serge	10053	dev->mode_config.preferred_depth = 24;
		10054	dev->mode_config.prefer_shadow = 1;
2330	Serge	10055
3031	serge	10056	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	10057
3031	serge	10058	intel_init_quirks(dev);
2330	Serge	10059
3031	serge	10060	intel_init_pm(dev);
2330	Serge	10061
3746	Serge	10062	if (INTEL_INFO(dev)->num_pipes == 0)
		10063	return;
		10064
3031	serge	10065	intel_init_display(dev);
2330	Serge	10066
3031	serge	10067	if (IS_GEN2(dev)) {
		10068	dev->mode_config.max_width = 2048;
		10069	dev->mode_config.max_height = 2048;
		10070	} else if (IS_GEN3(dev)) {
		10071	dev->mode_config.max_width = 4096;
		10072	dev->mode_config.max_height = 4096;
		10073	} else {
		10074	dev->mode_config.max_width = 8192;
		10075	dev->mode_config.max_height = 8192;
		10076	}
3480	Serge	10077	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
2330	Serge	10078
3031	serge	10079	DRM_DEBUG_KMS("%d display pipe%s available.\n",
3746	Serge	10080	INTEL_INFO(dev)->num_pipes,
		10081	INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
2330	Serge	10082
4104	Serge	10083	for_each_pipe(i) {
3031	serge	10084	intel_crtc_init(dev, i);
3746	Serge	10085	for (j = 0; j < dev_priv->num_plane; j++) {
		10086	ret = intel_plane_init(dev, i, j);
3031	serge	10087	if (ret)
4104	Serge	10088	DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
		10089	pipe_name(i), sprite_name(i, j), ret);
3746	Serge	10090	}
2330	Serge	10091	}
		10092
3243	Serge	10093	intel_cpu_pll_init(dev);
4104	Serge	10094	intel_shared_dpll_init(dev);
2330	Serge	10095
3031	serge	10096	/* Just disable it once at startup */
		10097	i915_disable_vga(dev);
		10098	intel_setup_outputs(dev);
3480	Serge	10099
		10100	/* Just in case the BIOS is doing something questionable. */
		10101	intel_disable_fbc(dev);
3031	serge	10102	}
2330	Serge	10103
3031	serge	10104	static void
		10105	intel_connector_break_all_links(struct intel_connector *connector)
		10106	{
		10107	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10108	connector->base.encoder = NULL;
		10109	connector->encoder->connectors_active = false;
		10110	connector->encoder->base.crtc = NULL;
2330	Serge	10111	}
		10112
3031	serge	10113	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	10114	{
3031	serge	10115	struct intel_connector *connector;
		10116	struct drm_connector *crt = NULL;
		10117	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	10118
3031	serge	10119	/* We can't just switch on the pipe A, we need to set things up with a
		10120	* proper mode and output configuration. As a gross hack, enable pipe A
		10121	* by enabling the load detect pipe once. */
		10122	list_for_each_entry(connector,
		10123	&dev->mode_config.connector_list,
		10124	base.head) {
		10125	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		10126	crt = &connector->base;
		10127	break;
2330	Serge	10128	}
		10129	}
		10130
3031	serge	10131	if (!crt)
		10132	return;
2330	Serge	10133
3031	serge	10134	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		10135	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	10136
		10137
		10138	}
		10139
3031	serge	10140	static bool
		10141	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	10142	{
3746	Serge	10143	struct drm_device *dev = crtc->base.dev;
		10144	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10145	u32 reg, val;
2327	Serge	10146
3746	Serge	10147	if (INTEL_INFO(dev)->num_pipes == 1)
3031	serge	10148	return true;
2327	Serge	10149
3031	serge	10150	reg = DSPCNTR(!crtc->plane);
		10151	val = I915_READ(reg);
2327	Serge	10152
3031	serge	10153	if ((val & DISPLAY_PLANE_ENABLE) &&
		10154	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		10155	return false;
2327	Serge	10156
3031	serge	10157	return true;
2327	Serge	10158	}
		10159
3031	serge	10160	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	10161	{
3031	serge	10162	struct drm_device *dev = crtc->base.dev;
2327	Serge	10163	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10164	u32 reg;
2327	Serge	10165
3031	serge	10166	/* Clear any frame start delays used for debugging left by the BIOS */
3746	Serge	10167	reg = PIPECONF(crtc->config.cpu_transcoder);
3031	serge	10168	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	10169
3031	serge	10170	/* We need to sanitize the plane -> pipe mapping first because this will
		10171	* disable the crtc (and hence change the state) if it is wrong. Note
		10172	* that gen4+ has a fixed plane -> pipe mapping. */
		10173	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		10174	struct intel_connector *connector;
		10175	bool plane;
2327	Serge	10176
3031	serge	10177	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		10178	crtc->base.base.id);
2327	Serge	10179
3031	serge	10180	/* Pipe has the wrong plane attached and the plane is active.
		10181	* Temporarily change the plane mapping and disable everything
		10182	* ... */
		10183	plane = crtc->plane;
		10184	crtc->plane = !plane;
		10185	dev_priv->display.crtc_disable(&crtc->base);
		10186	crtc->plane = plane;
2342	Serge	10187
3031	serge	10188	/* ... and break all links. */
		10189	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10190	base.head) {
		10191	if (connector->encoder->base.crtc != &crtc->base)
		10192	continue;
2327	Serge	10193
3031	serge	10194	intel_connector_break_all_links(connector);
		10195	}
2327	Serge	10196
3031	serge	10197	WARN_ON(crtc->active);
		10198	crtc->base.enabled = false;
		10199	}
2327	Serge	10200
3031	serge	10201	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		10202	crtc->pipe == PIPE_A && !crtc->active) {
		10203	/* BIOS forgot to enable pipe A, this mostly happens after
		10204	* resume. Force-enable the pipe to fix this, the update_dpms
		10205	* call below we restore the pipe to the right state, but leave
		10206	* the required bits on. */
		10207	intel_enable_pipe_a(dev);
		10208	}
2327	Serge	10209
3031	serge	10210	/* Adjust the state of the output pipe according to whether we
		10211	* have active connectors/encoders. */
		10212	intel_crtc_update_dpms(&crtc->base);
2327	Serge	10213
3031	serge	10214	if (crtc->active != crtc->base.enabled) {
		10215	struct intel_encoder *encoder;
2327	Serge	10216
3031	serge	10217	/* This can happen either due to bugs in the get_hw_state
		10218	* functions or because the pipe is force-enabled due to the
		10219	* pipe A quirk. */
		10220	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		10221	crtc->base.base.id,
		10222	crtc->base.enabled ? "enabled" : "disabled",
		10223	crtc->active ? "enabled" : "disabled");
2327	Serge	10224
3031	serge	10225	crtc->base.enabled = crtc->active;
2327	Serge	10226
3031	serge	10227	/* Because we only establish the connector -> encoder ->
		10228	* crtc links if something is active, this means the
		10229	* crtc is now deactivated. Break the links. connector
		10230	* -> encoder links are only establish when things are
		10231	* actually up, hence no need to break them. */
		10232	WARN_ON(crtc->active);
2327	Serge	10233
3031	serge	10234	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		10235	WARN_ON(encoder->connectors_active);
		10236	encoder->base.crtc = NULL;
		10237	}
		10238	}
2327	Serge	10239	}
		10240
3031	serge	10241	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	10242	{
3031	serge	10243	struct intel_connector *connector;
		10244	struct drm_device *dev = encoder->base.dev;
2327	Serge	10245
3031	serge	10246	/* We need to check both for a crtc link (meaning that the
		10247	* encoder is active and trying to read from a pipe) and the
		10248	* pipe itself being active. */
		10249	bool has_active_crtc = encoder->base.crtc &&
		10250	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	10251
3031	serge	10252	if (encoder->connectors_active && !has_active_crtc) {
		10253	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		10254	encoder->base.base.id,
		10255	drm_get_encoder_name(&encoder->base));
2327	Serge	10256
3031	serge	10257	/* Connector is active, but has no active pipe. This is
		10258	* fallout from our resume register restoring. Disable
		10259	* the encoder manually again. */
		10260	if (encoder->base.crtc) {
		10261	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		10262	encoder->base.base.id,
		10263	drm_get_encoder_name(&encoder->base));
		10264	encoder->disable(encoder);
		10265	}
2327	Serge	10266
3031	serge	10267	/* Inconsistent output/port/pipe state happens presumably due to
		10268	* a bug in one of the get_hw_state functions. Or someplace else
		10269	* in our code, like the register restore mess on resume. Clamp
		10270	* things to off as a safer default. */
		10271	list_for_each_entry(connector,
		10272	&dev->mode_config.connector_list,
		10273	base.head) {
		10274	if (connector->encoder != encoder)
		10275	continue;
2327	Serge	10276
3031	serge	10277	intel_connector_break_all_links(connector);
		10278	}
		10279	}
		10280	/* Enabled encoders without active connectors will be fixed in
		10281	* the crtc fixup. */
2327	Serge	10282	}
		10283
3746	Serge	10284	void i915_redisable_vga(struct drm_device *dev)
		10285	{
		10286	struct drm_i915_private *dev_priv = dev->dev_private;
		10287	u32 vga_reg = i915_vgacntrl_reg(dev);
		10288
4104	Serge	10289	/* This function can be called both from intel_modeset_setup_hw_state or
		10290	* at a very early point in our resume sequence, where the power well
		10291	* structures are not yet restored. Since this function is at a very
		10292	* paranoid "someone might have enabled VGA while we were not looking"
		10293	* level, just check if the power well is enabled instead of trying to
		10294	* follow the "don't touch the power well if we don't need it" policy
		10295	* the rest of the driver uses. */
		10296	if (HAS_POWER_WELL(dev) &&
		10297	(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
		10298	return;
		10299
3746	Serge	10300	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		10301	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
		10302	i915_disable_vga(dev);
		10303	}
		10304	}
		10305
4104	Serge	10306	static void intel_modeset_readout_hw_state(struct drm_device *dev)
2332	Serge	10307	{
		10308	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10309	enum pipe pipe;
		10310	struct intel_crtc *crtc;
		10311	struct intel_encoder *encoder;
		10312	struct intel_connector *connector;
4104	Serge	10313	int i;
2327	Serge	10314
3746	Serge	10315	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10316	base.head) {
		10317	memset(&crtc->config, 0, sizeof(crtc->config));
2327	Serge	10318
3746	Serge	10319	crtc->active = dev_priv->display.get_pipe_config(crtc,
		10320	&crtc->config);
2327	Serge	10321
3031	serge	10322	crtc->base.enabled = crtc->active;
2330	Serge	10323
3031	serge	10324	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		10325	crtc->base.base.id,
		10326	crtc->active ? "enabled" : "disabled");
2339	Serge	10327	}
2332	Serge	10328
4104	Serge	10329	/* FIXME: Smash this into the new shared dpll infrastructure. */
3480	Serge	10330	if (HAS_DDI(dev))
3243	Serge	10331	intel_ddi_setup_hw_pll_state(dev);
		10332
4104	Serge	10333	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10334	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10335
		10336	pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		10337	pll->active = 0;
		10338	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10339	base.head) {
		10340	if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
		10341	pll->active++;
		10342	}
		10343	pll->refcount = pll->active;
		10344
		10345	DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
		10346	pll->name, pll->refcount, pll->on);
		10347	}
		10348
3031	serge	10349	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10350	base.head) {
		10351	pipe = 0;
2332	Serge	10352
3031	serge	10353	if (encoder->get_hw_state(encoder, &pipe)) {
4104	Serge	10354	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10355	encoder->base.crtc = &crtc->base;
		10356	if (encoder->get_config)
		10357	encoder->get_config(encoder, &crtc->config);
3031	serge	10358	} else {
		10359	encoder->base.crtc = NULL;
		10360	}
2332	Serge	10361
3031	serge	10362	encoder->connectors_active = false;
		10363	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		10364	encoder->base.base.id,
		10365	drm_get_encoder_name(&encoder->base),
		10366	encoder->base.crtc ? "enabled" : "disabled",
		10367	pipe);
		10368	}
2332	Serge	10369
4104	Serge	10370	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10371	base.head) {
		10372	if (!crtc->active)
		10373	continue;
		10374	if (dev_priv->display.get_clock)
		10375	dev_priv->display.get_clock(crtc,
		10376	&crtc->config);
		10377	}
		10378
3031	serge	10379	list_for_each_entry(connector, &dev->mode_config.connector_list,
		10380	base.head) {
		10381	if (connector->get_hw_state(connector)) {
		10382	connector->base.dpms = DRM_MODE_DPMS_ON;
		10383	connector->encoder->connectors_active = true;
		10384	connector->base.encoder = &connector->encoder->base;
		10385	} else {
		10386	connector->base.dpms = DRM_MODE_DPMS_OFF;
		10387	connector->base.encoder = NULL;
		10388	}
		10389	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		10390	connector->base.base.id,
		10391	drm_get_connector_name(&connector->base),
		10392	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	10393	}
4104	Serge	10394	}
2332	Serge	10395
4104	Serge	10396	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		10397	* and i915 state tracking structures. */
		10398	void intel_modeset_setup_hw_state(struct drm_device *dev,
		10399	bool force_restore)
		10400	{
		10401	struct drm_i915_private *dev_priv = dev->dev_private;
		10402	enum pipe pipe;
		10403	struct drm_plane *plane;
		10404	struct intel_crtc *crtc;
		10405	struct intel_encoder *encoder;
		10406	int i;
		10407
		10408	intel_modeset_readout_hw_state(dev);
		10409
		10410	/*
		10411	* Now that we have the config, copy it to each CRTC struct
		10412	* Note that this could go away if we move to using crtc_config
		10413	* checking everywhere.
		10414	*/
		10415	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		10416	base.head) {
		10417	if (crtc->active && i915_fastboot) {
		10418	intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
		10419
		10420	DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
		10421	crtc->base.base.id);
		10422	drm_mode_debug_printmodeline(&crtc->base.mode);
		10423	}
		10424	}
		10425
3031	serge	10426	/* HW state is read out, now we need to sanitize this mess. */
		10427	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		10428	base.head) {
		10429	intel_sanitize_encoder(encoder);
2332	Serge	10430	}
		10431
3031	serge	10432	for_each_pipe(pipe) {
		10433	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		10434	intel_sanitize_crtc(crtc);
4104	Serge	10435	intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
2332	Serge	10436	}
		10437
4104	Serge	10438	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		10439	struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		10440
		10441	if (!pll->on \|\| pll->active)
		10442	continue;
		10443
		10444	DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
		10445
		10446	pll->disable(dev_priv, pll);
		10447	pll->on = false;
		10448	}
		10449
3243	Serge	10450	if (force_restore) {
3746	Serge	10451	/*
		10452	* We need to use raw interfaces for restoring state to avoid
		10453	* checking (bogus) intermediate states.
		10454	*/
3243	Serge	10455	for_each_pipe(pipe) {
3746	Serge	10456	struct drm_crtc *crtc =
		10457	dev_priv->pipe_to_crtc_mapping[pipe];
		10458
		10459	__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
		10460	crtc->fb);
3243	Serge	10461	}
3746	Serge	10462	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
		10463	intel_plane_restore(plane);
3243	Serge	10464
3746	Serge	10465	i915_redisable_vga(dev);
3243	Serge	10466	} else {
3031	serge	10467	intel_modeset_update_staged_output_state(dev);
3243	Serge	10468	}
2332	Serge	10469
3031	serge	10470	intel_modeset_check_state(dev);
3243	Serge	10471
		10472	drm_mode_config_reset(dev);
2332	Serge	10473	}
		10474
3031	serge	10475	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	10476	{
3031	serge	10477	intel_modeset_init_hw(dev);
2330	Serge	10478
3031	serge	10479	// intel_setup_overlay(dev);
2330	Serge	10480
3243	Serge	10481	intel_modeset_setup_hw_state(dev, false);
2330	Serge	10482	}
		10483
3031	serge	10484	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	10485	{
3031	serge	10486	#if 0
		10487	struct drm_i915_private *dev_priv = dev->dev_private;
		10488	struct drm_crtc *crtc;
2327	Serge	10489
4104	Serge	10490	/*
		10491	* Interrupts and polling as the first thing to avoid creating havoc.
		10492	* Too much stuff here (turning of rps, connectors, ...) would
		10493	* experience fancy races otherwise.
		10494	*/
		10495	drm_irq_uninstall(dev);
		10496	cancel_work_sync(&dev_priv->hotplug_work);
		10497	/*
		10498	* Due to the hpd irq storm handling the hotplug work can re-arm the
		10499	* poll handlers. Hence disable polling after hpd handling is shut down.
		10500	*/
3031	serge	10501	// drm_kms_helper_poll_fini(dev);
4104	Serge	10502
3031	serge	10503	mutex_lock(&dev->struct_mutex);
2327	Serge	10504
3031	serge	10505	// intel_unregister_dsm_handler();
2327	Serge	10506
3031	serge	10507	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		10508	/* Skip inactive CRTCs */
		10509	if (!crtc->fb)
		10510	continue;
2342	Serge	10511
3031	serge	10512	intel_increase_pllclock(crtc);
		10513	}
2342	Serge	10514
3031	serge	10515	intel_disable_fbc(dev);
2342	Serge	10516
3031	serge	10517	intel_disable_gt_powersave(dev);
2342	Serge	10518
3031	serge	10519	ironlake_teardown_rc6(dev);
2327	Serge	10520
3031	serge	10521	mutex_unlock(&dev->struct_mutex);
2327	Serge	10522
4104	Serge	10523	/* flush any delayed tasks or pending work */
		10524	flush_scheduled_work();
2327	Serge	10525
4280	Serge	10526	/* destroy backlight, if any, before the connectors */
		10527	intel_panel_destroy_backlight(dev);
2327	Serge	10528
3031	serge	10529	drm_mode_config_cleanup(dev);
2327	Serge	10530	#endif
		10531	}
		10532
		10533	/*
3031	serge	10534	* Return which encoder is currently attached for connector.
2327	Serge	10535	*/
3031	serge	10536	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	10537	{
3031	serge	10538	return &intel_attached_encoder(connector)->base;
		10539	}
2327	Serge	10540
3031	serge	10541	void intel_connector_attach_encoder(struct intel_connector *connector,
		10542	struct intel_encoder *encoder)
		10543	{
		10544	connector->encoder = encoder;
		10545	drm_mode_connector_attach_encoder(&connector->base,
		10546	&encoder->base);
2327	Serge	10547	}
		10548
		10549	/*
3031	serge	10550	* set vga decode state - true == enable VGA decode
2327	Serge	10551	*/
3031	serge	10552	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	10553	{
2330	Serge	10554	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	10555	u16 gmch_ctrl;
2327	Serge	10556
3031	serge	10557	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		10558	if (state)
		10559	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	10560	else
3031	serge	10561	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		10562	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		10563	return 0;
2330	Serge	10564	}
		10565
3031	serge	10566	#ifdef CONFIG_DEBUG_FS
		10567	#include
2327	Serge	10568
3031	serge	10569	struct intel_display_error_state {
4104	Serge	10570
		10571	u32 power_well_driver;
		10572
		10573	int num_transcoders;
		10574
3031	serge	10575	struct intel_cursor_error_state {
		10576	u32 control;
		10577	u32 position;
		10578	u32 base;
		10579	u32 size;
		10580	} cursor[I915_MAX_PIPES];
2327	Serge	10581
3031	serge	10582	struct intel_pipe_error_state {
		10583	u32 source;
		10584	} pipe[I915_MAX_PIPES];
2327	Serge	10585
3031	serge	10586	struct intel_plane_error_state {
		10587	u32 control;
		10588	u32 stride;
		10589	u32 size;
		10590	u32 pos;
		10591	u32 addr;
		10592	u32 surface;
		10593	u32 tile_offset;
		10594	} plane[I915_MAX_PIPES];
4104	Serge	10595
		10596	struct intel_transcoder_error_state {
		10597	enum transcoder cpu_transcoder;
		10598
		10599	u32 conf;
		10600
		10601	u32 htotal;
		10602	u32 hblank;
		10603	u32 hsync;
		10604	u32 vtotal;
		10605	u32 vblank;
		10606	u32 vsync;
		10607	} transcoder[4];
3031	serge	10608	};
2327	Serge	10609
3031	serge	10610	struct intel_display_error_state *
		10611	intel_display_capture_error_state(struct drm_device *dev)
		10612	{
		10613	drm_i915_private_t *dev_priv = dev->dev_private;
		10614	struct intel_display_error_state *error;
4104	Serge	10615	int transcoders[] = {
		10616	TRANSCODER_A,
		10617	TRANSCODER_B,
		10618	TRANSCODER_C,
		10619	TRANSCODER_EDP,
		10620	};
3031	serge	10621	int i;
2327	Serge	10622
4104	Serge	10623	if (INTEL_INFO(dev)->num_pipes == 0)
		10624	return NULL;
		10625
3031	serge	10626	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		10627	if (error == NULL)
		10628	return NULL;
2327	Serge	10629
4104	Serge	10630	if (HAS_POWER_WELL(dev))
		10631	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
		10632
3031	serge	10633	for_each_pipe(i) {
3746	Serge	10634	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
3031	serge	10635	error->cursor[i].control = I915_READ(CURCNTR(i));
		10636	error->cursor[i].position = I915_READ(CURPOS(i));
		10637	error->cursor[i].base = I915_READ(CURBASE(i));
3746	Serge	10638	} else {
		10639	error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
		10640	error->cursor[i].position = I915_READ(CURPOS_IVB(i));
		10641	error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		10642	}
2327	Serge	10643
3031	serge	10644	error->plane[i].control = I915_READ(DSPCNTR(i));
		10645	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
3746	Serge	10646	if (INTEL_INFO(dev)->gen <= 3) {
3031	serge	10647	error->plane[i].size = I915_READ(DSPSIZE(i));
		10648	error->plane[i].pos = I915_READ(DSPPOS(i));
3746	Serge	10649	}
		10650	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3031	serge	10651	error->plane[i].addr = I915_READ(DSPADDR(i));
		10652	if (INTEL_INFO(dev)->gen >= 4) {
		10653	error->plane[i].surface = I915_READ(DSPSURF(i));
		10654	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		10655	}
2327	Serge	10656
3031	serge	10657	error->pipe[i].source = I915_READ(PIPESRC(i));
		10658	}
2327	Serge	10659
4104	Serge	10660	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
		10661	if (HAS_DDI(dev_priv->dev))
		10662	error->num_transcoders++; /* Account for eDP. */
		10663
		10664	for (i = 0; i < error->num_transcoders; i++) {
		10665	enum transcoder cpu_transcoder = transcoders[i];
		10666
		10667	error->transcoder[i].cpu_transcoder = cpu_transcoder;
		10668
		10669	error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		10670	error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		10671	error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		10672	error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		10673	error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		10674	error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		10675	error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
		10676	}
		10677
		10678	/* In the code above we read the registers without checking if the power
		10679	* well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
		10680	* prevent the next I915_WRITE from detecting it and printing an error
		10681	* message. */
		10682	intel_uncore_clear_errors(dev);
		10683
3031	serge	10684	return error;
2330	Serge	10685	}
2327	Serge	10686
4104	Serge	10687	#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
		10688
3031	serge	10689	void
4104	Serge	10690	intel_display_print_error_state(struct drm_i915_error_state_buf *m,
3031	serge	10691	struct drm_device *dev,
		10692	struct intel_display_error_state *error)
2332	Serge	10693	{
3031	serge	10694	int i;
2330	Serge	10695
4104	Serge	10696	if (!error)
		10697	return;
		10698
		10699	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
		10700	if (HAS_POWER_WELL(dev))
		10701	err_printf(m, "PWR_WELL_CTL2: %08x\n",
		10702	error->power_well_driver);
3031	serge	10703	for_each_pipe(i) {
4104	Serge	10704	err_printf(m, "Pipe [%d]:\n", i);
		10705	err_printf(m, " SRC: %08x\n", error->pipe[i].source);
2332	Serge	10706
4104	Serge	10707	err_printf(m, "Plane [%d]:\n", i);
		10708	err_printf(m, " CNTR: %08x\n", error->plane[i].control);
		10709	err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
3746	Serge	10710	if (INTEL_INFO(dev)->gen <= 3) {
4104	Serge	10711	err_printf(m, " SIZE: %08x\n", error->plane[i].size);
		10712	err_printf(m, " POS: %08x\n", error->plane[i].pos);
3746	Serge	10713	}
		10714	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
4104	Serge	10715	err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
3031	serge	10716	if (INTEL_INFO(dev)->gen >= 4) {
4104	Serge	10717	err_printf(m, " SURF: %08x\n", error->plane[i].surface);
		10718	err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
3031	serge	10719	}
2332	Serge	10720
4104	Serge	10721	err_printf(m, "Cursor [%d]:\n", i);
		10722	err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		10723	err_printf(m, " POS: %08x\n", error->cursor[i].position);
		10724	err_printf(m, " BASE: %08x\n", error->cursor[i].base);
3031	serge	10725	}
4104	Serge	10726
		10727	for (i = 0; i < error->num_transcoders; i++) {
		10728	err_printf(m, " CPU transcoder: %c\n",
		10729	transcoder_name(error->transcoder[i].cpu_transcoder));
		10730	err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
		10731	err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
		10732	err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
		10733	err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
		10734	err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
		10735	err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
		10736	err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
		10737	}
2327	Serge	10738	}
3031	serge	10739	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_display.c – Rev 4293