WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
		27	//#include
		28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
2327	Serge	33	//#include
2342	Serge	34	#include
3031	serge	35	#include
2327	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2327	Serge	38	#include "i915_drv.h"
2351	Serge	39	#include "i915_trace.h"
3031	serge	40	#include
		41	#include
		42	//#include
2327	Serge	43
		44	phys_addr_t get_bus_addr(void);
		45
		46	static inline __attribute__((const))
		47	bool is_power_of_2(unsigned long n)
		48	{
		49	return (n != 0 && ((n & (n - 1)) == 0));
		50	}
		51
2330	Serge	52	#define MAX_ERRNO 4095
		53
		54	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
		55
		56	static inline long IS_ERR(const void *ptr)
		57	{
		58	return IS_ERR_VALUE((unsigned long)ptr);
		59	}
		60
		61	static inline void *ERR_PTR(long error)
		62	{
		63	return (void *) error;
		64	}
		65
		66
2327	Serge	67	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
		68
2342	Serge	69	bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327	Serge	70	static void intel_increase_pllclock(struct drm_crtc *crtc);
3031	serge	71	//static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
2327	Serge	72
		73	typedef struct {
		74	/* given values */
		75	int n;
		76	int m1, m2;
		77	int p1, p2;
		78	/* derived values */
		79	int dot;
		80	int vco;
		81	int m;
		82	int p;
		83	} intel_clock_t;
		84
		85	typedef struct {
		86	int min, max;
		87	} intel_range_t;
		88
		89	typedef struct {
		90	int dot_limit;
		91	int p2_slow, p2_fast;
		92	} intel_p2_t;
		93
		94	#define INTEL_P2_NUM 2
		95	typedef struct intel_limit intel_limit_t;
		96	struct intel_limit {
		97	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		98	intel_p2_t p2;
		99	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,
3031	serge	100	int, int, intel_clock_t , intel_clock_t );
2327	Serge	101	};
		102
		103	/* FDI */
		104	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		105
		106	static bool
		107	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	108	int target, int refclk, intel_clock_t *match_clock,
		109	intel_clock_t *best_clock);
2327	Serge	110	static bool
		111	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	112	int target, int refclk, intel_clock_t *match_clock,
		113	intel_clock_t *best_clock);
2327	Serge	114
		115	static bool
		116	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	117	int target, int refclk, intel_clock_t *match_clock,
		118	intel_clock_t *best_clock);
2327	Serge	119	static bool
		120	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
3031	serge	121	int target, int refclk, intel_clock_t *match_clock,
		122	intel_clock_t *best_clock);
2327	Serge	123
3031	serge	124	static bool
		125	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		126	int target, int refclk, intel_clock_t *match_clock,
		127	intel_clock_t *best_clock);
		128
2327	Serge	129	static inline u32 /* units of 100MHz */
		130	intel_fdi_link_freq(struct drm_device *dev)
		131	{
		132	if (IS_GEN5(dev)) {
		133	struct drm_i915_private *dev_priv = dev->dev_private;
		134	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		135	} else
		136	return 27;
		137	}
		138
		139	static const intel_limit_t intel_limits_i8xx_dvo = {
		140	.dot = { .min = 25000, .max = 350000 },
		141	.vco = { .min = 930000, .max = 1400000 },
		142	.n = { .min = 3, .max = 16 },
		143	.m = { .min = 96, .max = 140 },
		144	.m1 = { .min = 18, .max = 26 },
		145	.m2 = { .min = 6, .max = 16 },
		146	.p = { .min = 4, .max = 128 },
		147	.p1 = { .min = 2, .max = 33 },
		148	.p2 = { .dot_limit = 165000,
		149	.p2_slow = 4, .p2_fast = 2 },
		150	.find_pll = intel_find_best_PLL,
		151	};
		152
		153	static const intel_limit_t intel_limits_i8xx_lvds = {
		154	.dot = { .min = 25000, .max = 350000 },
		155	.vco = { .min = 930000, .max = 1400000 },
		156	.n = { .min = 3, .max = 16 },
		157	.m = { .min = 96, .max = 140 },
		158	.m1 = { .min = 18, .max = 26 },
		159	.m2 = { .min = 6, .max = 16 },
		160	.p = { .min = 4, .max = 128 },
		161	.p1 = { .min = 1, .max = 6 },
		162	.p2 = { .dot_limit = 165000,
		163	.p2_slow = 14, .p2_fast = 7 },
		164	.find_pll = intel_find_best_PLL,
		165	};
		166
		167	static const intel_limit_t intel_limits_i9xx_sdvo = {
		168	.dot = { .min = 20000, .max = 400000 },
		169	.vco = { .min = 1400000, .max = 2800000 },
		170	.n = { .min = 1, .max = 6 },
		171	.m = { .min = 70, .max = 120 },
		172	.m1 = { .min = 10, .max = 22 },
		173	.m2 = { .min = 5, .max = 9 },
		174	.p = { .min = 5, .max = 80 },
		175	.p1 = { .min = 1, .max = 8 },
		176	.p2 = { .dot_limit = 200000,
		177	.p2_slow = 10, .p2_fast = 5 },
		178	.find_pll = intel_find_best_PLL,
		179	};
		180
		181	static const intel_limit_t intel_limits_i9xx_lvds = {
		182	.dot = { .min = 20000, .max = 400000 },
		183	.vco = { .min = 1400000, .max = 2800000 },
		184	.n = { .min = 1, .max = 6 },
		185	.m = { .min = 70, .max = 120 },
		186	.m1 = { .min = 10, .max = 22 },
		187	.m2 = { .min = 5, .max = 9 },
		188	.p = { .min = 7, .max = 98 },
		189	.p1 = { .min = 1, .max = 8 },
		190	.p2 = { .dot_limit = 112000,
		191	.p2_slow = 14, .p2_fast = 7 },
		192	.find_pll = intel_find_best_PLL,
		193	};
		194
		195
		196	static const intel_limit_t intel_limits_g4x_sdvo = {
		197	.dot = { .min = 25000, .max = 270000 },
		198	.vco = { .min = 1750000, .max = 3500000},
		199	.n = { .min = 1, .max = 4 },
		200	.m = { .min = 104, .max = 138 },
		201	.m1 = { .min = 17, .max = 23 },
		202	.m2 = { .min = 5, .max = 11 },
		203	.p = { .min = 10, .max = 30 },
		204	.p1 = { .min = 1, .max = 3},
		205	.p2 = { .dot_limit = 270000,
		206	.p2_slow = 10,
		207	.p2_fast = 10
		208	},
		209	.find_pll = intel_g4x_find_best_PLL,
		210	};
		211
		212	static const intel_limit_t intel_limits_g4x_hdmi = {
		213	.dot = { .min = 22000, .max = 400000 },
		214	.vco = { .min = 1750000, .max = 3500000},
		215	.n = { .min = 1, .max = 4 },
		216	.m = { .min = 104, .max = 138 },
		217	.m1 = { .min = 16, .max = 23 },
		218	.m2 = { .min = 5, .max = 11 },
		219	.p = { .min = 5, .max = 80 },
		220	.p1 = { .min = 1, .max = 8},
		221	.p2 = { .dot_limit = 165000,
		222	.p2_slow = 10, .p2_fast = 5 },
		223	.find_pll = intel_g4x_find_best_PLL,
		224	};
		225
		226	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		227	.dot = { .min = 20000, .max = 115000 },
		228	.vco = { .min = 1750000, .max = 3500000 },
		229	.n = { .min = 1, .max = 3 },
		230	.m = { .min = 104, .max = 138 },
		231	.m1 = { .min = 17, .max = 23 },
		232	.m2 = { .min = 5, .max = 11 },
		233	.p = { .min = 28, .max = 112 },
		234	.p1 = { .min = 2, .max = 8 },
		235	.p2 = { .dot_limit = 0,
		236	.p2_slow = 14, .p2_fast = 14
		237	},
		238	.find_pll = intel_g4x_find_best_PLL,
		239	};
		240
		241	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		242	.dot = { .min = 80000, .max = 224000 },
		243	.vco = { .min = 1750000, .max = 3500000 },
		244	.n = { .min = 1, .max = 3 },
		245	.m = { .min = 104, .max = 138 },
		246	.m1 = { .min = 17, .max = 23 },
		247	.m2 = { .min = 5, .max = 11 },
		248	.p = { .min = 14, .max = 42 },
		249	.p1 = { .min = 2, .max = 6 },
		250	.p2 = { .dot_limit = 0,
		251	.p2_slow = 7, .p2_fast = 7
		252	},
		253	.find_pll = intel_g4x_find_best_PLL,
		254	};
		255
		256	static const intel_limit_t intel_limits_g4x_display_port = {
		257	.dot = { .min = 161670, .max = 227000 },
		258	.vco = { .min = 1750000, .max = 3500000},
		259	.n = { .min = 1, .max = 2 },
		260	.m = { .min = 97, .max = 108 },
		261	.m1 = { .min = 0x10, .max = 0x12 },
		262	.m2 = { .min = 0x05, .max = 0x06 },
		263	.p = { .min = 10, .max = 20 },
		264	.p1 = { .min = 1, .max = 2},
		265	.p2 = { .dot_limit = 0,
		266	.p2_slow = 10, .p2_fast = 10 },
		267	.find_pll = intel_find_pll_g4x_dp,
		268	};
		269
		270	static const intel_limit_t intel_limits_pineview_sdvo = {
		271	.dot = { .min = 20000, .max = 400000},
		272	.vco = { .min = 1700000, .max = 3500000 },
		273	/* Pineview's Ncounter is a ring counter */
		274	.n = { .min = 3, .max = 6 },
		275	.m = { .min = 2, .max = 256 },
		276	/* Pineview only has one combined m divider, which we treat as m2. */
		277	.m1 = { .min = 0, .max = 0 },
		278	.m2 = { .min = 0, .max = 254 },
		279	.p = { .min = 5, .max = 80 },
		280	.p1 = { .min = 1, .max = 8 },
		281	.p2 = { .dot_limit = 200000,
		282	.p2_slow = 10, .p2_fast = 5 },
		283	.find_pll = intel_find_best_PLL,
		284	};
		285
		286	static const intel_limit_t intel_limits_pineview_lvds = {
		287	.dot = { .min = 20000, .max = 400000 },
		288	.vco = { .min = 1700000, .max = 3500000 },
		289	.n = { .min = 3, .max = 6 },
		290	.m = { .min = 2, .max = 256 },
		291	.m1 = { .min = 0, .max = 0 },
		292	.m2 = { .min = 0, .max = 254 },
		293	.p = { .min = 7, .max = 112 },
		294	.p1 = { .min = 1, .max = 8 },
		295	.p2 = { .dot_limit = 112000,
		296	.p2_slow = 14, .p2_fast = 14 },
		297	.find_pll = intel_find_best_PLL,
		298	};
		299
		300	/* Ironlake / Sandybridge
		301	*
		302	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		303	* the range value for them is (actual_value - 2).
		304	*/
		305	static const intel_limit_t intel_limits_ironlake_dac = {
		306	.dot = { .min = 25000, .max = 350000 },
		307	.vco = { .min = 1760000, .max = 3510000 },
		308	.n = { .min = 1, .max = 5 },
		309	.m = { .min = 79, .max = 127 },
		310	.m1 = { .min = 12, .max = 22 },
		311	.m2 = { .min = 5, .max = 9 },
		312	.p = { .min = 5, .max = 80 },
		313	.p1 = { .min = 1, .max = 8 },
		314	.p2 = { .dot_limit = 225000,
		315	.p2_slow = 10, .p2_fast = 5 },
		316	.find_pll = intel_g4x_find_best_PLL,
		317	};
		318
		319	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		320	.dot = { .min = 25000, .max = 350000 },
		321	.vco = { .min = 1760000, .max = 3510000 },
		322	.n = { .min = 1, .max = 3 },
		323	.m = { .min = 79, .max = 118 },
		324	.m1 = { .min = 12, .max = 22 },
		325	.m2 = { .min = 5, .max = 9 },
		326	.p = { .min = 28, .max = 112 },
		327	.p1 = { .min = 2, .max = 8 },
		328	.p2 = { .dot_limit = 225000,
		329	.p2_slow = 14, .p2_fast = 14 },
		330	.find_pll = intel_g4x_find_best_PLL,
		331	};
		332
		333	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		334	.dot = { .min = 25000, .max = 350000 },
		335	.vco = { .min = 1760000, .max = 3510000 },
		336	.n = { .min = 1, .max = 3 },
		337	.m = { .min = 79, .max = 127 },
		338	.m1 = { .min = 12, .max = 22 },
		339	.m2 = { .min = 5, .max = 9 },
		340	.p = { .min = 14, .max = 56 },
		341	.p1 = { .min = 2, .max = 8 },
		342	.p2 = { .dot_limit = 225000,
		343	.p2_slow = 7, .p2_fast = 7 },
		344	.find_pll = intel_g4x_find_best_PLL,
		345	};
		346
		347	/* LVDS 100mhz refclk limits. */
		348	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		349	.dot = { .min = 25000, .max = 350000 },
		350	.vco = { .min = 1760000, .max = 3510000 },
		351	.n = { .min = 1, .max = 2 },
		352	.m = { .min = 79, .max = 126 },
		353	.m1 = { .min = 12, .max = 22 },
		354	.m2 = { .min = 5, .max = 9 },
		355	.p = { .min = 28, .max = 112 },
2342	Serge	356	.p1 = { .min = 2, .max = 8 },
2327	Serge	357	.p2 = { .dot_limit = 225000,
		358	.p2_slow = 14, .p2_fast = 14 },
		359	.find_pll = intel_g4x_find_best_PLL,
		360	};
		361
		362	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		363	.dot = { .min = 25000, .max = 350000 },
		364	.vco = { .min = 1760000, .max = 3510000 },
		365	.n = { .min = 1, .max = 3 },
		366	.m = { .min = 79, .max = 126 },
		367	.m1 = { .min = 12, .max = 22 },
		368	.m2 = { .min = 5, .max = 9 },
		369	.p = { .min = 14, .max = 42 },
2342	Serge	370	.p1 = { .min = 2, .max = 6 },
2327	Serge	371	.p2 = { .dot_limit = 225000,
		372	.p2_slow = 7, .p2_fast = 7 },
		373	.find_pll = intel_g4x_find_best_PLL,
		374	};
		375
		376	static const intel_limit_t intel_limits_ironlake_display_port = {
		377	.dot = { .min = 25000, .max = 350000 },
		378	.vco = { .min = 1760000, .max = 3510000},
		379	.n = { .min = 1, .max = 2 },
		380	.m = { .min = 81, .max = 90 },
		381	.m1 = { .min = 12, .max = 22 },
		382	.m2 = { .min = 5, .max = 9 },
		383	.p = { .min = 10, .max = 20 },
		384	.p1 = { .min = 1, .max = 2},
		385	.p2 = { .dot_limit = 0,
		386	.p2_slow = 10, .p2_fast = 10 },
		387	.find_pll = intel_find_pll_ironlake_dp,
		388	};
		389
3031	serge	390	static const intel_limit_t intel_limits_vlv_dac = {
		391	.dot = { .min = 25000, .max = 270000 },
		392	.vco = { .min = 4000000, .max = 6000000 },
		393	.n = { .min = 1, .max = 7 },
		394	.m = { .min = 22, .max = 450 }, /* guess */
		395	.m1 = { .min = 2, .max = 3 },
		396	.m2 = { .min = 11, .max = 156 },
		397	.p = { .min = 10, .max = 30 },
		398	.p1 = { .min = 2, .max = 3 },
		399	.p2 = { .dot_limit = 270000,
		400	.p2_slow = 2, .p2_fast = 20 },
		401	.find_pll = intel_vlv_find_best_pll,
		402	};
		403
		404	static const intel_limit_t intel_limits_vlv_hdmi = {
		405	.dot = { .min = 20000, .max = 165000 },
		406	.vco = { .min = 5994000, .max = 4000000 },
		407	.n = { .min = 1, .max = 7 },
		408	.m = { .min = 60, .max = 300 }, /* guess */
		409	.m1 = { .min = 2, .max = 3 },
		410	.m2 = { .min = 11, .max = 156 },
		411	.p = { .min = 10, .max = 30 },
		412	.p1 = { .min = 2, .max = 3 },
		413	.p2 = { .dot_limit = 270000,
		414	.p2_slow = 2, .p2_fast = 20 },
		415	.find_pll = intel_vlv_find_best_pll,
		416	};
		417
		418	static const intel_limit_t intel_limits_vlv_dp = {
		419	.dot = { .min = 162000, .max = 270000 },
		420	.vco = { .min = 5994000, .max = 4000000 },
		421	.n = { .min = 1, .max = 7 },
		422	.m = { .min = 60, .max = 300 }, /* guess */
		423	.m1 = { .min = 2, .max = 3 },
		424	.m2 = { .min = 11, .max = 156 },
		425	.p = { .min = 10, .max = 30 },
		426	.p1 = { .min = 2, .max = 3 },
		427	.p2 = { .dot_limit = 270000,
		428	.p2_slow = 2, .p2_fast = 20 },
		429	.find_pll = intel_vlv_find_best_pll,
		430	};
		431
		432	u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
		433	{
		434	unsigned long flags;
		435	u32 val = 0;
		436
		437	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		438	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		439	DRM_ERROR("DPIO idle wait timed out\n");
		440	goto out_unlock;
		441	}
		442
		443	I915_WRITE(DPIO_REG, reg);
		444	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_READ \| DPIO_PORTID \|
		445	DPIO_BYTE);
		446	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		447	DRM_ERROR("DPIO read wait timed out\n");
		448	goto out_unlock;
		449	}
		450	val = I915_READ(DPIO_DATA);
		451
		452	out_unlock:
		453	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		454	return val;
		455	}
		456
		457	static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
		458	u32 val)
		459	{
		460	unsigned long flags;
		461
		462	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		463	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		464	DRM_ERROR("DPIO idle wait timed out\n");
		465	goto out_unlock;
		466	}
		467
		468	I915_WRITE(DPIO_DATA, val);
		469	I915_WRITE(DPIO_REG, reg);
		470	I915_WRITE(DPIO_PKT, DPIO_RID \| DPIO_OP_WRITE \| DPIO_PORTID \|
		471	DPIO_BYTE);
		472	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
		473	DRM_ERROR("DPIO write wait timed out\n");
		474
		475	out_unlock:
		476	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		477	}
		478
		479	static void vlv_init_dpio(struct drm_device *dev)
		480	{
		481	struct drm_i915_private *dev_priv = dev->dev_private;
		482
		483	/* Reset the DPIO config */
		484	I915_WRITE(DPIO_CTL, 0);
		485	POSTING_READ(DPIO_CTL);
		486	I915_WRITE(DPIO_CTL, 1);
		487	POSTING_READ(DPIO_CTL);
		488	}
		489
		490	static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
		491	{
		492	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
		493	return 1;
		494	}
		495
		496	static const struct dmi_system_id intel_dual_link_lvds[] = {
		497	{
		498	.callback = intel_dual_link_lvds_callback,
		499	.ident = "Apple MacBook Pro (Core i5/i7 Series)",
		500	.matches = {
		501	DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
		502	DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
		503	},
		504	},
		505	{ } /* terminating entry */
		506	};
		507
		508	static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
		509	unsigned int reg)
		510	{
		511	unsigned int val;
		512
		513	/* use the module option value if specified */
		514	if (i915_lvds_channel_mode > 0)
		515	return i915_lvds_channel_mode == 2;
		516
		517	// if (dmi_check_system(intel_dual_link_lvds))
		518	// return true;
		519
		520	if (dev_priv->lvds_val)
		521	val = dev_priv->lvds_val;
		522	else {
		523	/* BIOS should set the proper LVDS register value at boot, but
		524	* in reality, it doesn't set the value when the lid is closed;
		525	* we need to check "the value to be set" in VBT when LVDS
		526	* register is uninitialized.
		527	*/
		528	val = I915_READ(reg);
		529	if (!(val & ~(LVDS_PIPE_MASK \| LVDS_DETECTED)))
		530	val = dev_priv->bios_lvds_val;
		531	dev_priv->lvds_val = val;
		532	}
		533	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
		534	}
		535
2327	Serge	536	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		537	int refclk)
		538	{
		539	struct drm_device *dev = crtc->dev;
		540	struct drm_i915_private *dev_priv = dev->dev_private;
		541	const intel_limit_t *limit;
		542
		543	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3031	serge	544	if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
2327	Serge	545	/* LVDS dual channel */
		546	if (refclk == 100000)
		547	limit = &intel_limits_ironlake_dual_lvds_100m;
		548	else
		549	limit = &intel_limits_ironlake_dual_lvds;
		550	} else {
		551	if (refclk == 100000)
		552	limit = &intel_limits_ironlake_single_lvds_100m;
		553	else
		554	limit = &intel_limits_ironlake_single_lvds;
		555	}
		556	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		557	HAS_eDP)
		558	limit = &intel_limits_ironlake_display_port;
		559	else
		560	limit = &intel_limits_ironlake_dac;
		561
		562	return limit;
		563	}
		564
		565	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		566	{
		567	struct drm_device *dev = crtc->dev;
		568	struct drm_i915_private *dev_priv = dev->dev_private;
		569	const intel_limit_t *limit;
		570
		571	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3031	serge	572	if (is_dual_link_lvds(dev_priv, LVDS))
2327	Serge	573	/* LVDS with dual channel */
		574	limit = &intel_limits_g4x_dual_channel_lvds;
		575	else
		576	/* LVDS with dual channel */
		577	limit = &intel_limits_g4x_single_channel_lvds;
		578	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		579	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		580	limit = &intel_limits_g4x_hdmi;
		581	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		582	limit = &intel_limits_g4x_sdvo;
2342	Serge	583	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2327	Serge	584	limit = &intel_limits_g4x_display_port;
		585	} else /* The option is for other outputs */
		586	limit = &intel_limits_i9xx_sdvo;
		587
		588	return limit;
		589	}
		590
		591	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		592	{
		593	struct drm_device *dev = crtc->dev;
		594	const intel_limit_t *limit;
		595
		596	if (HAS_PCH_SPLIT(dev))
		597	limit = intel_ironlake_limit(crtc, refclk);
		598	else if (IS_G4X(dev)) {
		599	limit = intel_g4x_limit(crtc);
		600	} else if (IS_PINEVIEW(dev)) {
		601	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		602	limit = &intel_limits_pineview_lvds;
		603	else
		604	limit = &intel_limits_pineview_sdvo;
3031	serge	605	} else if (IS_VALLEYVIEW(dev)) {
		606	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
		607	limit = &intel_limits_vlv_dac;
		608	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
		609	limit = &intel_limits_vlv_hdmi;
		610	else
		611	limit = &intel_limits_vlv_dp;
2327	Serge	612	} else if (!IS_GEN2(dev)) {
		613	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		614	limit = &intel_limits_i9xx_lvds;
		615	else
		616	limit = &intel_limits_i9xx_sdvo;
		617	} else {
		618	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		619	limit = &intel_limits_i8xx_lvds;
		620	else
		621	limit = &intel_limits_i8xx_dvo;
		622	}
		623	return limit;
		624	}
		625
		626	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		627	static void pineview_clock(int refclk, intel_clock_t *clock)
		628	{
		629	clock->m = clock->m2 + 2;
		630	clock->p = clock->p1 * clock->p2;
		631	clock->vco = refclk * clock->m / clock->n;
		632	clock->dot = clock->vco / clock->p;
		633	}
		634
		635	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
		636	{
		637	if (IS_PINEVIEW(dev)) {
		638	pineview_clock(refclk, clock);
		639	return;
		640	}
		641	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
		642	clock->p = clock->p1 * clock->p2;
		643	clock->vco = refclk * clock->m / (clock->n + 2);
		644	clock->dot = clock->vco / clock->p;
		645	}
		646
		647	/**
		648	* Returns whether any output on the specified pipe is of the specified type
		649	*/
		650	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		651	{
		652	struct drm_device *dev = crtc->dev;
		653	struct intel_encoder *encoder;
		654
3031	serge	655	for_each_encoder_on_crtc(dev, crtc, encoder)
		656	if (encoder->type == type)
2327	Serge	657	return true;
		658
		659	return false;
		660	}
		661
		662	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		663	/**
		664	* Returns whether the given set of divisors are valid for a given refclk with
		665	* the given connectors.
		666	*/
		667
		668	static bool intel_PLL_is_valid(struct drm_device *dev,
		669	const intel_limit_t *limit,
		670	const intel_clock_t *clock)
		671	{
		672	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
2342	Serge	673	INTELPllInvalid("p1 out of range\n");
2327	Serge	674	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
2342	Serge	675	INTELPllInvalid("p out of range\n");
2327	Serge	676	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
2342	Serge	677	INTELPllInvalid("m2 out of range\n");
2327	Serge	678	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
2342	Serge	679	INTELPllInvalid("m1 out of range\n");
2327	Serge	680	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342	Serge	681	INTELPllInvalid("m1 <= m2\n");
2327	Serge	682	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
2342	Serge	683	INTELPllInvalid("m out of range\n");
2327	Serge	684	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
2342	Serge	685	INTELPllInvalid("n out of range\n");
2327	Serge	686	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
2342	Serge	687	INTELPllInvalid("vco out of range\n");
2327	Serge	688	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		689	* connector, etc., rather than just a single range.
		690	*/
		691	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
2342	Serge	692	INTELPllInvalid("dot out of range\n");
2327	Serge	693
		694	return true;
		695	}
		696
		697	static bool
		698	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	699	int target, int refclk, intel_clock_t *match_clock,
		700	intel_clock_t *best_clock)
2327	Serge	701
		702	{
		703	struct drm_device *dev = crtc->dev;
		704	struct drm_i915_private *dev_priv = dev->dev_private;
		705	intel_clock_t clock;
		706	int err = target;
		707
		708	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		709	(I915_READ(LVDS)) != 0) {
		710	/*
		711	* For LVDS, if the panel is on, just rely on its current
		712	* settings for dual-channel. We haven't figured out how to
		713	* reliably set up different single/dual channel state, if we
		714	* even can.
		715	*/
3031	serge	716	if (is_dual_link_lvds(dev_priv, LVDS))
2327	Serge	717	clock.p2 = limit->p2.p2_fast;
		718	else
		719	clock.p2 = limit->p2.p2_slow;
		720	} else {
		721	if (target < limit->p2.dot_limit)
		722	clock.p2 = limit->p2.p2_slow;
		723	else
		724	clock.p2 = limit->p2.p2_fast;
		725	}
		726
2342	Serge	727	memset(best_clock, 0, sizeof(*best_clock));
2327	Serge	728
		729	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		730	clock.m1++) {
		731	for (clock.m2 = limit->m2.min;
		732	clock.m2 <= limit->m2.max; clock.m2++) {
		733	/* m1 is always 0 in Pineview */
		734	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
		735	break;
		736	for (clock.n = limit->n.min;
		737	clock.n <= limit->n.max; clock.n++) {
		738	for (clock.p1 = limit->p1.min;
		739	clock.p1 <= limit->p1.max; clock.p1++) {
		740	int this_err;
		741
		742	intel_clock(dev, refclk, &clock);
		743	if (!intel_PLL_is_valid(dev, limit,
		744	&clock))
		745	continue;
3031	serge	746	if (match_clock &&
		747	clock.p != match_clock->p)
		748	continue;
2327	Serge	749
		750	this_err = abs(clock.dot - target);
		751	if (this_err < err) {
		752	*best_clock = clock;
		753	err = this_err;
		754	}
		755	}
		756	}
		757	}
		758	}
		759
		760	return (err != target);
		761	}
		762
		763	static bool
		764	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	765	int target, int refclk, intel_clock_t *match_clock,
		766	intel_clock_t *best_clock)
2327	Serge	767	{
		768	struct drm_device *dev = crtc->dev;
		769	struct drm_i915_private *dev_priv = dev->dev_private;
		770	intel_clock_t clock;
		771	int max_n;
		772	bool found;
		773	/* approximately equals target * 0.00585 */
		774	int err_most = (target >> 8) + (target >> 9);
		775	found = false;
		776
		777	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		778	int lvds_reg;
		779
		780	if (HAS_PCH_SPLIT(dev))
		781	lvds_reg = PCH_LVDS;
		782	else
		783	lvds_reg = LVDS;
		784	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		785	LVDS_CLKB_POWER_UP)
		786	clock.p2 = limit->p2.p2_fast;
		787	else
		788	clock.p2 = limit->p2.p2_slow;
		789	} else {
		790	if (target < limit->p2.dot_limit)
		791	clock.p2 = limit->p2.p2_slow;
		792	else
		793	clock.p2 = limit->p2.p2_fast;
		794	}
		795
		796	memset(best_clock, 0, sizeof(*best_clock));
		797	max_n = limit->n.max;
		798	/* based on hardware requirement, prefer smaller n to precision */
		799	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		800	/* based on hardware requirement, prefere larger m1,m2 */
		801	for (clock.m1 = limit->m1.max;
		802	clock.m1 >= limit->m1.min; clock.m1--) {
		803	for (clock.m2 = limit->m2.max;
		804	clock.m2 >= limit->m2.min; clock.m2--) {
		805	for (clock.p1 = limit->p1.max;
		806	clock.p1 >= limit->p1.min; clock.p1--) {
		807	int this_err;
		808
		809	intel_clock(dev, refclk, &clock);
		810	if (!intel_PLL_is_valid(dev, limit,
		811	&clock))
		812	continue;
3031	serge	813	if (match_clock &&
		814	clock.p != match_clock->p)
		815	continue;
2327	Serge	816
		817	this_err = abs(clock.dot - target);
		818	if (this_err < err_most) {
		819	*best_clock = clock;
		820	err_most = this_err;
		821	max_n = clock.n;
		822	found = true;
		823	}
		824	}
		825	}
		826	}
		827	}
		828	return found;
		829	}
		830
		831	static bool
		832	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	833	int target, int refclk, intel_clock_t *match_clock,
		834	intel_clock_t *best_clock)
2327	Serge	835	{
		836	struct drm_device *dev = crtc->dev;
		837	intel_clock_t clock;
		838
		839	if (target < 200000) {
		840	clock.n = 1;
		841	clock.p1 = 2;
		842	clock.p2 = 10;
		843	clock.m1 = 12;
		844	clock.m2 = 9;
		845	} else {
		846	clock.n = 2;
		847	clock.p1 = 1;
		848	clock.p2 = 10;
		849	clock.m1 = 14;
		850	clock.m2 = 8;
		851	}
		852	intel_clock(dev, refclk, &clock);
		853	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		854	return true;
		855	}
		856
		857	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
		858	static bool
		859	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
3031	serge	860	int target, int refclk, intel_clock_t *match_clock,
		861	intel_clock_t *best_clock)
2327	Serge	862	{
		863	intel_clock_t clock;
		864	if (target < 200000) {
		865	clock.p1 = 2;
		866	clock.p2 = 10;
		867	clock.n = 2;
		868	clock.m1 = 23;
		869	clock.m2 = 8;
		870	} else {
		871	clock.p1 = 1;
		872	clock.p2 = 10;
		873	clock.n = 1;
		874	clock.m1 = 14;
		875	clock.m2 = 2;
		876	}
		877	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
		878	clock.p = (clock.p1 * clock.p2);
		879	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
		880	clock.vco = 0;
		881	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		882	return true;
		883	}
3031	serge	884	static bool
		885	intel_vlv_find_best_pll(const intel_limit_t limit, struct drm_crtc crtc,
		886	int target, int refclk, intel_clock_t *match_clock,
		887	intel_clock_t *best_clock)
		888	{
		889	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
		890	u32 m, n, fastclk;
		891	u32 updrate, minupdate, fracbits, p;
		892	unsigned long bestppm, ppm, absppm;
		893	int dotclk, flag;
2327	Serge	894
3031	serge	895	flag = 0;
		896	dotclk = target * 1000;
		897	bestppm = 1000000;
		898	ppm = absppm = 0;
		899	fastclk = dotclk / (2*100);
		900	updrate = 0;
		901	minupdate = 19200;
		902	fracbits = 1;
		903	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
		904	bestm1 = bestm2 = bestp1 = bestp2 = 0;
		905
		906	/* based on hardware requirement, prefer smaller n to precision */
		907	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		908	updrate = refclk / n;
		909	for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
		910	for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
		911	if (p2 > 10)
		912	p2 = p2 - 1;
		913	p = p1 * p2;
		914	/* based on hardware requirement, prefer bigger m1,m2 values */
		915	for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
		916	m2 = (((2(fastclk p * n / m1 )) +
		917	refclk) / (2*refclk));
		918	m = m1 * m2;
		919	vco = updrate * m;
		920	if (vco >= limit->vco.min && vco < limit->vco.max) {
		921	ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
		922	absppm = (ppm > 0) ? ppm : (-ppm);
		923	if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
		924	bestppm = 0;
		925	flag = 1;
		926	}
		927	if (absppm < bestppm - 10) {
		928	bestppm = absppm;
		929	flag = 1;
		930	}
		931	if (flag) {
		932	bestn = n;
		933	bestm1 = m1;
		934	bestm2 = m2;
		935	bestp1 = p1;
		936	bestp2 = p2;
		937	flag = 0;
		938	}
		939	}
		940	}
		941	}
		942	}
		943	}
		944	best_clock->n = bestn;
		945	best_clock->m1 = bestm1;
		946	best_clock->m2 = bestm2;
		947	best_clock->p1 = bestp1;
		948	best_clock->p2 = bestp2;
		949
		950	return true;
		951	}
		952
		953	static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
		954	{
		955	struct drm_i915_private *dev_priv = dev->dev_private;
		956	u32 frame, frame_reg = PIPEFRAME(pipe);
		957
		958	frame = I915_READ(frame_reg);
		959
		960	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		961	DRM_DEBUG_KMS("vblank wait timed out\n");
		962	}
		963
2327	Serge	964	/**
		965	* intel_wait_for_vblank - wait for vblank on a given pipe
		966	* @dev: drm device
		967	* @pipe: pipe to wait for
		968	*
		969	* Wait for vblank to occur on a given pipe. Needed for various bits of
		970	* mode setting code.
		971	*/
		972	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		973	{
		974	struct drm_i915_private *dev_priv = dev->dev_private;
		975	int pipestat_reg = PIPESTAT(pipe);
		976
3031	serge	977	if (INTEL_INFO(dev)->gen >= 5) {
		978	ironlake_wait_for_vblank(dev, pipe);
		979	return;
		980	}
		981
2327	Serge	982	/* Clear existing vblank status. Note this will clear any other
		983	* sticky status fields as well.
		984	*
		985	* This races with i915_driver_irq_handler() with the result
		986	* that either function could miss a vblank event. Here it is not
		987	* fatal, as we will either wait upon the next vblank interrupt or
		988	* timeout. Generally speaking intel_wait_for_vblank() is only
		989	* called during modeset at which time the GPU should be idle and
		990	* should not be performing page flips and thus not waiting on
		991	* vblanks...
		992	* Currently, the result of us stealing a vblank from the irq
		993	* handler is that a single frame will be skipped during swapbuffers.
		994	*/
		995	I915_WRITE(pipestat_reg,
		996	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		997
		998	/* Wait for vblank interrupt bit to set */
		999	if (wait_for(I915_READ(pipestat_reg) &
		1000	PIPE_VBLANK_INTERRUPT_STATUS,
		1001	50))
		1002	DRM_DEBUG_KMS("vblank wait timed out\n");
		1003	}
		1004
		1005	/*
		1006	* intel_wait_for_pipe_off - wait for pipe to turn off
		1007	* @dev: drm device
		1008	* @pipe: pipe to wait for
		1009	*
		1010	* After disabling a pipe, we can't wait for vblank in the usual way,
		1011	* spinning on the vblank interrupt status bit, since we won't actually
		1012	* see an interrupt when the pipe is disabled.
		1013	*
		1014	* On Gen4 and above:
		1015	* wait for the pipe register state bit to turn off
		1016	*
		1017	* Otherwise:
		1018	* wait for the display line value to settle (it usually
		1019	* ends up stopping at the start of the next frame).
		1020	*
		1021	*/
		1022	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		1023	{
		1024	struct drm_i915_private *dev_priv = dev->dev_private;
		1025
		1026	if (INTEL_INFO(dev)->gen >= 4) {
		1027	int reg = PIPECONF(pipe);
		1028
		1029	/* Wait for the Pipe State to go off */
		1030	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		1031	100))
3031	serge	1032	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1033	} else {
3031	serge	1034	u32 last_line, line_mask;
2327	Serge	1035	int reg = PIPEDSL(pipe);
3031	serge	1036	unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
2327	Serge	1037
3031	serge	1038	if (IS_GEN2(dev))
		1039	line_mask = DSL_LINEMASK_GEN2;
		1040	else
		1041	line_mask = DSL_LINEMASK_GEN3;
		1042
2327	Serge	1043	/* Wait for the display line to settle */
		1044	do {
3031	serge	1045	last_line = I915_READ(reg) & line_mask;
2327	Serge	1046	mdelay(5);
3031	serge	1047	} while (((I915_READ(reg) & line_mask) != last_line) &&
		1048	time_after(timeout, GetTimerTicks()));
		1049	if (time_after(GetTimerTicks(), timeout))
		1050	WARN(1, "pipe_off wait timed out\n");
2327	Serge	1051	}
		1052	}
		1053
		1054	static const char *state_string(bool enabled)
		1055	{
		1056	return enabled ? "on" : "off";
		1057	}
		1058
		1059	/* Only for pre-ILK configs */
		1060	static void assert_pll(struct drm_i915_private *dev_priv,
		1061	enum pipe pipe, bool state)
		1062	{
		1063	int reg;
		1064	u32 val;
		1065	bool cur_state;
		1066
		1067	reg = DPLL(pipe);
		1068	val = I915_READ(reg);
		1069	cur_state = !!(val & DPLL_VCO_ENABLE);
		1070	WARN(cur_state != state,
		1071	"PLL state assertion failure (expected %s, current %s)\n",
		1072	state_string(state), state_string(cur_state));
		1073	}
		1074	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
		1075	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
		1076
		1077	/* For ILK+ */
		1078	static void assert_pch_pll(struct drm_i915_private *dev_priv,
3031	serge	1079	struct intel_pch_pll *pll,
		1080	struct intel_crtc *crtc,
		1081	bool state)
2327	Serge	1082	{
		1083	u32 val;
		1084	bool cur_state;
		1085
3031	serge	1086	if (HAS_PCH_LPT(dev_priv->dev)) {
		1087	DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		1088	return;
		1089	}
2342	Serge	1090
3031	serge	1091	if (WARN (!pll,
		1092	"asserting PCH PLL %s with no PLL\n", state_string(state)))
		1093	return;
2342	Serge	1094
3031	serge	1095	val = I915_READ(pll->pll_reg);
		1096	cur_state = !!(val & DPLL_VCO_ENABLE);
		1097	WARN(cur_state != state,
		1098	"PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
		1099	pll->pll_reg, state_string(state), state_string(cur_state), val);
2342	Serge	1100
3031	serge	1101	/* Make sure the selected PLL is correctly attached to the transcoder */
		1102	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
		1103	u32 pch_dpll;
2342	Serge	1104
3031	serge	1105	pch_dpll = I915_READ(PCH_DPLL_SEL);
		1106	cur_state = pll->pll_reg == _PCH_DPLL_B;
		1107	if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
		1108	"PLL[%d] not attached to this transcoder %d: %08x\n",
		1109	cur_state, crtc->pipe, pch_dpll)) {
		1110	cur_state = !!(val >> (4*crtc->pipe + 3));
2327	Serge	1111	WARN(cur_state != state,
3031	serge	1112	"PLL[%d] not %s on this transcoder %d: %08x\n",
		1113	pll->pll_reg == _PCH_DPLL_B,
		1114	state_string(state),
		1115	crtc->pipe,
		1116	val);
		1117	}
		1118	}
2327	Serge	1119	}
3031	serge	1120	#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
		1121	#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
2327	Serge	1122
		1123	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		1124	enum pipe pipe, bool state)
		1125	{
		1126	int reg;
		1127	u32 val;
		1128	bool cur_state;
		1129
3031	serge	1130	if (IS_HASWELL(dev_priv->dev)) {
		1131	/* On Haswell, DDI is used instead of FDI_TX_CTL */
		1132	reg = DDI_FUNC_CTL(pipe);
		1133	val = I915_READ(reg);
		1134	cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
		1135	} else {
2327	Serge	1136	reg = FDI_TX_CTL(pipe);
		1137	val = I915_READ(reg);
		1138	cur_state = !!(val & FDI_TX_ENABLE);
3031	serge	1139	}
2327	Serge	1140	WARN(cur_state != state,
		1141	"FDI TX state assertion failure (expected %s, current %s)\n",
		1142	state_string(state), state_string(cur_state));
		1143	}
		1144	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		1145	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		1146
		1147	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		1148	enum pipe pipe, bool state)
		1149	{
		1150	int reg;
		1151	u32 val;
		1152	bool cur_state;
		1153
3031	serge	1154	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1155	DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
		1156	return;
		1157	} else {
2327	Serge	1158	reg = FDI_RX_CTL(pipe);
		1159	val = I915_READ(reg);
		1160	cur_state = !!(val & FDI_RX_ENABLE);
3031	serge	1161	}
2327	Serge	1162	WARN(cur_state != state,
		1163	"FDI RX state assertion failure (expected %s, current %s)\n",
		1164	state_string(state), state_string(cur_state));
		1165	}
		1166	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		1167	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		1168
		1169	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		1170	enum pipe pipe)
		1171	{
		1172	int reg;
		1173	u32 val;
		1174
		1175	/* ILK FDI PLL is always enabled */
		1176	if (dev_priv->info->gen == 5)
		1177	return;
		1178
3031	serge	1179	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
		1180	if (IS_HASWELL(dev_priv->dev))
		1181	return;
		1182
2327	Serge	1183	reg = FDI_TX_CTL(pipe);
		1184	val = I915_READ(reg);
		1185	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		1186	}
		1187
		1188	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
		1189	enum pipe pipe)
		1190	{
		1191	int reg;
		1192	u32 val;
		1193
3031	serge	1194	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1195	DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
		1196	return;
		1197	}
2327	Serge	1198	reg = FDI_RX_CTL(pipe);
		1199	val = I915_READ(reg);
		1200	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
		1201	}
		1202
		1203	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		1204	enum pipe pipe)
		1205	{
		1206	int pp_reg, lvds_reg;
		1207	u32 val;
		1208	enum pipe panel_pipe = PIPE_A;
		1209	bool locked = true;
		1210
		1211	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1212	pp_reg = PCH_PP_CONTROL;
		1213	lvds_reg = PCH_LVDS;
		1214	} else {
		1215	pp_reg = PP_CONTROL;
		1216	lvds_reg = LVDS;
		1217	}
		1218
		1219	val = I915_READ(pp_reg);
		1220	if (!(val & PANEL_POWER_ON) \|\|
		1221	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		1222	locked = false;
		1223
		1224	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		1225	panel_pipe = PIPE_B;
		1226
		1227	WARN(panel_pipe == pipe && locked,
		1228	"panel assertion failure, pipe %c regs locked\n",
		1229	pipe_name(pipe));
		1230	}
		1231
2342	Serge	1232	void assert_pipe(struct drm_i915_private *dev_priv,
2327	Serge	1233	enum pipe pipe, bool state)
		1234	{
		1235	int reg;
		1236	u32 val;
		1237	bool cur_state;
		1238
3031	serge	1239	/* if we need the pipe A quirk it must be always on */
		1240	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		1241	state = true;
		1242
2327	Serge	1243	reg = PIPECONF(pipe);
		1244	val = I915_READ(reg);
		1245	cur_state = !!(val & PIPECONF_ENABLE);
		1246	WARN(cur_state != state,
		1247	"pipe %c assertion failure (expected %s, current %s)\n",
		1248	pipe_name(pipe), state_string(state), state_string(cur_state));
		1249	}
		1250
3031	serge	1251	static void assert_plane(struct drm_i915_private *dev_priv,
		1252	enum plane plane, bool state)
2327	Serge	1253	{
		1254	int reg;
		1255	u32 val;
3031	serge	1256	bool cur_state;
2327	Serge	1257
		1258	reg = DSPCNTR(plane);
		1259	val = I915_READ(reg);
3031	serge	1260	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
		1261	WARN(cur_state != state,
		1262	"plane %c assertion failure (expected %s, current %s)\n",
		1263	plane_name(plane), state_string(state), state_string(cur_state));
2327	Serge	1264	}
		1265
3031	serge	1266	#define assert_plane_enabled(d, p) assert_plane(d, p, true)
		1267	#define assert_plane_disabled(d, p) assert_plane(d, p, false)
		1268
2327	Serge	1269	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		1270	enum pipe pipe)
		1271	{
		1272	int reg, i;
		1273	u32 val;
		1274	int cur_pipe;
		1275
		1276	/* Planes are fixed to pipes on ILK+ */
3031	serge	1277	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		1278	reg = DSPCNTR(pipe);
		1279	val = I915_READ(reg);
		1280	WARN((val & DISPLAY_PLANE_ENABLE),
		1281	"plane %c assertion failure, should be disabled but not\n",
		1282	plane_name(pipe));
2327	Serge	1283	return;
3031	serge	1284	}
2327	Serge	1285
		1286	/* Need to check both planes against the pipe */
		1287	for (i = 0; i < 2; i++) {
		1288	reg = DSPCNTR(i);
		1289	val = I915_READ(reg);
		1290	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		1291	DISPPLANE_SEL_PIPE_SHIFT;
		1292	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		1293	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		1294	plane_name(i), pipe_name(pipe));
		1295	}
		1296	}
		1297
		1298	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		1299	{
		1300	u32 val;
		1301	bool enabled;
		1302
3031	serge	1303	if (HAS_PCH_LPT(dev_priv->dev)) {
		1304	DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		1305	return;
		1306	}
		1307
2327	Serge	1308	val = I915_READ(PCH_DREF_CONTROL);
		1309	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		1310	DREF_SUPERSPREAD_SOURCE_MASK));
		1311	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		1312	}
		1313
		1314	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
		1315	enum pipe pipe)
		1316	{
		1317	int reg;
		1318	u32 val;
		1319	bool enabled;
		1320
		1321	reg = TRANSCONF(pipe);
		1322	val = I915_READ(reg);
		1323	enabled = !!(val & TRANS_ENABLE);
		1324	WARN(enabled,
		1325	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1326	pipe_name(pipe));
		1327	}
		1328
		1329	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1330	enum pipe pipe, u32 port_sel, u32 val)
		1331	{
		1332	if ((val & DP_PORT_EN) == 0)
		1333	return false;
		1334
		1335	if (HAS_PCH_CPT(dev_priv->dev)) {
		1336	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1337	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1338	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1339	return false;
		1340	} else {
		1341	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1342	return false;
		1343	}
		1344	return true;
		1345	}
		1346
		1347	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1348	enum pipe pipe, u32 val)
		1349	{
		1350	if ((val & PORT_ENABLE) == 0)
		1351	return false;
		1352
		1353	if (HAS_PCH_CPT(dev_priv->dev)) {
		1354	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1355	return false;
		1356	} else {
		1357	if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
		1358	return false;
		1359	}
		1360	return true;
		1361	}
		1362
		1363	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1364	enum pipe pipe, u32 val)
		1365	{
		1366	if ((val & LVDS_PORT_EN) == 0)
		1367	return false;
		1368
		1369	if (HAS_PCH_CPT(dev_priv->dev)) {
		1370	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1371	return false;
		1372	} else {
		1373	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1374	return false;
		1375	}
		1376	return true;
		1377	}
		1378
		1379	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1380	enum pipe pipe, u32 val)
		1381	{
		1382	if ((val & ADPA_DAC_ENABLE) == 0)
		1383	return false;
		1384	if (HAS_PCH_CPT(dev_priv->dev)) {
		1385	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1386	return false;
		1387	} else {
		1388	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1389	return false;
		1390	}
		1391	return true;
		1392	}
		1393
		1394	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1395	enum pipe pipe, int reg, u32 port_sel)
		1396	{
		1397	u32 val = I915_READ(reg);
		1398	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1399	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1400	reg, pipe_name(pipe));
3031	serge	1401
		1402	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
		1403	&& (val & DP_PIPEB_SELECT),
		1404	"IBX PCH dp port still using transcoder B\n");
2327	Serge	1405	}
		1406
		1407	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1408	enum pipe pipe, int reg)
		1409	{
		1410	u32 val = I915_READ(reg);
3031	serge	1411	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
		1412	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
2327	Serge	1413	reg, pipe_name(pipe));
3031	serge	1414
		1415	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
		1416	&& (val & SDVO_PIPE_B_SELECT),
		1417	"IBX PCH hdmi port still using transcoder B\n");
2327	Serge	1418	}
		1419
		1420	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1421	enum pipe pipe)
		1422	{
		1423	int reg;
		1424	u32 val;
		1425
		1426	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1427	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1428	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1429
		1430	reg = PCH_ADPA;
		1431	val = I915_READ(reg);
3031	serge	1432	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1433	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1434	pipe_name(pipe));
		1435
		1436	reg = PCH_LVDS;
		1437	val = I915_READ(reg);
3031	serge	1438	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
2327	Serge	1439	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1440	pipe_name(pipe));
		1441
		1442	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
		1443	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
		1444	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
		1445	}
		1446
		1447	/**
		1448	* intel_enable_pll - enable a PLL
		1449	* @dev_priv: i915 private structure
		1450	* @pipe: pipe PLL to enable
		1451	*
		1452	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
		1453	* make sure the PLL reg is writable first though, since the panel write
		1454	* protect mechanism may be enabled.
		1455	*
		1456	* Note! This is for pre-ILK only.
3031	serge	1457	*
		1458	* Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
2327	Serge	1459	*/
		1460	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1461	{
		1462	int reg;
		1463	u32 val;
		1464
		1465	/* No really, not for ILK+ */
3031	serge	1466	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
2327	Serge	1467
		1468	/* PLL is protected by panel, make sure we can write it */
		1469	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		1470	assert_panel_unlocked(dev_priv, pipe);
		1471
		1472	reg = DPLL(pipe);
		1473	val = I915_READ(reg);
		1474	val \|= DPLL_VCO_ENABLE;
		1475
		1476	/* We do this three times for luck */
		1477	I915_WRITE(reg, val);
		1478	POSTING_READ(reg);
		1479	udelay(150); /* wait for warmup */
		1480	I915_WRITE(reg, val);
		1481	POSTING_READ(reg);
		1482	udelay(150); /* wait for warmup */
		1483	I915_WRITE(reg, val);
		1484	POSTING_READ(reg);
		1485	udelay(150); /* wait for warmup */
		1486	}
		1487
		1488	/**
		1489	* intel_disable_pll - disable a PLL
		1490	* @dev_priv: i915 private structure
		1491	* @pipe: pipe PLL to disable
		1492	*
		1493	* Disable the PLL for @pipe, making sure the pipe is off first.
		1494	*
		1495	* Note! This is for pre-ILK only.
		1496	*/
		1497	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1498	{
		1499	int reg;
		1500	u32 val;
		1501
		1502	/* Don't disable pipe A or pipe A PLLs if needed */
		1503	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1504	return;
		1505
		1506	/* Make sure the pipe isn't still relying on us */
		1507	assert_pipe_disabled(dev_priv, pipe);
		1508
		1509	reg = DPLL(pipe);
		1510	val = I915_READ(reg);
		1511	val &= ~DPLL_VCO_ENABLE;
		1512	I915_WRITE(reg, val);
		1513	POSTING_READ(reg);
		1514	}
		1515
3031	serge	1516	/* SBI access */
		1517	static void
		1518	intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
		1519	{
		1520	unsigned long flags;
		1521
		1522	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		1523	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1524	100)) {
		1525	DRM_ERROR("timeout waiting for SBI to become ready\n");
		1526	goto out_unlock;
		1527	}
		1528
		1529	I915_WRITE(SBI_ADDR,
		1530	(reg << 16));
		1531	I915_WRITE(SBI_DATA,
		1532	value);
		1533	I915_WRITE(SBI_CTL_STAT,
		1534	SBI_BUSY \|
		1535	SBI_CTL_OP_CRWR);
		1536
		1537	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1538	100)) {
		1539	DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
		1540	goto out_unlock;
		1541	}
		1542
		1543	out_unlock:
		1544	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		1545	}
		1546
		1547	static u32
		1548	intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
		1549	{
		1550	unsigned long flags;
		1551	u32 value = 0;
		1552
		1553	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
		1554	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
		1555	100)) {
		1556	DRM_ERROR("timeout waiting for SBI to become ready\n");
		1557	goto out_unlock;
		1558	}
		1559
		1560	I915_WRITE(SBI_ADDR,
		1561	(reg << 16));
		1562	I915_WRITE(SBI_CTL_STAT,
		1563	SBI_BUSY \|
		1564	SBI_CTL_OP_CRRD);
		1565
		1566	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
		1567	100)) {
		1568	DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
		1569	goto out_unlock;
		1570	}
		1571
		1572	value = I915_READ(SBI_DATA);
		1573
		1574	out_unlock:
		1575	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
		1576	return value;
		1577	}
		1578
2327	Serge	1579	/**
		1580	* intel_enable_pch_pll - enable PCH PLL
		1581	* @dev_priv: i915 private structure
		1582	* @pipe: pipe PLL to enable
		1583	*
		1584	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1585	* drives the transcoder clock.
		1586	*/
3031	serge	1587	static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1588	{
3031	serge	1589	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1590	struct intel_pch_pll *pll;
2327	Serge	1591	int reg;
		1592	u32 val;
		1593
3031	serge	1594	/* PCH PLLs only available on ILK, SNB and IVB */
		1595	BUG_ON(dev_priv->info->gen < 5);
		1596	pll = intel_crtc->pch_pll;
		1597	if (pll == NULL)
2342	Serge	1598	return;
		1599
3031	serge	1600	if (WARN_ON(pll->refcount == 0))
		1601	return;
2327	Serge	1602
3031	serge	1603	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		1604	pll->pll_reg, pll->active, pll->on,
		1605	intel_crtc->base.base.id);
		1606
2327	Serge	1607	/* PCH refclock must be enabled first */
		1608	assert_pch_refclk_enabled(dev_priv);
		1609
3031	serge	1610	if (pll->active++ && pll->on) {
		1611	assert_pch_pll_enabled(dev_priv, pll, NULL);
		1612	return;
		1613	}
		1614
		1615	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
		1616
		1617	reg = pll->pll_reg;
2327	Serge	1618	val = I915_READ(reg);
		1619	val \|= DPLL_VCO_ENABLE;
		1620	I915_WRITE(reg, val);
		1621	POSTING_READ(reg);
		1622	udelay(200);
3031	serge	1623
		1624	pll->on = true;
2327	Serge	1625	}
		1626
3031	serge	1627	static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
2327	Serge	1628	{
3031	serge	1629	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		1630	struct intel_pch_pll *pll = intel_crtc->pch_pll;
2327	Serge	1631	int reg;
3031	serge	1632	u32 val;
2327	Serge	1633
		1634	/* PCH only available on ILK+ */
		1635	BUG_ON(dev_priv->info->gen < 5);
3031	serge	1636	if (pll == NULL)
		1637	return;
2327	Serge	1638
3031	serge	1639	if (WARN_ON(pll->refcount == 0))
		1640	return;
2327	Serge	1641
3031	serge	1642	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		1643	pll->pll_reg, pll->active, pll->on,
		1644	intel_crtc->base.base.id);
2342	Serge	1645
3031	serge	1646	if (WARN_ON(pll->active == 0)) {
		1647	assert_pch_pll_disabled(dev_priv, pll, NULL);
		1648	return;
		1649	}
2342	Serge	1650
3031	serge	1651	if (--pll->active) {
		1652	assert_pch_pll_enabled(dev_priv, pll, NULL);
2342	Serge	1653	return;
3031	serge	1654	}
2342	Serge	1655
3031	serge	1656	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
		1657
		1658	/* Make sure transcoder isn't still depending on us */
		1659	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
		1660
		1661	reg = pll->pll_reg;
2327	Serge	1662	val = I915_READ(reg);
		1663	val &= ~DPLL_VCO_ENABLE;
		1664	I915_WRITE(reg, val);
		1665	POSTING_READ(reg);
		1666	udelay(200);
3031	serge	1667
		1668	pll->on = false;
2327	Serge	1669	}
		1670
		1671	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
		1672	enum pipe pipe)
		1673	{
		1674	int reg;
3031	serge	1675	u32 val, pipeconf_val;
		1676	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	1677
		1678	/* PCH only available on ILK+ */
		1679	BUG_ON(dev_priv->info->gen < 5);
		1680
		1681	/* Make sure PCH DPLL is enabled */
3031	serge	1682	assert_pch_pll_enabled(dev_priv,
		1683	to_intel_crtc(crtc)->pch_pll,
		1684	to_intel_crtc(crtc));
2327	Serge	1685
		1686	/* FDI must be feeding us bits for PCH ports */
		1687	assert_fdi_tx_enabled(dev_priv, pipe);
		1688	assert_fdi_rx_enabled(dev_priv, pipe);
		1689
3031	serge	1690	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		1691	DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
		1692	return;
		1693	}
2327	Serge	1694	reg = TRANSCONF(pipe);
		1695	val = I915_READ(reg);
3031	serge	1696	pipeconf_val = I915_READ(PIPECONF(pipe));
2327	Serge	1697
		1698	if (HAS_PCH_IBX(dev_priv->dev)) {
		1699	/*
		1700	* make the BPC in transcoder be consistent with
		1701	* that in pipeconf reg.
		1702	*/
		1703	val &= ~PIPE_BPC_MASK;
3031	serge	1704	val \|= pipeconf_val & PIPE_BPC_MASK;
2327	Serge	1705	}
3031	serge	1706
		1707	val &= ~TRANS_INTERLACE_MASK;
		1708	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		1709	if (HAS_PCH_IBX(dev_priv->dev) &&
		1710	intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
		1711	val \|= TRANS_LEGACY_INTERLACED_ILK;
		1712	else
		1713	val \|= TRANS_INTERLACED;
		1714	else
		1715	val \|= TRANS_PROGRESSIVE;
		1716
2327	Serge	1717	I915_WRITE(reg, val \| TRANS_ENABLE);
		1718	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		1719	DRM_ERROR("failed to enable transcoder %d\n", pipe);
		1720	}
		1721
		1722	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
		1723	enum pipe pipe)
		1724	{
		1725	int reg;
		1726	u32 val;
		1727
		1728	/* FDI relies on the transcoder */
		1729	assert_fdi_tx_disabled(dev_priv, pipe);
		1730	assert_fdi_rx_disabled(dev_priv, pipe);
		1731
		1732	/* Ports must be off as well */
		1733	assert_pch_ports_disabled(dev_priv, pipe);
		1734
		1735	reg = TRANSCONF(pipe);
		1736	val = I915_READ(reg);
		1737	val &= ~TRANS_ENABLE;
		1738	I915_WRITE(reg, val);
		1739	/* wait for PCH transcoder off, transcoder state */
		1740	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2342	Serge	1741	DRM_ERROR("failed to disable transcoder %d\n", pipe);
2327	Serge	1742	}
		1743
		1744	/**
		1745	* intel_enable_pipe - enable a pipe, asserting requirements
		1746	* @dev_priv: i915 private structure
		1747	* @pipe: pipe to enable
		1748	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1749	*
		1750	* Enable @pipe, making sure that various hardware specific requirements
		1751	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1752	*
		1753	* @pipe should be %PIPE_A or %PIPE_B.
		1754	*
		1755	* Will wait until the pipe is actually running (i.e. first vblank) before
		1756	* returning.
		1757	*/
		1758	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1759	bool pch_port)
		1760	{
		1761	int reg;
		1762	u32 val;
		1763
		1764	/*
		1765	* A pipe without a PLL won't actually be able to drive bits from
		1766	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1767	* need the check.
		1768	*/
		1769	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1770	assert_pll_enabled(dev_priv, pipe);
		1771	else {
		1772	if (pch_port) {
		1773	/* if driving the PCH, we need FDI enabled */
		1774	assert_fdi_rx_pll_enabled(dev_priv, pipe);
		1775	assert_fdi_tx_pll_enabled(dev_priv, pipe);
		1776	}
		1777	/* FIXME: assert CPU port conditions for SNB+ */
		1778	}
		1779
		1780	reg = PIPECONF(pipe);
		1781	val = I915_READ(reg);
		1782	if (val & PIPECONF_ENABLE)
		1783	return;
		1784
		1785	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1786	intel_wait_for_vblank(dev_priv->dev, pipe);
		1787	}
		1788
		1789	/**
		1790	* intel_disable_pipe - disable a pipe, asserting requirements
		1791	* @dev_priv: i915 private structure
		1792	* @pipe: pipe to disable
		1793	*
		1794	* Disable @pipe, making sure that various hardware specific requirements
		1795	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1796	*
		1797	* @pipe should be %PIPE_A or %PIPE_B.
		1798	*
		1799	* Will wait until the pipe has shut down before returning.
		1800	*/
		1801	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1802	enum pipe pipe)
		1803	{
		1804	int reg;
		1805	u32 val;
		1806
3031	serge	1807	/*
2327	Serge	1808	* Make sure planes won't keep trying to pump pixels to us,
		1809	* or we might hang the display.
		1810	*/
		1811	assert_planes_disabled(dev_priv, pipe);
		1812
		1813	/* Don't disable pipe A or pipe A PLLs if needed */
		1814	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1815	return;
		1816
		1817	reg = PIPECONF(pipe);
		1818	val = I915_READ(reg);
		1819	if ((val & PIPECONF_ENABLE) == 0)
		1820	return;
		1821
		1822	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1823	intel_wait_for_pipe_off(dev_priv->dev, pipe);
3031	serge	1824
2327	Serge	1825	}
		1826
		1827	/*
		1828	* Plane regs are double buffered, going from enabled->disabled needs a
		1829	* trigger in order to latch. The display address reg provides this.
		1830	*/
3031	serge	1831	void intel_flush_display_plane(struct drm_i915_private *dev_priv,
2327	Serge	1832	enum plane plane)
		1833	{
		1834	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1835	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1836	}
		1837
		1838	/**
		1839	* intel_enable_plane - enable a display plane on a given pipe
		1840	* @dev_priv: i915 private structure
		1841	* @plane: plane to enable
		1842	* @pipe: pipe being fed
		1843	*
		1844	* Enable @plane on @pipe, making sure that @pipe is running first.
		1845	*/
		1846	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1847	enum plane plane, enum pipe pipe)
		1848	{
		1849	int reg;
		1850	u32 val;
		1851
		1852	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1853	assert_pipe_enabled(dev_priv, pipe);
		1854
		1855	reg = DSPCNTR(plane);
		1856	val = I915_READ(reg);
		1857	if (val & DISPLAY_PLANE_ENABLE)
		1858	return;
		1859
		1860	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1861	intel_flush_display_plane(dev_priv, plane);
		1862	intel_wait_for_vblank(dev_priv->dev, pipe);
		1863	}
		1864
		1865	/**
		1866	* intel_disable_plane - disable a display plane
		1867	* @dev_priv: i915 private structure
		1868	* @plane: plane to disable
		1869	* @pipe: pipe consuming the data
		1870	*
		1871	* Disable @plane; should be an independent operation.
		1872	*/
		1873	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1874	enum plane plane, enum pipe pipe)
		1875	{
		1876	int reg;
		1877	u32 val;
		1878
		1879	reg = DSPCNTR(plane);
		1880	val = I915_READ(reg);
		1881	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1882	return;
		1883
		1884	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1885	intel_flush_display_plane(dev_priv, plane);
3031	serge	1886	intel_wait_for_vblank(dev_priv->dev, pipe);
2327	Serge	1887	}
		1888
2335	Serge	1889	int
		1890	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1891	struct drm_i915_gem_object *obj,
		1892	struct intel_ring_buffer *pipelined)
		1893	{
		1894	struct drm_i915_private *dev_priv = dev->dev_private;
		1895	u32 alignment;
		1896	int ret;
2327	Serge	1897
2335	Serge	1898	switch (obj->tiling_mode) {
		1899	case I915_TILING_NONE:
		1900	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1901	alignment = 128 * 1024;
		1902	else if (INTEL_INFO(dev)->gen >= 4)
		1903	alignment = 4 * 1024;
		1904	else
		1905	alignment = 64 * 1024;
		1906	break;
		1907	case I915_TILING_X:
		1908	/* pin() will align the object as required by fence */
		1909	alignment = 0;
		1910	break;
		1911	case I915_TILING_Y:
		1912	/* FIXME: Is this true? */
		1913	DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		1914	return -EINVAL;
		1915	default:
		1916	BUG();
		1917	}
2327	Serge	1918
2335	Serge	1919	dev_priv->mm.interruptible = false;
		1920	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1921	if (ret)
		1922	goto err_interruptible;
2327	Serge	1923
2335	Serge	1924	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1925	* fence, whereas 965+ only requires a fence if using
		1926	* framebuffer compression. For simplicity, we always install
		1927	* a fence as the cost is not that onerous.
		1928	*/
		1929	// if (obj->tiling_mode != I915_TILING_NONE) {
		1930	// ret = i915_gem_object_get_fence(obj, pipelined);
		1931	// if (ret)
		1932	// goto err_unpin;
		1933	// }
2327	Serge	1934
2335	Serge	1935	dev_priv->mm.interruptible = true;
		1936	return 0;
2327	Serge	1937
2335	Serge	1938	err_unpin:
2344	Serge	1939	i915_gem_object_unpin(obj);
2335	Serge	1940	err_interruptible:
		1941	dev_priv->mm.interruptible = true;
		1942	return ret;
		1943	}
2327	Serge	1944
3031	serge	1945	void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
		1946	{
		1947	// i915_gem_object_unpin_fence(obj);
		1948	// i915_gem_object_unpin(obj);
		1949	}
		1950
		1951	/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
		1952	* is assumed to be a power-of-two. */
		1953	static unsigned long gen4_compute_dspaddr_offset_xtiled(int x, int y,
		1954	unsigned int bpp,
		1955	unsigned int pitch)
		1956	{
		1957	int tile_rows, tiles;
		1958
		1959	tile_rows = *y / 8;
		1960	*y %= 8;
		1961	tiles = *x / (512/bpp);
		1962	*x %= 512/bpp;
		1963
		1964	return tile_rows * pitch * 8 + tiles * 4096;
		1965	}
		1966
2327	Serge	1967	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1968	int x, int y)
		1969	{
		1970	struct drm_device *dev = crtc->dev;
		1971	struct drm_i915_private *dev_priv = dev->dev_private;
		1972	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1973	struct intel_framebuffer *intel_fb;
		1974	struct drm_i915_gem_object *obj;
		1975	int plane = intel_crtc->plane;
3031	serge	1976	unsigned long linear_offset;
2327	Serge	1977	u32 dspcntr;
		1978	u32 reg;
		1979
		1980	switch (plane) {
		1981	case 0:
		1982	case 1:
		1983	break;
		1984	default:
		1985	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		1986	return -EINVAL;
		1987	}
		1988
		1989	intel_fb = to_intel_framebuffer(fb);
		1990	obj = intel_fb->obj;
		1991
		1992	reg = DSPCNTR(plane);
		1993	dspcntr = I915_READ(reg);
		1994	/* Mask out pixel format bits in case we change it */
		1995	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		1996	switch (fb->bits_per_pixel) {
		1997	case 8:
		1998	dspcntr \|= DISPPLANE_8BPP;
		1999	break;
		2000	case 16:
		2001	if (fb->depth == 15)
		2002	dspcntr \|= DISPPLANE_15_16BPP;
		2003	else
		2004	dspcntr \|= DISPPLANE_16BPP;
		2005	break;
		2006	case 24:
		2007	case 32:
		2008	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2009	break;
		2010	default:
		2011	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2012	return -EINVAL;
		2013	}
		2014	if (INTEL_INFO(dev)->gen >= 4) {
		2015	if (obj->tiling_mode != I915_TILING_NONE)
		2016	dspcntr \|= DISPPLANE_TILED;
		2017	else
		2018	dspcntr &= ~DISPPLANE_TILED;
		2019	}
		2020
		2021	I915_WRITE(reg, dspcntr);
		2022
3031	serge	2023	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327	Serge	2024
3031	serge	2025	if (INTEL_INFO(dev)->gen >= 4) {
		2026	intel_crtc->dspaddr_offset =
		2027	gen4_compute_dspaddr_offset_xtiled(&x, &y,
		2028	fb->bits_per_pixel / 8,
		2029	fb->pitches[0]);
		2030	linear_offset -= intel_crtc->dspaddr_offset;
		2031	} else {
		2032	intel_crtc->dspaddr_offset = linear_offset;
		2033	}
		2034
		2035	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2036	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2037	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327	Serge	2038	if (INTEL_INFO(dev)->gen >= 4) {
3031	serge	2039	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2040	obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	2041	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2042	I915_WRITE(DSPLINOFF(plane), linear_offset);
2327	Serge	2043	} else
3031	serge	2044	I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2327	Serge	2045	POSTING_READ(reg);
		2046
		2047	return 0;
		2048	}
		2049
		2050	static int ironlake_update_plane(struct drm_crtc *crtc,
		2051	struct drm_framebuffer *fb, int x, int y)
		2052	{
		2053	struct drm_device *dev = crtc->dev;
		2054	struct drm_i915_private *dev_priv = dev->dev_private;
		2055	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2056	struct intel_framebuffer *intel_fb;
		2057	struct drm_i915_gem_object *obj;
		2058	int plane = intel_crtc->plane;
3031	serge	2059	unsigned long linear_offset;
2327	Serge	2060	u32 dspcntr;
		2061	u32 reg;
		2062
		2063	switch (plane) {
		2064	case 0:
		2065	case 1:
2342	Serge	2066	case 2:
2327	Serge	2067	break;
		2068	default:
		2069	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2070	return -EINVAL;
		2071	}
		2072
		2073	intel_fb = to_intel_framebuffer(fb);
		2074	obj = intel_fb->obj;
		2075
		2076	reg = DSPCNTR(plane);
		2077	dspcntr = I915_READ(reg);
		2078	/* Mask out pixel format bits in case we change it */
		2079	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2080	switch (fb->bits_per_pixel) {
		2081	case 8:
		2082	dspcntr \|= DISPPLANE_8BPP;
		2083	break;
		2084	case 16:
		2085	if (fb->depth != 16)
		2086	return -EINVAL;
		2087
		2088	dspcntr \|= DISPPLANE_16BPP;
		2089	break;
		2090	case 24:
		2091	case 32:
		2092	if (fb->depth == 24)
		2093	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2094	else if (fb->depth == 30)
		2095	dspcntr \|= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		2096	else
		2097	return -EINVAL;
		2098	break;
		2099	default:
		2100	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2101	return -EINVAL;
		2102	}
		2103
		2104	// if (obj->tiling_mode != I915_TILING_NONE)
		2105	// dspcntr \|= DISPPLANE_TILED;
		2106	// else
		2107	dspcntr &= ~DISPPLANE_TILED;
		2108
		2109	/* must disable */
		2110	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2111
		2112	I915_WRITE(reg, dspcntr);
		2113
3031	serge	2114	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
		2115	intel_crtc->dspaddr_offset =
		2116	gen4_compute_dspaddr_offset_xtiled(&x, &y,
		2117	fb->bits_per_pixel / 8,
		2118	fb->pitches[0]);
		2119	linear_offset -= intel_crtc->dspaddr_offset;
2327	Serge	2120
3031	serge	2121	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		2122	obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2342	Serge	2123	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3031	serge	2124	I915_MODIFY_DISPBASE(DSPSURF(plane),
		2125	obj->gtt_offset + intel_crtc->dspaddr_offset);
2330	Serge	2126	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
3031	serge	2127	I915_WRITE(DSPLINOFF(plane), linear_offset);
2330	Serge	2128	POSTING_READ(reg);
2327	Serge	2129
		2130	return 0;
		2131	}
		2132
		2133	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2134	static int
		2135	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2136	int x, int y, enum mode_set_atomic state)
		2137	{
		2138	struct drm_device *dev = crtc->dev;
		2139	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2140
		2141	if (dev_priv->display.disable_fbc)
		2142	dev_priv->display.disable_fbc(dev);
		2143	intel_increase_pllclock(crtc);
		2144
		2145	return dev_priv->display.update_plane(crtc, fb, x, y);
		2146	}
		2147
		2148	#if 0
		2149	static int
		2150	intel_finish_fb(struct drm_framebuffer *old_fb)
		2151	{
		2152	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
		2153	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		2154	bool was_interruptible = dev_priv->mm.interruptible;
2327	Serge	2155	int ret;
		2156
3031	serge	2157	wait_event(dev_priv->pending_flip_queue,
		2158	atomic_read(&dev_priv->mm.wedged) \|\|
		2159	atomic_read(&obj->pending_flip) == 0);
2327	Serge	2160
3031	serge	2161	/* Big Hammer, we also need to ensure that any pending
		2162	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		2163	* current scanout is retired before unpinning the old
		2164	* framebuffer.
		2165	*
		2166	* This should only fail upon a hung GPU, in which case we
		2167	* can safely continue.
		2168	*/
		2169	dev_priv->mm.interruptible = false;
		2170	ret = i915_gem_object_finish_gpu(obj);
		2171	dev_priv->mm.interruptible = was_interruptible;
2327	Serge	2172
3031	serge	2173	return ret;
2327	Serge	2174	}
3031	serge	2175	#endif
2327	Serge	2176
		2177	static int
		2178	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
3031	serge	2179	struct drm_framebuffer *fb)
2327	Serge	2180	{
		2181	struct drm_device *dev = crtc->dev;
3031	serge	2182	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2183	struct drm_i915_master_private *master_priv;
		2184	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	2185	struct drm_framebuffer *old_fb;
2342	Serge	2186	int ret;
2327	Serge	2187
		2188	/* no fb bound */
3031	serge	2189	if (!fb) {
2327	Serge	2190	DRM_ERROR("No FB bound\n");
		2191	return 0;
		2192	}
		2193
3031	serge	2194	if(intel_crtc->plane > dev_priv->num_pipe) {
		2195	DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
		2196	intel_crtc->plane,
		2197	dev_priv->num_pipe);
2327	Serge	2198	return -EINVAL;
		2199	}
		2200
		2201	mutex_lock(&dev->struct_mutex);
3031	serge	2202	// ret = intel_pin_and_fence_fb_obj(dev,
		2203	// to_intel_framebuffer(fb)->obj,
		2204	// NULL);
		2205	// if (ret != 0) {
		2206	// mutex_unlock(&dev->struct_mutex);
		2207	// DRM_ERROR("pin & fence failed\n");
		2208	// return ret;
		2209	// }
2327	Serge	2210
3031	serge	2211	// if (crtc->fb)
		2212	// intel_finish_fb(crtc->fb);
		2213
		2214	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327	Serge	2215	if (ret) {
3031	serge	2216	intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2327	Serge	2217	mutex_unlock(&dev->struct_mutex);
		2218	DRM_ERROR("failed to update base address\n");
2336	Serge	2219	LEAVE();
2327	Serge	2220	return ret;
		2221	}
		2222
3031	serge	2223	old_fb = crtc->fb;
		2224	crtc->fb = fb;
		2225	crtc->x = x;
		2226	crtc->y = y;
		2227
		2228	if (old_fb) {
		2229	intel_wait_for_vblank(dev, intel_crtc->pipe);
		2230	intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
		2231	}
		2232
		2233	intel_update_fbc(dev);
2336	Serge	2234	mutex_unlock(&dev->struct_mutex);
2327	Serge	2235
2336	Serge	2236	return 0;
2327	Serge	2237	}
		2238
		2239	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
		2240	{
		2241	struct drm_device *dev = crtc->dev;
		2242	struct drm_i915_private *dev_priv = dev->dev_private;
		2243	u32 dpa_ctl;
		2244
		2245	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
		2246	dpa_ctl = I915_READ(DP_A);
		2247	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		2248
		2249	if (clock < 200000) {
		2250	u32 temp;
		2251	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
		2252	/* workaround for 160Mhz:
		2253	1) program 0x4600c bits 15:0 = 0x8124
		2254	2) program 0x46010 bit 0 = 1
		2255	3) program 0x46034 bit 24 = 1
		2256	4) program 0x64000 bit 14 = 1
		2257	*/
		2258	temp = I915_READ(0x4600c);
		2259	temp &= 0xffff0000;
		2260	I915_WRITE(0x4600c, temp \| 0x8124);
		2261
		2262	temp = I915_READ(0x46010);
		2263	I915_WRITE(0x46010, temp \| 1);
		2264
		2265	temp = I915_READ(0x46034);
		2266	I915_WRITE(0x46034, temp \| (1 << 24));
		2267	} else {
		2268	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
		2269	}
		2270	I915_WRITE(DP_A, dpa_ctl);
		2271
		2272	POSTING_READ(DP_A);
		2273	udelay(500);
		2274	}
		2275
		2276	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2277	{
		2278	struct drm_device *dev = crtc->dev;
		2279	struct drm_i915_private *dev_priv = dev->dev_private;
		2280	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2281	int pipe = intel_crtc->pipe;
		2282	u32 reg, temp;
		2283
		2284	/* enable normal train */
		2285	reg = FDI_TX_CTL(pipe);
		2286	temp = I915_READ(reg);
		2287	if (IS_IVYBRIDGE(dev)) {
		2288	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2289	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2290	} else {
		2291	temp &= ~FDI_LINK_TRAIN_NONE;
		2292	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2293	}
		2294	I915_WRITE(reg, temp);
		2295
		2296	reg = FDI_RX_CTL(pipe);
		2297	temp = I915_READ(reg);
		2298	if (HAS_PCH_CPT(dev)) {
		2299	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2300	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2301	} else {
		2302	temp &= ~FDI_LINK_TRAIN_NONE;
		2303	temp \|= FDI_LINK_TRAIN_NONE;
		2304	}
		2305	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2306
		2307	/* wait one idle pattern time */
		2308	POSTING_READ(reg);
		2309	udelay(1000);
		2310
		2311	/* IVB wants error correction enabled */
		2312	if (IS_IVYBRIDGE(dev))
		2313	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2314	FDI_FE_ERRC_ENABLE);
		2315	}
		2316
		2317	static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
		2318	{
		2319	struct drm_i915_private *dev_priv = dev->dev_private;
		2320	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2321
		2322	flags \|= FDI_PHASE_SYNC_OVR(pipe);
		2323	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
		2324	flags \|= FDI_PHASE_SYNC_EN(pipe);
		2325	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
		2326	POSTING_READ(SOUTH_CHICKEN1);
		2327	}
		2328
		2329	/* The FDI link training functions for ILK/Ibexpeak. */
		2330	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2331	{
		2332	struct drm_device *dev = crtc->dev;
		2333	struct drm_i915_private *dev_priv = dev->dev_private;
		2334	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2335	int pipe = intel_crtc->pipe;
		2336	int plane = intel_crtc->plane;
		2337	u32 reg, temp, tries;
		2338
		2339	/* FDI needs bits from pipe & plane first */
		2340	assert_pipe_enabled(dev_priv, pipe);
		2341	assert_plane_enabled(dev_priv, plane);
		2342
		2343	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2344	for train result */
		2345	reg = FDI_RX_IMR(pipe);
		2346	temp = I915_READ(reg);
		2347	temp &= ~FDI_RX_SYMBOL_LOCK;
		2348	temp &= ~FDI_RX_BIT_LOCK;
		2349	I915_WRITE(reg, temp);
		2350	I915_READ(reg);
		2351	udelay(150);
		2352
		2353	/* enable CPU FDI TX and PCH FDI RX */
		2354	reg = FDI_TX_CTL(pipe);
		2355	temp = I915_READ(reg);
		2356	temp &= ~(7 << 19);
		2357	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2358	temp &= ~FDI_LINK_TRAIN_NONE;
		2359	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2360	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2361
		2362	reg = FDI_RX_CTL(pipe);
		2363	temp = I915_READ(reg);
		2364	temp &= ~FDI_LINK_TRAIN_NONE;
		2365	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2366	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2367
		2368	POSTING_READ(reg);
		2369	udelay(150);
		2370
		2371	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2372	if (HAS_PCH_IBX(dev)) {
		2373	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2374	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2375	FDI_RX_PHASE_SYNC_POINTER_EN);
		2376	}
		2377
		2378	reg = FDI_RX_IIR(pipe);
		2379	for (tries = 0; tries < 5; tries++) {
		2380	temp = I915_READ(reg);
		2381	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2382
		2383	if ((temp & FDI_RX_BIT_LOCK)) {
		2384	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2385	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2386	break;
		2387	}
		2388	}
		2389	if (tries == 5)
		2390	DRM_ERROR("FDI train 1 fail!\n");
		2391
		2392	/* Train 2 */
		2393	reg = FDI_TX_CTL(pipe);
		2394	temp = I915_READ(reg);
		2395	temp &= ~FDI_LINK_TRAIN_NONE;
		2396	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2397	I915_WRITE(reg, temp);
		2398
		2399	reg = FDI_RX_CTL(pipe);
		2400	temp = I915_READ(reg);
		2401	temp &= ~FDI_LINK_TRAIN_NONE;
		2402	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2403	I915_WRITE(reg, temp);
		2404
		2405	POSTING_READ(reg);
		2406	udelay(150);
		2407
		2408	reg = FDI_RX_IIR(pipe);
		2409	for (tries = 0; tries < 5; tries++) {
		2410	temp = I915_READ(reg);
		2411	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2412
		2413	if (temp & FDI_RX_SYMBOL_LOCK) {
		2414	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2415	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2416	break;
		2417	}
		2418	}
		2419	if (tries == 5)
		2420	DRM_ERROR("FDI train 2 fail!\n");
		2421
		2422	DRM_DEBUG_KMS("FDI train done\n");
		2423
		2424	}
		2425
2342	Serge	2426	static const int snb_b_fdi_train_param[] = {
2327	Serge	2427	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2428	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2429	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2430	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2431	};
		2432
		2433	/* The FDI link training functions for SNB/Cougarpoint. */
		2434	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2435	{
		2436	struct drm_device *dev = crtc->dev;
		2437	struct drm_i915_private *dev_priv = dev->dev_private;
		2438	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2439	int pipe = intel_crtc->pipe;
3031	serge	2440	u32 reg, temp, i, retry;
2327	Serge	2441
		2442	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2443	for train result */
		2444	reg = FDI_RX_IMR(pipe);
		2445	temp = I915_READ(reg);
		2446	temp &= ~FDI_RX_SYMBOL_LOCK;
		2447	temp &= ~FDI_RX_BIT_LOCK;
		2448	I915_WRITE(reg, temp);
		2449
		2450	POSTING_READ(reg);
		2451	udelay(150);
		2452
		2453	/* enable CPU FDI TX and PCH FDI RX */
		2454	reg = FDI_TX_CTL(pipe);
		2455	temp = I915_READ(reg);
		2456	temp &= ~(7 << 19);
		2457	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2458	temp &= ~FDI_LINK_TRAIN_NONE;
		2459	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2460	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2461	/* SNB-B */
		2462	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2463	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2464
		2465	reg = FDI_RX_CTL(pipe);
		2466	temp = I915_READ(reg);
		2467	if (HAS_PCH_CPT(dev)) {
		2468	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2469	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2470	} else {
		2471	temp &= ~FDI_LINK_TRAIN_NONE;
		2472	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2473	}
		2474	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2475
		2476	POSTING_READ(reg);
		2477	udelay(150);
		2478
		2479	if (HAS_PCH_CPT(dev))
		2480	cpt_phase_pointer_enable(dev, pipe);
		2481
2342	Serge	2482	for (i = 0; i < 4; i++) {
2327	Serge	2483	reg = FDI_TX_CTL(pipe);
		2484	temp = I915_READ(reg);
		2485	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2486	temp \|= snb_b_fdi_train_param[i];
		2487	I915_WRITE(reg, temp);
		2488
		2489	POSTING_READ(reg);
		2490	udelay(500);
		2491
3031	serge	2492	for (retry = 0; retry < 5; retry++) {
2327	Serge	2493	reg = FDI_RX_IIR(pipe);
		2494	temp = I915_READ(reg);
		2495	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2496	if (temp & FDI_RX_BIT_LOCK) {
		2497	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2498	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2499	break;
		2500	}
3031	serge	2501	udelay(50);
		2502	}
		2503	if (retry < 5)
		2504	break;
2327	Serge	2505	}
		2506	if (i == 4)
		2507	DRM_ERROR("FDI train 1 fail!\n");
		2508
		2509	/* Train 2 */
		2510	reg = FDI_TX_CTL(pipe);
		2511	temp = I915_READ(reg);
		2512	temp &= ~FDI_LINK_TRAIN_NONE;
		2513	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2514	if (IS_GEN6(dev)) {
		2515	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2516	/* SNB-B */
		2517	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2518	}
		2519	I915_WRITE(reg, temp);
		2520
		2521	reg = FDI_RX_CTL(pipe);
		2522	temp = I915_READ(reg);
		2523	if (HAS_PCH_CPT(dev)) {
		2524	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2525	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2526	} else {
		2527	temp &= ~FDI_LINK_TRAIN_NONE;
		2528	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2529	}
		2530	I915_WRITE(reg, temp);
		2531
		2532	POSTING_READ(reg);
		2533	udelay(150);
		2534
2342	Serge	2535	for (i = 0; i < 4; i++) {
2327	Serge	2536	reg = FDI_TX_CTL(pipe);
		2537	temp = I915_READ(reg);
		2538	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2539	temp \|= snb_b_fdi_train_param[i];
		2540	I915_WRITE(reg, temp);
		2541
		2542	POSTING_READ(reg);
		2543	udelay(500);
		2544
3031	serge	2545	for (retry = 0; retry < 5; retry++) {
2327	Serge	2546	reg = FDI_RX_IIR(pipe);
		2547	temp = I915_READ(reg);
		2548	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2549	if (temp & FDI_RX_SYMBOL_LOCK) {
		2550	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2551	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2552	break;
		2553	}
3031	serge	2554	udelay(50);
		2555	}
		2556	if (retry < 5)
		2557	break;
2327	Serge	2558	}
		2559	if (i == 4)
		2560	DRM_ERROR("FDI train 2 fail!\n");
		2561
		2562	DRM_DEBUG_KMS("FDI train done.\n");
		2563	}
		2564
		2565	/* Manual link training for Ivy Bridge A0 parts */
		2566	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2567	{
		2568	struct drm_device *dev = crtc->dev;
		2569	struct drm_i915_private *dev_priv = dev->dev_private;
		2570	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2571	int pipe = intel_crtc->pipe;
		2572	u32 reg, temp, i;
		2573
		2574	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2575	for train result */
		2576	reg = FDI_RX_IMR(pipe);
		2577	temp = I915_READ(reg);
		2578	temp &= ~FDI_RX_SYMBOL_LOCK;
		2579	temp &= ~FDI_RX_BIT_LOCK;
		2580	I915_WRITE(reg, temp);
		2581
		2582	POSTING_READ(reg);
		2583	udelay(150);
		2584
		2585	/* enable CPU FDI TX and PCH FDI RX */
		2586	reg = FDI_TX_CTL(pipe);
		2587	temp = I915_READ(reg);
		2588	temp &= ~(7 << 19);
		2589	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2590	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2591	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2592	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2593	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2342	Serge	2594	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2595	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2596
		2597	reg = FDI_RX_CTL(pipe);
		2598	temp = I915_READ(reg);
		2599	temp &= ~FDI_LINK_TRAIN_AUTO;
		2600	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2601	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342	Serge	2602	temp \|= FDI_COMPOSITE_SYNC;
2327	Serge	2603	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2604
		2605	POSTING_READ(reg);
		2606	udelay(150);
		2607
		2608	if (HAS_PCH_CPT(dev))
		2609	cpt_phase_pointer_enable(dev, pipe);
		2610
2342	Serge	2611	for (i = 0; i < 4; i++) {
2327	Serge	2612	reg = FDI_TX_CTL(pipe);
		2613	temp = I915_READ(reg);
		2614	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2615	temp \|= snb_b_fdi_train_param[i];
		2616	I915_WRITE(reg, temp);
		2617
		2618	POSTING_READ(reg);
		2619	udelay(500);
		2620
		2621	reg = FDI_RX_IIR(pipe);
		2622	temp = I915_READ(reg);
		2623	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2624
		2625	if (temp & FDI_RX_BIT_LOCK \|\|
		2626	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2627	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2628	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2629	break;
		2630	}
		2631	}
		2632	if (i == 4)
		2633	DRM_ERROR("FDI train 1 fail!\n");
		2634
		2635	/* Train 2 */
		2636	reg = FDI_TX_CTL(pipe);
		2637	temp = I915_READ(reg);
		2638	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2639	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2640	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2641	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2642	I915_WRITE(reg, temp);
		2643
		2644	reg = FDI_RX_CTL(pipe);
		2645	temp = I915_READ(reg);
		2646	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2647	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2648	I915_WRITE(reg, temp);
		2649
		2650	POSTING_READ(reg);
		2651	udelay(150);
		2652
2342	Serge	2653	for (i = 0; i < 4; i++) {
2327	Serge	2654	reg = FDI_TX_CTL(pipe);
		2655	temp = I915_READ(reg);
		2656	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2657	temp \|= snb_b_fdi_train_param[i];
		2658	I915_WRITE(reg, temp);
		2659
		2660	POSTING_READ(reg);
		2661	udelay(500);
		2662
		2663	reg = FDI_RX_IIR(pipe);
		2664	temp = I915_READ(reg);
		2665	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2666
		2667	if (temp & FDI_RX_SYMBOL_LOCK) {
		2668	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2669	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2670	break;
		2671	}
		2672	}
		2673	if (i == 4)
		2674	DRM_ERROR("FDI train 2 fail!\n");
		2675
		2676	DRM_DEBUG_KMS("FDI train done.\n");
		2677	}
		2678
3031	serge	2679	static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2327	Serge	2680	{
3031	serge	2681	struct drm_device *dev = intel_crtc->base.dev;
2327	Serge	2682	struct drm_i915_private *dev_priv = dev->dev_private;
		2683	int pipe = intel_crtc->pipe;
		2684	u32 reg, temp;
		2685
		2686	/* Write the TU size bits so error detection works */
		2687	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		2688	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		2689
		2690	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2691	reg = FDI_RX_CTL(pipe);
		2692	temp = I915_READ(reg);
		2693	temp &= ~((0x7 << 19) \| (0x7 << 16));
		2694	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2695	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2696	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2697
		2698	POSTING_READ(reg);
		2699	udelay(200);
		2700
		2701	/* Switch from Rawclk to PCDclk */
		2702	temp = I915_READ(reg);
		2703	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2704
		2705	POSTING_READ(reg);
		2706	udelay(200);
		2707
3031	serge	2708	/* On Haswell, the PLL configuration for ports and pipes is handled
		2709	* separately, as part of DDI setup */
		2710	if (!IS_HASWELL(dev)) {
2327	Serge	2711	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2712	reg = FDI_TX_CTL(pipe);
		2713	temp = I915_READ(reg);
		2714	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2715	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2716
		2717	POSTING_READ(reg);
		2718	udelay(100);
		2719	}
3031	serge	2720	}
2327	Serge	2721	}
		2722
3031	serge	2723	static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
		2724	{
		2725	struct drm_device *dev = intel_crtc->base.dev;
		2726	struct drm_i915_private *dev_priv = dev->dev_private;
		2727	int pipe = intel_crtc->pipe;
		2728	u32 reg, temp;
		2729
		2730	/* Switch from PCDclk to Rawclk */
		2731	reg = FDI_RX_CTL(pipe);
		2732	temp = I915_READ(reg);
		2733	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		2734
		2735	/* Disable CPU FDI TX PLL */
		2736	reg = FDI_TX_CTL(pipe);
		2737	temp = I915_READ(reg);
		2738	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		2739
		2740	POSTING_READ(reg);
		2741	udelay(100);
		2742
		2743	reg = FDI_RX_CTL(pipe);
		2744	temp = I915_READ(reg);
		2745	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		2746
		2747	/* Wait for the clocks to turn off. */
		2748	POSTING_READ(reg);
		2749	udelay(100);
		2750	}
		2751
2327	Serge	2752	static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
		2753	{
		2754	struct drm_i915_private *dev_priv = dev->dev_private;
		2755	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2756
		2757	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
		2758	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
		2759	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
		2760	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
		2761	POSTING_READ(SOUTH_CHICKEN1);
		2762	}
		2763	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2764	{
		2765	struct drm_device *dev = crtc->dev;
		2766	struct drm_i915_private *dev_priv = dev->dev_private;
		2767	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2768	int pipe = intel_crtc->pipe;
		2769	u32 reg, temp;
		2770
		2771	/* disable CPU FDI tx and PCH FDI rx */
		2772	reg = FDI_TX_CTL(pipe);
		2773	temp = I915_READ(reg);
		2774	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2775	POSTING_READ(reg);
		2776
		2777	reg = FDI_RX_CTL(pipe);
		2778	temp = I915_READ(reg);
		2779	temp &= ~(0x7 << 16);
		2780	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2781	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2782
		2783	POSTING_READ(reg);
		2784	udelay(100);
		2785
		2786	/* Ironlake workaround, disable clock pointer after downing FDI */
		2787	if (HAS_PCH_IBX(dev)) {
		2788	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2789	I915_WRITE(FDI_RX_CHICKEN(pipe),
		2790	I915_READ(FDI_RX_CHICKEN(pipe) &
		2791	~FDI_RX_PHASE_SYNC_POINTER_EN));
		2792	} else if (HAS_PCH_CPT(dev)) {
		2793	cpt_phase_pointer_disable(dev, pipe);
		2794	}
		2795
		2796	/* still set train pattern 1 */
		2797	reg = FDI_TX_CTL(pipe);
		2798	temp = I915_READ(reg);
		2799	temp &= ~FDI_LINK_TRAIN_NONE;
		2800	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2801	I915_WRITE(reg, temp);
		2802
		2803	reg = FDI_RX_CTL(pipe);
		2804	temp = I915_READ(reg);
		2805	if (HAS_PCH_CPT(dev)) {
		2806	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2807	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2808	} else {
		2809	temp &= ~FDI_LINK_TRAIN_NONE;
		2810	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2811	}
		2812	/* BPC in FDI rx is consistent with that in PIPECONF */
		2813	temp &= ~(0x07 << 16);
		2814	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2815	I915_WRITE(reg, temp);
		2816
		2817	POSTING_READ(reg);
		2818	udelay(100);
		2819	}
		2820
3031	serge	2821	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2327	Serge	2822	{
3031	serge	2823	struct drm_device *dev = crtc->dev;
2327	Serge	2824	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	2825	unsigned long flags;
		2826	bool pending;
2327	Serge	2827
3031	serge	2828	if (atomic_read(&dev_priv->mm.wedged))
		2829	return false;
2327	Serge	2830
3031	serge	2831	spin_lock_irqsave(&dev->event_lock, flags);
		2832	pending = to_intel_crtc(crtc)->unpin_work != NULL;
		2833	spin_unlock_irqrestore(&dev->event_lock, flags);
		2834
		2835	return pending;
2327	Serge	2836	}
		2837
3031	serge	2838	#if 0
2327	Serge	2839	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2840	{
3031	serge	2841	struct drm_device *dev = crtc->dev;
		2842	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	2843
		2844	if (crtc->fb == NULL)
		2845	return;
		2846
2360	Serge	2847	wait_event(dev_priv->pending_flip_queue,
3031	serge	2848	!intel_crtc_has_pending_flip(crtc));
		2849
		2850	mutex_lock(&dev->struct_mutex);
		2851	intel_finish_fb(crtc->fb);
		2852	mutex_unlock(&dev->struct_mutex);
2327	Serge	2853	}
3031	serge	2854	#endif
2327	Serge	2855
		2856	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
		2857	{
		2858	struct drm_device *dev = crtc->dev;
3031	serge	2859	struct intel_encoder *intel_encoder;
2327	Serge	2860
		2861	/*
		2862	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
		2863	* must be driven by its own crtc; no sharing is possible.
		2864	*/
3031	serge	2865	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2327	Serge	2866
3031	serge	2867	/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
		2868	* CPU handles all others */
		2869	if (IS_HASWELL(dev)) {
		2870	/* It is still unclear how this will work on PPT, so throw up a warning */
		2871	WARN_ON(!HAS_PCH_LPT(dev));
		2872
		2873	if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
		2874	DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
		2875	return true;
		2876	} else {
		2877	DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
		2878	intel_encoder->type);
		2879	return false;
		2880	}
		2881	}
		2882
		2883	switch (intel_encoder->type) {
2327	Serge	2884	case INTEL_OUTPUT_EDP:
3031	serge	2885	if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2327	Serge	2886	return false;
		2887	continue;
		2888	}
		2889	}
		2890
		2891	return true;
		2892	}
		2893
3031	serge	2894	/* Program iCLKIP clock to the desired frequency */
		2895	static void lpt_program_iclkip(struct drm_crtc *crtc)
		2896	{
		2897	struct drm_device *dev = crtc->dev;
		2898	struct drm_i915_private *dev_priv = dev->dev_private;
		2899	u32 divsel, phaseinc, auxdiv, phasedir = 0;
		2900	u32 temp;
		2901
		2902	/* It is necessary to ungate the pixclk gate prior to programming
		2903	* the divisors, and gate it back when it is done.
		2904	*/
		2905	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
		2906
		2907	/* Disable SSCCTL */
		2908	intel_sbi_write(dev_priv, SBI_SSCCTL6,
		2909	intel_sbi_read(dev_priv, SBI_SSCCTL6) \|
		2910	SBI_SSCCTL_DISABLE);
		2911
		2912	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
		2913	if (crtc->mode.clock == 20000) {
		2914	auxdiv = 1;
		2915	divsel = 0x41;
		2916	phaseinc = 0x20;
		2917	} else {
		2918	/* The iCLK virtual clock root frequency is in MHz,
		2919	* but the crtc->mode.clock in in KHz. To get the divisors,
		2920	* it is necessary to divide one by another, so we
		2921	* convert the virtual clock precision to KHz here for higher
		2922	* precision.
		2923	*/
		2924	u32 iclk_virtual_root_freq = 172800 * 1000;
		2925	u32 iclk_pi_range = 64;
		2926	u32 desired_divisor, msb_divisor_value, pi_value;
		2927
		2928	desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		2929	msb_divisor_value = desired_divisor / iclk_pi_range;
		2930	pi_value = desired_divisor % iclk_pi_range;
		2931
		2932	auxdiv = 0;
		2933	divsel = msb_divisor_value - 2;
		2934	phaseinc = pi_value;
		2935	}
		2936
		2937	/* This should not happen with any sane values */
		2938	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		2939	~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
		2940	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		2941	~SBI_SSCDIVINTPHASE_INCVAL_MASK);
		2942
		2943	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
		2944	crtc->mode.clock,
		2945	auxdiv,
		2946	divsel,
		2947	phasedir,
		2948	phaseinc);
		2949
		2950	/* Program SSCDIVINTPHASE6 */
		2951	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
		2952	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
		2953	temp \|= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
		2954	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
		2955	temp \|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
		2956	temp \|= SBI_SSCDIVINTPHASE_DIR(phasedir);
		2957	temp \|= SBI_SSCDIVINTPHASE_PROPAGATE;
		2958
		2959	intel_sbi_write(dev_priv,
		2960	SBI_SSCDIVINTPHASE6,
		2961	temp);
		2962
		2963	/* Program SSCAUXDIV */
		2964	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
		2965	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
		2966	temp \|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
		2967	intel_sbi_write(dev_priv,
		2968	SBI_SSCAUXDIV6,
		2969	temp);
		2970
		2971
		2972	/* Enable modulator and associated divider */
		2973	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
		2974	temp &= ~SBI_SSCCTL_DISABLE;
		2975	intel_sbi_write(dev_priv,
		2976	SBI_SSCCTL6,
		2977	temp);
		2978
		2979	/* Wait for initialization time */
		2980	udelay(24);
		2981
		2982	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
		2983	}
		2984
2327	Serge	2985	/*
		2986	* Enable PCH resources required for PCH ports:
		2987	* - PCH PLLs
		2988	* - FDI training & RX/TX
		2989	* - update transcoder timings
		2990	* - DP transcoding bits
		2991	* - transcoder
		2992	*/
		2993	static void ironlake_pch_enable(struct drm_crtc *crtc)
		2994	{
		2995	struct drm_device *dev = crtc->dev;
		2996	struct drm_i915_private *dev_priv = dev->dev_private;
		2997	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2998	int pipe = intel_crtc->pipe;
3031	serge	2999	u32 reg, temp;
2327	Serge	3000
3031	serge	3001	assert_transcoder_disabled(dev_priv, pipe);
		3002
2327	Serge	3003	/* For PCH output, training FDI link */
		3004	dev_priv->display.fdi_link_train(crtc);
		3005
3031	serge	3006	intel_enable_pch_pll(intel_crtc);
2327	Serge	3007
3031	serge	3008	if (HAS_PCH_LPT(dev)) {
		3009	DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
		3010	lpt_program_iclkip(crtc);
		3011	} else if (HAS_PCH_CPT(dev)) {
		3012	u32 sel;
2342	Serge	3013
2327	Serge	3014	temp = I915_READ(PCH_DPLL_SEL);
3031	serge	3015	switch (pipe) {
		3016	default:
		3017	case 0:
		3018	temp \|= TRANSA_DPLL_ENABLE;
		3019	sel = TRANSA_DPLLB_SEL;
		3020	break;
		3021	case 1:
		3022	temp \|= TRANSB_DPLL_ENABLE;
		3023	sel = TRANSB_DPLLB_SEL;
		3024	break;
		3025	case 2:
		3026	temp \|= TRANSC_DPLL_ENABLE;
		3027	sel = TRANSC_DPLLB_SEL;
		3028	break;
2342	Serge	3029	}
3031	serge	3030	if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
		3031	temp \|= sel;
		3032	else
		3033	temp &= ~sel;
2327	Serge	3034	I915_WRITE(PCH_DPLL_SEL, temp);
		3035	}
		3036
		3037	/* set transcoder timing, panel must allow it */
		3038	assert_panel_unlocked(dev_priv, pipe);
		3039	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
		3040	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
		3041	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
		3042
		3043	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
		3044	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		3045	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3031	serge	3046	I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2327	Serge	3047
3031	serge	3048	if (!IS_HASWELL(dev))
2327	Serge	3049	intel_fdi_normal_train(crtc);
		3050
		3051	/* For PCH DP, enable TRANS_DP_CTL */
		3052	if (HAS_PCH_CPT(dev) &&
2342	Serge	3053	(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		3054	intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2327	Serge	3055	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
		3056	reg = TRANS_DP_CTL(pipe);
		3057	temp = I915_READ(reg);
		3058	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		3059	TRANS_DP_SYNC_MASK \|
		3060	TRANS_DP_BPC_MASK);
		3061	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		3062	TRANS_DP_ENH_FRAMING);
		3063	temp \|= bpc << 9; /* same format but at 11:9 */
		3064
		3065	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		3066	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		3067	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		3068	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		3069
		3070	switch (intel_trans_dp_port_sel(crtc)) {
		3071	case PCH_DP_B:
		3072	temp \|= TRANS_DP_PORT_SEL_B;
		3073	break;
		3074	case PCH_DP_C:
		3075	temp \|= TRANS_DP_PORT_SEL_C;
		3076	break;
		3077	case PCH_DP_D:
		3078	temp \|= TRANS_DP_PORT_SEL_D;
		3079	break;
		3080	default:
		3081	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
		3082	temp \|= TRANS_DP_PORT_SEL_B;
		3083	break;
		3084	}
		3085
		3086	I915_WRITE(reg, temp);
		3087	}
		3088
		3089	intel_enable_transcoder(dev_priv, pipe);
		3090	}
		3091
3031	serge	3092	static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
		3093	{
		3094	struct intel_pch_pll *pll = intel_crtc->pch_pll;
		3095
		3096	if (pll == NULL)
		3097	return;
		3098
		3099	if (pll->refcount == 0) {
		3100	WARN(1, "bad PCH PLL refcount\n");
		3101	return;
		3102	}
		3103
		3104	--pll->refcount;
		3105	intel_crtc->pch_pll = NULL;
		3106	}
		3107
		3108	static struct intel_pch_pll intel_get_pch_pll(struct intel_crtc intel_crtc, u32 dpll, u32 fp)
		3109	{
		3110	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
		3111	struct intel_pch_pll *pll;
		3112	int i;
		3113
		3114	pll = intel_crtc->pch_pll;
		3115	if (pll) {
		3116	DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
		3117	intel_crtc->base.base.id, pll->pll_reg);
		3118	goto prepare;
		3119	}
		3120
		3121	if (HAS_PCH_IBX(dev_priv->dev)) {
		3122	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		3123	i = intel_crtc->pipe;
		3124	pll = &dev_priv->pch_plls[i];
		3125
		3126	DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
		3127	intel_crtc->base.base.id, pll->pll_reg);
		3128
		3129	goto found;
		3130	}
		3131
		3132	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3133	pll = &dev_priv->pch_plls[i];
		3134
		3135	/* Only want to check enabled timings first */
		3136	if (pll->refcount == 0)
		3137	continue;
		3138
		3139	if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		3140	fp == I915_READ(pll->fp0_reg)) {
		3141	DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
		3142	intel_crtc->base.base.id,
		3143	pll->pll_reg, pll->refcount, pll->active);
		3144
		3145	goto found;
		3146	}
		3147	}
		3148
		3149	/* Ok no matching timings, maybe there's a free one? */
		3150	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		3151	pll = &dev_priv->pch_plls[i];
		3152	if (pll->refcount == 0) {
		3153	DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
		3154	intel_crtc->base.base.id, pll->pll_reg);
		3155	goto found;
		3156	}
		3157	}
		3158
		3159	return NULL;
		3160
		3161	found:
		3162	intel_crtc->pch_pll = pll;
		3163	pll->refcount++;
		3164	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
		3165	prepare: /* separate function? */
		3166	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
		3167
		3168	/* Wait for the clocks to stabilize before rewriting the regs */
		3169	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3170	POSTING_READ(pll->pll_reg);
		3171	udelay(150);
		3172
		3173	I915_WRITE(pll->fp0_reg, fp);
		3174	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
		3175	pll->on = false;
		3176	return pll;
		3177	}
		3178
2342	Serge	3179	void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
		3180	{
		3181	struct drm_i915_private *dev_priv = dev->dev_private;
		3182	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
		3183	u32 temp;
		3184
		3185	temp = I915_READ(dslreg);
		3186	udelay(500);
		3187	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		3188	/* Without this, mode sets may fail silently on FDI */
		3189	I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
		3190	udelay(250);
		3191	I915_WRITE(tc2reg, 0);
		3192	if (wait_for(I915_READ(dslreg) != temp, 5))
		3193	DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
		3194	}
		3195	}
		3196
2327	Serge	3197	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		3198	{
		3199	struct drm_device *dev = crtc->dev;
		3200	struct drm_i915_private *dev_priv = dev->dev_private;
		3201	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3202	struct intel_encoder *encoder;
2327	Serge	3203	int pipe = intel_crtc->pipe;
		3204	int plane = intel_crtc->plane;
		3205	u32 temp;
		3206	bool is_pch_port;
		3207
3031	serge	3208	WARN_ON(!crtc->enabled);
		3209
2327	Serge	3210	if (intel_crtc->active)
		3211	return;
		3212
		3213	intel_crtc->active = true;
		3214	intel_update_watermarks(dev);
		3215
		3216	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		3217	temp = I915_READ(PCH_LVDS);
		3218	if ((temp & LVDS_PORT_EN) == 0)
		3219	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
		3220	}
		3221
		3222	is_pch_port = intel_crtc_driving_pch(crtc);
		3223
3031	serge	3224	if (is_pch_port) {
		3225	ironlake_fdi_pll_enable(intel_crtc);
		3226	} else {
		3227	assert_fdi_tx_disabled(dev_priv, pipe);
		3228	assert_fdi_rx_disabled(dev_priv, pipe);
		3229	}
2327	Serge	3230
3031	serge	3231	for_each_encoder_on_crtc(dev, crtc, encoder)
		3232	if (encoder->pre_enable)
		3233	encoder->pre_enable(encoder);
		3234
2327	Serge	3235	/* Enable panel fitting for LVDS */
		3236	if (dev_priv->pch_pf_size &&
		3237	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {
		3238	/* Force use of hard-coded filter coefficients
		3239	* as some pre-programmed values are broken,
		3240	* e.g. x201.
		3241	*/
		3242	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		3243	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		3244	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		3245	}
		3246
		3247	/*
		3248	* On ILK+ LUT must be loaded before the pipe is running but with
		3249	* clocks enabled
		3250	*/
		3251	intel_crtc_load_lut(crtc);
		3252
		3253	intel_enable_pipe(dev_priv, pipe, is_pch_port);
		3254	intel_enable_plane(dev_priv, plane, pipe);
		3255
		3256	if (is_pch_port)
		3257	ironlake_pch_enable(crtc);
		3258
		3259	mutex_lock(&dev->struct_mutex);
		3260	intel_update_fbc(dev);
		3261	mutex_unlock(&dev->struct_mutex);
		3262
		3263	// intel_crtc_update_cursor(crtc, true);
3031	serge	3264
		3265	for_each_encoder_on_crtc(dev, crtc, encoder)
		3266	encoder->enable(encoder);
		3267
		3268	if (HAS_PCH_CPT(dev))
		3269	intel_cpt_verify_modeset(dev, intel_crtc->pipe);
		3270
		3271	/*
		3272	* There seems to be a race in PCH platform hw (at least on some
		3273	* outputs) where an enabled pipe still completes any pageflip right
		3274	* away (as if the pipe is off) instead of waiting for vblank. As soon
		3275	* as the first vblank happend, everything works as expected. Hence just
		3276	* wait for one vblank before returning to avoid strange things
		3277	* happening.
		3278	*/
		3279	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	3280	}
		3281
		3282	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		3283	{
		3284	struct drm_device *dev = crtc->dev;
		3285	struct drm_i915_private *dev_priv = dev->dev_private;
		3286	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3287	struct intel_encoder *encoder;
2327	Serge	3288	int pipe = intel_crtc->pipe;
		3289	int plane = intel_crtc->plane;
		3290	u32 reg, temp;
		3291
3031	serge	3292
2327	Serge	3293	if (!intel_crtc->active)
		3294	return;
		3295
3031	serge	3296	for_each_encoder_on_crtc(dev, crtc, encoder)
		3297	encoder->disable(encoder);
2336	Serge	3298
3031	serge	3299	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3300	// drm_vblank_off(dev, pipe);
		3301	// intel_crtc_update_cursor(crtc, false);
		3302
		3303	intel_disable_plane(dev_priv, plane, pipe);
		3304
		3305	if (dev_priv->cfb_plane == plane)
		3306	intel_disable_fbc(dev);
		3307
		3308	intel_disable_pipe(dev_priv, pipe);
		3309
		3310	/* Disable PF */
		3311	I915_WRITE(PF_CTL(pipe), 0);
		3312	I915_WRITE(PF_WIN_SZ(pipe), 0);
		3313
3031	serge	3314	for_each_encoder_on_crtc(dev, crtc, encoder)
		3315	if (encoder->post_disable)
		3316	encoder->post_disable(encoder);
		3317
2327	Serge	3318	ironlake_fdi_disable(crtc);
		3319
		3320	intel_disable_transcoder(dev_priv, pipe);
		3321
		3322	if (HAS_PCH_CPT(dev)) {
		3323	/* disable TRANS_DP_CTL */
		3324	reg = TRANS_DP_CTL(pipe);
		3325	temp = I915_READ(reg);
		3326	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
		3327	temp \|= TRANS_DP_PORT_SEL_NONE;
		3328	I915_WRITE(reg, temp);
		3329
		3330	/* disable DPLL_SEL */
		3331	temp = I915_READ(PCH_DPLL_SEL);
		3332	switch (pipe) {
		3333	case 0:
2342	Serge	3334	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLB_SEL);
2327	Serge	3335	break;
		3336	case 1:
		3337	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		3338	break;
		3339	case 2:
2342	Serge	3340	/* C shares PLL A or B */
2327	Serge	3341	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
		3342	break;
		3343	default:
		3344	BUG(); /* wtf */
		3345	}
		3346	I915_WRITE(PCH_DPLL_SEL, temp);
		3347	}
		3348
		3349	/* disable PCH DPLL */
3031	serge	3350	intel_disable_pch_pll(intel_crtc);
2327	Serge	3351
3031	serge	3352	ironlake_fdi_pll_disable(intel_crtc);
2327	Serge	3353
		3354	intel_crtc->active = false;
		3355	intel_update_watermarks(dev);
		3356
		3357	mutex_lock(&dev->struct_mutex);
		3358	intel_update_fbc(dev);
		3359	mutex_unlock(&dev->struct_mutex);
2336	Serge	3360
2327	Serge	3361	}
		3362
3031	serge	3363	static void ironlake_crtc_off(struct drm_crtc *crtc)
2327	Serge	3364	{
		3365	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3366	intel_put_pch_pll(intel_crtc);
2327	Serge	3367	}
		3368
		3369	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3370	{
		3371	if (!enable && intel_crtc->overlay) {
		3372	struct drm_device *dev = intel_crtc->base.dev;
		3373	struct drm_i915_private *dev_priv = dev->dev_private;
		3374
		3375	mutex_lock(&dev->struct_mutex);
		3376	dev_priv->mm.interruptible = false;
		3377	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3378	dev_priv->mm.interruptible = true;
		3379	mutex_unlock(&dev->struct_mutex);
		3380	}
		3381
		3382	/* Let userspace switch the overlay on again. In most cases userspace
		3383	* has to recompute where to put it anyway.
		3384	*/
		3385	}
		3386
		3387	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3388	{
		3389	struct drm_device *dev = crtc->dev;
		3390	struct drm_i915_private *dev_priv = dev->dev_private;
		3391	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3392	struct intel_encoder *encoder;
2327	Serge	3393	int pipe = intel_crtc->pipe;
		3394	int plane = intel_crtc->plane;
		3395
3031	serge	3396	WARN_ON(!crtc->enabled);
		3397
2327	Serge	3398	if (intel_crtc->active)
		3399	return;
		3400
		3401	intel_crtc->active = true;
		3402	intel_update_watermarks(dev);
		3403
		3404	intel_enable_pll(dev_priv, pipe);
		3405	intel_enable_pipe(dev_priv, pipe, false);
		3406	intel_enable_plane(dev_priv, plane, pipe);
		3407
		3408	intel_crtc_load_lut(crtc);
		3409	intel_update_fbc(dev);
		3410
		3411	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3412	intel_crtc_dpms_overlay(intel_crtc, true);
		3413	// intel_crtc_update_cursor(crtc, true);
3031	serge	3414
		3415	for_each_encoder_on_crtc(dev, crtc, encoder)
		3416	encoder->enable(encoder);
2327	Serge	3417	}
		3418
		3419	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3420	{
		3421	struct drm_device *dev = crtc->dev;
		3422	struct drm_i915_private *dev_priv = dev->dev_private;
		3423	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031	serge	3424	struct intel_encoder *encoder;
2327	Serge	3425	int pipe = intel_crtc->pipe;
		3426	int plane = intel_crtc->plane;
		3427
3031	serge	3428
2327	Serge	3429	if (!intel_crtc->active)
		3430	return;
		3431
3031	serge	3432	for_each_encoder_on_crtc(dev, crtc, encoder)
		3433	encoder->disable(encoder);
		3434
2327	Serge	3435	/* Give the overlay scaler a chance to disable if it's on this pipe */
3031	serge	3436	// intel_crtc_wait_for_pending_flips(crtc);
2327	Serge	3437	// drm_vblank_off(dev, pipe);
		3438	intel_crtc_dpms_overlay(intel_crtc, false);
		3439	// intel_crtc_update_cursor(crtc, false);
		3440
		3441	if (dev_priv->cfb_plane == plane)
		3442	intel_disable_fbc(dev);
		3443
		3444	intel_disable_plane(dev_priv, plane, pipe);
		3445	intel_disable_pipe(dev_priv, pipe);
		3446	intel_disable_pll(dev_priv, pipe);
		3447
		3448	intel_crtc->active = false;
		3449	intel_update_fbc(dev);
		3450	intel_update_watermarks(dev);
		3451	}
		3452
3031	serge	3453	static void i9xx_crtc_off(struct drm_crtc *crtc)
2327	Serge	3454	{
		3455	}
		3456
3031	serge	3457	static void intel_crtc_update_sarea(struct drm_crtc *crtc,
		3458	bool enabled)
2330	Serge	3459	{
		3460	struct drm_device *dev = crtc->dev;
		3461	struct drm_i915_master_private *master_priv;
		3462	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3463	int pipe = intel_crtc->pipe;
2327	Serge	3464
		3465
2340	Serge	3466	#if 0
2330	Serge	3467	if (!dev->primary->master)
		3468	return;
2327	Serge	3469
2330	Serge	3470	master_priv = dev->primary->master->driver_priv;
		3471	if (!master_priv->sarea_priv)
		3472	return;
2327	Serge	3473
2330	Serge	3474	switch (pipe) {
		3475	case 0:
		3476	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3477	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3478	break;
		3479	case 1:
		3480	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3481	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3482	break;
		3483	default:
		3484	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3485	break;
		3486	}
2340	Serge	3487	#endif
		3488
2330	Serge	3489	}
2327	Serge	3490
3031	serge	3491	/**
		3492	* Sets the power management mode of the pipe and plane.
		3493	*/
		3494	void intel_crtc_update_dpms(struct drm_crtc *crtc)
		3495	{
		3496	struct drm_device *dev = crtc->dev;
		3497	struct drm_i915_private *dev_priv = dev->dev_private;
		3498	struct intel_encoder *intel_encoder;
		3499	bool enable = false;
		3500
		3501	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		3502	enable \|= intel_encoder->connectors_active;
		3503
		3504	if (enable)
		3505	dev_priv->display.crtc_enable(crtc);
		3506	else
		3507	dev_priv->display.crtc_disable(crtc);
		3508
		3509	intel_crtc_update_sarea(crtc, enable);
		3510	}
		3511
		3512	static void intel_crtc_noop(struct drm_crtc *crtc)
		3513	{
		3514	}
		3515
2330	Serge	3516	static void intel_crtc_disable(struct drm_crtc *crtc)
		3517	{
		3518	struct drm_device *dev = crtc->dev;
3031	serge	3519	struct drm_connector *connector;
		3520	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	3521
3031	serge	3522	/* crtc should still be enabled when we disable it. */
		3523	WARN_ON(!crtc->enabled);
2327	Serge	3524
3031	serge	3525	dev_priv->display.crtc_disable(crtc);
		3526	intel_crtc_update_sarea(crtc, false);
		3527	dev_priv->display.off(crtc);
		3528
		3529	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
		3530	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
		3531
		3532	// if (crtc->fb) {
		3533	// mutex_lock(&dev->struct_mutex);
		3534	// intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
		3535	// mutex_unlock(&dev->struct_mutex);
		3536	// crtc->fb = NULL;
		3537	// }
		3538
		3539	/* Update computed state. */
		3540	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		3541	if (!connector->encoder \|\| !connector->encoder->crtc)
		3542	continue;
		3543
		3544	if (connector->encoder->crtc != crtc)
		3545	continue;
		3546
		3547	connector->dpms = DRM_MODE_DPMS_OFF;
		3548	to_intel_encoder(connector->encoder)->connectors_active = false;
2330	Serge	3549	}
		3550	}
2327	Serge	3551
3031	serge	3552	void intel_modeset_disable(struct drm_device *dev)
2330	Serge	3553	{
3031	serge	3554	struct drm_crtc *crtc;
		3555
		3556	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		3557	if (crtc->enabled)
		3558	intel_crtc_disable(crtc);
		3559	}
2330	Serge	3560	}
2327	Serge	3561
3031	serge	3562	void intel_encoder_noop(struct drm_encoder *encoder)
2330	Serge	3563	{
		3564	}
2327	Serge	3565
3031	serge	3566	void intel_encoder_destroy(struct drm_encoder *encoder)
2330	Serge	3567	{
3031	serge	3568	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3569
		3570	drm_encoder_cleanup(encoder);
		3571	kfree(intel_encoder);
2330	Serge	3572	}
2327	Serge	3573
3031	serge	3574	/* Simple dpms helper for encodres with just one connector, no cloning and only
		3575	* one kind of off state. It clamps all !ON modes to fully OFF and changes the
		3576	* state of the entire output pipe. */
		3577	void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
2330	Serge	3578	{
3031	serge	3579	if (mode == DRM_MODE_DPMS_ON) {
		3580	encoder->connectors_active = true;
		3581
		3582	intel_crtc_update_dpms(encoder->base.crtc);
		3583	} else {
		3584	encoder->connectors_active = false;
		3585
		3586	intel_crtc_update_dpms(encoder->base.crtc);
		3587	}
2330	Serge	3588	}
2327	Serge	3589
3031	serge	3590	/* Cross check the actual hw state with our own modeset state tracking (and it's
		3591	* internal consistency). */
		3592	static void intel_connector_check_state(struct intel_connector *connector)
2330	Serge	3593	{
3031	serge	3594	if (connector->get_hw_state(connector)) {
		3595	struct intel_encoder *encoder = connector->encoder;
		3596	struct drm_crtc *crtc;
		3597	bool encoder_enabled;
		3598	enum pipe pipe;
		3599
		3600	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		3601	connector->base.base.id,
		3602	drm_get_connector_name(&connector->base));
		3603
		3604	WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		3605	"wrong connector dpms state\n");
		3606	WARN(connector->base.encoder != &encoder->base,
		3607	"active connector not linked to encoder\n");
		3608	WARN(!encoder->connectors_active,
		3609	"encoder->connectors_active not set\n");
		3610
		3611	encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		3612	WARN(!encoder_enabled, "encoder not enabled\n");
		3613	if (WARN_ON(!encoder->base.crtc))
		3614	return;
		3615
		3616	crtc = encoder->base.crtc;
		3617
		3618	WARN(!crtc->enabled, "crtc not enabled\n");
		3619	WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		3620	WARN(pipe != to_intel_crtc(crtc)->pipe,
		3621	"encoder active on the wrong pipe\n");
		3622	}
2330	Serge	3623	}
2327	Serge	3624
3031	serge	3625	/* Even simpler default implementation, if there's really no special case to
		3626	* consider. */
		3627	void intel_connector_dpms(struct drm_connector *connector, int mode)
2330	Serge	3628	{
3031	serge	3629	struct intel_encoder *encoder = intel_attached_encoder(connector);
2342	Serge	3630
3031	serge	3631	/* All the simple cases only support two dpms states. */
		3632	if (mode != DRM_MODE_DPMS_ON)
		3633	mode = DRM_MODE_DPMS_OFF;
2342	Serge	3634
3031	serge	3635	if (mode == connector->dpms)
		3636	return;
		3637
		3638	connector->dpms = mode;
		3639
		3640	/* Only need to change hw state when actually enabled */
		3641	if (encoder->base.crtc)
		3642	intel_encoder_dpms(encoder, mode);
		3643	else
		3644	WARN_ON(encoder->connectors_active != false);
		3645
		3646	intel_modeset_check_state(connector->dev);
2330	Serge	3647	}
2327	Serge	3648
3031	serge	3649	/* Simple connector->get_hw_state implementation for encoders that support only
		3650	* one connector and no cloning and hence the encoder state determines the state
		3651	* of the connector. */
		3652	bool intel_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	3653	{
3031	serge	3654	enum pipe pipe = 0;
		3655	struct intel_encoder *encoder = connector->encoder;
2330	Serge	3656
3031	serge	3657	return encoder->get_hw_state(encoder, &pipe);
2330	Serge	3658	}
		3659
		3660	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3031	serge	3661	const struct drm_display_mode *mode,
2330	Serge	3662	struct drm_display_mode *adjusted_mode)
		3663	{
		3664	struct drm_device *dev = crtc->dev;
		3665
		3666	if (HAS_PCH_SPLIT(dev)) {
		3667	/* FDI link clock is fixed at 2.7G */
		3668	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
		3669	return false;
		3670	}
		3671
3031	serge	3672	/* All interlaced capable intel hw wants timings in frames. Note though
		3673	* that intel_lvds_mode_fixup does some funny tricks with the crtc
		3674	* timings, so we need to be careful not to clobber these.*/
		3675	if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
2330	Serge	3676	drm_mode_set_crtcinfo(adjusted_mode, 0);
		3677
3031	serge	3678	/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
		3679	* with a hsync front porch of 0.
		3680	*/
		3681	if ((INTEL_INFO(dev)->gen > 4 \|\| IS_G4X(dev)) &&
		3682	adjusted_mode->hsync_start == adjusted_mode->hdisplay)
		3683	return false;
		3684
2330	Serge	3685	return true;
		3686	}
		3687
3031	serge	3688	static int valleyview_get_display_clock_speed(struct drm_device *dev)
		3689	{
		3690	return 400000; /* FIXME */
		3691	}
		3692
2327	Serge	3693	static int i945_get_display_clock_speed(struct drm_device *dev)
		3694	{
		3695	return 400000;
		3696	}
		3697
		3698	static int i915_get_display_clock_speed(struct drm_device *dev)
		3699	{
		3700	return 333000;
		3701	}
		3702
		3703	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		3704	{
		3705	return 200000;
		3706	}
		3707
		3708	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		3709	{
		3710	u16 gcfgc = 0;
		3711
		3712	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		3713
		3714	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		3715	return 133000;
		3716	else {
		3717	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		3718	case GC_DISPLAY_CLOCK_333_MHZ:
		3719	return 333000;
		3720	default:
		3721	case GC_DISPLAY_CLOCK_190_200_MHZ:
		3722	return 190000;
		3723	}
		3724	}
		3725	}
		3726
		3727	static int i865_get_display_clock_speed(struct drm_device *dev)
		3728	{
		3729	return 266000;
		3730	}
		3731
		3732	static int i855_get_display_clock_speed(struct drm_device *dev)
		3733	{
		3734	u16 hpllcc = 0;
		3735	/* Assume that the hardware is in the high speed state. This
		3736	* should be the default.
		3737	*/
		3738	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		3739	case GC_CLOCK_133_200:
		3740	case GC_CLOCK_100_200:
		3741	return 200000;
		3742	case GC_CLOCK_166_250:
		3743	return 250000;
		3744	case GC_CLOCK_100_133:
		3745	return 133000;
		3746	}
		3747
		3748	/* Shouldn't happen */
		3749	return 0;
		3750	}
		3751
		3752	static int i830_get_display_clock_speed(struct drm_device *dev)
		3753	{
		3754	return 133000;
		3755	}
		3756
		3757	struct fdi_m_n {
		3758	u32 tu;
		3759	u32 gmch_m;
		3760	u32 gmch_n;
		3761	u32 link_m;
		3762	u32 link_n;
		3763	};
		3764
		3765	static void
		3766	fdi_reduce_ratio(u32 num, u32 den)
		3767	{
		3768	while (num > 0xffffff \|\| den > 0xffffff) {
		3769	*num >>= 1;
		3770	*den >>= 1;
		3771	}
		3772	}
		3773
		3774	static void
		3775	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		3776	int link_clock, struct fdi_m_n *m_n)
		3777	{
		3778	m_n->tu = 64; /* default size */
		3779
		3780	/* BUG_ON(pixel_clock > INT_MAX / 36); */
		3781	m_n->gmch_m = bits_per_pixel * pixel_clock;
		3782	m_n->gmch_n = link_clock * nlanes * 8;
		3783	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		3784
		3785	m_n->link_m = pixel_clock;
		3786	m_n->link_n = link_clock;
		3787	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
		3788	}
		3789
		3790	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		3791	{
2342	Serge	3792	if (i915_panel_use_ssc >= 0)
		3793	return i915_panel_use_ssc != 0;
		3794	return dev_priv->lvds_use_ssc
2327	Serge	3795	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		3796	}
		3797
		3798	/**
		3799	* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
		3800	* @crtc: CRTC structure
2342	Serge	3801	* @mode: requested mode
2327	Serge	3802	*
		3803	* A pipe may be connected to one or more outputs. Based on the depth of the
		3804	* attached framebuffer, choose a good color depth to use on the pipe.
		3805	*
		3806	* If possible, match the pipe depth to the fb depth. In some cases, this
		3807	* isn't ideal, because the connected output supports a lesser or restricted
		3808	* set of depths. Resolve that here:
		3809	* LVDS typically supports only 6bpc, so clamp down in that case
		3810	* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
		3811	* Displays may support a restricted set as well, check EDID and clamp as
		3812	* appropriate.
2342	Serge	3813	* DP may want to dither down to 6bpc to fit larger modes
2327	Serge	3814	*
		3815	* RETURNS:
		3816	* Dithering requirement (i.e. false if display bpc and pipe bpc match,
		3817	* true if they don't match).
		3818	*/
		3819	static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3031	serge	3820	struct drm_framebuffer *fb,
2342	Serge	3821	unsigned int *pipe_bpp,
		3822	struct drm_display_mode *mode)
2327	Serge	3823	{
		3824	struct drm_device *dev = crtc->dev;
		3825	struct drm_i915_private *dev_priv = dev->dev_private;
		3826	struct drm_connector *connector;
3031	serge	3827	struct intel_encoder *intel_encoder;
2327	Serge	3828	unsigned int display_bpc = UINT_MAX, bpc;
		3829
		3830	/* Walk the encoders & connectors on this crtc, get min bpc */
3031	serge	3831	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2327	Serge	3832
		3833	if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
		3834	unsigned int lvds_bpc;
		3835
		3836	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
		3837	LVDS_A3_POWER_UP)
		3838	lvds_bpc = 8;
		3839	else
		3840	lvds_bpc = 6;
		3841
		3842	if (lvds_bpc < display_bpc) {
2342	Serge	3843	DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
2327	Serge	3844	display_bpc = lvds_bpc;
		3845	}
		3846	continue;
		3847	}
		3848
		3849	/* Not one of the known troublemakers, check the EDID */
		3850	list_for_each_entry(connector, &dev->mode_config.connector_list,
		3851	head) {
3031	serge	3852	if (connector->encoder != &intel_encoder->base)
2327	Serge	3853	continue;
		3854
		3855	/* Don't use an invalid EDID bpc value */
		3856	if (connector->display_info.bpc &&
		3857	connector->display_info.bpc < display_bpc) {
2342	Serge	3858	DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
2327	Serge	3859	display_bpc = connector->display_info.bpc;
3031	serge	3860	}
		3861	}
2327	Serge	3862
		3863	/*
		3864	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		3865	* through, clamp it down. (Note: >12bpc will be caught below.)
		3866	*/
		3867	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		3868	if (display_bpc > 8 && display_bpc < 12) {
2342	Serge	3869	DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
2327	Serge	3870	display_bpc = 12;
		3871	} else {
2342	Serge	3872	DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
2327	Serge	3873	display_bpc = 8;
		3874	}
		3875	}
		3876	}
		3877
2342	Serge	3878	if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		3879	DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
		3880	display_bpc = 6;
		3881	}
		3882
2327	Serge	3883	/*
		3884	* We could just drive the pipe at the highest bpc all the time and
		3885	* enable dithering as needed, but that costs bandwidth. So choose
		3886	* the minimum value that expresses the full color range of the fb but
		3887	* also stays within the max display bpc discovered above.
		3888	*/
		3889
3031	serge	3890	switch (fb->depth) {
2327	Serge	3891	case 8:
		3892	bpc = 8; /* since we go through a colormap */
		3893	break;
		3894	case 15:
		3895	case 16:
		3896	bpc = 6; /* min is 18bpp */
		3897	break;
		3898	case 24:
2342	Serge	3899	bpc = 8;
2327	Serge	3900	break;
		3901	case 30:
2342	Serge	3902	bpc = 10;
2327	Serge	3903	break;
		3904	case 48:
2342	Serge	3905	bpc = 12;
2327	Serge	3906	break;
		3907	default:
		3908	DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		3909	bpc = min((unsigned int)8, display_bpc);
		3910	break;
		3911	}
		3912
2342	Serge	3913	display_bpc = min(display_bpc, bpc);
		3914
		3915	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3031	serge	3916	bpc, display_bpc);
2327	Serge	3917
2342	Serge	3918	pipe_bpp = display_bpc 3;
2327	Serge	3919
		3920	return display_bpc != bpc;
		3921	}
		3922
3031	serge	3923	static int vlv_get_refclk(struct drm_crtc *crtc)
2327	Serge	3924	{
3031	serge	3925	struct drm_device *dev = crtc->dev;
		3926	struct drm_i915_private *dev_priv = dev->dev_private;
		3927	int refclk = 27000; /* for DP & HDMI */
2327	Serge	3928
3031	serge	3929	return 100000; /* only one validated so far */
2327	Serge	3930
3031	serge	3931	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		3932	refclk = 96000;
		3933	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		3934	if (intel_panel_use_ssc(dev_priv))
		3935	refclk = 100000;
		3936	else
		3937	refclk = 96000;
		3938	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		3939	refclk = 100000;
		3940	}
2327	Serge	3941
3031	serge	3942	return refclk;
		3943	}
2327	Serge	3944
3031	serge	3945	static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
		3946	{
		3947	struct drm_device *dev = crtc->dev;
		3948	struct drm_i915_private *dev_priv = dev->dev_private;
		3949	int refclk;
2327	Serge	3950
3031	serge	3951	if (IS_VALLEYVIEW(dev)) {
		3952	refclk = vlv_get_refclk(crtc);
		3953	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		3954	intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		3955	refclk = dev_priv->lvds_ssc_freq * 1000;
		3956	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		3957	refclk / 1000);
		3958	} else if (!IS_GEN2(dev)) {
		3959	refclk = 96000;
		3960	} else {
		3961	refclk = 48000;
		3962	}
2327	Serge	3963
3031	serge	3964	return refclk;
		3965	}
2327	Serge	3966
3031	serge	3967	static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
		3968	intel_clock_t *clock)
		3969	{
		3970	/* SDVO TV has fixed PLL values depend on its clock range,
		3971	this mirrors vbios setting. */
		3972	if (adjusted_mode->clock >= 100000
		3973	&& adjusted_mode->clock < 140500) {
		3974	clock->p1 = 2;
		3975	clock->p2 = 10;
		3976	clock->n = 3;
		3977	clock->m1 = 16;
		3978	clock->m2 = 8;
		3979	} else if (adjusted_mode->clock >= 140500
		3980	&& adjusted_mode->clock <= 200000) {
		3981	clock->p1 = 1;
		3982	clock->p2 = 10;
		3983	clock->n = 6;
		3984	clock->m1 = 12;
		3985	clock->m2 = 8;
		3986	}
		3987	}
2327	Serge	3988
3031	serge	3989	static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
		3990	intel_clock_t *clock,
		3991	intel_clock_t *reduced_clock)
		3992	{
		3993	struct drm_device *dev = crtc->dev;
		3994	struct drm_i915_private *dev_priv = dev->dev_private;
		3995	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3996	int pipe = intel_crtc->pipe;
		3997	u32 fp, fp2 = 0;
2327	Serge	3998
3031	serge	3999	if (IS_PINEVIEW(dev)) {
		4000	fp = (1 << clock->n) << 16 \| clock->m1 << 8 \| clock->m2;
		4001	if (reduced_clock)
		4002	fp2 = (1 << reduced_clock->n) << 16 \|
		4003	reduced_clock->m1 << 8 \| reduced_clock->m2;
		4004	} else {
		4005	fp = clock->n << 16 \| clock->m1 << 8 \| clock->m2;
		4006	if (reduced_clock)
		4007	fp2 = reduced_clock->n << 16 \| reduced_clock->m1 << 8 \|
		4008	reduced_clock->m2;
		4009	}
2327	Serge	4010
3031	serge	4011	I915_WRITE(FP0(pipe), fp);
2327	Serge	4012
3031	serge	4013	intel_crtc->lowfreq_avail = false;
		4014	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4015	reduced_clock && i915_powersave) {
		4016	I915_WRITE(FP1(pipe), fp2);
		4017	intel_crtc->lowfreq_avail = true;
		4018	} else {
		4019	I915_WRITE(FP1(pipe), fp);
		4020	}
		4021	}
2327	Serge	4022
3031	serge	4023	static void intel_update_lvds(struct drm_crtc crtc, intel_clock_t clock,
		4024	struct drm_display_mode *adjusted_mode)
		4025	{
		4026	struct drm_device *dev = crtc->dev;
		4027	struct drm_i915_private *dev_priv = dev->dev_private;
		4028	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4029	int pipe = intel_crtc->pipe;
		4030	u32 temp;
2327	Serge	4031
3031	serge	4032	temp = I915_READ(LVDS);
		4033	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		4034	if (pipe == 1) {
		4035	temp \|= LVDS_PIPEB_SELECT;
		4036	} else {
		4037	temp &= ~LVDS_PIPEB_SELECT;
		4038	}
		4039	/* set the corresponsding LVDS_BORDER bit */
		4040	temp \|= dev_priv->lvds_border_bits;
		4041	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4042	* set the DPLLs for dual-channel mode or not.
		4043	*/
		4044	if (clock->p2 == 7)
		4045	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		4046	else
		4047	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
2327	Serge	4048
3031	serge	4049	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		4050	* appropriately here, but we need to look more thoroughly into how
		4051	* panels behave in the two modes.
		4052	*/
		4053	/* set the dithering flag on LVDS as needed */
		4054	if (INTEL_INFO(dev)->gen >= 4) {
		4055	if (dev_priv->lvds_dither)
		4056	temp \|= LVDS_ENABLE_DITHER;
		4057	else
		4058	temp &= ~LVDS_ENABLE_DITHER;
		4059	}
		4060	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		4061	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		4062	temp \|= LVDS_HSYNC_POLARITY;
		4063	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		4064	temp \|= LVDS_VSYNC_POLARITY;
		4065	I915_WRITE(LVDS, temp);
		4066	}
2327	Serge	4067
3031	serge	4068	static void vlv_update_pll(struct drm_crtc *crtc,
		4069	struct drm_display_mode *mode,
		4070	struct drm_display_mode *adjusted_mode,
		4071	intel_clock_t clock, intel_clock_t reduced_clock,
		4072	int refclk, int num_connectors)
		4073	{
		4074	struct drm_device *dev = crtc->dev;
		4075	struct drm_i915_private *dev_priv = dev->dev_private;
		4076	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4077	int pipe = intel_crtc->pipe;
		4078	u32 dpll, mdiv, pdiv;
		4079	u32 bestn, bestm1, bestm2, bestp1, bestp2;
		4080	bool is_hdmi;
2327	Serge	4081
3031	serge	4082	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
2327	Serge	4083
3031	serge	4084	bestn = clock->n;
		4085	bestm1 = clock->m1;
		4086	bestm2 = clock->m2;
		4087	bestp1 = clock->p1;
		4088	bestp2 = clock->p2;
		4089
		4090	/* Enable DPIO clock input */
		4091	dpll = DPLL_EXT_BUFFER_ENABLE_VLV \| DPLL_REFA_CLK_ENABLE_VLV \|
		4092	DPLL_VGA_MODE_DIS \| DPLL_INTEGRATED_CLOCK_VLV;
		4093	I915_WRITE(DPLL(pipe), dpll);
		4094	POSTING_READ(DPLL(pipe));
		4095
		4096	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) \| (bestm2 & DPIO_M2DIV_MASK));
		4097	mdiv \|= ((bestp1 << DPIO_P1_SHIFT) \| (bestp2 << DPIO_P2_SHIFT));
		4098	mdiv \|= ((bestn << DPIO_N_SHIFT));
		4099	mdiv \|= (1 << DPIO_POST_DIV_SHIFT);
		4100	mdiv \|= (1 << DPIO_K_SHIFT);
		4101	mdiv \|= DPIO_ENABLE_CALIBRATION;
		4102	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
		4103
		4104	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
		4105
		4106	pdiv = DPIO_REFSEL_OVERRIDE \| (5 << DPIO_PLL_MODESEL_SHIFT) \|
		4107	(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) \| (1<<20) \|
		4108	(8 << DPIO_DRIVER_CTL_SHIFT) \| (5 << DPIO_CLK_BIAS_CTL_SHIFT);
		4109	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
		4110
		4111	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
		4112
		4113	dpll \|= DPLL_VCO_ENABLE;
		4114	I915_WRITE(DPLL(pipe), dpll);
		4115	POSTING_READ(DPLL(pipe));
		4116	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		4117	DRM_ERROR("DPLL %d failed to lock\n", pipe);
		4118
		4119	if (is_hdmi) {
		4120	u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		4121
		4122	if (temp > 1)
		4123	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4124	else
		4125	temp = 0;
		4126
		4127	I915_WRITE(DPLL_MD(pipe), temp);
		4128	POSTING_READ(DPLL_MD(pipe));
		4129	}
		4130
		4131	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
		4132	}
		4133
		4134	static void i9xx_update_pll(struct drm_crtc *crtc,
		4135	struct drm_display_mode *mode,
		4136	struct drm_display_mode *adjusted_mode,
		4137	intel_clock_t clock, intel_clock_t reduced_clock,
		4138	int num_connectors)
		4139	{
		4140	struct drm_device *dev = crtc->dev;
		4141	struct drm_i915_private *dev_priv = dev->dev_private;
		4142	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4143	int pipe = intel_crtc->pipe;
		4144	u32 dpll;
		4145	bool is_sdvo;
		4146
		4147	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) \|\|
		4148	intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
		4149
		4150	dpll = DPLL_VGA_MODE_DIS;
		4151
		4152	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4153	dpll \|= DPLLB_MODE_LVDS;
		4154	else
		4155	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4156	if (is_sdvo) {
		4157	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4158	if (pixel_multiplier > 1) {
		4159	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))
		4160	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2342	Serge	4161	}
3031	serge	4162	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4163	}
3031	serge	4164	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		4165	dpll \|= DPLL_DVO_HIGH_SPEED;
2342	Serge	4166
3031	serge	4167	/* compute bitmask from p1 value */
		4168	if (IS_PINEVIEW(dev))
		4169	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4170	else {
		4171	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4172	if (IS_G4X(dev) && reduced_clock)
		4173	dpll \|= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4174	}
		4175	switch (clock->p2) {
		4176	case 5:
		4177	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4178	break;
		4179	case 7:
		4180	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4181	break;
		4182	case 10:
		4183	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4184	break;
		4185	case 14:
		4186	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4187	break;
		4188	}
		4189	if (INTEL_INFO(dev)->gen >= 4)
		4190	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2327	Serge	4191
3031	serge	4192	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4193	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4194	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4195	/* XXX: just matching BIOS for now */
		4196	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4197	dpll \|= 3;
		4198	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4199	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4200	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4201	else
		4202	dpll \|= PLL_REF_INPUT_DREFCLK;
2327	Serge	4203
3031	serge	4204	dpll \|= DPLL_VCO_ENABLE;
		4205	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4206	POSTING_READ(DPLL(pipe));
		4207	udelay(150);
2327	Serge	4208
3031	serge	4209	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4210	* This is an exception to the general rule that mode_set doesn't turn
		4211	* things on.
		4212	*/
		4213	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4214	intel_update_lvds(crtc, clock, adjusted_mode);
2327	Serge	4215
3031	serge	4216	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		4217	intel_dp_set_m_n(crtc, mode, adjusted_mode);
2327	Serge	4218
3031	serge	4219	I915_WRITE(DPLL(pipe), dpll);
2327	Serge	4220
3031	serge	4221	/* Wait for the clocks to stabilize. */
		4222	POSTING_READ(DPLL(pipe));
		4223	udelay(150);
2327	Serge	4224
3031	serge	4225	if (INTEL_INFO(dev)->gen >= 4) {
		4226	u32 temp = 0;
		4227	if (is_sdvo) {
		4228	temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		4229	if (temp > 1)
		4230	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		4231	else
		4232	temp = 0;
		4233	}
		4234	I915_WRITE(DPLL_MD(pipe), temp);
		4235	} else {
		4236	/* The pixel multiplier can only be updated once the
		4237	* DPLL is enabled and the clocks are stable.
		4238	*
		4239	* So write it again.
		4240	*/
		4241	I915_WRITE(DPLL(pipe), dpll);
		4242	}
		4243	}
2327	Serge	4244
3031	serge	4245	static void i8xx_update_pll(struct drm_crtc *crtc,
		4246	struct drm_display_mode *adjusted_mode,
		4247	intel_clock_t *clock,
		4248	int num_connectors)
		4249	{
		4250	struct drm_device *dev = crtc->dev;
		4251	struct drm_i915_private *dev_priv = dev->dev_private;
		4252	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4253	int pipe = intel_crtc->pipe;
		4254	u32 dpll;
2327	Serge	4255
3031	serge	4256	dpll = DPLL_VGA_MODE_DIS;
2327	Serge	4257
3031	serge	4258	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		4259	dpll \|= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4260	} else {
		4261	if (clock->p1 == 2)
		4262	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4263	else
		4264	dpll \|= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4265	if (clock->p2 == 4)
		4266	dpll \|= PLL_P2_DIVIDE_BY_4;
		4267	}
2327	Serge	4268
3031	serge	4269	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		4270	/* XXX: just matching BIOS for now */
		4271	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4272	dpll \|= 3;
		4273	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		4274	intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4275	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4276	else
		4277	dpll \|= PLL_REF_INPUT_DREFCLK;
		4278
		4279	dpll \|= DPLL_VCO_ENABLE;
		4280	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4281	POSTING_READ(DPLL(pipe));
		4282	udelay(150);
		4283
		4284	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4285	* This is an exception to the general rule that mode_set doesn't turn
		4286	* things on.
		4287	*/
		4288	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		4289	intel_update_lvds(crtc, clock, adjusted_mode);
		4290
		4291	I915_WRITE(DPLL(pipe), dpll);
		4292
		4293	/* Wait for the clocks to stabilize. */
		4294	POSTING_READ(DPLL(pipe));
		4295	udelay(150);
		4296
		4297	/* The pixel multiplier can only be updated once the
		4298	* DPLL is enabled and the clocks are stable.
		4299	*
		4300	* So write it again.
		4301	*/
		4302	I915_WRITE(DPLL(pipe), dpll);
		4303	}
		4304
		4305	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4306	struct drm_display_mode *mode,
		4307	struct drm_display_mode *adjusted_mode,
		4308	int x, int y,
		4309	struct drm_framebuffer *fb)
		4310	{
		4311	struct drm_device *dev = crtc->dev;
		4312	struct drm_i915_private *dev_priv = dev->dev_private;
		4313	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4314	int pipe = intel_crtc->pipe;
		4315	int plane = intel_crtc->plane;
		4316	int refclk, num_connectors = 0;
		4317	intel_clock_t clock, reduced_clock;
		4318	u32 dspcntr, pipeconf, vsyncshift;
		4319	bool ok, has_reduced_clock = false, is_sdvo = false;
		4320	bool is_lvds = false, is_tv = false, is_dp = false;
		4321	struct intel_encoder *encoder;
		4322	const intel_limit_t *limit;
		4323	int ret;
		4324
		4325	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4326	switch (encoder->type) {
		4327	case INTEL_OUTPUT_LVDS:
		4328	is_lvds = true;
		4329	break;
		4330	case INTEL_OUTPUT_SDVO:
		4331	case INTEL_OUTPUT_HDMI:
		4332	is_sdvo = true;
		4333	if (encoder->needs_tv_clock)
		4334	is_tv = true;
		4335	break;
		4336	case INTEL_OUTPUT_TVOUT:
		4337	is_tv = true;
		4338	break;
		4339	case INTEL_OUTPUT_DISPLAYPORT:
		4340	is_dp = true;
		4341	break;
		4342	}
		4343
		4344	num_connectors++;
		4345	}
		4346
		4347	refclk = i9xx_get_refclk(crtc, num_connectors);
		4348
		4349	/*
		4350	* Returns a set of divisors for the desired target clock with the given
		4351	* refclk, or FALSE. The returned values represent the clock equation:
		4352	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4353	*/
		4354	limit = intel_limit(crtc, refclk);
		4355	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		4356	&clock);
		4357	if (!ok) {
		4358	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4359	return -EINVAL;
		4360	}
		4361
		4362	/* Ensure that the cursor is valid for the new mode before changing... */
		4363	// intel_crtc_update_cursor(crtc, true);
		4364
		4365	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4366	/*
		4367	* Ensure we match the reduced clock's P to the target clock.
		4368	* If the clocks don't match, we can't switch the display clock
		4369	* by using the FP0/FP1. In such case we will disable the LVDS
		4370	* downclock feature.
		4371	*/
		4372	has_reduced_clock = limit->find_pll(limit, crtc,
		4373	dev_priv->lvds_downclock,
		4374	refclk,
		4375	&clock,
		4376	&reduced_clock);
		4377	}
		4378
		4379	if (is_sdvo && is_tv)
		4380	i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
		4381
		4382	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
		4383	&reduced_clock : NULL);
		4384
		4385	if (IS_GEN2(dev))
		4386	i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
		4387	else if (IS_VALLEYVIEW(dev))
		4388	vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
		4389	refclk, num_connectors);
		4390	else
		4391	i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
		4392	has_reduced_clock ? &reduced_clock : NULL,
		4393	num_connectors);
		4394
		4395	/* setup pipeconf */
		4396	pipeconf = I915_READ(PIPECONF(pipe));
		4397
		4398	/* Set up the display plane register */
		4399	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4400
		4401	if (pipe == 0)
		4402	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4403	else
		4404	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		4405
		4406	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4407	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4408	* core speed.
		4409	*
		4410	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4411	* pipe == 0 check?
		4412	*/
		4413	if (mode->clock >
		4414	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4415	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4416	else
		4417	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
		4418	}
		4419
		4420	/* default to 8bpc */
		4421	pipeconf &= ~(PIPECONF_BPP_MASK \| PIPECONF_DITHER_EN);
		4422	if (is_dp) {
		4423	if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		4424	pipeconf \|= PIPECONF_BPP_6 \|
		4425	PIPECONF_DITHER_EN \|
		4426	PIPECONF_DITHER_TYPE_SP;
		4427	}
		4428	}
		4429
		4430	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		4431	drm_mode_debug_printmodeline(mode);
		4432
		4433	if (HAS_PIPE_CXSR(dev)) {
		4434	if (intel_crtc->lowfreq_avail) {
		4435	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		4436	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		4437	} else {
		4438	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		4439	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		4440	}
		4441	}
		4442
2360	Serge	4443	pipeconf &= ~PIPECONF_INTERLACE_MASK;
3031	serge	4444	if (!IS_GEN2(dev) &&
		4445	adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		4446	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		4447	/* the chip adds 2 halflines automatically */
		4448	adjusted_mode->crtc_vtotal -= 1;
		4449	adjusted_mode->crtc_vblank_end -= 1;
		4450	vsyncshift = adjusted_mode->crtc_hsync_start
		4451	- adjusted_mode->crtc_htotal/2;
		4452	} else {
2360	Serge	4453	pipeconf \|= PIPECONF_PROGRESSIVE;
3031	serge	4454	vsyncshift = 0;
		4455	}
2327	Serge	4456
3031	serge	4457	if (!IS_GEN3(dev))
		4458	I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
2327	Serge	4459
3031	serge	4460	I915_WRITE(HTOTAL(pipe),
		4461	(adjusted_mode->crtc_hdisplay - 1) \|
		4462	((adjusted_mode->crtc_htotal - 1) << 16));
		4463	I915_WRITE(HBLANK(pipe),
		4464	(adjusted_mode->crtc_hblank_start - 1) \|
		4465	((adjusted_mode->crtc_hblank_end - 1) << 16));
		4466	I915_WRITE(HSYNC(pipe),
		4467	(adjusted_mode->crtc_hsync_start - 1) \|
		4468	((adjusted_mode->crtc_hsync_end - 1) << 16));
2327	Serge	4469
3031	serge	4470	I915_WRITE(VTOTAL(pipe),
		4471	(adjusted_mode->crtc_vdisplay - 1) \|
		4472	((adjusted_mode->crtc_vtotal - 1) << 16));
		4473	I915_WRITE(VBLANK(pipe),
		4474	(adjusted_mode->crtc_vblank_start - 1) \|
		4475	((adjusted_mode->crtc_vblank_end - 1) << 16));
		4476	I915_WRITE(VSYNC(pipe),
		4477	(adjusted_mode->crtc_vsync_start - 1) \|
		4478	((adjusted_mode->crtc_vsync_end - 1) << 16));
2327	Serge	4479
3031	serge	4480	/* pipesrc and dspsize control the size that is scaled from,
		4481	* which should always be the user's requested size.
		4482	*/
		4483	I915_WRITE(DSPSIZE(plane),
		4484	((mode->vdisplay - 1) << 16) \|
		4485	(mode->hdisplay - 1));
		4486	I915_WRITE(DSPPOS(plane), 0);
		4487	I915_WRITE(PIPESRC(pipe),
		4488	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
2327	Serge	4489
3031	serge	4490	I915_WRITE(PIPECONF(pipe), pipeconf);
		4491	POSTING_READ(PIPECONF(pipe));
		4492	intel_enable_pipe(dev_priv, pipe, false);
2327	Serge	4493
3031	serge	4494	intel_wait_for_vblank(dev, pipe);
2327	Serge	4495
3031	serge	4496	I915_WRITE(DSPCNTR(plane), dspcntr);
		4497	POSTING_READ(DSPCNTR(plane));
2327	Serge	4498
3031	serge	4499	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	4500
3031	serge	4501	intel_update_watermarks(dev);
		4502
2327	Serge	4503	return ret;
		4504	}
		4505
2342	Serge	4506	/*
		4507	* Initialize reference clocks when the driver loads
		4508	*/
		4509	void ironlake_init_pch_refclk(struct drm_device *dev)
2327	Serge	4510	{
		4511	struct drm_i915_private *dev_priv = dev->dev_private;
		4512	struct drm_mode_config *mode_config = &dev->mode_config;
		4513	struct intel_encoder *encoder;
		4514	u32 temp;
		4515	bool has_lvds = false;
2342	Serge	4516	bool has_cpu_edp = false;
		4517	bool has_pch_edp = false;
		4518	bool has_panel = false;
		4519	bool has_ck505 = false;
		4520	bool can_ssc = false;
2327	Serge	4521
		4522	/* We need to take the global config into account */
		4523	list_for_each_entry(encoder, &mode_config->encoder_list,
		4524	base.head) {
		4525	switch (encoder->type) {
		4526	case INTEL_OUTPUT_LVDS:
2342	Serge	4527	has_panel = true;
2327	Serge	4528	has_lvds = true;
2342	Serge	4529	break;
2327	Serge	4530	case INTEL_OUTPUT_EDP:
2342	Serge	4531	has_panel = true;
		4532	if (intel_encoder_is_pch_edp(&encoder->base))
		4533	has_pch_edp = true;
		4534	else
		4535	has_cpu_edp = true;
2327	Serge	4536	break;
		4537	}
		4538	}
2342	Serge	4539
		4540	if (HAS_PCH_IBX(dev)) {
		4541	has_ck505 = dev_priv->display_clock_mode;
		4542	can_ssc = has_ck505;
		4543	} else {
		4544	has_ck505 = false;
		4545	can_ssc = true;
2327	Serge	4546	}
		4547
2342	Serge	4548	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		4549	has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		4550	has_ck505);
		4551
2327	Serge	4552	/* Ironlake: try to setup display ref clock before DPLL
		4553	* enabling. This is only under driver's control after
		4554	* PCH B stepping, previous chipset stepping should be
		4555	* ignoring this setting.
		4556	*/
		4557	temp = I915_READ(PCH_DREF_CONTROL);
		4558	/* Always enable nonspread source */
		4559	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2342	Serge	4560
		4561	if (has_ck505)
		4562	temp \|= DREF_NONSPREAD_CK505_ENABLE;
		4563	else
2327	Serge	4564	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;
2342	Serge	4565
		4566	if (has_panel) {
2327	Serge	4567	temp &= ~DREF_SSC_SOURCE_MASK;
		4568	temp \|= DREF_SSC_SOURCE_ENABLE;
		4569
2342	Serge	4570	/* SSC must be turned on before enabling the CPU output */
		4571	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4572	DRM_DEBUG_KMS("Using SSC on panel\n");
		4573	temp \|= DREF_SSC1_ENABLE;
3031	serge	4574	} else
		4575	temp &= ~DREF_SSC1_ENABLE;
2327	Serge	4576
2342	Serge	4577	/* Get SSC going before enabling the outputs */
2327	Serge	4578	I915_WRITE(PCH_DREF_CONTROL, temp);
		4579	POSTING_READ(PCH_DREF_CONTROL);
		4580	udelay(200);
2342	Serge	4581
2327	Serge	4582	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		4583
		4584	/* Enable CPU source on CPU attached eDP */
2342	Serge	4585	if (has_cpu_edp) {
		4586	if (intel_panel_use_ssc(dev_priv) && can_ssc) {
		4587	DRM_DEBUG_KMS("Using SSC on eDP\n");
2327	Serge	4588	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342	Serge	4589	}
2327	Serge	4590	else
		4591	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342	Serge	4592	} else
		4593	temp \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4594
		4595	I915_WRITE(PCH_DREF_CONTROL, temp);
		4596	POSTING_READ(PCH_DREF_CONTROL);
		4597	udelay(200);
2327	Serge	4598	} else {
2342	Serge	4599	DRM_DEBUG_KMS("Disabling SSC entirely\n");
		4600
		4601	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		4602
		4603	/* Turn off CPU output */
		4604	temp \|= DREF_CPU_SOURCE_OUTPUT_DISABLE;
		4605
2327	Serge	4606	I915_WRITE(PCH_DREF_CONTROL, temp);
		4607	POSTING_READ(PCH_DREF_CONTROL);
		4608	udelay(200);
2342	Serge	4609
		4610	/* Turn off the SSC source */
		4611	temp &= ~DREF_SSC_SOURCE_MASK;
		4612	temp \|= DREF_SSC_SOURCE_DISABLE;
		4613
		4614	/* Turn off SSC1 */
		4615	temp &= ~ DREF_SSC1_ENABLE;
		4616
		4617	I915_WRITE(PCH_DREF_CONTROL, temp);
		4618	POSTING_READ(PCH_DREF_CONTROL);
		4619	udelay(200);
2327	Serge	4620	}
		4621	}
		4622
2342	Serge	4623	static int ironlake_get_refclk(struct drm_crtc *crtc)
		4624	{
		4625	struct drm_device *dev = crtc->dev;
		4626	struct drm_i915_private *dev_priv = dev->dev_private;
		4627	struct intel_encoder *encoder;
		4628	struct intel_encoder *edp_encoder = NULL;
		4629	int num_connectors = 0;
		4630	bool is_lvds = false;
		4631
3031	serge	4632	for_each_encoder_on_crtc(dev, crtc, encoder) {
2342	Serge	4633	switch (encoder->type) {
		4634	case INTEL_OUTPUT_LVDS:
		4635	is_lvds = true;
		4636	break;
		4637	case INTEL_OUTPUT_EDP:
		4638	edp_encoder = encoder;
		4639	break;
		4640	}
		4641	num_connectors++;
		4642	}
		4643
		4644	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		4645	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4646	dev_priv->lvds_ssc_freq);
		4647	return dev_priv->lvds_ssc_freq * 1000;
		4648	}
		4649
		4650	return 120000;
		4651	}
		4652
3031	serge	4653	static void ironlake_set_pipeconf(struct drm_crtc *crtc,
		4654	struct drm_display_mode *adjusted_mode,
		4655	bool dither)
		4656	{
		4657	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		4658	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4659	int pipe = intel_crtc->pipe;
		4660	uint32_t val;
		4661
		4662	val = I915_READ(PIPECONF(pipe));
		4663
		4664	val &= ~PIPE_BPC_MASK;
		4665	switch (intel_crtc->bpp) {
		4666	case 18:
		4667	val \|= PIPE_6BPC;
		4668	break;
		4669	case 24:
		4670	val \|= PIPE_8BPC;
		4671	break;
		4672	case 30:
		4673	val \|= PIPE_10BPC;
		4674	break;
		4675	case 36:
		4676	val \|= PIPE_12BPC;
		4677	break;
		4678	default:
		4679	val \|= PIPE_8BPC;
		4680	break;
		4681	}
		4682
		4683	val &= ~(PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_MASK);
		4684	if (dither)
		4685	val \|= (PIPECONF_DITHER_EN \| PIPECONF_DITHER_TYPE_SP);
		4686
		4687	val &= ~PIPECONF_INTERLACE_MASK;
		4688	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		4689	val \|= PIPECONF_INTERLACED_ILK;
		4690	else
		4691	val \|= PIPECONF_PROGRESSIVE;
		4692
		4693	I915_WRITE(PIPECONF(pipe), val);
		4694	POSTING_READ(PIPECONF(pipe));
		4695	}
		4696
		4697	static bool ironlake_compute_clocks(struct drm_crtc *crtc,
		4698	struct drm_display_mode *adjusted_mode,
		4699	intel_clock_t *clock,
		4700	bool *has_reduced_clock,
		4701	intel_clock_t *reduced_clock)
		4702	{
		4703	struct drm_device *dev = crtc->dev;
		4704	struct drm_i915_private *dev_priv = dev->dev_private;
		4705	struct intel_encoder *intel_encoder;
		4706	int refclk;
		4707	const intel_limit_t *limit;
		4708	bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
		4709
		4710	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		4711	switch (intel_encoder->type) {
		4712	case INTEL_OUTPUT_LVDS:
		4713	is_lvds = true;
		4714	break;
		4715	case INTEL_OUTPUT_SDVO:
		4716	case INTEL_OUTPUT_HDMI:
		4717	is_sdvo = true;
		4718	if (intel_encoder->needs_tv_clock)
		4719	is_tv = true;
		4720	break;
		4721	case INTEL_OUTPUT_TVOUT:
		4722	is_tv = true;
		4723	break;
		4724	}
		4725	}
		4726
		4727	refclk = ironlake_get_refclk(crtc);
		4728
		4729	/*
		4730	* Returns a set of divisors for the desired target clock with the given
		4731	* refclk, or FALSE. The returned values represent the clock equation:
		4732	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4733	*/
		4734	limit = intel_limit(crtc, refclk);
		4735	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
		4736	clock);
		4737	if (!ret)
		4738	return false;
		4739
		4740	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4741	/*
		4742	* Ensure we match the reduced clock's P to the target clock.
		4743	* If the clocks don't match, we can't switch the display clock
		4744	* by using the FP0/FP1. In such case we will disable the LVDS
		4745	* downclock feature.
		4746	*/
		4747	*has_reduced_clock = limit->find_pll(limit, crtc,
		4748	dev_priv->lvds_downclock,
		4749	refclk,
		4750	clock,
		4751	reduced_clock);
		4752	}
		4753
		4754	if (is_sdvo && is_tv)
		4755	i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
		4756
		4757	return true;
		4758	}
		4759
2327	Serge	4760	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		4761	struct drm_display_mode *mode,
		4762	struct drm_display_mode *adjusted_mode,
		4763	int x, int y,
3031	serge	4764	struct drm_framebuffer *fb)
2327	Serge	4765	{
		4766	struct drm_device *dev = crtc->dev;
		4767	struct drm_i915_private *dev_priv = dev->dev_private;
		4768	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4769	int pipe = intel_crtc->pipe;
		4770	int plane = intel_crtc->plane;
3031	serge	4771	int num_connectors = 0;
2327	Serge	4772	intel_clock_t clock, reduced_clock;
3031	serge	4773	u32 dpll, fp = 0, fp2 = 0;
2327	Serge	4774	bool ok, has_reduced_clock = false, is_sdvo = false;
		4775	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3031	serge	4776	struct intel_encoder encoder, edp_encoder = NULL;
2327	Serge	4777	int ret;
		4778	struct fdi_m_n m_n = {0};
		4779	u32 temp;
		4780	int target_clock, pixel_multiplier, lane, link_bw, factor;
		4781	unsigned int pipe_bpp;
		4782	bool dither;
3031	serge	4783	bool is_cpu_edp = false, is_pch_edp = false;
2327	Serge	4784
3031	serge	4785	for_each_encoder_on_crtc(dev, crtc, encoder) {
2327	Serge	4786	switch (encoder->type) {
		4787	case INTEL_OUTPUT_LVDS:
		4788	is_lvds = true;
		4789	break;
		4790	case INTEL_OUTPUT_SDVO:
		4791	case INTEL_OUTPUT_HDMI:
		4792	is_sdvo = true;
		4793	if (encoder->needs_tv_clock)
		4794	is_tv = true;
		4795	break;
		4796	case INTEL_OUTPUT_TVOUT:
		4797	is_tv = true;
		4798	break;
		4799	case INTEL_OUTPUT_ANALOG:
		4800	is_crt = true;
		4801	break;
		4802	case INTEL_OUTPUT_DISPLAYPORT:
		4803	is_dp = true;
		4804	break;
		4805	case INTEL_OUTPUT_EDP:
3031	serge	4806	is_dp = true;
		4807	if (intel_encoder_is_pch_edp(&encoder->base))
		4808	is_pch_edp = true;
		4809	else
		4810	is_cpu_edp = true;
		4811	edp_encoder = encoder;
2327	Serge	4812	break;
		4813	}
		4814
		4815	num_connectors++;
		4816	}
		4817
3031	serge	4818	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
		4819	&has_reduced_clock, &reduced_clock);
2327	Serge	4820	if (!ok) {
		4821	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4822	return -EINVAL;
		4823	}
		4824
		4825	/* Ensure that the cursor is valid for the new mode before changing... */
		4826	// intel_crtc_update_cursor(crtc, true);
		4827
		4828	/* FDI link */
		4829	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4830	lane = 0;
		4831	/* CPU eDP doesn't require FDI link, so just set DP M/N
		4832	according to current link config */
3031	serge	4833	if (is_cpu_edp) {
		4834	intel_edp_link_config(edp_encoder, &lane, &link_bw);
2327	Serge	4835	} else {
		4836	/* FDI is a binary signal running at ~2.7GHz, encoding
		4837	* each output octet as 10 bits. The actual frequency
		4838	* is stored as a divider into a 100MHz clock, and the
		4839	* mode pixel clock is stored in units of 1KHz.
		4840	* Hence the bw of each lane in terms of the mode signal
		4841	* is:
		4842	*/
		4843	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		4844	}
		4845
3031	serge	4846	/* [e]DP over FDI requires target mode clock instead of link clock. */
		4847	if (edp_encoder)
		4848	target_clock = intel_edp_target_clock(edp_encoder, mode);
		4849	else if (is_dp)
		4850	target_clock = mode->clock;
		4851	else
		4852	target_clock = adjusted_mode->clock;
		4853
2327	Serge	4854	/* determine panel color depth */
3031	serge	4855	dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
		4856	adjusted_mode);
		4857	if (is_lvds && dev_priv->lvds_dither)
		4858	dither = true;
		4859
		4860	if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
		4861	pipe_bpp != 36) {
2327	Serge	4862	WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
		4863	pipe_bpp);
		4864	pipe_bpp = 24;
		4865	}
		4866	intel_crtc->bpp = pipe_bpp;
		4867
		4868	if (!lane) {
		4869	/*
		4870	* Account for spread spectrum to avoid
		4871	* oversubscribing the link. Max center spread
		4872	* is 2.5%; use 5% for safety's sake.
		4873	*/
		4874	u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
		4875	lane = bps / (link_bw * 8) + 1;
		4876	}
		4877
		4878	intel_crtc->fdi_lanes = lane;
		4879
		4880	if (pixel_multiplier > 1)
		4881	link_bw *= pixel_multiplier;
		4882	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
		4883	&m_n);
		4884
		4885	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		4886	if (has_reduced_clock)
		4887	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		4888	reduced_clock.m2;
		4889
		4890	/* Enable autotuning of the PLL clock (if permissible) */
		4891	factor = 21;
		4892	if (is_lvds) {
		4893	if ((intel_panel_use_ssc(dev_priv) &&
		4894	dev_priv->lvds_ssc_freq == 100) \|\|
		4895	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
		4896	factor = 25;
		4897	} else if (is_sdvo && is_tv)
		4898	factor = 20;
		4899
		4900	if (clock.m < factor * clock.n)
		4901	fp \|= FP_CB_TUNE;
		4902
		4903	dpll = 0;
		4904
		4905	if (is_lvds)
		4906	dpll \|= DPLLB_MODE_LVDS;
		4907	else
		4908	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4909	if (is_sdvo) {
		4910	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4911	if (pixel_multiplier > 1) {
		4912	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
		4913	}
		4914	dpll \|= DPLL_DVO_HIGH_SPEED;
		4915	}
3031	serge	4916	if (is_dp && !is_cpu_edp)
2327	Serge	4917	dpll \|= DPLL_DVO_HIGH_SPEED;
		4918
		4919	/* compute bitmask from p1 value */
		4920	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4921	/* also FPA1 */
		4922	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4923
		4924	switch (clock.p2) {
		4925	case 5:
		4926	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4927	break;
		4928	case 7:
		4929	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4930	break;
		4931	case 10:
		4932	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4933	break;
		4934	case 14:
		4935	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4936	break;
		4937	}
		4938
		4939	if (is_sdvo && is_tv)
		4940	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4941	else if (is_tv)
		4942	/* XXX: just matching BIOS for now */
		4943	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4944	dpll \|= 3;
		4945	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4946	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4947	else
		4948	dpll \|= PLL_REF_INPUT_DREFCLK;
		4949
2342	Serge	4950	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
2327	Serge	4951	drm_mode_debug_printmodeline(mode);
		4952
3031	serge	4953	/* CPU eDP is the only output that doesn't need a PCH PLL of its own on
		4954	* pre-Haswell/LPT generation */
		4955	if (HAS_PCH_LPT(dev)) {
		4956	DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
		4957	pipe);
		4958	} else if (!is_cpu_edp) {
		4959	struct intel_pch_pll *pll;
2327	Serge	4960
3031	serge	4961	pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		4962	if (pll == NULL) {
		4963	DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
		4964	pipe);
2342	Serge	4965	return -EINVAL;
2327	Serge	4966	}
3031	serge	4967	} else
		4968	intel_put_pch_pll(intel_crtc);
2327	Serge	4969
		4970	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4971	* This is an exception to the general rule that mode_set doesn't turn
		4972	* things on.
		4973	*/
		4974	if (is_lvds) {
		4975	temp = I915_READ(PCH_LVDS);
		4976	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
2342	Serge	4977	if (HAS_PCH_CPT(dev)) {
		4978	temp &= ~PORT_TRANS_SEL_MASK;
		4979	temp \|= PORT_TRANS_SEL_CPT(pipe);
		4980	} else {
		4981	if (pipe == 1)
2327	Serge	4982	temp \|= LVDS_PIPEB_SELECT;
		4983	else
		4984	temp &= ~LVDS_PIPEB_SELECT;
		4985	}
2342	Serge	4986
2327	Serge	4987	/* set the corresponsding LVDS_BORDER bit */
		4988	temp \|= dev_priv->lvds_border_bits;
		4989	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4990	* set the DPLLs for dual-channel mode or not.
		4991	*/
		4992	if (clock.p2 == 7)
		4993	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		4994	else
		4995	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		4996
		4997	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		4998	* appropriately here, but we need to look more thoroughly into how
		4999	* panels behave in the two modes.
		5000	*/
3031	serge	5001	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
2327	Serge	5002	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3031	serge	5003	temp \|= LVDS_HSYNC_POLARITY;
2327	Serge	5004	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3031	serge	5005	temp \|= LVDS_VSYNC_POLARITY;
2327	Serge	5006	I915_WRITE(PCH_LVDS, temp);
		5007	}
		5008
3031	serge	5009	if (is_dp && !is_cpu_edp) {
2327	Serge	5010	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		5011	} else {
		5012	/* For non-DP output, clear any trans DP clock recovery setting.*/
		5013	I915_WRITE(TRANSDATA_M1(pipe), 0);
		5014	I915_WRITE(TRANSDATA_N1(pipe), 0);
		5015	I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		5016	I915_WRITE(TRANSDPLINK_N1(pipe), 0);
		5017	}
		5018
3031	serge	5019	if (intel_crtc->pch_pll) {
		5020	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5021
		5022	/* Wait for the clocks to stabilize. */
3031	serge	5023	POSTING_READ(intel_crtc->pch_pll->pll_reg);
2327	Serge	5024	udelay(150);
		5025
		5026	/* The pixel multiplier can only be updated once the
		5027	* DPLL is enabled and the clocks are stable.
		5028	*
		5029	* So write it again.
		5030	*/
3031	serge	5031	I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
2327	Serge	5032	}
		5033
		5034	intel_crtc->lowfreq_avail = false;
3031	serge	5035	if (intel_crtc->pch_pll) {
2327	Serge	5036	if (is_lvds && has_reduced_clock && i915_powersave) {
3031	serge	5037	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
2327	Serge	5038	intel_crtc->lowfreq_avail = true;
		5039	} else {
3031	serge	5040	I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
2327	Serge	5041	}
2342	Serge	5042	}
2327	Serge	5043
		5044	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5045	/* the chip adds 2 halflines automatically */
		5046	adjusted_mode->crtc_vtotal -= 1;
		5047	adjusted_mode->crtc_vblank_end -= 1;
3031	serge	5048	I915_WRITE(VSYNCSHIFT(pipe),
		5049	adjusted_mode->crtc_hsync_start
		5050	- adjusted_mode->crtc_htotal/2);
		5051	} else {
		5052	I915_WRITE(VSYNCSHIFT(pipe), 0);
		5053	}
2327	Serge	5054
		5055	I915_WRITE(HTOTAL(pipe),
		5056	(adjusted_mode->crtc_hdisplay - 1) \|
		5057	((adjusted_mode->crtc_htotal - 1) << 16));
		5058	I915_WRITE(HBLANK(pipe),
		5059	(adjusted_mode->crtc_hblank_start - 1) \|
		5060	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5061	I915_WRITE(HSYNC(pipe),
		5062	(adjusted_mode->crtc_hsync_start - 1) \|
		5063	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5064
		5065	I915_WRITE(VTOTAL(pipe),
		5066	(adjusted_mode->crtc_vdisplay - 1) \|
		5067	((adjusted_mode->crtc_vtotal - 1) << 16));
		5068	I915_WRITE(VBLANK(pipe),
		5069	(adjusted_mode->crtc_vblank_start - 1) \|
		5070	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5071	I915_WRITE(VSYNC(pipe),
		5072	(adjusted_mode->crtc_vsync_start - 1) \|
		5073	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5074
		5075	/* pipesrc controls the size that is scaled from, which should
		5076	* always be the user's requested size.
		5077	*/
		5078	I915_WRITE(PIPESRC(pipe),
		5079	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5080
		5081	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);
		5082	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		5083	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		5084	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
		5085
3031	serge	5086	if (is_cpu_edp)
2327	Serge	5087	ironlake_set_pll_edp(crtc, adjusted_mode->clock);
		5088
3031	serge	5089	ironlake_set_pipeconf(crtc, adjusted_mode, dither);
2327	Serge	5090
		5091	intel_wait_for_vblank(dev, pipe);
		5092
3031	serge	5093	/* Set up the display plane register */
		5094	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
2327	Serge	5095	POSTING_READ(DSPCNTR(plane));
		5096
3031	serge	5097	ret = intel_pipe_set_base(crtc, x, y, fb);
2327	Serge	5098
		5099	intel_update_watermarks(dev);
		5100
3031	serge	5101	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
2336	Serge	5102
2327	Serge	5103	return ret;
		5104	}
		5105
2330	Serge	5106	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		5107	struct drm_display_mode *mode,
		5108	struct drm_display_mode *adjusted_mode,
		5109	int x, int y,
3031	serge	5110	struct drm_framebuffer *fb)
2330	Serge	5111	{
		5112	struct drm_device *dev = crtc->dev;
		5113	struct drm_i915_private *dev_priv = dev->dev_private;
		5114	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5115	int pipe = intel_crtc->pipe;
		5116	int ret;
2327	Serge	5117
3031	serge	5118	drm_vblank_pre_modeset(dev, pipe);
2327	Serge	5119
2330	Serge	5120	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
3031	serge	5121	x, y, fb);
		5122	drm_vblank_post_modeset(dev, pipe);
2327	Serge	5123
2330	Serge	5124	return ret;
		5125	}
2327	Serge	5126
2342	Serge	5127	static bool intel_eld_uptodate(struct drm_connector *connector,
		5128	int reg_eldv, uint32_t bits_eldv,
		5129	int reg_elda, uint32_t bits_elda,
		5130	int reg_edid)
		5131	{
		5132	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5133	uint8_t *eld = connector->eld;
		5134	uint32_t i;
		5135
		5136	i = I915_READ(reg_eldv);
		5137	i &= bits_eldv;
		5138
		5139	if (!eld[0])
		5140	return !i;
		5141
		5142	if (!i)
		5143	return false;
		5144
		5145	i = I915_READ(reg_elda);
		5146	i &= ~bits_elda;
		5147	I915_WRITE(reg_elda, i);
		5148
		5149	for (i = 0; i < eld[2]; i++)
		5150	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
		5151	return false;
		5152
		5153	return true;
		5154	}
		5155
		5156	static void g4x_write_eld(struct drm_connector *connector,
		5157	struct drm_crtc *crtc)
		5158	{
		5159	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5160	uint8_t *eld = connector->eld;
		5161	uint32_t eldv;
		5162	uint32_t len;
		5163	uint32_t i;
		5164
		5165	i = I915_READ(G4X_AUD_VID_DID);
		5166
		5167	if (i == INTEL_AUDIO_DEVBLC \|\| i == INTEL_AUDIO_DEVCL)
		5168	eldv = G4X_ELDV_DEVCL_DEVBLC;
		5169	else
		5170	eldv = G4X_ELDV_DEVCTG;
		5171
		5172	if (intel_eld_uptodate(connector,
		5173	G4X_AUD_CNTL_ST, eldv,
		5174	G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
		5175	G4X_HDMIW_HDMIEDID))
		5176	return;
		5177
		5178	i = I915_READ(G4X_AUD_CNTL_ST);
		5179	i &= ~(eldv \| G4X_ELD_ADDR);
		5180	len = (i >> 9) & 0x1f; /* ELD buffer size */
		5181	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5182
		5183	if (!eld[0])
		5184	return;
		5185
		5186	len = min_t(uint8_t, eld[2], len);
		5187	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5188	for (i = 0; i < len; i++)
		5189	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
		5190
		5191	i = I915_READ(G4X_AUD_CNTL_ST);
		5192	i \|= eldv;
		5193	I915_WRITE(G4X_AUD_CNTL_ST, i);
		5194	}
		5195
3031	serge	5196	static void haswell_write_eld(struct drm_connector *connector,
		5197	struct drm_crtc *crtc)
		5198	{
		5199	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5200	uint8_t *eld = connector->eld;
		5201	struct drm_device *dev = crtc->dev;
		5202	uint32_t eldv;
		5203	uint32_t i;
		5204	int len;
		5205	int pipe = to_intel_crtc(crtc)->pipe;
		5206	int tmp;
		5207
		5208	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
		5209	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
		5210	int aud_config = HSW_AUD_CFG(pipe);
		5211	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
		5212
		5213
		5214	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
		5215
		5216	/* Audio output enable */
		5217	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
		5218	tmp = I915_READ(aud_cntrl_st2);
		5219	tmp \|= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
		5220	I915_WRITE(aud_cntrl_st2, tmp);
		5221
		5222	/* Wait for 1 vertical blank */
		5223	intel_wait_for_vblank(dev, pipe);
		5224
		5225	/* Set ELD valid state */
		5226	tmp = I915_READ(aud_cntrl_st2);
		5227	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
		5228	tmp \|= (AUDIO_ELD_VALID_A << (pipe * 4));
		5229	I915_WRITE(aud_cntrl_st2, tmp);
		5230	tmp = I915_READ(aud_cntrl_st2);
		5231	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
		5232
		5233	/* Enable HDMI mode */
		5234	tmp = I915_READ(aud_config);
		5235	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
		5236	/* clear N_programing_enable and N_value_index */
		5237	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX \| AUD_CONFIG_N_PROG_ENABLE);
		5238	I915_WRITE(aud_config, tmp);
		5239
		5240	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
		5241
		5242	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
		5243
		5244	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		5245	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		5246	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
		5247	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		5248	} else
		5249	I915_WRITE(aud_config, 0);
		5250
		5251	if (intel_eld_uptodate(connector,
		5252	aud_cntrl_st2, eldv,
		5253	aud_cntl_st, IBX_ELD_ADDRESS,
		5254	hdmiw_hdmiedid))
		5255	return;
		5256
		5257	i = I915_READ(aud_cntrl_st2);
		5258	i &= ~eldv;
		5259	I915_WRITE(aud_cntrl_st2, i);
		5260
		5261	if (!eld[0])
		5262	return;
		5263
		5264	i = I915_READ(aud_cntl_st);
		5265	i &= ~IBX_ELD_ADDRESS;
		5266	I915_WRITE(aud_cntl_st, i);
		5267	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
		5268	DRM_DEBUG_DRIVER("port num:%d\n", i);
		5269
		5270	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		5271	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5272	for (i = 0; i < len; i++)
		5273	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		5274
		5275	i = I915_READ(aud_cntrl_st2);
		5276	i \|= eldv;
		5277	I915_WRITE(aud_cntrl_st2, i);
		5278
		5279	}
		5280
2342	Serge	5281	static void ironlake_write_eld(struct drm_connector *connector,
		5282	struct drm_crtc *crtc)
		5283	{
		5284	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		5285	uint8_t *eld = connector->eld;
		5286	uint32_t eldv;
		5287	uint32_t i;
		5288	int len;
		5289	int hdmiw_hdmiedid;
3031	serge	5290	int aud_config;
2342	Serge	5291	int aud_cntl_st;
		5292	int aud_cntrl_st2;
3031	serge	5293	int pipe = to_intel_crtc(crtc)->pipe;
2342	Serge	5294
		5295	if (HAS_PCH_IBX(connector->dev)) {
3031	serge	5296	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		5297	aud_config = IBX_AUD_CFG(pipe);
		5298	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
2342	Serge	5299	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
		5300	} else {
3031	serge	5301	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		5302	aud_config = CPT_AUD_CFG(pipe);
		5303	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
2342	Serge	5304	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
		5305	}
		5306
3031	serge	5307	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
2342	Serge	5308
		5309	i = I915_READ(aud_cntl_st);
3031	serge	5310	i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
2342	Serge	5311	if (!i) {
		5312	DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		5313	/* operate blindly on all ports */
		5314	eldv = IBX_ELD_VALIDB;
		5315	eldv \|= IBX_ELD_VALIDB << 4;
		5316	eldv \|= IBX_ELD_VALIDB << 8;
		5317	} else {
		5318	DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
		5319	eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
		5320	}
		5321
		5322	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		5323	DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		5324	eld[5] \|= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
3031	serge	5325	I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
		5326	} else
		5327	I915_WRITE(aud_config, 0);
2342	Serge	5328
		5329	if (intel_eld_uptodate(connector,
		5330	aud_cntrl_st2, eldv,
		5331	aud_cntl_st, IBX_ELD_ADDRESS,
		5332	hdmiw_hdmiedid))
		5333	return;
		5334
		5335	i = I915_READ(aud_cntrl_st2);
		5336	i &= ~eldv;
		5337	I915_WRITE(aud_cntrl_st2, i);
		5338
		5339	if (!eld[0])
		5340	return;
		5341
		5342	i = I915_READ(aud_cntl_st);
		5343	i &= ~IBX_ELD_ADDRESS;
		5344	I915_WRITE(aud_cntl_st, i);
		5345
		5346	len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
		5347	DRM_DEBUG_DRIVER("ELD size %d\n", len);
		5348	for (i = 0; i < len; i++)
		5349	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
		5350
		5351	i = I915_READ(aud_cntrl_st2);
		5352	i \|= eldv;
		5353	I915_WRITE(aud_cntrl_st2, i);
		5354	}
		5355
		5356	void intel_write_eld(struct drm_encoder *encoder,
		5357	struct drm_display_mode *mode)
		5358	{
		5359	struct drm_crtc *crtc = encoder->crtc;
		5360	struct drm_connector *connector;
		5361	struct drm_device *dev = encoder->dev;
		5362	struct drm_i915_private *dev_priv = dev->dev_private;
		5363
		5364	connector = drm_select_eld(encoder, mode);
		5365	if (!connector)
		5366	return;
		5367
		5368	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5369	connector->base.id,
		5370	drm_get_connector_name(connector),
		5371	connector->encoder->base.id,
		5372	drm_get_encoder_name(connector->encoder));
		5373
		5374	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
		5375
		5376	if (dev_priv->display.write_eld)
		5377	dev_priv->display.write_eld(connector, crtc);
		5378	}
		5379
2327	Serge	5380	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		5381	void intel_crtc_load_lut(struct drm_crtc *crtc)
		5382	{
		5383	struct drm_device *dev = crtc->dev;
		5384	struct drm_i915_private *dev_priv = dev->dev_private;
		5385	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5386	int palreg = PALETTE(intel_crtc->pipe);
		5387	int i;
		5388
		5389	/* The clocks have to be on to load the palette. */
3031	serge	5390	if (!crtc->enabled \|\| !intel_crtc->active)
2327	Serge	5391	return;
		5392
		5393	/* use legacy palette for Ironlake */
		5394	if (HAS_PCH_SPLIT(dev))
		5395	palreg = LGC_PALETTE(intel_crtc->pipe);
		5396
		5397	for (i = 0; i < 256; i++) {
		5398	I915_WRITE(palreg + 4 * i,
		5399	(intel_crtc->lut_r[i] << 16) \|
		5400	(intel_crtc->lut_g[i] << 8) \|
		5401	intel_crtc->lut_b[i]);
		5402	}
		5403	}
		5404
3031	serge	5405	#if 0
		5406	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
		5407	{
		5408	struct drm_device *dev = crtc->dev;
		5409	struct drm_i915_private *dev_priv = dev->dev_private;
		5410	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5411	bool visible = base != 0;
		5412	u32 cntl;
2327	Serge	5413
3031	serge	5414	if (intel_crtc->cursor_visible == visible)
		5415	return;
2327	Serge	5416
3031	serge	5417	cntl = I915_READ(_CURACNTR);
		5418	if (visible) {
		5419	/* On these chipsets we can only modify the base whilst
		5420	* the cursor is disabled.
		5421	*/
		5422	I915_WRITE(_CURABASE, base);
2327	Serge	5423
3031	serge	5424	cntl &= ~(CURSOR_FORMAT_MASK);
		5425	/* XXX width must be 64, stride 256 => 0x00 << 28 */
		5426	cntl \|= CURSOR_ENABLE \|
		5427	CURSOR_GAMMA_ENABLE \|
		5428	CURSOR_FORMAT_ARGB;
		5429	} else
		5430	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
		5431	I915_WRITE(_CURACNTR, cntl);
2327	Serge	5432
3031	serge	5433	intel_crtc->cursor_visible = visible;
		5434	}
2327	Serge	5435
3031	serge	5436	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
		5437	{
		5438	struct drm_device *dev = crtc->dev;
		5439	struct drm_i915_private *dev_priv = dev->dev_private;
		5440	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5441	int pipe = intel_crtc->pipe;
		5442	bool visible = base != 0;
2327	Serge	5443
3031	serge	5444	if (intel_crtc->cursor_visible != visible) {
		5445	uint32_t cntl = I915_READ(CURCNTR(pipe));
		5446	if (base) {
		5447	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
		5448	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		5449	cntl \|= pipe << 28; /* Connect to correct pipe */
		5450	} else {
		5451	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		5452	cntl \|= CURSOR_MODE_DISABLE;
		5453	}
		5454	I915_WRITE(CURCNTR(pipe), cntl);
2327	Serge	5455
3031	serge	5456	intel_crtc->cursor_visible = visible;
		5457	}
		5458	/* and commit changes on next vblank */
		5459	I915_WRITE(CURBASE(pipe), base);
		5460	}
2327	Serge	5461
3031	serge	5462	static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
		5463	{
		5464	struct drm_device *dev = crtc->dev;
		5465	struct drm_i915_private *dev_priv = dev->dev_private;
		5466	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5467	int pipe = intel_crtc->pipe;
		5468	bool visible = base != 0;
2327	Serge	5469
3031	serge	5470	if (intel_crtc->cursor_visible != visible) {
		5471	uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		5472	if (base) {
		5473	cntl &= ~CURSOR_MODE;
		5474	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
		5475	} else {
		5476	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
		5477	cntl \|= CURSOR_MODE_DISABLE;
		5478	}
		5479	I915_WRITE(CURCNTR_IVB(pipe), cntl);
2327	Serge	5480
3031	serge	5481	intel_crtc->cursor_visible = visible;
		5482	}
		5483	/* and commit changes on next vblank */
		5484	I915_WRITE(CURBASE_IVB(pipe), base);
		5485	}
2327	Serge	5486
3031	serge	5487	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
		5488	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
		5489	bool on)
		5490	{
		5491	struct drm_device *dev = crtc->dev;
		5492	struct drm_i915_private *dev_priv = dev->dev_private;
		5493	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5494	int pipe = intel_crtc->pipe;
		5495	int x = intel_crtc->cursor_x;
		5496	int y = intel_crtc->cursor_y;
		5497	u32 base, pos;
		5498	bool visible;
2327	Serge	5499
3031	serge	5500	pos = 0;
2327	Serge	5501
3031	serge	5502	if (on && crtc->enabled && crtc->fb) {
		5503	base = intel_crtc->cursor_addr;
		5504	if (x > (int) crtc->fb->width)
		5505	base = 0;
2327	Serge	5506
3031	serge	5507	if (y > (int) crtc->fb->height)
		5508	base = 0;
		5509	} else
		5510	base = 0;
2327	Serge	5511
3031	serge	5512	if (x < 0) {
		5513	if (x + intel_crtc->cursor_width < 0)
		5514	base = 0;
2327	Serge	5515
3031	serge	5516	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		5517	x = -x;
		5518	}
		5519	pos \|= x << CURSOR_X_SHIFT;
2327	Serge	5520
3031	serge	5521	if (y < 0) {
		5522	if (y + intel_crtc->cursor_height < 0)
		5523	base = 0;
2327	Serge	5524
3031	serge	5525	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		5526	y = -y;
		5527	}
		5528	pos \|= y << CURSOR_Y_SHIFT;
2327	Serge	5529
3031	serge	5530	visible = base != 0;
		5531	if (!visible && !intel_crtc->cursor_visible)
		5532	return;
2327	Serge	5533
3031	serge	5534	if (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev)) {
		5535	I915_WRITE(CURPOS_IVB(pipe), pos);
		5536	ivb_update_cursor(crtc, base);
		5537	} else {
		5538	I915_WRITE(CURPOS(pipe), pos);
		5539	if (IS_845G(dev) \|\| IS_I865G(dev))
		5540	i845_update_cursor(crtc, base);
		5541	else
		5542	i9xx_update_cursor(crtc, base);
		5543	}
		5544	}
2327	Serge	5545
3031	serge	5546	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
		5547	struct drm_file *file,
		5548	uint32_t handle,
		5549	uint32_t width, uint32_t height)
		5550	{
		5551	struct drm_device *dev = crtc->dev;
		5552	struct drm_i915_private *dev_priv = dev->dev_private;
		5553	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5554	struct drm_i915_gem_object *obj;
		5555	uint32_t addr;
		5556	int ret;
2327	Serge	5557
3031	serge	5558	/* if we want to turn off the cursor ignore width and height */
		5559	if (!handle) {
		5560	DRM_DEBUG_KMS("cursor off\n");
		5561	addr = 0;
		5562	obj = NULL;
		5563	mutex_lock(&dev->struct_mutex);
		5564	goto finish;
		5565	}
2327	Serge	5566
3031	serge	5567	/* Currently we only support 64x64 cursors */
		5568	if (width != 64 \|\| height != 64) {
		5569	DRM_ERROR("we currently only support 64x64 cursors\n");
		5570	return -EINVAL;
		5571	}
2327	Serge	5572
3031	serge	5573	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
		5574	if (&obj->base == NULL)
		5575	return -ENOENT;
2327	Serge	5576
3031	serge	5577	if (obj->base.size < width * height * 4) {
		5578	DRM_ERROR("buffer is to small\n");
		5579	ret = -ENOMEM;
		5580	goto fail;
		5581	}
2327	Serge	5582
3031	serge	5583	/* we only need to pin inside GTT if cursor is non-phy */
		5584	mutex_lock(&dev->struct_mutex);
		5585	if (!dev_priv->info->cursor_needs_physical) {
		5586	if (obj->tiling_mode) {
		5587	DRM_ERROR("cursor cannot be tiled\n");
		5588	ret = -EINVAL;
		5589	goto fail_locked;
		5590	}
2327	Serge	5591
3031	serge	5592	ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
		5593	if (ret) {
		5594	DRM_ERROR("failed to move cursor bo into the GTT\n");
		5595	goto fail_locked;
		5596	}
2327	Serge	5597
3031	serge	5598	ret = i915_gem_object_put_fence(obj);
		5599	if (ret) {
		5600	DRM_ERROR("failed to release fence for cursor");
		5601	goto fail_unpin;
		5602	}
2327	Serge	5603
3031	serge	5604	addr = obj->gtt_offset;
		5605	} else {
		5606	int align = IS_I830(dev) ? 16 * 1024 : 256;
		5607	ret = i915_gem_attach_phys_object(dev, obj,
		5608	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
		5609	align);
		5610	if (ret) {
		5611	DRM_ERROR("failed to attach phys object\n");
		5612	goto fail_locked;
		5613	}
		5614	addr = obj->phys_obj->handle->busaddr;
		5615	}
2327	Serge	5616
3031	serge	5617	if (IS_GEN2(dev))
		5618	I915_WRITE(CURSIZE, (height << 12) \| width);
2327	Serge	5619
3031	serge	5620	finish:
		5621	if (intel_crtc->cursor_bo) {
		5622	if (dev_priv->info->cursor_needs_physical) {
		5623	if (intel_crtc->cursor_bo != obj)
		5624	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		5625	} else
		5626	i915_gem_object_unpin(intel_crtc->cursor_bo);
		5627	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
		5628	}
2327	Serge	5629
3031	serge	5630	mutex_unlock(&dev->struct_mutex);
2327	Serge	5631
3031	serge	5632	intel_crtc->cursor_addr = addr;
		5633	intel_crtc->cursor_bo = obj;
		5634	intel_crtc->cursor_width = width;
		5635	intel_crtc->cursor_height = height;
2327	Serge	5636
3031	serge	5637	// intel_crtc_update_cursor(crtc, true);
2327	Serge	5638
3031	serge	5639	return 0;
		5640	fail_unpin:
		5641	i915_gem_object_unpin(obj);
		5642	fail_locked:
		5643	mutex_unlock(&dev->struct_mutex);
		5644	fail:
		5645	drm_gem_object_unreference_unlocked(&obj->base);
		5646	return ret;
		5647	}
2327	Serge	5648
3031	serge	5649	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
		5650	{
		5651	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5652
		5653	intel_crtc->cursor_x = x;
		5654	intel_crtc->cursor_y = y;
		5655
		5656	// intel_crtc_update_cursor(crtc, true);
		5657
		5658	return 0;
		5659	}
		5660	#endif
		5661
2332	Serge	5662	/** Sets the color ramps on behalf of RandR */
		5663	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		5664	u16 blue, int regno)
		5665	{
		5666	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5667
2332	Serge	5668	intel_crtc->lut_r[regno] = red >> 8;
		5669	intel_crtc->lut_g[regno] = green >> 8;
		5670	intel_crtc->lut_b[regno] = blue >> 8;
		5671	}
2327	Serge	5672
2332	Serge	5673	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		5674	u16 *blue, int regno)
		5675	{
		5676	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5677
2332	Serge	5678	*red = intel_crtc->lut_r[regno] << 8;
		5679	*green = intel_crtc->lut_g[regno] << 8;
		5680	*blue = intel_crtc->lut_b[regno] << 8;
		5681	}
2327	Serge	5682
2330	Serge	5683	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		5684	u16 *blue, uint32_t start, uint32_t size)
		5685	{
		5686	int end = (start + size > 256) ? 256 : start + size, i;
		5687	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5688
2330	Serge	5689	for (i = start; i < end; i++) {
		5690	intel_crtc->lut_r[i] = red[i] >> 8;
		5691	intel_crtc->lut_g[i] = green[i] >> 8;
		5692	intel_crtc->lut_b[i] = blue[i] >> 8;
		5693	}
2327	Serge	5694
2330	Serge	5695	intel_crtc_load_lut(crtc);
		5696	}
2327	Serge	5697
2330	Serge	5698	/**
		5699	* Get a pipe with a simple mode set on it for doing load-based monitor
		5700	* detection.
		5701	*
		5702	* It will be up to the load-detect code to adjust the pipe as appropriate for
		5703	* its requirements. The pipe will be connected to no other encoders.
		5704	*
		5705	* Currently this code will only succeed if there is a pipe with no encoders
		5706	* configured for it. In the future, it could choose to temporarily disable
		5707	* some outputs to free up a pipe for its use.
		5708	*
		5709	* \return crtc, or NULL if no pipes are available.
		5710	*/
2327	Serge	5711
2330	Serge	5712	/* VESA 640x480x72Hz mode to set on the pipe */
		5713	static struct drm_display_mode load_detect_mode = {
		5714	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		5715	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		5716	};
2327	Serge	5717
3031	serge	5718	static struct drm_framebuffer *
		5719	intel_framebuffer_create(struct drm_device *dev,
		5720	struct drm_mode_fb_cmd2 *mode_cmd,
		5721	struct drm_i915_gem_object *obj)
		5722	{
		5723	struct intel_framebuffer *intel_fb;
		5724	int ret;
2327	Serge	5725
3031	serge	5726	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
		5727	if (!intel_fb) {
		5728	drm_gem_object_unreference_unlocked(&obj->base);
		5729	return ERR_PTR(-ENOMEM);
		5730	}
2327	Serge	5731
3031	serge	5732	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
		5733	if (ret) {
		5734	drm_gem_object_unreference_unlocked(&obj->base);
		5735	kfree(intel_fb);
		5736	return ERR_PTR(ret);
		5737	}
2327	Serge	5738
3031	serge	5739	return &intel_fb->base;
		5740	}
2327	Serge	5741
2330	Serge	5742	static u32
		5743	intel_framebuffer_pitch_for_width(int width, int bpp)
		5744	{
		5745	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		5746	return ALIGN(pitch, 64);
		5747	}
2327	Serge	5748
2330	Serge	5749	static u32
		5750	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		5751	{
		5752	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		5753	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		5754	}
2327	Serge	5755
2330	Serge	5756	static struct drm_framebuffer *
		5757	intel_framebuffer_create_for_mode(struct drm_device *dev,
		5758	struct drm_display_mode *mode,
		5759	int depth, int bpp)
		5760	{
		5761	struct drm_i915_gem_object *obj;
2344	Serge	5762	struct drm_mode_fb_cmd2 mode_cmd;
2327	Serge	5763
2330	Serge	5764	// obj = i915_gem_alloc_object(dev,
		5765	// intel_framebuffer_size_for_mode(mode, bpp));
		5766	// if (obj == NULL)
		5767	return ERR_PTR(-ENOMEM);
2327	Serge	5768
2330	Serge	5769	// mode_cmd.width = mode->hdisplay;
		5770	// mode_cmd.height = mode->vdisplay;
		5771	// mode_cmd.depth = depth;
		5772	// mode_cmd.bpp = bpp;
		5773	// mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327	Serge	5774
2330	Serge	5775	// return intel_framebuffer_create(dev, &mode_cmd, obj);
		5776	}
2327	Serge	5777
2330	Serge	5778	static struct drm_framebuffer *
		5779	mode_fits_in_fbdev(struct drm_device *dev,
		5780	struct drm_display_mode *mode)
		5781	{
		5782	struct drm_i915_private *dev_priv = dev->dev_private;
		5783	struct drm_i915_gem_object *obj;
		5784	struct drm_framebuffer *fb;
2327	Serge	5785
2330	Serge	5786	// if (dev_priv->fbdev == NULL)
		5787	// return NULL;
2327	Serge	5788
2330	Serge	5789	// obj = dev_priv->fbdev->ifb.obj;
		5790	// if (obj == NULL)
		5791	return NULL;
2327	Serge	5792
2330	Serge	5793	// if (obj->base.size < mode->vdisplay * fb->pitch)
3031	serge	5794	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
		5795	fb->bits_per_pixel))
2330	Serge	5796	// return NULL;
2327	Serge	5797
3031	serge	5798	if (obj->base.size < mode->vdisplay * fb->pitches[0])
		5799	return NULL;
		5800
2330	Serge	5801	// return fb;
		5802	}
2327	Serge	5803
3031	serge	5804	bool intel_get_load_detect_pipe(struct drm_connector *connector,
2330	Serge	5805	struct drm_display_mode *mode,
		5806	struct intel_load_detect_pipe *old)
		5807	{
		5808	struct intel_crtc *intel_crtc;
3031	serge	5809	struct intel_encoder *intel_encoder =
		5810	intel_attached_encoder(connector);
2330	Serge	5811	struct drm_crtc *possible_crtc;
		5812	struct drm_encoder *encoder = &intel_encoder->base;
		5813	struct drm_crtc *crtc = NULL;
		5814	struct drm_device *dev = encoder->dev;
3031	serge	5815	struct drm_framebuffer *fb;
2330	Serge	5816	int i = -1;
2327	Serge	5817
2330	Serge	5818	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5819	connector->base.id, drm_get_connector_name(connector),
		5820	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5821
2330	Serge	5822	/*
		5823	* Algorithm gets a little messy:
		5824	*
		5825	* - if the connector already has an assigned crtc, use it (but make
		5826	* sure it's on first)
		5827	*
		5828	* - try to find the first unused crtc that can drive this connector,
		5829	* and use that if we find one
		5830	*/
2327	Serge	5831
2330	Serge	5832	/* See if we already have a CRTC for this connector */
		5833	if (encoder->crtc) {
		5834	crtc = encoder->crtc;
2327	Serge	5835
3031	serge	5836	old->dpms_mode = connector->dpms;
2330	Serge	5837	old->load_detect_temp = false;
2327	Serge	5838
2330	Serge	5839	/* Make sure the crtc and connector are running */
3031	serge	5840	if (connector->dpms != DRM_MODE_DPMS_ON)
		5841	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
2327	Serge	5842
2330	Serge	5843	return true;
		5844	}
2327	Serge	5845
2330	Serge	5846	/* Find an unused one (if possible) */
		5847	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		5848	i++;
		5849	if (!(encoder->possible_crtcs & (1 << i)))
		5850	continue;
		5851	if (!possible_crtc->enabled) {
		5852	crtc = possible_crtc;
		5853	break;
		5854	}
		5855	}
2327	Serge	5856
2330	Serge	5857	/*
		5858	* If we didn't find an unused CRTC, don't use any.
		5859	*/
		5860	if (!crtc) {
		5861	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		5862	return false;
		5863	}
2327	Serge	5864
3031	serge	5865	intel_encoder->new_crtc = to_intel_crtc(crtc);
		5866	to_intel_connector(connector)->new_encoder = intel_encoder;
2327	Serge	5867
2330	Serge	5868	intel_crtc = to_intel_crtc(crtc);
3031	serge	5869	old->dpms_mode = connector->dpms;
2330	Serge	5870	old->load_detect_temp = true;
		5871	old->release_fb = NULL;
2327	Serge	5872
2330	Serge	5873	if (!mode)
		5874	mode = &load_detect_mode;
2327	Serge	5875
2330	Serge	5876	/* We need a framebuffer large enough to accommodate all accesses
		5877	* that the plane may generate whilst we perform load detection.
		5878	* We can not rely on the fbcon either being present (we get called
		5879	* during its initialisation to detect all boot displays, or it may
		5880	* not even exist) or that it is large enough to satisfy the
		5881	* requested mode.
		5882	*/
3031	serge	5883	fb = mode_fits_in_fbdev(dev, mode);
		5884	if (fb == NULL) {
2330	Serge	5885	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
3031	serge	5886	fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		5887	old->release_fb = fb;
2330	Serge	5888	} else
		5889	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
3031	serge	5890	if (IS_ERR(fb)) {
2330	Serge	5891	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
3031	serge	5892	goto fail;
2330	Serge	5893	}
2327	Serge	5894
3031	serge	5895	if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
2330	Serge	5896	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		5897	if (old->release_fb)
		5898	old->release_fb->funcs->destroy(old->release_fb);
3031	serge	5899	goto fail;
2330	Serge	5900	}
2327	Serge	5901
2330	Serge	5902	/* let the connector get through one full cycle before testing */
		5903	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	5904
2330	Serge	5905	return true;
3031	serge	5906	fail:
		5907	connector->encoder = NULL;
		5908	encoder->crtc = NULL;
		5909	return false;
2330	Serge	5910	}
2327	Serge	5911
3031	serge	5912	void intel_release_load_detect_pipe(struct drm_connector *connector,
2330	Serge	5913	struct intel_load_detect_pipe *old)
		5914	{
3031	serge	5915	struct intel_encoder *intel_encoder =
		5916	intel_attached_encoder(connector);
2330	Serge	5917	struct drm_encoder *encoder = &intel_encoder->base;
2327	Serge	5918
2330	Serge	5919	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5920	connector->base.id, drm_get_connector_name(connector),
		5921	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5922
2330	Serge	5923	if (old->load_detect_temp) {
3031	serge	5924	struct drm_crtc *crtc = encoder->crtc;
2327	Serge	5925
3031	serge	5926	to_intel_connector(connector)->new_encoder = NULL;
		5927	intel_encoder->new_crtc = NULL;
		5928	intel_set_mode(crtc, NULL, 0, 0, NULL);
		5929
2330	Serge	5930	if (old->release_fb)
		5931	old->release_fb->funcs->destroy(old->release_fb);
2327	Serge	5932
2330	Serge	5933	return;
		5934	}
2327	Serge	5935
2330	Serge	5936	/* Switch crtc and encoder back off if necessary */
3031	serge	5937	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		5938	connector->funcs->dpms(connector, old->dpms_mode);
2330	Serge	5939	}
2327	Serge	5940
2330	Serge	5941	/* Returns the clock of the currently programmed mode of the given pipe. */
		5942	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
		5943	{
		5944	struct drm_i915_private *dev_priv = dev->dev_private;
		5945	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5946	int pipe = intel_crtc->pipe;
		5947	u32 dpll = I915_READ(DPLL(pipe));
		5948	u32 fp;
		5949	intel_clock_t clock;
2327	Serge	5950
2330	Serge	5951	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		5952	fp = I915_READ(FP0(pipe));
		5953	else
		5954	fp = I915_READ(FP1(pipe));
2327	Serge	5955
2330	Serge	5956	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		5957	if (IS_PINEVIEW(dev)) {
		5958	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		5959	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		5960	} else {
		5961	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		5962	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		5963	}
2327	Serge	5964
2330	Serge	5965	if (!IS_GEN2(dev)) {
		5966	if (IS_PINEVIEW(dev))
		5967	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		5968	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		5969	else
		5970	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		5971	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	5972
2330	Serge	5973	switch (dpll & DPLL_MODE_MASK) {
		5974	case DPLLB_MODE_DAC_SERIAL:
		5975	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		5976	5 : 10;
		5977	break;
		5978	case DPLLB_MODE_LVDS:
		5979	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		5980	7 : 14;
		5981	break;
		5982	default:
		5983	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		5984	"mode\n", (int)(dpll & DPLL_MODE_MASK));
		5985	return 0;
		5986	}
2327	Serge	5987
2330	Serge	5988	/* XXX: Handle the 100Mhz refclk */
		5989	intel_clock(dev, 96000, &clock);
		5990	} else {
		5991	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	5992
2330	Serge	5993	if (is_lvds) {
		5994	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		5995	DPLL_FPA01_P1_POST_DIV_SHIFT);
		5996	clock.p2 = 14;
2327	Serge	5997
2330	Serge	5998	if ((dpll & PLL_REF_INPUT_MASK) ==
		5999	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		6000	/* XXX: might not be 66MHz */
		6001	intel_clock(dev, 66000, &clock);
		6002	} else
		6003	intel_clock(dev, 48000, &clock);
		6004	} else {
		6005	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		6006	clock.p1 = 2;
		6007	else {
		6008	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		6009	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		6010	}
		6011	if (dpll & PLL_P2_DIVIDE_BY_4)
		6012	clock.p2 = 4;
		6013	else
		6014	clock.p2 = 2;
2327	Serge	6015
2330	Serge	6016	intel_clock(dev, 48000, &clock);
		6017	}
		6018	}
2327	Serge	6019
2330	Serge	6020	/* XXX: It would be nice to validate the clocks, but we can't reuse
		6021	* i830PllIsValid() because it relies on the xf86_config connector
		6022	* configuration being accurate, which it isn't necessarily.
		6023	*/
2327	Serge	6024
2330	Serge	6025	return clock.dot;
		6026	}
2327	Serge	6027
2330	Serge	6028	/** Returns the currently programmed mode of the given pipe. */
		6029	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		6030	struct drm_crtc *crtc)
		6031	{
		6032	struct drm_i915_private *dev_priv = dev->dev_private;
		6033	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6034	int pipe = intel_crtc->pipe;
		6035	struct drm_display_mode *mode;
		6036	int htot = I915_READ(HTOTAL(pipe));
		6037	int hsync = I915_READ(HSYNC(pipe));
		6038	int vtot = I915_READ(VTOTAL(pipe));
		6039	int vsync = I915_READ(VSYNC(pipe));
2327	Serge	6040
2330	Serge	6041	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		6042	if (!mode)
		6043	return NULL;
		6044
		6045	mode->clock = intel_crtc_clock_get(dev, crtc);
		6046	mode->hdisplay = (htot & 0xffff) + 1;
		6047	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		6048	mode->hsync_start = (hsync & 0xffff) + 1;
		6049	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		6050	mode->vdisplay = (vtot & 0xffff) + 1;
		6051	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		6052	mode->vsync_start = (vsync & 0xffff) + 1;
		6053	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		6054
		6055	drm_mode_set_name(mode);
		6056
		6057	return mode;
		6058	}
		6059
2327	Serge	6060	static void intel_increase_pllclock(struct drm_crtc *crtc)
		6061	{
		6062	struct drm_device *dev = crtc->dev;
		6063	drm_i915_private_t *dev_priv = dev->dev_private;
		6064	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6065	int pipe = intel_crtc->pipe;
		6066	int dpll_reg = DPLL(pipe);
		6067	int dpll;
		6068
		6069	if (HAS_PCH_SPLIT(dev))
		6070	return;
		6071
		6072	if (!dev_priv->lvds_downclock_avail)
		6073	return;
		6074
		6075	dpll = I915_READ(dpll_reg);
		6076	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		6077	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		6078
3031	serge	6079	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6080
		6081	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		6082	I915_WRITE(dpll_reg, dpll);
		6083	intel_wait_for_vblank(dev, pipe);
		6084
		6085	dpll = I915_READ(dpll_reg);
		6086	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		6087	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		6088	}
		6089	}
		6090
3031	serge	6091	static void intel_decrease_pllclock(struct drm_crtc *crtc)
		6092	{
		6093	struct drm_device *dev = crtc->dev;
		6094	drm_i915_private_t *dev_priv = dev->dev_private;
		6095	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6096
3031	serge	6097	if (HAS_PCH_SPLIT(dev))
		6098	return;
2327	Serge	6099
3031	serge	6100	if (!dev_priv->lvds_downclock_avail)
		6101	return;
2327	Serge	6102
3031	serge	6103	/*
		6104	* Since this is called by a timer, we should never get here in
		6105	* the manual case.
		6106	*/
		6107	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		6108	int pipe = intel_crtc->pipe;
		6109	int dpll_reg = DPLL(pipe);
		6110	int dpll;
2327	Serge	6111
3031	serge	6112	DRM_DEBUG_DRIVER("downclocking LVDS\n");
2327	Serge	6113
3031	serge	6114	assert_panel_unlocked(dev_priv, pipe);
2327	Serge	6115
3031	serge	6116	dpll = I915_READ(dpll_reg);
		6117	dpll \|= DISPLAY_RATE_SELECT_FPA1;
		6118	I915_WRITE(dpll_reg, dpll);
		6119	intel_wait_for_vblank(dev, pipe);
		6120	dpll = I915_READ(dpll_reg);
		6121	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
		6122	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
		6123	}
2327	Serge	6124
3031	serge	6125	}
2327	Serge	6126
3031	serge	6127	void intel_mark_busy(struct drm_device *dev)
		6128	{
		6129	i915_update_gfx_val(dev->dev_private);
		6130	}
2327	Serge	6131
3031	serge	6132	void intel_mark_idle(struct drm_device *dev)
		6133	{
		6134	}
2327	Serge	6135
3031	serge	6136	void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
		6137	{
		6138	struct drm_device *dev = obj->base.dev;
		6139	struct drm_crtc *crtc;
2327	Serge	6140
3031	serge	6141	if (!i915_powersave)
		6142	return;
2327	Serge	6143
3031	serge	6144	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6145	if (!crtc->fb)
		6146	continue;
2327	Serge	6147
3031	serge	6148	if (to_intel_framebuffer(crtc->fb)->obj == obj)
		6149	intel_increase_pllclock(crtc);
		6150	}
		6151	}
2327	Serge	6152
3031	serge	6153	void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
		6154	{
		6155	struct drm_device *dev = obj->base.dev;
		6156	struct drm_crtc *crtc;
2327	Serge	6157
3031	serge	6158	if (!i915_powersave)
		6159	return;
2327	Serge	6160
3031	serge	6161	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		6162	if (!crtc->fb)
		6163	continue;
2327	Serge	6164
3031	serge	6165	if (to_intel_framebuffer(crtc->fb)->obj == obj)
		6166	intel_decrease_pllclock(crtc);
		6167	}
		6168	}
2327	Serge	6169
2330	Serge	6170	static void intel_crtc_destroy(struct drm_crtc *crtc)
		6171	{
		6172	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6173	struct drm_device *dev = crtc->dev;
		6174	struct intel_unpin_work *work;
		6175	unsigned long flags;
2327	Serge	6176
2330	Serge	6177	spin_lock_irqsave(&dev->event_lock, flags);
		6178	work = intel_crtc->unpin_work;
		6179	intel_crtc->unpin_work = NULL;
		6180	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6181
2330	Serge	6182	if (work) {
		6183	// cancel_work_sync(&work->work);
		6184	kfree(work);
		6185	}
2327	Serge	6186
2330	Serge	6187	drm_crtc_cleanup(crtc);
2327	Serge	6188
2330	Serge	6189	kfree(intel_crtc);
		6190	}
2327	Serge	6191
3031	serge	6192	#if 0
		6193	static void intel_unpin_work_fn(struct work_struct *__work)
		6194	{
		6195	struct intel_unpin_work *work =
		6196	container_of(__work, struct intel_unpin_work, work);
2327	Serge	6197
3031	serge	6198	mutex_lock(&work->dev->struct_mutex);
		6199	intel_unpin_fb_obj(work->old_fb_obj);
		6200	drm_gem_object_unreference(&work->pending_flip_obj->base);
		6201	drm_gem_object_unreference(&work->old_fb_obj->base);
2327	Serge	6202
3031	serge	6203	intel_update_fbc(work->dev);
		6204	mutex_unlock(&work->dev->struct_mutex);
		6205	kfree(work);
		6206	}
2327	Serge	6207
3031	serge	6208	static void do_intel_finish_page_flip(struct drm_device *dev,
		6209	struct drm_crtc *crtc)
		6210	{
		6211	drm_i915_private_t *dev_priv = dev->dev_private;
		6212	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6213	struct intel_unpin_work *work;
		6214	struct drm_i915_gem_object *obj;
		6215	struct drm_pending_vblank_event *e;
		6216	struct timeval tvbl;
		6217	unsigned long flags;
2327	Serge	6218
3031	serge	6219	/* Ignore early vblank irqs */
		6220	if (intel_crtc == NULL)
		6221	return;
2327	Serge	6222
3031	serge	6223	spin_lock_irqsave(&dev->event_lock, flags);
		6224	work = intel_crtc->unpin_work;
		6225	if (work == NULL \|\| !work->pending) {
		6226	spin_unlock_irqrestore(&dev->event_lock, flags);
		6227	return;
		6228	}
2327	Serge	6229
3031	serge	6230	intel_crtc->unpin_work = NULL;
2327	Serge	6231
3031	serge	6232	if (work->event) {
		6233	e = work->event;
		6234	e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
2327	Serge	6235
3031	serge	6236	e->event.tv_sec = tvbl.tv_sec;
		6237	e->event.tv_usec = tvbl.tv_usec;
2327	Serge	6238
3031	serge	6239	list_add_tail(&e->base.link,
		6240	&e->base.file_priv->event_list);
		6241	wake_up_interruptible(&e->base.file_priv->event_wait);
		6242	}
2327	Serge	6243
3031	serge	6244	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	6245
3031	serge	6246	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6247
3031	serge	6248	obj = work->old_fb_obj;
2327	Serge	6249
3031	serge	6250	atomic_clear_mask(1 << intel_crtc->plane,
		6251	&obj->pending_flip.counter);
2327	Serge	6252
3031	serge	6253	wake_up(&dev_priv->pending_flip_queue);
		6254	schedule_work(&work->work);
2327	Serge	6255
3031	serge	6256	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
		6257	}
2327	Serge	6258
3031	serge	6259	void intel_finish_page_flip(struct drm_device *dev, int pipe)
		6260	{
		6261	drm_i915_private_t *dev_priv = dev->dev_private;
		6262	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2327	Serge	6263
3031	serge	6264	do_intel_finish_page_flip(dev, crtc);
		6265	}
2327	Serge	6266
3031	serge	6267	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
		6268	{
		6269	drm_i915_private_t *dev_priv = dev->dev_private;
		6270	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
2327	Serge	6271
3031	serge	6272	do_intel_finish_page_flip(dev, crtc);
		6273	}
2327	Serge	6274
3031	serge	6275	void intel_prepare_page_flip(struct drm_device *dev, int plane)
		6276	{
		6277	drm_i915_private_t *dev_priv = dev->dev_private;
		6278	struct intel_crtc *intel_crtc =
		6279	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
		6280	unsigned long flags;
2327	Serge	6281
3031	serge	6282	spin_lock_irqsave(&dev->event_lock, flags);
		6283	if (intel_crtc->unpin_work) {
		6284	if ((++intel_crtc->unpin_work->pending) > 1)
		6285	DRM_ERROR("Prepared flip multiple times\n");
		6286	} else {
		6287	DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
		6288	}
		6289	spin_unlock_irqrestore(&dev->event_lock, flags);
		6290	}
2327	Serge	6291
3031	serge	6292	static int intel_gen2_queue_flip(struct drm_device *dev,
		6293	struct drm_crtc *crtc,
		6294	struct drm_framebuffer *fb,
		6295	struct drm_i915_gem_object *obj)
		6296	{
		6297	struct drm_i915_private *dev_priv = dev->dev_private;
		6298	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6299	u32 flip_mask;
		6300	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6301	int ret;
2327	Serge	6302
3031	serge	6303	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6304	if (ret)
		6305	goto err;
2327	Serge	6306
3031	serge	6307	ret = intel_ring_begin(ring, 6);
		6308	if (ret)
		6309	goto err_unpin;
2327	Serge	6310
3031	serge	6311	/* Can't queue multiple flips, so wait for the previous
		6312	* one to finish before executing the next.
		6313	*/
		6314	if (intel_crtc->plane)
		6315	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		6316	else
		6317	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		6318	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		6319	intel_ring_emit(ring, MI_NOOP);
		6320	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6321	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6322	intel_ring_emit(ring, fb->pitches[0]);
		6323	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6324	intel_ring_emit(ring, 0); /* aux display base address, unused */
		6325	intel_ring_advance(ring);
		6326	return 0;
2327	Serge	6327
3031	serge	6328	err_unpin:
		6329	intel_unpin_fb_obj(obj);
		6330	err:
		6331	return ret;
		6332	}
2327	Serge	6333
3031	serge	6334	static int intel_gen3_queue_flip(struct drm_device *dev,
		6335	struct drm_crtc *crtc,
		6336	struct drm_framebuffer *fb,
		6337	struct drm_i915_gem_object *obj)
		6338	{
		6339	struct drm_i915_private *dev_priv = dev->dev_private;
		6340	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6341	u32 flip_mask;
		6342	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6343	int ret;
2327	Serge	6344
3031	serge	6345	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6346	if (ret)
		6347	goto err;
2327	Serge	6348
3031	serge	6349	ret = intel_ring_begin(ring, 6);
		6350	if (ret)
		6351	goto err_unpin;
2327	Serge	6352
3031	serge	6353	if (intel_crtc->plane)
		6354	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		6355	else
		6356	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		6357	intel_ring_emit(ring, MI_WAIT_FOR_EVENT \| flip_mask);
		6358	intel_ring_emit(ring, MI_NOOP);
		6359	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \|
		6360	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6361	intel_ring_emit(ring, fb->pitches[0]);
		6362	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6363	intel_ring_emit(ring, MI_NOOP);
2327	Serge	6364
3031	serge	6365	intel_ring_advance(ring);
		6366	return 0;
2327	Serge	6367
3031	serge	6368	err_unpin:
		6369	intel_unpin_fb_obj(obj);
		6370	err:
		6371	return ret;
		6372	}
2327	Serge	6373
3031	serge	6374	static int intel_gen4_queue_flip(struct drm_device *dev,
		6375	struct drm_crtc *crtc,
		6376	struct drm_framebuffer *fb,
		6377	struct drm_i915_gem_object *obj)
		6378	{
		6379	struct drm_i915_private *dev_priv = dev->dev_private;
		6380	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6381	uint32_t pf, pipesrc;
		6382	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6383	int ret;
2327	Serge	6384
3031	serge	6385	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6386	if (ret)
		6387	goto err;
2327	Serge	6388
3031	serge	6389	ret = intel_ring_begin(ring, 4);
		6390	if (ret)
		6391	goto err_unpin;
2327	Serge	6392
3031	serge	6393	/* i965+ uses the linear or tiled offsets from the
		6394	* Display Registers (which do not change across a page-flip)
		6395	* so we need only reprogram the base address.
		6396	*/
		6397	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6398	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6399	intel_ring_emit(ring, fb->pitches[0]);
		6400	intel_ring_emit(ring,
		6401	(obj->gtt_offset + intel_crtc->dspaddr_offset) \|
		6402	obj->tiling_mode);
2327	Serge	6403
3031	serge	6404	/* XXX Enabling the panel-fitter across page-flip is so far
		6405	* untested on non-native modes, so ignore it for now.
		6406	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		6407	*/
		6408	pf = 0;
		6409	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		6410	intel_ring_emit(ring, pf \| pipesrc);
		6411	intel_ring_advance(ring);
		6412	return 0;
2327	Serge	6413
3031	serge	6414	err_unpin:
		6415	intel_unpin_fb_obj(obj);
		6416	err:
		6417	return ret;
		6418	}
2327	Serge	6419
3031	serge	6420	static int intel_gen6_queue_flip(struct drm_device *dev,
		6421	struct drm_crtc *crtc,
		6422	struct drm_framebuffer *fb,
		6423	struct drm_i915_gem_object *obj)
		6424	{
		6425	struct drm_i915_private *dev_priv = dev->dev_private;
		6426	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6427	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
		6428	uint32_t pf, pipesrc;
		6429	int ret;
2327	Serge	6430
3031	serge	6431	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6432	if (ret)
		6433	goto err;
2327	Serge	6434
3031	serge	6435	ret = intel_ring_begin(ring, 4);
		6436	if (ret)
		6437	goto err_unpin;
2327	Serge	6438
3031	serge	6439	intel_ring_emit(ring, MI_DISPLAY_FLIP \|
		6440	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		6441	intel_ring_emit(ring, fb->pitches[0] \| obj->tiling_mode);
		6442	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
2327	Serge	6443
3031	serge	6444	/* Contrary to the suggestions in the documentation,
		6445	* "Enable Panel Fitter" does not seem to be required when page
		6446	* flipping with a non-native mode, and worse causes a normal
		6447	* modeset to fail.
		6448	* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
		6449	*/
		6450	pf = 0;
		6451	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
		6452	intel_ring_emit(ring, pf \| pipesrc);
		6453	intel_ring_advance(ring);
		6454	return 0;
2327	Serge	6455
3031	serge	6456	err_unpin:
		6457	intel_unpin_fb_obj(obj);
		6458	err:
		6459	return ret;
		6460	}
2327	Serge	6461
3031	serge	6462	/*
		6463	* On gen7 we currently use the blit ring because (in early silicon at least)
		6464	* the render ring doesn't give us interrpts for page flip completion, which
		6465	* means clients will hang after the first flip is queued. Fortunately the
		6466	* blit ring generates interrupts properly, so use it instead.
		6467	*/
		6468	static int intel_gen7_queue_flip(struct drm_device *dev,
		6469	struct drm_crtc *crtc,
		6470	struct drm_framebuffer *fb,
		6471	struct drm_i915_gem_object *obj)
		6472	{
		6473	struct drm_i915_private *dev_priv = dev->dev_private;
		6474	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6475	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
		6476	uint32_t plane_bit = 0;
		6477	int ret;
2327	Serge	6478
3031	serge	6479	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
		6480	if (ret)
		6481	goto err;
2327	Serge	6482
3031	serge	6483	switch(intel_crtc->plane) {
		6484	case PLANE_A:
		6485	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		6486	break;
		6487	case PLANE_B:
		6488	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		6489	break;
		6490	case PLANE_C:
		6491	plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		6492	break;
		6493	default:
		6494	WARN_ONCE(1, "unknown plane in flip command\n");
		6495	ret = -ENODEV;
		6496	goto err_unpin;
		6497	}
2327	Serge	6498
3031	serge	6499	ret = intel_ring_begin(ring, 4);
		6500	if (ret)
		6501	goto err_unpin;
2327	Serge	6502
3031	serge	6503	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 \| plane_bit);
		6504	intel_ring_emit(ring, (fb->pitches[0] \| obj->tiling_mode));
		6505	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
		6506	intel_ring_emit(ring, (MI_NOOP));
		6507	intel_ring_advance(ring);
		6508	return 0;
2327	Serge	6509
3031	serge	6510	err_unpin:
		6511	intel_unpin_fb_obj(obj);
		6512	err:
		6513	return ret;
		6514	}
2327	Serge	6515
3031	serge	6516	static int intel_default_queue_flip(struct drm_device *dev,
		6517	struct drm_crtc *crtc,
		6518	struct drm_framebuffer *fb,
		6519	struct drm_i915_gem_object *obj)
		6520	{
		6521	return -ENODEV;
		6522	}
2327	Serge	6523
3031	serge	6524	static int intel_crtc_page_flip(struct drm_crtc *crtc,
		6525	struct drm_framebuffer *fb,
		6526	struct drm_pending_vblank_event *event)
		6527	{
		6528	struct drm_device *dev = crtc->dev;
		6529	struct drm_i915_private *dev_priv = dev->dev_private;
		6530	struct intel_framebuffer *intel_fb;
		6531	struct drm_i915_gem_object *obj;
		6532	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6533	struct intel_unpin_work *work;
		6534	unsigned long flags;
		6535	int ret;
2327	Serge	6536
3031	serge	6537	/* Can't change pixel format via MI display flips. */
		6538	if (fb->pixel_format != crtc->fb->pixel_format)
		6539	return -EINVAL;
2327	Serge	6540
3031	serge	6541	/*
		6542	* TILEOFF/LINOFF registers can't be changed via MI display flips.
		6543	* Note that pitch changes could also affect these register.
		6544	*/
		6545	if (INTEL_INFO(dev)->gen > 3 &&
		6546	(fb->offsets[0] != crtc->fb->offsets[0] \|\|
		6547	fb->pitches[0] != crtc->fb->pitches[0]))
		6548	return -EINVAL;
2327	Serge	6549
3031	serge	6550	work = kzalloc(sizeof *work, GFP_KERNEL);
		6551	if (work == NULL)
		6552	return -ENOMEM;
2327	Serge	6553
3031	serge	6554	work->event = event;
		6555	work->dev = crtc->dev;
		6556	intel_fb = to_intel_framebuffer(crtc->fb);
		6557	work->old_fb_obj = intel_fb->obj;
		6558	INIT_WORK(&work->work, intel_unpin_work_fn);
2327	Serge	6559
3031	serge	6560	ret = drm_vblank_get(dev, intel_crtc->pipe);
		6561	if (ret)
		6562	goto free_work;
2327	Serge	6563
3031	serge	6564	/* We borrow the event spin lock for protecting unpin_work */
		6565	spin_lock_irqsave(&dev->event_lock, flags);
		6566	if (intel_crtc->unpin_work) {
		6567	spin_unlock_irqrestore(&dev->event_lock, flags);
		6568	kfree(work);
		6569	drm_vblank_put(dev, intel_crtc->pipe);
2327	Serge	6570
3031	serge	6571	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		6572	return -EBUSY;
		6573	}
		6574	intel_crtc->unpin_work = work;
		6575	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6576
3031	serge	6577	intel_fb = to_intel_framebuffer(fb);
		6578	obj = intel_fb->obj;
2327	Serge	6579
3031	serge	6580	ret = i915_mutex_lock_interruptible(dev);
		6581	if (ret)
		6582	goto cleanup;
2327	Serge	6583
3031	serge	6584	/* Reference the objects for the scheduled work. */
		6585	drm_gem_object_reference(&work->old_fb_obj->base);
		6586	drm_gem_object_reference(&obj->base);
2327	Serge	6587
3031	serge	6588	crtc->fb = fb;
2327	Serge	6589
3031	serge	6590	work->pending_flip_obj = obj;
2327	Serge	6591
3031	serge	6592	work->enable_stall_check = true;
		6593
		6594	/* Block clients from rendering to the new back buffer until
		6595	* the flip occurs and the object is no longer visible.
		6596	*/
		6597	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
		6598
		6599	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
		6600	if (ret)
		6601	goto cleanup_pending;
		6602
		6603	intel_disable_fbc(dev);
		6604	intel_mark_fb_busy(obj);
		6605	mutex_unlock(&dev->struct_mutex);
		6606
		6607	trace_i915_flip_request(intel_crtc->plane, obj);
		6608
		6609	return 0;
		6610
		6611	cleanup_pending:
		6612	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
		6613	drm_gem_object_unreference(&work->old_fb_obj->base);
		6614	drm_gem_object_unreference(&obj->base);
		6615	mutex_unlock(&dev->struct_mutex);
		6616
		6617	cleanup:
		6618	spin_lock_irqsave(&dev->event_lock, flags);
		6619	intel_crtc->unpin_work = NULL;
		6620	spin_unlock_irqrestore(&dev->event_lock, flags);
		6621
		6622	drm_vblank_put(dev, intel_crtc->pipe);
		6623	free_work:
		6624	kfree(work);
		6625
		6626	return ret;
		6627	}
		6628
		6629	#endif
		6630
		6631	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		6632	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		6633	.load_lut = intel_crtc_load_lut,
		6634	.disable = intel_crtc_noop,
		6635	};
		6636
		6637	bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
2330	Serge	6638	{
3031	serge	6639	struct intel_encoder *other_encoder;
		6640	struct drm_crtc *crtc = &encoder->new_crtc->base;
2327	Serge	6641
3031	serge	6642	if (WARN_ON(!crtc))
		6643	return false;
2327	Serge	6644
3031	serge	6645	list_for_each_entry(other_encoder,
		6646	&crtc->dev->mode_config.encoder_list,
		6647	base.head) {
		6648
		6649	if (&other_encoder->new_crtc->base != crtc \|\|
		6650	encoder == other_encoder)
		6651	continue;
		6652	else
		6653	return true;
		6654	}
		6655
		6656	return false;
		6657	}
		6658
		6659	static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
		6660	struct drm_crtc *crtc)
		6661	{
		6662	struct drm_device *dev;
		6663	struct drm_crtc *tmp;
		6664	int crtc_mask = 1;
		6665
		6666	WARN(!crtc, "checking null crtc?\n");
		6667
		6668	dev = crtc->dev;
		6669
		6670	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		6671	if (tmp == crtc)
		6672	break;
		6673	crtc_mask <<= 1;
		6674	}
		6675
		6676	if (encoder->possible_crtcs & crtc_mask)
		6677	return true;
		6678	return false;
		6679	}
		6680
		6681	/**
		6682	* intel_modeset_update_staged_output_state
		6683	*
		6684	* Updates the staged output configuration state, e.g. after we've read out the
		6685	* current hw state.
		6686	*/
		6687	static void intel_modeset_update_staged_output_state(struct drm_device *dev)
		6688	{
		6689	struct intel_encoder *encoder;
		6690	struct intel_connector *connector;
		6691
		6692	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6693	base.head) {
		6694	connector->new_encoder =
		6695	to_intel_encoder(connector->base.encoder);
		6696	}
		6697
		6698	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6699	base.head) {
		6700	encoder->new_crtc =
		6701	to_intel_crtc(encoder->base.crtc);
		6702	}
		6703	}
		6704
		6705	/**
		6706	* intel_modeset_commit_output_state
		6707	*
		6708	* This function copies the stage display pipe configuration to the real one.
		6709	*/
		6710	static void intel_modeset_commit_output_state(struct drm_device *dev)
		6711	{
		6712	struct intel_encoder *encoder;
		6713	struct intel_connector *connector;
		6714
		6715	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6716	base.head) {
		6717	connector->base.encoder = &connector->new_encoder->base;
		6718	}
		6719
		6720	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6721	base.head) {
		6722	encoder->base.crtc = &encoder->new_crtc->base;
		6723	}
		6724	}
		6725
		6726	static struct drm_display_mode *
		6727	intel_modeset_adjusted_mode(struct drm_crtc *crtc,
		6728	struct drm_display_mode *mode)
		6729	{
		6730	struct drm_device *dev = crtc->dev;
		6731	struct drm_display_mode *adjusted_mode;
		6732	struct drm_encoder_helper_funcs *encoder_funcs;
		6733	struct intel_encoder *encoder;
		6734
		6735	adjusted_mode = drm_mode_duplicate(dev, mode);
		6736	if (!adjusted_mode)
		6737	return ERR_PTR(-ENOMEM);
		6738
		6739	/* Pass our mode to the connectors and the CRTC to give them a chance to
		6740	* adjust it according to limitations or connector properties, and also
		6741	* a chance to reject the mode entirely.
2330	Serge	6742	*/
3031	serge	6743	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6744	base.head) {
2327	Serge	6745
3031	serge	6746	if (&encoder->new_crtc->base != crtc)
		6747	continue;
		6748	encoder_funcs = encoder->base.helper_private;
		6749	if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
		6750	adjusted_mode))) {
		6751	DRM_DEBUG_KMS("Encoder fixup failed\n");
		6752	goto fail;
		6753	}
		6754	}
2327	Serge	6755
3031	serge	6756	if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
		6757	DRM_DEBUG_KMS("CRTC fixup failed\n");
		6758	goto fail;
		6759	}
		6760	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
2327	Serge	6761
3031	serge	6762	return adjusted_mode;
		6763	fail:
		6764	drm_mode_destroy(dev, adjusted_mode);
		6765	return ERR_PTR(-EINVAL);
		6766	}
2327	Serge	6767
3031	serge	6768	/* Computes which crtcs are affected and sets the relevant bits in the mask. For
		6769	* simplicity we use the crtc's pipe number (because it's easier to obtain). */
		6770	static void
		6771	intel_modeset_affected_pipes(struct drm_crtc crtc, unsigned modeset_pipes,
		6772	unsigned prepare_pipes, unsigned disable_pipes)
		6773	{
		6774	struct intel_crtc *intel_crtc;
		6775	struct drm_device *dev = crtc->dev;
		6776	struct intel_encoder *encoder;
		6777	struct intel_connector *connector;
		6778	struct drm_crtc *tmp_crtc;
		6779
		6780	disable_pipes = modeset_pipes = *prepare_pipes = 0;
		6781
		6782	/* Check which crtcs have changed outputs connected to them, these need
		6783	* to be part of the prepare_pipes mask. We don't (yet) support global
		6784	* modeset across multiple crtcs, so modeset_pipes will only have one
		6785	* bit set at most. */
		6786	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6787	base.head) {
		6788	if (connector->base.encoder == &connector->new_encoder->base)
		6789	continue;
		6790
		6791	if (connector->base.encoder) {
		6792	tmp_crtc = connector->base.encoder->crtc;
		6793
		6794	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		6795	}
		6796
		6797	if (connector->new_encoder)
		6798	*prepare_pipes \|=
		6799	1 << connector->new_encoder->new_crtc->pipe;
		6800	}
		6801
		6802	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6803	base.head) {
		6804	if (encoder->base.crtc == &encoder->new_crtc->base)
		6805	continue;
		6806
		6807	if (encoder->base.crtc) {
		6808	tmp_crtc = encoder->base.crtc;
		6809
		6810	*prepare_pipes \|= 1 << to_intel_crtc(tmp_crtc)->pipe;
		6811	}
		6812
		6813	if (encoder->new_crtc)
		6814	*prepare_pipes \|= 1 << encoder->new_crtc->pipe;
		6815	}
		6816
		6817	/* Check for any pipes that will be fully disabled ... */
		6818	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		6819	base.head) {
		6820	bool used = false;
		6821
		6822	/* Don't try to disable disabled crtcs. */
		6823	if (!intel_crtc->base.enabled)
		6824	continue;
		6825
		6826	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6827	base.head) {
		6828	if (encoder->new_crtc == intel_crtc)
		6829	used = true;
		6830	}
		6831
		6832	if (!used)
		6833	*disable_pipes \|= 1 << intel_crtc->pipe;
		6834	}
		6835
		6836
		6837	/* set_mode is also used to update properties on life display pipes. */
		6838	intel_crtc = to_intel_crtc(crtc);
		6839	if (crtc->enabled)
		6840	*prepare_pipes \|= 1 << intel_crtc->pipe;
		6841
		6842	/* We only support modeset on one single crtc, hence we need to do that
		6843	* only for the passed in crtc iff we change anything else than just
		6844	* disable crtcs.
		6845	*
		6846	* This is actually not true, to be fully compatible with the old crtc
		6847	* helper we automatically disable _any_ output (i.e. doesn't need to be
		6848	* connected to the crtc we're modesetting on) if it's disconnected.
		6849	* Which is a rather nutty api (since changed the output configuration
		6850	* without userspace's explicit request can lead to confusion), but
		6851	* alas. Hence we currently need to modeset on all pipes we prepare. */
		6852	if (*prepare_pipes)
		6853	modeset_pipes = prepare_pipes;
		6854
		6855	/* ... and mask these out. */
		6856	modeset_pipes &= ~(disable_pipes);
		6857	prepare_pipes &= ~(disable_pipes);
2330	Serge	6858	}
2327	Serge	6859
3031	serge	6860	static bool intel_crtc_in_use(struct drm_crtc *crtc)
2330	Serge	6861	{
3031	serge	6862	struct drm_encoder *encoder;
2330	Serge	6863	struct drm_device *dev = crtc->dev;
2327	Serge	6864
3031	serge	6865	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		6866	if (encoder->crtc == crtc)
		6867	return true;
		6868
		6869	return false;
		6870	}
		6871
		6872	static void
		6873	intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
		6874	{
		6875	struct intel_encoder *intel_encoder;
		6876	struct intel_crtc *intel_crtc;
		6877	struct drm_connector *connector;
		6878
		6879	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
		6880	base.head) {
		6881	if (!intel_encoder->base.crtc)
		6882	continue;
		6883
		6884	intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
		6885
		6886	if (prepare_pipes & (1 << intel_crtc->pipe))
		6887	intel_encoder->connectors_active = false;
		6888	}
		6889
		6890	intel_modeset_commit_output_state(dev);
		6891
		6892	/* Update computed state. */
		6893	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
		6894	base.head) {
		6895	intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
		6896	}
		6897
		6898	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		6899	if (!connector->encoder \|\| !connector->encoder->crtc)
		6900	continue;
		6901
		6902	intel_crtc = to_intel_crtc(connector->encoder->crtc);
		6903
		6904	if (prepare_pipes & (1 << intel_crtc->pipe)) {
		6905	struct drm_property *dpms_property =
		6906	dev->mode_config.dpms_property;
		6907
		6908	connector->dpms = DRM_MODE_DPMS_ON;
		6909	drm_connector_property_set_value(connector,
		6910	dpms_property,
		6911	DRM_MODE_DPMS_ON);
		6912
		6913	intel_encoder = to_intel_encoder(connector->encoder);
		6914	intel_encoder->connectors_active = true;
		6915	}
		6916	}
		6917
		6918	}
		6919
		6920	#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
		6921	list_for_each_entry((intel_crtc), \
		6922	&(dev)->mode_config.crtc_list, \
		6923	base.head) \
		6924	if (mask & (1 <<(intel_crtc)->pipe)) \
		6925
		6926	void
		6927	intel_modeset_check_state(struct drm_device *dev)
		6928	{
		6929	struct intel_crtc *crtc;
		6930	struct intel_encoder *encoder;
		6931	struct intel_connector *connector;
		6932
		6933	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6934	base.head) {
		6935	/* This also checks the encoder/connector hw state with the
		6936	* ->get_hw_state callbacks. */
		6937	intel_connector_check_state(connector);
		6938
		6939	WARN(&connector->new_encoder->base != connector->base.encoder,
		6940	"connector's staged encoder doesn't match current encoder\n");
		6941	}
		6942
		6943	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		6944	base.head) {
		6945	bool enabled = false;
		6946	bool active = false;
		6947	enum pipe pipe, tracked_pipe;
		6948
		6949	DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
		6950	encoder->base.base.id,
		6951	drm_get_encoder_name(&encoder->base));
		6952
		6953	WARN(&encoder->new_crtc->base != encoder->base.crtc,
		6954	"encoder's stage crtc doesn't match current crtc\n");
		6955	WARN(encoder->connectors_active && !encoder->base.crtc,
		6956	"encoder's active_connectors set, but no crtc\n");
		6957
		6958	list_for_each_entry(connector, &dev->mode_config.connector_list,
		6959	base.head) {
		6960	if (connector->base.encoder != &encoder->base)
		6961	continue;
		6962	enabled = true;
		6963	if (connector->base.dpms != DRM_MODE_DPMS_OFF)
		6964	active = true;
		6965	}
		6966	WARN(!!encoder->base.crtc != enabled,
		6967	"encoder's enabled state mismatch "
		6968	"(expected %i, found %i)\n",
		6969	!!encoder->base.crtc, enabled);
		6970	WARN(active && !encoder->base.crtc,
		6971	"active encoder with no crtc\n");
		6972
		6973	WARN(encoder->connectors_active != active,
		6974	"encoder's computed active state doesn't match tracked active state "
		6975	"(expected %i, found %i)\n", active, encoder->connectors_active);
		6976
		6977	active = encoder->get_hw_state(encoder, &pipe);
		6978	WARN(active != encoder->connectors_active,
		6979	"encoder's hw state doesn't match sw tracking "
		6980	"(expected %i, found %i)\n",
		6981	encoder->connectors_active, active);
		6982
		6983	if (!encoder->base.crtc)
		6984	continue;
		6985
		6986	tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		6987	WARN(active && pipe != tracked_pipe,
		6988	"active encoder's pipe doesn't match"
		6989	"(expected %i, found %i)\n",
		6990	tracked_pipe, pipe);
		6991
		6992	}
		6993
		6994	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
		6995	base.head) {
		6996	bool enabled = false;
		6997	bool active = false;
		6998
		6999	DRM_DEBUG_KMS("[CRTC:%d]\n",
		7000	crtc->base.base.id);
		7001
		7002	WARN(crtc->active && !crtc->base.enabled,
		7003	"active crtc, but not enabled in sw tracking\n");
		7004
		7005	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7006	base.head) {
		7007	if (encoder->base.crtc != &crtc->base)
		7008	continue;
		7009	enabled = true;
		7010	if (encoder->connectors_active)
		7011	active = true;
		7012	}
		7013	WARN(active != crtc->active,
		7014	"crtc's computed active state doesn't match tracked active state "
		7015	"(expected %i, found %i)\n", active, crtc->active);
		7016	WARN(enabled != crtc->base.enabled,
		7017	"crtc's computed enabled state doesn't match tracked enabled state "
		7018	"(expected %i, found %i)\n", enabled, crtc->base.enabled);
		7019
		7020	assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
		7021	}
		7022	}
		7023
		7024	bool intel_set_mode(struct drm_crtc *crtc,
		7025	struct drm_display_mode *mode,
		7026	int x, int y, struct drm_framebuffer *fb)
		7027	{
		7028	struct drm_device *dev = crtc->dev;
		7029	drm_i915_private_t *dev_priv = dev->dev_private;
		7030	struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
		7031	struct drm_encoder_helper_funcs *encoder_funcs;
		7032	struct drm_encoder *encoder;
		7033	struct intel_crtc *intel_crtc;
		7034	unsigned disable_pipes, prepare_pipes, modeset_pipes;
		7035	bool ret = true;
		7036
		7037	intel_modeset_affected_pipes(crtc, &modeset_pipes,
		7038	&prepare_pipes, &disable_pipes);
		7039
		7040	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		7041	modeset_pipes, prepare_pipes, disable_pipes);
		7042
		7043	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		7044	intel_crtc_disable(&intel_crtc->base);
		7045
		7046	saved_hwmode = crtc->hwmode;
		7047	saved_mode = crtc->mode;
		7048
		7049	/* Hack: Because we don't (yet) support global modeset on multiple
		7050	* crtcs, we don't keep track of the new mode for more than one crtc.
		7051	* Hence simply check whether any bit is set in modeset_pipes in all the
		7052	* pieces of code that are not yet converted to deal with mutliple crtcs
		7053	* changing their mode at the same time. */
		7054	adjusted_mode = NULL;
		7055	if (modeset_pipes) {
		7056	adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
		7057	if (IS_ERR(adjusted_mode)) {
		7058	return false;
		7059	}
		7060	}
		7061
		7062	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		7063	if (intel_crtc->base.enabled)
		7064	dev_priv->display.crtc_disable(&intel_crtc->base);
		7065	}
		7066
		7067	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
		7068	* to set it here already despite that we pass it down the callchain.
2330	Serge	7069	*/
3031	serge	7070	if (modeset_pipes)
		7071	crtc->mode = *mode;
2327	Serge	7072
3031	serge	7073	/* Only after disabling all output pipelines that will be changed can we
		7074	* update the the output configuration. */
		7075	intel_modeset_update_state(dev, prepare_pipes);
		7076
		7077	/* Set up the DPLL and any encoders state that needs to adjust or depend
		7078	* on the DPLL.
2330	Serge	7079	*/
3031	serge	7080	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
		7081	ret = !intel_crtc_mode_set(&intel_crtc->base,
		7082	mode, adjusted_mode,
		7083	x, y, fb);
		7084	if (!ret)
		7085	goto done;
		7086
		7087	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		7088
		7089	if (encoder->crtc != &intel_crtc->base)
		7090	continue;
		7091
		7092	DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
		7093	encoder->base.id, drm_get_encoder_name(encoder),
		7094	mode->base.id, mode->name);
		7095	encoder_funcs = encoder->helper_private;
		7096	encoder_funcs->mode_set(encoder, mode, adjusted_mode);
		7097	}
		7098	}
		7099
		7100	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
		7101	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		7102	dev_priv->display.crtc_enable(&intel_crtc->base);
		7103
		7104	if (modeset_pipes) {
		7105	/* Store real post-adjustment hardware mode. */
		7106	crtc->hwmode = *adjusted_mode;
		7107
		7108	/* Calculate and store various constants which
		7109	* are later needed by vblank and swap-completion
		7110	* timestamping. They are derived from true hwmode.
		7111	*/
		7112	drm_calc_timestamping_constants(crtc);
		7113	}
		7114
		7115	/* FIXME: add subpixel order */
		7116	done:
		7117	drm_mode_destroy(dev, adjusted_mode);
		7118	if (!ret && crtc->enabled) {
		7119	crtc->hwmode = saved_hwmode;
		7120	crtc->mode = saved_mode;
		7121	} else {
		7122	intel_modeset_check_state(dev);
		7123	}
		7124
		7125	return ret;
2330	Serge	7126	}
2327	Serge	7127
3031	serge	7128	#undef for_each_intel_crtc_masked
2327	Serge	7129
3031	serge	7130	static void intel_set_config_free(struct intel_set_config *config)
		7131	{
		7132	if (!config)
		7133	return;
		7134
		7135	kfree(config->save_connector_encoders);
		7136	kfree(config->save_encoder_crtcs);
		7137	kfree(config);
		7138	}
		7139
		7140	static int intel_set_config_save_state(struct drm_device *dev,
		7141	struct intel_set_config *config)
		7142	{
		7143	struct drm_encoder *encoder;
		7144	struct drm_connector *connector;
		7145	int count;
		7146
		7147	config->save_encoder_crtcs =
		7148	kcalloc(dev->mode_config.num_encoder,
		7149	sizeof(struct drm_crtc *), GFP_KERNEL);
		7150	if (!config->save_encoder_crtcs)
		7151	return -ENOMEM;
		7152
		7153	config->save_connector_encoders =
		7154	kcalloc(dev->mode_config.num_connector,
		7155	sizeof(struct drm_encoder *), GFP_KERNEL);
		7156	if (!config->save_connector_encoders)
		7157	return -ENOMEM;
		7158
		7159	/* Copy data. Note that driver private data is not affected.
		7160	* Should anything bad happen only the expected state is
		7161	* restored, not the drivers personal bookkeeping.
		7162	*/
		7163	count = 0;
		7164	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		7165	config->save_encoder_crtcs[count++] = encoder->crtc;
		7166	}
		7167
		7168	count = 0;
		7169	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		7170	config->save_connector_encoders[count++] = connector->encoder;
		7171	}
		7172
		7173	return 0;
		7174	}
		7175
		7176	static void intel_set_config_restore_state(struct drm_device *dev,
		7177	struct intel_set_config *config)
		7178	{
		7179	struct intel_encoder *encoder;
		7180	struct intel_connector *connector;
		7181	int count;
		7182
		7183	count = 0;
		7184	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		7185	encoder->new_crtc =
		7186	to_intel_crtc(config->save_encoder_crtcs[count++]);
		7187	}
		7188
		7189	count = 0;
		7190	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		7191	connector->new_encoder =
		7192	to_intel_encoder(config->save_connector_encoders[count++]);
		7193	}
		7194	}
		7195
		7196	static void
		7197	intel_set_config_compute_mode_changes(struct drm_mode_set *set,
		7198	struct intel_set_config *config)
		7199	{
		7200
		7201	/* We should be able to check here if the fb has the same properties
		7202	* and then just flip_or_move it */
		7203	if (set->crtc->fb != set->fb) {
		7204	/* If we have no fb then treat it as a full mode set */
		7205	if (set->crtc->fb == NULL) {
		7206	DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
		7207	config->mode_changed = true;
		7208	} else if (set->fb == NULL) {
		7209	config->mode_changed = true;
		7210	} else if (set->fb->depth != set->crtc->fb->depth) {
		7211	config->mode_changed = true;
		7212	} else if (set->fb->bits_per_pixel !=
		7213	set->crtc->fb->bits_per_pixel) {
		7214	config->mode_changed = true;
		7215	} else
		7216	config->fb_changed = true;
		7217	}
		7218
		7219	if (set->fb && (set->x != set->crtc->x \|\| set->y != set->crtc->y))
		7220	config->fb_changed = true;
		7221
		7222	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		7223	DRM_DEBUG_KMS("modes are different, full mode set\n");
		7224	drm_mode_debug_printmodeline(&set->crtc->mode);
		7225	drm_mode_debug_printmodeline(set->mode);
		7226	config->mode_changed = true;
		7227	}
		7228	}
		7229
		7230	static int
		7231	intel_modeset_stage_output_state(struct drm_device *dev,
		7232	struct drm_mode_set *set,
		7233	struct intel_set_config *config)
		7234	{
		7235	struct drm_crtc *new_crtc;
		7236	struct intel_connector *connector;
		7237	struct intel_encoder *encoder;
		7238	int count, ro;
		7239
		7240	/* The upper layers ensure that we either disabl a crtc or have a list
		7241	* of connectors. For paranoia, double-check this. */
		7242	WARN_ON(!set->fb && (set->num_connectors != 0));
		7243	WARN_ON(set->fb && (set->num_connectors == 0));
		7244
		7245	count = 0;
		7246	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7247	base.head) {
		7248	/* Otherwise traverse passed in connector list and get encoders
		7249	* for them. */
		7250	for (ro = 0; ro < set->num_connectors; ro++) {
		7251	if (set->connectors[ro] == &connector->base) {
		7252	connector->new_encoder = connector->encoder;
		7253	break;
		7254	}
		7255	}
		7256
		7257	/* If we disable the crtc, disable all its connectors. Also, if
		7258	* the connector is on the changing crtc but not on the new
		7259	* connector list, disable it. */
		7260	if ((!set->fb \|\| ro == set->num_connectors) &&
		7261	connector->base.encoder &&
		7262	connector->base.encoder->crtc == set->crtc) {
		7263	connector->new_encoder = NULL;
		7264
		7265	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
		7266	connector->base.base.id,
		7267	drm_get_connector_name(&connector->base));
		7268	}
		7269
		7270
		7271	if (&connector->new_encoder->base != connector->base.encoder) {
		7272	DRM_DEBUG_KMS("encoder changed, full mode switch\n");
		7273	config->mode_changed = true;
		7274	}
		7275
		7276	/* Disable all disconnected encoders. */
		7277	if (connector->base.status == connector_status_disconnected)
		7278	connector->new_encoder = NULL;
		7279	}
		7280	/* connector->new_encoder is now updated for all connectors. */
		7281
		7282	/* Update crtc of enabled connectors. */
		7283	count = 0;
		7284	list_for_each_entry(connector, &dev->mode_config.connector_list,
		7285	base.head) {
		7286	if (!connector->new_encoder)
		7287	continue;
		7288
		7289	new_crtc = connector->new_encoder->base.crtc;
		7290
		7291	for (ro = 0; ro < set->num_connectors; ro++) {
		7292	if (set->connectors[ro] == &connector->base)
		7293	new_crtc = set->crtc;
		7294	}
		7295
		7296	/* Make sure the new CRTC will work with the encoder */
		7297	if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
		7298	new_crtc)) {
		7299	return -EINVAL;
		7300	}
		7301	connector->encoder->new_crtc = to_intel_crtc(new_crtc);
		7302
		7303	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
		7304	connector->base.base.id,
		7305	drm_get_connector_name(&connector->base),
		7306	new_crtc->base.id);
		7307	}
		7308
		7309	/* Check for any encoders that needs to be disabled. */
		7310	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		7311	base.head) {
		7312	list_for_each_entry(connector,
		7313	&dev->mode_config.connector_list,
		7314	base.head) {
		7315	if (connector->new_encoder == encoder) {
		7316	WARN_ON(!connector->new_encoder->new_crtc);
		7317
		7318	goto next_encoder;
		7319	}
		7320	}
		7321	encoder->new_crtc = NULL;
		7322	next_encoder:
		7323	/* Only now check for crtc changes so we don't miss encoders
		7324	* that will be disabled. */
		7325	if (&encoder->new_crtc->base != encoder->base.crtc) {
		7326	DRM_DEBUG_KMS("crtc changed, full mode switch\n");
		7327	config->mode_changed = true;
		7328	}
		7329	}
		7330	/* Now we've also updated encoder->new_crtc for all encoders. */
		7331
		7332	return 0;
		7333	}
		7334
		7335	static int intel_crtc_set_config(struct drm_mode_set *set)
		7336	{
		7337	struct drm_device *dev;
		7338	struct drm_mode_set save_set;
		7339	struct intel_set_config *config;
		7340	int ret;
		7341
		7342	BUG_ON(!set);
		7343	BUG_ON(!set->crtc);
		7344	BUG_ON(!set->crtc->helper_private);
		7345
		7346	if (!set->mode)
		7347	set->fb = NULL;
		7348
		7349	/* The fb helper likes to play gross jokes with ->mode_set_config.
		7350	* Unfortunately the crtc helper doesn't do much at all for this case,
		7351	* so we have to cope with this madness until the fb helper is fixed up. */
		7352	if (set->fb && set->num_connectors == 0)
		7353	return 0;
		7354
		7355	if (set->fb) {
		7356	DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
		7357	set->crtc->base.id, set->fb->base.id,
		7358	(int)set->num_connectors, set->x, set->y);
		7359	} else {
		7360	DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
		7361	}
		7362
		7363	dev = set->crtc->dev;
		7364
		7365	ret = -ENOMEM;
		7366	config = kzalloc(sizeof(*config), GFP_KERNEL);
		7367	if (!config)
		7368	goto out_config;
		7369
		7370	ret = intel_set_config_save_state(dev, config);
		7371	if (ret)
		7372	goto out_config;
		7373
		7374	save_set.crtc = set->crtc;
		7375	save_set.mode = &set->crtc->mode;
		7376	save_set.x = set->crtc->x;
		7377	save_set.y = set->crtc->y;
		7378	save_set.fb = set->crtc->fb;
		7379
		7380	/* Compute whether we need a full modeset, only an fb base update or no
		7381	* change at all. In the future we might also check whether only the
		7382	* mode changed, e.g. for LVDS where we only change the panel fitter in
		7383	* such cases. */
		7384	intel_set_config_compute_mode_changes(set, config);
		7385
		7386	ret = intel_modeset_stage_output_state(dev, set, config);
		7387	if (ret)
		7388	goto fail;
		7389
		7390	if (config->mode_changed) {
		7391	if (set->mode) {
		7392	DRM_DEBUG_KMS("attempting to set mode from"
		7393	" userspace\n");
		7394	drm_mode_debug_printmodeline(set->mode);
		7395	}
		7396
		7397	if (!intel_set_mode(set->crtc, set->mode,
		7398	set->x, set->y, set->fb)) {
		7399	DRM_ERROR("failed to set mode on [CRTC:%d]\n",
		7400	set->crtc->base.id);
		7401	ret = -EINVAL;
		7402	goto fail;
		7403	}
		7404	} else if (config->fb_changed) {
		7405	ret = intel_pipe_set_base(set->crtc,
		7406	set->x, set->y, set->fb);
		7407	}
		7408
		7409	intel_set_config_free(config);
		7410
		7411	return 0;
		7412
		7413	fail:
		7414	intel_set_config_restore_state(dev, config);
		7415
		7416	/* Try to restore the config */
		7417	if (config->mode_changed &&
		7418	!intel_set_mode(save_set.crtc, save_set.mode,
		7419	save_set.x, save_set.y, save_set.fb))
		7420	DRM_ERROR("failed to restore config after modeset failure\n");
		7421
		7422	out_config:
		7423	intel_set_config_free(config);
		7424	return ret;
		7425	}
		7426
2330	Serge	7427	static const struct drm_crtc_funcs intel_crtc_funcs = {
		7428	// .cursor_set = intel_crtc_cursor_set,
		7429	// .cursor_move = intel_crtc_cursor_move,
		7430	.gamma_set = intel_crtc_gamma_set,
3031	serge	7431	.set_config = intel_crtc_set_config,
2330	Serge	7432	.destroy = intel_crtc_destroy,
		7433	// .page_flip = intel_crtc_page_flip,
		7434	};
2327	Serge	7435
3031	serge	7436	static void intel_pch_pll_init(struct drm_device *dev)
		7437	{
		7438	drm_i915_private_t *dev_priv = dev->dev_private;
		7439	int i;
		7440
		7441	if (dev_priv->num_pch_pll == 0) {
		7442	DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		7443	return;
		7444	}
		7445
		7446	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		7447	dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		7448	dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		7449	dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
		7450	}
		7451	}
		7452
2330	Serge	7453	static void intel_crtc_init(struct drm_device *dev, int pipe)
		7454	{
		7455	drm_i915_private_t *dev_priv = dev->dev_private;
		7456	struct intel_crtc *intel_crtc;
		7457	int i;
2327	Serge	7458
2330	Serge	7459	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		7460	if (intel_crtc == NULL)
		7461	return;
2327	Serge	7462
2330	Serge	7463	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	7464
2330	Serge	7465	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		7466	for (i = 0; i < 256; i++) {
		7467	intel_crtc->lut_r[i] = i;
		7468	intel_crtc->lut_g[i] = i;
		7469	intel_crtc->lut_b[i] = i;
		7470	}
2327	Serge	7471
2330	Serge	7472	/* Swap pipes & planes for FBC on pre-965 */
		7473	intel_crtc->pipe = pipe;
		7474	intel_crtc->plane = pipe;
		7475	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		7476	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		7477	intel_crtc->plane = !pipe;
		7478	}
2327	Serge	7479
2330	Serge	7480	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		7481	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		7482	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		7483	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	7484
2330	Serge	7485	intel_crtc->bpp = 24; /* default for pre-Ironlake */
2327	Serge	7486
2330	Serge	7487	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2327	Serge	7488
3031	serge	7489	dbgprintf("CRTC %d mode %x FB %x enable %d\n",
		7490	intel_crtc->base.base.id, intel_crtc->base.mode,
		7491	intel_crtc->base.fb, intel_crtc->base.enabled);
2327	Serge	7492
2330	Serge	7493	}
2327	Serge	7494
3031	serge	7495	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
		7496	struct drm_file *file)
		7497	{
		7498	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
		7499	struct drm_mode_object *drmmode_obj;
		7500	struct intel_crtc *crtc;
2327	Serge	7501
3031	serge	7502	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
		7503	DRM_MODE_OBJECT_CRTC);
2327	Serge	7504
3031	serge	7505	if (!drmmode_obj) {
		7506	DRM_ERROR("no such CRTC id\n");
		7507	return -EINVAL;
		7508	}
2327	Serge	7509
3031	serge	7510	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
		7511	pipe_from_crtc_id->pipe = crtc->pipe;
2327	Serge	7512
3031	serge	7513	return 0;
		7514	}
2327	Serge	7515
3031	serge	7516	static int intel_encoder_clones(struct intel_encoder *encoder)
2330	Serge	7517	{
3031	serge	7518	struct drm_device *dev = encoder->base.dev;
		7519	struct intel_encoder *source_encoder;
2330	Serge	7520	int index_mask = 0;
		7521	int entry = 0;
2327	Serge	7522
3031	serge	7523	list_for_each_entry(source_encoder,
		7524	&dev->mode_config.encoder_list, base.head) {
		7525
		7526	if (encoder == source_encoder)
2330	Serge	7527	index_mask \|= (1 << entry);
3031	serge	7528
		7529	/* Intel hw has only one MUX where enocoders could be cloned. */
		7530	if (encoder->cloneable && source_encoder->cloneable)
		7531	index_mask \|= (1 << entry);
		7532
2330	Serge	7533	entry++;
		7534	}
2327	Serge	7535
2330	Serge	7536	return index_mask;
		7537	}
2327	Serge	7538
2330	Serge	7539	static bool has_edp_a(struct drm_device *dev)
		7540	{
		7541	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7542
2330	Serge	7543	if (!IS_MOBILE(dev))
		7544	return false;
2327	Serge	7545
2330	Serge	7546	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		7547	return false;
2327	Serge	7548
2330	Serge	7549	if (IS_GEN5(dev) &&
		7550	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		7551	return false;
2327	Serge	7552
2330	Serge	7553	return true;
		7554	}
2327	Serge	7555
2330	Serge	7556	static void intel_setup_outputs(struct drm_device *dev)
		7557	{
		7558	struct drm_i915_private *dev_priv = dev->dev_private;
		7559	struct intel_encoder *encoder;
		7560	bool dpd_is_edp = false;
3031	serge	7561	bool has_lvds;
2327	Serge	7562
2330	Serge	7563	has_lvds = intel_lvds_init(dev);
		7564	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		7565	/* disable the panel fitter on everything but LVDS */
		7566	I915_WRITE(PFIT_CONTROL, 0);
		7567	}
2327	Serge	7568
2330	Serge	7569	if (HAS_PCH_SPLIT(dev)) {
		7570	dpd_is_edp = intel_dpd_is_edp(dev);
2327	Serge	7571
2330	Serge	7572	if (has_edp_a(dev))
3031	serge	7573	intel_dp_init(dev, DP_A, PORT_A);
2327	Serge	7574
2330	Serge	7575	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
3031	serge	7576	intel_dp_init(dev, PCH_DP_D, PORT_D);
2330	Serge	7577	}
2327	Serge	7578
2330	Serge	7579	intel_crt_init(dev);
2327	Serge	7580
3031	serge	7581	if (IS_HASWELL(dev)) {
2330	Serge	7582	int found;
2327	Serge	7583
3031	serge	7584	/* Haswell uses DDI functions to detect digital outputs */
		7585	found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		7586	/* DDI A only supports eDP */
		7587	if (found)
		7588	intel_ddi_init(dev, PORT_A);
		7589
		7590	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		7591	* register */
		7592	found = I915_READ(SFUSE_STRAP);
		7593
		7594	if (found & SFUSE_STRAP_DDIB_DETECTED)
		7595	intel_ddi_init(dev, PORT_B);
		7596	if (found & SFUSE_STRAP_DDIC_DETECTED)
		7597	intel_ddi_init(dev, PORT_C);
		7598	if (found & SFUSE_STRAP_DDID_DETECTED)
		7599	intel_ddi_init(dev, PORT_D);
		7600	} else if (HAS_PCH_SPLIT(dev)) {
		7601	int found;
		7602
2330	Serge	7603	if (I915_READ(HDMIB) & PORT_DETECTED) {
		7604	/* PCH SDVOB multiplex with HDMIB */
3031	serge	7605	found = intel_sdvo_init(dev, PCH_SDVOB, true);
2330	Serge	7606	if (!found)
3031	serge	7607	intel_hdmi_init(dev, HDMIB, PORT_B);
2330	Serge	7608	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3031	serge	7609	intel_dp_init(dev, PCH_DP_B, PORT_B);
2330	Serge	7610	}
2327	Serge	7611
2330	Serge	7612	if (I915_READ(HDMIC) & PORT_DETECTED)
3031	serge	7613	intel_hdmi_init(dev, HDMIC, PORT_C);
2327	Serge	7614
3031	serge	7615	if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
		7616	intel_hdmi_init(dev, HDMID, PORT_D);
2327	Serge	7617
2330	Serge	7618	if (I915_READ(PCH_DP_C) & DP_DETECTED)
3031	serge	7619	intel_dp_init(dev, PCH_DP_C, PORT_C);
2327	Serge	7620
2330	Serge	7621	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
3031	serge	7622	intel_dp_init(dev, PCH_DP_D, PORT_D);
		7623	} else if (IS_VALLEYVIEW(dev)) {
		7624	int found;
2327	Serge	7625
3031	serge	7626	if (I915_READ(SDVOB) & PORT_DETECTED) {
		7627	/* SDVOB multiplex with HDMIB */
		7628	found = intel_sdvo_init(dev, SDVOB, true);
		7629	if (!found)
		7630	intel_hdmi_init(dev, SDVOB, PORT_B);
		7631	if (!found && (I915_READ(DP_B) & DP_DETECTED))
		7632	intel_dp_init(dev, DP_B, PORT_B);
		7633	}
		7634
		7635	if (I915_READ(SDVOC) & PORT_DETECTED)
		7636	intel_hdmi_init(dev, SDVOC, PORT_C);
		7637
		7638	/* Shares lanes with HDMI on SDVOC */
		7639	if (I915_READ(DP_C) & DP_DETECTED)
		7640	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	7641	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		7642	bool found = false;
2327	Serge	7643
2330	Serge	7644	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		7645	DRM_DEBUG_KMS("probing SDVOB\n");
3031	serge	7646	found = intel_sdvo_init(dev, SDVOB, true);
2330	Serge	7647	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		7648	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
3031	serge	7649	intel_hdmi_init(dev, SDVOB, PORT_B);
2330	Serge	7650	}
2327	Serge	7651
2330	Serge	7652	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
		7653	DRM_DEBUG_KMS("probing DP_B\n");
3031	serge	7654	intel_dp_init(dev, DP_B, PORT_B);
2330	Serge	7655	}
		7656	}
2327	Serge	7657
2330	Serge	7658	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	7659
2330	Serge	7660	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		7661	DRM_DEBUG_KMS("probing SDVOC\n");
3031	serge	7662	found = intel_sdvo_init(dev, SDVOC, false);
2330	Serge	7663	}
2327	Serge	7664
2330	Serge	7665	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
2327	Serge	7666
2330	Serge	7667	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		7668	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
3031	serge	7669	intel_hdmi_init(dev, SDVOC, PORT_C);
2330	Serge	7670	}
		7671	if (SUPPORTS_INTEGRATED_DP(dev)) {
		7672	DRM_DEBUG_KMS("probing DP_C\n");
3031	serge	7673	intel_dp_init(dev, DP_C, PORT_C);
2330	Serge	7674	}
		7675	}
2327	Serge	7676
2330	Serge	7677	if (SUPPORTS_INTEGRATED_DP(dev) &&
		7678	(I915_READ(DP_D) & DP_DETECTED)) {
		7679	DRM_DEBUG_KMS("probing DP_D\n");
3031	serge	7680	intel_dp_init(dev, DP_D, PORT_D);
2330	Serge	7681	}
		7682	} else if (IS_GEN2(dev))
		7683	intel_dvo_init(dev);
2327	Serge	7684
2330	Serge	7685	// if (SUPPORTS_TV(dev))
		7686	// intel_tv_init(dev);
2327	Serge	7687
2330	Serge	7688	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		7689	encoder->base.possible_crtcs = encoder->crtc_mask;
		7690	encoder->base.possible_clones =
3031	serge	7691	intel_encoder_clones(encoder);
2330	Serge	7692	}
2327	Serge	7693
3031	serge	7694	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
2342	Serge	7695	ironlake_init_pch_refclk(dev);
2330	Serge	7696	}
		7697
		7698
		7699
2335	Serge	7700	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		7701	// .destroy = intel_user_framebuffer_destroy,
		7702	// .create_handle = intel_user_framebuffer_create_handle,
		7703	};
2327	Serge	7704
2335	Serge	7705	int intel_framebuffer_init(struct drm_device *dev,
		7706	struct intel_framebuffer *intel_fb,
2342	Serge	7707	struct drm_mode_fb_cmd2 *mode_cmd,
2335	Serge	7708	struct drm_i915_gem_object *obj)
		7709	{
		7710	int ret;
2327	Serge	7711
2335	Serge	7712	if (obj->tiling_mode == I915_TILING_Y)
		7713	return -EINVAL;
2327	Serge	7714
2342	Serge	7715	if (mode_cmd->pitches[0] & 63)
2335	Serge	7716	return -EINVAL;
2327	Serge	7717
2342	Serge	7718	switch (mode_cmd->pixel_format) {
		7719	case DRM_FORMAT_RGB332:
		7720	case DRM_FORMAT_RGB565:
		7721	case DRM_FORMAT_XRGB8888:
3031	serge	7722	case DRM_FORMAT_XBGR8888:
2342	Serge	7723	case DRM_FORMAT_ARGB8888:
		7724	case DRM_FORMAT_XRGB2101010:
		7725	case DRM_FORMAT_ARGB2101010:
		7726	/* RGB formats are common across chipsets */
2335	Serge	7727	break;
2342	Serge	7728	case DRM_FORMAT_YUYV:
		7729	case DRM_FORMAT_UYVY:
		7730	case DRM_FORMAT_YVYU:
		7731	case DRM_FORMAT_VYUY:
		7732	break;
2335	Serge	7733	default:
3031	serge	7734	DRM_DEBUG_KMS("unsupported pixel format %u\n",
		7735	mode_cmd->pixel_format);
2335	Serge	7736	return -EINVAL;
		7737	}
2327	Serge	7738
2335	Serge	7739	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		7740	if (ret) {
		7741	DRM_ERROR("framebuffer init failed %d\n", ret);
		7742	return ret;
		7743	}
2327	Serge	7744
2335	Serge	7745	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		7746	intel_fb->obj = obj;
		7747	return 0;
		7748	}
2327	Serge	7749
		7750
2360	Serge	7751	static const struct drm_mode_config_funcs intel_mode_funcs = {
		7752	.fb_create = NULL /intel_user_framebuffer_create/,
		7753	.output_poll_changed = NULL /intel_fb_output_poll_changed/,
		7754	};
2327	Serge	7755
3031	serge	7756	/* Set up chip specific display functions */
		7757	static void intel_init_display(struct drm_device *dev)
		7758	{
		7759	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7760
3031	serge	7761	/* We always want a DPMS function */
		7762	if (HAS_PCH_SPLIT(dev)) {
		7763	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		7764	dev_priv->display.crtc_enable = ironlake_crtc_enable;
		7765	dev_priv->display.crtc_disable = ironlake_crtc_disable;
		7766	dev_priv->display.off = ironlake_crtc_off;
		7767	dev_priv->display.update_plane = ironlake_update_plane;
		7768	} else {
		7769	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		7770	dev_priv->display.crtc_enable = i9xx_crtc_enable;
		7771	dev_priv->display.crtc_disable = i9xx_crtc_disable;
		7772	dev_priv->display.off = i9xx_crtc_off;
		7773	dev_priv->display.update_plane = i9xx_update_plane;
		7774	}
2327	Serge	7775
3031	serge	7776	/* Returns the core display clock speed */
		7777	if (IS_VALLEYVIEW(dev))
		7778	dev_priv->display.get_display_clock_speed =
		7779	valleyview_get_display_clock_speed;
		7780	else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		7781	dev_priv->display.get_display_clock_speed =
		7782	i945_get_display_clock_speed;
		7783	else if (IS_I915G(dev))
		7784	dev_priv->display.get_display_clock_speed =
		7785	i915_get_display_clock_speed;
		7786	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
		7787	dev_priv->display.get_display_clock_speed =
		7788	i9xx_misc_get_display_clock_speed;
		7789	else if (IS_I915GM(dev))
		7790	dev_priv->display.get_display_clock_speed =
		7791	i915gm_get_display_clock_speed;
		7792	else if (IS_I865G(dev))
		7793	dev_priv->display.get_display_clock_speed =
		7794	i865_get_display_clock_speed;
		7795	else if (IS_I85X(dev))
		7796	dev_priv->display.get_display_clock_speed =
		7797	i855_get_display_clock_speed;
		7798	else /* 852, 830 */
		7799	dev_priv->display.get_display_clock_speed =
		7800	i830_get_display_clock_speed;
2327	Serge	7801
3031	serge	7802	if (HAS_PCH_SPLIT(dev)) {
		7803	if (IS_GEN5(dev)) {
		7804	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		7805	dev_priv->display.write_eld = ironlake_write_eld;
		7806	} else if (IS_GEN6(dev)) {
		7807	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		7808	dev_priv->display.write_eld = ironlake_write_eld;
		7809	} else if (IS_IVYBRIDGE(dev)) {
		7810	/* FIXME: detect B0+ stepping and use auto training */
		7811	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		7812	dev_priv->display.write_eld = ironlake_write_eld;
		7813	} else if (IS_HASWELL(dev)) {
		7814	dev_priv->display.fdi_link_train = hsw_fdi_link_train;
		7815	dev_priv->display.write_eld = haswell_write_eld;
		7816	} else
		7817	dev_priv->display.update_wm = NULL;
		7818	} else if (IS_G4X(dev)) {
		7819	dev_priv->display.write_eld = g4x_write_eld;
		7820	}
2327	Serge	7821
3031	serge	7822	/* Default just returns -ENODEV to indicate unsupported */
		7823	// dev_priv->display.queue_flip = intel_default_queue_flip;
2327	Serge	7824
		7825
		7826
		7827
3031	serge	7828	}
		7829
		7830	/*
		7831	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		7832	* resume, or other times. This quirk makes sure that's the case for
		7833	* affected systems.
		7834	*/
		7835	static void quirk_pipea_force(struct drm_device *dev)
2330	Serge	7836	{
		7837	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7838
3031	serge	7839	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		7840	DRM_INFO("applying pipe a force quirk\n");
		7841	}
2327	Serge	7842
3031	serge	7843	/*
		7844	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		7845	*/
		7846	static void quirk_ssc_force_disable(struct drm_device *dev)
		7847	{
		7848	struct drm_i915_private *dev_priv = dev->dev_private;
		7849	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		7850	DRM_INFO("applying lvds SSC disable quirk\n");
2330	Serge	7851	}
2327	Serge	7852
3031	serge	7853	/*
		7854	* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
		7855	* brightness value
		7856	*/
		7857	static void quirk_invert_brightness(struct drm_device *dev)
2330	Serge	7858	{
		7859	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7860	dev_priv->quirks \|= QUIRK_INVERT_BRIGHTNESS;
		7861	DRM_INFO("applying inverted panel brightness quirk\n");
		7862	}
2327	Serge	7863
3031	serge	7864	struct intel_quirk {
		7865	int device;
		7866	int subsystem_vendor;
		7867	int subsystem_device;
		7868	void (hook)(struct drm_device dev);
		7869	};
2327	Serge	7870
3031	serge	7871	/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
		7872	struct intel_dmi_quirk {
		7873	void (hook)(struct drm_device dev);
		7874	const struct dmi_system_id (*dmi_id_list)[];
		7875	};
2327	Serge	7876
3031	serge	7877	static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
		7878	{
		7879	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
		7880	return 1;
2330	Serge	7881	}
2327	Serge	7882
3031	serge	7883	static const struct intel_dmi_quirk intel_dmi_quirks[] = {
		7884	{
		7885	.dmi_id_list = &(const struct dmi_system_id[]) {
		7886	{
		7887	.callback = intel_dmi_reverse_brightness,
		7888	.ident = "NCR Corporation",
		7889	.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
		7890	DMI_MATCH(DMI_PRODUCT_NAME, ""),
		7891	},
		7892	},
		7893	{ } /* terminating entry */
		7894	},
		7895	.hook = quirk_invert_brightness,
		7896	},
		7897	};
2327	Serge	7898
3031	serge	7899	static struct intel_quirk intel_quirks[] = {
		7900	/* HP Mini needs pipe A force quirk (LP: #322104) */
		7901	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327	Serge	7902
3031	serge	7903	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		7904	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
2327	Serge	7905
3031	serge	7906	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		7907	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
2327	Serge	7908
3031	serge	7909	/* 830/845 need to leave pipe A & dpll A up */
		7910	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7911	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
2327	Serge	7912
3031	serge	7913	/* Lenovo U160 cannot use SSC on LVDS */
		7914	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
2327	Serge	7915
3031	serge	7916	/* Sony Vaio Y cannot use SSC on LVDS */
		7917	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
2327	Serge	7918
3031	serge	7919	/* Acer Aspire 5734Z must invert backlight brightness */
		7920	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
		7921	};
2327	Serge	7922
3031	serge	7923	static void intel_init_quirks(struct drm_device *dev)
2330	Serge	7924	{
3031	serge	7925	struct pci_dev *d = dev->pdev;
		7926	int i;
2327	Serge	7927
3031	serge	7928	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		7929	struct intel_quirk *q = &intel_quirks[i];
2327	Serge	7930
3031	serge	7931	if (d->device == q->device &&
		7932	(d->subsystem_vendor == q->subsystem_vendor \|\|
		7933	q->subsystem_vendor == PCI_ANY_ID) &&
		7934	(d->subsystem_device == q->subsystem_device \|\|
		7935	q->subsystem_device == PCI_ANY_ID))
		7936	q->hook(dev);
		7937	}
		7938	// for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		7939	// if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
		7940	// intel_dmi_quirks[i].hook(dev);
		7941	// }
2330	Serge	7942	}
2327	Serge	7943
3031	serge	7944	/* Disable the VGA plane that we never use */
		7945	static void i915_disable_vga(struct drm_device *dev)
2330	Serge	7946	{
		7947	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	7948	u8 sr1;
		7949	u32 vga_reg;
2327	Serge	7950
3031	serge	7951	if (HAS_PCH_SPLIT(dev))
		7952	vga_reg = CPU_VGACNTRL;
		7953	else
		7954	vga_reg = VGACNTRL;
2327	Serge	7955
3031	serge	7956	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		7957	out8(SR01, VGA_SR_INDEX);
		7958	sr1 = in8(VGA_SR_DATA);
		7959	out8(sr1 \| 1<<5, VGA_SR_DATA);
		7960	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		7961	udelay(300);
2327	Serge	7962
3031	serge	7963	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		7964	POSTING_READ(vga_reg);
2330	Serge	7965	}
		7966
3031	serge	7967	void intel_modeset_init_hw(struct drm_device *dev)
2342	Serge	7968	{
3031	serge	7969	/* We attempt to init the necessary power wells early in the initialization
		7970	* time, so the subsystems that expect power to be enabled can work.
2342	Serge	7971	*/
3031	serge	7972	intel_init_power_wells(dev);
2342	Serge	7973
3031	serge	7974	intel_prepare_ddi(dev);
2342	Serge	7975
3031	serge	7976	intel_init_clock_gating(dev);
		7977
		7978	// mutex_lock(&dev->struct_mutex);
		7979	// intel_enable_gt_powersave(dev);
		7980	// mutex_unlock(&dev->struct_mutex);
2342	Serge	7981	}
		7982
3031	serge	7983	void intel_modeset_init(struct drm_device *dev)
2330	Serge	7984	{
3031	serge	7985	struct drm_i915_private *dev_priv = dev->dev_private;
		7986	int i, ret;
2330	Serge	7987
3031	serge	7988	drm_mode_config_init(dev);
2330	Serge	7989
3031	serge	7990	dev->mode_config.min_width = 0;
		7991	dev->mode_config.min_height = 0;
2330	Serge	7992
3031	serge	7993	dev->mode_config.preferred_depth = 24;
		7994	dev->mode_config.prefer_shadow = 1;
2330	Serge	7995
3031	serge	7996	dev->mode_config.funcs = &intel_mode_funcs;
2330	Serge	7997
3031	serge	7998	intel_init_quirks(dev);
2330	Serge	7999
3031	serge	8000	intel_init_pm(dev);
2330	Serge	8001
3031	serge	8002	intel_init_display(dev);
2330	Serge	8003
3031	serge	8004	if (IS_GEN2(dev)) {
		8005	dev->mode_config.max_width = 2048;
		8006	dev->mode_config.max_height = 2048;
		8007	} else if (IS_GEN3(dev)) {
		8008	dev->mode_config.max_width = 4096;
		8009	dev->mode_config.max_height = 4096;
		8010	} else {
		8011	dev->mode_config.max_width = 8192;
		8012	dev->mode_config.max_height = 8192;
		8013	}
		8014	dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
2330	Serge	8015
3031	serge	8016	DRM_DEBUG_KMS("%d display pipe%s available.\n",
		8017	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
2330	Serge	8018
3031	serge	8019	for (i = 0; i < dev_priv->num_pipe; i++) {
		8020	intel_crtc_init(dev, i);
		8021	ret = intel_plane_init(dev, i);
		8022	if (ret)
		8023	DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
2330	Serge	8024	}
		8025
3031	serge	8026	intel_pch_pll_init(dev);
2330	Serge	8027
3031	serge	8028	/* Just disable it once at startup */
		8029	i915_disable_vga(dev);
		8030	intel_setup_outputs(dev);
		8031	}
2330	Serge	8032
3031	serge	8033	static void
		8034	intel_connector_break_all_links(struct intel_connector *connector)
		8035	{
		8036	connector->base.dpms = DRM_MODE_DPMS_OFF;
		8037	connector->base.encoder = NULL;
		8038	connector->encoder->connectors_active = false;
		8039	connector->encoder->base.crtc = NULL;
2330	Serge	8040	}
		8041
3031	serge	8042	static void intel_enable_pipe_a(struct drm_device *dev)
2330	Serge	8043	{
3031	serge	8044	struct intel_connector *connector;
		8045	struct drm_connector *crt = NULL;
		8046	struct intel_load_detect_pipe load_detect_temp;
2330	Serge	8047
3031	serge	8048	/* We can't just switch on the pipe A, we need to set things up with a
		8049	* proper mode and output configuration. As a gross hack, enable pipe A
		8050	* by enabling the load detect pipe once. */
		8051	list_for_each_entry(connector,
		8052	&dev->mode_config.connector_list,
		8053	base.head) {
		8054	if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
		8055	crt = &connector->base;
		8056	break;
2330	Serge	8057	}
		8058	}
		8059
3031	serge	8060	if (!crt)
		8061	return;
2330	Serge	8062
3031	serge	8063	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		8064	intel_release_load_detect_pipe(crt, &load_detect_temp);
2327	Serge	8065
		8066
		8067	}
		8068
3031	serge	8069	static bool
		8070	intel_check_plane_mapping(struct intel_crtc *crtc)
2327	Serge	8071	{
3031	serge	8072	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
		8073	u32 reg, val;
2327	Serge	8074
3031	serge	8075	if (dev_priv->num_pipe == 1)
		8076	return true;
2327	Serge	8077
3031	serge	8078	reg = DSPCNTR(!crtc->plane);
		8079	val = I915_READ(reg);
2327	Serge	8080
3031	serge	8081	if ((val & DISPLAY_PLANE_ENABLE) &&
		8082	(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		8083	return false;
2327	Serge	8084
3031	serge	8085	return true;
2327	Serge	8086	}
		8087
3031	serge	8088	static void intel_sanitize_crtc(struct intel_crtc *crtc)
2327	Serge	8089	{
3031	serge	8090	struct drm_device *dev = crtc->base.dev;
2327	Serge	8091	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8092	u32 reg;
2327	Serge	8093
3031	serge	8094	/* Clear any frame start delays used for debugging left by the BIOS */
		8095	reg = PIPECONF(crtc->pipe);
		8096	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
2327	Serge	8097
3031	serge	8098	/* We need to sanitize the plane -> pipe mapping first because this will
		8099	* disable the crtc (and hence change the state) if it is wrong. Note
		8100	* that gen4+ has a fixed plane -> pipe mapping. */
		8101	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
		8102	struct intel_connector *connector;
		8103	bool plane;
2327	Serge	8104
3031	serge	8105	DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
		8106	crtc->base.base.id);
2327	Serge	8107
3031	serge	8108	/* Pipe has the wrong plane attached and the plane is active.
		8109	* Temporarily change the plane mapping and disable everything
		8110	* ... */
		8111	plane = crtc->plane;
		8112	crtc->plane = !plane;
		8113	dev_priv->display.crtc_disable(&crtc->base);
		8114	crtc->plane = plane;
2342	Serge	8115
3031	serge	8116	/* ... and break all links. */
		8117	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8118	base.head) {
		8119	if (connector->encoder->base.crtc != &crtc->base)
		8120	continue;
2327	Serge	8121
3031	serge	8122	intel_connector_break_all_links(connector);
		8123	}
2327	Serge	8124
3031	serge	8125	WARN_ON(crtc->active);
		8126	crtc->base.enabled = false;
		8127	}
2327	Serge	8128
3031	serge	8129	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
		8130	crtc->pipe == PIPE_A && !crtc->active) {
		8131	/* BIOS forgot to enable pipe A, this mostly happens after
		8132	* resume. Force-enable the pipe to fix this, the update_dpms
		8133	* call below we restore the pipe to the right state, but leave
		8134	* the required bits on. */
		8135	intel_enable_pipe_a(dev);
		8136	}
2327	Serge	8137
3031	serge	8138	/* Adjust the state of the output pipe according to whether we
		8139	* have active connectors/encoders. */
		8140	intel_crtc_update_dpms(&crtc->base);
2327	Serge	8141
3031	serge	8142	if (crtc->active != crtc->base.enabled) {
		8143	struct intel_encoder *encoder;
2327	Serge	8144
3031	serge	8145	/* This can happen either due to bugs in the get_hw_state
		8146	* functions or because the pipe is force-enabled due to the
		8147	* pipe A quirk. */
		8148	DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
		8149	crtc->base.base.id,
		8150	crtc->base.enabled ? "enabled" : "disabled",
		8151	crtc->active ? "enabled" : "disabled");
2327	Serge	8152
3031	serge	8153	crtc->base.enabled = crtc->active;
2327	Serge	8154
3031	serge	8155	/* Because we only establish the connector -> encoder ->
		8156	* crtc links if something is active, this means the
		8157	* crtc is now deactivated. Break the links. connector
		8158	* -> encoder links are only establish when things are
		8159	* actually up, hence no need to break them. */
		8160	WARN_ON(crtc->active);
2327	Serge	8161
3031	serge	8162	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		8163	WARN_ON(encoder->connectors_active);
		8164	encoder->base.crtc = NULL;
		8165	}
		8166	}
2327	Serge	8167	}
		8168
3031	serge	8169	static void intel_sanitize_encoder(struct intel_encoder *encoder)
2327	Serge	8170	{
3031	serge	8171	struct intel_connector *connector;
		8172	struct drm_device *dev = encoder->base.dev;
2327	Serge	8173
3031	serge	8174	/* We need to check both for a crtc link (meaning that the
		8175	* encoder is active and trying to read from a pipe) and the
		8176	* pipe itself being active. */
		8177	bool has_active_crtc = encoder->base.crtc &&
		8178	to_intel_crtc(encoder->base.crtc)->active;
2327	Serge	8179
3031	serge	8180	if (encoder->connectors_active && !has_active_crtc) {
		8181	DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
		8182	encoder->base.base.id,
		8183	drm_get_encoder_name(&encoder->base));
2327	Serge	8184
3031	serge	8185	/* Connector is active, but has no active pipe. This is
		8186	* fallout from our resume register restoring. Disable
		8187	* the encoder manually again. */
		8188	if (encoder->base.crtc) {
		8189	DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
		8190	encoder->base.base.id,
		8191	drm_get_encoder_name(&encoder->base));
		8192	encoder->disable(encoder);
		8193	}
2327	Serge	8194
3031	serge	8195	/* Inconsistent output/port/pipe state happens presumably due to
		8196	* a bug in one of the get_hw_state functions. Or someplace else
		8197	* in our code, like the register restore mess on resume. Clamp
		8198	* things to off as a safer default. */
		8199	list_for_each_entry(connector,
		8200	&dev->mode_config.connector_list,
		8201	base.head) {
		8202	if (connector->encoder != encoder)
		8203	continue;
2327	Serge	8204
3031	serge	8205	intel_connector_break_all_links(connector);
		8206	}
		8207	}
		8208	/* Enabled encoders without active connectors will be fixed in
		8209	* the crtc fixup. */
2327	Serge	8210	}
		8211
3031	serge	8212	/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
		8213	* and i915 state tracking structures. */
		8214	void intel_modeset_setup_hw_state(struct drm_device *dev)
2332	Serge	8215	{
		8216	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8217	enum pipe pipe;
		8218	u32 tmp;
		8219	struct intel_crtc *crtc;
		8220	struct intel_encoder *encoder;
		8221	struct intel_connector *connector;
2327	Serge	8222
3031	serge	8223	for_each_pipe(pipe) {
		8224	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2327	Serge	8225
3031	serge	8226	tmp = I915_READ(PIPECONF(pipe));
		8227	if (tmp & PIPECONF_ENABLE)
		8228	crtc->active = true;
		8229	else
		8230	crtc->active = false;
2327	Serge	8231
3031	serge	8232	crtc->base.enabled = crtc->active;
2330	Serge	8233
3031	serge	8234	DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
		8235	crtc->base.base.id,
		8236	crtc->active ? "enabled" : "disabled");
2339	Serge	8237	}
2332	Serge	8238
3031	serge	8239	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8240	base.head) {
		8241	pipe = 0;
2332	Serge	8242
3031	serge	8243	if (encoder->get_hw_state(encoder, &pipe)) {
		8244	encoder->base.crtc =
		8245	dev_priv->pipe_to_crtc_mapping[pipe];
		8246	} else {
		8247	encoder->base.crtc = NULL;
		8248	}
2332	Serge	8249
3031	serge	8250	encoder->connectors_active = false;
		8251	DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
		8252	encoder->base.base.id,
		8253	drm_get_encoder_name(&encoder->base),
		8254	encoder->base.crtc ? "enabled" : "disabled",
		8255	pipe);
		8256	}
2332	Serge	8257
3031	serge	8258	list_for_each_entry(connector, &dev->mode_config.connector_list,
		8259	base.head) {
		8260	if (connector->get_hw_state(connector)) {
		8261	connector->base.dpms = DRM_MODE_DPMS_ON;
		8262	connector->encoder->connectors_active = true;
		8263	connector->base.encoder = &connector->encoder->base;
		8264	} else {
		8265	connector->base.dpms = DRM_MODE_DPMS_OFF;
		8266	connector->base.encoder = NULL;
		8267	}
		8268	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
		8269	connector->base.base.id,
		8270	drm_get_connector_name(&connector->base),
		8271	connector->base.encoder ? "enabled" : "disabled");
2332	Serge	8272	}
		8273
3031	serge	8274	/* HW state is read out, now we need to sanitize this mess. */
		8275	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
		8276	base.head) {
		8277	intel_sanitize_encoder(encoder);
2332	Serge	8278	}
		8279
3031	serge	8280	for_each_pipe(pipe) {
		8281	crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		8282	intel_sanitize_crtc(crtc);
2332	Serge	8283	}
		8284
3031	serge	8285	intel_modeset_update_staged_output_state(dev);
2332	Serge	8286
3031	serge	8287	intel_modeset_check_state(dev);
2332	Serge	8288	}
		8289
3031	serge	8290	void intel_modeset_gem_init(struct drm_device *dev)
2330	Serge	8291	{
3031	serge	8292	intel_modeset_init_hw(dev);
2330	Serge	8293
3031	serge	8294	// intel_setup_overlay(dev);
2330	Serge	8295
3031	serge	8296	intel_modeset_setup_hw_state(dev);
2330	Serge	8297	}
		8298
3031	serge	8299	void intel_modeset_cleanup(struct drm_device *dev)
2327	Serge	8300	{
3031	serge	8301	#if 0
		8302	struct drm_i915_private *dev_priv = dev->dev_private;
		8303	struct drm_crtc *crtc;
		8304	struct intel_crtc *intel_crtc;
2327	Serge	8305
3031	serge	8306	// drm_kms_helper_poll_fini(dev);
		8307	mutex_lock(&dev->struct_mutex);
2327	Serge	8308
3031	serge	8309	// intel_unregister_dsm_handler();
2327	Serge	8310
		8311
3031	serge	8312	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		8313	/* Skip inactive CRTCs */
		8314	if (!crtc->fb)
		8315	continue;
2342	Serge	8316
3031	serge	8317	intel_crtc = to_intel_crtc(crtc);
		8318	intel_increase_pllclock(crtc);
		8319	}
2342	Serge	8320
3031	serge	8321	intel_disable_fbc(dev);
2342	Serge	8322
3031	serge	8323	intel_disable_gt_powersave(dev);
2342	Serge	8324
3031	serge	8325	ironlake_teardown_rc6(dev);
2327	Serge	8326
3031	serge	8327	if (IS_VALLEYVIEW(dev))
		8328	vlv_init_dpio(dev);
2327	Serge	8329
3031	serge	8330	mutex_unlock(&dev->struct_mutex);
2327	Serge	8331
3031	serge	8332	/* Disable the irq before mode object teardown, for the irq might
		8333	* enqueue unpin/hotplug work. */
		8334	// drm_irq_uninstall(dev);
		8335	// cancel_work_sync(&dev_priv->hotplug_work);
		8336	// cancel_work_sync(&dev_priv->rps.work);
2327	Serge	8337
3031	serge	8338	/* flush any delayed tasks or pending work */
		8339	// flush_scheduled_work();
2327	Serge	8340
3031	serge	8341	drm_mode_config_cleanup(dev);
2327	Serge	8342	#endif
		8343	}
		8344
		8345	/*
3031	serge	8346	* Return which encoder is currently attached for connector.
2327	Serge	8347	*/
3031	serge	8348	struct drm_encoder intel_best_encoder(struct drm_connector connector)
2327	Serge	8349	{
3031	serge	8350	return &intel_attached_encoder(connector)->base;
		8351	}
2327	Serge	8352
3031	serge	8353	void intel_connector_attach_encoder(struct intel_connector *connector,
		8354	struct intel_encoder *encoder)
		8355	{
		8356	connector->encoder = encoder;
		8357	drm_mode_connector_attach_encoder(&connector->base,
		8358	&encoder->base);
2327	Serge	8359	}
		8360
		8361	/*
3031	serge	8362	* set vga decode state - true == enable VGA decode
2327	Serge	8363	*/
3031	serge	8364	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
2327	Serge	8365	{
2330	Serge	8366	struct drm_i915_private *dev_priv = dev->dev_private;
3031	serge	8367	u16 gmch_ctrl;
2327	Serge	8368
3031	serge	8369	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
		8370	if (state)
		8371	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
2330	Serge	8372	else
3031	serge	8373	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
		8374	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
		8375	return 0;
2330	Serge	8376	}
		8377
3031	serge	8378	#ifdef CONFIG_DEBUG_FS
		8379	#include
2327	Serge	8380
3031	serge	8381	struct intel_display_error_state {
		8382	struct intel_cursor_error_state {
		8383	u32 control;
		8384	u32 position;
		8385	u32 base;
		8386	u32 size;
		8387	} cursor[I915_MAX_PIPES];
2327	Serge	8388
3031	serge	8389	struct intel_pipe_error_state {
		8390	u32 conf;
		8391	u32 source;
2327	Serge	8392
3031	serge	8393	u32 htotal;
		8394	u32 hblank;
		8395	u32 hsync;
		8396	u32 vtotal;
		8397	u32 vblank;
		8398	u32 vsync;
		8399	} pipe[I915_MAX_PIPES];
2327	Serge	8400
3031	serge	8401	struct intel_plane_error_state {
		8402	u32 control;
		8403	u32 stride;
		8404	u32 size;
		8405	u32 pos;
		8406	u32 addr;
		8407	u32 surface;
		8408	u32 tile_offset;
		8409	} plane[I915_MAX_PIPES];
		8410	};
2327	Serge	8411
3031	serge	8412	struct intel_display_error_state *
		8413	intel_display_capture_error_state(struct drm_device *dev)
		8414	{
		8415	drm_i915_private_t *dev_priv = dev->dev_private;
		8416	struct intel_display_error_state *error;
		8417	int i;
2327	Serge	8418
3031	serge	8419	error = kmalloc(sizeof(*error), GFP_ATOMIC);
		8420	if (error == NULL)
		8421	return NULL;
2327	Serge	8422
3031	serge	8423	for_each_pipe(i) {
		8424	error->cursor[i].control = I915_READ(CURCNTR(i));
		8425	error->cursor[i].position = I915_READ(CURPOS(i));
		8426	error->cursor[i].base = I915_READ(CURBASE(i));
2327	Serge	8427
3031	serge	8428	error->plane[i].control = I915_READ(DSPCNTR(i));
		8429	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
		8430	error->plane[i].size = I915_READ(DSPSIZE(i));
		8431	error->plane[i].pos = I915_READ(DSPPOS(i));
		8432	error->plane[i].addr = I915_READ(DSPADDR(i));
		8433	if (INTEL_INFO(dev)->gen >= 4) {
		8434	error->plane[i].surface = I915_READ(DSPSURF(i));
		8435	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		8436	}
2327	Serge	8437
3031	serge	8438	error->pipe[i].conf = I915_READ(PIPECONF(i));
		8439	error->pipe[i].source = I915_READ(PIPESRC(i));
		8440	error->pipe[i].htotal = I915_READ(HTOTAL(i));
		8441	error->pipe[i].hblank = I915_READ(HBLANK(i));
		8442	error->pipe[i].hsync = I915_READ(HSYNC(i));
		8443	error->pipe[i].vtotal = I915_READ(VTOTAL(i));
		8444	error->pipe[i].vblank = I915_READ(VBLANK(i));
		8445	error->pipe[i].vsync = I915_READ(VSYNC(i));
		8446	}
2327	Serge	8447
3031	serge	8448	return error;
2330	Serge	8449	}
2327	Serge	8450
3031	serge	8451	void
		8452	intel_display_print_error_state(struct seq_file *m,
		8453	struct drm_device *dev,
		8454	struct intel_display_error_state *error)
2332	Serge	8455	{
3031	serge	8456	drm_i915_private_t *dev_priv = dev->dev_private;
		8457	int i;
2330	Serge	8458
3031	serge	8459	seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
		8460	for_each_pipe(i) {
		8461	seq_printf(m, "Pipe [%d]:\n", i);
		8462	seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
		8463	seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
		8464	seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
		8465	seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
		8466	seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
		8467	seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
		8468	seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
		8469	seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
2332	Serge	8470
3031	serge	8471	seq_printf(m, "Plane [%d]:\n", i);
		8472	seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
		8473	seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
		8474	seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
		8475	seq_printf(m, " POS: %08x\n", error->plane[i].pos);
		8476	seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
		8477	if (INTEL_INFO(dev)->gen >= 4) {
		8478	seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
		8479	seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
		8480	}
2332	Serge	8481
3031	serge	8482	seq_printf(m, "Cursor [%d]:\n", i);
		8483	seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
		8484	seq_printf(m, " POS: %08x\n", error->cursor[i].position);
		8485	seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
		8486	}
2327	Serge	8487	}
3031	serge	8488	#endif

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(root)/drivers/video/drm/i915/intel_display.c – Rev 3031