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2327 Serge 1
/*
2
 * Copyright © 2006-2007 Intel Corporation
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice (including the next
12
 * paragraph) shall be included in all copies or substantial portions of the
13
 * Software.
14
 *
15
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
 * DEALINGS IN THE SOFTWARE.
22
 *
23
 * Authors:
24
 *  Eric Anholt 
25
 */
26
 
27
//#include 
28
#include 
29
//#include 
30
#include 
31
#include 
2330 Serge 32
#include 
2327 Serge 33
//#include 
2342 Serge 34
#include 
2327 Serge 35
#include "drmP.h"
36
#include "intel_drv.h"
2330 Serge 37
#include "i915_drm.h"
2327 Serge 38
#include "i915_drv.h"
39
//#include "i915_trace.h"
40
#include "drm_dp_helper.h"
41
 
42
#include "drm_crtc_helper.h"
43
 
44
phys_addr_t get_bus_addr(void);
45
 
46
static inline __attribute__((const))
47
bool is_power_of_2(unsigned long n)
48
{
49
    return (n != 0 && ((n & (n - 1)) == 0));
50
}
51
 
2330 Serge 52
#define MAX_ERRNO       4095
53
 
54
#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
55
 
56
static inline long IS_ERR(const void *ptr)
57
{
58
    return IS_ERR_VALUE((unsigned long)ptr);
59
}
60
 
61
static inline void *ERR_PTR(long error)
62
{
63
    return (void *) error;
64
}
65
 
66
 
2327 Serge 67
static inline int pci_read_config_word(struct pci_dev *dev, int where,
68
                    u16 *val)
69
{
70
    *val = PciRead16(dev->busnr, dev->devfn, where);
71
    return 1;
72
}
73
 
74
 
75
#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
76
 
2342 Serge 77
bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
2327 Serge 78
static void intel_update_watermarks(struct drm_device *dev);
79
static void intel_increase_pllclock(struct drm_crtc *crtc);
80
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
81
 
82
typedef struct {
83
    /* given values */
84
    int n;
85
    int m1, m2;
86
    int p1, p2;
87
    /* derived values */
88
    int dot;
89
    int vco;
90
    int m;
91
    int p;
92
} intel_clock_t;
93
 
94
typedef struct {
95
    int min, max;
96
} intel_range_t;
97
 
98
typedef struct {
99
    int dot_limit;
100
    int p2_slow, p2_fast;
101
} intel_p2_t;
102
 
103
#define INTEL_P2_NUM              2
104
typedef struct intel_limit intel_limit_t;
105
struct intel_limit {
106
    intel_range_t   dot, vco, n, m, m1, m2, p, p1;
107
    intel_p2_t      p2;
108
    bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
109
              int, int, intel_clock_t *);
110
};
111
 
112
/* FDI */
113
#define IRONLAKE_FDI_FREQ       2700000 /* in kHz for mode->clock */
114
 
115
static bool
116
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
117
            int target, int refclk, intel_clock_t *best_clock);
118
static bool
119
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
120
            int target, int refclk, intel_clock_t *best_clock);
121
 
122
static bool
123
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
124
              int target, int refclk, intel_clock_t *best_clock);
125
static bool
126
intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
127
               int target, int refclk, intel_clock_t *best_clock);
128
 
129
static inline u32 /* units of 100MHz */
130
intel_fdi_link_freq(struct drm_device *dev)
131
{
132
	if (IS_GEN5(dev)) {
133
		struct drm_i915_private *dev_priv = dev->dev_private;
134
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135
	} else
136
		return 27;
137
}
138
 
139
static const intel_limit_t intel_limits_i8xx_dvo = {
140
        .dot = { .min = 25000, .max = 350000 },
141
        .vco = { .min = 930000, .max = 1400000 },
142
        .n = { .min = 3, .max = 16 },
143
        .m = { .min = 96, .max = 140 },
144
        .m1 = { .min = 18, .max = 26 },
145
        .m2 = { .min = 6, .max = 16 },
146
        .p = { .min = 4, .max = 128 },
147
        .p1 = { .min = 2, .max = 33 },
148
	.p2 = { .dot_limit = 165000,
149
		.p2_slow = 4, .p2_fast = 2 },
150
	.find_pll = intel_find_best_PLL,
151
};
152
 
153
static const intel_limit_t intel_limits_i8xx_lvds = {
154
        .dot = { .min = 25000, .max = 350000 },
155
        .vco = { .min = 930000, .max = 1400000 },
156
        .n = { .min = 3, .max = 16 },
157
        .m = { .min = 96, .max = 140 },
158
        .m1 = { .min = 18, .max = 26 },
159
        .m2 = { .min = 6, .max = 16 },
160
        .p = { .min = 4, .max = 128 },
161
        .p1 = { .min = 1, .max = 6 },
162
	.p2 = { .dot_limit = 165000,
163
		.p2_slow = 14, .p2_fast = 7 },
164
	.find_pll = intel_find_best_PLL,
165
};
166
 
167
static const intel_limit_t intel_limits_i9xx_sdvo = {
168
        .dot = { .min = 20000, .max = 400000 },
169
        .vco = { .min = 1400000, .max = 2800000 },
170
        .n = { .min = 1, .max = 6 },
171
        .m = { .min = 70, .max = 120 },
172
        .m1 = { .min = 10, .max = 22 },
173
        .m2 = { .min = 5, .max = 9 },
174
        .p = { .min = 5, .max = 80 },
175
        .p1 = { .min = 1, .max = 8 },
176
	.p2 = { .dot_limit = 200000,
177
		.p2_slow = 10, .p2_fast = 5 },
178
	.find_pll = intel_find_best_PLL,
179
};
180
 
181
static const intel_limit_t intel_limits_i9xx_lvds = {
182
        .dot = { .min = 20000, .max = 400000 },
183
        .vco = { .min = 1400000, .max = 2800000 },
184
        .n = { .min = 1, .max = 6 },
185
        .m = { .min = 70, .max = 120 },
186
        .m1 = { .min = 10, .max = 22 },
187
        .m2 = { .min = 5, .max = 9 },
188
        .p = { .min = 7, .max = 98 },
189
        .p1 = { .min = 1, .max = 8 },
190
	.p2 = { .dot_limit = 112000,
191
		.p2_slow = 14, .p2_fast = 7 },
192
	.find_pll = intel_find_best_PLL,
193
};
194
 
195
 
196
static const intel_limit_t intel_limits_g4x_sdvo = {
197
	.dot = { .min = 25000, .max = 270000 },
198
	.vco = { .min = 1750000, .max = 3500000},
199
	.n = { .min = 1, .max = 4 },
200
	.m = { .min = 104, .max = 138 },
201
	.m1 = { .min = 17, .max = 23 },
202
	.m2 = { .min = 5, .max = 11 },
203
	.p = { .min = 10, .max = 30 },
204
	.p1 = { .min = 1, .max = 3},
205
	.p2 = { .dot_limit = 270000,
206
		.p2_slow = 10,
207
		.p2_fast = 10
208
	},
209
	.find_pll = intel_g4x_find_best_PLL,
210
};
211
 
212
static const intel_limit_t intel_limits_g4x_hdmi = {
213
	.dot = { .min = 22000, .max = 400000 },
214
	.vco = { .min = 1750000, .max = 3500000},
215
	.n = { .min = 1, .max = 4 },
216
	.m = { .min = 104, .max = 138 },
217
	.m1 = { .min = 16, .max = 23 },
218
	.m2 = { .min = 5, .max = 11 },
219
	.p = { .min = 5, .max = 80 },
220
	.p1 = { .min = 1, .max = 8},
221
	.p2 = { .dot_limit = 165000,
222
		.p2_slow = 10, .p2_fast = 5 },
223
	.find_pll = intel_g4x_find_best_PLL,
224
};
225
 
226
static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
227
	.dot = { .min = 20000, .max = 115000 },
228
	.vco = { .min = 1750000, .max = 3500000 },
229
	.n = { .min = 1, .max = 3 },
230
	.m = { .min = 104, .max = 138 },
231
	.m1 = { .min = 17, .max = 23 },
232
	.m2 = { .min = 5, .max = 11 },
233
	.p = { .min = 28, .max = 112 },
234
	.p1 = { .min = 2, .max = 8 },
235
	.p2 = { .dot_limit = 0,
236
		.p2_slow = 14, .p2_fast = 14
237
	},
238
	.find_pll = intel_g4x_find_best_PLL,
239
};
240
 
241
static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
242
	.dot = { .min = 80000, .max = 224000 },
243
	.vco = { .min = 1750000, .max = 3500000 },
244
	.n = { .min = 1, .max = 3 },
245
	.m = { .min = 104, .max = 138 },
246
	.m1 = { .min = 17, .max = 23 },
247
	.m2 = { .min = 5, .max = 11 },
248
	.p = { .min = 14, .max = 42 },
249
	.p1 = { .min = 2, .max = 6 },
250
	.p2 = { .dot_limit = 0,
251
		.p2_slow = 7, .p2_fast = 7
252
	},
253
	.find_pll = intel_g4x_find_best_PLL,
254
};
255
 
256
static const intel_limit_t intel_limits_g4x_display_port = {
257
        .dot = { .min = 161670, .max = 227000 },
258
        .vco = { .min = 1750000, .max = 3500000},
259
        .n = { .min = 1, .max = 2 },
260
        .m = { .min = 97, .max = 108 },
261
        .m1 = { .min = 0x10, .max = 0x12 },
262
        .m2 = { .min = 0x05, .max = 0x06 },
263
        .p = { .min = 10, .max = 20 },
264
        .p1 = { .min = 1, .max = 2},
265
        .p2 = { .dot_limit = 0,
266
		.p2_slow = 10, .p2_fast = 10 },
267
        .find_pll = intel_find_pll_g4x_dp,
268
};
269
 
270
static const intel_limit_t intel_limits_pineview_sdvo = {
271
        .dot = { .min = 20000, .max = 400000},
272
        .vco = { .min = 1700000, .max = 3500000 },
273
	/* Pineview's Ncounter is a ring counter */
274
        .n = { .min = 3, .max = 6 },
275
        .m = { .min = 2, .max = 256 },
276
	/* Pineview only has one combined m divider, which we treat as m2. */
277
        .m1 = { .min = 0, .max = 0 },
278
        .m2 = { .min = 0, .max = 254 },
279
        .p = { .min = 5, .max = 80 },
280
        .p1 = { .min = 1, .max = 8 },
281
	.p2 = { .dot_limit = 200000,
282
		.p2_slow = 10, .p2_fast = 5 },
283
	.find_pll = intel_find_best_PLL,
284
};
285
 
286
static const intel_limit_t intel_limits_pineview_lvds = {
287
        .dot = { .min = 20000, .max = 400000 },
288
        .vco = { .min = 1700000, .max = 3500000 },
289
        .n = { .min = 3, .max = 6 },
290
        .m = { .min = 2, .max = 256 },
291
        .m1 = { .min = 0, .max = 0 },
292
        .m2 = { .min = 0, .max = 254 },
293
        .p = { .min = 7, .max = 112 },
294
        .p1 = { .min = 1, .max = 8 },
295
	.p2 = { .dot_limit = 112000,
296
		.p2_slow = 14, .p2_fast = 14 },
297
	.find_pll = intel_find_best_PLL,
298
};
299
 
300
/* Ironlake / Sandybridge
301
 *
302
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303
 * the range value for them is (actual_value - 2).
304
 */
305
static const intel_limit_t intel_limits_ironlake_dac = {
306
	.dot = { .min = 25000, .max = 350000 },
307
	.vco = { .min = 1760000, .max = 3510000 },
308
	.n = { .min = 1, .max = 5 },
309
	.m = { .min = 79, .max = 127 },
310
	.m1 = { .min = 12, .max = 22 },
311
	.m2 = { .min = 5, .max = 9 },
312
	.p = { .min = 5, .max = 80 },
313
	.p1 = { .min = 1, .max = 8 },
314
	.p2 = { .dot_limit = 225000,
315
		.p2_slow = 10, .p2_fast = 5 },
316
	.find_pll = intel_g4x_find_best_PLL,
317
};
318
 
319
static const intel_limit_t intel_limits_ironlake_single_lvds = {
320
	.dot = { .min = 25000, .max = 350000 },
321
	.vco = { .min = 1760000, .max = 3510000 },
322
	.n = { .min = 1, .max = 3 },
323
	.m = { .min = 79, .max = 118 },
324
	.m1 = { .min = 12, .max = 22 },
325
	.m2 = { .min = 5, .max = 9 },
326
	.p = { .min = 28, .max = 112 },
327
	.p1 = { .min = 2, .max = 8 },
328
	.p2 = { .dot_limit = 225000,
329
		.p2_slow = 14, .p2_fast = 14 },
330
	.find_pll = intel_g4x_find_best_PLL,
331
};
332
 
333
static const intel_limit_t intel_limits_ironlake_dual_lvds = {
334
	.dot = { .min = 25000, .max = 350000 },
335
	.vco = { .min = 1760000, .max = 3510000 },
336
	.n = { .min = 1, .max = 3 },
337
	.m = { .min = 79, .max = 127 },
338
	.m1 = { .min = 12, .max = 22 },
339
	.m2 = { .min = 5, .max = 9 },
340
	.p = { .min = 14, .max = 56 },
341
	.p1 = { .min = 2, .max = 8 },
342
	.p2 = { .dot_limit = 225000,
343
		.p2_slow = 7, .p2_fast = 7 },
344
	.find_pll = intel_g4x_find_best_PLL,
345
};
346
 
347
/* LVDS 100mhz refclk limits. */
348
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
349
	.dot = { .min = 25000, .max = 350000 },
350
	.vco = { .min = 1760000, .max = 3510000 },
351
	.n = { .min = 1, .max = 2 },
352
	.m = { .min = 79, .max = 126 },
353
	.m1 = { .min = 12, .max = 22 },
354
	.m2 = { .min = 5, .max = 9 },
355
	.p = { .min = 28, .max = 112 },
2342 Serge 356
	.p1 = { .min = 2, .max = 8 },
2327 Serge 357
	.p2 = { .dot_limit = 225000,
358
		.p2_slow = 14, .p2_fast = 14 },
359
	.find_pll = intel_g4x_find_best_PLL,
360
};
361
 
362
static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
363
	.dot = { .min = 25000, .max = 350000 },
364
	.vco = { .min = 1760000, .max = 3510000 },
365
	.n = { .min = 1, .max = 3 },
366
	.m = { .min = 79, .max = 126 },
367
	.m1 = { .min = 12, .max = 22 },
368
	.m2 = { .min = 5, .max = 9 },
369
	.p = { .min = 14, .max = 42 },
2342 Serge 370
	.p1 = { .min = 2, .max = 6 },
2327 Serge 371
	.p2 = { .dot_limit = 225000,
372
		.p2_slow = 7, .p2_fast = 7 },
373
	.find_pll = intel_g4x_find_best_PLL,
374
};
375
 
376
static const intel_limit_t intel_limits_ironlake_display_port = {
377
        .dot = { .min = 25000, .max = 350000 },
378
        .vco = { .min = 1760000, .max = 3510000},
379
        .n = { .min = 1, .max = 2 },
380
        .m = { .min = 81, .max = 90 },
381
        .m1 = { .min = 12, .max = 22 },
382
        .m2 = { .min = 5, .max = 9 },
383
        .p = { .min = 10, .max = 20 },
384
        .p1 = { .min = 1, .max = 2},
385
        .p2 = { .dot_limit = 0,
386
		.p2_slow = 10, .p2_fast = 10 },
387
        .find_pll = intel_find_pll_ironlake_dp,
388
};
389
 
390
static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
391
						int refclk)
392
{
393
	struct drm_device *dev = crtc->dev;
394
	struct drm_i915_private *dev_priv = dev->dev_private;
395
	const intel_limit_t *limit;
396
 
397
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
398
		if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
399
		    LVDS_CLKB_POWER_UP) {
400
			/* LVDS dual channel */
401
			if (refclk == 100000)
402
				limit = &intel_limits_ironlake_dual_lvds_100m;
403
			else
404
				limit = &intel_limits_ironlake_dual_lvds;
405
		} else {
406
			if (refclk == 100000)
407
				limit = &intel_limits_ironlake_single_lvds_100m;
408
			else
409
				limit = &intel_limits_ironlake_single_lvds;
410
		}
411
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
412
			HAS_eDP)
413
		limit = &intel_limits_ironlake_display_port;
414
	else
415
		limit = &intel_limits_ironlake_dac;
416
 
417
	return limit;
418
}
419
 
420
static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
421
{
422
	struct drm_device *dev = crtc->dev;
423
	struct drm_i915_private *dev_priv = dev->dev_private;
424
	const intel_limit_t *limit;
425
 
426
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
427
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
428
		    LVDS_CLKB_POWER_UP)
429
			/* LVDS with dual channel */
430
			limit = &intel_limits_g4x_dual_channel_lvds;
431
		else
432
			/* LVDS with dual channel */
433
			limit = &intel_limits_g4x_single_channel_lvds;
434
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
435
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
436
		limit = &intel_limits_g4x_hdmi;
437
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
438
		limit = &intel_limits_g4x_sdvo;
2342 Serge 439
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2327 Serge 440
		limit = &intel_limits_g4x_display_port;
441
	} else /* The option is for other outputs */
442
		limit = &intel_limits_i9xx_sdvo;
443
 
444
	return limit;
445
}
446
 
447
static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
448
{
449
	struct drm_device *dev = crtc->dev;
450
	const intel_limit_t *limit;
451
 
452
	if (HAS_PCH_SPLIT(dev))
453
		limit = intel_ironlake_limit(crtc, refclk);
454
	else if (IS_G4X(dev)) {
455
		limit = intel_g4x_limit(crtc);
456
	} else if (IS_PINEVIEW(dev)) {
457
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
458
			limit = &intel_limits_pineview_lvds;
459
		else
460
			limit = &intel_limits_pineview_sdvo;
461
	} else if (!IS_GEN2(dev)) {
462
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
463
			limit = &intel_limits_i9xx_lvds;
464
		else
465
			limit = &intel_limits_i9xx_sdvo;
466
	} else {
467
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
468
			limit = &intel_limits_i8xx_lvds;
469
		else
470
			limit = &intel_limits_i8xx_dvo;
471
	}
472
	return limit;
473
}
474
 
475
/* m1 is reserved as 0 in Pineview, n is a ring counter */
476
static void pineview_clock(int refclk, intel_clock_t *clock)
477
{
478
	clock->m = clock->m2 + 2;
479
	clock->p = clock->p1 * clock->p2;
480
	clock->vco = refclk * clock->m / clock->n;
481
	clock->dot = clock->vco / clock->p;
482
}
483
 
484
static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
485
{
486
	if (IS_PINEVIEW(dev)) {
487
		pineview_clock(refclk, clock);
488
		return;
489
	}
490
	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
491
	clock->p = clock->p1 * clock->p2;
492
	clock->vco = refclk * clock->m / (clock->n + 2);
493
	clock->dot = clock->vco / clock->p;
494
}
495
 
496
/**
497
 * Returns whether any output on the specified pipe is of the specified type
498
 */
499
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
500
{
501
	struct drm_device *dev = crtc->dev;
502
	struct drm_mode_config *mode_config = &dev->mode_config;
503
	struct intel_encoder *encoder;
504
 
505
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
506
		if (encoder->base.crtc == crtc && encoder->type == type)
507
			return true;
508
 
509
	return false;
510
}
511
 
512
#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
513
/**
514
 * Returns whether the given set of divisors are valid for a given refclk with
515
 * the given connectors.
516
 */
517
 
518
static bool intel_PLL_is_valid(struct drm_device *dev,
519
			       const intel_limit_t *limit,
520
			       const intel_clock_t *clock)
521
{
522
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
2342 Serge 523
		INTELPllInvalid("p1 out of range\n");
2327 Serge 524
	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
2342 Serge 525
		INTELPllInvalid("p out of range\n");
2327 Serge 526
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
2342 Serge 527
		INTELPllInvalid("m2 out of range\n");
2327 Serge 528
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
2342 Serge 529
		INTELPllInvalid("m1 out of range\n");
2327 Serge 530
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
2342 Serge 531
		INTELPllInvalid("m1 <= m2\n");
2327 Serge 532
	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
2342 Serge 533
		INTELPllInvalid("m out of range\n");
2327 Serge 534
	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
2342 Serge 535
		INTELPllInvalid("n out of range\n");
2327 Serge 536
	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
2342 Serge 537
		INTELPllInvalid("vco out of range\n");
2327 Serge 538
	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
539
	 * connector, etc., rather than just a single range.
540
	 */
541
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
2342 Serge 542
		INTELPllInvalid("dot out of range\n");
2327 Serge 543
 
544
	return true;
545
}
546
 
547
static bool
548
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
549
		    int target, int refclk, intel_clock_t *best_clock)
550
 
551
{
552
	struct drm_device *dev = crtc->dev;
553
	struct drm_i915_private *dev_priv = dev->dev_private;
554
	intel_clock_t clock;
555
	int err = target;
556
 
557
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
558
	    (I915_READ(LVDS)) != 0) {
559
		/*
560
		 * For LVDS, if the panel is on, just rely on its current
561
		 * settings for dual-channel.  We haven't figured out how to
562
		 * reliably set up different single/dual channel state, if we
563
		 * even can.
564
		 */
565
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
566
		    LVDS_CLKB_POWER_UP)
567
			clock.p2 = limit->p2.p2_fast;
568
		else
569
			clock.p2 = limit->p2.p2_slow;
570
	} else {
571
		if (target < limit->p2.dot_limit)
572
			clock.p2 = limit->p2.p2_slow;
573
		else
574
			clock.p2 = limit->p2.p2_fast;
575
	}
576
 
2342 Serge 577
	memset(best_clock, 0, sizeof(*best_clock));
2327 Serge 578
 
579
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580
	     clock.m1++) {
581
		for (clock.m2 = limit->m2.min;
582
		     clock.m2 <= limit->m2.max; clock.m2++) {
583
			/* m1 is always 0 in Pineview */
584
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
585
				break;
586
			for (clock.n = limit->n.min;
587
			     clock.n <= limit->n.max; clock.n++) {
588
				for (clock.p1 = limit->p1.min;
589
					clock.p1 <= limit->p1.max; clock.p1++) {
590
					int this_err;
591
 
592
					intel_clock(dev, refclk, &clock);
593
					if (!intel_PLL_is_valid(dev, limit,
594
								&clock))
595
						continue;
596
 
597
					this_err = abs(clock.dot - target);
598
					if (this_err < err) {
599
						*best_clock = clock;
600
						err = this_err;
601
					}
602
				}
603
			}
604
		}
605
	}
606
 
607
	return (err != target);
608
}
609
 
610
static bool
611
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
612
			int target, int refclk, intel_clock_t *best_clock)
613
{
614
	struct drm_device *dev = crtc->dev;
615
	struct drm_i915_private *dev_priv = dev->dev_private;
616
	intel_clock_t clock;
617
	int max_n;
618
	bool found;
619
	/* approximately equals target * 0.00585 */
620
	int err_most = (target >> 8) + (target >> 9);
621
	found = false;
622
 
623
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
624
		int lvds_reg;
625
 
626
		if (HAS_PCH_SPLIT(dev))
627
			lvds_reg = PCH_LVDS;
628
		else
629
			lvds_reg = LVDS;
630
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
631
		    LVDS_CLKB_POWER_UP)
632
			clock.p2 = limit->p2.p2_fast;
633
		else
634
			clock.p2 = limit->p2.p2_slow;
635
	} else {
636
		if (target < limit->p2.dot_limit)
637
			clock.p2 = limit->p2.p2_slow;
638
		else
639
			clock.p2 = limit->p2.p2_fast;
640
	}
641
 
642
	memset(best_clock, 0, sizeof(*best_clock));
643
	max_n = limit->n.max;
644
	/* based on hardware requirement, prefer smaller n to precision */
645
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646
		/* based on hardware requirement, prefere larger m1,m2 */
647
		for (clock.m1 = limit->m1.max;
648
		     clock.m1 >= limit->m1.min; clock.m1--) {
649
			for (clock.m2 = limit->m2.max;
650
			     clock.m2 >= limit->m2.min; clock.m2--) {
651
				for (clock.p1 = limit->p1.max;
652
				     clock.p1 >= limit->p1.min; clock.p1--) {
653
					int this_err;
654
 
655
					intel_clock(dev, refclk, &clock);
656
					if (!intel_PLL_is_valid(dev, limit,
657
								&clock))
658
						continue;
659
 
660
					this_err = abs(clock.dot - target);
661
					if (this_err < err_most) {
662
						*best_clock = clock;
663
						err_most = this_err;
664
						max_n = clock.n;
665
						found = true;
666
					}
667
				}
668
			}
669
		}
670
	}
671
	return found;
672
}
673
 
674
static bool
675
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
676
			   int target, int refclk, intel_clock_t *best_clock)
677
{
678
	struct drm_device *dev = crtc->dev;
679
	intel_clock_t clock;
680
 
681
	if (target < 200000) {
682
		clock.n = 1;
683
		clock.p1 = 2;
684
		clock.p2 = 10;
685
		clock.m1 = 12;
686
		clock.m2 = 9;
687
	} else {
688
		clock.n = 2;
689
		clock.p1 = 1;
690
		clock.p2 = 10;
691
		clock.m1 = 14;
692
		clock.m2 = 8;
693
	}
694
	intel_clock(dev, refclk, &clock);
695
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
696
	return true;
697
}
698
 
699
/* DisplayPort has only two frequencies, 162MHz and 270MHz */
700
static bool
701
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
702
		      int target, int refclk, intel_clock_t *best_clock)
703
{
704
	intel_clock_t clock;
705
	if (target < 200000) {
706
		clock.p1 = 2;
707
		clock.p2 = 10;
708
		clock.n = 2;
709
		clock.m1 = 23;
710
		clock.m2 = 8;
711
	} else {
712
		clock.p1 = 1;
713
		clock.p2 = 10;
714
		clock.n = 1;
715
		clock.m1 = 14;
716
		clock.m2 = 2;
717
	}
718
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
719
	clock.p = (clock.p1 * clock.p2);
720
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
721
	clock.vco = 0;
722
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
723
	return true;
724
}
725
 
726
/**
727
 * intel_wait_for_vblank - wait for vblank on a given pipe
728
 * @dev: drm device
729
 * @pipe: pipe to wait for
730
 *
731
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
732
 * mode setting code.
733
 */
734
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
735
{
736
	struct drm_i915_private *dev_priv = dev->dev_private;
737
	int pipestat_reg = PIPESTAT(pipe);
738
 
739
	/* Clear existing vblank status. Note this will clear any other
740
	 * sticky status fields as well.
741
	 *
742
	 * This races with i915_driver_irq_handler() with the result
743
	 * that either function could miss a vblank event.  Here it is not
744
	 * fatal, as we will either wait upon the next vblank interrupt or
745
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
746
	 * called during modeset at which time the GPU should be idle and
747
	 * should *not* be performing page flips and thus not waiting on
748
	 * vblanks...
749
	 * Currently, the result of us stealing a vblank from the irq
750
	 * handler is that a single frame will be skipped during swapbuffers.
751
	 */
752
	I915_WRITE(pipestat_reg,
753
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
754
 
755
	/* Wait for vblank interrupt bit to set */
756
	if (wait_for(I915_READ(pipestat_reg) &
757
		     PIPE_VBLANK_INTERRUPT_STATUS,
758
		     50))
759
		DRM_DEBUG_KMS("vblank wait timed out\n");
760
}
761
 
762
/*
763
 * intel_wait_for_pipe_off - wait for pipe to turn off
764
 * @dev: drm device
765
 * @pipe: pipe to wait for
766
 *
767
 * After disabling a pipe, we can't wait for vblank in the usual way,
768
 * spinning on the vblank interrupt status bit, since we won't actually
769
 * see an interrupt when the pipe is disabled.
770
 *
771
 * On Gen4 and above:
772
 *   wait for the pipe register state bit to turn off
773
 *
774
 * Otherwise:
775
 *   wait for the display line value to settle (it usually
776
 *   ends up stopping at the start of the next frame).
777
 *
778
 */
779
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
780
{
781
	struct drm_i915_private *dev_priv = dev->dev_private;
782
 
783
	if (INTEL_INFO(dev)->gen >= 4) {
784
		int reg = PIPECONF(pipe);
785
 
786
		/* Wait for the Pipe State to go off */
787
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
788
			     100))
789
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
790
	} else {
791
		u32 last_line;
792
		int reg = PIPEDSL(pipe);
793
		unsigned long timeout = jiffies + msecs_to_jiffies(100);
794
 
795
		/* Wait for the display line to settle */
796
		do {
797
			last_line = I915_READ(reg) & DSL_LINEMASK;
798
			mdelay(5);
799
		} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
800
			 time_after(timeout, jiffies));
801
		if (time_after(jiffies, timeout))
802
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
803
	}
804
}
805
 
806
static const char *state_string(bool enabled)
807
{
808
	return enabled ? "on" : "off";
809
}
810
 
811
/* Only for pre-ILK configs */
812
static void assert_pll(struct drm_i915_private *dev_priv,
813
		       enum pipe pipe, bool state)
814
{
815
	int reg;
816
	u32 val;
817
	bool cur_state;
818
 
819
	reg = DPLL(pipe);
820
	val = I915_READ(reg);
821
	cur_state = !!(val & DPLL_VCO_ENABLE);
822
	WARN(cur_state != state,
823
	     "PLL state assertion failure (expected %s, current %s)\n",
824
	     state_string(state), state_string(cur_state));
825
}
826
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
827
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
828
 
829
/* For ILK+ */
830
static void assert_pch_pll(struct drm_i915_private *dev_priv,
831
			   enum pipe pipe, bool state)
832
{
833
	int reg;
834
	u32 val;
835
	bool cur_state;
836
 
2342 Serge 837
	if (HAS_PCH_CPT(dev_priv->dev)) {
838
		u32 pch_dpll;
839
 
840
		pch_dpll = I915_READ(PCH_DPLL_SEL);
841
 
842
		/* Make sure the selected PLL is enabled to the transcoder */
843
		WARN(!((pch_dpll >> (4 * pipe)) & 8),
844
		     "transcoder %d PLL not enabled\n", pipe);
845
 
846
		/* Convert the transcoder pipe number to a pll pipe number */
847
		pipe = (pch_dpll >> (4 * pipe)) & 1;
848
	}
849
 
2327 Serge 850
	reg = PCH_DPLL(pipe);
851
	val = I915_READ(reg);
852
	cur_state = !!(val & DPLL_VCO_ENABLE);
853
	WARN(cur_state != state,
854
	     "PCH PLL state assertion failure (expected %s, current %s)\n",
855
	     state_string(state), state_string(cur_state));
856
}
857
#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
858
#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
859
 
860
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
861
			  enum pipe pipe, bool state)
862
{
863
	int reg;
864
	u32 val;
865
	bool cur_state;
866
 
867
	reg = FDI_TX_CTL(pipe);
868
	val = I915_READ(reg);
869
	cur_state = !!(val & FDI_TX_ENABLE);
870
	WARN(cur_state != state,
871
	     "FDI TX state assertion failure (expected %s, current %s)\n",
872
	     state_string(state), state_string(cur_state));
873
}
874
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
875
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
876
 
877
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
878
			  enum pipe pipe, bool state)
879
{
880
	int reg;
881
	u32 val;
882
	bool cur_state;
883
 
884
	reg = FDI_RX_CTL(pipe);
885
	val = I915_READ(reg);
886
	cur_state = !!(val & FDI_RX_ENABLE);
887
	WARN(cur_state != state,
888
	     "FDI RX state assertion failure (expected %s, current %s)\n",
889
	     state_string(state), state_string(cur_state));
890
}
891
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
892
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
893
 
894
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
895
				      enum pipe pipe)
896
{
897
	int reg;
898
	u32 val;
899
 
900
	/* ILK FDI PLL is always enabled */
901
	if (dev_priv->info->gen == 5)
902
		return;
903
 
904
	reg = FDI_TX_CTL(pipe);
905
	val = I915_READ(reg);
906
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
907
}
908
 
909
static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
910
				      enum pipe pipe)
911
{
912
	int reg;
913
	u32 val;
914
 
915
	reg = FDI_RX_CTL(pipe);
916
	val = I915_READ(reg);
917
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
918
}
919
 
920
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
921
				  enum pipe pipe)
922
{
923
	int pp_reg, lvds_reg;
924
	u32 val;
925
	enum pipe panel_pipe = PIPE_A;
926
	bool locked = true;
927
 
928
	if (HAS_PCH_SPLIT(dev_priv->dev)) {
929
		pp_reg = PCH_PP_CONTROL;
930
		lvds_reg = PCH_LVDS;
931
	} else {
932
		pp_reg = PP_CONTROL;
933
		lvds_reg = LVDS;
934
	}
935
 
936
	val = I915_READ(pp_reg);
937
	if (!(val & PANEL_POWER_ON) ||
938
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
939
		locked = false;
940
 
941
	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
942
		panel_pipe = PIPE_B;
943
 
944
	WARN(panel_pipe == pipe && locked,
945
	     "panel assertion failure, pipe %c regs locked\n",
946
	     pipe_name(pipe));
947
}
948
 
2342 Serge 949
void assert_pipe(struct drm_i915_private *dev_priv,
2327 Serge 950
			enum pipe pipe, bool state)
951
{
952
	int reg;
953
	u32 val;
954
	bool cur_state;
955
 
956
	reg = PIPECONF(pipe);
957
	val = I915_READ(reg);
958
	cur_state = !!(val & PIPECONF_ENABLE);
959
	WARN(cur_state != state,
960
	     "pipe %c assertion failure (expected %s, current %s)\n",
961
	     pipe_name(pipe), state_string(state), state_string(cur_state));
962
}
963
 
964
static void assert_plane_enabled(struct drm_i915_private *dev_priv,
965
				 enum plane plane)
966
{
967
	int reg;
968
	u32 val;
969
 
970
	reg = DSPCNTR(plane);
971
	val = I915_READ(reg);
972
	WARN(!(val & DISPLAY_PLANE_ENABLE),
973
	     "plane %c assertion failure, should be active but is disabled\n",
974
	     plane_name(plane));
975
}
976
 
977
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
978
				   enum pipe pipe)
979
{
980
	int reg, i;
981
	u32 val;
982
	int cur_pipe;
983
 
984
	/* Planes are fixed to pipes on ILK+ */
985
	if (HAS_PCH_SPLIT(dev_priv->dev))
986
		return;
987
 
988
	/* Need to check both planes against the pipe */
989
	for (i = 0; i < 2; i++) {
990
		reg = DSPCNTR(i);
991
		val = I915_READ(reg);
992
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
993
			DISPPLANE_SEL_PIPE_SHIFT;
994
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
995
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
996
		     plane_name(i), pipe_name(pipe));
997
	}
998
}
999
 
1000
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1001
{
1002
	u32 val;
1003
	bool enabled;
1004
 
1005
	val = I915_READ(PCH_DREF_CONTROL);
1006
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1007
			    DREF_SUPERSPREAD_SOURCE_MASK));
1008
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1009
}
1010
 
1011
static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1012
				       enum pipe pipe)
1013
{
1014
	int reg;
1015
	u32 val;
1016
	bool enabled;
1017
 
1018
	reg = TRANSCONF(pipe);
1019
	val = I915_READ(reg);
1020
	enabled = !!(val & TRANS_ENABLE);
1021
	WARN(enabled,
1022
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
1023
	     pipe_name(pipe));
1024
}
1025
 
1026
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1027
			    enum pipe pipe, u32 port_sel, u32 val)
1028
{
1029
	if ((val & DP_PORT_EN) == 0)
1030
		return false;
1031
 
1032
	if (HAS_PCH_CPT(dev_priv->dev)) {
1033
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1034
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1035
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1036
			return false;
1037
	} else {
1038
		if ((val & DP_PIPE_MASK) != (pipe << 30))
1039
			return false;
1040
	}
1041
	return true;
1042
}
1043
 
1044
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1045
			      enum pipe pipe, u32 val)
1046
{
1047
	if ((val & PORT_ENABLE) == 0)
1048
		return false;
1049
 
1050
	if (HAS_PCH_CPT(dev_priv->dev)) {
1051
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1052
			return false;
1053
	} else {
1054
		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1055
			return false;
1056
	}
1057
	return true;
1058
}
1059
 
1060
static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1061
			      enum pipe pipe, u32 val)
1062
{
1063
	if ((val & LVDS_PORT_EN) == 0)
1064
		return false;
1065
 
1066
	if (HAS_PCH_CPT(dev_priv->dev)) {
1067
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1068
			return false;
1069
	} else {
1070
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1071
			return false;
1072
	}
1073
	return true;
1074
}
1075
 
1076
static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1077
			      enum pipe pipe, u32 val)
1078
{
1079
	if ((val & ADPA_DAC_ENABLE) == 0)
1080
		return false;
1081
	if (HAS_PCH_CPT(dev_priv->dev)) {
1082
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1083
			return false;
1084
	} else {
1085
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1086
			return false;
1087
	}
1088
	return true;
1089
}
1090
 
1091
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1092
				   enum pipe pipe, int reg, u32 port_sel)
1093
{
1094
	u32 val = I915_READ(reg);
1095
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1096
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1097
	     reg, pipe_name(pipe));
1098
}
1099
 
1100
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1101
				     enum pipe pipe, int reg)
1102
{
1103
	u32 val = I915_READ(reg);
1104
	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1105
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1106
	     reg, pipe_name(pipe));
1107
}
1108
 
1109
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1110
				      enum pipe pipe)
1111
{
1112
	int reg;
1113
	u32 val;
1114
 
1115
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1116
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1117
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1118
 
1119
	reg = PCH_ADPA;
1120
	val = I915_READ(reg);
1121
	WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1122
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1123
	     pipe_name(pipe));
1124
 
1125
	reg = PCH_LVDS;
1126
	val = I915_READ(reg);
1127
	WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1128
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1129
	     pipe_name(pipe));
1130
 
1131
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1132
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1133
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1134
}
1135
 
1136
/**
1137
 * intel_enable_pll - enable a PLL
1138
 * @dev_priv: i915 private structure
1139
 * @pipe: pipe PLL to enable
1140
 *
1141
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1142
 * make sure the PLL reg is writable first though, since the panel write
1143
 * protect mechanism may be enabled.
1144
 *
1145
 * Note!  This is for pre-ILK only.
1146
 */
1147
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1148
{
1149
    int reg;
1150
    u32 val;
1151
 
1152
    /* No really, not for ILK+ */
1153
    BUG_ON(dev_priv->info->gen >= 5);
1154
 
1155
    /* PLL is protected by panel, make sure we can write it */
1156
    if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1157
        assert_panel_unlocked(dev_priv, pipe);
1158
 
1159
    reg = DPLL(pipe);
1160
    val = I915_READ(reg);
1161
    val |= DPLL_VCO_ENABLE;
1162
 
1163
    /* We do this three times for luck */
1164
    I915_WRITE(reg, val);
1165
    POSTING_READ(reg);
1166
    udelay(150); /* wait for warmup */
1167
    I915_WRITE(reg, val);
1168
    POSTING_READ(reg);
1169
    udelay(150); /* wait for warmup */
1170
    I915_WRITE(reg, val);
1171
    POSTING_READ(reg);
1172
    udelay(150); /* wait for warmup */
1173
}
1174
 
1175
/**
1176
 * intel_disable_pll - disable a PLL
1177
 * @dev_priv: i915 private structure
1178
 * @pipe: pipe PLL to disable
1179
 *
1180
 * Disable the PLL for @pipe, making sure the pipe is off first.
1181
 *
1182
 * Note!  This is for pre-ILK only.
1183
 */
1184
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1185
{
1186
	int reg;
1187
	u32 val;
1188
 
1189
	/* Don't disable pipe A or pipe A PLLs if needed */
1190
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1191
		return;
1192
 
1193
	/* Make sure the pipe isn't still relying on us */
1194
	assert_pipe_disabled(dev_priv, pipe);
1195
 
1196
	reg = DPLL(pipe);
1197
	val = I915_READ(reg);
1198
	val &= ~DPLL_VCO_ENABLE;
1199
	I915_WRITE(reg, val);
1200
	POSTING_READ(reg);
1201
}
1202
 
1203
/**
1204
 * intel_enable_pch_pll - enable PCH PLL
1205
 * @dev_priv: i915 private structure
1206
 * @pipe: pipe PLL to enable
1207
 *
1208
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1209
 * drives the transcoder clock.
1210
 */
1211
static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1212
				 enum pipe pipe)
1213
{
1214
	int reg;
1215
	u32 val;
1216
 
2342 Serge 1217
	if (pipe > 1)
1218
		return;
1219
 
2327 Serge 1220
	/* PCH only available on ILK+ */
1221
	BUG_ON(dev_priv->info->gen < 5);
1222
 
1223
	/* PCH refclock must be enabled first */
1224
	assert_pch_refclk_enabled(dev_priv);
1225
 
1226
	reg = PCH_DPLL(pipe);
1227
	val = I915_READ(reg);
1228
	val |= DPLL_VCO_ENABLE;
1229
	I915_WRITE(reg, val);
1230
	POSTING_READ(reg);
1231
	udelay(200);
1232
}
1233
 
1234
static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1235
				  enum pipe pipe)
1236
{
1237
	int reg;
2342 Serge 1238
	u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1239
		pll_sel = TRANSC_DPLL_ENABLE;
2327 Serge 1240
 
2342 Serge 1241
	if (pipe > 1)
1242
		return;
1243
 
2327 Serge 1244
	/* PCH only available on ILK+ */
1245
	BUG_ON(dev_priv->info->gen < 5);
1246
 
1247
	/* Make sure transcoder isn't still depending on us */
1248
	assert_transcoder_disabled(dev_priv, pipe);
1249
 
2342 Serge 1250
	if (pipe == 0)
1251
		pll_sel |= TRANSC_DPLLA_SEL;
1252
	else if (pipe == 1)
1253
		pll_sel |= TRANSC_DPLLB_SEL;
1254
 
1255
 
1256
	if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1257
		return;
1258
 
2327 Serge 1259
	reg = PCH_DPLL(pipe);
1260
	val = I915_READ(reg);
1261
	val &= ~DPLL_VCO_ENABLE;
1262
	I915_WRITE(reg, val);
1263
	POSTING_READ(reg);
1264
	udelay(200);
1265
}
1266
 
1267
static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1268
				    enum pipe pipe)
1269
{
1270
	int reg;
1271
	u32 val;
1272
 
1273
	/* PCH only available on ILK+ */
1274
	BUG_ON(dev_priv->info->gen < 5);
1275
 
1276
	/* Make sure PCH DPLL is enabled */
1277
	assert_pch_pll_enabled(dev_priv, pipe);
1278
 
1279
	/* FDI must be feeding us bits for PCH ports */
1280
	assert_fdi_tx_enabled(dev_priv, pipe);
1281
	assert_fdi_rx_enabled(dev_priv, pipe);
1282
 
1283
	reg = TRANSCONF(pipe);
1284
	val = I915_READ(reg);
1285
 
1286
	if (HAS_PCH_IBX(dev_priv->dev)) {
1287
		/*
1288
		 * make the BPC in transcoder be consistent with
1289
		 * that in pipeconf reg.
1290
		 */
1291
		val &= ~PIPE_BPC_MASK;
1292
		val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1293
	}
1294
	I915_WRITE(reg, val | TRANS_ENABLE);
1295
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1296
		DRM_ERROR("failed to enable transcoder %d\n", pipe);
1297
}
1298
 
1299
static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1300
				     enum pipe pipe)
1301
{
1302
	int reg;
1303
	u32 val;
1304
 
1305
	/* FDI relies on the transcoder */
1306
	assert_fdi_tx_disabled(dev_priv, pipe);
1307
	assert_fdi_rx_disabled(dev_priv, pipe);
1308
 
1309
	/* Ports must be off as well */
1310
	assert_pch_ports_disabled(dev_priv, pipe);
1311
 
1312
	reg = TRANSCONF(pipe);
1313
	val = I915_READ(reg);
1314
	val &= ~TRANS_ENABLE;
1315
	I915_WRITE(reg, val);
1316
	/* wait for PCH transcoder off, transcoder state */
1317
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2342 Serge 1318
		DRM_ERROR("failed to disable transcoder %d\n", pipe);
2327 Serge 1319
}
1320
 
1321
/**
1322
 * intel_enable_pipe - enable a pipe, asserting requirements
1323
 * @dev_priv: i915 private structure
1324
 * @pipe: pipe to enable
1325
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1326
 *
1327
 * Enable @pipe, making sure that various hardware specific requirements
1328
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1329
 *
1330
 * @pipe should be %PIPE_A or %PIPE_B.
1331
 *
1332
 * Will wait until the pipe is actually running (i.e. first vblank) before
1333
 * returning.
1334
 */
1335
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1336
			      bool pch_port)
1337
{
1338
	int reg;
1339
	u32 val;
1340
 
1341
	/*
1342
	 * A pipe without a PLL won't actually be able to drive bits from
1343
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1344
	 * need the check.
1345
	 */
1346
	if (!HAS_PCH_SPLIT(dev_priv->dev))
1347
		assert_pll_enabled(dev_priv, pipe);
1348
	else {
1349
		if (pch_port) {
1350
			/* if driving the PCH, we need FDI enabled */
1351
			assert_fdi_rx_pll_enabled(dev_priv, pipe);
1352
			assert_fdi_tx_pll_enabled(dev_priv, pipe);
1353
		}
1354
		/* FIXME: assert CPU port conditions for SNB+ */
1355
	}
1356
 
1357
	reg = PIPECONF(pipe);
1358
	val = I915_READ(reg);
1359
	if (val & PIPECONF_ENABLE)
1360
		return;
1361
 
1362
	I915_WRITE(reg, val | PIPECONF_ENABLE);
1363
	intel_wait_for_vblank(dev_priv->dev, pipe);
1364
}
1365
 
1366
/**
1367
 * intel_disable_pipe - disable a pipe, asserting requirements
1368
 * @dev_priv: i915 private structure
1369
 * @pipe: pipe to disable
1370
 *
1371
 * Disable @pipe, making sure that various hardware specific requirements
1372
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1373
 *
1374
 * @pipe should be %PIPE_A or %PIPE_B.
1375
 *
1376
 * Will wait until the pipe has shut down before returning.
1377
 */
1378
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1379
			       enum pipe pipe)
1380
{
1381
	int reg;
1382
	u32 val;
1383
 
1384
	/*
1385
	 * Make sure planes won't keep trying to pump pixels to us,
1386
	 * or we might hang the display.
1387
	 */
1388
	assert_planes_disabled(dev_priv, pipe);
1389
 
1390
	/* Don't disable pipe A or pipe A PLLs if needed */
1391
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1392
		return;
1393
 
1394
	reg = PIPECONF(pipe);
1395
	val = I915_READ(reg);
1396
	if ((val & PIPECONF_ENABLE) == 0)
1397
		return;
1398
 
1399
	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1400
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
1401
}
1402
 
1403
/*
1404
 * Plane regs are double buffered, going from enabled->disabled needs a
1405
 * trigger in order to latch.  The display address reg provides this.
1406
 */
1407
static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1408
				      enum plane plane)
1409
{
1410
	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1411
	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1412
}
1413
 
1414
/**
1415
 * intel_enable_plane - enable a display plane on a given pipe
1416
 * @dev_priv: i915 private structure
1417
 * @plane: plane to enable
1418
 * @pipe: pipe being fed
1419
 *
1420
 * Enable @plane on @pipe, making sure that @pipe is running first.
1421
 */
1422
static void intel_enable_plane(struct drm_i915_private *dev_priv,
1423
			       enum plane plane, enum pipe pipe)
1424
{
1425
	int reg;
1426
	u32 val;
1427
 
1428
	/* If the pipe isn't enabled, we can't pump pixels and may hang */
1429
	assert_pipe_enabled(dev_priv, pipe);
1430
 
1431
	reg = DSPCNTR(plane);
1432
	val = I915_READ(reg);
1433
	if (val & DISPLAY_PLANE_ENABLE)
1434
		return;
1435
 
1436
	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1437
	intel_flush_display_plane(dev_priv, plane);
1438
	intel_wait_for_vblank(dev_priv->dev, pipe);
1439
}
1440
 
1441
/**
1442
 * intel_disable_plane - disable a display plane
1443
 * @dev_priv: i915 private structure
1444
 * @plane: plane to disable
1445
 * @pipe: pipe consuming the data
1446
 *
1447
 * Disable @plane; should be an independent operation.
1448
 */
1449
static void intel_disable_plane(struct drm_i915_private *dev_priv,
1450
				enum plane plane, enum pipe pipe)
1451
{
1452
	int reg;
1453
	u32 val;
1454
 
1455
	reg = DSPCNTR(plane);
1456
	val = I915_READ(reg);
1457
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
1458
		return;
1459
 
1460
	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1461
	intel_flush_display_plane(dev_priv, plane);
1462
	intel_wait_for_vblank(dev_priv->dev, pipe);
1463
}
1464
 
1465
static void disable_pch_dp(struct drm_i915_private *dev_priv,
1466
			   enum pipe pipe, int reg, u32 port_sel)
1467
{
1468
	u32 val = I915_READ(reg);
1469
	if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1470
		DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1471
		I915_WRITE(reg, val & ~DP_PORT_EN);
1472
	}
1473
}
1474
 
1475
static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1476
			     enum pipe pipe, int reg)
1477
{
1478
	u32 val = I915_READ(reg);
1479
	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1480
		DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1481
			      reg, pipe);
1482
		I915_WRITE(reg, val & ~PORT_ENABLE);
1483
	}
1484
}
1485
 
1486
/* Disable any ports connected to this transcoder */
1487
static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1488
				    enum pipe pipe)
1489
{
1490
	u32 reg, val;
1491
 
1492
	val = I915_READ(PCH_PP_CONTROL);
1493
	I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1494
 
1495
	disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1496
	disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1497
	disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1498
 
1499
	reg = PCH_ADPA;
1500
	val = I915_READ(reg);
1501
	if (adpa_pipe_enabled(dev_priv, val, pipe))
1502
		I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1503
 
1504
	reg = PCH_LVDS;
1505
	val = I915_READ(reg);
1506
	if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1507
		DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1508
		I915_WRITE(reg, val & ~LVDS_PORT_EN);
1509
		POSTING_READ(reg);
1510
		udelay(100);
1511
	}
1512
 
1513
	disable_pch_hdmi(dev_priv, pipe, HDMIB);
1514
	disable_pch_hdmi(dev_priv, pipe, HDMIC);
1515
	disable_pch_hdmi(dev_priv, pipe, HDMID);
1516
}
1517
 
1518
static void i8xx_disable_fbc(struct drm_device *dev)
1519
{
1520
    struct drm_i915_private *dev_priv = dev->dev_private;
1521
    u32 fbc_ctl;
1522
 
1523
    /* Disable compression */
1524
    fbc_ctl = I915_READ(FBC_CONTROL);
1525
    if ((fbc_ctl & FBC_CTL_EN) == 0)
1526
        return;
1527
 
1528
    fbc_ctl &= ~FBC_CTL_EN;
1529
    I915_WRITE(FBC_CONTROL, fbc_ctl);
1530
 
1531
    /* Wait for compressing bit to clear */
1532
    if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1533
        DRM_DEBUG_KMS("FBC idle timed out\n");
1534
        return;
1535
    }
1536
 
1537
    DRM_DEBUG_KMS("disabled FBC\n");
1538
}
1539
 
1540
static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1541
{
1542
    struct drm_device *dev = crtc->dev;
1543
    struct drm_i915_private *dev_priv = dev->dev_private;
1544
    struct drm_framebuffer *fb = crtc->fb;
1545
    struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1546
    struct drm_i915_gem_object *obj = intel_fb->obj;
1547
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1548
    int cfb_pitch;
1549
    int plane, i;
1550
    u32 fbc_ctl, fbc_ctl2;
1551
 
1552
    cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
2342 Serge 1553
	if (fb->pitches[0] < cfb_pitch)
1554
		cfb_pitch = fb->pitches[0];
2327 Serge 1555
 
1556
    /* FBC_CTL wants 64B units */
1557
    cfb_pitch = (cfb_pitch / 64) - 1;
1558
    plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1559
 
1560
    /* Clear old tags */
1561
    for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1562
        I915_WRITE(FBC_TAG + (i * 4), 0);
1563
 
1564
    /* Set it up... */
1565
    fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1566
    fbc_ctl2 |= plane;
1567
    I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1568
    I915_WRITE(FBC_FENCE_OFF, crtc->y);
1569
 
1570
    /* enable it... */
1571
    fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1572
    if (IS_I945GM(dev))
1573
        fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1574
    fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1575
    fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1576
    fbc_ctl |= obj->fence_reg;
1577
    I915_WRITE(FBC_CONTROL, fbc_ctl);
1578
 
1579
    DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1580
              cfb_pitch, crtc->y, intel_crtc->plane);
1581
}
1582
 
1583
static bool i8xx_fbc_enabled(struct drm_device *dev)
1584
{
1585
    struct drm_i915_private *dev_priv = dev->dev_private;
1586
 
1587
    return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1588
}
1589
 
1590
static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1591
{
1592
    struct drm_device *dev = crtc->dev;
1593
    struct drm_i915_private *dev_priv = dev->dev_private;
1594
    struct drm_framebuffer *fb = crtc->fb;
1595
    struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1596
    struct drm_i915_gem_object *obj = intel_fb->obj;
1597
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1598
    int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1599
    unsigned long stall_watermark = 200;
1600
    u32 dpfc_ctl;
1601
 
1602
    dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1603
    dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1604
    I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1605
 
1606
    I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1607
           (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1608
           (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1609
    I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1610
 
1611
    /* enable it... */
1612
    I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1613
 
1614
    DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1615
}
1616
 
1617
static void g4x_disable_fbc(struct drm_device *dev)
1618
{
1619
    struct drm_i915_private *dev_priv = dev->dev_private;
1620
    u32 dpfc_ctl;
1621
 
1622
    /* Disable compression */
1623
    dpfc_ctl = I915_READ(DPFC_CONTROL);
1624
    if (dpfc_ctl & DPFC_CTL_EN) {
1625
        dpfc_ctl &= ~DPFC_CTL_EN;
1626
        I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1627
 
1628
        DRM_DEBUG_KMS("disabled FBC\n");
1629
    }
1630
}
1631
 
1632
static bool g4x_fbc_enabled(struct drm_device *dev)
1633
{
1634
    struct drm_i915_private *dev_priv = dev->dev_private;
1635
 
1636
    return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1637
}
1638
 
1639
static void sandybridge_blit_fbc_update(struct drm_device *dev)
1640
{
1641
	struct drm_i915_private *dev_priv = dev->dev_private;
1642
	u32 blt_ecoskpd;
1643
 
1644
	/* Make sure blitter notifies FBC of writes */
1645
	gen6_gt_force_wake_get(dev_priv);
1646
	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1647
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1648
		GEN6_BLITTER_LOCK_SHIFT;
1649
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1651
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1652
	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1653
			 GEN6_BLITTER_LOCK_SHIFT);
1654
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1655
	POSTING_READ(GEN6_BLITTER_ECOSKPD);
1656
	gen6_gt_force_wake_put(dev_priv);
1657
}
1658
 
1659
static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1660
{
1661
    struct drm_device *dev = crtc->dev;
1662
    struct drm_i915_private *dev_priv = dev->dev_private;
1663
    struct drm_framebuffer *fb = crtc->fb;
1664
    struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1665
    struct drm_i915_gem_object *obj = intel_fb->obj;
1666
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1667
    int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1668
    unsigned long stall_watermark = 200;
1669
    u32 dpfc_ctl;
1670
 
1671
    dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1672
    dpfc_ctl &= DPFC_RESERVED;
1673
    dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1674
    /* Set persistent mode for front-buffer rendering, ala X. */
1675
    dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1676
    dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1677
    I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1678
 
1679
    I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1680
           (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1681
           (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1682
    I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1683
    I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1684
    /* enable it... */
1685
    I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1686
 
1687
    if (IS_GEN6(dev)) {
1688
        I915_WRITE(SNB_DPFC_CTL_SA,
1689
               SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1690
        I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1691
        sandybridge_blit_fbc_update(dev);
1692
    }
1693
 
1694
    DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1695
}
1696
 
1697
static void ironlake_disable_fbc(struct drm_device *dev)
1698
{
1699
    struct drm_i915_private *dev_priv = dev->dev_private;
1700
    u32 dpfc_ctl;
1701
 
1702
    /* Disable compression */
1703
    dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1704
    if (dpfc_ctl & DPFC_CTL_EN) {
1705
        dpfc_ctl &= ~DPFC_CTL_EN;
1706
        I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1707
 
1708
        DRM_DEBUG_KMS("disabled FBC\n");
1709
    }
1710
}
1711
 
1712
static bool ironlake_fbc_enabled(struct drm_device *dev)
1713
{
1714
    struct drm_i915_private *dev_priv = dev->dev_private;
1715
 
1716
    return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1717
}
1718
 
1719
bool intel_fbc_enabled(struct drm_device *dev)
1720
{
1721
	struct drm_i915_private *dev_priv = dev->dev_private;
1722
 
1723
	if (!dev_priv->display.fbc_enabled)
1724
		return false;
1725
 
1726
	return dev_priv->display.fbc_enabled(dev);
1727
}
1728
 
1729
 
1730
 
1731
 
1732
 
1733
 
1734
 
1735
 
1736
 
1737
 
1738
static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1739
{
1740
	struct intel_fbc_work *work;
1741
	struct drm_device *dev = crtc->dev;
1742
	struct drm_i915_private *dev_priv = dev->dev_private;
1743
 
1744
	if (!dev_priv->display.enable_fbc)
1745
		return;
1746
 
1747
//	intel_cancel_fbc_work(dev_priv);
1748
 
1749
//	work = kzalloc(sizeof *work, GFP_KERNEL);
1750
//	if (work == NULL) {
1751
//		dev_priv->display.enable_fbc(crtc, interval);
1752
//		return;
1753
//	}
1754
 
1755
//	work->crtc = crtc;
1756
//	work->fb = crtc->fb;
1757
//	work->interval = interval;
1758
//	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1759
 
1760
//	dev_priv->fbc_work = work;
1761
 
1762
	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1763
 
1764
	/* Delay the actual enabling to let pageflipping cease and the
1765
	 * display to settle before starting the compression. Note that
1766
	 * this delay also serves a second purpose: it allows for a
1767
	 * vblank to pass after disabling the FBC before we attempt
1768
	 * to modify the control registers.
1769
	 *
1770
	 * A more complicated solution would involve tracking vblanks
1771
	 * following the termination of the page-flipping sequence
1772
	 * and indeed performing the enable as a co-routine and not
1773
	 * waiting synchronously upon the vblank.
1774
	 */
1775
//	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1776
}
1777
 
1778
void intel_disable_fbc(struct drm_device *dev)
1779
{
1780
	struct drm_i915_private *dev_priv = dev->dev_private;
1781
 
1782
//   intel_cancel_fbc_work(dev_priv);
1783
 
1784
	if (!dev_priv->display.disable_fbc)
1785
		return;
1786
 
1787
	dev_priv->display.disable_fbc(dev);
1788
	dev_priv->cfb_plane = -1;
1789
}
1790
 
1791
/**
1792
 * intel_update_fbc - enable/disable FBC as needed
1793
 * @dev: the drm_device
1794
 *
1795
 * Set up the framebuffer compression hardware at mode set time.  We
1796
 * enable it if possible:
1797
 *   - plane A only (on pre-965)
1798
 *   - no pixel mulitply/line duplication
1799
 *   - no alpha buffer discard
1800
 *   - no dual wide
1801
 *   - framebuffer <= 2048 in width, 1536 in height
1802
 *
1803
 * We can't assume that any compression will take place (worst case),
1804
 * so the compressed buffer has to be the same size as the uncompressed
1805
 * one.  It also must reside (along with the line length buffer) in
1806
 * stolen memory.
1807
 *
1808
 * We need to enable/disable FBC on a global basis.
1809
 */
1810
static void intel_update_fbc(struct drm_device *dev)
1811
{
1812
	struct drm_i915_private *dev_priv = dev->dev_private;
1813
	struct drm_crtc *crtc = NULL, *tmp_crtc;
1814
	struct intel_crtc *intel_crtc;
1815
	struct drm_framebuffer *fb;
1816
	struct intel_framebuffer *intel_fb;
1817
	struct drm_i915_gem_object *obj;
2342 Serge 1818
	int enable_fbc;
2327 Serge 1819
 
1820
	DRM_DEBUG_KMS("\n");
1821
 
1822
	if (!i915_powersave)
1823
		return;
1824
 
1825
	if (!I915_HAS_FBC(dev))
1826
		return;
1827
 
1828
	/*
1829
	 * If FBC is already on, we just have to verify that we can
1830
	 * keep it that way...
1831
	 * Need to disable if:
1832
	 *   - more than one pipe is active
1833
	 *   - changing FBC params (stride, fence, mode)
1834
	 *   - new fb is too large to fit in compressed buffer
1835
	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
1836
	 */
1837
	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1838
		if (tmp_crtc->enabled && tmp_crtc->fb) {
1839
			if (crtc) {
1840
				DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2336 Serge 1841
                dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2327 Serge 1842
				goto out_disable;
1843
			}
1844
			crtc = tmp_crtc;
1845
		}
1846
	}
1847
 
1848
	if (!crtc || crtc->fb == NULL) {
1849
		DRM_DEBUG_KMS("no output, disabling\n");
2336 Serge 1850
        dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2327 Serge 1851
		goto out_disable;
1852
	}
1853
 
1854
	intel_crtc = to_intel_crtc(crtc);
1855
	fb = crtc->fb;
1856
	intel_fb = to_intel_framebuffer(fb);
1857
	obj = intel_fb->obj;
1858
 
2342 Serge 1859
	enable_fbc = i915_enable_fbc;
1860
	if (enable_fbc < 0) {
1861
		DRM_DEBUG_KMS("fbc set to per-chip default\n");
1862
		enable_fbc = 1;
1863
		if (INTEL_INFO(dev)->gen <= 5)
1864
			enable_fbc = 0;
1865
	}
1866
	if (!enable_fbc) {
1867
		DRM_DEBUG_KMS("fbc disabled per module param\n");
2336 Serge 1868
        dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2327 Serge 1869
		goto out_disable;
1870
	}
1871
	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1872
		DRM_DEBUG_KMS("framebuffer too large, disabling "
1873
			      "compression\n");
2336 Serge 1874
        dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2327 Serge 1875
		goto out_disable;
1876
	}
1877
	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1878
	    (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1879
		DRM_DEBUG_KMS("mode incompatible with compression, "
1880
			      "disabling\n");
2336 Serge 1881
        dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2327 Serge 1882
		goto out_disable;
1883
	}
1884
	if ((crtc->mode.hdisplay > 2048) ||
1885
	    (crtc->mode.vdisplay > 1536)) {
1886
		DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2336 Serge 1887
        dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2327 Serge 1888
		goto out_disable;
1889
	}
1890
	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1891
		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2336 Serge 1892
        dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2327 Serge 1893
		goto out_disable;
1894
	}
1895
 
1896
	/* The use of a CPU fence is mandatory in order to detect writes
1897
	 * by the CPU to the scanout and trigger updates to the FBC.
1898
	 */
1899
//	if (obj->tiling_mode != I915_TILING_X ||
1900
//	    obj->fence_reg == I915_FENCE_REG_NONE) {
1901
//		DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1902
//		dev_priv->no_fbc_reason = FBC_NOT_TILED;
1903
//		goto out_disable;
1904
//	}
1905
 
1906
	/* If the kernel debugger is active, always disable compression */
1907
	if (in_dbg_master())
1908
		goto out_disable;
1909
 
1910
	/* If the scanout has not changed, don't modify the FBC settings.
1911
	 * Note that we make the fundamental assumption that the fb->obj
1912
	 * cannot be unpinned (and have its GTT offset and fence revoked)
1913
	 * without first being decoupled from the scanout and FBC disabled.
1914
	 */
1915
	if (dev_priv->cfb_plane == intel_crtc->plane &&
1916
	    dev_priv->cfb_fb == fb->base.id &&
1917
	    dev_priv->cfb_y == crtc->y)
1918
		return;
1919
 
1920
	if (intel_fbc_enabled(dev)) {
1921
		/* We update FBC along two paths, after changing fb/crtc
1922
		 * configuration (modeswitching) and after page-flipping
1923
		 * finishes. For the latter, we know that not only did
1924
		 * we disable the FBC at the start of the page-flip
1925
		 * sequence, but also more than one vblank has passed.
1926
		 *
1927
		 * For the former case of modeswitching, it is possible
1928
		 * to switch between two FBC valid configurations
1929
		 * instantaneously so we do need to disable the FBC
1930
		 * before we can modify its control registers. We also
1931
		 * have to wait for the next vblank for that to take
1932
		 * effect. However, since we delay enabling FBC we can
1933
		 * assume that a vblank has passed since disabling and
1934
		 * that we can safely alter the registers in the deferred
1935
		 * callback.
1936
		 *
1937
		 * In the scenario that we go from a valid to invalid
1938
		 * and then back to valid FBC configuration we have
1939
		 * no strict enforcement that a vblank occurred since
1940
		 * disabling the FBC. However, along all current pipe
1941
		 * disabling paths we do need to wait for a vblank at
1942
		 * some point. And we wait before enabling FBC anyway.
1943
		 */
1944
		DRM_DEBUG_KMS("disabling active FBC for update\n");
1945
		intel_disable_fbc(dev);
1946
	}
1947
 
1948
	intel_enable_fbc(crtc, 500);
1949
	return;
1950
 
1951
out_disable:
1952
	/* Multiple disables should be harmless */
1953
	if (intel_fbc_enabled(dev)) {
1954
		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1955
		intel_disable_fbc(dev);
1956
	}
1957
}
1958
 
2335 Serge 1959
int
1960
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1961
			   struct drm_i915_gem_object *obj,
1962
			   struct intel_ring_buffer *pipelined)
1963
{
1964
	struct drm_i915_private *dev_priv = dev->dev_private;
1965
	u32 alignment;
1966
	int ret;
2327 Serge 1967
 
2335 Serge 1968
	switch (obj->tiling_mode) {
1969
	case I915_TILING_NONE:
1970
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1971
			alignment = 128 * 1024;
1972
		else if (INTEL_INFO(dev)->gen >= 4)
1973
			alignment = 4 * 1024;
1974
		else
1975
			alignment = 64 * 1024;
1976
		break;
1977
	case I915_TILING_X:
1978
		/* pin() will align the object as required by fence */
1979
		alignment = 0;
1980
		break;
1981
	case I915_TILING_Y:
1982
		/* FIXME: Is this true? */
1983
		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1984
		return -EINVAL;
1985
	default:
1986
		BUG();
1987
	}
2327 Serge 1988
 
2335 Serge 1989
	dev_priv->mm.interruptible = false;
1990
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1991
	if (ret)
1992
		goto err_interruptible;
2327 Serge 1993
 
2335 Serge 1994
	/* Install a fence for tiled scan-out. Pre-i965 always needs a
1995
	 * fence, whereas 965+ only requires a fence if using
1996
	 * framebuffer compression.  For simplicity, we always install
1997
	 * a fence as the cost is not that onerous.
1998
	 */
1999
//	if (obj->tiling_mode != I915_TILING_NONE) {
2000
//		ret = i915_gem_object_get_fence(obj, pipelined);
2001
//		if (ret)
2002
//			goto err_unpin;
2003
//	}
2327 Serge 2004
 
2335 Serge 2005
	dev_priv->mm.interruptible = true;
2006
	return 0;
2327 Serge 2007
 
2335 Serge 2008
err_unpin:
2344 Serge 2009
	i915_gem_object_unpin(obj);
2335 Serge 2010
err_interruptible:
2011
	dev_priv->mm.interruptible = true;
2012
	return ret;
2013
}
2327 Serge 2014
 
2015
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2016
                 int x, int y)
2017
{
2018
    struct drm_device *dev = crtc->dev;
2019
    struct drm_i915_private *dev_priv = dev->dev_private;
2020
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021
    struct intel_framebuffer *intel_fb;
2022
    struct drm_i915_gem_object *obj;
2023
    int plane = intel_crtc->plane;
2024
    unsigned long Start, Offset;
2025
    u32 dspcntr;
2026
    u32 reg;
2027
 
2028
    switch (plane) {
2029
    case 0:
2030
    case 1:
2031
        break;
2032
    default:
2033
        DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2034
        return -EINVAL;
2035
    }
2036
 
2037
    intel_fb = to_intel_framebuffer(fb);
2038
    obj = intel_fb->obj;
2039
 
2040
    reg = DSPCNTR(plane);
2041
    dspcntr = I915_READ(reg);
2042
    /* Mask out pixel format bits in case we change it */
2043
    dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2044
    switch (fb->bits_per_pixel) {
2045
    case 8:
2046
        dspcntr |= DISPPLANE_8BPP;
2047
        break;
2048
    case 16:
2049
        if (fb->depth == 15)
2050
            dspcntr |= DISPPLANE_15_16BPP;
2051
        else
2052
            dspcntr |= DISPPLANE_16BPP;
2053
        break;
2054
    case 24:
2055
    case 32:
2056
        dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2057
        break;
2058
    default:
2059
        DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2060
        return -EINVAL;
2061
    }
2062
    if (INTEL_INFO(dev)->gen >= 4) {
2063
        if (obj->tiling_mode != I915_TILING_NONE)
2064
            dspcntr |= DISPPLANE_TILED;
2065
        else
2066
            dspcntr &= ~DISPPLANE_TILED;
2067
    }
2068
 
2069
    I915_WRITE(reg, dspcntr);
2070
 
2071
    Start = obj->gtt_offset;
2342 Serge 2072
	Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327 Serge 2073
 
2074
    DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2342 Serge 2075
		      Start, Offset, x, y, fb->pitches[0]);
2076
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2327 Serge 2077
    if (INTEL_INFO(dev)->gen >= 4) {
2078
        I915_WRITE(DSPSURF(plane), Start);
2079
        I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2080
        I915_WRITE(DSPADDR(plane), Offset);
2081
    } else
2082
        I915_WRITE(DSPADDR(plane), Start + Offset);
2083
    POSTING_READ(reg);
2084
 
2085
    return 0;
2086
}
2087
 
2088
static int ironlake_update_plane(struct drm_crtc *crtc,
2089
                 struct drm_framebuffer *fb, int x, int y)
2090
{
2091
    struct drm_device *dev = crtc->dev;
2092
    struct drm_i915_private *dev_priv = dev->dev_private;
2093
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
    struct intel_framebuffer *intel_fb;
2095
    struct drm_i915_gem_object *obj;
2096
    int plane = intel_crtc->plane;
2097
    unsigned long Start, Offset;
2098
    u32 dspcntr;
2099
    u32 reg;
2100
 
2101
    switch (plane) {
2102
    case 0:
2103
    case 1:
2342 Serge 2104
	case 2:
2327 Serge 2105
        break;
2106
    default:
2107
        DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2108
        return -EINVAL;
2109
    }
2110
 
2111
    intel_fb = to_intel_framebuffer(fb);
2112
    obj = intel_fb->obj;
2113
 
2114
    reg = DSPCNTR(plane);
2115
    dspcntr = I915_READ(reg);
2116
    /* Mask out pixel format bits in case we change it */
2117
    dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2118
    switch (fb->bits_per_pixel) {
2119
    case 8:
2120
        dspcntr |= DISPPLANE_8BPP;
2121
        break;
2122
    case 16:
2123
        if (fb->depth != 16)
2124
            return -EINVAL;
2125
 
2126
        dspcntr |= DISPPLANE_16BPP;
2127
        break;
2128
    case 24:
2129
    case 32:
2130
        if (fb->depth == 24)
2131
            dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2132
        else if (fb->depth == 30)
2133
            dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2134
        else
2135
            return -EINVAL;
2136
        break;
2137
    default:
2138
        DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2139
        return -EINVAL;
2140
    }
2141
 
2142
//    if (obj->tiling_mode != I915_TILING_NONE)
2143
//        dspcntr |= DISPPLANE_TILED;
2144
//    else
2145
        dspcntr &= ~DISPPLANE_TILED;
2146
 
2147
    /* must disable */
2148
    dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2149
 
2150
    I915_WRITE(reg, dspcntr);
2151
 
2336 Serge 2152
    Start = obj->gtt_offset;
2342 Serge 2153
	Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327 Serge 2154
 
2155
    DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2342 Serge 2156
		      Start, Offset, x, y, fb->pitches[0]);
2157
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2330 Serge 2158
	I915_WRITE(DSPSURF(plane), Start);
2159
	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2160
	I915_WRITE(DSPADDR(plane), Offset);
2161
	POSTING_READ(reg);
2327 Serge 2162
 
2163
    return 0;
2164
}
2165
 
2166
/* Assume fb object is pinned & idle & fenced and just update base pointers */
2167
static int
2168
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2169
			   int x, int y, enum mode_set_atomic state)
2170
{
2171
	struct drm_device *dev = crtc->dev;
2172
	struct drm_i915_private *dev_priv = dev->dev_private;
2173
	int ret;
2174
 
2336 Serge 2175
    ENTER();
2176
 
2327 Serge 2177
	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2178
	if (ret)
2336 Serge 2179
    {
2180
        LEAVE();
2327 Serge 2181
		return ret;
2336 Serge 2182
    };
2327 Serge 2183
 
2184
	intel_update_fbc(dev);
2185
	intel_increase_pllclock(crtc);
2336 Serge 2186
    LEAVE();
2327 Serge 2187
 
2188
	return 0;
2189
}
2190
 
2191
static int
2192
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2193
		    struct drm_framebuffer *old_fb)
2194
{
2195
	struct drm_device *dev = crtc->dev;
2196
	struct drm_i915_master_private *master_priv;
2197
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2342 Serge 2198
	int ret;
2327 Serge 2199
 
2336 Serge 2200
    ENTER();
2201
 
2327 Serge 2202
	/* no fb bound */
2203
	if (!crtc->fb) {
2204
		DRM_ERROR("No FB bound\n");
2205
		return 0;
2206
	}
2207
 
2208
	switch (intel_crtc->plane) {
2209
	case 0:
2210
	case 1:
2211
		break;
2342 Serge 2212
	case 2:
2213
		if (IS_IVYBRIDGE(dev))
2214
			break;
2215
		/* fall through otherwise */
2327 Serge 2216
	default:
2217
		DRM_ERROR("no plane for crtc\n");
2218
		return -EINVAL;
2219
	}
2220
 
2221
	mutex_lock(&dev->struct_mutex);
2222
 
2336 Serge 2223
    ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2224
					 LEAVE_ATOMIC_MODE_SET);
2327 Serge 2225
	if (ret) {
2344 Serge 2226
		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2327 Serge 2227
		mutex_unlock(&dev->struct_mutex);
2228
		DRM_ERROR("failed to update base address\n");
2336 Serge 2229
        LEAVE();
2327 Serge 2230
		return ret;
2231
	}
2232
 
2336 Serge 2233
	mutex_unlock(&dev->struct_mutex);
2327 Serge 2234
 
2336 Serge 2235
 
2236
    LEAVE();
2237
    return 0;
2238
 
2330 Serge 2239
#if 0
2240
	if (!dev->primary->master)
2336 Serge 2241
    {
2242
        LEAVE();
2330 Serge 2243
		return 0;
2336 Serge 2244
    };
2327 Serge 2245
 
2330 Serge 2246
	master_priv = dev->primary->master->driver_priv;
2247
	if (!master_priv->sarea_priv)
2336 Serge 2248
    {
2249
        LEAVE();
2330 Serge 2250
		return 0;
2336 Serge 2251
    };
2327 Serge 2252
 
2330 Serge 2253
	if (intel_crtc->pipe) {
2254
		master_priv->sarea_priv->pipeB_x = x;
2255
		master_priv->sarea_priv->pipeB_y = y;
2256
	} else {
2257
		master_priv->sarea_priv->pipeA_x = x;
2258
		master_priv->sarea_priv->pipeA_y = y;
2259
	}
2336 Serge 2260
    LEAVE();
2261
 
2262
	return 0;
2330 Serge 2263
#endif
2336 Serge 2264
 
2327 Serge 2265
}
2266
 
2267
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2268
{
2269
	struct drm_device *dev = crtc->dev;
2270
	struct drm_i915_private *dev_priv = dev->dev_private;
2271
	u32 dpa_ctl;
2272
 
2273
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2274
	dpa_ctl = I915_READ(DP_A);
2275
	dpa_ctl &= ~DP_PLL_FREQ_MASK;
2276
 
2277
	if (clock < 200000) {
2278
		u32 temp;
2279
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
2280
		/* workaround for 160Mhz:
2281
		   1) program 0x4600c bits 15:0 = 0x8124
2282
		   2) program 0x46010 bit 0 = 1
2283
		   3) program 0x46034 bit 24 = 1
2284
		   4) program 0x64000 bit 14 = 1
2285
		   */
2286
		temp = I915_READ(0x4600c);
2287
		temp &= 0xffff0000;
2288
		I915_WRITE(0x4600c, temp | 0x8124);
2289
 
2290
		temp = I915_READ(0x46010);
2291
		I915_WRITE(0x46010, temp | 1);
2292
 
2293
		temp = I915_READ(0x46034);
2294
		I915_WRITE(0x46034, temp | (1 << 24));
2295
	} else {
2296
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
2297
	}
2298
	I915_WRITE(DP_A, dpa_ctl);
2299
 
2300
	POSTING_READ(DP_A);
2301
	udelay(500);
2302
}
2303
 
2304
static void intel_fdi_normal_train(struct drm_crtc *crtc)
2305
{
2306
	struct drm_device *dev = crtc->dev;
2307
	struct drm_i915_private *dev_priv = dev->dev_private;
2308
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
	int pipe = intel_crtc->pipe;
2310
	u32 reg, temp;
2311
 
2312
	/* enable normal train */
2313
	reg = FDI_TX_CTL(pipe);
2314
	temp = I915_READ(reg);
2315
	if (IS_IVYBRIDGE(dev)) {
2316
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2317
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2318
	} else {
2319
		temp &= ~FDI_LINK_TRAIN_NONE;
2320
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2321
	}
2322
	I915_WRITE(reg, temp);
2323
 
2324
	reg = FDI_RX_CTL(pipe);
2325
	temp = I915_READ(reg);
2326
	if (HAS_PCH_CPT(dev)) {
2327
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2328
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2329
	} else {
2330
		temp &= ~FDI_LINK_TRAIN_NONE;
2331
		temp |= FDI_LINK_TRAIN_NONE;
2332
	}
2333
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2334
 
2335
	/* wait one idle pattern time */
2336
	POSTING_READ(reg);
2337
	udelay(1000);
2338
 
2339
	/* IVB wants error correction enabled */
2340
	if (IS_IVYBRIDGE(dev))
2341
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2342
			   FDI_FE_ERRC_ENABLE);
2343
}
2344
 
2345
static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2346
{
2347
	struct drm_i915_private *dev_priv = dev->dev_private;
2348
	u32 flags = I915_READ(SOUTH_CHICKEN1);
2349
 
2350
	flags |= FDI_PHASE_SYNC_OVR(pipe);
2351
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2352
	flags |= FDI_PHASE_SYNC_EN(pipe);
2353
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2354
	POSTING_READ(SOUTH_CHICKEN1);
2355
}
2356
 
2357
/* The FDI link training functions for ILK/Ibexpeak. */
2358
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2359
{
2360
    struct drm_device *dev = crtc->dev;
2361
    struct drm_i915_private *dev_priv = dev->dev_private;
2362
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2363
    int pipe = intel_crtc->pipe;
2364
    int plane = intel_crtc->plane;
2365
    u32 reg, temp, tries;
2366
 
2367
    /* FDI needs bits from pipe & plane first */
2368
    assert_pipe_enabled(dev_priv, pipe);
2369
    assert_plane_enabled(dev_priv, plane);
2370
 
2371
    /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2372
       for train result */
2373
    reg = FDI_RX_IMR(pipe);
2374
    temp = I915_READ(reg);
2375
    temp &= ~FDI_RX_SYMBOL_LOCK;
2376
    temp &= ~FDI_RX_BIT_LOCK;
2377
    I915_WRITE(reg, temp);
2378
    I915_READ(reg);
2379
    udelay(150);
2380
 
2381
    /* enable CPU FDI TX and PCH FDI RX */
2382
    reg = FDI_TX_CTL(pipe);
2383
    temp = I915_READ(reg);
2384
    temp &= ~(7 << 19);
2385
    temp |= (intel_crtc->fdi_lanes - 1) << 19;
2386
    temp &= ~FDI_LINK_TRAIN_NONE;
2387
    temp |= FDI_LINK_TRAIN_PATTERN_1;
2388
    I915_WRITE(reg, temp | FDI_TX_ENABLE);
2389
 
2390
    reg = FDI_RX_CTL(pipe);
2391
    temp = I915_READ(reg);
2392
    temp &= ~FDI_LINK_TRAIN_NONE;
2393
    temp |= FDI_LINK_TRAIN_PATTERN_1;
2394
    I915_WRITE(reg, temp | FDI_RX_ENABLE);
2395
 
2396
    POSTING_READ(reg);
2397
    udelay(150);
2398
 
2399
    /* Ironlake workaround, enable clock pointer after FDI enable*/
2400
    if (HAS_PCH_IBX(dev)) {
2401
        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2402
        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2403
               FDI_RX_PHASE_SYNC_POINTER_EN);
2404
    }
2405
 
2406
    reg = FDI_RX_IIR(pipe);
2407
    for (tries = 0; tries < 5; tries++) {
2408
        temp = I915_READ(reg);
2409
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
 
2411
        if ((temp & FDI_RX_BIT_LOCK)) {
2412
            DRM_DEBUG_KMS("FDI train 1 done.\n");
2413
            I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2414
            break;
2415
        }
2416
    }
2417
    if (tries == 5)
2418
        DRM_ERROR("FDI train 1 fail!\n");
2419
 
2420
    /* Train 2 */
2421
    reg = FDI_TX_CTL(pipe);
2422
    temp = I915_READ(reg);
2423
    temp &= ~FDI_LINK_TRAIN_NONE;
2424
    temp |= FDI_LINK_TRAIN_PATTERN_2;
2425
    I915_WRITE(reg, temp);
2426
 
2427
    reg = FDI_RX_CTL(pipe);
2428
    temp = I915_READ(reg);
2429
    temp &= ~FDI_LINK_TRAIN_NONE;
2430
    temp |= FDI_LINK_TRAIN_PATTERN_2;
2431
    I915_WRITE(reg, temp);
2432
 
2433
    POSTING_READ(reg);
2434
    udelay(150);
2435
 
2436
    reg = FDI_RX_IIR(pipe);
2437
    for (tries = 0; tries < 5; tries++) {
2438
        temp = I915_READ(reg);
2439
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2440
 
2441
        if (temp & FDI_RX_SYMBOL_LOCK) {
2442
            I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2443
            DRM_DEBUG_KMS("FDI train 2 done.\n");
2444
            break;
2445
        }
2446
    }
2447
    if (tries == 5)
2448
        DRM_ERROR("FDI train 2 fail!\n");
2449
 
2450
    DRM_DEBUG_KMS("FDI train done\n");
2451
 
2452
}
2453
 
2342 Serge 2454
static const int snb_b_fdi_train_param[] = {
2327 Serge 2455
    FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2456
    FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2457
    FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2458
    FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2459
};
2460
 
2461
/* The FDI link training functions for SNB/Cougarpoint. */
2462
static void gen6_fdi_link_train(struct drm_crtc *crtc)
2463
{
2464
    struct drm_device *dev = crtc->dev;
2465
    struct drm_i915_private *dev_priv = dev->dev_private;
2466
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467
    int pipe = intel_crtc->pipe;
2468
    u32 reg, temp, i;
2469
 
2470
    /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471
       for train result */
2472
    reg = FDI_RX_IMR(pipe);
2473
    temp = I915_READ(reg);
2474
    temp &= ~FDI_RX_SYMBOL_LOCK;
2475
    temp &= ~FDI_RX_BIT_LOCK;
2476
    I915_WRITE(reg, temp);
2477
 
2478
    POSTING_READ(reg);
2479
    udelay(150);
2480
 
2481
    /* enable CPU FDI TX and PCH FDI RX */
2482
    reg = FDI_TX_CTL(pipe);
2483
    temp = I915_READ(reg);
2484
    temp &= ~(7 << 19);
2485
    temp |= (intel_crtc->fdi_lanes - 1) << 19;
2486
    temp &= ~FDI_LINK_TRAIN_NONE;
2487
    temp |= FDI_LINK_TRAIN_PATTERN_1;
2488
    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2489
    /* SNB-B */
2490
    temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2491
    I915_WRITE(reg, temp | FDI_TX_ENABLE);
2492
 
2493
    reg = FDI_RX_CTL(pipe);
2494
    temp = I915_READ(reg);
2495
    if (HAS_PCH_CPT(dev)) {
2496
        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497
        temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2498
    } else {
2499
        temp &= ~FDI_LINK_TRAIN_NONE;
2500
        temp |= FDI_LINK_TRAIN_PATTERN_1;
2501
    }
2502
    I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
 
2504
    POSTING_READ(reg);
2505
    udelay(150);
2506
 
2507
    if (HAS_PCH_CPT(dev))
2508
        cpt_phase_pointer_enable(dev, pipe);
2509
 
2342 Serge 2510
	for (i = 0; i < 4; i++) {
2327 Serge 2511
        reg = FDI_TX_CTL(pipe);
2512
        temp = I915_READ(reg);
2513
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514
        temp |= snb_b_fdi_train_param[i];
2515
        I915_WRITE(reg, temp);
2516
 
2517
        POSTING_READ(reg);
2518
        udelay(500);
2519
 
2520
        reg = FDI_RX_IIR(pipe);
2521
        temp = I915_READ(reg);
2522
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2523
 
2524
        if (temp & FDI_RX_BIT_LOCK) {
2525
            I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526
            DRM_DEBUG_KMS("FDI train 1 done.\n");
2527
            break;
2528
        }
2529
    }
2530
    if (i == 4)
2531
        DRM_ERROR("FDI train 1 fail!\n");
2532
 
2533
    /* Train 2 */
2534
    reg = FDI_TX_CTL(pipe);
2535
    temp = I915_READ(reg);
2536
    temp &= ~FDI_LINK_TRAIN_NONE;
2537
    temp |= FDI_LINK_TRAIN_PATTERN_2;
2538
    if (IS_GEN6(dev)) {
2539
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2540
        /* SNB-B */
2541
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2542
    }
2543
    I915_WRITE(reg, temp);
2544
 
2545
    reg = FDI_RX_CTL(pipe);
2546
    temp = I915_READ(reg);
2547
    if (HAS_PCH_CPT(dev)) {
2548
        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549
        temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2550
    } else {
2551
        temp &= ~FDI_LINK_TRAIN_NONE;
2552
        temp |= FDI_LINK_TRAIN_PATTERN_2;
2553
    }
2554
    I915_WRITE(reg, temp);
2555
 
2556
    POSTING_READ(reg);
2557
    udelay(150);
2558
 
2342 Serge 2559
	for (i = 0; i < 4; i++) {
2327 Serge 2560
        reg = FDI_TX_CTL(pipe);
2561
        temp = I915_READ(reg);
2562
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563
        temp |= snb_b_fdi_train_param[i];
2564
        I915_WRITE(reg, temp);
2565
 
2566
        POSTING_READ(reg);
2567
        udelay(500);
2568
 
2569
        reg = FDI_RX_IIR(pipe);
2570
        temp = I915_READ(reg);
2571
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
 
2573
        if (temp & FDI_RX_SYMBOL_LOCK) {
2574
            I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575
            DRM_DEBUG_KMS("FDI train 2 done.\n");
2576
            break;
2577
        }
2578
    }
2579
    if (i == 4)
2580
        DRM_ERROR("FDI train 2 fail!\n");
2581
 
2582
    DRM_DEBUG_KMS("FDI train done.\n");
2583
}
2584
 
2585
/* Manual link training for Ivy Bridge A0 parts */
2586
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2587
{
2588
    struct drm_device *dev = crtc->dev;
2589
    struct drm_i915_private *dev_priv = dev->dev_private;
2590
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591
    int pipe = intel_crtc->pipe;
2592
    u32 reg, temp, i;
2593
 
2594
    /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2595
       for train result */
2596
    reg = FDI_RX_IMR(pipe);
2597
    temp = I915_READ(reg);
2598
    temp &= ~FDI_RX_SYMBOL_LOCK;
2599
    temp &= ~FDI_RX_BIT_LOCK;
2600
    I915_WRITE(reg, temp);
2601
 
2602
    POSTING_READ(reg);
2603
    udelay(150);
2604
 
2605
    /* enable CPU FDI TX and PCH FDI RX */
2606
    reg = FDI_TX_CTL(pipe);
2607
    temp = I915_READ(reg);
2608
    temp &= ~(7 << 19);
2609
    temp |= (intel_crtc->fdi_lanes - 1) << 19;
2610
    temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2611
    temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2612
    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613
    temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2342 Serge 2614
	temp |= FDI_COMPOSITE_SYNC;
2327 Serge 2615
    I915_WRITE(reg, temp | FDI_TX_ENABLE);
2616
 
2617
    reg = FDI_RX_CTL(pipe);
2618
    temp = I915_READ(reg);
2619
    temp &= ~FDI_LINK_TRAIN_AUTO;
2620
    temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621
    temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2342 Serge 2622
	temp |= FDI_COMPOSITE_SYNC;
2327 Serge 2623
    I915_WRITE(reg, temp | FDI_RX_ENABLE);
2624
 
2625
    POSTING_READ(reg);
2626
    udelay(150);
2627
 
2628
    if (HAS_PCH_CPT(dev))
2629
        cpt_phase_pointer_enable(dev, pipe);
2630
 
2342 Serge 2631
	for (i = 0; i < 4; i++) {
2327 Serge 2632
        reg = FDI_TX_CTL(pipe);
2633
        temp = I915_READ(reg);
2634
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635
        temp |= snb_b_fdi_train_param[i];
2636
        I915_WRITE(reg, temp);
2637
 
2638
        POSTING_READ(reg);
2639
        udelay(500);
2640
 
2641
        reg = FDI_RX_IIR(pipe);
2642
        temp = I915_READ(reg);
2643
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644
 
2645
        if (temp & FDI_RX_BIT_LOCK ||
2646
            (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2647
            I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2648
            DRM_DEBUG_KMS("FDI train 1 done.\n");
2649
            break;
2650
        }
2651
    }
2652
    if (i == 4)
2653
        DRM_ERROR("FDI train 1 fail!\n");
2654
 
2655
    /* Train 2 */
2656
    reg = FDI_TX_CTL(pipe);
2657
    temp = I915_READ(reg);
2658
    temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2659
    temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2660
    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661
    temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2662
    I915_WRITE(reg, temp);
2663
 
2664
    reg = FDI_RX_CTL(pipe);
2665
    temp = I915_READ(reg);
2666
    temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2667
    temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2668
    I915_WRITE(reg, temp);
2669
 
2670
    POSTING_READ(reg);
2671
    udelay(150);
2672
 
2342 Serge 2673
	for (i = 0; i < 4; i++) {
2327 Serge 2674
        reg = FDI_TX_CTL(pipe);
2675
        temp = I915_READ(reg);
2676
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2677
        temp |= snb_b_fdi_train_param[i];
2678
        I915_WRITE(reg, temp);
2679
 
2680
        POSTING_READ(reg);
2681
        udelay(500);
2682
 
2683
        reg = FDI_RX_IIR(pipe);
2684
        temp = I915_READ(reg);
2685
        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2686
 
2687
        if (temp & FDI_RX_SYMBOL_LOCK) {
2688
            I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2689
            DRM_DEBUG_KMS("FDI train 2 done.\n");
2690
            break;
2691
        }
2692
    }
2693
    if (i == 4)
2694
        DRM_ERROR("FDI train 2 fail!\n");
2695
 
2696
    DRM_DEBUG_KMS("FDI train done.\n");
2697
}
2698
 
2699
static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2700
{
2701
	struct drm_device *dev = crtc->dev;
2702
	struct drm_i915_private *dev_priv = dev->dev_private;
2703
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704
	int pipe = intel_crtc->pipe;
2705
	u32 reg, temp;
2706
 
2707
	/* Write the TU size bits so error detection works */
2708
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
2709
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2710
 
2711
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2712
	reg = FDI_RX_CTL(pipe);
2713
	temp = I915_READ(reg);
2714
	temp &= ~((0x7 << 19) | (0x7 << 16));
2715
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2717
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2718
 
2719
	POSTING_READ(reg);
2720
	udelay(200);
2721
 
2722
	/* Switch from Rawclk to PCDclk */
2723
	temp = I915_READ(reg);
2724
	I915_WRITE(reg, temp | FDI_PCDCLK);
2725
 
2726
	POSTING_READ(reg);
2727
	udelay(200);
2728
 
2729
	/* Enable CPU FDI TX PLL, always on for Ironlake */
2730
	reg = FDI_TX_CTL(pipe);
2731
	temp = I915_READ(reg);
2732
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2733
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2734
 
2735
		POSTING_READ(reg);
2736
		udelay(100);
2737
	}
2738
}
2739
 
2740
static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741
{
2742
	struct drm_i915_private *dev_priv = dev->dev_private;
2743
	u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
 
2745
	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747
	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749
	POSTING_READ(SOUTH_CHICKEN1);
2750
}
2751
static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752
{
2753
	struct drm_device *dev = crtc->dev;
2754
	struct drm_i915_private *dev_priv = dev->dev_private;
2755
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756
	int pipe = intel_crtc->pipe;
2757
	u32 reg, temp;
2758
 
2759
	/* disable CPU FDI tx and PCH FDI rx */
2760
	reg = FDI_TX_CTL(pipe);
2761
	temp = I915_READ(reg);
2762
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763
	POSTING_READ(reg);
2764
 
2765
	reg = FDI_RX_CTL(pipe);
2766
	temp = I915_READ(reg);
2767
	temp &= ~(0x7 << 16);
2768
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
 
2771
	POSTING_READ(reg);
2772
	udelay(100);
2773
 
2774
	/* Ironlake workaround, disable clock pointer after downing FDI */
2775
	if (HAS_PCH_IBX(dev)) {
2776
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777
		I915_WRITE(FDI_RX_CHICKEN(pipe),
2778
			   I915_READ(FDI_RX_CHICKEN(pipe) &
2779
				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780
	} else if (HAS_PCH_CPT(dev)) {
2781
		cpt_phase_pointer_disable(dev, pipe);
2782
	}
2783
 
2784
	/* still set train pattern 1 */
2785
	reg = FDI_TX_CTL(pipe);
2786
	temp = I915_READ(reg);
2787
	temp &= ~FDI_LINK_TRAIN_NONE;
2788
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2789
	I915_WRITE(reg, temp);
2790
 
2791
	reg = FDI_RX_CTL(pipe);
2792
	temp = I915_READ(reg);
2793
	if (HAS_PCH_CPT(dev)) {
2794
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796
	} else {
2797
		temp &= ~FDI_LINK_TRAIN_NONE;
2798
		temp |= FDI_LINK_TRAIN_PATTERN_1;
2799
	}
2800
	/* BPC in FDI rx is consistent with that in PIPECONF */
2801
	temp &= ~(0x07 << 16);
2802
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803
	I915_WRITE(reg, temp);
2804
 
2805
	POSTING_READ(reg);
2806
	udelay(100);
2807
}
2808
 
2809
/*
2810
 * When we disable a pipe, we need to clear any pending scanline wait events
2811
 * to avoid hanging the ring, which we assume we are waiting on.
2812
 */
2813
static void intel_clear_scanline_wait(struct drm_device *dev)
2814
{
2815
	struct drm_i915_private *dev_priv = dev->dev_private;
2816
	struct intel_ring_buffer *ring;
2817
	u32 tmp;
2818
 
2819
	if (IS_GEN2(dev))
2820
		/* Can't break the hang on i8xx */
2821
		return;
2822
 
2823
	ring = LP_RING(dev_priv);
2824
	tmp = I915_READ_CTL(ring);
2825
	if (tmp & RING_WAIT)
2826
		I915_WRITE_CTL(ring, tmp);
2827
}
2828
 
2829
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2830
{
2831
	struct drm_i915_gem_object *obj;
2832
	struct drm_i915_private *dev_priv;
2833
 
2834
	if (crtc->fb == NULL)
2835
		return;
2836
 
2837
	obj = to_intel_framebuffer(crtc->fb)->obj;
2838
	dev_priv = crtc->dev->dev_private;
2839
//	wait_event(dev_priv->pending_flip_queue,
2840
//		   atomic_read(&obj->pending_flip) == 0);
2841
}
2842
 
2843
static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2844
{
2845
	struct drm_device *dev = crtc->dev;
2846
	struct drm_mode_config *mode_config = &dev->mode_config;
2847
	struct intel_encoder *encoder;
2848
 
2849
	/*
2850
	 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2851
	 * must be driven by its own crtc; no sharing is possible.
2852
	 */
2853
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2854
		if (encoder->base.crtc != crtc)
2855
			continue;
2856
 
2857
		switch (encoder->type) {
2858
		case INTEL_OUTPUT_EDP:
2859
			if (!intel_encoder_is_pch_edp(&encoder->base))
2860
				return false;
2861
			continue;
2862
		}
2863
	}
2864
 
2865
	return true;
2866
}
2867
 
2868
/*
2869
 * Enable PCH resources required for PCH ports:
2870
 *   - PCH PLLs
2871
 *   - FDI training & RX/TX
2872
 *   - update transcoder timings
2873
 *   - DP transcoding bits
2874
 *   - transcoder
2875
 */
2876
static void ironlake_pch_enable(struct drm_crtc *crtc)
2877
{
2878
	struct drm_device *dev = crtc->dev;
2879
	struct drm_i915_private *dev_priv = dev->dev_private;
2880
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881
	int pipe = intel_crtc->pipe;
2342 Serge 2882
	u32 reg, temp, transc_sel;
2327 Serge 2883
 
2884
	/* For PCH output, training FDI link */
2885
	dev_priv->display.fdi_link_train(crtc);
2886
 
2887
	intel_enable_pch_pll(dev_priv, pipe);
2888
 
2889
	if (HAS_PCH_CPT(dev)) {
2342 Serge 2890
		transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2891
			TRANSC_DPLLB_SEL;
2892
 
2327 Serge 2893
		/* Be sure PCH DPLL SEL is set */
2894
		temp = I915_READ(PCH_DPLL_SEL);
2342 Serge 2895
		if (pipe == 0) {
2896
			temp &= ~(TRANSA_DPLLB_SEL);
2327 Serge 2897
			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2342 Serge 2898
		} else if (pipe == 1) {
2899
			temp &= ~(TRANSB_DPLLB_SEL);
2327 Serge 2900
			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2342 Serge 2901
		} else if (pipe == 2) {
2902
			temp &= ~(TRANSC_DPLLB_SEL);
2903
			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2904
		}
2327 Serge 2905
		I915_WRITE(PCH_DPLL_SEL, temp);
2906
	}
2907
 
2908
	/* set transcoder timing, panel must allow it */
2909
	assert_panel_unlocked(dev_priv, pipe);
2910
	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2911
	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2912
	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2913
 
2914
	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2915
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2916
	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2917
 
2918
	intel_fdi_normal_train(crtc);
2919
 
2920
	/* For PCH DP, enable TRANS_DP_CTL */
2921
	if (HAS_PCH_CPT(dev) &&
2342 Serge 2922
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2923
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2327 Serge 2924
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2925
		reg = TRANS_DP_CTL(pipe);
2926
		temp = I915_READ(reg);
2927
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
2928
			  TRANS_DP_SYNC_MASK |
2929
			  TRANS_DP_BPC_MASK);
2930
		temp |= (TRANS_DP_OUTPUT_ENABLE |
2931
			 TRANS_DP_ENH_FRAMING);
2932
		temp |= bpc << 9; /* same format but at 11:9 */
2933
 
2934
		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2935
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2936
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2937
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2938
 
2939
		switch (intel_trans_dp_port_sel(crtc)) {
2940
		case PCH_DP_B:
2941
			temp |= TRANS_DP_PORT_SEL_B;
2942
			break;
2943
		case PCH_DP_C:
2944
			temp |= TRANS_DP_PORT_SEL_C;
2945
			break;
2946
		case PCH_DP_D:
2947
			temp |= TRANS_DP_PORT_SEL_D;
2948
			break;
2949
		default:
2950
			DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2951
			temp |= TRANS_DP_PORT_SEL_B;
2952
			break;
2953
		}
2954
 
2955
		I915_WRITE(reg, temp);
2956
	}
2957
 
2958
	intel_enable_transcoder(dev_priv, pipe);
2959
}
2960
 
2342 Serge 2961
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2962
{
2963
	struct drm_i915_private *dev_priv = dev->dev_private;
2964
	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2965
	u32 temp;
2966
 
2967
	temp = I915_READ(dslreg);
2968
	udelay(500);
2969
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
2970
		/* Without this, mode sets may fail silently on FDI */
2971
		I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2972
		udelay(250);
2973
		I915_WRITE(tc2reg, 0);
2974
		if (wait_for(I915_READ(dslreg) != temp, 5))
2975
			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2976
	}
2977
}
2978
 
2327 Serge 2979
static void ironlake_crtc_enable(struct drm_crtc *crtc)
2980
{
2981
    struct drm_device *dev = crtc->dev;
2982
    struct drm_i915_private *dev_priv = dev->dev_private;
2983
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984
    int pipe = intel_crtc->pipe;
2985
    int plane = intel_crtc->plane;
2986
    u32 temp;
2987
    bool is_pch_port;
2988
 
2989
    if (intel_crtc->active)
2990
        return;
2991
 
2992
    intel_crtc->active = true;
2993
    intel_update_watermarks(dev);
2994
 
2995
    if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2996
        temp = I915_READ(PCH_LVDS);
2997
        if ((temp & LVDS_PORT_EN) == 0)
2998
            I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2999
    }
3000
 
3001
    is_pch_port = intel_crtc_driving_pch(crtc);
3002
 
3003
    if (is_pch_port)
3004
        ironlake_fdi_pll_enable(crtc);
3005
    else
3006
        ironlake_fdi_disable(crtc);
3007
 
3008
    /* Enable panel fitting for LVDS */
3009
    if (dev_priv->pch_pf_size &&
3010
        (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3011
        /* Force use of hard-coded filter coefficients
3012
         * as some pre-programmed values are broken,
3013
         * e.g. x201.
3014
         */
3015
        I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3016
        I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3017
        I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3018
    }
3019
 
3020
    /*
3021
     * On ILK+ LUT must be loaded before the pipe is running but with
3022
     * clocks enabled
3023
     */
3024
    intel_crtc_load_lut(crtc);
3025
 
3026
    intel_enable_pipe(dev_priv, pipe, is_pch_port);
3027
    intel_enable_plane(dev_priv, plane, pipe);
3028
 
3029
    if (is_pch_port)
3030
        ironlake_pch_enable(crtc);
3031
 
3032
    mutex_lock(&dev->struct_mutex);
3033
    intel_update_fbc(dev);
3034
    mutex_unlock(&dev->struct_mutex);
3035
 
3036
//    intel_crtc_update_cursor(crtc, true);
3037
}
3038
 
3039
static void ironlake_crtc_disable(struct drm_crtc *crtc)
3040
{
3041
    struct drm_device *dev = crtc->dev;
3042
    struct drm_i915_private *dev_priv = dev->dev_private;
3043
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3044
    int pipe = intel_crtc->pipe;
3045
    int plane = intel_crtc->plane;
3046
    u32 reg, temp;
3047
 
3048
    if (!intel_crtc->active)
3049
        return;
3050
 
2336 Serge 3051
    ENTER();
3052
 
2327 Serge 3053
    intel_crtc_wait_for_pending_flips(crtc);
3054
//    drm_vblank_off(dev, pipe);
3055
//    intel_crtc_update_cursor(crtc, false);
3056
 
3057
    intel_disable_plane(dev_priv, plane, pipe);
3058
 
3059
    if (dev_priv->cfb_plane == plane)
3060
        intel_disable_fbc(dev);
3061
 
3062
    intel_disable_pipe(dev_priv, pipe);
3063
 
3064
    /* Disable PF */
3065
    I915_WRITE(PF_CTL(pipe), 0);
3066
    I915_WRITE(PF_WIN_SZ(pipe), 0);
3067
 
3068
    ironlake_fdi_disable(crtc);
3069
 
3070
    /* This is a horrible layering violation; we should be doing this in
3071
     * the connector/encoder ->prepare instead, but we don't always have
3072
     * enough information there about the config to know whether it will
3073
     * actually be necessary or just cause undesired flicker.
3074
     */
3075
    intel_disable_pch_ports(dev_priv, pipe);
3076
 
3077
    intel_disable_transcoder(dev_priv, pipe);
3078
 
3079
    if (HAS_PCH_CPT(dev)) {
3080
        /* disable TRANS_DP_CTL */
3081
        reg = TRANS_DP_CTL(pipe);
3082
        temp = I915_READ(reg);
3083
        temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3084
        temp |= TRANS_DP_PORT_SEL_NONE;
3085
        I915_WRITE(reg, temp);
3086
 
3087
        /* disable DPLL_SEL */
3088
        temp = I915_READ(PCH_DPLL_SEL);
3089
        switch (pipe) {
3090
        case 0:
2342 Serge 3091
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2327 Serge 3092
            break;
3093
        case 1:
3094
            temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3095
            break;
3096
        case 2:
2342 Serge 3097
			/* C shares PLL A or B */
2327 Serge 3098
            temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3099
            break;
3100
        default:
3101
            BUG(); /* wtf */
3102
        }
3103
        I915_WRITE(PCH_DPLL_SEL, temp);
3104
    }
3105
 
3106
    /* disable PCH DPLL */
2342 Serge 3107
	if (!intel_crtc->no_pll)
3108
    	intel_disable_pch_pll(dev_priv, pipe);
2327 Serge 3109
 
3110
    /* Switch from PCDclk to Rawclk */
3111
    reg = FDI_RX_CTL(pipe);
3112
    temp = I915_READ(reg);
3113
    I915_WRITE(reg, temp & ~FDI_PCDCLK);
3114
 
3115
    /* Disable CPU FDI TX PLL */
3116
    reg = FDI_TX_CTL(pipe);
3117
    temp = I915_READ(reg);
3118
    I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3119
 
3120
    POSTING_READ(reg);
3121
    udelay(100);
3122
 
3123
    reg = FDI_RX_CTL(pipe);
3124
    temp = I915_READ(reg);
3125
    I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3126
 
3127
    /* Wait for the clocks to turn off. */
3128
    POSTING_READ(reg);
3129
    udelay(100);
3130
 
3131
    intel_crtc->active = false;
3132
    intel_update_watermarks(dev);
3133
 
3134
    mutex_lock(&dev->struct_mutex);
3135
    intel_update_fbc(dev);
3136
    intel_clear_scanline_wait(dev);
3137
    mutex_unlock(&dev->struct_mutex);
2336 Serge 3138
 
3139
    LEAVE();
3140
 
2327 Serge 3141
}
3142
 
3143
static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3144
{
3145
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3146
    int pipe = intel_crtc->pipe;
3147
    int plane = intel_crtc->plane;
3148
 
3149
    /* XXX: When our outputs are all unaware of DPMS modes other than off
3150
     * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3151
     */
3152
    switch (mode) {
3153
    case DRM_MODE_DPMS_ON:
3154
    case DRM_MODE_DPMS_STANDBY:
3155
    case DRM_MODE_DPMS_SUSPEND:
3156
        DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3157
        ironlake_crtc_enable(crtc);
3158
        break;
3159
 
3160
    case DRM_MODE_DPMS_OFF:
3161
        DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3162
        ironlake_crtc_disable(crtc);
3163
        break;
3164
    }
3165
}
3166
 
3167
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3168
{
3169
	if (!enable && intel_crtc->overlay) {
3170
		struct drm_device *dev = intel_crtc->base.dev;
3171
		struct drm_i915_private *dev_priv = dev->dev_private;
3172
 
3173
		mutex_lock(&dev->struct_mutex);
3174
		dev_priv->mm.interruptible = false;
3175
//       (void) intel_overlay_switch_off(intel_crtc->overlay);
3176
		dev_priv->mm.interruptible = true;
3177
		mutex_unlock(&dev->struct_mutex);
3178
	}
3179
 
3180
	/* Let userspace switch the overlay on again. In most cases userspace
3181
	 * has to recompute where to put it anyway.
3182
	 */
3183
}
3184
 
3185
static void i9xx_crtc_enable(struct drm_crtc *crtc)
3186
{
3187
    struct drm_device *dev = crtc->dev;
3188
    struct drm_i915_private *dev_priv = dev->dev_private;
3189
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190
    int pipe = intel_crtc->pipe;
3191
    int plane = intel_crtc->plane;
3192
 
3193
    if (intel_crtc->active)
3194
        return;
3195
 
3196
    intel_crtc->active = true;
3197
    intel_update_watermarks(dev);
3198
 
3199
    intel_enable_pll(dev_priv, pipe);
3200
    intel_enable_pipe(dev_priv, pipe, false);
3201
    intel_enable_plane(dev_priv, plane, pipe);
3202
 
3203
    intel_crtc_load_lut(crtc);
3204
    intel_update_fbc(dev);
3205
 
3206
    /* Give the overlay scaler a chance to enable if it's on this pipe */
3207
    intel_crtc_dpms_overlay(intel_crtc, true);
3208
//    intel_crtc_update_cursor(crtc, true);
3209
}
3210
 
3211
static void i9xx_crtc_disable(struct drm_crtc *crtc)
3212
{
3213
    struct drm_device *dev = crtc->dev;
3214
    struct drm_i915_private *dev_priv = dev->dev_private;
3215
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216
    int pipe = intel_crtc->pipe;
3217
    int plane = intel_crtc->plane;
3218
 
3219
    if (!intel_crtc->active)
3220
        return;
3221
 
3222
    /* Give the overlay scaler a chance to disable if it's on this pipe */
3223
    intel_crtc_wait_for_pending_flips(crtc);
3224
//    drm_vblank_off(dev, pipe);
3225
    intel_crtc_dpms_overlay(intel_crtc, false);
3226
//    intel_crtc_update_cursor(crtc, false);
3227
 
3228
    if (dev_priv->cfb_plane == plane)
3229
        intel_disable_fbc(dev);
3230
 
3231
    intel_disable_plane(dev_priv, plane, pipe);
3232
    intel_disable_pipe(dev_priv, pipe);
3233
    intel_disable_pll(dev_priv, pipe);
3234
 
3235
    intel_crtc->active = false;
3236
    intel_update_fbc(dev);
3237
    intel_update_watermarks(dev);
3238
    intel_clear_scanline_wait(dev);
3239
}
3240
 
3241
static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3242
{
3243
    /* XXX: When our outputs are all unaware of DPMS modes other than off
3244
     * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3245
     */
3246
    switch (mode) {
3247
    case DRM_MODE_DPMS_ON:
3248
    case DRM_MODE_DPMS_STANDBY:
3249
    case DRM_MODE_DPMS_SUSPEND:
3250
        i9xx_crtc_enable(crtc);
3251
        break;
3252
    case DRM_MODE_DPMS_OFF:
3253
        i9xx_crtc_disable(crtc);
3254
        break;
3255
    }
3256
}
3257
 
2330 Serge 3258
/**
3259
 * Sets the power management mode of the pipe and plane.
3260
 */
3261
static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3262
{
3263
	struct drm_device *dev = crtc->dev;
3264
	struct drm_i915_private *dev_priv = dev->dev_private;
3265
	struct drm_i915_master_private *master_priv;
3266
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267
	int pipe = intel_crtc->pipe;
3268
	bool enabled;
2327 Serge 3269
 
2330 Serge 3270
	if (intel_crtc->dpms_mode == mode)
3271
		return;
2327 Serge 3272
 
2330 Serge 3273
	intel_crtc->dpms_mode = mode;
2327 Serge 3274
 
2330 Serge 3275
	dev_priv->display.dpms(crtc, mode);
2327 Serge 3276
 
2340 Serge 3277
#if 0
2330 Serge 3278
	if (!dev->primary->master)
3279
		return;
2327 Serge 3280
 
2330 Serge 3281
	master_priv = dev->primary->master->driver_priv;
3282
	if (!master_priv->sarea_priv)
3283
		return;
2327 Serge 3284
 
2330 Serge 3285
	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2327 Serge 3286
 
2330 Serge 3287
	switch (pipe) {
3288
	case 0:
3289
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3290
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3291
		break;
3292
	case 1:
3293
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3294
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3295
		break;
3296
	default:
3297
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3298
		break;
3299
	}
2340 Serge 3300
#endif
3301
 
2330 Serge 3302
}
2327 Serge 3303
 
2330 Serge 3304
static void intel_crtc_disable(struct drm_crtc *crtc)
3305
{
3306
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3307
	struct drm_device *dev = crtc->dev;
2327 Serge 3308
 
2330 Serge 3309
	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327 Serge 3310
 
2330 Serge 3311
	if (crtc->fb) {
3312
		mutex_lock(&dev->struct_mutex);
2344 Serge 3313
		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2330 Serge 3314
		mutex_unlock(&dev->struct_mutex);
3315
	}
3316
}
2327 Serge 3317
 
2330 Serge 3318
/* Prepare for a mode set.
3319
 *
3320
 * Note we could be a lot smarter here.  We need to figure out which outputs
3321
 * will be enabled, which disabled (in short, how the config will changes)
3322
 * and perform the minimum necessary steps to accomplish that, e.g. updating
3323
 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3324
 * panel fitting is in the proper state, etc.
3325
 */
3326
static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3327
{
3328
	i9xx_crtc_disable(crtc);
3329
}
2327 Serge 3330
 
2330 Serge 3331
static void i9xx_crtc_commit(struct drm_crtc *crtc)
3332
{
3333
	i9xx_crtc_enable(crtc);
3334
}
2327 Serge 3335
 
2330 Serge 3336
static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3337
{
3338
	ironlake_crtc_disable(crtc);
3339
}
2327 Serge 3340
 
2330 Serge 3341
static void ironlake_crtc_commit(struct drm_crtc *crtc)
3342
{
3343
	ironlake_crtc_enable(crtc);
3344
}
2327 Serge 3345
 
2342 Serge 3346
void intel_encoder_prepare(struct drm_encoder *encoder)
2330 Serge 3347
{
3348
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3349
	/* lvds has its own version of prepare see intel_lvds_prepare */
3350
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3351
}
2327 Serge 3352
 
2342 Serge 3353
void intel_encoder_commit(struct drm_encoder *encoder)
2330 Serge 3354
{
3355
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2342 Serge 3356
	struct drm_device *dev = encoder->dev;
3357
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3358
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3359
 
2330 Serge 3360
	/* lvds has its own version of commit see intel_lvds_commit */
3361
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2342 Serge 3362
 
3363
	if (HAS_PCH_CPT(dev))
3364
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
2330 Serge 3365
}
2327 Serge 3366
 
2330 Serge 3367
void intel_encoder_destroy(struct drm_encoder *encoder)
3368
{
3369
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3370
 
3371
	drm_encoder_cleanup(encoder);
3372
	kfree(intel_encoder);
3373
}
3374
 
3375
static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3376
				  struct drm_display_mode *mode,
3377
				  struct drm_display_mode *adjusted_mode)
3378
{
3379
	struct drm_device *dev = crtc->dev;
3380
 
3381
	if (HAS_PCH_SPLIT(dev)) {
3382
		/* FDI link clock is fixed at 2.7G */
3383
		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3384
			return false;
3385
	}
3386
 
3387
	/* XXX some encoders set the crtcinfo, others don't.
3388
	 * Obviously we need some form of conflict resolution here...
3389
	 */
3390
	if (adjusted_mode->crtc_htotal == 0)
3391
		drm_mode_set_crtcinfo(adjusted_mode, 0);
3392
 
3393
	return true;
3394
}
3395
 
2327 Serge 3396
static int i945_get_display_clock_speed(struct drm_device *dev)
3397
{
3398
	return 400000;
3399
}
3400
 
3401
static int i915_get_display_clock_speed(struct drm_device *dev)
3402
{
3403
	return 333000;
3404
}
3405
 
3406
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3407
{
3408
	return 200000;
3409
}
3410
 
3411
static int i915gm_get_display_clock_speed(struct drm_device *dev)
3412
{
3413
	u16 gcfgc = 0;
3414
 
3415
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3416
 
3417
	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3418
		return 133000;
3419
	else {
3420
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3421
		case GC_DISPLAY_CLOCK_333_MHZ:
3422
			return 333000;
3423
		default:
3424
		case GC_DISPLAY_CLOCK_190_200_MHZ:
3425
			return 190000;
3426
		}
3427
	}
3428
}
3429
 
3430
static int i865_get_display_clock_speed(struct drm_device *dev)
3431
{
3432
	return 266000;
3433
}
3434
 
3435
static int i855_get_display_clock_speed(struct drm_device *dev)
3436
{
3437
	u16 hpllcc = 0;
3438
	/* Assume that the hardware is in the high speed state.  This
3439
	 * should be the default.
3440
	 */
3441
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3442
	case GC_CLOCK_133_200:
3443
	case GC_CLOCK_100_200:
3444
		return 200000;
3445
	case GC_CLOCK_166_250:
3446
		return 250000;
3447
	case GC_CLOCK_100_133:
3448
		return 133000;
3449
	}
3450
 
3451
	/* Shouldn't happen */
3452
	return 0;
3453
}
3454
 
3455
static int i830_get_display_clock_speed(struct drm_device *dev)
3456
{
3457
	return 133000;
3458
}
3459
 
3460
struct fdi_m_n {
3461
    u32        tu;
3462
    u32        gmch_m;
3463
    u32        gmch_n;
3464
    u32        link_m;
3465
    u32        link_n;
3466
};
3467
 
3468
static void
3469
fdi_reduce_ratio(u32 *num, u32 *den)
3470
{
3471
	while (*num > 0xffffff || *den > 0xffffff) {
3472
		*num >>= 1;
3473
		*den >>= 1;
3474
	}
3475
}
3476
 
3477
static void
3478
ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3479
		     int link_clock, struct fdi_m_n *m_n)
3480
{
3481
	m_n->tu = 64; /* default size */
3482
 
3483
	/* BUG_ON(pixel_clock > INT_MAX / 36); */
3484
	m_n->gmch_m = bits_per_pixel * pixel_clock;
3485
	m_n->gmch_n = link_clock * nlanes * 8;
3486
	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3487
 
3488
	m_n->link_m = pixel_clock;
3489
	m_n->link_n = link_clock;
3490
	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3491
}
3492
 
3493
 
3494
struct intel_watermark_params {
3495
    unsigned long fifo_size;
3496
    unsigned long max_wm;
3497
    unsigned long default_wm;
3498
    unsigned long guard_size;
3499
    unsigned long cacheline_size;
3500
};
3501
 
3502
/* Pineview has different values for various configs */
3503
static const struct intel_watermark_params pineview_display_wm = {
3504
    PINEVIEW_DISPLAY_FIFO,
3505
    PINEVIEW_MAX_WM,
3506
    PINEVIEW_DFT_WM,
3507
    PINEVIEW_GUARD_WM,
3508
    PINEVIEW_FIFO_LINE_SIZE
3509
};
3510
static const struct intel_watermark_params pineview_display_hplloff_wm = {
3511
    PINEVIEW_DISPLAY_FIFO,
3512
    PINEVIEW_MAX_WM,
3513
    PINEVIEW_DFT_HPLLOFF_WM,
3514
    PINEVIEW_GUARD_WM,
3515
    PINEVIEW_FIFO_LINE_SIZE
3516
};
3517
static const struct intel_watermark_params pineview_cursor_wm = {
3518
    PINEVIEW_CURSOR_FIFO,
3519
    PINEVIEW_CURSOR_MAX_WM,
3520
    PINEVIEW_CURSOR_DFT_WM,
3521
    PINEVIEW_CURSOR_GUARD_WM,
3522
    PINEVIEW_FIFO_LINE_SIZE,
3523
};
3524
static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3525
    PINEVIEW_CURSOR_FIFO,
3526
    PINEVIEW_CURSOR_MAX_WM,
3527
    PINEVIEW_CURSOR_DFT_WM,
3528
    PINEVIEW_CURSOR_GUARD_WM,
3529
    PINEVIEW_FIFO_LINE_SIZE
3530
};
3531
static const struct intel_watermark_params g4x_wm_info = {
3532
    G4X_FIFO_SIZE,
3533
    G4X_MAX_WM,
3534
    G4X_MAX_WM,
3535
    2,
3536
    G4X_FIFO_LINE_SIZE,
3537
};
3538
static const struct intel_watermark_params g4x_cursor_wm_info = {
3539
    I965_CURSOR_FIFO,
3540
    I965_CURSOR_MAX_WM,
3541
    I965_CURSOR_DFT_WM,
3542
    2,
3543
    G4X_FIFO_LINE_SIZE,
3544
};
3545
static const struct intel_watermark_params i965_cursor_wm_info = {
3546
    I965_CURSOR_FIFO,
3547
    I965_CURSOR_MAX_WM,
3548
    I965_CURSOR_DFT_WM,
3549
    2,
3550
    I915_FIFO_LINE_SIZE,
3551
};
3552
static const struct intel_watermark_params i945_wm_info = {
3553
    I945_FIFO_SIZE,
3554
    I915_MAX_WM,
3555
    1,
3556
    2,
3557
    I915_FIFO_LINE_SIZE
3558
};
3559
static const struct intel_watermark_params i915_wm_info = {
3560
    I915_FIFO_SIZE,
3561
    I915_MAX_WM,
3562
    1,
3563
    2,
3564
    I915_FIFO_LINE_SIZE
3565
};
3566
static const struct intel_watermark_params i855_wm_info = {
3567
    I855GM_FIFO_SIZE,
3568
    I915_MAX_WM,
3569
    1,
3570
    2,
3571
    I830_FIFO_LINE_SIZE
3572
};
3573
static const struct intel_watermark_params i830_wm_info = {
3574
    I830_FIFO_SIZE,
3575
    I915_MAX_WM,
3576
    1,
3577
    2,
3578
    I830_FIFO_LINE_SIZE
3579
};
3580
 
3581
static const struct intel_watermark_params ironlake_display_wm_info = {
3582
    ILK_DISPLAY_FIFO,
3583
    ILK_DISPLAY_MAXWM,
3584
    ILK_DISPLAY_DFTWM,
3585
    2,
3586
    ILK_FIFO_LINE_SIZE
3587
};
3588
static const struct intel_watermark_params ironlake_cursor_wm_info = {
3589
    ILK_CURSOR_FIFO,
3590
    ILK_CURSOR_MAXWM,
3591
    ILK_CURSOR_DFTWM,
3592
    2,
3593
    ILK_FIFO_LINE_SIZE
3594
};
3595
static const struct intel_watermark_params ironlake_display_srwm_info = {
3596
    ILK_DISPLAY_SR_FIFO,
3597
    ILK_DISPLAY_MAX_SRWM,
3598
    ILK_DISPLAY_DFT_SRWM,
3599
    2,
3600
    ILK_FIFO_LINE_SIZE
3601
};
3602
static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3603
    ILK_CURSOR_SR_FIFO,
3604
    ILK_CURSOR_MAX_SRWM,
3605
    ILK_CURSOR_DFT_SRWM,
3606
    2,
3607
    ILK_FIFO_LINE_SIZE
3608
};
3609
 
3610
static const struct intel_watermark_params sandybridge_display_wm_info = {
3611
    SNB_DISPLAY_FIFO,
3612
    SNB_DISPLAY_MAXWM,
3613
    SNB_DISPLAY_DFTWM,
3614
    2,
3615
    SNB_FIFO_LINE_SIZE
3616
};
3617
static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3618
    SNB_CURSOR_FIFO,
3619
    SNB_CURSOR_MAXWM,
3620
    SNB_CURSOR_DFTWM,
3621
    2,
3622
    SNB_FIFO_LINE_SIZE
3623
};
3624
static const struct intel_watermark_params sandybridge_display_srwm_info = {
3625
    SNB_DISPLAY_SR_FIFO,
3626
    SNB_DISPLAY_MAX_SRWM,
3627
    SNB_DISPLAY_DFT_SRWM,
3628
    2,
3629
    SNB_FIFO_LINE_SIZE
3630
};
3631
static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3632
    SNB_CURSOR_SR_FIFO,
3633
    SNB_CURSOR_MAX_SRWM,
3634
    SNB_CURSOR_DFT_SRWM,
3635
    2,
3636
    SNB_FIFO_LINE_SIZE
3637
};
3638
 
3639
 
3640
/**
3641
 * intel_calculate_wm - calculate watermark level
3642
 * @clock_in_khz: pixel clock
3643
 * @wm: chip FIFO params
3644
 * @pixel_size: display pixel size
3645
 * @latency_ns: memory latency for the platform
3646
 *
3647
 * Calculate the watermark level (the level at which the display plane will
3648
 * start fetching from memory again).  Each chip has a different display
3649
 * FIFO size and allocation, so the caller needs to figure that out and pass
3650
 * in the correct intel_watermark_params structure.
3651
 *
3652
 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3653
 * on the pixel size.  When it reaches the watermark level, it'll start
3654
 * fetching FIFO line sized based chunks from memory until the FIFO fills
3655
 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3656
 * will occur, and a display engine hang could result.
3657
 */
3658
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3659
                    const struct intel_watermark_params *wm,
3660
                    int fifo_size,
3661
                    int pixel_size,
3662
                    unsigned long latency_ns)
3663
{
3664
    long entries_required, wm_size;
3665
 
3666
    /*
3667
     * Note: we need to make sure we don't overflow for various clock &
3668
     * latency values.
3669
     * clocks go from a few thousand to several hundred thousand.
3670
     * latency is usually a few thousand
3671
     */
3672
    entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3673
        1000;
3674
    entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3675
 
3676
    DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3677
 
3678
    wm_size = fifo_size - (entries_required + wm->guard_size);
3679
 
3680
    DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3681
 
3682
    /* Don't promote wm_size to unsigned... */
3683
    if (wm_size > (long)wm->max_wm)
3684
        wm_size = wm->max_wm;
3685
    if (wm_size <= 0)
3686
        wm_size = wm->default_wm;
3687
    return wm_size;
3688
}
3689
 
3690
struct cxsr_latency {
3691
    int is_desktop;
3692
    int is_ddr3;
3693
    unsigned long fsb_freq;
3694
    unsigned long mem_freq;
3695
    unsigned long display_sr;
3696
    unsigned long display_hpll_disable;
3697
    unsigned long cursor_sr;
3698
    unsigned long cursor_hpll_disable;
3699
};
3700
 
3701
static const struct cxsr_latency cxsr_latency_table[] = {
3702
    {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3703
    {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3704
    {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3705
    {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3706
    {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3707
 
3708
    {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3709
    {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3710
    {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3711
    {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3712
    {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3713
 
3714
    {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3715
    {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3716
    {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3717
    {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3718
    {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3719
 
3720
    {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3721
    {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3722
    {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3723
    {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3724
    {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3725
 
3726
    {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3727
    {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3728
    {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3729
    {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3730
    {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3731
 
3732
    {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3733
    {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3734
    {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3735
    {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3736
    {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3737
};
3738
 
3739
static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3740
                             int is_ddr3,
3741
                             int fsb,
3742
                             int mem)
3743
{
3744
    const struct cxsr_latency *latency;
3745
    int i;
3746
 
3747
    if (fsb == 0 || mem == 0)
3748
        return NULL;
3749
 
3750
    for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3751
        latency = &cxsr_latency_table[i];
3752
        if (is_desktop == latency->is_desktop &&
3753
            is_ddr3 == latency->is_ddr3 &&
3754
            fsb == latency->fsb_freq && mem == latency->mem_freq)
3755
            return latency;
3756
    }
3757
 
3758
    DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3759
 
3760
    return NULL;
3761
}
3762
 
3763
static void pineview_disable_cxsr(struct drm_device *dev)
3764
{
3765
    struct drm_i915_private *dev_priv = dev->dev_private;
3766
 
3767
    /* deactivate cxsr */
3768
    I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3769
}
3770
 
3771
/*
3772
 * Latency for FIFO fetches is dependent on several factors:
3773
 *   - memory configuration (speed, channels)
3774
 *   - chipset
3775
 *   - current MCH state
3776
 * It can be fairly high in some situations, so here we assume a fairly
3777
 * pessimal value.  It's a tradeoff between extra memory fetches (if we
3778
 * set this value too high, the FIFO will fetch frequently to stay full)
3779
 * and power consumption (set it too low to save power and we might see
3780
 * FIFO underruns and display "flicker").
3781
 *
3782
 * A value of 5us seems to be a good balance; safe for very low end
3783
 * platforms but not overly aggressive on lower latency configs.
3784
 */
3785
static const int latency_ns = 5000;
3786
 
3787
static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3788
{
3789
	struct drm_i915_private *dev_priv = dev->dev_private;
3790
	uint32_t dsparb = I915_READ(DSPARB);
3791
	int size;
3792
 
3793
	size = dsparb & 0x7f;
3794
	if (plane)
3795
		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3796
 
3797
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3798
		      plane ? "B" : "A", size);
3799
 
3800
	return size;
3801
}
3802
 
3803
static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3804
{
3805
	struct drm_i915_private *dev_priv = dev->dev_private;
3806
	uint32_t dsparb = I915_READ(DSPARB);
3807
	int size;
3808
 
3809
	size = dsparb & 0x1ff;
3810
	if (plane)
3811
		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3812
	size >>= 1; /* Convert to cachelines */
3813
 
3814
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3815
		      plane ? "B" : "A", size);
3816
 
3817
	return size;
3818
}
3819
 
3820
static int i845_get_fifo_size(struct drm_device *dev, int plane)
3821
{
3822
	struct drm_i915_private *dev_priv = dev->dev_private;
3823
	uint32_t dsparb = I915_READ(DSPARB);
3824
	int size;
3825
 
3826
	size = dsparb & 0x7f;
3827
	size >>= 2; /* Convert to cachelines */
3828
 
3829
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3830
		      plane ? "B" : "A",
3831
		      size);
3832
 
3833
	return size;
3834
}
3835
 
3836
static int i830_get_fifo_size(struct drm_device *dev, int plane)
3837
{
3838
	struct drm_i915_private *dev_priv = dev->dev_private;
3839
	uint32_t dsparb = I915_READ(DSPARB);
3840
	int size;
3841
 
3842
	size = dsparb & 0x7f;
3843
	size >>= 1; /* Convert to cachelines */
3844
 
3845
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3846
		      plane ? "B" : "A", size);
3847
 
3848
	return size;
3849
}
3850
 
3851
static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3852
{
3853
    struct drm_crtc *crtc, *enabled = NULL;
3854
 
3855
    list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3856
        if (crtc->enabled && crtc->fb) {
3857
            if (enabled)
3858
                return NULL;
3859
            enabled = crtc;
3860
        }
3861
    }
3862
 
3863
    return enabled;
3864
}
3865
 
3866
static void pineview_update_wm(struct drm_device *dev)
3867
{
3868
	struct drm_i915_private *dev_priv = dev->dev_private;
3869
	struct drm_crtc *crtc;
3870
	const struct cxsr_latency *latency;
3871
	u32 reg;
3872
	unsigned long wm;
3873
 
3874
	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3875
					 dev_priv->fsb_freq, dev_priv->mem_freq);
3876
	if (!latency) {
3877
		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3878
		pineview_disable_cxsr(dev);
3879
		return;
3880
	}
3881
 
3882
	crtc = single_enabled_crtc(dev);
3883
	if (crtc) {
3884
		int clock = crtc->mode.clock;
3885
		int pixel_size = crtc->fb->bits_per_pixel / 8;
3886
 
3887
		/* Display SR */
3888
		wm = intel_calculate_wm(clock, &pineview_display_wm,
3889
					pineview_display_wm.fifo_size,
3890
					pixel_size, latency->display_sr);
3891
		reg = I915_READ(DSPFW1);
3892
		reg &= ~DSPFW_SR_MASK;
3893
		reg |= wm << DSPFW_SR_SHIFT;
3894
		I915_WRITE(DSPFW1, reg);
3895
		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3896
 
3897
		/* cursor SR */
3898
		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3899
					pineview_display_wm.fifo_size,
3900
					pixel_size, latency->cursor_sr);
3901
		reg = I915_READ(DSPFW3);
3902
		reg &= ~DSPFW_CURSOR_SR_MASK;
3903
		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3904
		I915_WRITE(DSPFW3, reg);
3905
 
3906
		/* Display HPLL off SR */
3907
		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3908
					pineview_display_hplloff_wm.fifo_size,
3909
					pixel_size, latency->display_hpll_disable);
3910
		reg = I915_READ(DSPFW3);
3911
		reg &= ~DSPFW_HPLL_SR_MASK;
3912
		reg |= wm & DSPFW_HPLL_SR_MASK;
3913
		I915_WRITE(DSPFW3, reg);
3914
 
3915
		/* cursor HPLL off SR */
3916
		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3917
					pineview_display_hplloff_wm.fifo_size,
3918
					pixel_size, latency->cursor_hpll_disable);
3919
		reg = I915_READ(DSPFW3);
3920
		reg &= ~DSPFW_HPLL_CURSOR_MASK;
3921
		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3922
		I915_WRITE(DSPFW3, reg);
3923
		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3924
 
3925
		/* activate cxsr */
3926
		I915_WRITE(DSPFW3,
3927
			   I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3928
		DRM_DEBUG_KMS("Self-refresh is enabled\n");
3929
	} else {
3930
		pineview_disable_cxsr(dev);
3931
		DRM_DEBUG_KMS("Self-refresh is disabled\n");
3932
	}
3933
}
3934
 
3935
static bool g4x_compute_wm0(struct drm_device *dev,
3936
                int plane,
3937
                const struct intel_watermark_params *display,
3938
                int display_latency_ns,
3939
                const struct intel_watermark_params *cursor,
3940
                int cursor_latency_ns,
3941
                int *plane_wm,
3942
                int *cursor_wm)
3943
{
3944
    struct drm_crtc *crtc;
3945
    int htotal, hdisplay, clock, pixel_size;
3946
    int line_time_us, line_count;
3947
    int entries, tlb_miss;
3948
 
3949
    crtc = intel_get_crtc_for_plane(dev, plane);
3950
    if (crtc->fb == NULL || !crtc->enabled) {
3951
        *cursor_wm = cursor->guard_size;
3952
        *plane_wm = display->guard_size;
3953
        return false;
3954
    }
3955
 
3956
    htotal = crtc->mode.htotal;
3957
    hdisplay = crtc->mode.hdisplay;
3958
    clock = crtc->mode.clock;
3959
    pixel_size = crtc->fb->bits_per_pixel / 8;
3960
 
3961
    /* Use the small buffer method to calculate plane watermark */
3962
    entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3963
    tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3964
    if (tlb_miss > 0)
3965
        entries += tlb_miss;
3966
    entries = DIV_ROUND_UP(entries, display->cacheline_size);
3967
    *plane_wm = entries + display->guard_size;
3968
    if (*plane_wm > (int)display->max_wm)
3969
        *plane_wm = display->max_wm;
3970
 
3971
    /* Use the large buffer method to calculate cursor watermark */
3972
    line_time_us = ((htotal * 1000) / clock);
3973
    line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3974
    entries = line_count * 64 * pixel_size;
3975
    tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3976
    if (tlb_miss > 0)
3977
        entries += tlb_miss;
3978
    entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3979
    *cursor_wm = entries + cursor->guard_size;
3980
    if (*cursor_wm > (int)cursor->max_wm)
3981
        *cursor_wm = (int)cursor->max_wm;
3982
 
3983
    return true;
3984
}
3985
 
3986
/*
3987
 * Check the wm result.
3988
 *
3989
 * If any calculated watermark values is larger than the maximum value that
3990
 * can be programmed into the associated watermark register, that watermark
3991
 * must be disabled.
3992
 */
3993
static bool g4x_check_srwm(struct drm_device *dev,
3994
			   int display_wm, int cursor_wm,
3995
			   const struct intel_watermark_params *display,
3996
			   const struct intel_watermark_params *cursor)
3997
{
3998
	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3999
		      display_wm, cursor_wm);
4000
 
4001
	if (display_wm > display->max_wm) {
4002
		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4003
			      display_wm, display->max_wm);
4004
		return false;
4005
	}
4006
 
4007
	if (cursor_wm > cursor->max_wm) {
4008
		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4009
			      cursor_wm, cursor->max_wm);
4010
		return false;
4011
	}
4012
 
4013
	if (!(display_wm || cursor_wm)) {
4014
		DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4015
		return false;
4016
	}
4017
 
4018
	return true;
4019
}
4020
 
4021
static bool g4x_compute_srwm(struct drm_device *dev,
4022
			     int plane,
4023
			     int latency_ns,
4024
			     const struct intel_watermark_params *display,
4025
			     const struct intel_watermark_params *cursor,
4026
			     int *display_wm, int *cursor_wm)
4027
{
4028
	struct drm_crtc *crtc;
4029
	int hdisplay, htotal, pixel_size, clock;
4030
	unsigned long line_time_us;
4031
	int line_count, line_size;
4032
	int small, large;
4033
	int entries;
4034
 
4035
	if (!latency_ns) {
4036
		*display_wm = *cursor_wm = 0;
4037
		return false;
4038
	}
4039
 
4040
	crtc = intel_get_crtc_for_plane(dev, plane);
4041
	hdisplay = crtc->mode.hdisplay;
4042
	htotal = crtc->mode.htotal;
4043
	clock = crtc->mode.clock;
4044
	pixel_size = crtc->fb->bits_per_pixel / 8;
4045
 
4046
	line_time_us = (htotal * 1000) / clock;
4047
	line_count = (latency_ns / line_time_us + 1000) / 1000;
4048
	line_size = hdisplay * pixel_size;
4049
 
4050
	/* Use the minimum of the small and large buffer method for primary */
4051
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4052
	large = line_count * line_size;
4053
 
4054
	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4055
	*display_wm = entries + display->guard_size;
4056
 
4057
	/* calculate the self-refresh watermark for display cursor */
4058
	entries = line_count * pixel_size * 64;
4059
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4060
	*cursor_wm = entries + cursor->guard_size;
4061
 
4062
	return g4x_check_srwm(dev,
4063
			      *display_wm, *cursor_wm,
4064
			      display, cursor);
4065
}
4066
 
4067
#define single_plane_enabled(mask) is_power_of_2(mask)
4068
 
4069
static void g4x_update_wm(struct drm_device *dev)
4070
{
4071
	static const int sr_latency_ns = 12000;
4072
	struct drm_i915_private *dev_priv = dev->dev_private;
4073
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4074
	int plane_sr, cursor_sr;
4075
	unsigned int enabled = 0;
4076
 
4077
	if (g4x_compute_wm0(dev, 0,
4078
			    &g4x_wm_info, latency_ns,
4079
			    &g4x_cursor_wm_info, latency_ns,
4080
			    &planea_wm, &cursora_wm))
4081
		enabled |= 1;
4082
 
4083
	if (g4x_compute_wm0(dev, 1,
4084
			    &g4x_wm_info, latency_ns,
4085
			    &g4x_cursor_wm_info, latency_ns,
4086
			    &planeb_wm, &cursorb_wm))
4087
		enabled |= 2;
4088
 
4089
	plane_sr = cursor_sr = 0;
4090
	if (single_plane_enabled(enabled) &&
4091
	    g4x_compute_srwm(dev, ffs(enabled) - 1,
4092
			     sr_latency_ns,
4093
			     &g4x_wm_info,
4094
			     &g4x_cursor_wm_info,
4095
			     &plane_sr, &cursor_sr))
4096
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4097
	else
4098
		I915_WRITE(FW_BLC_SELF,
4099
			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4100
 
4101
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4102
		      planea_wm, cursora_wm,
4103
		      planeb_wm, cursorb_wm,
4104
		      plane_sr, cursor_sr);
4105
 
4106
	I915_WRITE(DSPFW1,
4107
		   (plane_sr << DSPFW_SR_SHIFT) |
4108
		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4109
		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
4110
		   planea_wm);
4111
	I915_WRITE(DSPFW2,
4112
		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4113
		   (cursora_wm << DSPFW_CURSORA_SHIFT));
4114
	/* HPLL off in SR has some issues on G4x... disable it */
4115
	I915_WRITE(DSPFW3,
4116
		   (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4117
		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4118
}
4119
 
4120
static void i965_update_wm(struct drm_device *dev)
4121
{
4122
	struct drm_i915_private *dev_priv = dev->dev_private;
4123
	struct drm_crtc *crtc;
4124
	int srwm = 1;
4125
	int cursor_sr = 16;
4126
 
4127
	/* Calc sr entries for one plane configs */
4128
	crtc = single_enabled_crtc(dev);
4129
	if (crtc) {
4130
		/* self-refresh has much higher latency */
4131
		static const int sr_latency_ns = 12000;
4132
		int clock = crtc->mode.clock;
4133
		int htotal = crtc->mode.htotal;
4134
		int hdisplay = crtc->mode.hdisplay;
4135
		int pixel_size = crtc->fb->bits_per_pixel / 8;
4136
		unsigned long line_time_us;
4137
		int entries;
4138
 
4139
		line_time_us = ((htotal * 1000) / clock);
4140
 
4141
		/* Use ns/us then divide to preserve precision */
4142
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4143
			pixel_size * hdisplay;
4144
		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4145
		srwm = I965_FIFO_SIZE - entries;
4146
		if (srwm < 0)
4147
			srwm = 1;
4148
		srwm &= 0x1ff;
4149
		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4150
			      entries, srwm);
4151
 
4152
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4153
			pixel_size * 64;
4154
		entries = DIV_ROUND_UP(entries,
4155
					  i965_cursor_wm_info.cacheline_size);
4156
		cursor_sr = i965_cursor_wm_info.fifo_size -
4157
			(entries + i965_cursor_wm_info.guard_size);
4158
 
4159
		if (cursor_sr > i965_cursor_wm_info.max_wm)
4160
			cursor_sr = i965_cursor_wm_info.max_wm;
4161
 
4162
		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4163
			      "cursor %d\n", srwm, cursor_sr);
4164
 
4165
		if (IS_CRESTLINE(dev))
4166
			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4167
	} else {
4168
		/* Turn off self refresh if both pipes are enabled */
4169
		if (IS_CRESTLINE(dev))
4170
			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4171
				   & ~FW_BLC_SELF_EN);
4172
	}
4173
 
4174
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4175
		      srwm);
4176
 
4177
	/* 965 has limitations... */
4178
	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4179
		   (8 << 16) | (8 << 8) | (8 << 0));
4180
	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4181
	/* update cursor SR watermark */
4182
	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4183
}
4184
 
4185
static void i9xx_update_wm(struct drm_device *dev)
4186
{
4187
	struct drm_i915_private *dev_priv = dev->dev_private;
4188
	const struct intel_watermark_params *wm_info;
4189
	uint32_t fwater_lo;
4190
	uint32_t fwater_hi;
4191
	int cwm, srwm = 1;
4192
	int fifo_size;
4193
	int planea_wm, planeb_wm;
4194
	struct drm_crtc *crtc, *enabled = NULL;
4195
 
4196
	if (IS_I945GM(dev))
4197
		wm_info = &i945_wm_info;
4198
	else if (!IS_GEN2(dev))
4199
		wm_info = &i915_wm_info;
4200
	else
4201
		wm_info = &i855_wm_info;
4202
 
4203
	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4204
	crtc = intel_get_crtc_for_plane(dev, 0);
4205
	if (crtc->enabled && crtc->fb) {
4206
		planea_wm = intel_calculate_wm(crtc->mode.clock,
4207
					       wm_info, fifo_size,
4208
					       crtc->fb->bits_per_pixel / 8,
4209
					       latency_ns);
4210
		enabled = crtc;
4211
	} else
4212
		planea_wm = fifo_size - wm_info->guard_size;
4213
 
4214
	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4215
	crtc = intel_get_crtc_for_plane(dev, 1);
4216
	if (crtc->enabled && crtc->fb) {
4217
		planeb_wm = intel_calculate_wm(crtc->mode.clock,
4218
					       wm_info, fifo_size,
4219
					       crtc->fb->bits_per_pixel / 8,
4220
					       latency_ns);
4221
		if (enabled == NULL)
4222
			enabled = crtc;
4223
		else
4224
			enabled = NULL;
4225
	} else
4226
		planeb_wm = fifo_size - wm_info->guard_size;
4227
 
4228
	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4229
 
4230
	/*
4231
	 * Overlay gets an aggressive default since video jitter is bad.
4232
	 */
4233
	cwm = 2;
4234
 
4235
	/* Play safe and disable self-refresh before adjusting watermarks. */
4236
	if (IS_I945G(dev) || IS_I945GM(dev))
4237
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4238
	else if (IS_I915GM(dev))
4239
		I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4240
 
4241
	/* Calc sr entries for one plane configs */
4242
	if (HAS_FW_BLC(dev) && enabled) {
4243
		/* self-refresh has much higher latency */
4244
		static const int sr_latency_ns = 6000;
4245
		int clock = enabled->mode.clock;
4246
		int htotal = enabled->mode.htotal;
4247
		int hdisplay = enabled->mode.hdisplay;
4248
		int pixel_size = enabled->fb->bits_per_pixel / 8;
4249
		unsigned long line_time_us;
4250
		int entries;
4251
 
4252
		line_time_us = (htotal * 1000) / clock;
4253
 
4254
		/* Use ns/us then divide to preserve precision */
4255
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4256
			pixel_size * hdisplay;
4257
		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4258
		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4259
		srwm = wm_info->fifo_size - entries;
4260
		if (srwm < 0)
4261
			srwm = 1;
4262
 
4263
		if (IS_I945G(dev) || IS_I945GM(dev))
4264
			I915_WRITE(FW_BLC_SELF,
4265
				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4266
		else if (IS_I915GM(dev))
4267
			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4268
	}
4269
 
4270
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4271
		      planea_wm, planeb_wm, cwm, srwm);
4272
 
4273
	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4274
	fwater_hi = (cwm & 0x1f);
4275
 
4276
	/* Set request length to 8 cachelines per fetch */
4277
	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4278
	fwater_hi = fwater_hi | (1 << 8);
4279
 
4280
	I915_WRITE(FW_BLC, fwater_lo);
4281
	I915_WRITE(FW_BLC2, fwater_hi);
4282
 
4283
	if (HAS_FW_BLC(dev)) {
4284
		if (enabled) {
4285
			if (IS_I945G(dev) || IS_I945GM(dev))
4286
				I915_WRITE(FW_BLC_SELF,
4287
					   FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4288
			else if (IS_I915GM(dev))
4289
				I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4290
			DRM_DEBUG_KMS("memory self refresh enabled\n");
4291
		} else
4292
			DRM_DEBUG_KMS("memory self refresh disabled\n");
4293
	}
4294
}
4295
 
4296
static void i830_update_wm(struct drm_device *dev)
4297
{
4298
	struct drm_i915_private *dev_priv = dev->dev_private;
4299
	struct drm_crtc *crtc;
4300
	uint32_t fwater_lo;
4301
	int planea_wm;
4302
 
4303
	crtc = single_enabled_crtc(dev);
4304
	if (crtc == NULL)
4305
		return;
4306
 
4307
	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4308
				       dev_priv->display.get_fifo_size(dev, 0),
4309
				       crtc->fb->bits_per_pixel / 8,
4310
				       latency_ns);
4311
	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4312
	fwater_lo |= (3<<8) | planea_wm;
4313
 
4314
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4315
 
4316
	I915_WRITE(FW_BLC, fwater_lo);
4317
}
4318
 
4319
#define ILK_LP0_PLANE_LATENCY		700
4320
#define ILK_LP0_CURSOR_LATENCY		1300
4321
 
4322
/*
4323
 * Check the wm result.
4324
 *
4325
 * If any calculated watermark values is larger than the maximum value that
4326
 * can be programmed into the associated watermark register, that watermark
4327
 * must be disabled.
4328
 */
4329
static bool ironlake_check_srwm(struct drm_device *dev, int level,
4330
				int fbc_wm, int display_wm, int cursor_wm,
4331
				const struct intel_watermark_params *display,
4332
				const struct intel_watermark_params *cursor)
4333
{
4334
	struct drm_i915_private *dev_priv = dev->dev_private;
4335
 
4336
	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4337
		      " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4338
 
4339
	if (fbc_wm > SNB_FBC_MAX_SRWM) {
4340
		DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4341
			      fbc_wm, SNB_FBC_MAX_SRWM, level);
4342
 
4343
		/* fbc has it's own way to disable FBC WM */
4344
		I915_WRITE(DISP_ARB_CTL,
4345
			   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4346
		return false;
4347
	}
4348
 
4349
	if (display_wm > display->max_wm) {
4350
		DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4351
			      display_wm, SNB_DISPLAY_MAX_SRWM, level);
4352
		return false;
4353
	}
4354
 
4355
	if (cursor_wm > cursor->max_wm) {
4356
		DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4357
			      cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4358
		return false;
4359
	}
4360
 
4361
	if (!(fbc_wm || display_wm || cursor_wm)) {
4362
		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4363
		return false;
4364
	}
4365
 
4366
	return true;
4367
}
4368
 
4369
/*
4370
 * Compute watermark values of WM[1-3],
4371
 */
4372
static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4373
                  int latency_ns,
4374
                  const struct intel_watermark_params *display,
4375
                  const struct intel_watermark_params *cursor,
4376
                  int *fbc_wm, int *display_wm, int *cursor_wm)
4377
{
4378
    struct drm_crtc *crtc;
4379
    unsigned long line_time_us;
4380
    int hdisplay, htotal, pixel_size, clock;
4381
    int line_count, line_size;
4382
    int small, large;
4383
    int entries;
4384
 
4385
    if (!latency_ns) {
4386
        *fbc_wm = *display_wm = *cursor_wm = 0;
4387
        return false;
4388
    }
4389
 
4390
    crtc = intel_get_crtc_for_plane(dev, plane);
4391
    hdisplay = crtc->mode.hdisplay;
4392
    htotal = crtc->mode.htotal;
4393
    clock = crtc->mode.clock;
4394
    pixel_size = crtc->fb->bits_per_pixel / 8;
4395
 
4396
    line_time_us = (htotal * 1000) / clock;
4397
    line_count = (latency_ns / line_time_us + 1000) / 1000;
4398
    line_size = hdisplay * pixel_size;
4399
 
4400
    /* Use the minimum of the small and large buffer method for primary */
4401
    small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4402
    large = line_count * line_size;
4403
 
4404
    entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4405
    *display_wm = entries + display->guard_size;
4406
 
4407
    /*
4408
     * Spec says:
4409
     * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4410
     */
4411
    *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4412
 
4413
    /* calculate the self-refresh watermark for display cursor */
4414
    entries = line_count * pixel_size * 64;
4415
    entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4416
    *cursor_wm = entries + cursor->guard_size;
4417
 
4418
    return ironlake_check_srwm(dev, level,
4419
                   *fbc_wm, *display_wm, *cursor_wm,
4420
                   display, cursor);
4421
}
4422
 
4423
static void ironlake_update_wm(struct drm_device *dev)
4424
{
4425
	struct drm_i915_private *dev_priv = dev->dev_private;
4426
	int fbc_wm, plane_wm, cursor_wm;
4427
	unsigned int enabled;
4428
 
4429
	enabled = 0;
4430
	if (g4x_compute_wm0(dev, 0,
4431
			    &ironlake_display_wm_info,
4432
			    ILK_LP0_PLANE_LATENCY,
4433
			    &ironlake_cursor_wm_info,
4434
			    ILK_LP0_CURSOR_LATENCY,
4435
			    &plane_wm, &cursor_wm)) {
4436
		I915_WRITE(WM0_PIPEA_ILK,
4437
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4438
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4439
			      " plane %d, " "cursor: %d\n",
4440
			      plane_wm, cursor_wm);
4441
		enabled |= 1;
4442
	}
4443
 
4444
	if (g4x_compute_wm0(dev, 1,
4445
			    &ironlake_display_wm_info,
4446
			    ILK_LP0_PLANE_LATENCY,
4447
			    &ironlake_cursor_wm_info,
4448
			    ILK_LP0_CURSOR_LATENCY,
4449
			    &plane_wm, &cursor_wm)) {
4450
		I915_WRITE(WM0_PIPEB_ILK,
4451
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4453
			      " plane %d, cursor: %d\n",
4454
			      plane_wm, cursor_wm);
4455
		enabled |= 2;
4456
	}
4457
 
4458
	/*
4459
	 * Calculate and update the self-refresh watermark only when one
4460
	 * display plane is used.
4461
	 */
4462
	I915_WRITE(WM3_LP_ILK, 0);
4463
	I915_WRITE(WM2_LP_ILK, 0);
4464
	I915_WRITE(WM1_LP_ILK, 0);
4465
 
4466
	if (!single_plane_enabled(enabled))
4467
		return;
4468
	enabled = ffs(enabled) - 1;
4469
 
4470
	/* WM1 */
4471
	if (!ironlake_compute_srwm(dev, 1, enabled,
4472
				   ILK_READ_WM1_LATENCY() * 500,
4473
				   &ironlake_display_srwm_info,
4474
				   &ironlake_cursor_srwm_info,
4475
				   &fbc_wm, &plane_wm, &cursor_wm))
4476
		return;
4477
 
4478
	I915_WRITE(WM1_LP_ILK,
4479
		   WM1_LP_SR_EN |
4480
		   (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4481
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
4482
		   (plane_wm << WM1_LP_SR_SHIFT) |
4483
		   cursor_wm);
4484
 
4485
	/* WM2 */
4486
	if (!ironlake_compute_srwm(dev, 2, enabled,
4487
				   ILK_READ_WM2_LATENCY() * 500,
4488
				   &ironlake_display_srwm_info,
4489
				   &ironlake_cursor_srwm_info,
4490
				   &fbc_wm, &plane_wm, &cursor_wm))
4491
		return;
4492
 
4493
	I915_WRITE(WM2_LP_ILK,
4494
		   WM2_LP_EN |
4495
		   (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4496
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
4497
		   (plane_wm << WM1_LP_SR_SHIFT) |
4498
		   cursor_wm);
4499
 
4500
	/*
4501
	 * WM3 is unsupported on ILK, probably because we don't have latency
4502
	 * data for that power state
4503
	 */
4504
}
4505
 
2342 Serge 4506
void sandybridge_update_wm(struct drm_device *dev)
2327 Serge 4507
{
4508
	struct drm_i915_private *dev_priv = dev->dev_private;
4509
	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
4510
	int fbc_wm, plane_wm, cursor_wm;
4511
	unsigned int enabled;
4512
 
2336 Serge 4513
    ENTER();
4514
 
2327 Serge 4515
	enabled = 0;
4516
	if (g4x_compute_wm0(dev, 0,
4517
			    &sandybridge_display_wm_info, latency,
4518
			    &sandybridge_cursor_wm_info, latency,
4519
			    &plane_wm, &cursor_wm)) {
4520
		I915_WRITE(WM0_PIPEA_ILK,
4521
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4522
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4523
			      " plane %d, " "cursor: %d\n",
4524
			      plane_wm, cursor_wm);
4525
		enabled |= 1;
4526
	}
4527
 
4528
	if (g4x_compute_wm0(dev, 1,
4529
			    &sandybridge_display_wm_info, latency,
4530
			    &sandybridge_cursor_wm_info, latency,
4531
			    &plane_wm, &cursor_wm)) {
4532
		I915_WRITE(WM0_PIPEB_ILK,
4533
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4535
			      " plane %d, cursor: %d\n",
4536
			      plane_wm, cursor_wm);
4537
		enabled |= 2;
4538
	}
4539
 
2342 Serge 4540
	/* IVB has 3 pipes */
4541
	if (IS_IVYBRIDGE(dev) &&
4542
	    g4x_compute_wm0(dev, 2,
4543
			    &sandybridge_display_wm_info, latency,
4544
			    &sandybridge_cursor_wm_info, latency,
4545
			    &plane_wm, &cursor_wm)) {
4546
		I915_WRITE(WM0_PIPEC_IVB,
4547
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4548
		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4549
			      " plane %d, cursor: %d\n",
4550
			      plane_wm, cursor_wm);
4551
		enabled |= 3;
4552
	}
4553
 
2327 Serge 4554
	/*
4555
	 * Calculate and update the self-refresh watermark only when one
4556
	 * display plane is used.
4557
	 *
4558
	 * SNB support 3 levels of watermark.
4559
	 *
4560
	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4561
	 * and disabled in the descending order
4562
	 *
4563
	 */
4564
	I915_WRITE(WM3_LP_ILK, 0);
4565
	I915_WRITE(WM2_LP_ILK, 0);
4566
	I915_WRITE(WM1_LP_ILK, 0);
4567
 
2342 Serge 4568
	if (!single_plane_enabled(enabled) ||
4569
	    dev_priv->sprite_scaling_enabled)
2327 Serge 4570
		return;
4571
	enabled = ffs(enabled) - 1;
4572
 
4573
	/* WM1 */
4574
	if (!ironlake_compute_srwm(dev, 1, enabled,
4575
				   SNB_READ_WM1_LATENCY() * 500,
4576
				   &sandybridge_display_srwm_info,
4577
				   &sandybridge_cursor_srwm_info,
4578
				   &fbc_wm, &plane_wm, &cursor_wm))
4579
		return;
4580
 
4581
	I915_WRITE(WM1_LP_ILK,
4582
		   WM1_LP_SR_EN |
4583
		   (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4584
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
4585
		   (plane_wm << WM1_LP_SR_SHIFT) |
4586
		   cursor_wm);
4587
 
4588
	/* WM2 */
4589
	if (!ironlake_compute_srwm(dev, 2, enabled,
4590
				   SNB_READ_WM2_LATENCY() * 500,
4591
				   &sandybridge_display_srwm_info,
4592
				   &sandybridge_cursor_srwm_info,
4593
				   &fbc_wm, &plane_wm, &cursor_wm))
4594
		return;
4595
 
4596
	I915_WRITE(WM2_LP_ILK,
4597
		   WM2_LP_EN |
4598
		   (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4599
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
4600
		   (plane_wm << WM1_LP_SR_SHIFT) |
4601
		   cursor_wm);
4602
 
4603
	/* WM3 */
4604
	if (!ironlake_compute_srwm(dev, 3, enabled,
4605
				   SNB_READ_WM3_LATENCY() * 500,
4606
				   &sandybridge_display_srwm_info,
4607
				   &sandybridge_cursor_srwm_info,
4608
				   &fbc_wm, &plane_wm, &cursor_wm))
4609
		return;
4610
 
4611
	I915_WRITE(WM3_LP_ILK,
4612
		   WM3_LP_EN |
4613
		   (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4614
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
4615
		   (plane_wm << WM1_LP_SR_SHIFT) |
4616
		   cursor_wm);
2342 Serge 4617
}
2336 Serge 4618
 
2342 Serge 4619
static bool
4620
sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4621
			      uint32_t sprite_width, int pixel_size,
4622
			      const struct intel_watermark_params *display,
4623
			      int display_latency_ns, int *sprite_wm)
4624
{
4625
	struct drm_crtc *crtc;
4626
	int clock;
4627
	int entries, tlb_miss;
2336 Serge 4628
 
2342 Serge 4629
	crtc = intel_get_crtc_for_plane(dev, plane);
4630
	if (crtc->fb == NULL || !crtc->enabled) {
4631
		*sprite_wm = display->guard_size;
4632
		return false;
4633
	}
4634
 
4635
	clock = crtc->mode.clock;
4636
 
4637
	/* Use the small buffer method to calculate the sprite watermark */
4638
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4639
	tlb_miss = display->fifo_size*display->cacheline_size -
4640
		sprite_width * 8;
4641
	if (tlb_miss > 0)
4642
		entries += tlb_miss;
4643
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
4644
	*sprite_wm = entries + display->guard_size;
4645
	if (*sprite_wm > (int)display->max_wm)
4646
		*sprite_wm = display->max_wm;
4647
 
4648
	return true;
2327 Serge 4649
}
4650
 
2342 Serge 4651
static bool
4652
sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4653
				uint32_t sprite_width, int pixel_size,
4654
				const struct intel_watermark_params *display,
4655
				int latency_ns, int *sprite_wm)
4656
{
4657
	struct drm_crtc *crtc;
4658
	unsigned long line_time_us;
4659
	int clock;
4660
	int line_count, line_size;
4661
	int small, large;
4662
	int entries;
4663
 
4664
	if (!latency_ns) {
4665
		*sprite_wm = 0;
4666
		return false;
4667
	}
4668
 
4669
	crtc = intel_get_crtc_for_plane(dev, plane);
4670
	clock = crtc->mode.clock;
4671
 
4672
	line_time_us = (sprite_width * 1000) / clock;
4673
	line_count = (latency_ns / line_time_us + 1000) / 1000;
4674
	line_size = sprite_width * pixel_size;
4675
 
4676
	/* Use the minimum of the small and large buffer method for primary */
4677
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4678
	large = line_count * line_size;
4679
 
4680
	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4681
	*sprite_wm = entries + display->guard_size;
4682
 
4683
	return *sprite_wm > 0x3ff ? false : true;
4684
}
4685
 
4686
static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4687
					 uint32_t sprite_width, int pixel_size)
4688
{
4689
	struct drm_i915_private *dev_priv = dev->dev_private;
4690
	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
4691
	int sprite_wm, reg;
4692
	int ret;
4693
 
4694
	switch (pipe) {
4695
	case 0:
4696
		reg = WM0_PIPEA_ILK;
4697
		break;
4698
	case 1:
4699
		reg = WM0_PIPEB_ILK;
4700
		break;
4701
	case 2:
4702
		reg = WM0_PIPEC_IVB;
4703
		break;
4704
	default:
4705
		return; /* bad pipe */
4706
	}
4707
 
4708
	ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4709
					    &sandybridge_display_wm_info,
4710
					    latency, &sprite_wm);
4711
	if (!ret) {
4712
		DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4713
			      pipe);
4714
		return;
4715
	}
4716
 
4717
	I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4718
	DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4719
 
4720
 
4721
	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4722
					      pixel_size,
4723
					      &sandybridge_display_srwm_info,
4724
					      SNB_READ_WM1_LATENCY() * 500,
4725
					      &sprite_wm);
4726
	if (!ret) {
4727
		DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4728
			      pipe);
4729
		return;
4730
	}
4731
	I915_WRITE(WM1S_LP_ILK, sprite_wm);
4732
 
4733
	/* Only IVB has two more LP watermarks for sprite */
4734
	if (!IS_IVYBRIDGE(dev))
4735
		return;
4736
 
4737
	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4738
					      pixel_size,
4739
					      &sandybridge_display_srwm_info,
4740
					      SNB_READ_WM2_LATENCY() * 500,
4741
					      &sprite_wm);
4742
	if (!ret) {
4743
		DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4744
			      pipe);
4745
		return;
4746
	}
4747
	I915_WRITE(WM2S_LP_IVB, sprite_wm);
4748
 
4749
	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4750
					      pixel_size,
4751
					      &sandybridge_display_srwm_info,
4752
					      SNB_READ_WM3_LATENCY() * 500,
4753
					      &sprite_wm);
4754
	if (!ret) {
4755
		DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4756
			      pipe);
4757
		return;
4758
	}
4759
	I915_WRITE(WM3S_LP_IVB, sprite_wm);
4760
}
4761
 
2327 Serge 4762
/**
4763
 * intel_update_watermarks - update FIFO watermark values based on current modes
4764
 *
4765
 * Calculate watermark values for the various WM regs based on current mode
4766
 * and plane configuration.
4767
 *
4768
 * There are several cases to deal with here:
4769
 *   - normal (i.e. non-self-refresh)
4770
 *   - self-refresh (SR) mode
4771
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
4772
 *   - lines are small relative to FIFO size (buffer can hold more than 2
4773
 *     lines), so need to account for TLB latency
4774
 *
4775
 *   The normal calculation is:
4776
 *     watermark = dotclock * bytes per pixel * latency
4777
 *   where latency is platform & configuration dependent (we assume pessimal
4778
 *   values here).
4779
 *
4780
 *   The SR calculation is:
4781
 *     watermark = (trunc(latency/line time)+1) * surface width *
4782
 *       bytes per pixel
4783
 *   where
4784
 *     line time = htotal / dotclock
4785
 *     surface width = hdisplay for normal plane and 64 for cursor
4786
 *   and latency is assumed to be high, as above.
4787
 *
4788
 * The final value programmed to the register should always be rounded up,
4789
 * and include an extra 2 entries to account for clock crossings.
4790
 *
4791
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
4792
 * to set the non-SR watermarks to 8.
4793
 */
4794
static void intel_update_watermarks(struct drm_device *dev)
4795
{
4796
	struct drm_i915_private *dev_priv = dev->dev_private;
2336 Serge 4797
    ENTER();
2327 Serge 4798
	if (dev_priv->display.update_wm)
4799
		dev_priv->display.update_wm(dev);
2336 Serge 4800
    LEAVE();
2327 Serge 4801
}
4802
 
2342 Serge 4803
void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4804
				    uint32_t sprite_width, int pixel_size)
4805
{
4806
	struct drm_i915_private *dev_priv = dev->dev_private;
4807
 
4808
	if (dev_priv->display.update_sprite_wm)
4809
		dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4810
						   pixel_size);
4811
}
4812
 
2327 Serge 4813
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4814
{
2342 Serge 4815
	if (i915_panel_use_ssc >= 0)
4816
		return i915_panel_use_ssc != 0;
4817
	return dev_priv->lvds_use_ssc
2327 Serge 4818
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4819
}
4820
 
4821
/**
4822
 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4823
 * @crtc: CRTC structure
2342 Serge 4824
 * @mode: requested mode
2327 Serge 4825
 *
4826
 * A pipe may be connected to one or more outputs.  Based on the depth of the
4827
 * attached framebuffer, choose a good color depth to use on the pipe.
4828
 *
4829
 * If possible, match the pipe depth to the fb depth.  In some cases, this
4830
 * isn't ideal, because the connected output supports a lesser or restricted
4831
 * set of depths.  Resolve that here:
4832
 *    LVDS typically supports only 6bpc, so clamp down in that case
4833
 *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4834
 *    Displays may support a restricted set as well, check EDID and clamp as
4835
 *      appropriate.
2342 Serge 4836
 *    DP may want to dither down to 6bpc to fit larger modes
2327 Serge 4837
 *
4838
 * RETURNS:
4839
 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4840
 * true if they don't match).
4841
 */
4842
static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
2342 Serge 4843
					 unsigned int *pipe_bpp,
4844
					 struct drm_display_mode *mode)
2327 Serge 4845
{
4846
	struct drm_device *dev = crtc->dev;
4847
	struct drm_i915_private *dev_priv = dev->dev_private;
4848
	struct drm_encoder *encoder;
4849
	struct drm_connector *connector;
4850
	unsigned int display_bpc = UINT_MAX, bpc;
4851
 
4852
	/* Walk the encoders & connectors on this crtc, get min bpc */
4853
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4854
		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4855
 
4856
		if (encoder->crtc != crtc)
4857
			continue;
4858
 
4859
		if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4860
			unsigned int lvds_bpc;
4861
 
4862
			if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4863
			    LVDS_A3_POWER_UP)
4864
				lvds_bpc = 8;
4865
			else
4866
				lvds_bpc = 6;
4867
 
4868
			if (lvds_bpc < display_bpc) {
2342 Serge 4869
				DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
2327 Serge 4870
				display_bpc = lvds_bpc;
4871
			}
4872
			continue;
4873
		}
4874
 
4875
		if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4876
			/* Use VBT settings if we have an eDP panel */
4877
			unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4878
 
4879
			if (edp_bpc < display_bpc) {
2342 Serge 4880
				DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
2327 Serge 4881
				display_bpc = edp_bpc;
4882
			}
4883
			continue;
4884
		}
4885
 
4886
		/* Not one of the known troublemakers, check the EDID */
4887
		list_for_each_entry(connector, &dev->mode_config.connector_list,
4888
				    head) {
4889
			if (connector->encoder != encoder)
4890
				continue;
4891
 
4892
			/* Don't use an invalid EDID bpc value */
4893
			if (connector->display_info.bpc &&
4894
			    connector->display_info.bpc < display_bpc) {
2342 Serge 4895
				DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
2327 Serge 4896
				display_bpc = connector->display_info.bpc;
4897
			}
4898
		}
4899
 
4900
		/*
4901
		 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4902
		 * through, clamp it down.  (Note: >12bpc will be caught below.)
4903
		 */
4904
		if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4905
			if (display_bpc > 8 && display_bpc < 12) {
2342 Serge 4906
				DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
2327 Serge 4907
				display_bpc = 12;
4908
			} else {
2342 Serge 4909
				DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
2327 Serge 4910
				display_bpc = 8;
4911
			}
4912
		}
4913
	}
4914
 
2342 Serge 4915
	if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4916
		DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4917
		display_bpc = 6;
4918
	}
4919
 
2327 Serge 4920
	/*
4921
	 * We could just drive the pipe at the highest bpc all the time and
4922
	 * enable dithering as needed, but that costs bandwidth.  So choose
4923
	 * the minimum value that expresses the full color range of the fb but
4924
	 * also stays within the max display bpc discovered above.
4925
	 */
4926
 
4927
	switch (crtc->fb->depth) {
4928
	case 8:
4929
		bpc = 8; /* since we go through a colormap */
4930
		break;
4931
	case 15:
4932
	case 16:
4933
		bpc = 6; /* min is 18bpp */
4934
		break;
4935
	case 24:
2342 Serge 4936
		bpc = 8;
2327 Serge 4937
		break;
4938
	case 30:
2342 Serge 4939
		bpc = 10;
2327 Serge 4940
		break;
4941
	case 48:
2342 Serge 4942
		bpc = 12;
2327 Serge 4943
		break;
4944
	default:
4945
		DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4946
		bpc = min((unsigned int)8, display_bpc);
4947
		break;
4948
	}
4949
 
2342 Serge 4950
	display_bpc = min(display_bpc, bpc);
4951
 
4952
	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
2327 Serge 4953
			 bpc, display_bpc);
4954
 
2342 Serge 4955
	*pipe_bpp = display_bpc * 3;
2327 Serge 4956
 
4957
	return display_bpc != bpc;
4958
}
4959
 
4960
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4961
                  struct drm_display_mode *mode,
4962
                  struct drm_display_mode *adjusted_mode,
4963
                  int x, int y,
4964
                  struct drm_framebuffer *old_fb)
4965
{
4966
    struct drm_device *dev = crtc->dev;
4967
    struct drm_i915_private *dev_priv = dev->dev_private;
4968
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969
    int pipe = intel_crtc->pipe;
4970
    int plane = intel_crtc->plane;
4971
    int refclk, num_connectors = 0;
4972
    intel_clock_t clock, reduced_clock;
4973
    u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4974
    bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4975
    bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4976
    struct drm_mode_config *mode_config = &dev->mode_config;
4977
    struct intel_encoder *encoder;
4978
    const intel_limit_t *limit;
4979
    int ret;
4980
    u32 temp;
4981
    u32 lvds_sync = 0;
4982
 
4983
    list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4984
        if (encoder->base.crtc != crtc)
4985
            continue;
4986
 
4987
        switch (encoder->type) {
4988
        case INTEL_OUTPUT_LVDS:
4989
            is_lvds = true;
4990
            break;
4991
        case INTEL_OUTPUT_SDVO:
4992
        case INTEL_OUTPUT_HDMI:
4993
            is_sdvo = true;
4994
            if (encoder->needs_tv_clock)
4995
                is_tv = true;
4996
            break;
4997
        case INTEL_OUTPUT_DVO:
4998
            is_dvo = true;
4999
            break;
5000
        case INTEL_OUTPUT_TVOUT:
5001
            is_tv = true;
5002
            break;
5003
        case INTEL_OUTPUT_ANALOG:
5004
            is_crt = true;
5005
            break;
5006
        case INTEL_OUTPUT_DISPLAYPORT:
5007
            is_dp = true;
5008
            break;
5009
        }
5010
 
5011
        num_connectors++;
5012
    }
5013
 
5014
    if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5015
        refclk = dev_priv->lvds_ssc_freq * 1000;
5016
        DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5017
                  refclk / 1000);
5018
    } else if (!IS_GEN2(dev)) {
5019
        refclk = 96000;
5020
    } else {
5021
        refclk = 48000;
5022
    }
5023
 
5024
    /*
5025
     * Returns a set of divisors for the desired target clock with the given
5026
     * refclk, or FALSE.  The returned values represent the clock equation:
5027
     * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5028
     */
5029
    limit = intel_limit(crtc, refclk);
5030
    ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5031
    if (!ok) {
5032
        DRM_ERROR("Couldn't find PLL settings for mode!\n");
5033
        return -EINVAL;
5034
    }
5035
 
5036
    /* Ensure that the cursor is valid for the new mode before changing... */
5037
//    intel_crtc_update_cursor(crtc, true);
5038
 
5039
    if (is_lvds && dev_priv->lvds_downclock_avail) {
5040
        has_reduced_clock = limit->find_pll(limit, crtc,
5041
                            dev_priv->lvds_downclock,
5042
                            refclk,
5043
                            &reduced_clock);
5044
        if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5045
            /*
5046
             * If the different P is found, it means that we can't
5047
             * switch the display clock by using the FP0/FP1.
5048
             * In such case we will disable the LVDS downclock
5049
             * feature.
5050
             */
5051
            DRM_DEBUG_KMS("Different P is found for "
5052
                      "LVDS clock/downclock\n");
5053
            has_reduced_clock = 0;
5054
        }
5055
    }
5056
    /* SDVO TV has fixed PLL values depend on its clock range,
5057
       this mirrors vbios setting. */
5058
    if (is_sdvo && is_tv) {
5059
        if (adjusted_mode->clock >= 100000
5060
            && adjusted_mode->clock < 140500) {
5061
            clock.p1 = 2;
5062
            clock.p2 = 10;
5063
            clock.n = 3;
5064
            clock.m1 = 16;
5065
            clock.m2 = 8;
5066
        } else if (adjusted_mode->clock >= 140500
5067
               && adjusted_mode->clock <= 200000) {
5068
            clock.p1 = 1;
5069
            clock.p2 = 10;
5070
            clock.n = 6;
5071
            clock.m1 = 12;
5072
            clock.m2 = 8;
5073
        }
5074
    }
5075
 
5076
    if (IS_PINEVIEW(dev)) {
5077
        fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
5078
        if (has_reduced_clock)
5079
            fp2 = (1 << reduced_clock.n) << 16 |
5080
                reduced_clock.m1 << 8 | reduced_clock.m2;
5081
    } else {
5082
        fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5083
        if (has_reduced_clock)
5084
            fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5085
                reduced_clock.m2;
5086
    }
5087
 
5088
    dpll = DPLL_VGA_MODE_DIS;
5089
 
5090
    if (!IS_GEN2(dev)) {
5091
        if (is_lvds)
5092
            dpll |= DPLLB_MODE_LVDS;
5093
        else
5094
            dpll |= DPLLB_MODE_DAC_SERIAL;
5095
        if (is_sdvo) {
5096
            int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5097
            if (pixel_multiplier > 1) {
5098
                if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5099
                    dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5100
            }
5101
            dpll |= DPLL_DVO_HIGH_SPEED;
5102
        }
5103
        if (is_dp)
5104
            dpll |= DPLL_DVO_HIGH_SPEED;
5105
 
5106
        /* compute bitmask from p1 value */
5107
        if (IS_PINEVIEW(dev))
5108
            dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5109
        else {
5110
            dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5111
            if (IS_G4X(dev) && has_reduced_clock)
5112
                dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5113
        }
5114
        switch (clock.p2) {
5115
        case 5:
5116
            dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5117
            break;
5118
        case 7:
5119
            dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5120
            break;
5121
        case 10:
5122
            dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5123
            break;
5124
        case 14:
5125
            dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5126
            break;
5127
        }
5128
        if (INTEL_INFO(dev)->gen >= 4)
5129
            dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5130
    } else {
5131
        if (is_lvds) {
5132
            dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5133
        } else {
5134
            if (clock.p1 == 2)
5135
                dpll |= PLL_P1_DIVIDE_BY_TWO;
5136
            else
5137
                dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5138
            if (clock.p2 == 4)
5139
                dpll |= PLL_P2_DIVIDE_BY_4;
5140
        }
5141
    }
5142
 
5143
    if (is_sdvo && is_tv)
5144
        dpll |= PLL_REF_INPUT_TVCLKINBC;
5145
    else if (is_tv)
5146
        /* XXX: just matching BIOS for now */
5147
        /*  dpll |= PLL_REF_INPUT_TVCLKINBC; */
5148
        dpll |= 3;
5149
    else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5150
        dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5151
    else
5152
        dpll |= PLL_REF_INPUT_DREFCLK;
5153
 
5154
    /* setup pipeconf */
5155
    pipeconf = I915_READ(PIPECONF(pipe));
5156
 
5157
    /* Set up the display plane register */
5158
    dspcntr = DISPPLANE_GAMMA_ENABLE;
5159
 
5160
    /* Ironlake's plane is forced to pipe, bit 24 is to
5161
       enable color space conversion */
5162
    if (pipe == 0)
5163
        dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5164
    else
5165
        dspcntr |= DISPPLANE_SEL_PIPE_B;
5166
 
5167
    if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5168
        /* Enable pixel doubling when the dot clock is > 90% of the (display)
5169
         * core speed.
5170
         *
5171
         * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5172
         * pipe == 0 check?
5173
         */
5174
        if (mode->clock >
5175
            dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5176
            pipeconf |= PIPECONF_DOUBLE_WIDE;
5177
        else
5178
            pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5179
    }
5180
 
2342 Serge 5181
	/* default to 8bpc */
5182
	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5183
	if (is_dp) {
5184
		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5185
			pipeconf |= PIPECONF_BPP_6 |
5186
				    PIPECONF_DITHER_EN |
5187
				    PIPECONF_DITHER_TYPE_SP;
5188
		}
5189
	}
5190
 
2327 Serge 5191
    dpll |= DPLL_VCO_ENABLE;
5192
 
5193
    DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5194
    drm_mode_debug_printmodeline(mode);
5195
 
5196
    I915_WRITE(FP0(pipe), fp);
5197
    I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5198
 
5199
    POSTING_READ(DPLL(pipe));
5200
    udelay(150);
5201
 
5202
    /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5203
     * This is an exception to the general rule that mode_set doesn't turn
5204
     * things on.
5205
     */
5206
    if (is_lvds) {
5207
        temp = I915_READ(LVDS);
5208
        temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5209
        if (pipe == 1) {
5210
            temp |= LVDS_PIPEB_SELECT;
5211
        } else {
5212
            temp &= ~LVDS_PIPEB_SELECT;
5213
        }
5214
        /* set the corresponsding LVDS_BORDER bit */
5215
        temp |= dev_priv->lvds_border_bits;
5216
        /* Set the B0-B3 data pairs corresponding to whether we're going to
5217
         * set the DPLLs for dual-channel mode or not.
5218
         */
5219
        if (clock.p2 == 7)
5220
            temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5221
        else
5222
            temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5223
 
5224
        /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5225
         * appropriately here, but we need to look more thoroughly into how
5226
         * panels behave in the two modes.
5227
         */
5228
        /* set the dithering flag on LVDS as needed */
5229
        if (INTEL_INFO(dev)->gen >= 4) {
5230
            if (dev_priv->lvds_dither)
5231
                temp |= LVDS_ENABLE_DITHER;
5232
            else
5233
                temp &= ~LVDS_ENABLE_DITHER;
5234
        }
5235
        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5236
            lvds_sync |= LVDS_HSYNC_POLARITY;
5237
        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5238
            lvds_sync |= LVDS_VSYNC_POLARITY;
5239
        if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5240
            != lvds_sync) {
5241
            char flags[2] = "-+";
5242
            DRM_INFO("Changing LVDS panel from "
5243
                 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5244
                 flags[!(temp & LVDS_HSYNC_POLARITY)],
5245
                 flags[!(temp & LVDS_VSYNC_POLARITY)],
5246
                 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5247
                 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5248
            temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5249
            temp |= lvds_sync;
5250
        }
5251
        I915_WRITE(LVDS, temp);
5252
    }
5253
 
5254
    if (is_dp) {
5255
        intel_dp_set_m_n(crtc, mode, adjusted_mode);
5256
    }
5257
 
5258
    I915_WRITE(DPLL(pipe), dpll);
5259
 
5260
    /* Wait for the clocks to stabilize. */
5261
    POSTING_READ(DPLL(pipe));
5262
    udelay(150);
5263
 
5264
    if (INTEL_INFO(dev)->gen >= 4) {
5265
        temp = 0;
5266
        if (is_sdvo) {
5267
            temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5268
            if (temp > 1)
5269
                temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5270
            else
5271
                temp = 0;
5272
        }
5273
        I915_WRITE(DPLL_MD(pipe), temp);
5274
    } else {
5275
        /* The pixel multiplier can only be updated once the
5276
         * DPLL is enabled and the clocks are stable.
5277
         *
5278
         * So write it again.
5279
         */
5280
        I915_WRITE(DPLL(pipe), dpll);
5281
    }
5282
 
5283
    intel_crtc->lowfreq_avail = false;
5284
    if (is_lvds && has_reduced_clock && i915_powersave) {
5285
        I915_WRITE(FP1(pipe), fp2);
5286
        intel_crtc->lowfreq_avail = true;
5287
        if (HAS_PIPE_CXSR(dev)) {
5288
            DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5289
            pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5290
        }
5291
    } else {
5292
        I915_WRITE(FP1(pipe), fp);
5293
        if (HAS_PIPE_CXSR(dev)) {
5294
            DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5295
            pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5296
        }
5297
    }
5298
 
5299
    if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5300
        pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5301
        /* the chip adds 2 halflines automatically */
5302
        adjusted_mode->crtc_vdisplay -= 1;
5303
        adjusted_mode->crtc_vtotal -= 1;
5304
        adjusted_mode->crtc_vblank_start -= 1;
5305
        adjusted_mode->crtc_vblank_end -= 1;
5306
        adjusted_mode->crtc_vsync_end -= 1;
5307
        adjusted_mode->crtc_vsync_start -= 1;
5308
    } else
2342 Serge 5309
		pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
2327 Serge 5310
 
5311
    I915_WRITE(HTOTAL(pipe),
5312
           (adjusted_mode->crtc_hdisplay - 1) |
5313
           ((adjusted_mode->crtc_htotal - 1) << 16));
5314
    I915_WRITE(HBLANK(pipe),
5315
           (adjusted_mode->crtc_hblank_start - 1) |
5316
           ((adjusted_mode->crtc_hblank_end - 1) << 16));
5317
    I915_WRITE(HSYNC(pipe),
5318
           (adjusted_mode->crtc_hsync_start - 1) |
5319
           ((adjusted_mode->crtc_hsync_end - 1) << 16));
5320
 
5321
    I915_WRITE(VTOTAL(pipe),
5322
           (adjusted_mode->crtc_vdisplay - 1) |
5323
           ((adjusted_mode->crtc_vtotal - 1) << 16));
5324
    I915_WRITE(VBLANK(pipe),
5325
           (adjusted_mode->crtc_vblank_start - 1) |
5326
           ((adjusted_mode->crtc_vblank_end - 1) << 16));
5327
    I915_WRITE(VSYNC(pipe),
5328
           (adjusted_mode->crtc_vsync_start - 1) |
5329
           ((adjusted_mode->crtc_vsync_end - 1) << 16));
5330
 
5331
    /* pipesrc and dspsize control the size that is scaled from,
5332
     * which should always be the user's requested size.
5333
     */
5334
    I915_WRITE(DSPSIZE(plane),
5335
           ((mode->vdisplay - 1) << 16) |
5336
           (mode->hdisplay - 1));
5337
    I915_WRITE(DSPPOS(plane), 0);
5338
    I915_WRITE(PIPESRC(pipe),
5339
           ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5340
 
5341
    I915_WRITE(PIPECONF(pipe), pipeconf);
5342
    POSTING_READ(PIPECONF(pipe));
5343
    intel_enable_pipe(dev_priv, pipe, false);
5344
 
5345
    intel_wait_for_vblank(dev, pipe);
5346
 
5347
    I915_WRITE(DSPCNTR(plane), dspcntr);
5348
    POSTING_READ(DSPCNTR(plane));
5349
    intel_enable_plane(dev_priv, plane, pipe);
5350
 
5351
    ret = intel_pipe_set_base(crtc, x, y, old_fb);
5352
 
5353
    intel_update_watermarks(dev);
5354
 
5355
    return ret;
5356
}
5357
 
2342 Serge 5358
/*
5359
 * Initialize reference clocks when the driver loads
5360
 */
5361
void ironlake_init_pch_refclk(struct drm_device *dev)
2327 Serge 5362
{
5363
	struct drm_i915_private *dev_priv = dev->dev_private;
5364
	struct drm_mode_config *mode_config = &dev->mode_config;
5365
	struct intel_encoder *encoder;
5366
	u32 temp;
5367
	bool has_lvds = false;
2342 Serge 5368
	bool has_cpu_edp = false;
5369
	bool has_pch_edp = false;
5370
	bool has_panel = false;
5371
	bool has_ck505 = false;
5372
	bool can_ssc = false;
2327 Serge 5373
 
5374
	/* We need to take the global config into account */
5375
		list_for_each_entry(encoder, &mode_config->encoder_list,
5376
				    base.head) {
5377
			switch (encoder->type) {
5378
			case INTEL_OUTPUT_LVDS:
2342 Serge 5379
			has_panel = true;
2327 Serge 5380
				has_lvds = true;
2342 Serge 5381
			break;
2327 Serge 5382
			case INTEL_OUTPUT_EDP:
2342 Serge 5383
			has_panel = true;
5384
			if (intel_encoder_is_pch_edp(&encoder->base))
5385
				has_pch_edp = true;
5386
			else
5387
				has_cpu_edp = true;
2327 Serge 5388
				break;
5389
			}
5390
		}
2342 Serge 5391
 
5392
	if (HAS_PCH_IBX(dev)) {
5393
		has_ck505 = dev_priv->display_clock_mode;
5394
		can_ssc = has_ck505;
5395
	} else {
5396
		has_ck505 = false;
5397
		can_ssc = true;
2327 Serge 5398
	}
5399
 
2342 Serge 5400
	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5401
		      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5402
		      has_ck505);
5403
 
2327 Serge 5404
	/* Ironlake: try to setup display ref clock before DPLL
5405
	 * enabling. This is only under driver's control after
5406
	 * PCH B stepping, previous chipset stepping should be
5407
	 * ignoring this setting.
5408
	 */
5409
	temp = I915_READ(PCH_DREF_CONTROL);
5410
	/* Always enable nonspread source */
5411
	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2342 Serge 5412
 
5413
	if (has_ck505)
5414
		temp |= DREF_NONSPREAD_CK505_ENABLE;
5415
	else
2327 Serge 5416
	temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2342 Serge 5417
 
5418
	if (has_panel) {
2327 Serge 5419
	temp &= ~DREF_SSC_SOURCE_MASK;
5420
	temp |= DREF_SSC_SOURCE_ENABLE;
5421
 
2342 Serge 5422
		/* SSC must be turned on before enabling the CPU output  */
5423
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5424
			DRM_DEBUG_KMS("Using SSC on panel\n");
5425
			temp |= DREF_SSC1_ENABLE;
5426
		}
2327 Serge 5427
 
2342 Serge 5428
		/* Get SSC going before enabling the outputs */
2327 Serge 5429
			I915_WRITE(PCH_DREF_CONTROL, temp);
5430
			POSTING_READ(PCH_DREF_CONTROL);
5431
			udelay(200);
2342 Serge 5432
 
2327 Serge 5433
		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5434
 
5435
		/* Enable CPU source on CPU attached eDP */
2342 Serge 5436
		if (has_cpu_edp) {
5437
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5438
				DRM_DEBUG_KMS("Using SSC on eDP\n");
2327 Serge 5439
				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2342 Serge 5440
			}
2327 Serge 5441
			else
5442
				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2342 Serge 5443
		} else
5444
			temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5445
 
5446
		I915_WRITE(PCH_DREF_CONTROL, temp);
5447
		POSTING_READ(PCH_DREF_CONTROL);
5448
		udelay(200);
2327 Serge 5449
		} else {
2342 Serge 5450
		DRM_DEBUG_KMS("Disabling SSC entirely\n");
5451
 
5452
		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5453
 
5454
		/* Turn off CPU output */
5455
		temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5456
 
2327 Serge 5457
		I915_WRITE(PCH_DREF_CONTROL, temp);
5458
		POSTING_READ(PCH_DREF_CONTROL);
5459
		udelay(200);
2342 Serge 5460
 
5461
		/* Turn off the SSC source */
5462
		temp &= ~DREF_SSC_SOURCE_MASK;
5463
		temp |= DREF_SSC_SOURCE_DISABLE;
5464
 
5465
		/* Turn off SSC1 */
5466
		temp &= ~ DREF_SSC1_ENABLE;
5467
 
5468
		I915_WRITE(PCH_DREF_CONTROL, temp);
5469
		POSTING_READ(PCH_DREF_CONTROL);
5470
		udelay(200);
2327 Serge 5471
	}
5472
}
5473
 
2342 Serge 5474
static int ironlake_get_refclk(struct drm_crtc *crtc)
5475
{
5476
	struct drm_device *dev = crtc->dev;
5477
	struct drm_i915_private *dev_priv = dev->dev_private;
5478
	struct intel_encoder *encoder;
5479
	struct drm_mode_config *mode_config = &dev->mode_config;
5480
	struct intel_encoder *edp_encoder = NULL;
5481
	int num_connectors = 0;
5482
	bool is_lvds = false;
5483
 
5484
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5485
		if (encoder->base.crtc != crtc)
5486
			continue;
5487
 
5488
		switch (encoder->type) {
5489
		case INTEL_OUTPUT_LVDS:
5490
			is_lvds = true;
5491
			break;
5492
		case INTEL_OUTPUT_EDP:
5493
			edp_encoder = encoder;
5494
			break;
5495
		}
5496
		num_connectors++;
5497
	}
5498
 
5499
	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5500
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5501
			      dev_priv->lvds_ssc_freq);
5502
		return dev_priv->lvds_ssc_freq * 1000;
5503
	}
5504
 
5505
	return 120000;
5506
}
5507
 
2327 Serge 5508
static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5509
                  struct drm_display_mode *mode,
5510
                  struct drm_display_mode *adjusted_mode,
5511
                  int x, int y,
5512
                  struct drm_framebuffer *old_fb)
5513
{
5514
    struct drm_device *dev = crtc->dev;
5515
    struct drm_i915_private *dev_priv = dev->dev_private;
5516
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5517
    int pipe = intel_crtc->pipe;
5518
    int plane = intel_crtc->plane;
5519
    int refclk, num_connectors = 0;
5520
    intel_clock_t clock, reduced_clock;
5521
    u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5522
    bool ok, has_reduced_clock = false, is_sdvo = false;
5523
    bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5524
    struct intel_encoder *has_edp_encoder = NULL;
5525
    struct drm_mode_config *mode_config = &dev->mode_config;
5526
    struct intel_encoder *encoder;
5527
    const intel_limit_t *limit;
5528
    int ret;
5529
    struct fdi_m_n m_n = {0};
5530
    u32 temp;
5531
    u32 lvds_sync = 0;
5532
    int target_clock, pixel_multiplier, lane, link_bw, factor;
5533
    unsigned int pipe_bpp;
5534
    bool dither;
5535
 
2336 Serge 5536
    ENTER();
5537
 
2327 Serge 5538
    list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5539
        if (encoder->base.crtc != crtc)
5540
            continue;
5541
 
5542
        switch (encoder->type) {
5543
        case INTEL_OUTPUT_LVDS:
5544
            is_lvds = true;
5545
            break;
5546
        case INTEL_OUTPUT_SDVO:
5547
        case INTEL_OUTPUT_HDMI:
5548
            is_sdvo = true;
5549
            if (encoder->needs_tv_clock)
5550
                is_tv = true;
5551
            break;
5552
        case INTEL_OUTPUT_TVOUT:
5553
            is_tv = true;
5554
            break;
5555
        case INTEL_OUTPUT_ANALOG:
5556
            is_crt = true;
5557
            break;
5558
        case INTEL_OUTPUT_DISPLAYPORT:
5559
            is_dp = true;
5560
            break;
5561
        case INTEL_OUTPUT_EDP:
5562
            has_edp_encoder = encoder;
5563
            break;
5564
        }
5565
 
5566
        num_connectors++;
5567
    }
5568
 
2342 Serge 5569
	refclk = ironlake_get_refclk(crtc);
2327 Serge 5570
 
5571
    /*
5572
     * Returns a set of divisors for the desired target clock with the given
5573
     * refclk, or FALSE.  The returned values represent the clock equation:
5574
     * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5575
     */
5576
    limit = intel_limit(crtc, refclk);
5577
    ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5578
    if (!ok) {
5579
        DRM_ERROR("Couldn't find PLL settings for mode!\n");
5580
        return -EINVAL;
5581
    }
5582
 
5583
    /* Ensure that the cursor is valid for the new mode before changing... */
5584
//    intel_crtc_update_cursor(crtc, true);
5585
 
5586
    if (is_lvds && dev_priv->lvds_downclock_avail) {
5587
        has_reduced_clock = limit->find_pll(limit, crtc,
5588
                            dev_priv->lvds_downclock,
5589
                            refclk,
5590
                            &reduced_clock);
5591
        if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5592
            /*
5593
             * If the different P is found, it means that we can't
5594
             * switch the display clock by using the FP0/FP1.
5595
             * In such case we will disable the LVDS downclock
5596
             * feature.
5597
             */
5598
            DRM_DEBUG_KMS("Different P is found for "
5599
                      "LVDS clock/downclock\n");
5600
            has_reduced_clock = 0;
5601
        }
5602
    }
5603
    /* SDVO TV has fixed PLL values depend on its clock range,
5604
       this mirrors vbios setting. */
5605
    if (is_sdvo && is_tv) {
5606
        if (adjusted_mode->clock >= 100000
5607
            && adjusted_mode->clock < 140500) {
5608
            clock.p1 = 2;
5609
            clock.p2 = 10;
5610
            clock.n = 3;
5611
            clock.m1 = 16;
5612
            clock.m2 = 8;
5613
        } else if (adjusted_mode->clock >= 140500
5614
               && adjusted_mode->clock <= 200000) {
5615
            clock.p1 = 1;
5616
            clock.p2 = 10;
5617
            clock.n = 6;
5618
            clock.m1 = 12;
5619
            clock.m2 = 8;
5620
        }
5621
    }
5622
 
5623
    /* FDI link */
5624
    pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5625
    lane = 0;
5626
    /* CPU eDP doesn't require FDI link, so just set DP M/N
5627
       according to current link config */
5628
    if (has_edp_encoder &&
5629
        !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5630
        target_clock = mode->clock;
5631
        intel_edp_link_config(has_edp_encoder,
5632
                      &lane, &link_bw);
5633
    } else {
5634
        /* [e]DP over FDI requires target mode clock
5635
           instead of link clock */
5636
        if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5637
            target_clock = mode->clock;
5638
        else
5639
            target_clock = adjusted_mode->clock;
5640
 
5641
        /* FDI is a binary signal running at ~2.7GHz, encoding
5642
         * each output octet as 10 bits. The actual frequency
5643
         * is stored as a divider into a 100MHz clock, and the
5644
         * mode pixel clock is stored in units of 1KHz.
5645
         * Hence the bw of each lane in terms of the mode signal
5646
         * is:
5647
         */
5648
        link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5649
    }
5650
 
5651
    /* determine panel color depth */
5652
    temp = I915_READ(PIPECONF(pipe));
5653
    temp &= ~PIPE_BPC_MASK;
2342 Serge 5654
	dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
2327 Serge 5655
    switch (pipe_bpp) {
5656
    case 18:
5657
        temp |= PIPE_6BPC;
5658
        break;
5659
    case 24:
5660
        temp |= PIPE_8BPC;
5661
        break;
5662
    case 30:
5663
        temp |= PIPE_10BPC;
5664
        break;
5665
    case 36:
5666
        temp |= PIPE_12BPC;
5667
        break;
5668
    default:
5669
        WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5670
            pipe_bpp);
5671
        temp |= PIPE_8BPC;
5672
        pipe_bpp = 24;
5673
        break;
5674
    }
5675
 
5676
    intel_crtc->bpp = pipe_bpp;
5677
    I915_WRITE(PIPECONF(pipe), temp);
5678
 
5679
    if (!lane) {
5680
        /*
5681
         * Account for spread spectrum to avoid
5682
         * oversubscribing the link. Max center spread
5683
         * is 2.5%; use 5% for safety's sake.
5684
         */
5685
        u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5686
        lane = bps / (link_bw * 8) + 1;
5687
    }
5688
 
5689
    intel_crtc->fdi_lanes = lane;
5690
 
5691
    if (pixel_multiplier > 1)
5692
        link_bw *= pixel_multiplier;
5693
    ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5694
                 &m_n);
5695
 
5696
    fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5697
    if (has_reduced_clock)
5698
        fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5699
            reduced_clock.m2;
5700
 
5701
    /* Enable autotuning of the PLL clock (if permissible) */
5702
    factor = 21;
5703
    if (is_lvds) {
5704
        if ((intel_panel_use_ssc(dev_priv) &&
5705
             dev_priv->lvds_ssc_freq == 100) ||
5706
            (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5707
            factor = 25;
5708
    } else if (is_sdvo && is_tv)
5709
        factor = 20;
5710
 
5711
    if (clock.m < factor * clock.n)
5712
        fp |= FP_CB_TUNE;
5713
 
5714
    dpll = 0;
5715
 
5716
    if (is_lvds)
5717
        dpll |= DPLLB_MODE_LVDS;
5718
    else
5719
        dpll |= DPLLB_MODE_DAC_SERIAL;
5720
    if (is_sdvo) {
5721
        int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5722
        if (pixel_multiplier > 1) {
5723
            dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5724
        }
5725
        dpll |= DPLL_DVO_HIGH_SPEED;
5726
    }
5727
    if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5728
        dpll |= DPLL_DVO_HIGH_SPEED;
5729
 
5730
    /* compute bitmask from p1 value */
5731
    dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5732
    /* also FPA1 */
5733
    dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5734
 
5735
    switch (clock.p2) {
5736
    case 5:
5737
        dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5738
        break;
5739
    case 7:
5740
        dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5741
        break;
5742
    case 10:
5743
        dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5744
        break;
5745
    case 14:
5746
        dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5747
        break;
5748
    }
5749
 
5750
    if (is_sdvo && is_tv)
5751
        dpll |= PLL_REF_INPUT_TVCLKINBC;
5752
    else if (is_tv)
5753
        /* XXX: just matching BIOS for now */
5754
        /*  dpll |= PLL_REF_INPUT_TVCLKINBC; */
5755
        dpll |= 3;
5756
    else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5757
        dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5758
    else
5759
        dpll |= PLL_REF_INPUT_DREFCLK;
5760
 
5761
    /* setup pipeconf */
5762
    pipeconf = I915_READ(PIPECONF(pipe));
5763
 
5764
    /* Set up the display plane register */
5765
    dspcntr = DISPPLANE_GAMMA_ENABLE;
5766
 
2342 Serge 5767
	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
2327 Serge 5768
    drm_mode_debug_printmodeline(mode);
5769
 
5770
    /* PCH eDP needs FDI, but CPU eDP does not */
2342 Serge 5771
	if (!intel_crtc->no_pll) {
5772
		if (!has_edp_encoder ||
5773
		    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
2327 Serge 5774
        I915_WRITE(PCH_FP0(pipe), fp);
5775
        I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5776
 
5777
        POSTING_READ(PCH_DPLL(pipe));
5778
        udelay(150);
5779
    }
2342 Serge 5780
	} else {
5781
		if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5782
		    fp == I915_READ(PCH_FP0(0))) {
5783
			intel_crtc->use_pll_a = true;
5784
			DRM_DEBUG_KMS("using pipe a dpll\n");
5785
		} else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5786
			   fp == I915_READ(PCH_FP0(1))) {
5787
			intel_crtc->use_pll_a = false;
5788
			DRM_DEBUG_KMS("using pipe b dpll\n");
5789
		} else {
5790
			DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5791
			return -EINVAL;
2327 Serge 5792
        }
5793
    }
5794
 
5795
    /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5796
     * This is an exception to the general rule that mode_set doesn't turn
5797
     * things on.
5798
     */
5799
    if (is_lvds) {
5800
        temp = I915_READ(PCH_LVDS);
5801
        temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
2342 Serge 5802
		if (HAS_PCH_CPT(dev)) {
5803
			temp &= ~PORT_TRANS_SEL_MASK;
5804
			temp |= PORT_TRANS_SEL_CPT(pipe);
5805
		} else {
5806
			if (pipe == 1)
2327 Serge 5807
                temp |= LVDS_PIPEB_SELECT;
5808
            else
5809
                temp &= ~LVDS_PIPEB_SELECT;
5810
        }
2342 Serge 5811
 
2327 Serge 5812
        /* set the corresponsding LVDS_BORDER bit */
5813
        temp |= dev_priv->lvds_border_bits;
5814
        /* Set the B0-B3 data pairs corresponding to whether we're going to
5815
         * set the DPLLs for dual-channel mode or not.
5816
         */
5817
        if (clock.p2 == 7)
5818
            temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5819
        else
5820
            temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5821
 
5822
        /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5823
         * appropriately here, but we need to look more thoroughly into how
5824
         * panels behave in the two modes.
5825
         */
5826
        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5827
            lvds_sync |= LVDS_HSYNC_POLARITY;
5828
        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5829
            lvds_sync |= LVDS_VSYNC_POLARITY;
5830
        if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5831
            != lvds_sync) {
5832
            char flags[2] = "-+";
5833
            DRM_INFO("Changing LVDS panel from "
5834
                 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5835
                 flags[!(temp & LVDS_HSYNC_POLARITY)],
5836
                 flags[!(temp & LVDS_VSYNC_POLARITY)],
5837
                 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5838
                 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5839
            temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5840
            temp |= lvds_sync;
5841
        }
5842
        I915_WRITE(PCH_LVDS, temp);
5843
    }
5844
 
5845
    pipeconf &= ~PIPECONF_DITHER_EN;
5846
    pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5847
    if ((is_lvds && dev_priv->lvds_dither) || dither) {
5848
        pipeconf |= PIPECONF_DITHER_EN;
2342 Serge 5849
		pipeconf |= PIPECONF_DITHER_TYPE_SP;
2327 Serge 5850
    }
5851
    if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5852
        intel_dp_set_m_n(crtc, mode, adjusted_mode);
5853
    } else {
5854
        /* For non-DP output, clear any trans DP clock recovery setting.*/
5855
        I915_WRITE(TRANSDATA_M1(pipe), 0);
5856
        I915_WRITE(TRANSDATA_N1(pipe), 0);
5857
        I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5858
        I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5859
    }
5860
 
2342 Serge 5861
	if (!intel_crtc->no_pll &&
5862
	    (!has_edp_encoder ||
5863
	     intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
2327 Serge 5864
        I915_WRITE(PCH_DPLL(pipe), dpll);
5865
 
5866
        /* Wait for the clocks to stabilize. */
5867
        POSTING_READ(PCH_DPLL(pipe));
5868
        udelay(150);
5869
 
5870
        /* The pixel multiplier can only be updated once the
5871
         * DPLL is enabled and the clocks are stable.
5872
         *
5873
         * So write it again.
5874
         */
5875
        I915_WRITE(PCH_DPLL(pipe), dpll);
5876
    }
5877
 
5878
    intel_crtc->lowfreq_avail = false;
2342 Serge 5879
	if (!intel_crtc->no_pll) {
2327 Serge 5880
    if (is_lvds && has_reduced_clock && i915_powersave) {
5881
        I915_WRITE(PCH_FP1(pipe), fp2);
5882
        intel_crtc->lowfreq_avail = true;
5883
        if (HAS_PIPE_CXSR(dev)) {
5884
            DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5885
            pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5886
        }
5887
    } else {
5888
        I915_WRITE(PCH_FP1(pipe), fp);
5889
        if (HAS_PIPE_CXSR(dev)) {
5890
            DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5891
            pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5892
        }
5893
    }
2342 Serge 5894
	}
2327 Serge 5895
 
5896
    if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5897
        pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5898
        /* the chip adds 2 halflines automatically */
5899
        adjusted_mode->crtc_vdisplay -= 1;
5900
        adjusted_mode->crtc_vtotal -= 1;
5901
        adjusted_mode->crtc_vblank_start -= 1;
5902
        adjusted_mode->crtc_vblank_end -= 1;
5903
        adjusted_mode->crtc_vsync_end -= 1;
5904
        adjusted_mode->crtc_vsync_start -= 1;
5905
    } else
5906
        pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5907
 
5908
    I915_WRITE(HTOTAL(pipe),
5909
           (adjusted_mode->crtc_hdisplay - 1) |
5910
           ((adjusted_mode->crtc_htotal - 1) << 16));
5911
    I915_WRITE(HBLANK(pipe),
5912
           (adjusted_mode->crtc_hblank_start - 1) |
5913
           ((adjusted_mode->crtc_hblank_end - 1) << 16));
5914
    I915_WRITE(HSYNC(pipe),
5915
           (adjusted_mode->crtc_hsync_start - 1) |
5916
           ((adjusted_mode->crtc_hsync_end - 1) << 16));
5917
 
5918
    I915_WRITE(VTOTAL(pipe),
5919
           (adjusted_mode->crtc_vdisplay - 1) |
5920
           ((adjusted_mode->crtc_vtotal - 1) << 16));
5921
    I915_WRITE(VBLANK(pipe),
5922
           (adjusted_mode->crtc_vblank_start - 1) |
5923
           ((adjusted_mode->crtc_vblank_end - 1) << 16));
5924
    I915_WRITE(VSYNC(pipe),
5925
           (adjusted_mode->crtc_vsync_start - 1) |
5926
           ((adjusted_mode->crtc_vsync_end - 1) << 16));
5927
 
5928
    /* pipesrc controls the size that is scaled from, which should
5929
     * always be the user's requested size.
5930
     */
5931
    I915_WRITE(PIPESRC(pipe),
5932
           ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5933
 
5934
    I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5935
    I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5936
    I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5937
    I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5938
 
5939
    if (has_edp_encoder &&
5940
        !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5941
        ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5942
    }
5943
 
5944
    I915_WRITE(PIPECONF(pipe), pipeconf);
5945
    POSTING_READ(PIPECONF(pipe));
5946
 
5947
    intel_wait_for_vblank(dev, pipe);
5948
 
5949
    if (IS_GEN5(dev)) {
5950
        /* enable address swizzle for tiling buffer */
5951
        temp = I915_READ(DISP_ARB_CTL);
5952
        I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5953
    }
5954
 
5955
    I915_WRITE(DSPCNTR(plane), dspcntr);
5956
    POSTING_READ(DSPCNTR(plane));
5957
 
5958
    ret = intel_pipe_set_base(crtc, x, y, old_fb);
5959
 
2336 Serge 5960
    dbgprintf("Set base\n");
5961
 
2327 Serge 5962
    intel_update_watermarks(dev);
5963
 
2336 Serge 5964
    LEAVE();
5965
 
2327 Serge 5966
    return ret;
5967
}
5968
 
2330 Serge 5969
static int intel_crtc_mode_set(struct drm_crtc *crtc,
5970
			       struct drm_display_mode *mode,
5971
			       struct drm_display_mode *adjusted_mode,
5972
			       int x, int y,
5973
			       struct drm_framebuffer *old_fb)
5974
{
5975
	struct drm_device *dev = crtc->dev;
5976
	struct drm_i915_private *dev_priv = dev->dev_private;
5977
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5978
	int pipe = intel_crtc->pipe;
5979
	int ret;
2327 Serge 5980
 
2330 Serge 5981
//	drm_vblank_pre_modeset(dev, pipe);
2336 Serge 5982
    ENTER();
2327 Serge 5983
 
2330 Serge 5984
	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5985
					      x, y, old_fb);
2327 Serge 5986
 
2330 Serge 5987
//	drm_vblank_post_modeset(dev, pipe);
2327 Serge 5988
 
2330 Serge 5989
	intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
2336 Serge 5990
    LEAVE();
2327 Serge 5991
 
2330 Serge 5992
	return ret;
5993
}
2327 Serge 5994
 
2342 Serge 5995
static bool intel_eld_uptodate(struct drm_connector *connector,
5996
			       int reg_eldv, uint32_t bits_eldv,
5997
			       int reg_elda, uint32_t bits_elda,
5998
			       int reg_edid)
5999
{
6000
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
6001
	uint8_t *eld = connector->eld;
6002
	uint32_t i;
6003
 
6004
	i = I915_READ(reg_eldv);
6005
	i &= bits_eldv;
6006
 
6007
	if (!eld[0])
6008
		return !i;
6009
 
6010
	if (!i)
6011
		return false;
6012
 
6013
	i = I915_READ(reg_elda);
6014
	i &= ~bits_elda;
6015
	I915_WRITE(reg_elda, i);
6016
 
6017
	for (i = 0; i < eld[2]; i++)
6018
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6019
			return false;
6020
 
6021
	return true;
6022
}
6023
 
6024
static void g4x_write_eld(struct drm_connector *connector,
6025
			  struct drm_crtc *crtc)
6026
{
6027
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
6028
	uint8_t *eld = connector->eld;
6029
	uint32_t eldv;
6030
	uint32_t len;
6031
	uint32_t i;
6032
 
6033
	i = I915_READ(G4X_AUD_VID_DID);
6034
 
6035
	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6036
		eldv = G4X_ELDV_DEVCL_DEVBLC;
6037
	else
6038
		eldv = G4X_ELDV_DEVCTG;
6039
 
6040
	if (intel_eld_uptodate(connector,
6041
			       G4X_AUD_CNTL_ST, eldv,
6042
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6043
			       G4X_HDMIW_HDMIEDID))
6044
		return;
6045
 
6046
	i = I915_READ(G4X_AUD_CNTL_ST);
6047
	i &= ~(eldv | G4X_ELD_ADDR);
6048
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
6049
	I915_WRITE(G4X_AUD_CNTL_ST, i);
6050
 
6051
	if (!eld[0])
6052
		return;
6053
 
6054
	len = min_t(uint8_t, eld[2], len);
6055
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
6056
	for (i = 0; i < len; i++)
6057
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6058
 
6059
	i = I915_READ(G4X_AUD_CNTL_ST);
6060
	i |= eldv;
6061
	I915_WRITE(G4X_AUD_CNTL_ST, i);
6062
}
6063
 
6064
static void ironlake_write_eld(struct drm_connector *connector,
6065
				     struct drm_crtc *crtc)
6066
{
6067
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
6068
	uint8_t *eld = connector->eld;
6069
	uint32_t eldv;
6070
	uint32_t i;
6071
	int len;
6072
	int hdmiw_hdmiedid;
6073
	int aud_cntl_st;
6074
	int aud_cntrl_st2;
6075
 
6076
	if (HAS_PCH_IBX(connector->dev)) {
6077
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6078
		aud_cntl_st = IBX_AUD_CNTL_ST_A;
6079
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6080
	} else {
6081
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6082
		aud_cntl_st = CPT_AUD_CNTL_ST_A;
6083
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6084
	}
6085
 
6086
	i = to_intel_crtc(crtc)->pipe;
6087
	hdmiw_hdmiedid += i * 0x100;
6088
	aud_cntl_st += i * 0x100;
6089
 
6090
	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6091
 
6092
	i = I915_READ(aud_cntl_st);
6093
	i = (i >> 29) & 0x3;		/* DIP_Port_Select, 0x1 = PortB */
6094
	if (!i) {
6095
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6096
		/* operate blindly on all ports */
6097
		eldv = IBX_ELD_VALIDB;
6098
		eldv |= IBX_ELD_VALIDB << 4;
6099
		eldv |= IBX_ELD_VALIDB << 8;
6100
	} else {
6101
		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6102
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6103
	}
6104
 
6105
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6106
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6107
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
6108
	}
6109
 
6110
	if (intel_eld_uptodate(connector,
6111
			       aud_cntrl_st2, eldv,
6112
			       aud_cntl_st, IBX_ELD_ADDRESS,
6113
			       hdmiw_hdmiedid))
6114
		return;
6115
 
6116
	i = I915_READ(aud_cntrl_st2);
6117
	i &= ~eldv;
6118
	I915_WRITE(aud_cntrl_st2, i);
6119
 
6120
	if (!eld[0])
6121
		return;
6122
 
6123
	i = I915_READ(aud_cntl_st);
6124
	i &= ~IBX_ELD_ADDRESS;
6125
	I915_WRITE(aud_cntl_st, i);
6126
 
6127
	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
6128
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
6129
	for (i = 0; i < len; i++)
6130
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6131
 
6132
	i = I915_READ(aud_cntrl_st2);
6133
	i |= eldv;
6134
	I915_WRITE(aud_cntrl_st2, i);
6135
}
6136
 
6137
void intel_write_eld(struct drm_encoder *encoder,
6138
		     struct drm_display_mode *mode)
6139
{
6140
	struct drm_crtc *crtc = encoder->crtc;
6141
	struct drm_connector *connector;
6142
	struct drm_device *dev = encoder->dev;
6143
	struct drm_i915_private *dev_priv = dev->dev_private;
6144
 
6145
	connector = drm_select_eld(encoder, mode);
6146
	if (!connector)
6147
		return;
6148
 
6149
	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6150
			 connector->base.id,
6151
			 drm_get_connector_name(connector),
6152
			 connector->encoder->base.id,
6153
			 drm_get_encoder_name(connector->encoder));
6154
 
6155
	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6156
 
6157
	if (dev_priv->display.write_eld)
6158
		dev_priv->display.write_eld(connector, crtc);
6159
}
6160
 
2327 Serge 6161
/** Loads the palette/gamma unit for the CRTC with the prepared values */
6162
void intel_crtc_load_lut(struct drm_crtc *crtc)
6163
{
6164
	struct drm_device *dev = crtc->dev;
6165
	struct drm_i915_private *dev_priv = dev->dev_private;
6166
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167
	int palreg = PALETTE(intel_crtc->pipe);
6168
	int i;
6169
 
6170
	/* The clocks have to be on to load the palette. */
6171
	if (!crtc->enabled)
6172
		return;
6173
 
6174
	/* use legacy palette for Ironlake */
6175
	if (HAS_PCH_SPLIT(dev))
6176
		palreg = LGC_PALETTE(intel_crtc->pipe);
6177
 
6178
	for (i = 0; i < 256; i++) {
6179
		I915_WRITE(palreg + 4 * i,
6180
			   (intel_crtc->lut_r[i] << 16) |
6181
			   (intel_crtc->lut_g[i] << 8) |
6182
			   intel_crtc->lut_b[i]);
6183
	}
6184
}
6185
 
6186
 
6187
 
6188
 
6189
 
6190
 
6191
 
6192
 
6193
 
6194
 
6195
 
6196
 
6197
 
6198
 
6199
 
6200
 
6201
 
6202
 
6203
 
6204
 
6205
 
6206
 
6207
 
6208
 
6209
 
6210
 
6211
 
6212
 
6213
 
6214
 
6215
 
6216
 
6217
 
6218
 
6219
 
6220
 
6221
 
2332 Serge 6222
/** Sets the color ramps on behalf of RandR */
6223
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6224
				 u16 blue, int regno)
6225
{
6226
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 Serge 6227
 
2332 Serge 6228
	intel_crtc->lut_r[regno] = red >> 8;
6229
	intel_crtc->lut_g[regno] = green >> 8;
6230
	intel_crtc->lut_b[regno] = blue >> 8;
6231
}
2327 Serge 6232
 
2332 Serge 6233
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6234
			     u16 *blue, int regno)
6235
{
6236
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 Serge 6237
 
2332 Serge 6238
	*red = intel_crtc->lut_r[regno] << 8;
6239
	*green = intel_crtc->lut_g[regno] << 8;
6240
	*blue = intel_crtc->lut_b[regno] << 8;
6241
}
2327 Serge 6242
 
2330 Serge 6243
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6244
				 u16 *blue, uint32_t start, uint32_t size)
6245
{
6246
	int end = (start + size > 256) ? 256 : start + size, i;
6247
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 Serge 6248
 
2330 Serge 6249
	for (i = start; i < end; i++) {
6250
		intel_crtc->lut_r[i] = red[i] >> 8;
6251
		intel_crtc->lut_g[i] = green[i] >> 8;
6252
		intel_crtc->lut_b[i] = blue[i] >> 8;
6253
	}
2327 Serge 6254
 
2330 Serge 6255
	intel_crtc_load_lut(crtc);
6256
}
2327 Serge 6257
 
2330 Serge 6258
/**
6259
 * Get a pipe with a simple mode set on it for doing load-based monitor
6260
 * detection.
6261
 *
6262
 * It will be up to the load-detect code to adjust the pipe as appropriate for
6263
 * its requirements.  The pipe will be connected to no other encoders.
6264
 *
6265
 * Currently this code will only succeed if there is a pipe with no encoders
6266
 * configured for it.  In the future, it could choose to temporarily disable
6267
 * some outputs to free up a pipe for its use.
6268
 *
6269
 * \return crtc, or NULL if no pipes are available.
6270
 */
2327 Serge 6271
 
2330 Serge 6272
/* VESA 640x480x72Hz mode to set on the pipe */
6273
static struct drm_display_mode load_detect_mode = {
6274
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6275
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6276
};
2327 Serge 6277
 
6278
 
6279
 
6280
 
6281
 
2330 Serge 6282
static u32
6283
intel_framebuffer_pitch_for_width(int width, int bpp)
6284
{
6285
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6286
	return ALIGN(pitch, 64);
6287
}
2327 Serge 6288
 
2330 Serge 6289
static u32
6290
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6291
{
6292
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6293
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6294
}
2327 Serge 6295
 
2330 Serge 6296
static struct drm_framebuffer *
6297
intel_framebuffer_create_for_mode(struct drm_device *dev,
6298
				  struct drm_display_mode *mode,
6299
				  int depth, int bpp)
6300
{
6301
	struct drm_i915_gem_object *obj;
2344 Serge 6302
	struct drm_mode_fb_cmd2 mode_cmd;
2327 Serge 6303
 
2330 Serge 6304
//	obj = i915_gem_alloc_object(dev,
6305
//				    intel_framebuffer_size_for_mode(mode, bpp));
6306
//	if (obj == NULL)
6307
		return ERR_PTR(-ENOMEM);
2327 Serge 6308
 
2330 Serge 6309
//	mode_cmd.width = mode->hdisplay;
6310
//	mode_cmd.height = mode->vdisplay;
6311
//	mode_cmd.depth = depth;
6312
//	mode_cmd.bpp = bpp;
6313
//	mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327 Serge 6314
 
2330 Serge 6315
//	return intel_framebuffer_create(dev, &mode_cmd, obj);
6316
}
2327 Serge 6317
 
2330 Serge 6318
static struct drm_framebuffer *
6319
mode_fits_in_fbdev(struct drm_device *dev,
6320
		   struct drm_display_mode *mode)
6321
{
6322
	struct drm_i915_private *dev_priv = dev->dev_private;
6323
	struct drm_i915_gem_object *obj;
6324
	struct drm_framebuffer *fb;
2327 Serge 6325
 
2330 Serge 6326
//	if (dev_priv->fbdev == NULL)
6327
//		return NULL;
2327 Serge 6328
 
2330 Serge 6329
//	obj = dev_priv->fbdev->ifb.obj;
6330
//	if (obj == NULL)
6331
//		return NULL;
2327 Serge 6332
 
2330 Serge 6333
//	fb = &dev_priv->fbdev->ifb.base;
6334
//	if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6335
//							  fb->bits_per_pixel))
6336
		return NULL;
2327 Serge 6337
 
2330 Serge 6338
//	if (obj->base.size < mode->vdisplay * fb->pitch)
6339
//		return NULL;
2327 Serge 6340
 
2330 Serge 6341
//	return fb;
6342
}
2327 Serge 6343
 
2330 Serge 6344
bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6345
				struct drm_connector *connector,
6346
				struct drm_display_mode *mode,
6347
				struct intel_load_detect_pipe *old)
6348
{
6349
	struct intel_crtc *intel_crtc;
6350
	struct drm_crtc *possible_crtc;
6351
	struct drm_encoder *encoder = &intel_encoder->base;
6352
	struct drm_crtc *crtc = NULL;
6353
	struct drm_device *dev = encoder->dev;
6354
	struct drm_framebuffer *old_fb;
6355
	int i = -1;
2327 Serge 6356
 
2330 Serge 6357
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6358
		      connector->base.id, drm_get_connector_name(connector),
6359
		      encoder->base.id, drm_get_encoder_name(encoder));
2327 Serge 6360
 
2330 Serge 6361
	/*
6362
	 * Algorithm gets a little messy:
6363
	 *
6364
	 *   - if the connector already has an assigned crtc, use it (but make
6365
	 *     sure it's on first)
6366
	 *
6367
	 *   - try to find the first unused crtc that can drive this connector,
6368
	 *     and use that if we find one
6369
	 */
2327 Serge 6370
 
2330 Serge 6371
	/* See if we already have a CRTC for this connector */
6372
	if (encoder->crtc) {
6373
		crtc = encoder->crtc;
2327 Serge 6374
 
2330 Serge 6375
		intel_crtc = to_intel_crtc(crtc);
6376
		old->dpms_mode = intel_crtc->dpms_mode;
6377
		old->load_detect_temp = false;
2327 Serge 6378
 
2330 Serge 6379
		/* Make sure the crtc and connector are running */
6380
		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6381
			struct drm_encoder_helper_funcs *encoder_funcs;
6382
			struct drm_crtc_helper_funcs *crtc_funcs;
2327 Serge 6383
 
2330 Serge 6384
			crtc_funcs = crtc->helper_private;
6385
			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2327 Serge 6386
 
2330 Serge 6387
			encoder_funcs = encoder->helper_private;
6388
			encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6389
		}
2327 Serge 6390
 
2330 Serge 6391
		return true;
6392
	}
2327 Serge 6393
 
2330 Serge 6394
	/* Find an unused one (if possible) */
6395
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6396
		i++;
6397
		if (!(encoder->possible_crtcs & (1 << i)))
6398
			continue;
6399
		if (!possible_crtc->enabled) {
6400
			crtc = possible_crtc;
6401
			break;
6402
		}
6403
	}
2327 Serge 6404
 
2330 Serge 6405
	/*
6406
	 * If we didn't find an unused CRTC, don't use any.
6407
	 */
6408
	if (!crtc) {
6409
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
6410
		return false;
6411
	}
2327 Serge 6412
 
2330 Serge 6413
	encoder->crtc = crtc;
6414
	connector->encoder = encoder;
2327 Serge 6415
 
2330 Serge 6416
	intel_crtc = to_intel_crtc(crtc);
6417
	old->dpms_mode = intel_crtc->dpms_mode;
6418
	old->load_detect_temp = true;
6419
	old->release_fb = NULL;
2327 Serge 6420
 
2330 Serge 6421
	if (!mode)
6422
		mode = &load_detect_mode;
2327 Serge 6423
 
2330 Serge 6424
	old_fb = crtc->fb;
2327 Serge 6425
 
2330 Serge 6426
	/* We need a framebuffer large enough to accommodate all accesses
6427
	 * that the plane may generate whilst we perform load detection.
6428
	 * We can not rely on the fbcon either being present (we get called
6429
	 * during its initialisation to detect all boot displays, or it may
6430
	 * not even exist) or that it is large enough to satisfy the
6431
	 * requested mode.
6432
	 */
6433
	crtc->fb = mode_fits_in_fbdev(dev, mode);
6434
	if (crtc->fb == NULL) {
6435
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6436
		crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6437
		old->release_fb = crtc->fb;
6438
	} else
6439
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6440
	if (IS_ERR(crtc->fb)) {
6441
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6442
		crtc->fb = old_fb;
6443
		return false;
6444
	}
2327 Serge 6445
 
2330 Serge 6446
	if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6447
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6448
		if (old->release_fb)
6449
			old->release_fb->funcs->destroy(old->release_fb);
6450
		crtc->fb = old_fb;
6451
		return false;
6452
	}
2327 Serge 6453
 
2330 Serge 6454
	/* let the connector get through one full cycle before testing */
6455
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327 Serge 6456
 
2330 Serge 6457
	return true;
6458
}
2327 Serge 6459
 
2330 Serge 6460
void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6461
				    struct drm_connector *connector,
6462
				    struct intel_load_detect_pipe *old)
6463
{
6464
	struct drm_encoder *encoder = &intel_encoder->base;
6465
	struct drm_device *dev = encoder->dev;
6466
	struct drm_crtc *crtc = encoder->crtc;
6467
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6468
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2327 Serge 6469
 
2330 Serge 6470
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6471
		      connector->base.id, drm_get_connector_name(connector),
6472
		      encoder->base.id, drm_get_encoder_name(encoder));
2327 Serge 6473
 
2330 Serge 6474
	if (old->load_detect_temp) {
6475
		connector->encoder = NULL;
6476
		drm_helper_disable_unused_functions(dev);
2327 Serge 6477
 
2330 Serge 6478
		if (old->release_fb)
6479
			old->release_fb->funcs->destroy(old->release_fb);
2327 Serge 6480
 
2330 Serge 6481
		return;
6482
	}
2327 Serge 6483
 
2330 Serge 6484
	/* Switch crtc and encoder back off if necessary */
6485
	if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6486
		encoder_funcs->dpms(encoder, old->dpms_mode);
6487
		crtc_funcs->dpms(crtc, old->dpms_mode);
6488
	}
6489
}
2327 Serge 6490
 
2330 Serge 6491
/* Returns the clock of the currently programmed mode of the given pipe. */
6492
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6493
{
6494
	struct drm_i915_private *dev_priv = dev->dev_private;
6495
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6496
	int pipe = intel_crtc->pipe;
6497
	u32 dpll = I915_READ(DPLL(pipe));
6498
	u32 fp;
6499
	intel_clock_t clock;
2327 Serge 6500
 
2330 Serge 6501
	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6502
		fp = I915_READ(FP0(pipe));
6503
	else
6504
		fp = I915_READ(FP1(pipe));
2327 Serge 6505
 
2330 Serge 6506
	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6507
	if (IS_PINEVIEW(dev)) {
6508
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6509
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6510
	} else {
6511
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6512
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6513
	}
2327 Serge 6514
 
2330 Serge 6515
	if (!IS_GEN2(dev)) {
6516
		if (IS_PINEVIEW(dev))
6517
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6518
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6519
		else
6520
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6521
			       DPLL_FPA01_P1_POST_DIV_SHIFT);
2327 Serge 6522
 
2330 Serge 6523
		switch (dpll & DPLL_MODE_MASK) {
6524
		case DPLLB_MODE_DAC_SERIAL:
6525
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6526
				5 : 10;
6527
			break;
6528
		case DPLLB_MODE_LVDS:
6529
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6530
				7 : 14;
6531
			break;
6532
		default:
6533
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6534
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
6535
			return 0;
6536
		}
2327 Serge 6537
 
2330 Serge 6538
		/* XXX: Handle the 100Mhz refclk */
6539
		intel_clock(dev, 96000, &clock);
6540
	} else {
6541
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327 Serge 6542
 
2330 Serge 6543
		if (is_lvds) {
6544
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6545
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
6546
			clock.p2 = 14;
2327 Serge 6547
 
2330 Serge 6548
			if ((dpll & PLL_REF_INPUT_MASK) ==
6549
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6550
				/* XXX: might not be 66MHz */
6551
				intel_clock(dev, 66000, &clock);
6552
			} else
6553
				intel_clock(dev, 48000, &clock);
6554
		} else {
6555
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
6556
				clock.p1 = 2;
6557
			else {
6558
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6559
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6560
			}
6561
			if (dpll & PLL_P2_DIVIDE_BY_4)
6562
				clock.p2 = 4;
6563
			else
6564
				clock.p2 = 2;
2327 Serge 6565
 
2330 Serge 6566
			intel_clock(dev, 48000, &clock);
6567
		}
6568
	}
2327 Serge 6569
 
2330 Serge 6570
	/* XXX: It would be nice to validate the clocks, but we can't reuse
6571
	 * i830PllIsValid() because it relies on the xf86_config connector
6572
	 * configuration being accurate, which it isn't necessarily.
6573
	 */
2327 Serge 6574
 
2330 Serge 6575
	return clock.dot;
6576
}
2327 Serge 6577
 
2330 Serge 6578
/** Returns the currently programmed mode of the given pipe. */
6579
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6580
					     struct drm_crtc *crtc)
6581
{
6582
	struct drm_i915_private *dev_priv = dev->dev_private;
6583
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6584
	int pipe = intel_crtc->pipe;
6585
	struct drm_display_mode *mode;
6586
	int htot = I915_READ(HTOTAL(pipe));
6587
	int hsync = I915_READ(HSYNC(pipe));
6588
	int vtot = I915_READ(VTOTAL(pipe));
6589
	int vsync = I915_READ(VSYNC(pipe));
2327 Serge 6590
 
2330 Serge 6591
	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6592
	if (!mode)
6593
		return NULL;
6594
 
6595
	mode->clock = intel_crtc_clock_get(dev, crtc);
6596
	mode->hdisplay = (htot & 0xffff) + 1;
6597
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6598
	mode->hsync_start = (hsync & 0xffff) + 1;
6599
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6600
	mode->vdisplay = (vtot & 0xffff) + 1;
6601
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6602
	mode->vsync_start = (vsync & 0xffff) + 1;
6603
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6604
 
6605
	drm_mode_set_name(mode);
6606
	drm_mode_set_crtcinfo(mode, 0);
6607
 
6608
	return mode;
6609
}
6610
 
6611
#define GPU_IDLE_TIMEOUT 500 /* ms */
6612
 
6613
 
6614
 
6615
 
6616
#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6617
 
6618
 
6619
 
6620
 
2327 Serge 6621
static void intel_increase_pllclock(struct drm_crtc *crtc)
6622
{
6623
	struct drm_device *dev = crtc->dev;
6624
	drm_i915_private_t *dev_priv = dev->dev_private;
6625
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626
	int pipe = intel_crtc->pipe;
6627
	int dpll_reg = DPLL(pipe);
6628
	int dpll;
6629
 
2336 Serge 6630
    ENTER();
6631
 
2327 Serge 6632
	if (HAS_PCH_SPLIT(dev))
6633
		return;
6634
 
6635
	if (!dev_priv->lvds_downclock_avail)
6636
		return;
6637
 
6638
	dpll = I915_READ(dpll_reg);
6639
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6640
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
6641
 
6642
		/* Unlock panel regs */
6643
		I915_WRITE(PP_CONTROL,
6644
			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6645
 
6646
		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6647
		I915_WRITE(dpll_reg, dpll);
6648
		intel_wait_for_vblank(dev, pipe);
6649
 
6650
		dpll = I915_READ(dpll_reg);
6651
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
6652
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6653
 
6654
		/* ...and lock them again */
6655
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6656
	}
6657
 
2336 Serge 6658
    LEAVE();
6659
 
2327 Serge 6660
	/* Schedule downclock */
6661
}
6662
 
6663
 
6664
 
6665
 
6666
 
6667
 
6668
 
6669
 
6670
 
6671
 
6672
 
6673
 
6674
 
6675
 
6676
 
6677
 
6678
 
6679
 
6680
 
6681
 
6682
 
6683
 
2330 Serge 6684
static void intel_crtc_destroy(struct drm_crtc *crtc)
6685
{
6686
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6687
	struct drm_device *dev = crtc->dev;
6688
	struct intel_unpin_work *work;
6689
	unsigned long flags;
2327 Serge 6690
 
2330 Serge 6691
	spin_lock_irqsave(&dev->event_lock, flags);
6692
	work = intel_crtc->unpin_work;
6693
	intel_crtc->unpin_work = NULL;
6694
	spin_unlock_irqrestore(&dev->event_lock, flags);
2327 Serge 6695
 
2330 Serge 6696
	if (work) {
6697
//		cancel_work_sync(&work->work);
6698
		kfree(work);
6699
	}
2327 Serge 6700
 
2330 Serge 6701
	drm_crtc_cleanup(crtc);
2327 Serge 6702
 
2330 Serge 6703
	kfree(intel_crtc);
6704
}
2327 Serge 6705
 
6706
 
6707
 
6708
 
6709
 
6710
 
6711
 
6712
 
6713
 
6714
 
6715
 
6716
 
6717
 
6718
 
6719
 
6720
 
6721
 
6722
 
6723
 
6724
 
6725
 
6726
 
6727
 
6728
 
6729
 
6730
 
6731
 
6732
 
6733
 
6734
 
6735
 
6736
 
6737
 
6738
 
6739
 
6740
 
6741
 
6742
 
6743
 
6744
 
6745
 
6746
 
6747
 
6748
 
6749
 
6750
 
6751
 
6752
 
6753
 
6754
 
6755
 
6756
 
6757
 
6758
 
6759
 
6760
 
6761
 
6762
 
6763
 
6764
 
6765
 
6766
 
6767
 
6768
 
6769
 
6770
 
2330 Serge 6771
static void intel_sanitize_modesetting(struct drm_device *dev,
6772
				       int pipe, int plane)
6773
{
6774
	struct drm_i915_private *dev_priv = dev->dev_private;
6775
	u32 reg, val;
2327 Serge 6776
 
2330 Serge 6777
	if (HAS_PCH_SPLIT(dev))
6778
		return;
2327 Serge 6779
 
2330 Serge 6780
	/* Who knows what state these registers were left in by the BIOS or
6781
	 * grub?
6782
	 *
6783
	 * If we leave the registers in a conflicting state (e.g. with the
6784
	 * display plane reading from the other pipe than the one we intend
6785
	 * to use) then when we attempt to teardown the active mode, we will
6786
	 * not disable the pipes and planes in the correct order -- leaving
6787
	 * a plane reading from a disabled pipe and possibly leading to
6788
	 * undefined behaviour.
6789
	 */
2327 Serge 6790
 
2330 Serge 6791
	reg = DSPCNTR(plane);
6792
	val = I915_READ(reg);
2327 Serge 6793
 
2330 Serge 6794
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
6795
		return;
6796
	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6797
		return;
2327 Serge 6798
 
2330 Serge 6799
	/* This display plane is active and attached to the other CPU pipe. */
6800
	pipe = !pipe;
2327 Serge 6801
 
2330 Serge 6802
	/* Disable the plane and wait for it to stop reading from the pipe. */
6803
	intel_disable_plane(dev_priv, plane, pipe);
6804
	intel_disable_pipe(dev_priv, pipe);
6805
}
2327 Serge 6806
 
2330 Serge 6807
static void intel_crtc_reset(struct drm_crtc *crtc)
6808
{
6809
	struct drm_device *dev = crtc->dev;
6810
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 Serge 6811
 
2330 Serge 6812
	/* Reset flags back to the 'unknown' status so that they
6813
	 * will be correctly set on the initial modeset.
6814
	 */
6815
	intel_crtc->dpms_mode = -1;
2327 Serge 6816
 
2330 Serge 6817
	/* We need to fix up any BIOS configuration that conflicts with
6818
	 * our expectations.
6819
	 */
6820
	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6821
}
2327 Serge 6822
 
2330 Serge 6823
static struct drm_crtc_helper_funcs intel_helper_funcs = {
6824
	.dpms = intel_crtc_dpms,
6825
	.mode_fixup = intel_crtc_mode_fixup,
6826
	.mode_set = intel_crtc_mode_set,
6827
	.mode_set_base = intel_pipe_set_base,
6828
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
6829
	.load_lut = intel_crtc_load_lut,
6830
	.disable = intel_crtc_disable,
6831
};
2327 Serge 6832
 
2330 Serge 6833
static const struct drm_crtc_funcs intel_crtc_funcs = {
6834
	.reset = intel_crtc_reset,
6835
//	.cursor_set = intel_crtc_cursor_set,
6836
//	.cursor_move = intel_crtc_cursor_move,
6837
	.gamma_set = intel_crtc_gamma_set,
6838
	.set_config = drm_crtc_helper_set_config,
6839
	.destroy = intel_crtc_destroy,
6840
//	.page_flip = intel_crtc_page_flip,
6841
};
2327 Serge 6842
 
2330 Serge 6843
static void intel_crtc_init(struct drm_device *dev, int pipe)
6844
{
6845
	drm_i915_private_t *dev_priv = dev->dev_private;
6846
	struct intel_crtc *intel_crtc;
6847
	int i;
2327 Serge 6848
 
2330 Serge 6849
	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6850
	if (intel_crtc == NULL)
6851
		return;
2327 Serge 6852
 
2330 Serge 6853
	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327 Serge 6854
 
2330 Serge 6855
	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6856
	for (i = 0; i < 256; i++) {
6857
		intel_crtc->lut_r[i] = i;
6858
		intel_crtc->lut_g[i] = i;
6859
		intel_crtc->lut_b[i] = i;
6860
	}
2327 Serge 6861
 
2330 Serge 6862
	/* Swap pipes & planes for FBC on pre-965 */
6863
	intel_crtc->pipe = pipe;
6864
	intel_crtc->plane = pipe;
6865
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6866
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6867
		intel_crtc->plane = !pipe;
6868
	}
2327 Serge 6869
 
2330 Serge 6870
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6871
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6872
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6873
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327 Serge 6874
 
2330 Serge 6875
	intel_crtc_reset(&intel_crtc->base);
6876
	intel_crtc->active = true; /* force the pipe off on setup_init_config */
6877
	intel_crtc->bpp = 24; /* default for pre-Ironlake */
2327 Serge 6878
 
2330 Serge 6879
	if (HAS_PCH_SPLIT(dev)) {
2342 Serge 6880
		if (pipe == 2 && IS_IVYBRIDGE(dev))
6881
			intel_crtc->no_pll = true;
2330 Serge 6882
		intel_helper_funcs.prepare = ironlake_crtc_prepare;
6883
		intel_helper_funcs.commit = ironlake_crtc_commit;
6884
	} else {
6885
		intel_helper_funcs.prepare = i9xx_crtc_prepare;
6886
		intel_helper_funcs.commit = i9xx_crtc_commit;
6887
	}
2327 Serge 6888
 
2330 Serge 6889
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2327 Serge 6890
 
2330 Serge 6891
	intel_crtc->busy = false;
2327 Serge 6892
 
2330 Serge 6893
}
2327 Serge 6894
 
6895
 
6896
 
6897
 
6898
 
6899
 
6900
 
2330 Serge 6901
static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6902
{
6903
	struct intel_encoder *encoder;
6904
	int index_mask = 0;
6905
	int entry = 0;
2327 Serge 6906
 
2330 Serge 6907
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6908
		if (type_mask & encoder->clone_mask)
6909
			index_mask |= (1 << entry);
6910
		entry++;
6911
	}
2327 Serge 6912
 
2330 Serge 6913
	return index_mask;
6914
}
2327 Serge 6915
 
2330 Serge 6916
static bool has_edp_a(struct drm_device *dev)
6917
{
6918
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 6919
 
2330 Serge 6920
	if (!IS_MOBILE(dev))
6921
		return false;
2327 Serge 6922
 
2330 Serge 6923
	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6924
		return false;
2327 Serge 6925
 
2330 Serge 6926
	if (IS_GEN5(dev) &&
6927
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6928
		return false;
2327 Serge 6929
 
2330 Serge 6930
	return true;
6931
}
2327 Serge 6932
 
2330 Serge 6933
static void intel_setup_outputs(struct drm_device *dev)
6934
{
6935
	struct drm_i915_private *dev_priv = dev->dev_private;
6936
	struct intel_encoder *encoder;
6937
	bool dpd_is_edp = false;
6938
	bool has_lvds = false;
2327 Serge 6939
 
2336 Serge 6940
    ENTER();
6941
 
2330 Serge 6942
	if (IS_MOBILE(dev) && !IS_I830(dev))
6943
		has_lvds = intel_lvds_init(dev);
6944
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6945
		/* disable the panel fitter on everything but LVDS */
6946
		I915_WRITE(PFIT_CONTROL, 0);
6947
	}
2327 Serge 6948
 
2330 Serge 6949
	if (HAS_PCH_SPLIT(dev)) {
6950
		dpd_is_edp = intel_dpd_is_edp(dev);
2327 Serge 6951
 
2330 Serge 6952
		if (has_edp_a(dev))
6953
			intel_dp_init(dev, DP_A);
2327 Serge 6954
 
2330 Serge 6955
		if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6956
			intel_dp_init(dev, PCH_DP_D);
6957
	}
2327 Serge 6958
 
2330 Serge 6959
	intel_crt_init(dev);
2327 Serge 6960
 
2330 Serge 6961
	if (HAS_PCH_SPLIT(dev)) {
6962
		int found;
2327 Serge 6963
 
2330 Serge 6964
		if (I915_READ(HDMIB) & PORT_DETECTED) {
6965
			/* PCH SDVOB multiplex with HDMIB */
6966
			found = intel_sdvo_init(dev, PCH_SDVOB);
6967
			if (!found)
6968
				intel_hdmi_init(dev, HDMIB);
6969
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6970
				intel_dp_init(dev, PCH_DP_B);
6971
		}
2327 Serge 6972
 
2330 Serge 6973
		if (I915_READ(HDMIC) & PORT_DETECTED)
6974
			intel_hdmi_init(dev, HDMIC);
2327 Serge 6975
 
2330 Serge 6976
		if (I915_READ(HDMID) & PORT_DETECTED)
6977
			intel_hdmi_init(dev, HDMID);
2327 Serge 6978
 
2330 Serge 6979
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
6980
			intel_dp_init(dev, PCH_DP_C);
2327 Serge 6981
 
2330 Serge 6982
		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6983
			intel_dp_init(dev, PCH_DP_D);
2327 Serge 6984
 
2330 Serge 6985
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6986
		bool found = false;
2327 Serge 6987
 
2330 Serge 6988
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
6989
			DRM_DEBUG_KMS("probing SDVOB\n");
6990
			found = intel_sdvo_init(dev, SDVOB);
6991
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6992
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6993
				intel_hdmi_init(dev, SDVOB);
6994
			}
2327 Serge 6995
 
2330 Serge 6996
			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6997
				DRM_DEBUG_KMS("probing DP_B\n");
6998
				intel_dp_init(dev, DP_B);
6999
			}
7000
		}
2327 Serge 7001
 
2330 Serge 7002
		/* Before G4X SDVOC doesn't have its own detect register */
2327 Serge 7003
 
2330 Serge 7004
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
7005
			DRM_DEBUG_KMS("probing SDVOC\n");
7006
			found = intel_sdvo_init(dev, SDVOC);
7007
		}
2327 Serge 7008
 
2330 Serge 7009
		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
2327 Serge 7010
 
2330 Serge 7011
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7012
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7013
				intel_hdmi_init(dev, SDVOC);
7014
			}
7015
			if (SUPPORTS_INTEGRATED_DP(dev)) {
7016
				DRM_DEBUG_KMS("probing DP_C\n");
7017
				intel_dp_init(dev, DP_C);
7018
			}
7019
		}
2327 Serge 7020
 
2330 Serge 7021
		if (SUPPORTS_INTEGRATED_DP(dev) &&
7022
		    (I915_READ(DP_D) & DP_DETECTED)) {
7023
			DRM_DEBUG_KMS("probing DP_D\n");
7024
			intel_dp_init(dev, DP_D);
7025
		}
7026
	} else if (IS_GEN2(dev))
7027
		intel_dvo_init(dev);
2327 Serge 7028
 
2330 Serge 7029
//   if (SUPPORTS_TV(dev))
7030
//       intel_tv_init(dev);
2327 Serge 7031
 
2330 Serge 7032
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7033
		encoder->base.possible_crtcs = encoder->crtc_mask;
7034
		encoder->base.possible_clones =
7035
			intel_encoder_clones(dev, encoder->clone_mask);
7036
	}
2327 Serge 7037
 
2330 Serge 7038
	/* disable all the possible outputs/crtcs before entering KMS mode */
7039
//	drm_helper_disable_unused_functions(dev);
2336 Serge 7040
 
2342 Serge 7041
	if (HAS_PCH_SPLIT(dev))
7042
		ironlake_init_pch_refclk(dev);
7043
 
2336 Serge 7044
    LEAVE();
2330 Serge 7045
}
7046
 
7047
 
7048
 
7049
 
2327 Serge 7050
static const struct drm_mode_config_funcs intel_mode_funcs = {
7051
	.fb_create = NULL /*intel_user_framebuffer_create*/,
7052
	.output_poll_changed = NULL /*intel_fb_output_poll_changed*/,
7053
};
7054
 
7055
 
7056
 
7057
 
2335 Serge 7058
static const struct drm_framebuffer_funcs intel_fb_funcs = {
7059
//	.destroy = intel_user_framebuffer_destroy,
7060
//	.create_handle = intel_user_framebuffer_create_handle,
7061
};
2327 Serge 7062
 
2335 Serge 7063
int intel_framebuffer_init(struct drm_device *dev,
7064
			   struct intel_framebuffer *intel_fb,
2342 Serge 7065
			   struct drm_mode_fb_cmd2 *mode_cmd,
2335 Serge 7066
			   struct drm_i915_gem_object *obj)
7067
{
7068
	int ret;
2327 Serge 7069
 
2335 Serge 7070
	if (obj->tiling_mode == I915_TILING_Y)
7071
		return -EINVAL;
2327 Serge 7072
 
2342 Serge 7073
	if (mode_cmd->pitches[0] & 63)
2335 Serge 7074
			return -EINVAL;
2327 Serge 7075
 
2342 Serge 7076
	switch (mode_cmd->pixel_format) {
7077
	case DRM_FORMAT_RGB332:
7078
	case DRM_FORMAT_RGB565:
7079
	case DRM_FORMAT_XRGB8888:
7080
	case DRM_FORMAT_ARGB8888:
7081
	case DRM_FORMAT_XRGB2101010:
7082
	case DRM_FORMAT_ARGB2101010:
7083
		/* RGB formats are common across chipsets */
2335 Serge 7084
		break;
2342 Serge 7085
	case DRM_FORMAT_YUYV:
7086
	case DRM_FORMAT_UYVY:
7087
	case DRM_FORMAT_YVYU:
7088
	case DRM_FORMAT_VYUY:
7089
		break;
2335 Serge 7090
	default:
2342 Serge 7091
		DRM_ERROR("unsupported pixel format\n");
2335 Serge 7092
		return -EINVAL;
7093
	}
2327 Serge 7094
 
2335 Serge 7095
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7096
	if (ret) {
7097
		DRM_ERROR("framebuffer init failed %d\n", ret);
7098
		return ret;
7099
	}
2327 Serge 7100
 
2335 Serge 7101
	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7102
	intel_fb->obj = obj;
7103
	return 0;
7104
}
2327 Serge 7105
 
7106
 
7107
 
7108
 
7109
 
7110
 
7111
 
7112
 
7113
 
7114
 
7115
 
7116
 
2330 Serge 7117
bool ironlake_set_drps(struct drm_device *dev, u8 val)
7118
{
7119
	struct drm_i915_private *dev_priv = dev->dev_private;
7120
	u16 rgvswctl;
2327 Serge 7121
 
2330 Serge 7122
	rgvswctl = I915_READ16(MEMSWCTL);
7123
	if (rgvswctl & MEMCTL_CMD_STS) {
7124
		DRM_DEBUG("gpu busy, RCS change rejected\n");
7125
		return false; /* still busy with another command */
7126
	}
2327 Serge 7127
 
2330 Serge 7128
	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7129
		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7130
	I915_WRITE16(MEMSWCTL, rgvswctl);
7131
	POSTING_READ16(MEMSWCTL);
2327 Serge 7132
 
2330 Serge 7133
	rgvswctl |= MEMCTL_CMD_STS;
7134
	I915_WRITE16(MEMSWCTL, rgvswctl);
2327 Serge 7135
 
2330 Serge 7136
	return true;
7137
}
2327 Serge 7138
 
2330 Serge 7139
void ironlake_enable_drps(struct drm_device *dev)
7140
{
7141
	struct drm_i915_private *dev_priv = dev->dev_private;
7142
	u32 rgvmodectl = I915_READ(MEMMODECTL);
7143
	u8 fmax, fmin, fstart, vstart;
2327 Serge 7144
 
2330 Serge 7145
	/* Enable temp reporting */
7146
	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7147
	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2327 Serge 7148
 
2330 Serge 7149
	/* 100ms RC evaluation intervals */
7150
	I915_WRITE(RCUPEI, 100000);
7151
	I915_WRITE(RCDNEI, 100000);
2327 Serge 7152
 
2330 Serge 7153
	/* Set max/min thresholds to 90ms and 80ms respectively */
7154
	I915_WRITE(RCBMAXAVG, 90000);
7155
	I915_WRITE(RCBMINAVG, 80000);
2327 Serge 7156
 
2330 Serge 7157
	I915_WRITE(MEMIHYST, 1);
2327 Serge 7158
 
2330 Serge 7159
	/* Set up min, max, and cur for interrupt handling */
7160
	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7161
	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7162
	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7163
		MEMMODE_FSTART_SHIFT;
2327 Serge 7164
 
2330 Serge 7165
	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7166
		PXVFREQ_PX_SHIFT;
2327 Serge 7167
 
2330 Serge 7168
	dev_priv->fmax = fmax; /* IPS callback will increase this */
7169
	dev_priv->fstart = fstart;
2327 Serge 7170
 
2330 Serge 7171
	dev_priv->max_delay = fstart;
7172
	dev_priv->min_delay = fmin;
7173
	dev_priv->cur_delay = fstart;
2327 Serge 7174
 
2330 Serge 7175
	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7176
			 fmax, fmin, fstart);
2327 Serge 7177
 
2330 Serge 7178
	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2327 Serge 7179
 
2330 Serge 7180
	/*
7181
	 * Interrupts will be enabled in ironlake_irq_postinstall
7182
	 */
2327 Serge 7183
 
2330 Serge 7184
	I915_WRITE(VIDSTART, vstart);
7185
	POSTING_READ(VIDSTART);
2327 Serge 7186
 
2330 Serge 7187
	rgvmodectl |= MEMMODE_SWMODE_EN;
7188
	I915_WRITE(MEMMODECTL, rgvmodectl);
2327 Serge 7189
 
2330 Serge 7190
	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7191
		DRM_ERROR("stuck trying to change perf mode\n");
7192
	msleep(1);
2327 Serge 7193
 
2330 Serge 7194
	ironlake_set_drps(dev, fstart);
2327 Serge 7195
 
2330 Serge 7196
	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7197
		I915_READ(0x112e0);
7198
//   dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7199
	dev_priv->last_count2 = I915_READ(0x112f4);
7200
//   getrawmonotonic(&dev_priv->last_time2);
7201
}
2327 Serge 7202
 
7203
 
7204
 
7205
 
7206
 
7207
 
7208
 
7209
 
7210
 
7211
 
7212
 
7213
 
2330 Serge 7214
static unsigned long intel_pxfreq(u32 vidfreq)
7215
{
7216
	unsigned long freq;
7217
	int div = (vidfreq & 0x3f0000) >> 16;
7218
	int post = (vidfreq & 0x3000) >> 12;
7219
	int pre = (vidfreq & 0x7);
2327 Serge 7220
 
2330 Serge 7221
	if (!pre)
7222
		return 0;
2327 Serge 7223
 
2330 Serge 7224
	freq = ((div * 133333) / ((1<
2327 Serge 7225
 
2330 Serge 7226
	return freq;
7227
}
2327 Serge 7228
 
2330 Serge 7229
void intel_init_emon(struct drm_device *dev)
7230
{
7231
	struct drm_i915_private *dev_priv = dev->dev_private;
7232
	u32 lcfuse;
7233
	u8 pxw[16];
7234
	int i;
2327 Serge 7235
 
2330 Serge 7236
	/* Disable to program */
7237
	I915_WRITE(ECR, 0);
7238
	POSTING_READ(ECR);
2327 Serge 7239
 
2330 Serge 7240
	/* Program energy weights for various events */
7241
	I915_WRITE(SDEW, 0x15040d00);
7242
	I915_WRITE(CSIEW0, 0x007f0000);
7243
	I915_WRITE(CSIEW1, 0x1e220004);
7244
	I915_WRITE(CSIEW2, 0x04000004);
2327 Serge 7245
 
2330 Serge 7246
	for (i = 0; i < 5; i++)
7247
		I915_WRITE(PEW + (i * 4), 0);
7248
	for (i = 0; i < 3; i++)
7249
		I915_WRITE(DEW + (i * 4), 0);
2327 Serge 7250
 
2330 Serge 7251
	/* Program P-state weights to account for frequency power adjustment */
7252
	for (i = 0; i < 16; i++) {
7253
		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7254
		unsigned long freq = intel_pxfreq(pxvidfreq);
7255
		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7256
			PXVFREQ_PX_SHIFT;
7257
		unsigned long val;
2327 Serge 7258
 
2330 Serge 7259
		val = vid * vid;
7260
		val *= (freq / 1000);
7261
		val *= 255;
7262
		val /= (127*127*900);
7263
		if (val > 0xff)
7264
			DRM_ERROR("bad pxval: %ld\n", val);
7265
		pxw[i] = val;
7266
	}
7267
	/* Render standby states get 0 weight */
7268
	pxw[14] = 0;
7269
	pxw[15] = 0;
2327 Serge 7270
 
2330 Serge 7271
	for (i = 0; i < 4; i++) {
7272
		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7273
			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7274
		I915_WRITE(PXW + (i * 4), val);
7275
	}
2327 Serge 7276
 
2330 Serge 7277
	/* Adjust magic regs to magic values (more experimental results) */
7278
	I915_WRITE(OGW0, 0);
7279
	I915_WRITE(OGW1, 0);
7280
	I915_WRITE(EG0, 0x00007f00);
7281
	I915_WRITE(EG1, 0x0000000e);
7282
	I915_WRITE(EG2, 0x000e0000);
7283
	I915_WRITE(EG3, 0x68000300);
7284
	I915_WRITE(EG4, 0x42000000);
7285
	I915_WRITE(EG5, 0x00140031);
7286
	I915_WRITE(EG6, 0);
7287
	I915_WRITE(EG7, 0);
2327 Serge 7288
 
2330 Serge 7289
	for (i = 0; i < 8; i++)
7290
		I915_WRITE(PXWL + (i * 4), 0);
2327 Serge 7291
 
2330 Serge 7292
	/* Enable PMON + select events */
7293
	I915_WRITE(ECR, 0x80000019);
2327 Serge 7294
 
2330 Serge 7295
	lcfuse = I915_READ(LCFUSE02);
7296
 
7297
	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7298
}
7299
 
2342 Serge 7300
static bool intel_enable_rc6(struct drm_device *dev)
7301
{
7302
	/*
7303
	 * Respect the kernel parameter if it is set
7304
	 */
7305
	if (i915_enable_rc6 >= 0)
7306
		return i915_enable_rc6;
7307
 
7308
	/*
7309
	 * Disable RC6 on Ironlake
7310
	 */
7311
	if (INTEL_INFO(dev)->gen == 5)
7312
		return 0;
7313
 
7314
	/*
7315
	 * Disable rc6 on Sandybridge
7316
	 */
7317
	if (INTEL_INFO(dev)->gen == 6) {
7318
		DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
7319
		return 0;
7320
	}
7321
	DRM_DEBUG_DRIVER("RC6 enabled\n");
7322
	return 1;
7323
}
7324
 
2330 Serge 7325
void gen6_enable_rps(struct drm_i915_private *dev_priv)
7326
{
7327
	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7328
	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7329
	u32 pcu_mbox, rc6_mask = 0;
7330
	int cur_freq, min_freq, max_freq;
7331
	int i;
7332
 
7333
	/* Here begins a magic sequence of register writes to enable
7334
	 * auto-downclocking.
7335
	 *
7336
	 * Perhaps there might be some value in exposing these to
7337
	 * userspace...
7338
	 */
7339
	I915_WRITE(GEN6_RC_STATE, 0);
7340
	mutex_lock(&dev_priv->dev->struct_mutex);
7341
	gen6_gt_force_wake_get(dev_priv);
7342
 
7343
	/* disable the counters and set deterministic thresholds */
7344
	I915_WRITE(GEN6_RC_CONTROL, 0);
7345
 
7346
	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7347
	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7348
	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7349
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7350
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7351
 
7352
	for (i = 0; i < I915_NUM_RINGS; i++)
7353
		I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7354
 
7355
	I915_WRITE(GEN6_RC_SLEEP, 0);
7356
	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7357
	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7358
	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7359
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7360
 
2342 Serge 7361
	if (intel_enable_rc6(dev_priv->dev))
2330 Serge 7362
		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7363
			GEN6_RC_CTL_RC6_ENABLE;
7364
 
7365
	I915_WRITE(GEN6_RC_CONTROL,
7366
		   rc6_mask |
7367
		   GEN6_RC_CTL_EI_MODE(1) |
7368
		   GEN6_RC_CTL_HW_ENABLE);
7369
 
7370
	I915_WRITE(GEN6_RPNSWREQ,
7371
		   GEN6_FREQUENCY(10) |
7372
		   GEN6_OFFSET(0) |
7373
		   GEN6_AGGRESSIVE_TURBO);
7374
	I915_WRITE(GEN6_RC_VIDEO_FREQ,
7375
		   GEN6_FREQUENCY(12));
7376
 
7377
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7378
	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7379
		   18 << 24 |
7380
		   6 << 16);
7381
	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7382
	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7383
	I915_WRITE(GEN6_RP_UP_EI, 100000);
7384
	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7385
	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7386
	I915_WRITE(GEN6_RP_CONTROL,
7387
		   GEN6_RP_MEDIA_TURBO |
2342 Serge 7388
		   GEN6_RP_MEDIA_HW_MODE |
2330 Serge 7389
		   GEN6_RP_MEDIA_IS_GFX |
7390
		   GEN6_RP_ENABLE |
7391
		   GEN6_RP_UP_BUSY_AVG |
7392
		   GEN6_RP_DOWN_IDLE_CONT);
7393
 
7394
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7395
		     500))
7396
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7397
 
7398
	I915_WRITE(GEN6_PCODE_DATA, 0);
7399
	I915_WRITE(GEN6_PCODE_MAILBOX,
7400
		   GEN6_PCODE_READY |
7401
		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7402
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7403
		     500))
7404
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7405
 
7406
	min_freq = (rp_state_cap & 0xff0000) >> 16;
7407
	max_freq = rp_state_cap & 0xff;
7408
	cur_freq = (gt_perf_status & 0xff00) >> 8;
7409
 
7410
	/* Check for overclock support */
7411
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7412
		     500))
7413
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7414
	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7415
	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7416
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7417
		     500))
7418
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7419
	if (pcu_mbox & (1<<31)) { /* OC supported */
7420
		max_freq = pcu_mbox & 0xff;
7421
		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7422
	}
7423
 
7424
	/* In units of 100MHz */
7425
	dev_priv->max_delay = max_freq;
7426
	dev_priv->min_delay = min_freq;
7427
	dev_priv->cur_delay = cur_freq;
7428
 
7429
	/* requires MSI enabled */
7430
	I915_WRITE(GEN6_PMIER,
7431
		   GEN6_PM_MBOX_EVENT |
7432
		   GEN6_PM_THERMAL_EVENT |
7433
		   GEN6_PM_RP_DOWN_TIMEOUT |
7434
		   GEN6_PM_RP_UP_THRESHOLD |
7435
		   GEN6_PM_RP_DOWN_THRESHOLD |
7436
		   GEN6_PM_RP_UP_EI_EXPIRED |
7437
		   GEN6_PM_RP_DOWN_EI_EXPIRED);
7438
//   spin_lock_irq(&dev_priv->rps_lock);
7439
//   WARN_ON(dev_priv->pm_iir != 0);
7440
	I915_WRITE(GEN6_PMIMR, 0);
7441
//   spin_unlock_irq(&dev_priv->rps_lock);
7442
	/* enable all PM interrupts */
7443
	I915_WRITE(GEN6_PMINTRMSK, 0);
7444
 
7445
	gen6_gt_force_wake_put(dev_priv);
7446
	mutex_unlock(&dev_priv->dev->struct_mutex);
7447
}
7448
 
7449
void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7450
{
7451
	int min_freq = 15;
7452
	int gpu_freq, ia_freq, max_ia_freq;
7453
	int scaling_factor = 180;
7454
 
7455
//   max_ia_freq = cpufreq_quick_get_max(0);
7456
	/*
7457
	 * Default to measured freq if none found, PCU will ensure we don't go
7458
	 * over
7459
	 */
7460
//   if (!max_ia_freq)
7461
		max_ia_freq = 3000000; //tsc_khz;
7462
 
7463
	/* Convert from kHz to MHz */
7464
	max_ia_freq /= 1000;
7465
 
7466
	mutex_lock(&dev_priv->dev->struct_mutex);
7467
 
7468
	/*
7469
	 * For each potential GPU frequency, load a ring frequency we'd like
7470
	 * to use for memory access.  We do this by specifying the IA frequency
7471
	 * the PCU should use as a reference to determine the ring frequency.
7472
	 */
7473
	for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7474
	     gpu_freq--) {
7475
		int diff = dev_priv->max_delay - gpu_freq;
7476
 
7477
		/*
7478
		 * For GPU frequencies less than 750MHz, just use the lowest
7479
		 * ring freq.
7480
		 */
7481
		if (gpu_freq < min_freq)
7482
			ia_freq = 800;
7483
		else
7484
			ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7485
		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7486
 
7487
		I915_WRITE(GEN6_PCODE_DATA,
7488
			   (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7489
			   gpu_freq);
7490
		I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7491
			   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7492
		if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7493
			      GEN6_PCODE_READY) == 0, 10)) {
7494
			DRM_ERROR("pcode write of freq table timed out\n");
7495
			continue;
7496
		}
7497
	}
7498
 
7499
	mutex_unlock(&dev_priv->dev->struct_mutex);
7500
}
7501
 
2327 Serge 7502
static void ironlake_init_clock_gating(struct drm_device *dev)
7503
{
7504
    struct drm_i915_private *dev_priv = dev->dev_private;
7505
    uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7506
 
7507
    /* Required for FBC */
7508
    dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7509
        DPFCRUNIT_CLOCK_GATE_DISABLE |
7510
        DPFDUNIT_CLOCK_GATE_DISABLE;
7511
    /* Required for CxSR */
7512
    dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7513
 
7514
    I915_WRITE(PCH_3DCGDIS0,
7515
           MARIUNIT_CLOCK_GATE_DISABLE |
7516
           SVSMUNIT_CLOCK_GATE_DISABLE);
7517
    I915_WRITE(PCH_3DCGDIS1,
7518
           VFMUNIT_CLOCK_GATE_DISABLE);
7519
 
7520
    I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7521
 
7522
    /*
7523
     * According to the spec the following bits should be set in
7524
     * order to enable memory self-refresh
7525
     * The bit 22/21 of 0x42004
7526
     * The bit 5 of 0x42020
7527
     * The bit 15 of 0x45000
7528
     */
7529
    I915_WRITE(ILK_DISPLAY_CHICKEN2,
7530
           (I915_READ(ILK_DISPLAY_CHICKEN2) |
7531
            ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7532
    I915_WRITE(ILK_DSPCLK_GATE,
7533
           (I915_READ(ILK_DSPCLK_GATE) |
7534
            ILK_DPARB_CLK_GATE));
7535
    I915_WRITE(DISP_ARB_CTL,
7536
           (I915_READ(DISP_ARB_CTL) |
7537
            DISP_FBC_WM_DIS));
7538
    I915_WRITE(WM3_LP_ILK, 0);
7539
    I915_WRITE(WM2_LP_ILK, 0);
7540
    I915_WRITE(WM1_LP_ILK, 0);
7541
 
7542
    /*
7543
     * Based on the document from hardware guys the following bits
7544
     * should be set unconditionally in order to enable FBC.
7545
     * The bit 22 of 0x42000
7546
     * The bit 22 of 0x42004
7547
     * The bit 7,8,9 of 0x42020.
7548
     */
7549
    if (IS_IRONLAKE_M(dev)) {
7550
        I915_WRITE(ILK_DISPLAY_CHICKEN1,
7551
               I915_READ(ILK_DISPLAY_CHICKEN1) |
7552
               ILK_FBCQ_DIS);
7553
        I915_WRITE(ILK_DISPLAY_CHICKEN2,
7554
               I915_READ(ILK_DISPLAY_CHICKEN2) |
7555
               ILK_DPARB_GATE);
7556
        I915_WRITE(ILK_DSPCLK_GATE,
7557
               I915_READ(ILK_DSPCLK_GATE) |
7558
               ILK_DPFC_DIS1 |
7559
               ILK_DPFC_DIS2 |
7560
               ILK_CLK_FBC);
7561
    }
7562
 
7563
    I915_WRITE(ILK_DISPLAY_CHICKEN2,
7564
           I915_READ(ILK_DISPLAY_CHICKEN2) |
7565
           ILK_ELPIN_409_SELECT);
7566
    I915_WRITE(_3D_CHICKEN2,
7567
           _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7568
           _3D_CHICKEN2_WM_READ_PIPELINED);
7569
}
7570
 
7571
static void gen6_init_clock_gating(struct drm_device *dev)
7572
{
7573
	struct drm_i915_private *dev_priv = dev->dev_private;
7574
	int pipe;
7575
	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7576
 
7577
	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7578
 
7579
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7580
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
7581
		   ILK_ELPIN_409_SELECT);
7582
 
7583
	I915_WRITE(WM3_LP_ILK, 0);
7584
	I915_WRITE(WM2_LP_ILK, 0);
7585
	I915_WRITE(WM1_LP_ILK, 0);
7586
 
2342 Serge 7587
	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7588
	 * gating disable must be set.  Failure to set it results in
7589
	 * flickering pixels due to Z write ordering failures after
7590
	 * some amount of runtime in the Mesa "fire" demo, and Unigine
7591
	 * Sanctuary and Tropics, and apparently anything else with
7592
	 * alpha test or pixel discard.
7593
	 *
7594
	 * According to the spec, bit 11 (RCCUNIT) must also be set,
7595
	 * but we didn't debug actual testcases to find it out.
7596
	 */
7597
	I915_WRITE(GEN6_UCGCTL2,
7598
		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7599
		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7600
 
2327 Serge 7601
	/*
7602
	 * According to the spec the following bits should be
7603
	 * set in order to enable memory self-refresh and fbc:
7604
	 * The bit21 and bit22 of 0x42000
7605
	 * The bit21 and bit22 of 0x42004
7606
	 * The bit5 and bit7 of 0x42020
7607
	 * The bit14 of 0x70180
7608
	 * The bit14 of 0x71180
7609
	 */
7610
	I915_WRITE(ILK_DISPLAY_CHICKEN1,
7611
		   I915_READ(ILK_DISPLAY_CHICKEN1) |
7612
		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7613
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7614
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
7615
		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7616
	I915_WRITE(ILK_DSPCLK_GATE,
7617
		   I915_READ(ILK_DSPCLK_GATE) |
7618
		   ILK_DPARB_CLK_GATE  |
7619
		   ILK_DPFD_CLK_GATE);
7620
 
7621
	for_each_pipe(pipe) {
7622
		I915_WRITE(DSPCNTR(pipe),
7623
			   I915_READ(DSPCNTR(pipe)) |
7624
			   DISPPLANE_TRICKLE_FEED_DISABLE);
7625
		intel_flush_display_plane(dev_priv, pipe);
7626
	}
7627
}
7628
 
7629
static void ivybridge_init_clock_gating(struct drm_device *dev)
7630
{
7631
	struct drm_i915_private *dev_priv = dev->dev_private;
7632
	int pipe;
7633
	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7634
 
7635
	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7636
 
7637
	I915_WRITE(WM3_LP_ILK, 0);
7638
	I915_WRITE(WM2_LP_ILK, 0);
7639
	I915_WRITE(WM1_LP_ILK, 0);
7640
 
7641
	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7642
 
2342 Serge 7643
	I915_WRITE(IVB_CHICKEN3,
7644
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7645
		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
7646
 
2327 Serge 7647
	for_each_pipe(pipe) {
7648
		I915_WRITE(DSPCNTR(pipe),
7649
			   I915_READ(DSPCNTR(pipe)) |
7650
			   DISPPLANE_TRICKLE_FEED_DISABLE);
7651
		intel_flush_display_plane(dev_priv, pipe);
7652
	}
7653
}
7654
 
7655
static void g4x_init_clock_gating(struct drm_device *dev)
7656
{
7657
    struct drm_i915_private *dev_priv = dev->dev_private;
7658
    uint32_t dspclk_gate;
7659
 
7660
    I915_WRITE(RENCLK_GATE_D1, 0);
7661
    I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7662
           GS_UNIT_CLOCK_GATE_DISABLE |
7663
           CL_UNIT_CLOCK_GATE_DISABLE);
7664
    I915_WRITE(RAMCLK_GATE_D, 0);
7665
    dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7666
        OVRUNIT_CLOCK_GATE_DISABLE |
7667
        OVCUNIT_CLOCK_GATE_DISABLE;
7668
    if (IS_GM45(dev))
7669
        dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7670
    I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7671
}
7672
 
7673
static void crestline_init_clock_gating(struct drm_device *dev)
7674
{
7675
	struct drm_i915_private *dev_priv = dev->dev_private;
7676
 
7677
	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7678
	I915_WRITE(RENCLK_GATE_D2, 0);
7679
	I915_WRITE(DSPCLK_GATE_D, 0);
7680
	I915_WRITE(RAMCLK_GATE_D, 0);
7681
	I915_WRITE16(DEUC, 0);
7682
}
7683
 
7684
static void broadwater_init_clock_gating(struct drm_device *dev)
7685
{
7686
	struct drm_i915_private *dev_priv = dev->dev_private;
7687
 
7688
	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7689
		   I965_RCC_CLOCK_GATE_DISABLE |
7690
		   I965_RCPB_CLOCK_GATE_DISABLE |
7691
		   I965_ISC_CLOCK_GATE_DISABLE |
7692
		   I965_FBC_CLOCK_GATE_DISABLE);
7693
	I915_WRITE(RENCLK_GATE_D2, 0);
7694
}
7695
 
7696
static void gen3_init_clock_gating(struct drm_device *dev)
7697
{
7698
    struct drm_i915_private *dev_priv = dev->dev_private;
7699
    u32 dstate = I915_READ(D_STATE);
7700
 
7701
    dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7702
        DSTATE_DOT_CLOCK_GATING;
7703
    I915_WRITE(D_STATE, dstate);
7704
}
7705
 
7706
static void i85x_init_clock_gating(struct drm_device *dev)
7707
{
7708
	struct drm_i915_private *dev_priv = dev->dev_private;
7709
 
7710
	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7711
}
7712
 
7713
static void i830_init_clock_gating(struct drm_device *dev)
7714
{
7715
	struct drm_i915_private *dev_priv = dev->dev_private;
7716
 
7717
	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7718
}
7719
 
7720
static void ibx_init_clock_gating(struct drm_device *dev)
7721
{
7722
    struct drm_i915_private *dev_priv = dev->dev_private;
7723
 
7724
    /*
7725
     * On Ibex Peak and Cougar Point, we need to disable clock
7726
     * gating for the panel power sequencer or it will fail to
7727
     * start up when no ports are active.
7728
     */
7729
    I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7730
}
7731
 
7732
static void cpt_init_clock_gating(struct drm_device *dev)
7733
{
7734
    struct drm_i915_private *dev_priv = dev->dev_private;
7735
    int pipe;
7736
 
7737
    /*
7738
     * On Ibex Peak and Cougar Point, we need to disable clock
7739
     * gating for the panel power sequencer or it will fail to
7740
     * start up when no ports are active.
7741
     */
7742
    I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7743
    I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7744
           DPLS_EDP_PPS_FIX_DIS);
7745
    /* Without this, mode sets may fail silently on FDI */
7746
    for_each_pipe(pipe)
7747
        I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7748
}
7749
 
2332 Serge 7750
static void ironlake_teardown_rc6(struct drm_device *dev)
7751
{
7752
	struct drm_i915_private *dev_priv = dev->dev_private;
2327 Serge 7753
 
2332 Serge 7754
	if (dev_priv->renderctx) {
7755
//		i915_gem_object_unpin(dev_priv->renderctx);
7756
//		drm_gem_object_unreference(&dev_priv->renderctx->base);
7757
		dev_priv->renderctx = NULL;
7758
	}
2327 Serge 7759
 
2332 Serge 7760
	if (dev_priv->pwrctx) {
7761
//		i915_gem_object_unpin(dev_priv->pwrctx);
7762
//		drm_gem_object_unreference(&dev_priv->pwrctx->base);
7763
		dev_priv->pwrctx = NULL;
7764
	}
7765
}
2327 Serge 7766
 
2339 Serge 7767
static void ironlake_disable_rc6(struct drm_device *dev)
7768
{
7769
	struct drm_i915_private *dev_priv = dev->dev_private;
2330 Serge 7770
 
2339 Serge 7771
	if (I915_READ(PWRCTXA)) {
7772
		/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7773
		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7774
		wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7775
			 50);
2332 Serge 7776
 
2339 Serge 7777
		I915_WRITE(PWRCTXA, 0);
7778
		POSTING_READ(PWRCTXA);
2332 Serge 7779
 
2339 Serge 7780
		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7781
		POSTING_READ(RSTDBYCTL);
7782
	}
2332 Serge 7783
 
2339 Serge 7784
	ironlake_teardown_rc6(dev);
7785
}
2332 Serge 7786
 
7787
static int ironlake_setup_rc6(struct drm_device *dev)
7788
{
7789
	struct drm_i915_private *dev_priv = dev->dev_private;
7790
 
7791
	if (dev_priv->renderctx == NULL)
7792
//		dev_priv->renderctx = intel_alloc_context_page(dev);
7793
	if (!dev_priv->renderctx)
7794
		return -ENOMEM;
7795
 
7796
	if (dev_priv->pwrctx == NULL)
7797
//		dev_priv->pwrctx = intel_alloc_context_page(dev);
7798
	if (!dev_priv->pwrctx) {
7799
		ironlake_teardown_rc6(dev);
7800
		return -ENOMEM;
7801
	}
7802
 
7803
	return 0;
7804
}
7805
 
7806
void ironlake_enable_rc6(struct drm_device *dev)
7807
{
7808
	struct drm_i915_private *dev_priv = dev->dev_private;
7809
	int ret;
7810
 
7811
	/* rc6 disabled by default due to repeated reports of hanging during
7812
	 * boot and resume.
7813
	 */
2342 Serge 7814
	if (!intel_enable_rc6(dev))
2332 Serge 7815
		return;
7816
 
7817
	mutex_lock(&dev->struct_mutex);
7818
	ret = ironlake_setup_rc6(dev);
7819
	if (ret) {
7820
		mutex_unlock(&dev->struct_mutex);
7821
		return;
7822
	}
7823
 
7824
	/*
7825
	 * GPU can automatically power down the render unit if given a page
7826
	 * to save state.
7827
	 */
7828
#if 0
7829
	ret = BEGIN_LP_RING(6);
7830
	if (ret) {
7831
		ironlake_teardown_rc6(dev);
7832
		mutex_unlock(&dev->struct_mutex);
7833
		return;
7834
	}
7835
 
7836
	OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7837
	OUT_RING(MI_SET_CONTEXT);
7838
	OUT_RING(dev_priv->renderctx->gtt_offset |
7839
		 MI_MM_SPACE_GTT |
7840
		 MI_SAVE_EXT_STATE_EN |
7841
		 MI_RESTORE_EXT_STATE_EN |
7842
		 MI_RESTORE_INHIBIT);
7843
	OUT_RING(MI_SUSPEND_FLUSH);
7844
	OUT_RING(MI_NOOP);
7845
	OUT_RING(MI_FLUSH);
7846
	ADVANCE_LP_RING();
7847
 
7848
	/*
7849
	 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7850
	 * does an implicit flush, combined with MI_FLUSH above, it should be
7851
	 * safe to assume that renderctx is valid
7852
	 */
7853
	ret = intel_wait_ring_idle(LP_RING(dev_priv));
7854
	if (ret) {
7855
		DRM_ERROR("failed to enable ironlake power power savings\n");
7856
		ironlake_teardown_rc6(dev);
7857
		mutex_unlock(&dev->struct_mutex);
7858
		return;
7859
	}
7860
#endif
7861
 
7862
	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7863
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7864
	mutex_unlock(&dev->struct_mutex);
7865
}
7866
 
2330 Serge 7867
void intel_init_clock_gating(struct drm_device *dev)
7868
{
7869
	struct drm_i915_private *dev_priv = dev->dev_private;
7870
 
7871
	dev_priv->display.init_clock_gating(dev);
7872
 
7873
	if (dev_priv->display.init_pch_clock_gating)
7874
		dev_priv->display.init_pch_clock_gating(dev);
7875
}
7876
 
2327 Serge 7877
/* Set up chip specific display functions */
7878
static void intel_init_display(struct drm_device *dev)
7879
{
7880
    struct drm_i915_private *dev_priv = dev->dev_private;
7881
 
7882
    /* We always want a DPMS function */
7883
    if (HAS_PCH_SPLIT(dev)) {
7884
        dev_priv->display.dpms = ironlake_crtc_dpms;
7885
        dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7886
        dev_priv->display.update_plane = ironlake_update_plane;
7887
    } else {
7888
        dev_priv->display.dpms = i9xx_crtc_dpms;
7889
        dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7890
        dev_priv->display.update_plane = i9xx_update_plane;
7891
    }
7892
 
7893
    if (I915_HAS_FBC(dev)) {
7894
        if (HAS_PCH_SPLIT(dev)) {
7895
            dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7896
            dev_priv->display.enable_fbc = ironlake_enable_fbc;
7897
            dev_priv->display.disable_fbc = ironlake_disable_fbc;
7898
        } else if (IS_GM45(dev)) {
7899
            dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7900
            dev_priv->display.enable_fbc = g4x_enable_fbc;
7901
            dev_priv->display.disable_fbc = g4x_disable_fbc;
7902
        } else if (IS_CRESTLINE(dev)) {
7903
            dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7904
            dev_priv->display.enable_fbc = i8xx_enable_fbc;
7905
            dev_priv->display.disable_fbc = i8xx_disable_fbc;
7906
        }
7907
        /* 855GM needs testing */
7908
    }
7909
 
7910
    /* Returns the core display clock speed */
2342 Serge 7911
	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
2327 Serge 7912
        dev_priv->display.get_display_clock_speed =
7913
            i945_get_display_clock_speed;
7914
    else if (IS_I915G(dev))
7915
        dev_priv->display.get_display_clock_speed =
7916
            i915_get_display_clock_speed;
7917
    else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7918
        dev_priv->display.get_display_clock_speed =
7919
            i9xx_misc_get_display_clock_speed;
7920
    else if (IS_I915GM(dev))
7921
        dev_priv->display.get_display_clock_speed =
7922
            i915gm_get_display_clock_speed;
7923
    else if (IS_I865G(dev))
7924
        dev_priv->display.get_display_clock_speed =
7925
            i865_get_display_clock_speed;
7926
    else if (IS_I85X(dev))
7927
        dev_priv->display.get_display_clock_speed =
7928
            i855_get_display_clock_speed;
7929
    else /* 852, 830 */
7930
        dev_priv->display.get_display_clock_speed =
7931
            i830_get_display_clock_speed;
7932
 
7933
    /* For FIFO watermark updates */
7934
    if (HAS_PCH_SPLIT(dev)) {
2342 Serge 7935
		dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
7936
		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
7937
 
7938
		/* IVB configs may use multi-threaded forcewake */
7939
		if (IS_IVYBRIDGE(dev)) {
7940
			u32	ecobus;
7941
 
7942
			/* A small trick here - if the bios hasn't configured MT forcewake,
7943
			 * and if the device is in RC6, then force_wake_mt_get will not wake
7944
			 * the device and the ECOBUS read will return zero. Which will be
7945
			 * (correctly) interpreted by the test below as MT forcewake being
7946
			 * disabled.
7947
			 */
7948
			mutex_lock(&dev->struct_mutex);
7949
			__gen6_gt_force_wake_mt_get(dev_priv);
7950
			ecobus = I915_READ_NOTRACE(ECOBUS);
7951
			__gen6_gt_force_wake_mt_put(dev_priv);
7952
			mutex_unlock(&dev->struct_mutex);
7953
 
7954
			if (ecobus & FORCEWAKE_MT_ENABLE) {
7955
				DRM_DEBUG_KMS("Using MT version of forcewake\n");
7956
				dev_priv->display.force_wake_get =
7957
					__gen6_gt_force_wake_mt_get;
7958
				dev_priv->display.force_wake_put =
7959
					__gen6_gt_force_wake_mt_put;
7960
			}
7961
		}
7962
 
2327 Serge 7963
        if (HAS_PCH_IBX(dev))
7964
            dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7965
        else if (HAS_PCH_CPT(dev))
7966
            dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7967
 
7968
        if (IS_GEN5(dev)) {
7969
            if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7970
                dev_priv->display.update_wm = ironlake_update_wm;
7971
            else {
7972
                DRM_DEBUG_KMS("Failed to get proper latency. "
7973
                          "Disable CxSR\n");
7974
                dev_priv->display.update_wm = NULL;
7975
            }
7976
            dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7977
            dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
2342 Serge 7978
			dev_priv->display.write_eld = ironlake_write_eld;
2327 Serge 7979
        } else if (IS_GEN6(dev)) {
7980
            if (SNB_READ_WM0_LATENCY()) {
7981
                dev_priv->display.update_wm = sandybridge_update_wm;
2342 Serge 7982
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
2327 Serge 7983
            } else {
7984
                DRM_DEBUG_KMS("Failed to read display plane latency. "
7985
                          "Disable CxSR\n");
7986
                dev_priv->display.update_wm = NULL;
7987
            }
7988
            dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7989
            dev_priv->display.init_clock_gating = gen6_init_clock_gating;
2342 Serge 7990
			dev_priv->display.write_eld = ironlake_write_eld;
2327 Serge 7991
        } else if (IS_IVYBRIDGE(dev)) {
7992
            /* FIXME: detect B0+ stepping and use auto training */
7993
            dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7994
            if (SNB_READ_WM0_LATENCY()) {
7995
                dev_priv->display.update_wm = sandybridge_update_wm;
2342 Serge 7996
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
2327 Serge 7997
            } else {
7998
                DRM_DEBUG_KMS("Failed to read display plane latency. "
7999
                          "Disable CxSR\n");
8000
                dev_priv->display.update_wm = NULL;
8001
            }
8002
            dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
2342 Serge 8003
			dev_priv->display.write_eld = ironlake_write_eld;
2327 Serge 8004
        } else
8005
            dev_priv->display.update_wm = NULL;
8006
    } else if (IS_PINEVIEW(dev)) {
8007
        if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8008
                        dev_priv->is_ddr3,
8009
                        dev_priv->fsb_freq,
8010
                        dev_priv->mem_freq)) {
8011
            DRM_INFO("failed to find known CxSR latency "
8012
                 "(found ddr%s fsb freq %d, mem freq %d), "
8013
                 "disabling CxSR\n",
2342 Serge 8014
				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
2327 Serge 8015
                 dev_priv->fsb_freq, dev_priv->mem_freq);
8016
            /* Disable CxSR and never update its watermark again */
8017
            pineview_disable_cxsr(dev);
8018
            dev_priv->display.update_wm = NULL;
8019
        } else
8020
            dev_priv->display.update_wm = pineview_update_wm;
8021
        dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8022
    } else if (IS_G4X(dev)) {
2342 Serge 8023
		dev_priv->display.write_eld = g4x_write_eld;
2327 Serge 8024
        dev_priv->display.update_wm = g4x_update_wm;
8025
        dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8026
    } else if (IS_GEN4(dev)) {
8027
        dev_priv->display.update_wm = i965_update_wm;
8028
        if (IS_CRESTLINE(dev))
8029
            dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8030
        else if (IS_BROADWATER(dev))
8031
            dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8032
    } else if (IS_GEN3(dev)) {
8033
        dev_priv->display.update_wm = i9xx_update_wm;
8034
        dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8035
        dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8036
    } else if (IS_I865G(dev)) {
8037
        dev_priv->display.update_wm = i830_update_wm;
8038
        dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8039
        dev_priv->display.get_fifo_size = i830_get_fifo_size;
8040
    } else if (IS_I85X(dev)) {
8041
        dev_priv->display.update_wm = i9xx_update_wm;
8042
        dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8043
        dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8044
    } else {
8045
        dev_priv->display.update_wm = i830_update_wm;
8046
        dev_priv->display.init_clock_gating = i830_init_clock_gating;
8047
        if (IS_845G(dev))
8048
            dev_priv->display.get_fifo_size = i845_get_fifo_size;
8049
        else
8050
            dev_priv->display.get_fifo_size = i830_get_fifo_size;
8051
    }
8052
 
8053
    /* Default just returns -ENODEV to indicate unsupported */
8054
//    dev_priv->display.queue_flip = intel_default_queue_flip;
8055
 
8056
#if 0
8057
    switch (INTEL_INFO(dev)->gen) {
8058
    case 2:
8059
        dev_priv->display.queue_flip = intel_gen2_queue_flip;
8060
        break;
8061
 
8062
    case 3:
8063
        dev_priv->display.queue_flip = intel_gen3_queue_flip;
8064
        break;
8065
 
8066
    case 4:
8067
    case 5:
8068
        dev_priv->display.queue_flip = intel_gen4_queue_flip;
8069
        break;
8070
 
8071
    case 6:
8072
        dev_priv->display.queue_flip = intel_gen6_queue_flip;
8073
        break;
8074
    case 7:
8075
        dev_priv->display.queue_flip = intel_gen7_queue_flip;
8076
        break;
8077
    }
8078
#endif
8079
}
8080
 
8081
/*
8082
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8083
 * resume, or other times.  This quirk makes sure that's the case for
8084
 * affected systems.
8085
 */
2342 Serge 8086
static void quirk_pipea_force(struct drm_device *dev)
2327 Serge 8087
{
8088
    struct drm_i915_private *dev_priv = dev->dev_private;
8089
 
8090
    dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8091
    DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8092
}
8093
 
8094
/*
8095
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8096
 */
8097
static void quirk_ssc_force_disable(struct drm_device *dev)
8098
{
8099
    struct drm_i915_private *dev_priv = dev->dev_private;
8100
    dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8101
}
8102
 
8103
struct intel_quirk {
8104
    int device;
8105
    int subsystem_vendor;
8106
    int subsystem_device;
8107
    void (*hook)(struct drm_device *dev);
8108
};
8109
 
8110
struct intel_quirk intel_quirks[] = {
8111
    /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8112
    { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8113
    /* HP Mini needs pipe A force quirk (LP: #322104) */
2342 Serge 8114
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
2327 Serge 8115
 
8116
    /* Thinkpad R31 needs pipe A force quirk */
8117
    { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8118
    /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8119
    { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8120
 
8121
    /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8122
    { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8123
    /* ThinkPad X40 needs pipe A force quirk */
8124
 
8125
    /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8126
    { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8127
 
8128
    /* 855 & before need to leave pipe A & dpll A up */
8129
    { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8130
    { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8131
 
8132
    /* Lenovo U160 cannot use SSC on LVDS */
8133
    { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8134
 
8135
    /* Sony Vaio Y cannot use SSC on LVDS */
8136
    { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8137
};
8138
 
8139
static void intel_init_quirks(struct drm_device *dev)
8140
{
8141
    struct pci_dev *d = dev->pdev;
8142
    int i;
8143
 
8144
    for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8145
        struct intel_quirk *q = &intel_quirks[i];
8146
 
8147
        if (d->device == q->device &&
8148
            (d->subsystem_vendor == q->subsystem_vendor ||
8149
             q->subsystem_vendor == PCI_ANY_ID) &&
8150
            (d->subsystem_device == q->subsystem_device ||
8151
             q->subsystem_device == PCI_ANY_ID))
8152
            q->hook(dev);
8153
    }
8154
}
8155
 
2330 Serge 8156
/* Disable the VGA plane that we never use */
8157
static void i915_disable_vga(struct drm_device *dev)
8158
{
8159
	struct drm_i915_private *dev_priv = dev->dev_private;
8160
	u8 sr1;
8161
	u32 vga_reg;
2327 Serge 8162
 
2330 Serge 8163
	if (HAS_PCH_SPLIT(dev))
8164
		vga_reg = CPU_VGACNTRL;
8165
	else
8166
		vga_reg = VGACNTRL;
8167
 
8168
//	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8169
    out8(VGA_SR_INDEX, 1);
8170
    sr1 = in8(VGA_SR_DATA);
8171
    out8(VGA_SR_DATA,sr1 | 1<<5);
8172
//   vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8173
	udelay(300);
8174
 
8175
	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8176
	POSTING_READ(vga_reg);
8177
}
8178
 
2327 Serge 8179
void intel_modeset_init(struct drm_device *dev)
8180
{
8181
    struct drm_i915_private *dev_priv = dev->dev_private;
2342 Serge 8182
	int i, ret;
2327 Serge 8183
 
8184
    drm_mode_config_init(dev);
8185
 
8186
    dev->mode_config.min_width = 0;
8187
    dev->mode_config.min_height = 0;
8188
 
8189
    dev->mode_config.funcs = (void *)&intel_mode_funcs;
8190
 
8191
    intel_init_quirks(dev);
8192
 
8193
    intel_init_display(dev);
8194
 
8195
    if (IS_GEN2(dev)) {
8196
        dev->mode_config.max_width = 2048;
8197
        dev->mode_config.max_height = 2048;
8198
    } else if (IS_GEN3(dev)) {
8199
        dev->mode_config.max_width = 4096;
8200
        dev->mode_config.max_height = 4096;
8201
    } else {
8202
        dev->mode_config.max_width = 8192;
8203
        dev->mode_config.max_height = 8192;
8204
    }
8205
    dev->mode_config.fb_base = get_bus_addr();
8206
 
8207
    DRM_DEBUG_KMS("%d display pipe%s available.\n",
8208
              dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8209
 
8210
    for (i = 0; i < dev_priv->num_pipe; i++) {
8211
        intel_crtc_init(dev, i);
2342 Serge 8212
		ret = intel_plane_init(dev, i);
8213
		if (ret)
8214
			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
2327 Serge 8215
    }
8216
 
8217
    /* Just disable it once at startup */
8218
    i915_disable_vga(dev);
8219
    intel_setup_outputs(dev);
8220
 
8221
    intel_init_clock_gating(dev);
8222
 
8223
    if (IS_IRONLAKE_M(dev)) {
8224
        ironlake_enable_drps(dev);
8225
        intel_init_emon(dev);
8226
    }
8227
 
8228
    if (IS_GEN6(dev) || IS_GEN7(dev)) {
8229
        gen6_enable_rps(dev_priv);
8230
        gen6_update_ring_freq(dev_priv);
8231
    }
8232
 
2332 Serge 8233
//   INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8234
//   setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8235
//           (unsigned long)dev);
2330 Serge 8236
}
2327 Serge 8237
 
2332 Serge 8238
void intel_modeset_gem_init(struct drm_device *dev)
8239
{
8240
	if (IS_IRONLAKE_M(dev))
8241
		ironlake_enable_rc6(dev);
2330 Serge 8242
 
2332 Serge 8243
//	intel_setup_overlay(dev);
8244
}
8245
 
8246
 
2330 Serge 8247
/*
8248
 * Return which encoder is currently attached for connector.
8249
 */
8250
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8251
{
8252
	return &intel_attached_encoder(connector)->base;
2327 Serge 8253
}
8254
 
2330 Serge 8255
void intel_connector_attach_encoder(struct intel_connector *connector,
8256
				    struct intel_encoder *encoder)
8257
{
8258
	connector->encoder = encoder;
8259
	drm_mode_connector_attach_encoder(&connector->base,
8260
					  &encoder->base);
8261
}
2327 Serge 8262
 
2330 Serge 8263