WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_display.c

Rev	Author	Line No.	Line
2327	Serge	1	/*
		2	* Copyright © 2006-2007 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		21	* DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eric Anholt
		25	*/
		26
		27	//#include
		28	#include
		29	//#include
		30	#include
		31	#include
2330	Serge	32	#include
2327	Serge	33	//#include
		34	#include "drmP.h"
		35	#include "intel_drv.h"
2330	Serge	36	#include "i915_drm.h"
2327	Serge	37	#include "i915_drv.h"
		38	//#include "i915_trace.h"
		39	#include "drm_dp_helper.h"
		40
		41	#include "drm_crtc_helper.h"
		42
		43	phys_addr_t get_bus_addr(void);
		44
		45	static inline __attribute__((const))
		46	bool is_power_of_2(unsigned long n)
		47	{
		48	return (n != 0 && ((n & (n - 1)) == 0));
		49	}
		50
2330	Serge	51	#define MAX_ERRNO 4095
		52
		53	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
		54
		55	static inline long IS_ERR(const void *ptr)
		56	{
		57	return IS_ERR_VALUE((unsigned long)ptr);
		58	}
		59
		60	static inline void *ERR_PTR(long error)
		61	{
		62	return (void *) error;
		63	}
		64
		65
2327	Serge	66	static inline int pci_read_config_word(struct pci_dev *dev, int where,
		67	u16 *val)
		68	{
		69	*val = PciRead16(dev->busnr, dev->devfn, where);
		70	return 1;
		71	}
		72
		73
		74	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
		75
		76	bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
		77	static void intel_update_watermarks(struct drm_device *dev);
		78	static void intel_increase_pllclock(struct drm_crtc *crtc);
		79	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
		80
		81	typedef struct {
		82	/* given values */
		83	int n;
		84	int m1, m2;
		85	int p1, p2;
		86	/* derived values */
		87	int dot;
		88	int vco;
		89	int m;
		90	int p;
		91	} intel_clock_t;
		92
		93	typedef struct {
		94	int min, max;
		95	} intel_range_t;
		96
		97	typedef struct {
		98	int dot_limit;
		99	int p2_slow, p2_fast;
		100	} intel_p2_t;
		101
		102	#define INTEL_P2_NUM 2
		103	typedef struct intel_limit intel_limit_t;
		104	struct intel_limit {
		105	intel_range_t dot, vco, n, m, m1, m2, p, p1;
		106	intel_p2_t p2;
		107	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,
		108	int, int, intel_clock_t *);
		109	};
		110
		111	/* FDI */
		112	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
		113
		114	static bool
		115	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		116	int target, int refclk, intel_clock_t *best_clock);
		117	static bool
		118	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		119	int target, int refclk, intel_clock_t *best_clock);
		120
		121	static bool
		122	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
		123	int target, int refclk, intel_clock_t *best_clock);
		124	static bool
		125	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
		126	int target, int refclk, intel_clock_t *best_clock);
		127
		128	static inline u32 /* units of 100MHz */
		129	intel_fdi_link_freq(struct drm_device *dev)
		130	{
		131	if (IS_GEN5(dev)) {
		132	struct drm_i915_private *dev_priv = dev->dev_private;
		133	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
		134	} else
		135	return 27;
		136	}
		137
		138	static const intel_limit_t intel_limits_i8xx_dvo = {
		139	.dot = { .min = 25000, .max = 350000 },
		140	.vco = { .min = 930000, .max = 1400000 },
		141	.n = { .min = 3, .max = 16 },
		142	.m = { .min = 96, .max = 140 },
		143	.m1 = { .min = 18, .max = 26 },
		144	.m2 = { .min = 6, .max = 16 },
		145	.p = { .min = 4, .max = 128 },
		146	.p1 = { .min = 2, .max = 33 },
		147	.p2 = { .dot_limit = 165000,
		148	.p2_slow = 4, .p2_fast = 2 },
		149	.find_pll = intel_find_best_PLL,
		150	};
		151
		152	static const intel_limit_t intel_limits_i8xx_lvds = {
		153	.dot = { .min = 25000, .max = 350000 },
		154	.vco = { .min = 930000, .max = 1400000 },
		155	.n = { .min = 3, .max = 16 },
		156	.m = { .min = 96, .max = 140 },
		157	.m1 = { .min = 18, .max = 26 },
		158	.m2 = { .min = 6, .max = 16 },
		159	.p = { .min = 4, .max = 128 },
		160	.p1 = { .min = 1, .max = 6 },
		161	.p2 = { .dot_limit = 165000,
		162	.p2_slow = 14, .p2_fast = 7 },
		163	.find_pll = intel_find_best_PLL,
		164	};
		165
		166	static const intel_limit_t intel_limits_i9xx_sdvo = {
		167	.dot = { .min = 20000, .max = 400000 },
		168	.vco = { .min = 1400000, .max = 2800000 },
		169	.n = { .min = 1, .max = 6 },
		170	.m = { .min = 70, .max = 120 },
		171	.m1 = { .min = 10, .max = 22 },
		172	.m2 = { .min = 5, .max = 9 },
		173	.p = { .min = 5, .max = 80 },
		174	.p1 = { .min = 1, .max = 8 },
		175	.p2 = { .dot_limit = 200000,
		176	.p2_slow = 10, .p2_fast = 5 },
		177	.find_pll = intel_find_best_PLL,
		178	};
		179
		180	static const intel_limit_t intel_limits_i9xx_lvds = {
		181	.dot = { .min = 20000, .max = 400000 },
		182	.vco = { .min = 1400000, .max = 2800000 },
		183	.n = { .min = 1, .max = 6 },
		184	.m = { .min = 70, .max = 120 },
		185	.m1 = { .min = 10, .max = 22 },
		186	.m2 = { .min = 5, .max = 9 },
		187	.p = { .min = 7, .max = 98 },
		188	.p1 = { .min = 1, .max = 8 },
		189	.p2 = { .dot_limit = 112000,
		190	.p2_slow = 14, .p2_fast = 7 },
		191	.find_pll = intel_find_best_PLL,
		192	};
		193
		194
		195	static const intel_limit_t intel_limits_g4x_sdvo = {
		196	.dot = { .min = 25000, .max = 270000 },
		197	.vco = { .min = 1750000, .max = 3500000},
		198	.n = { .min = 1, .max = 4 },
		199	.m = { .min = 104, .max = 138 },
		200	.m1 = { .min = 17, .max = 23 },
		201	.m2 = { .min = 5, .max = 11 },
		202	.p = { .min = 10, .max = 30 },
		203	.p1 = { .min = 1, .max = 3},
		204	.p2 = { .dot_limit = 270000,
		205	.p2_slow = 10,
		206	.p2_fast = 10
		207	},
		208	.find_pll = intel_g4x_find_best_PLL,
		209	};
		210
		211	static const intel_limit_t intel_limits_g4x_hdmi = {
		212	.dot = { .min = 22000, .max = 400000 },
		213	.vco = { .min = 1750000, .max = 3500000},
		214	.n = { .min = 1, .max = 4 },
		215	.m = { .min = 104, .max = 138 },
		216	.m1 = { .min = 16, .max = 23 },
		217	.m2 = { .min = 5, .max = 11 },
		218	.p = { .min = 5, .max = 80 },
		219	.p1 = { .min = 1, .max = 8},
		220	.p2 = { .dot_limit = 165000,
		221	.p2_slow = 10, .p2_fast = 5 },
		222	.find_pll = intel_g4x_find_best_PLL,
		223	};
		224
		225	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
		226	.dot = { .min = 20000, .max = 115000 },
		227	.vco = { .min = 1750000, .max = 3500000 },
		228	.n = { .min = 1, .max = 3 },
		229	.m = { .min = 104, .max = 138 },
		230	.m1 = { .min = 17, .max = 23 },
		231	.m2 = { .min = 5, .max = 11 },
		232	.p = { .min = 28, .max = 112 },
		233	.p1 = { .min = 2, .max = 8 },
		234	.p2 = { .dot_limit = 0,
		235	.p2_slow = 14, .p2_fast = 14
		236	},
		237	.find_pll = intel_g4x_find_best_PLL,
		238	};
		239
		240	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
		241	.dot = { .min = 80000, .max = 224000 },
		242	.vco = { .min = 1750000, .max = 3500000 },
		243	.n = { .min = 1, .max = 3 },
		244	.m = { .min = 104, .max = 138 },
		245	.m1 = { .min = 17, .max = 23 },
		246	.m2 = { .min = 5, .max = 11 },
		247	.p = { .min = 14, .max = 42 },
		248	.p1 = { .min = 2, .max = 6 },
		249	.p2 = { .dot_limit = 0,
		250	.p2_slow = 7, .p2_fast = 7
		251	},
		252	.find_pll = intel_g4x_find_best_PLL,
		253	};
		254
		255	static const intel_limit_t intel_limits_g4x_display_port = {
		256	.dot = { .min = 161670, .max = 227000 },
		257	.vco = { .min = 1750000, .max = 3500000},
		258	.n = { .min = 1, .max = 2 },
		259	.m = { .min = 97, .max = 108 },
		260	.m1 = { .min = 0x10, .max = 0x12 },
		261	.m2 = { .min = 0x05, .max = 0x06 },
		262	.p = { .min = 10, .max = 20 },
		263	.p1 = { .min = 1, .max = 2},
		264	.p2 = { .dot_limit = 0,
		265	.p2_slow = 10, .p2_fast = 10 },
		266	.find_pll = intel_find_pll_g4x_dp,
		267	};
		268
		269	static const intel_limit_t intel_limits_pineview_sdvo = {
		270	.dot = { .min = 20000, .max = 400000},
		271	.vco = { .min = 1700000, .max = 3500000 },
		272	/* Pineview's Ncounter is a ring counter */
		273	.n = { .min = 3, .max = 6 },
		274	.m = { .min = 2, .max = 256 },
		275	/* Pineview only has one combined m divider, which we treat as m2. */
		276	.m1 = { .min = 0, .max = 0 },
		277	.m2 = { .min = 0, .max = 254 },
		278	.p = { .min = 5, .max = 80 },
		279	.p1 = { .min = 1, .max = 8 },
		280	.p2 = { .dot_limit = 200000,
		281	.p2_slow = 10, .p2_fast = 5 },
		282	.find_pll = intel_find_best_PLL,
		283	};
		284
		285	static const intel_limit_t intel_limits_pineview_lvds = {
		286	.dot = { .min = 20000, .max = 400000 },
		287	.vco = { .min = 1700000, .max = 3500000 },
		288	.n = { .min = 3, .max = 6 },
		289	.m = { .min = 2, .max = 256 },
		290	.m1 = { .min = 0, .max = 0 },
		291	.m2 = { .min = 0, .max = 254 },
		292	.p = { .min = 7, .max = 112 },
		293	.p1 = { .min = 1, .max = 8 },
		294	.p2 = { .dot_limit = 112000,
		295	.p2_slow = 14, .p2_fast = 14 },
		296	.find_pll = intel_find_best_PLL,
		297	};
		298
		299	/* Ironlake / Sandybridge
		300	*
		301	* We calculate clock using (register_value + 2) for N/M1/M2, so here
		302	* the range value for them is (actual_value - 2).
		303	*/
		304	static const intel_limit_t intel_limits_ironlake_dac = {
		305	.dot = { .min = 25000, .max = 350000 },
		306	.vco = { .min = 1760000, .max = 3510000 },
		307	.n = { .min = 1, .max = 5 },
		308	.m = { .min = 79, .max = 127 },
		309	.m1 = { .min = 12, .max = 22 },
		310	.m2 = { .min = 5, .max = 9 },
		311	.p = { .min = 5, .max = 80 },
		312	.p1 = { .min = 1, .max = 8 },
		313	.p2 = { .dot_limit = 225000,
		314	.p2_slow = 10, .p2_fast = 5 },
		315	.find_pll = intel_g4x_find_best_PLL,
		316	};
		317
		318	static const intel_limit_t intel_limits_ironlake_single_lvds = {
		319	.dot = { .min = 25000, .max = 350000 },
		320	.vco = { .min = 1760000, .max = 3510000 },
		321	.n = { .min = 1, .max = 3 },
		322	.m = { .min = 79, .max = 118 },
		323	.m1 = { .min = 12, .max = 22 },
		324	.m2 = { .min = 5, .max = 9 },
		325	.p = { .min = 28, .max = 112 },
		326	.p1 = { .min = 2, .max = 8 },
		327	.p2 = { .dot_limit = 225000,
		328	.p2_slow = 14, .p2_fast = 14 },
		329	.find_pll = intel_g4x_find_best_PLL,
		330	};
		331
		332	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
		333	.dot = { .min = 25000, .max = 350000 },
		334	.vco = { .min = 1760000, .max = 3510000 },
		335	.n = { .min = 1, .max = 3 },
		336	.m = { .min = 79, .max = 127 },
		337	.m1 = { .min = 12, .max = 22 },
		338	.m2 = { .min = 5, .max = 9 },
		339	.p = { .min = 14, .max = 56 },
		340	.p1 = { .min = 2, .max = 8 },
		341	.p2 = { .dot_limit = 225000,
		342	.p2_slow = 7, .p2_fast = 7 },
		343	.find_pll = intel_g4x_find_best_PLL,
		344	};
		345
		346	/* LVDS 100mhz refclk limits. */
		347	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
		348	.dot = { .min = 25000, .max = 350000 },
		349	.vco = { .min = 1760000, .max = 3510000 },
		350	.n = { .min = 1, .max = 2 },
		351	.m = { .min = 79, .max = 126 },
		352	.m1 = { .min = 12, .max = 22 },
		353	.m2 = { .min = 5, .max = 9 },
		354	.p = { .min = 28, .max = 112 },
		355	.p1 = { .min = 2,.max = 8 },
		356	.p2 = { .dot_limit = 225000,
		357	.p2_slow = 14, .p2_fast = 14 },
		358	.find_pll = intel_g4x_find_best_PLL,
		359	};
		360
		361	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
		362	.dot = { .min = 25000, .max = 350000 },
		363	.vco = { .min = 1760000, .max = 3510000 },
		364	.n = { .min = 1, .max = 3 },
		365	.m = { .min = 79, .max = 126 },
		366	.m1 = { .min = 12, .max = 22 },
		367	.m2 = { .min = 5, .max = 9 },
		368	.p = { .min = 14, .max = 42 },
		369	.p1 = { .min = 2,.max = 6 },
		370	.p2 = { .dot_limit = 225000,
		371	.p2_slow = 7, .p2_fast = 7 },
		372	.find_pll = intel_g4x_find_best_PLL,
		373	};
		374
		375	static const intel_limit_t intel_limits_ironlake_display_port = {
		376	.dot = { .min = 25000, .max = 350000 },
		377	.vco = { .min = 1760000, .max = 3510000},
		378	.n = { .min = 1, .max = 2 },
		379	.m = { .min = 81, .max = 90 },
		380	.m1 = { .min = 12, .max = 22 },
		381	.m2 = { .min = 5, .max = 9 },
		382	.p = { .min = 10, .max = 20 },
		383	.p1 = { .min = 1, .max = 2},
		384	.p2 = { .dot_limit = 0,
		385	.p2_slow = 10, .p2_fast = 10 },
		386	.find_pll = intel_find_pll_ironlake_dp,
		387	};
		388
		389	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
		390	int refclk)
		391	{
		392	struct drm_device *dev = crtc->dev;
		393	struct drm_i915_private *dev_priv = dev->dev_private;
		394	const intel_limit_t *limit;
		395
		396	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		397	if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
		398	LVDS_CLKB_POWER_UP) {
		399	/* LVDS dual channel */
		400	if (refclk == 100000)
		401	limit = &intel_limits_ironlake_dual_lvds_100m;
		402	else
		403	limit = &intel_limits_ironlake_dual_lvds;
		404	} else {
		405	if (refclk == 100000)
		406	limit = &intel_limits_ironlake_single_lvds_100m;
		407	else
		408	limit = &intel_limits_ironlake_single_lvds;
		409	}
		410	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
		411	HAS_eDP)
		412	limit = &intel_limits_ironlake_display_port;
		413	else
		414	limit = &intel_limits_ironlake_dac;
		415
		416	return limit;
		417	}
		418
		419	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
		420	{
		421	struct drm_device *dev = crtc->dev;
		422	struct drm_i915_private *dev_priv = dev->dev_private;
		423	const intel_limit_t *limit;
		424
		425	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		426	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		427	LVDS_CLKB_POWER_UP)
		428	/* LVDS with dual channel */
		429	limit = &intel_limits_g4x_dual_channel_lvds;
		430	else
		431	/* LVDS with dual channel */
		432	limit = &intel_limits_g4x_single_channel_lvds;
		433	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
		434	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		435	limit = &intel_limits_g4x_hdmi;
		436	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		437	limit = &intel_limits_g4x_sdvo;
		438	} else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		439	limit = &intel_limits_g4x_display_port;
		440	} else /* The option is for other outputs */
		441	limit = &intel_limits_i9xx_sdvo;
		442
		443	return limit;
		444	}
		445
		446	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
		447	{
		448	struct drm_device *dev = crtc->dev;
		449	const intel_limit_t *limit;
		450
		451	if (HAS_PCH_SPLIT(dev))
		452	limit = intel_ironlake_limit(crtc, refclk);
		453	else if (IS_G4X(dev)) {
		454	limit = intel_g4x_limit(crtc);
		455	} else if (IS_PINEVIEW(dev)) {
		456	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		457	limit = &intel_limits_pineview_lvds;
		458	else
		459	limit = &intel_limits_pineview_sdvo;
		460	} else if (!IS_GEN2(dev)) {
		461	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		462	limit = &intel_limits_i9xx_lvds;
		463	else
		464	limit = &intel_limits_i9xx_sdvo;
		465	} else {
		466	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		467	limit = &intel_limits_i8xx_lvds;
		468	else
		469	limit = &intel_limits_i8xx_dvo;
		470	}
		471	return limit;
		472	}
		473
		474	/* m1 is reserved as 0 in Pineview, n is a ring counter */
		475	static void pineview_clock(int refclk, intel_clock_t *clock)
		476	{
		477	clock->m = clock->m2 + 2;
		478	clock->p = clock->p1 * clock->p2;
		479	clock->vco = refclk * clock->m / clock->n;
		480	clock->dot = clock->vco / clock->p;
		481	}
		482
		483	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
		484	{
		485	if (IS_PINEVIEW(dev)) {
		486	pineview_clock(refclk, clock);
		487	return;
		488	}
		489	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
		490	clock->p = clock->p1 * clock->p2;
		491	clock->vco = refclk * clock->m / (clock->n + 2);
		492	clock->dot = clock->vco / clock->p;
		493	}
		494
		495	/**
		496	* Returns whether any output on the specified pipe is of the specified type
		497	*/
		498	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
		499	{
		500	struct drm_device *dev = crtc->dev;
		501	struct drm_mode_config *mode_config = &dev->mode_config;
		502	struct intel_encoder *encoder;
		503
		504	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		505	if (encoder->base.crtc == crtc && encoder->type == type)
		506	return true;
		507
		508	return false;
		509	}
		510
		511	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
		512	/**
		513	* Returns whether the given set of divisors are valid for a given refclk with
		514	* the given connectors.
		515	*/
		516
		517	static bool intel_PLL_is_valid(struct drm_device *dev,
		518	const intel_limit_t *limit,
		519	const intel_clock_t *clock)
		520	{
		521	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
		522	INTELPllInvalid ("p1 out of range\n");
		523	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
		524	INTELPllInvalid ("p out of range\n");
		525	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
		526	INTELPllInvalid ("m2 out of range\n");
		527	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
		528	INTELPllInvalid ("m1 out of range\n");
		529	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
		530	INTELPllInvalid ("m1 <= m2\n");
		531	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
		532	INTELPllInvalid ("m out of range\n");
		533	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
		534	INTELPllInvalid ("n out of range\n");
		535	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
		536	INTELPllInvalid ("vco out of range\n");
		537	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
		538	* connector, etc., rather than just a single range.
		539	*/
		540	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
		541	INTELPllInvalid ("dot out of range\n");
		542
		543	return true;
		544	}
		545
		546	static bool
		547	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		548	int target, int refclk, intel_clock_t *best_clock)
		549
		550	{
		551	struct drm_device *dev = crtc->dev;
		552	struct drm_i915_private *dev_priv = dev->dev_private;
		553	intel_clock_t clock;
		554	int err = target;
		555
		556	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		557	(I915_READ(LVDS)) != 0) {
		558	/*
		559	* For LVDS, if the panel is on, just rely on its current
		560	* settings for dual-channel. We haven't figured out how to
		561	* reliably set up different single/dual channel state, if we
		562	* even can.
		563	*/
		564	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		565	LVDS_CLKB_POWER_UP)
		566	clock.p2 = limit->p2.p2_fast;
		567	else
		568	clock.p2 = limit->p2.p2_slow;
		569	} else {
		570	if (target < limit->p2.dot_limit)
		571	clock.p2 = limit->p2.p2_slow;
		572	else
		573	clock.p2 = limit->p2.p2_fast;
		574	}
		575
		576	memset (best_clock, 0, sizeof (*best_clock));
		577
		578	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
		579	clock.m1++) {
		580	for (clock.m2 = limit->m2.min;
		581	clock.m2 <= limit->m2.max; clock.m2++) {
		582	/* m1 is always 0 in Pineview */
		583	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
		584	break;
		585	for (clock.n = limit->n.min;
		586	clock.n <= limit->n.max; clock.n++) {
		587	for (clock.p1 = limit->p1.min;
		588	clock.p1 <= limit->p1.max; clock.p1++) {
		589	int this_err;
		590
		591	intel_clock(dev, refclk, &clock);
		592	if (!intel_PLL_is_valid(dev, limit,
		593	&clock))
		594	continue;
		595
		596	this_err = abs(clock.dot - target);
		597	if (this_err < err) {
		598	*best_clock = clock;
		599	err = this_err;
		600	}
		601	}
		602	}
		603	}
		604	}
		605
		606	return (err != target);
		607	}
		608
		609	static bool
		610	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
		611	int target, int refclk, intel_clock_t *best_clock)
		612	{
		613	struct drm_device *dev = crtc->dev;
		614	struct drm_i915_private *dev_priv = dev->dev_private;
		615	intel_clock_t clock;
		616	int max_n;
		617	bool found;
		618	/* approximately equals target * 0.00585 */
		619	int err_most = (target >> 8) + (target >> 9);
		620	found = false;
		621
		622	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		623	int lvds_reg;
		624
		625	if (HAS_PCH_SPLIT(dev))
		626	lvds_reg = PCH_LVDS;
		627	else
		628	lvds_reg = LVDS;
		629	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		630	LVDS_CLKB_POWER_UP)
		631	clock.p2 = limit->p2.p2_fast;
		632	else
		633	clock.p2 = limit->p2.p2_slow;
		634	} else {
		635	if (target < limit->p2.dot_limit)
		636	clock.p2 = limit->p2.p2_slow;
		637	else
		638	clock.p2 = limit->p2.p2_fast;
		639	}
		640
		641	memset(best_clock, 0, sizeof(*best_clock));
		642	max_n = limit->n.max;
		643	/* based on hardware requirement, prefer smaller n to precision */
		644	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		645	/* based on hardware requirement, prefere larger m1,m2 */
		646	for (clock.m1 = limit->m1.max;
		647	clock.m1 >= limit->m1.min; clock.m1--) {
		648	for (clock.m2 = limit->m2.max;
		649	clock.m2 >= limit->m2.min; clock.m2--) {
		650	for (clock.p1 = limit->p1.max;
		651	clock.p1 >= limit->p1.min; clock.p1--) {
		652	int this_err;
		653
		654	intel_clock(dev, refclk, &clock);
		655	if (!intel_PLL_is_valid(dev, limit,
		656	&clock))
		657	continue;
		658
		659	this_err = abs(clock.dot - target);
		660	if (this_err < err_most) {
		661	*best_clock = clock;
		662	err_most = this_err;
		663	max_n = clock.n;
		664	found = true;
		665	}
		666	}
		667	}
		668	}
		669	}
		670	return found;
		671	}
		672
		673	static bool
		674	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
		675	int target, int refclk, intel_clock_t *best_clock)
		676	{
		677	struct drm_device *dev = crtc->dev;
		678	intel_clock_t clock;
		679
		680	if (target < 200000) {
		681	clock.n = 1;
		682	clock.p1 = 2;
		683	clock.p2 = 10;
		684	clock.m1 = 12;
		685	clock.m2 = 9;
		686	} else {
		687	clock.n = 2;
		688	clock.p1 = 1;
		689	clock.p2 = 10;
		690	clock.m1 = 14;
		691	clock.m2 = 8;
		692	}
		693	intel_clock(dev, refclk, &clock);
		694	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		695	return true;
		696	}
		697
		698	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
		699	static bool
		700	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
		701	int target, int refclk, intel_clock_t *best_clock)
		702	{
		703	intel_clock_t clock;
		704	if (target < 200000) {
		705	clock.p1 = 2;
		706	clock.p2 = 10;
		707	clock.n = 2;
		708	clock.m1 = 23;
		709	clock.m2 = 8;
		710	} else {
		711	clock.p1 = 1;
		712	clock.p2 = 10;
		713	clock.n = 1;
		714	clock.m1 = 14;
		715	clock.m2 = 2;
		716	}
		717	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
		718	clock.p = (clock.p1 * clock.p2);
		719	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
		720	clock.vco = 0;
		721	memcpy(best_clock, &clock, sizeof(intel_clock_t));
		722	return true;
		723	}
		724
		725	/**
		726	* intel_wait_for_vblank - wait for vblank on a given pipe
		727	* @dev: drm device
		728	* @pipe: pipe to wait for
		729	*
		730	* Wait for vblank to occur on a given pipe. Needed for various bits of
		731	* mode setting code.
		732	*/
		733	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
		734	{
		735	struct drm_i915_private *dev_priv = dev->dev_private;
		736	int pipestat_reg = PIPESTAT(pipe);
		737
		738	/* Clear existing vblank status. Note this will clear any other
		739	* sticky status fields as well.
		740	*
		741	* This races with i915_driver_irq_handler() with the result
		742	* that either function could miss a vblank event. Here it is not
		743	* fatal, as we will either wait upon the next vblank interrupt or
		744	* timeout. Generally speaking intel_wait_for_vblank() is only
		745	* called during modeset at which time the GPU should be idle and
		746	* should not be performing page flips and thus not waiting on
		747	* vblanks...
		748	* Currently, the result of us stealing a vblank from the irq
		749	* handler is that a single frame will be skipped during swapbuffers.
		750	*/
		751	I915_WRITE(pipestat_reg,
		752	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
		753
		754	/* Wait for vblank interrupt bit to set */
		755	if (wait_for(I915_READ(pipestat_reg) &
		756	PIPE_VBLANK_INTERRUPT_STATUS,
		757	50))
		758	DRM_DEBUG_KMS("vblank wait timed out\n");
		759	}
		760
		761	/*
		762	* intel_wait_for_pipe_off - wait for pipe to turn off
		763	* @dev: drm device
		764	* @pipe: pipe to wait for
		765	*
		766	* After disabling a pipe, we can't wait for vblank in the usual way,
		767	* spinning on the vblank interrupt status bit, since we won't actually
		768	* see an interrupt when the pipe is disabled.
		769	*
		770	* On Gen4 and above:
		771	* wait for the pipe register state bit to turn off
		772	*
		773	* Otherwise:
		774	* wait for the display line value to settle (it usually
		775	* ends up stopping at the start of the next frame).
		776	*
		777	*/
		778	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
		779	{
		780	struct drm_i915_private *dev_priv = dev->dev_private;
		781
		782	if (INTEL_INFO(dev)->gen >= 4) {
		783	int reg = PIPECONF(pipe);
		784
		785	/* Wait for the Pipe State to go off */
		786	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
		787	100))
		788	DRM_DEBUG_KMS("pipe_off wait timed out\n");
		789	} else {
		790	u32 last_line;
		791	int reg = PIPEDSL(pipe);
		792	unsigned long timeout = jiffies + msecs_to_jiffies(100);
		793
		794	/* Wait for the display line to settle */
		795	do {
		796	last_line = I915_READ(reg) & DSL_LINEMASK;
		797	mdelay(5);
		798	} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
		799	time_after(timeout, jiffies));
		800	if (time_after(jiffies, timeout))
		801	DRM_DEBUG_KMS("pipe_off wait timed out\n");
		802	}
		803	}
		804
		805	static const char *state_string(bool enabled)
		806	{
		807	return enabled ? "on" : "off";
		808	}
		809
		810	/* Only for pre-ILK configs */
		811	static void assert_pll(struct drm_i915_private *dev_priv,
		812	enum pipe pipe, bool state)
		813	{
		814	int reg;
		815	u32 val;
		816	bool cur_state;
		817
		818	reg = DPLL(pipe);
		819	val = I915_READ(reg);
		820	cur_state = !!(val & DPLL_VCO_ENABLE);
		821	WARN(cur_state != state,
		822	"PLL state assertion failure (expected %s, current %s)\n",
		823	state_string(state), state_string(cur_state));
		824	}
		825	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
		826	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
		827
		828	/* For ILK+ */
		829	static void assert_pch_pll(struct drm_i915_private *dev_priv,
		830	enum pipe pipe, bool state)
		831	{
		832	int reg;
		833	u32 val;
		834	bool cur_state;
		835
		836	reg = PCH_DPLL(pipe);
		837	val = I915_READ(reg);
		838	cur_state = !!(val & DPLL_VCO_ENABLE);
		839	WARN(cur_state != state,
		840	"PCH PLL state assertion failure (expected %s, current %s)\n",
		841	state_string(state), state_string(cur_state));
		842	}
		843	#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
		844	#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
		845
		846	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		847	enum pipe pipe, bool state)
		848	{
		849	int reg;
		850	u32 val;
		851	bool cur_state;
		852
		853	reg = FDI_TX_CTL(pipe);
		854	val = I915_READ(reg);
		855	cur_state = !!(val & FDI_TX_ENABLE);
		856	WARN(cur_state != state,
		857	"FDI TX state assertion failure (expected %s, current %s)\n",
		858	state_string(state), state_string(cur_state));
		859	}
		860	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
		861	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
		862
		863	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
		864	enum pipe pipe, bool state)
		865	{
		866	int reg;
		867	u32 val;
		868	bool cur_state;
		869
		870	reg = FDI_RX_CTL(pipe);
		871	val = I915_READ(reg);
		872	cur_state = !!(val & FDI_RX_ENABLE);
		873	WARN(cur_state != state,
		874	"FDI RX state assertion failure (expected %s, current %s)\n",
		875	state_string(state), state_string(cur_state));
		876	}
		877	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
		878	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
		879
		880	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		881	enum pipe pipe)
		882	{
		883	int reg;
		884	u32 val;
		885
		886	/* ILK FDI PLL is always enabled */
		887	if (dev_priv->info->gen == 5)
		888	return;
		889
		890	reg = FDI_TX_CTL(pipe);
		891	val = I915_READ(reg);
		892	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		893	}
		894
		895	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
		896	enum pipe pipe)
		897	{
		898	int reg;
		899	u32 val;
		900
		901	reg = FDI_RX_CTL(pipe);
		902	val = I915_READ(reg);
		903	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
		904	}
		905
		906	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
		907	enum pipe pipe)
		908	{
		909	int pp_reg, lvds_reg;
		910	u32 val;
		911	enum pipe panel_pipe = PIPE_A;
		912	bool locked = true;
		913
		914	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		915	pp_reg = PCH_PP_CONTROL;
		916	lvds_reg = PCH_LVDS;
		917	} else {
		918	pp_reg = PP_CONTROL;
		919	lvds_reg = LVDS;
		920	}
		921
		922	val = I915_READ(pp_reg);
		923	if (!(val & PANEL_POWER_ON) \|\|
		924	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		925	locked = false;
		926
		927	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		928	panel_pipe = PIPE_B;
		929
		930	WARN(panel_pipe == pipe && locked,
		931	"panel assertion failure, pipe %c regs locked\n",
		932	pipe_name(pipe));
		933	}
		934
		935	static void assert_pipe(struct drm_i915_private *dev_priv,
		936	enum pipe pipe, bool state)
		937	{
		938	int reg;
		939	u32 val;
		940	bool cur_state;
		941
		942	reg = PIPECONF(pipe);
		943	val = I915_READ(reg);
		944	cur_state = !!(val & PIPECONF_ENABLE);
		945	WARN(cur_state != state,
		946	"pipe %c assertion failure (expected %s, current %s)\n",
		947	pipe_name(pipe), state_string(state), state_string(cur_state));
		948	}
		949	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
		950	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
		951
		952	static void assert_plane_enabled(struct drm_i915_private *dev_priv,
		953	enum plane plane)
		954	{
		955	int reg;
		956	u32 val;
		957
		958	reg = DSPCNTR(plane);
		959	val = I915_READ(reg);
		960	WARN(!(val & DISPLAY_PLANE_ENABLE),
		961	"plane %c assertion failure, should be active but is disabled\n",
		962	plane_name(plane));
		963	}
		964
		965	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
		966	enum pipe pipe)
		967	{
		968	int reg, i;
		969	u32 val;
		970	int cur_pipe;
		971
		972	/* Planes are fixed to pipes on ILK+ */
		973	if (HAS_PCH_SPLIT(dev_priv->dev))
		974	return;
		975
		976	/* Need to check both planes against the pipe */
		977	for (i = 0; i < 2; i++) {
		978	reg = DSPCNTR(i);
		979	val = I915_READ(reg);
		980	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
		981	DISPPLANE_SEL_PIPE_SHIFT;
		982	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
		983	"plane %c assertion failure, should be off on pipe %c but is still active\n",
		984	plane_name(i), pipe_name(pipe));
		985	}
		986	}
		987
		988	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
		989	{
		990	u32 val;
		991	bool enabled;
		992
		993	val = I915_READ(PCH_DREF_CONTROL);
		994	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
		995	DREF_SUPERSPREAD_SOURCE_MASK));
		996	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
		997	}
		998
		999	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
		1000	enum pipe pipe)
		1001	{
		1002	int reg;
		1003	u32 val;
		1004	bool enabled;
		1005
		1006	reg = TRANSCONF(pipe);
		1007	val = I915_READ(reg);
		1008	enabled = !!(val & TRANS_ENABLE);
		1009	WARN(enabled,
		1010	"transcoder assertion failed, should be off on pipe %c but is still active\n",
		1011	pipe_name(pipe));
		1012	}
		1013
		1014	static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
		1015	enum pipe pipe, u32 port_sel, u32 val)
		1016	{
		1017	if ((val & DP_PORT_EN) == 0)
		1018	return false;
		1019
		1020	if (HAS_PCH_CPT(dev_priv->dev)) {
		1021	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		1022	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		1023	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
		1024	return false;
		1025	} else {
		1026	if ((val & DP_PIPE_MASK) != (pipe << 30))
		1027	return false;
		1028	}
		1029	return true;
		1030	}
		1031
		1032	static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
		1033	enum pipe pipe, u32 val)
		1034	{
		1035	if ((val & PORT_ENABLE) == 0)
		1036	return false;
		1037
		1038	if (HAS_PCH_CPT(dev_priv->dev)) {
		1039	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1040	return false;
		1041	} else {
		1042	if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
		1043	return false;
		1044	}
		1045	return true;
		1046	}
		1047
		1048	static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
		1049	enum pipe pipe, u32 val)
		1050	{
		1051	if ((val & LVDS_PORT_EN) == 0)
		1052	return false;
		1053
		1054	if (HAS_PCH_CPT(dev_priv->dev)) {
		1055	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1056	return false;
		1057	} else {
		1058	if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
		1059	return false;
		1060	}
		1061	return true;
		1062	}
		1063
		1064	static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
		1065	enum pipe pipe, u32 val)
		1066	{
		1067	if ((val & ADPA_DAC_ENABLE) == 0)
		1068	return false;
		1069	if (HAS_PCH_CPT(dev_priv->dev)) {
		1070	if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
		1071	return false;
		1072	} else {
		1073	if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
		1074	return false;
		1075	}
		1076	return true;
		1077	}
		1078
		1079	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
		1080	enum pipe pipe, int reg, u32 port_sel)
		1081	{
		1082	u32 val = I915_READ(reg);
		1083	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
		1084	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1085	reg, pipe_name(pipe));
		1086	}
		1087
		1088	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
		1089	enum pipe pipe, int reg)
		1090	{
		1091	u32 val = I915_READ(reg);
		1092	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
		1093	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
		1094	reg, pipe_name(pipe));
		1095	}
		1096
		1097	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
		1098	enum pipe pipe)
		1099	{
		1100	int reg;
		1101	u32 val;
		1102
		1103	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1104	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1105	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1106
		1107	reg = PCH_ADPA;
		1108	val = I915_READ(reg);
		1109	WARN(adpa_pipe_enabled(dev_priv, val, pipe),
		1110	"PCH VGA enabled on transcoder %c, should be disabled\n",
		1111	pipe_name(pipe));
		1112
		1113	reg = PCH_LVDS;
		1114	val = I915_READ(reg);
		1115	WARN(lvds_pipe_enabled(dev_priv, val, pipe),
		1116	"PCH LVDS enabled on transcoder %c, should be disabled\n",
		1117	pipe_name(pipe));
		1118
		1119	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
		1120	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
		1121	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
		1122	}
		1123
		1124	/**
		1125	* intel_enable_pll - enable a PLL
		1126	* @dev_priv: i915 private structure
		1127	* @pipe: pipe PLL to enable
		1128	*
		1129	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
		1130	* make sure the PLL reg is writable first though, since the panel write
		1131	* protect mechanism may be enabled.
		1132	*
		1133	* Note! This is for pre-ILK only.
		1134	*/
		1135	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1136	{
		1137	int reg;
		1138	u32 val;
		1139
		1140	/* No really, not for ILK+ */
		1141	BUG_ON(dev_priv->info->gen >= 5);
		1142
		1143	/* PLL is protected by panel, make sure we can write it */
		1144	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		1145	assert_panel_unlocked(dev_priv, pipe);
		1146
		1147	reg = DPLL(pipe);
		1148	val = I915_READ(reg);
		1149	val \|= DPLL_VCO_ENABLE;
		1150
		1151	/* We do this three times for luck */
		1152	I915_WRITE(reg, val);
		1153	POSTING_READ(reg);
		1154	udelay(150); /* wait for warmup */
		1155	I915_WRITE(reg, val);
		1156	POSTING_READ(reg);
		1157	udelay(150); /* wait for warmup */
		1158	I915_WRITE(reg, val);
		1159	POSTING_READ(reg);
		1160	udelay(150); /* wait for warmup */
		1161	}
		1162
		1163	/**
		1164	* intel_disable_pll - disable a PLL
		1165	* @dev_priv: i915 private structure
		1166	* @pipe: pipe PLL to disable
		1167	*
		1168	* Disable the PLL for @pipe, making sure the pipe is off first.
		1169	*
		1170	* Note! This is for pre-ILK only.
		1171	*/
		1172	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
		1173	{
		1174	int reg;
		1175	u32 val;
		1176
		1177	/* Don't disable pipe A or pipe A PLLs if needed */
		1178	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1179	return;
		1180
		1181	/* Make sure the pipe isn't still relying on us */
		1182	assert_pipe_disabled(dev_priv, pipe);
		1183
		1184	reg = DPLL(pipe);
		1185	val = I915_READ(reg);
		1186	val &= ~DPLL_VCO_ENABLE;
		1187	I915_WRITE(reg, val);
		1188	POSTING_READ(reg);
		1189	}
		1190
		1191	/**
		1192	* intel_enable_pch_pll - enable PCH PLL
		1193	* @dev_priv: i915 private structure
		1194	* @pipe: pipe PLL to enable
		1195	*
		1196	* The PCH PLL needs to be enabled before the PCH transcoder, since it
		1197	* drives the transcoder clock.
		1198	*/
		1199	static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
		1200	enum pipe pipe)
		1201	{
		1202	int reg;
		1203	u32 val;
		1204
		1205	/* PCH only available on ILK+ */
		1206	BUG_ON(dev_priv->info->gen < 5);
		1207
		1208	/* PCH refclock must be enabled first */
		1209	assert_pch_refclk_enabled(dev_priv);
		1210
		1211	reg = PCH_DPLL(pipe);
		1212	val = I915_READ(reg);
		1213	val \|= DPLL_VCO_ENABLE;
		1214	I915_WRITE(reg, val);
		1215	POSTING_READ(reg);
		1216	udelay(200);
		1217	}
		1218
		1219	static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
		1220	enum pipe pipe)
		1221	{
		1222	int reg;
		1223	u32 val;
		1224
		1225	/* PCH only available on ILK+ */
		1226	BUG_ON(dev_priv->info->gen < 5);
		1227
		1228	/* Make sure transcoder isn't still depending on us */
		1229	assert_transcoder_disabled(dev_priv, pipe);
		1230
		1231	reg = PCH_DPLL(pipe);
		1232	val = I915_READ(reg);
		1233	val &= ~DPLL_VCO_ENABLE;
		1234	I915_WRITE(reg, val);
		1235	POSTING_READ(reg);
		1236	udelay(200);
		1237	}
		1238
		1239	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
		1240	enum pipe pipe)
		1241	{
		1242	int reg;
		1243	u32 val;
		1244
		1245	/* PCH only available on ILK+ */
		1246	BUG_ON(dev_priv->info->gen < 5);
		1247
		1248	/* Make sure PCH DPLL is enabled */
		1249	assert_pch_pll_enabled(dev_priv, pipe);
		1250
		1251	/* FDI must be feeding us bits for PCH ports */
		1252	assert_fdi_tx_enabled(dev_priv, pipe);
		1253	assert_fdi_rx_enabled(dev_priv, pipe);
		1254
		1255	reg = TRANSCONF(pipe);
		1256	val = I915_READ(reg);
		1257
		1258	if (HAS_PCH_IBX(dev_priv->dev)) {
		1259	/*
		1260	* make the BPC in transcoder be consistent with
		1261	* that in pipeconf reg.
		1262	*/
		1263	val &= ~PIPE_BPC_MASK;
		1264	val \|= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
		1265	}
		1266	I915_WRITE(reg, val \| TRANS_ENABLE);
		1267	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		1268	DRM_ERROR("failed to enable transcoder %d\n", pipe);
		1269	}
		1270
		1271	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
		1272	enum pipe pipe)
		1273	{
		1274	int reg;
		1275	u32 val;
		1276
		1277	/* FDI relies on the transcoder */
		1278	assert_fdi_tx_disabled(dev_priv, pipe);
		1279	assert_fdi_rx_disabled(dev_priv, pipe);
		1280
		1281	/* Ports must be off as well */
		1282	assert_pch_ports_disabled(dev_priv, pipe);
		1283
		1284	reg = TRANSCONF(pipe);
		1285	val = I915_READ(reg);
		1286	val &= ~TRANS_ENABLE;
		1287	I915_WRITE(reg, val);
		1288	/* wait for PCH transcoder off, transcoder state */
		1289	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
		1290	DRM_ERROR("failed to disable transcoder\n");
		1291	}
		1292
		1293	/**
		1294	* intel_enable_pipe - enable a pipe, asserting requirements
		1295	* @dev_priv: i915 private structure
		1296	* @pipe: pipe to enable
		1297	* @pch_port: on ILK+, is this pipe driving a PCH port or not
		1298	*
		1299	* Enable @pipe, making sure that various hardware specific requirements
		1300	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
		1301	*
		1302	* @pipe should be %PIPE_A or %PIPE_B.
		1303	*
		1304	* Will wait until the pipe is actually running (i.e. first vblank) before
		1305	* returning.
		1306	*/
		1307	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
		1308	bool pch_port)
		1309	{
		1310	int reg;
		1311	u32 val;
		1312
		1313	/*
		1314	* A pipe without a PLL won't actually be able to drive bits from
		1315	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
		1316	* need the check.
		1317	*/
		1318	if (!HAS_PCH_SPLIT(dev_priv->dev))
		1319	assert_pll_enabled(dev_priv, pipe);
		1320	else {
		1321	if (pch_port) {
		1322	/* if driving the PCH, we need FDI enabled */
		1323	assert_fdi_rx_pll_enabled(dev_priv, pipe);
		1324	assert_fdi_tx_pll_enabled(dev_priv, pipe);
		1325	}
		1326	/* FIXME: assert CPU port conditions for SNB+ */
		1327	}
		1328
		1329	reg = PIPECONF(pipe);
		1330	val = I915_READ(reg);
		1331	if (val & PIPECONF_ENABLE)
		1332	return;
		1333
		1334	I915_WRITE(reg, val \| PIPECONF_ENABLE);
		1335	intel_wait_for_vblank(dev_priv->dev, pipe);
		1336	}
		1337
		1338	/**
		1339	* intel_disable_pipe - disable a pipe, asserting requirements
		1340	* @dev_priv: i915 private structure
		1341	* @pipe: pipe to disable
		1342	*
		1343	* Disable @pipe, making sure that various hardware specific requirements
		1344	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
		1345	*
		1346	* @pipe should be %PIPE_A or %PIPE_B.
		1347	*
		1348	* Will wait until the pipe has shut down before returning.
		1349	*/
		1350	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
		1351	enum pipe pipe)
		1352	{
		1353	int reg;
		1354	u32 val;
		1355
		1356	/*
		1357	* Make sure planes won't keep trying to pump pixels to us,
		1358	* or we might hang the display.
		1359	*/
		1360	assert_planes_disabled(dev_priv, pipe);
		1361
		1362	/* Don't disable pipe A or pipe A PLLs if needed */
		1363	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		1364	return;
		1365
		1366	reg = PIPECONF(pipe);
		1367	val = I915_READ(reg);
		1368	if ((val & PIPECONF_ENABLE) == 0)
		1369	return;
		1370
		1371	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		1372	intel_wait_for_pipe_off(dev_priv->dev, pipe);
		1373	}
		1374
		1375	/*
		1376	* Plane regs are double buffered, going from enabled->disabled needs a
		1377	* trigger in order to latch. The display address reg provides this.
		1378	*/
		1379	static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
		1380	enum plane plane)
		1381	{
		1382	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
		1383	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
		1384	}
		1385
		1386	/**
		1387	* intel_enable_plane - enable a display plane on a given pipe
		1388	* @dev_priv: i915 private structure
		1389	* @plane: plane to enable
		1390	* @pipe: pipe being fed
		1391	*
		1392	* Enable @plane on @pipe, making sure that @pipe is running first.
		1393	*/
		1394	static void intel_enable_plane(struct drm_i915_private *dev_priv,
		1395	enum plane plane, enum pipe pipe)
		1396	{
		1397	int reg;
		1398	u32 val;
		1399
		1400	/* If the pipe isn't enabled, we can't pump pixels and may hang */
		1401	assert_pipe_enabled(dev_priv, pipe);
		1402
		1403	reg = DSPCNTR(plane);
		1404	val = I915_READ(reg);
		1405	if (val & DISPLAY_PLANE_ENABLE)
		1406	return;
		1407
		1408	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
		1409	intel_flush_display_plane(dev_priv, plane);
		1410	intel_wait_for_vblank(dev_priv->dev, pipe);
		1411	}
		1412
		1413	/**
		1414	* intel_disable_plane - disable a display plane
		1415	* @dev_priv: i915 private structure
		1416	* @plane: plane to disable
		1417	* @pipe: pipe consuming the data
		1418	*
		1419	* Disable @plane; should be an independent operation.
		1420	*/
		1421	static void intel_disable_plane(struct drm_i915_private *dev_priv,
		1422	enum plane plane, enum pipe pipe)
		1423	{
		1424	int reg;
		1425	u32 val;
		1426
		1427	reg = DSPCNTR(plane);
		1428	val = I915_READ(reg);
		1429	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		1430	return;
		1431
		1432	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
		1433	intel_flush_display_plane(dev_priv, plane);
		1434	intel_wait_for_vblank(dev_priv->dev, pipe);
		1435	}
		1436
		1437	static void disable_pch_dp(struct drm_i915_private *dev_priv,
		1438	enum pipe pipe, int reg, u32 port_sel)
		1439	{
		1440	u32 val = I915_READ(reg);
		1441	if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
		1442	DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
		1443	I915_WRITE(reg, val & ~DP_PORT_EN);
		1444	}
		1445	}
		1446
		1447	static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
		1448	enum pipe pipe, int reg)
		1449	{
		1450	u32 val = I915_READ(reg);
		1451	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
		1452	DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
		1453	reg, pipe);
		1454	I915_WRITE(reg, val & ~PORT_ENABLE);
		1455	}
		1456	}
		1457
		1458	/* Disable any ports connected to this transcoder */
		1459	static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
		1460	enum pipe pipe)
		1461	{
		1462	u32 reg, val;
		1463
		1464	val = I915_READ(PCH_PP_CONTROL);
		1465	I915_WRITE(PCH_PP_CONTROL, val \| PANEL_UNLOCK_REGS);
		1466
		1467	disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
		1468	disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
		1469	disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
		1470
		1471	reg = PCH_ADPA;
		1472	val = I915_READ(reg);
		1473	if (adpa_pipe_enabled(dev_priv, val, pipe))
		1474	I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
		1475
		1476	reg = PCH_LVDS;
		1477	val = I915_READ(reg);
		1478	if (lvds_pipe_enabled(dev_priv, val, pipe)) {
		1479	DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
		1480	I915_WRITE(reg, val & ~LVDS_PORT_EN);
		1481	POSTING_READ(reg);
		1482	udelay(100);
		1483	}
		1484
		1485	disable_pch_hdmi(dev_priv, pipe, HDMIB);
		1486	disable_pch_hdmi(dev_priv, pipe, HDMIC);
		1487	disable_pch_hdmi(dev_priv, pipe, HDMID);
		1488	}
		1489
		1490	static void i8xx_disable_fbc(struct drm_device *dev)
		1491	{
		1492	struct drm_i915_private *dev_priv = dev->dev_private;
		1493	u32 fbc_ctl;
		1494
		1495	/* Disable compression */
		1496	fbc_ctl = I915_READ(FBC_CONTROL);
		1497	if ((fbc_ctl & FBC_CTL_EN) == 0)
		1498	return;
		1499
		1500	fbc_ctl &= ~FBC_CTL_EN;
		1501	I915_WRITE(FBC_CONTROL, fbc_ctl);
		1502
		1503	/* Wait for compressing bit to clear */
		1504	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
		1505	DRM_DEBUG_KMS("FBC idle timed out\n");
		1506	return;
		1507	}
		1508
		1509	DRM_DEBUG_KMS("disabled FBC\n");
		1510	}
		1511
		1512	static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1513	{
		1514	struct drm_device *dev = crtc->dev;
		1515	struct drm_i915_private *dev_priv = dev->dev_private;
		1516	struct drm_framebuffer *fb = crtc->fb;
		1517	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1518	struct drm_i915_gem_object *obj = intel_fb->obj;
		1519	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1520	int cfb_pitch;
		1521	int plane, i;
		1522	u32 fbc_ctl, fbc_ctl2;
		1523
		1524	cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
		1525	if (fb->pitch < cfb_pitch)
		1526	cfb_pitch = fb->pitch;
		1527
		1528	/* FBC_CTL wants 64B units */
		1529	cfb_pitch = (cfb_pitch / 64) - 1;
		1530	plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
		1531
		1532	/* Clear old tags */
		1533	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		1534	I915_WRITE(FBC_TAG + (i * 4), 0);
		1535
		1536	/* Set it up... */
		1537	fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM \| FBC_CTL_CPU_FENCE;
		1538	fbc_ctl2 \|= plane;
		1539	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
		1540	I915_WRITE(FBC_FENCE_OFF, crtc->y);
		1541
		1542	/* enable it... */
		1543	fbc_ctl = FBC_CTL_EN \| FBC_CTL_PERIODIC;
		1544	if (IS_I945GM(dev))
		1545	fbc_ctl \|= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
		1546	fbc_ctl \|= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
		1547	fbc_ctl \|= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
		1548	fbc_ctl \|= obj->fence_reg;
		1549	I915_WRITE(FBC_CONTROL, fbc_ctl);
		1550
		1551	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
		1552	cfb_pitch, crtc->y, intel_crtc->plane);
		1553	}
		1554
		1555	static bool i8xx_fbc_enabled(struct drm_device *dev)
		1556	{
		1557	struct drm_i915_private *dev_priv = dev->dev_private;
		1558
		1559	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
		1560	}
		1561
		1562	static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1563	{
		1564	struct drm_device *dev = crtc->dev;
		1565	struct drm_i915_private *dev_priv = dev->dev_private;
		1566	struct drm_framebuffer *fb = crtc->fb;
		1567	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1568	struct drm_i915_gem_object *obj = intel_fb->obj;
		1569	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1570	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
		1571	unsigned long stall_watermark = 200;
		1572	u32 dpfc_ctl;
		1573
		1574	dpfc_ctl = plane \| DPFC_SR_EN \| DPFC_CTL_LIMIT_1X;
		1575	dpfc_ctl \|= DPFC_CTL_FENCE_EN \| obj->fence_reg;
		1576	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
		1577
		1578	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
		1579	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
		1580	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
		1581	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
		1582
		1583	/* enable it... */
		1584	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) \| DPFC_CTL_EN);
		1585
		1586	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
		1587	}
		1588
		1589	static void g4x_disable_fbc(struct drm_device *dev)
		1590	{
		1591	struct drm_i915_private *dev_priv = dev->dev_private;
		1592	u32 dpfc_ctl;
		1593
		1594	/* Disable compression */
		1595	dpfc_ctl = I915_READ(DPFC_CONTROL);
		1596	if (dpfc_ctl & DPFC_CTL_EN) {
		1597	dpfc_ctl &= ~DPFC_CTL_EN;
		1598	I915_WRITE(DPFC_CONTROL, dpfc_ctl);
		1599
		1600	DRM_DEBUG_KMS("disabled FBC\n");
		1601	}
		1602	}
		1603
		1604	static bool g4x_fbc_enabled(struct drm_device *dev)
		1605	{
		1606	struct drm_i915_private *dev_priv = dev->dev_private;
		1607
		1608	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
		1609	}
		1610
		1611	static void sandybridge_blit_fbc_update(struct drm_device *dev)
		1612	{
		1613	struct drm_i915_private *dev_priv = dev->dev_private;
		1614	u32 blt_ecoskpd;
		1615
		1616	/* Make sure blitter notifies FBC of writes */
		1617	gen6_gt_force_wake_get(dev_priv);
		1618	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
		1619	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY <<
		1620	GEN6_BLITTER_LOCK_SHIFT;
		1621	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1622	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY;
		1623	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1624	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
		1625	GEN6_BLITTER_LOCK_SHIFT);
		1626	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
		1627	POSTING_READ(GEN6_BLITTER_ECOSKPD);
		1628	gen6_gt_force_wake_put(dev_priv);
		1629	}
		1630
		1631	static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1632	{
		1633	struct drm_device *dev = crtc->dev;
		1634	struct drm_i915_private *dev_priv = dev->dev_private;
		1635	struct drm_framebuffer *fb = crtc->fb;
		1636	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
		1637	struct drm_i915_gem_object *obj = intel_fb->obj;
		1638	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1639	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
		1640	unsigned long stall_watermark = 200;
		1641	u32 dpfc_ctl;
		1642
		1643	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
		1644	dpfc_ctl &= DPFC_RESERVED;
		1645	dpfc_ctl \|= (plane \| DPFC_CTL_LIMIT_1X);
		1646	/* Set persistent mode for front-buffer rendering, ala X. */
		1647	dpfc_ctl \|= DPFC_CTL_PERSISTENT_MODE;
		1648	dpfc_ctl \|= (DPFC_CTL_FENCE_EN \| obj->fence_reg);
		1649	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
		1650
		1651	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
		1652	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
		1653	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
		1654	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
		1655	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset \| ILK_FBC_RT_VALID);
		1656	/* enable it... */
		1657	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl \| DPFC_CTL_EN);
		1658
		1659	if (IS_GEN6(dev)) {
		1660	I915_WRITE(SNB_DPFC_CTL_SA,
		1661	SNB_CPU_FENCE_ENABLE \| obj->fence_reg);
		1662	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
		1663	sandybridge_blit_fbc_update(dev);
		1664	}
		1665
		1666	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
		1667	}
		1668
		1669	static void ironlake_disable_fbc(struct drm_device *dev)
		1670	{
		1671	struct drm_i915_private *dev_priv = dev->dev_private;
		1672	u32 dpfc_ctl;
		1673
		1674	/* Disable compression */
		1675	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
		1676	if (dpfc_ctl & DPFC_CTL_EN) {
		1677	dpfc_ctl &= ~DPFC_CTL_EN;
		1678	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
		1679
		1680	DRM_DEBUG_KMS("disabled FBC\n");
		1681	}
		1682	}
		1683
		1684	static bool ironlake_fbc_enabled(struct drm_device *dev)
		1685	{
		1686	struct drm_i915_private *dev_priv = dev->dev_private;
		1687
		1688	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
		1689	}
		1690
		1691	bool intel_fbc_enabled(struct drm_device *dev)
		1692	{
		1693	struct drm_i915_private *dev_priv = dev->dev_private;
		1694
		1695	if (!dev_priv->display.fbc_enabled)
		1696	return false;
		1697
		1698	return dev_priv->display.fbc_enabled(dev);
		1699	}
		1700
		1701
		1702
		1703
		1704
		1705
		1706
		1707
		1708
		1709
		1710	static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
		1711	{
		1712	struct intel_fbc_work *work;
		1713	struct drm_device *dev = crtc->dev;
		1714	struct drm_i915_private *dev_priv = dev->dev_private;
		1715
		1716	if (!dev_priv->display.enable_fbc)
		1717	return;
		1718
		1719	// intel_cancel_fbc_work(dev_priv);
		1720
		1721	// work = kzalloc(sizeof *work, GFP_KERNEL);
		1722	// if (work == NULL) {
		1723	// dev_priv->display.enable_fbc(crtc, interval);
		1724	// return;
		1725	// }
		1726
		1727	// work->crtc = crtc;
		1728	// work->fb = crtc->fb;
		1729	// work->interval = interval;
		1730	// INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
		1731
		1732	// dev_priv->fbc_work = work;
		1733
		1734	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
		1735
		1736	/* Delay the actual enabling to let pageflipping cease and the
		1737	* display to settle before starting the compression. Note that
		1738	* this delay also serves a second purpose: it allows for a
		1739	* vblank to pass after disabling the FBC before we attempt
		1740	* to modify the control registers.
		1741	*
		1742	* A more complicated solution would involve tracking vblanks
		1743	* following the termination of the page-flipping sequence
		1744	* and indeed performing the enable as a co-routine and not
		1745	* waiting synchronously upon the vblank.
		1746	*/
		1747	// schedule_delayed_work(&work->work, msecs_to_jiffies(50));
		1748	}
		1749
		1750	void intel_disable_fbc(struct drm_device *dev)
		1751	{
		1752	struct drm_i915_private *dev_priv = dev->dev_private;
		1753
		1754	// intel_cancel_fbc_work(dev_priv);
		1755
		1756	if (!dev_priv->display.disable_fbc)
		1757	return;
		1758
		1759	dev_priv->display.disable_fbc(dev);
		1760	dev_priv->cfb_plane = -1;
		1761	}
		1762
		1763	/**
		1764	* intel_update_fbc - enable/disable FBC as needed
		1765	* @dev: the drm_device
		1766	*
		1767	* Set up the framebuffer compression hardware at mode set time. We
		1768	* enable it if possible:
		1769	* - plane A only (on pre-965)
		1770	* - no pixel mulitply/line duplication
		1771	* - no alpha buffer discard
		1772	* - no dual wide
		1773	* - framebuffer <= 2048 in width, 1536 in height
		1774	*
		1775	* We can't assume that any compression will take place (worst case),
		1776	* so the compressed buffer has to be the same size as the uncompressed
		1777	* one. It also must reside (along with the line length buffer) in
		1778	* stolen memory.
		1779	*
		1780	* We need to enable/disable FBC on a global basis.
		1781	*/
		1782	static void intel_update_fbc(struct drm_device *dev)
		1783	{
		1784	struct drm_i915_private *dev_priv = dev->dev_private;
		1785	struct drm_crtc crtc = NULL, tmp_crtc;
		1786	struct intel_crtc *intel_crtc;
		1787	struct drm_framebuffer *fb;
		1788	struct intel_framebuffer *intel_fb;
		1789	struct drm_i915_gem_object *obj;
		1790
		1791	DRM_DEBUG_KMS("\n");
		1792
		1793	if (!i915_powersave)
		1794	return;
		1795
		1796	if (!I915_HAS_FBC(dev))
		1797	return;
		1798
		1799	/*
		1800	* If FBC is already on, we just have to verify that we can
		1801	* keep it that way...
		1802	* Need to disable if:
		1803	* - more than one pipe is active
		1804	* - changing FBC params (stride, fence, mode)
		1805	* - new fb is too large to fit in compressed buffer
		1806	* - going to an unsupported config (interlace, pixel multiply, etc.)
		1807	*/
		1808	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
		1809	if (tmp_crtc->enabled && tmp_crtc->fb) {
		1810	if (crtc) {
		1811	DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2336	Serge	1812	dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2327	Serge	1813	goto out_disable;
		1814	}
		1815	crtc = tmp_crtc;
		1816	}
		1817	}
		1818
		1819	if (!crtc \|\| crtc->fb == NULL) {
		1820	DRM_DEBUG_KMS("no output, disabling\n");
2336	Serge	1821	dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2327	Serge	1822	goto out_disable;
		1823	}
		1824
		1825	intel_crtc = to_intel_crtc(crtc);
		1826	fb = crtc->fb;
		1827	intel_fb = to_intel_framebuffer(fb);
		1828	obj = intel_fb->obj;
		1829
		1830	if (!i915_enable_fbc) {
		1831	DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
2336	Serge	1832	dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2327	Serge	1833	goto out_disable;
		1834	}
		1835	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
		1836	DRM_DEBUG_KMS("framebuffer too large, disabling "
		1837	"compression\n");
2336	Serge	1838	dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2327	Serge	1839	goto out_disable;
		1840	}
		1841	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) \|\|
		1842	(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
		1843	DRM_DEBUG_KMS("mode incompatible with compression, "
		1844	"disabling\n");
2336	Serge	1845	dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2327	Serge	1846	goto out_disable;
		1847	}
		1848	if ((crtc->mode.hdisplay > 2048) \|\|
		1849	(crtc->mode.vdisplay > 1536)) {
		1850	DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2336	Serge	1851	dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2327	Serge	1852	goto out_disable;
		1853	}
		1854	if ((IS_I915GM(dev) \|\| IS_I945GM(dev)) && intel_crtc->plane != 0) {
		1855	DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2336	Serge	1856	dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2327	Serge	1857	goto out_disable;
		1858	}
		1859
		1860	/* The use of a CPU fence is mandatory in order to detect writes
		1861	* by the CPU to the scanout and trigger updates to the FBC.
		1862	*/
		1863	// if (obj->tiling_mode != I915_TILING_X \|\|
		1864	// obj->fence_reg == I915_FENCE_REG_NONE) {
		1865	// DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
		1866	// dev_priv->no_fbc_reason = FBC_NOT_TILED;
		1867	// goto out_disable;
		1868	// }
		1869
		1870	/* If the kernel debugger is active, always disable compression */
		1871	if (in_dbg_master())
		1872	goto out_disable;
		1873
		1874	/* If the scanout has not changed, don't modify the FBC settings.
		1875	* Note that we make the fundamental assumption that the fb->obj
		1876	* cannot be unpinned (and have its GTT offset and fence revoked)
		1877	* without first being decoupled from the scanout and FBC disabled.
		1878	*/
		1879	if (dev_priv->cfb_plane == intel_crtc->plane &&
		1880	dev_priv->cfb_fb == fb->base.id &&
		1881	dev_priv->cfb_y == crtc->y)
		1882	return;
		1883
		1884	if (intel_fbc_enabled(dev)) {
		1885	/* We update FBC along two paths, after changing fb/crtc
		1886	* configuration (modeswitching) and after page-flipping
		1887	* finishes. For the latter, we know that not only did
		1888	* we disable the FBC at the start of the page-flip
		1889	* sequence, but also more than one vblank has passed.
		1890	*
		1891	* For the former case of modeswitching, it is possible
		1892	* to switch between two FBC valid configurations
		1893	* instantaneously so we do need to disable the FBC
		1894	* before we can modify its control registers. We also
		1895	* have to wait for the next vblank for that to take
		1896	* effect. However, since we delay enabling FBC we can
		1897	* assume that a vblank has passed since disabling and
		1898	* that we can safely alter the registers in the deferred
		1899	* callback.
		1900	*
		1901	* In the scenario that we go from a valid to invalid
		1902	* and then back to valid FBC configuration we have
		1903	* no strict enforcement that a vblank occurred since
		1904	* disabling the FBC. However, along all current pipe
		1905	* disabling paths we do need to wait for a vblank at
		1906	* some point. And we wait before enabling FBC anyway.
		1907	*/
		1908	DRM_DEBUG_KMS("disabling active FBC for update\n");
		1909	intel_disable_fbc(dev);
		1910	}
		1911
		1912	intel_enable_fbc(crtc, 500);
		1913	return;
		1914
		1915	out_disable:
		1916	/* Multiple disables should be harmless */
		1917	if (intel_fbc_enabled(dev)) {
		1918	DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
		1919	intel_disable_fbc(dev);
		1920	}
		1921	}
		1922
2335	Serge	1923	int
		1924	intel_pin_and_fence_fb_obj(struct drm_device *dev,
		1925	struct drm_i915_gem_object *obj,
		1926	struct intel_ring_buffer *pipelined)
		1927	{
		1928	struct drm_i915_private *dev_priv = dev->dev_private;
		1929	u32 alignment;
		1930	int ret;
2327	Serge	1931
2335	Serge	1932	switch (obj->tiling_mode) {
		1933	case I915_TILING_NONE:
		1934	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
		1935	alignment = 128 * 1024;
		1936	else if (INTEL_INFO(dev)->gen >= 4)
		1937	alignment = 4 * 1024;
		1938	else
		1939	alignment = 64 * 1024;
		1940	break;
		1941	case I915_TILING_X:
		1942	/* pin() will align the object as required by fence */
		1943	alignment = 0;
		1944	break;
		1945	case I915_TILING_Y:
		1946	/* FIXME: Is this true? */
		1947	DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		1948	return -EINVAL;
		1949	default:
		1950	BUG();
		1951	}
2327	Serge	1952
2335	Serge	1953	dev_priv->mm.interruptible = false;
		1954	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
		1955	if (ret)
		1956	goto err_interruptible;
2327	Serge	1957
2335	Serge	1958	/* Install a fence for tiled scan-out. Pre-i965 always needs a
		1959	* fence, whereas 965+ only requires a fence if using
		1960	* framebuffer compression. For simplicity, we always install
		1961	* a fence as the cost is not that onerous.
		1962	*/
		1963	// if (obj->tiling_mode != I915_TILING_NONE) {
		1964	// ret = i915_gem_object_get_fence(obj, pipelined);
		1965	// if (ret)
		1966	// goto err_unpin;
		1967	// }
2327	Serge	1968
2335	Serge	1969	dev_priv->mm.interruptible = true;
		1970	return 0;
2327	Serge	1971
2335	Serge	1972	err_unpin:
		1973	// i915_gem_object_unpin(obj);
		1974	err_interruptible:
		1975	dev_priv->mm.interruptible = true;
		1976	return ret;
		1977	}
2327	Serge	1978
		1979	static int i9xx_update_plane(struct drm_crtc crtc, struct drm_framebuffer fb,
		1980	int x, int y)
		1981	{
		1982	struct drm_device *dev = crtc->dev;
		1983	struct drm_i915_private *dev_priv = dev->dev_private;
		1984	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1985	struct intel_framebuffer *intel_fb;
		1986	struct drm_i915_gem_object *obj;
		1987	int plane = intel_crtc->plane;
		1988	unsigned long Start, Offset;
		1989	u32 dspcntr;
		1990	u32 reg;
		1991
		1992	switch (plane) {
		1993	case 0:
		1994	case 1:
		1995	break;
		1996	default:
		1997	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		1998	return -EINVAL;
		1999	}
		2000
		2001	intel_fb = to_intel_framebuffer(fb);
		2002	obj = intel_fb->obj;
		2003
		2004	reg = DSPCNTR(plane);
		2005	dspcntr = I915_READ(reg);
		2006	/* Mask out pixel format bits in case we change it */
		2007	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2008	switch (fb->bits_per_pixel) {
		2009	case 8:
		2010	dspcntr \|= DISPPLANE_8BPP;
		2011	break;
		2012	case 16:
		2013	if (fb->depth == 15)
		2014	dspcntr \|= DISPPLANE_15_16BPP;
		2015	else
		2016	dspcntr \|= DISPPLANE_16BPP;
		2017	break;
		2018	case 24:
		2019	case 32:
		2020	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2021	break;
		2022	default:
		2023	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2024	return -EINVAL;
		2025	}
		2026	if (INTEL_INFO(dev)->gen >= 4) {
		2027	if (obj->tiling_mode != I915_TILING_NONE)
		2028	dspcntr \|= DISPPLANE_TILED;
		2029	else
		2030	dspcntr &= ~DISPPLANE_TILED;
		2031	}
		2032
		2033	I915_WRITE(reg, dspcntr);
		2034
		2035	Start = obj->gtt_offset;
		2036	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
		2037
		2038	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2039	Start, Offset, x, y, fb->pitch);
		2040	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
		2041	if (INTEL_INFO(dev)->gen >= 4) {
		2042	I915_WRITE(DSPSURF(plane), Start);
		2043	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
		2044	I915_WRITE(DSPADDR(plane), Offset);
		2045	} else
		2046	I915_WRITE(DSPADDR(plane), Start + Offset);
		2047	POSTING_READ(reg);
		2048
		2049	return 0;
		2050	}
		2051
		2052	static int ironlake_update_plane(struct drm_crtc *crtc,
		2053	struct drm_framebuffer *fb, int x, int y)
		2054	{
		2055	struct drm_device *dev = crtc->dev;
		2056	struct drm_i915_private *dev_priv = dev->dev_private;
		2057	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2058	struct intel_framebuffer *intel_fb;
		2059	struct drm_i915_gem_object *obj;
		2060	int plane = intel_crtc->plane;
		2061	unsigned long Start, Offset;
		2062	u32 dspcntr;
		2063	u32 reg;
		2064
		2065	switch (plane) {
		2066	case 0:
		2067	case 1:
		2068	break;
		2069	default:
		2070	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		2071	return -EINVAL;
		2072	}
		2073
		2074	intel_fb = to_intel_framebuffer(fb);
		2075	obj = intel_fb->obj;
		2076
		2077	reg = DSPCNTR(plane);
		2078	dspcntr = I915_READ(reg);
		2079	/* Mask out pixel format bits in case we change it */
		2080	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
		2081	switch (fb->bits_per_pixel) {
		2082	case 8:
		2083	dspcntr \|= DISPPLANE_8BPP;
		2084	break;
		2085	case 16:
		2086	if (fb->depth != 16)
		2087	return -EINVAL;
		2088
		2089	dspcntr \|= DISPPLANE_16BPP;
		2090	break;
		2091	case 24:
		2092	case 32:
		2093	if (fb->depth == 24)
		2094	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
		2095	else if (fb->depth == 30)
		2096	dspcntr \|= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		2097	else
		2098	return -EINVAL;
		2099	break;
		2100	default:
		2101	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		2102	return -EINVAL;
		2103	}
		2104
		2105	// if (obj->tiling_mode != I915_TILING_NONE)
		2106	// dspcntr \|= DISPPLANE_TILED;
		2107	// else
		2108	dspcntr &= ~DISPPLANE_TILED;
		2109
		2110	/* must disable */
		2111	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
		2112
		2113	I915_WRITE(reg, dspcntr);
		2114
2336	Serge	2115	Start = obj->gtt_offset;
		2116	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2327	Serge	2117
		2118	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		2119	Start, Offset, x, y, fb->pitch);
2330	Serge	2120	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
		2121	I915_WRITE(DSPSURF(plane), Start);
		2122	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
		2123	I915_WRITE(DSPADDR(plane), Offset);
		2124	POSTING_READ(reg);
2327	Serge	2125
		2126	return 0;
		2127	}
		2128
		2129	/* Assume fb object is pinned & idle & fenced and just update base pointers */
		2130	static int
		2131	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
		2132	int x, int y, enum mode_set_atomic state)
		2133	{
		2134	struct drm_device *dev = crtc->dev;
		2135	struct drm_i915_private *dev_priv = dev->dev_private;
		2136	int ret;
		2137
2336	Serge	2138	ENTER();
		2139
2327	Serge	2140	ret = dev_priv->display.update_plane(crtc, fb, x, y);
		2141	if (ret)
2336	Serge	2142	{
		2143	LEAVE();
2327	Serge	2144	return ret;
2336	Serge	2145	};
2327	Serge	2146
		2147	intel_update_fbc(dev);
		2148	intel_increase_pllclock(crtc);
2336	Serge	2149	LEAVE();
2327	Serge	2150
		2151	return 0;
		2152	}
		2153
		2154	static int
		2155	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
		2156	struct drm_framebuffer *old_fb)
		2157	{
		2158	struct drm_device *dev = crtc->dev;
		2159	struct drm_i915_master_private *master_priv;
		2160	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336	Serge	2161	int ret = 0;
2327	Serge	2162
2336	Serge	2163	ENTER();
		2164
2327	Serge	2165	/* no fb bound */
		2166	if (!crtc->fb) {
		2167	DRM_ERROR("No FB bound\n");
		2168	return 0;
		2169	}
		2170
		2171	switch (intel_crtc->plane) {
		2172	case 0:
		2173	case 1:
		2174	break;
		2175	default:
		2176	DRM_ERROR("no plane for crtc\n");
		2177	return -EINVAL;
		2178	}
		2179
		2180	mutex_lock(&dev->struct_mutex);
		2181
2336	Serge	2182	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
		2183	LEAVE_ATOMIC_MODE_SET);
2327	Serge	2184	if (ret) {
		2185	// i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		2186	mutex_unlock(&dev->struct_mutex);
		2187	DRM_ERROR("failed to update base address\n");
2336	Serge	2188	LEAVE();
2327	Serge	2189	return ret;
		2190	}
		2191
2336	Serge	2192	mutex_unlock(&dev->struct_mutex);
2327	Serge	2193
2336	Serge	2194
		2195	LEAVE();
		2196	return 0;
		2197
2330	Serge	2198	#if 0
2336	Serge	2199
2330	Serge	2200	if (!dev->primary->master)
2336	Serge	2201	{
		2202	LEAVE();
2330	Serge	2203	return 0;
2336	Serge	2204	};
2327	Serge	2205
2330	Serge	2206	master_priv = dev->primary->master->driver_priv;
		2207	if (!master_priv->sarea_priv)
2336	Serge	2208	{
		2209	LEAVE();
2330	Serge	2210	return 0;
2336	Serge	2211	};
2327	Serge	2212
2330	Serge	2213	if (intel_crtc->pipe) {
		2214	master_priv->sarea_priv->pipeB_x = x;
		2215	master_priv->sarea_priv->pipeB_y = y;
		2216	} else {
		2217	master_priv->sarea_priv->pipeA_x = x;
		2218	master_priv->sarea_priv->pipeA_y = y;
		2219	}
2336	Serge	2220	LEAVE();
		2221
		2222	return 0;
2330	Serge	2223	#endif
2336	Serge	2224
2327	Serge	2225	}
		2226
		2227	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
		2228	{
		2229	struct drm_device *dev = crtc->dev;
		2230	struct drm_i915_private *dev_priv = dev->dev_private;
		2231	u32 dpa_ctl;
		2232
		2233	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
		2234	dpa_ctl = I915_READ(DP_A);
		2235	dpa_ctl &= ~DP_PLL_FREQ_MASK;
		2236
		2237	if (clock < 200000) {
		2238	u32 temp;
		2239	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
		2240	/* workaround for 160Mhz:
		2241	1) program 0x4600c bits 15:0 = 0x8124
		2242	2) program 0x46010 bit 0 = 1
		2243	3) program 0x46034 bit 24 = 1
		2244	4) program 0x64000 bit 14 = 1
		2245	*/
		2246	temp = I915_READ(0x4600c);
		2247	temp &= 0xffff0000;
		2248	I915_WRITE(0x4600c, temp \| 0x8124);
		2249
		2250	temp = I915_READ(0x46010);
		2251	I915_WRITE(0x46010, temp \| 1);
		2252
		2253	temp = I915_READ(0x46034);
		2254	I915_WRITE(0x46034, temp \| (1 << 24));
		2255	} else {
		2256	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
		2257	}
		2258	I915_WRITE(DP_A, dpa_ctl);
		2259
		2260	POSTING_READ(DP_A);
		2261	udelay(500);
		2262	}
		2263
		2264	static void intel_fdi_normal_train(struct drm_crtc *crtc)
		2265	{
		2266	struct drm_device *dev = crtc->dev;
		2267	struct drm_i915_private *dev_priv = dev->dev_private;
		2268	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2269	int pipe = intel_crtc->pipe;
		2270	u32 reg, temp;
		2271
		2272	/* enable normal train */
		2273	reg = FDI_TX_CTL(pipe);
		2274	temp = I915_READ(reg);
		2275	if (IS_IVYBRIDGE(dev)) {
		2276	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2277	temp \|= FDI_LINK_TRAIN_NONE_IVB \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2278	} else {
		2279	temp &= ~FDI_LINK_TRAIN_NONE;
		2280	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		2281	}
		2282	I915_WRITE(reg, temp);
		2283
		2284	reg = FDI_RX_CTL(pipe);
		2285	temp = I915_READ(reg);
		2286	if (HAS_PCH_CPT(dev)) {
		2287	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2288	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		2289	} else {
		2290	temp &= ~FDI_LINK_TRAIN_NONE;
		2291	temp \|= FDI_LINK_TRAIN_NONE;
		2292	}
		2293	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
		2294
		2295	/* wait one idle pattern time */
		2296	POSTING_READ(reg);
		2297	udelay(1000);
		2298
		2299	/* IVB wants error correction enabled */
		2300	if (IS_IVYBRIDGE(dev))
		2301	I915_WRITE(reg, I915_READ(reg) \| FDI_FS_ERRC_ENABLE \|
		2302	FDI_FE_ERRC_ENABLE);
		2303	}
		2304
		2305	static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
		2306	{
		2307	struct drm_i915_private *dev_priv = dev->dev_private;
		2308	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2309
		2310	flags \|= FDI_PHASE_SYNC_OVR(pipe);
		2311	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
		2312	flags \|= FDI_PHASE_SYNC_EN(pipe);
		2313	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
		2314	POSTING_READ(SOUTH_CHICKEN1);
		2315	}
		2316
		2317	/* The FDI link training functions for ILK/Ibexpeak. */
		2318	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		2319	{
		2320	struct drm_device *dev = crtc->dev;
		2321	struct drm_i915_private *dev_priv = dev->dev_private;
		2322	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2323	int pipe = intel_crtc->pipe;
		2324	int plane = intel_crtc->plane;
		2325	u32 reg, temp, tries;
		2326
		2327	/* FDI needs bits from pipe & plane first */
		2328	assert_pipe_enabled(dev_priv, pipe);
		2329	assert_plane_enabled(dev_priv, plane);
		2330
		2331	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2332	for train result */
		2333	reg = FDI_RX_IMR(pipe);
		2334	temp = I915_READ(reg);
		2335	temp &= ~FDI_RX_SYMBOL_LOCK;
		2336	temp &= ~FDI_RX_BIT_LOCK;
		2337	I915_WRITE(reg, temp);
		2338	I915_READ(reg);
		2339	udelay(150);
		2340
		2341	/* enable CPU FDI TX and PCH FDI RX */
		2342	reg = FDI_TX_CTL(pipe);
		2343	temp = I915_READ(reg);
		2344	temp &= ~(7 << 19);
		2345	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2346	temp &= ~FDI_LINK_TRAIN_NONE;
		2347	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2348	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2349
		2350	reg = FDI_RX_CTL(pipe);
		2351	temp = I915_READ(reg);
		2352	temp &= ~FDI_LINK_TRAIN_NONE;
		2353	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2354	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2355
		2356	POSTING_READ(reg);
		2357	udelay(150);
		2358
		2359	/* Ironlake workaround, enable clock pointer after FDI enable*/
		2360	if (HAS_PCH_IBX(dev)) {
		2361	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2362	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
		2363	FDI_RX_PHASE_SYNC_POINTER_EN);
		2364	}
		2365
		2366	reg = FDI_RX_IIR(pipe);
		2367	for (tries = 0; tries < 5; tries++) {
		2368	temp = I915_READ(reg);
		2369	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2370
		2371	if ((temp & FDI_RX_BIT_LOCK)) {
		2372	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2373	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2374	break;
		2375	}
		2376	}
		2377	if (tries == 5)
		2378	DRM_ERROR("FDI train 1 fail!\n");
		2379
		2380	/* Train 2 */
		2381	reg = FDI_TX_CTL(pipe);
		2382	temp = I915_READ(reg);
		2383	temp &= ~FDI_LINK_TRAIN_NONE;
		2384	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2385	I915_WRITE(reg, temp);
		2386
		2387	reg = FDI_RX_CTL(pipe);
		2388	temp = I915_READ(reg);
		2389	temp &= ~FDI_LINK_TRAIN_NONE;
		2390	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2391	I915_WRITE(reg, temp);
		2392
		2393	POSTING_READ(reg);
		2394	udelay(150);
		2395
		2396	reg = FDI_RX_IIR(pipe);
		2397	for (tries = 0; tries < 5; tries++) {
		2398	temp = I915_READ(reg);
		2399	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2400
		2401	if (temp & FDI_RX_SYMBOL_LOCK) {
		2402	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2403	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2404	break;
		2405	}
		2406	}
		2407	if (tries == 5)
		2408	DRM_ERROR("FDI train 2 fail!\n");
		2409
		2410	DRM_DEBUG_KMS("FDI train done\n");
		2411
		2412	}
		2413
		2414	static const int snb_b_fdi_train_param [] = {
		2415	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
		2416	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
		2417	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
		2418	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
		2419	};
		2420
		2421	/* The FDI link training functions for SNB/Cougarpoint. */
		2422	static void gen6_fdi_link_train(struct drm_crtc *crtc)
		2423	{
		2424	struct drm_device *dev = crtc->dev;
		2425	struct drm_i915_private *dev_priv = dev->dev_private;
		2426	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2427	int pipe = intel_crtc->pipe;
		2428	u32 reg, temp, i;
		2429
		2430	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2431	for train result */
		2432	reg = FDI_RX_IMR(pipe);
		2433	temp = I915_READ(reg);
		2434	temp &= ~FDI_RX_SYMBOL_LOCK;
		2435	temp &= ~FDI_RX_BIT_LOCK;
		2436	I915_WRITE(reg, temp);
		2437
		2438	POSTING_READ(reg);
		2439	udelay(150);
		2440
		2441	/* enable CPU FDI TX and PCH FDI RX */
		2442	reg = FDI_TX_CTL(pipe);
		2443	temp = I915_READ(reg);
		2444	temp &= ~(7 << 19);
		2445	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2446	temp &= ~FDI_LINK_TRAIN_NONE;
		2447	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2448	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2449	/* SNB-B */
		2450	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2451	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2452
		2453	reg = FDI_RX_CTL(pipe);
		2454	temp = I915_READ(reg);
		2455	if (HAS_PCH_CPT(dev)) {
		2456	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2457	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2458	} else {
		2459	temp &= ~FDI_LINK_TRAIN_NONE;
		2460	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2461	}
		2462	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2463
		2464	POSTING_READ(reg);
		2465	udelay(150);
		2466
		2467	if (HAS_PCH_CPT(dev))
		2468	cpt_phase_pointer_enable(dev, pipe);
		2469
		2470	for (i = 0; i < 4; i++ ) {
		2471	reg = FDI_TX_CTL(pipe);
		2472	temp = I915_READ(reg);
		2473	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2474	temp \|= snb_b_fdi_train_param[i];
		2475	I915_WRITE(reg, temp);
		2476
		2477	POSTING_READ(reg);
		2478	udelay(500);
		2479
		2480	reg = FDI_RX_IIR(pipe);
		2481	temp = I915_READ(reg);
		2482	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2483
		2484	if (temp & FDI_RX_BIT_LOCK) {
		2485	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2486	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2487	break;
		2488	}
		2489	}
		2490	if (i == 4)
		2491	DRM_ERROR("FDI train 1 fail!\n");
		2492
		2493	/* Train 2 */
		2494	reg = FDI_TX_CTL(pipe);
		2495	temp = I915_READ(reg);
		2496	temp &= ~FDI_LINK_TRAIN_NONE;
		2497	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2498	if (IS_GEN6(dev)) {
		2499	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2500	/* SNB-B */
		2501	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2502	}
		2503	I915_WRITE(reg, temp);
		2504
		2505	reg = FDI_RX_CTL(pipe);
		2506	temp = I915_READ(reg);
		2507	if (HAS_PCH_CPT(dev)) {
		2508	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2509	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2510	} else {
		2511	temp &= ~FDI_LINK_TRAIN_NONE;
		2512	temp \|= FDI_LINK_TRAIN_PATTERN_2;
		2513	}
		2514	I915_WRITE(reg, temp);
		2515
		2516	POSTING_READ(reg);
		2517	udelay(150);
		2518
		2519	for (i = 0; i < 4; i++ ) {
		2520	reg = FDI_TX_CTL(pipe);
		2521	temp = I915_READ(reg);
		2522	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2523	temp \|= snb_b_fdi_train_param[i];
		2524	I915_WRITE(reg, temp);
		2525
		2526	POSTING_READ(reg);
		2527	udelay(500);
		2528
		2529	reg = FDI_RX_IIR(pipe);
		2530	temp = I915_READ(reg);
		2531	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2532
		2533	if (temp & FDI_RX_SYMBOL_LOCK) {
		2534	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2535	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2536	break;
		2537	}
		2538	}
		2539	if (i == 4)
		2540	DRM_ERROR("FDI train 2 fail!\n");
		2541
		2542	DRM_DEBUG_KMS("FDI train done.\n");
		2543	}
		2544
		2545	/* Manual link training for Ivy Bridge A0 parts */
		2546	static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
		2547	{
		2548	struct drm_device *dev = crtc->dev;
		2549	struct drm_i915_private *dev_priv = dev->dev_private;
		2550	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2551	int pipe = intel_crtc->pipe;
		2552	u32 reg, temp, i;
		2553
		2554	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
		2555	for train result */
		2556	reg = FDI_RX_IMR(pipe);
		2557	temp = I915_READ(reg);
		2558	temp &= ~FDI_RX_SYMBOL_LOCK;
		2559	temp &= ~FDI_RX_BIT_LOCK;
		2560	I915_WRITE(reg, temp);
		2561
		2562	POSTING_READ(reg);
		2563	udelay(150);
		2564
		2565	/* enable CPU FDI TX and PCH FDI RX */
		2566	reg = FDI_TX_CTL(pipe);
		2567	temp = I915_READ(reg);
		2568	temp &= ~(7 << 19);
		2569	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2570	temp &= ~(FDI_LINK_TRAIN_AUTO \| FDI_LINK_TRAIN_NONE_IVB);
		2571	temp \|= FDI_LINK_TRAIN_PATTERN_1_IVB;
		2572	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2573	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2574	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
		2575
		2576	reg = FDI_RX_CTL(pipe);
		2577	temp = I915_READ(reg);
		2578	temp &= ~FDI_LINK_TRAIN_AUTO;
		2579	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2580	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2581	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
		2582
		2583	POSTING_READ(reg);
		2584	udelay(150);
		2585
		2586	if (HAS_PCH_CPT(dev))
		2587	cpt_phase_pointer_enable(dev, pipe);
		2588
		2589	for (i = 0; i < 4; i++ ) {
		2590	reg = FDI_TX_CTL(pipe);
		2591	temp = I915_READ(reg);
		2592	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2593	temp \|= snb_b_fdi_train_param[i];
		2594	I915_WRITE(reg, temp);
		2595
		2596	POSTING_READ(reg);
		2597	udelay(500);
		2598
		2599	reg = FDI_RX_IIR(pipe);
		2600	temp = I915_READ(reg);
		2601	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2602
		2603	if (temp & FDI_RX_BIT_LOCK \|\|
		2604	(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
		2605	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
		2606	DRM_DEBUG_KMS("FDI train 1 done.\n");
		2607	break;
		2608	}
		2609	}
		2610	if (i == 4)
		2611	DRM_ERROR("FDI train 1 fail!\n");
		2612
		2613	/* Train 2 */
		2614	reg = FDI_TX_CTL(pipe);
		2615	temp = I915_READ(reg);
		2616	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		2617	temp \|= FDI_LINK_TRAIN_PATTERN_2_IVB;
		2618	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2619	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
		2620	I915_WRITE(reg, temp);
		2621
		2622	reg = FDI_RX_CTL(pipe);
		2623	temp = I915_READ(reg);
		2624	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2625	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
		2626	I915_WRITE(reg, temp);
		2627
		2628	POSTING_READ(reg);
		2629	udelay(150);
		2630
		2631	for (i = 0; i < 4; i++ ) {
		2632	reg = FDI_TX_CTL(pipe);
		2633	temp = I915_READ(reg);
		2634	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		2635	temp \|= snb_b_fdi_train_param[i];
		2636	I915_WRITE(reg, temp);
		2637
		2638	POSTING_READ(reg);
		2639	udelay(500);
		2640
		2641	reg = FDI_RX_IIR(pipe);
		2642	temp = I915_READ(reg);
		2643	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
		2644
		2645	if (temp & FDI_RX_SYMBOL_LOCK) {
		2646	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
		2647	DRM_DEBUG_KMS("FDI train 2 done.\n");
		2648	break;
		2649	}
		2650	}
		2651	if (i == 4)
		2652	DRM_ERROR("FDI train 2 fail!\n");
		2653
		2654	DRM_DEBUG_KMS("FDI train done.\n");
		2655	}
		2656
		2657	static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
		2658	{
		2659	struct drm_device *dev = crtc->dev;
		2660	struct drm_i915_private *dev_priv = dev->dev_private;
		2661	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2662	int pipe = intel_crtc->pipe;
		2663	u32 reg, temp;
		2664
		2665	/* Write the TU size bits so error detection works */
		2666	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		2667	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
		2668
		2669	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
		2670	reg = FDI_RX_CTL(pipe);
		2671	temp = I915_READ(reg);
		2672	temp &= ~((0x7 << 19) \| (0x7 << 16));
		2673	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
		2674	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2675	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
		2676
		2677	POSTING_READ(reg);
		2678	udelay(200);
		2679
		2680	/* Switch from Rawclk to PCDclk */
		2681	temp = I915_READ(reg);
		2682	I915_WRITE(reg, temp \| FDI_PCDCLK);
		2683
		2684	POSTING_READ(reg);
		2685	udelay(200);
		2686
		2687	/* Enable CPU FDI TX PLL, always on for Ironlake */
		2688	reg = FDI_TX_CTL(pipe);
		2689	temp = I915_READ(reg);
		2690	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		2691	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
		2692
		2693	POSTING_READ(reg);
		2694	udelay(100);
		2695	}
		2696	}
		2697
		2698	static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
		2699	{
		2700	struct drm_i915_private *dev_priv = dev->dev_private;
		2701	u32 flags = I915_READ(SOUTH_CHICKEN1);
		2702
		2703	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
		2704	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
		2705	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
		2706	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
		2707	POSTING_READ(SOUTH_CHICKEN1);
		2708	}
		2709	static void ironlake_fdi_disable(struct drm_crtc *crtc)
		2710	{
		2711	struct drm_device *dev = crtc->dev;
		2712	struct drm_i915_private *dev_priv = dev->dev_private;
		2713	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2714	int pipe = intel_crtc->pipe;
		2715	u32 reg, temp;
		2716
		2717	/* disable CPU FDI tx and PCH FDI rx */
		2718	reg = FDI_TX_CTL(pipe);
		2719	temp = I915_READ(reg);
		2720	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
		2721	POSTING_READ(reg);
		2722
		2723	reg = FDI_RX_CTL(pipe);
		2724	temp = I915_READ(reg);
		2725	temp &= ~(0x7 << 16);
		2726	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2727	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
		2728
		2729	POSTING_READ(reg);
		2730	udelay(100);
		2731
		2732	/* Ironlake workaround, disable clock pointer after downing FDI */
		2733	if (HAS_PCH_IBX(dev)) {
		2734	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		2735	I915_WRITE(FDI_RX_CHICKEN(pipe),
		2736	I915_READ(FDI_RX_CHICKEN(pipe) &
		2737	~FDI_RX_PHASE_SYNC_POINTER_EN));
		2738	} else if (HAS_PCH_CPT(dev)) {
		2739	cpt_phase_pointer_disable(dev, pipe);
		2740	}
		2741
		2742	/* still set train pattern 1 */
		2743	reg = FDI_TX_CTL(pipe);
		2744	temp = I915_READ(reg);
		2745	temp &= ~FDI_LINK_TRAIN_NONE;
		2746	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2747	I915_WRITE(reg, temp);
		2748
		2749	reg = FDI_RX_CTL(pipe);
		2750	temp = I915_READ(reg);
		2751	if (HAS_PCH_CPT(dev)) {
		2752	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		2753	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
		2754	} else {
		2755	temp &= ~FDI_LINK_TRAIN_NONE;
		2756	temp \|= FDI_LINK_TRAIN_PATTERN_1;
		2757	}
		2758	/* BPC in FDI rx is consistent with that in PIPECONF */
		2759	temp &= ~(0x07 << 16);
		2760	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
		2761	I915_WRITE(reg, temp);
		2762
		2763	POSTING_READ(reg);
		2764	udelay(100);
		2765	}
		2766
		2767	/*
		2768	* When we disable a pipe, we need to clear any pending scanline wait events
		2769	* to avoid hanging the ring, which we assume we are waiting on.
		2770	*/
		2771	static void intel_clear_scanline_wait(struct drm_device *dev)
		2772	{
		2773	struct drm_i915_private *dev_priv = dev->dev_private;
		2774	struct intel_ring_buffer *ring;
		2775	u32 tmp;
		2776
		2777	if (IS_GEN2(dev))
		2778	/* Can't break the hang on i8xx */
		2779	return;
		2780
		2781	ring = LP_RING(dev_priv);
		2782	tmp = I915_READ_CTL(ring);
		2783	if (tmp & RING_WAIT)
		2784	I915_WRITE_CTL(ring, tmp);
		2785	}
		2786
		2787	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
		2788	{
		2789	struct drm_i915_gem_object *obj;
		2790	struct drm_i915_private *dev_priv;
		2791
		2792	if (crtc->fb == NULL)
		2793	return;
		2794
		2795	obj = to_intel_framebuffer(crtc->fb)->obj;
		2796	dev_priv = crtc->dev->dev_private;
		2797	// wait_event(dev_priv->pending_flip_queue,
		2798	// atomic_read(&obj->pending_flip) == 0);
		2799	}
		2800
		2801	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
		2802	{
		2803	struct drm_device *dev = crtc->dev;
		2804	struct drm_mode_config *mode_config = &dev->mode_config;
		2805	struct intel_encoder *encoder;
		2806
		2807	/*
		2808	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
		2809	* must be driven by its own crtc; no sharing is possible.
		2810	*/
		2811	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		2812	if (encoder->base.crtc != crtc)
		2813	continue;
		2814
		2815	switch (encoder->type) {
		2816	case INTEL_OUTPUT_EDP:
		2817	if (!intel_encoder_is_pch_edp(&encoder->base))
		2818	return false;
		2819	continue;
		2820	}
		2821	}
		2822
		2823	return true;
		2824	}
		2825
		2826	/*
		2827	* Enable PCH resources required for PCH ports:
		2828	* - PCH PLLs
		2829	* - FDI training & RX/TX
		2830	* - update transcoder timings
		2831	* - DP transcoding bits
		2832	* - transcoder
		2833	*/
		2834	static void ironlake_pch_enable(struct drm_crtc *crtc)
		2835	{
		2836	struct drm_device *dev = crtc->dev;
		2837	struct drm_i915_private *dev_priv = dev->dev_private;
		2838	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2839	int pipe = intel_crtc->pipe;
		2840	u32 reg, temp;
		2841
		2842	/* For PCH output, training FDI link */
		2843	dev_priv->display.fdi_link_train(crtc);
		2844
		2845	intel_enable_pch_pll(dev_priv, pipe);
		2846
		2847	if (HAS_PCH_CPT(dev)) {
		2848	/* Be sure PCH DPLL SEL is set */
		2849	temp = I915_READ(PCH_DPLL_SEL);
		2850	if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
		2851	temp \|= (TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
		2852	else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
		2853	temp \|= (TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		2854	I915_WRITE(PCH_DPLL_SEL, temp);
		2855	}
		2856
		2857	/* set transcoder timing, panel must allow it */
		2858	assert_panel_unlocked(dev_priv, pipe);
		2859	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
		2860	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
		2861	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
		2862
		2863	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
		2864	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		2865	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
		2866
		2867	intel_fdi_normal_train(crtc);
		2868
		2869	/* For PCH DP, enable TRANS_DP_CTL */
		2870	if (HAS_PCH_CPT(dev) &&
		2871	intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		2872	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
		2873	reg = TRANS_DP_CTL(pipe);
		2874	temp = I915_READ(reg);
		2875	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
		2876	TRANS_DP_SYNC_MASK \|
		2877	TRANS_DP_BPC_MASK);
		2878	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
		2879	TRANS_DP_ENH_FRAMING);
		2880	temp \|= bpc << 9; /* same format but at 11:9 */
		2881
		2882	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
		2883	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
		2884	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
		2885	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
		2886
		2887	switch (intel_trans_dp_port_sel(crtc)) {
		2888	case PCH_DP_B:
		2889	temp \|= TRANS_DP_PORT_SEL_B;
		2890	break;
		2891	case PCH_DP_C:
		2892	temp \|= TRANS_DP_PORT_SEL_C;
		2893	break;
		2894	case PCH_DP_D:
		2895	temp \|= TRANS_DP_PORT_SEL_D;
		2896	break;
		2897	default:
		2898	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
		2899	temp \|= TRANS_DP_PORT_SEL_B;
		2900	break;
		2901	}
		2902
		2903	I915_WRITE(reg, temp);
		2904	}
		2905
		2906	intel_enable_transcoder(dev_priv, pipe);
		2907	}
		2908
		2909	static void ironlake_crtc_enable(struct drm_crtc *crtc)
		2910	{
		2911	struct drm_device *dev = crtc->dev;
		2912	struct drm_i915_private *dev_priv = dev->dev_private;
		2913	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2914	int pipe = intel_crtc->pipe;
		2915	int plane = intel_crtc->plane;
		2916	u32 temp;
		2917	bool is_pch_port;
		2918
		2919	if (intel_crtc->active)
		2920	return;
		2921
		2922	intel_crtc->active = true;
		2923	intel_update_watermarks(dev);
		2924
		2925	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		2926	temp = I915_READ(PCH_LVDS);
		2927	if ((temp & LVDS_PORT_EN) == 0)
		2928	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
		2929	}
		2930
		2931	is_pch_port = intel_crtc_driving_pch(crtc);
		2932
		2933	if (is_pch_port)
		2934	ironlake_fdi_pll_enable(crtc);
		2935	else
		2936	ironlake_fdi_disable(crtc);
		2937
		2938	/* Enable panel fitting for LVDS */
		2939	if (dev_priv->pch_pf_size &&
		2940	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {
		2941	/* Force use of hard-coded filter coefficients
		2942	* as some pre-programmed values are broken,
		2943	* e.g. x201.
		2944	*/
		2945	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
		2946	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		2947	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
		2948	}
		2949
		2950	/*
		2951	* On ILK+ LUT must be loaded before the pipe is running but with
		2952	* clocks enabled
		2953	*/
		2954	intel_crtc_load_lut(crtc);
		2955
		2956	intel_enable_pipe(dev_priv, pipe, is_pch_port);
		2957	intel_enable_plane(dev_priv, plane, pipe);
		2958
		2959	if (is_pch_port)
		2960	ironlake_pch_enable(crtc);
		2961
		2962	mutex_lock(&dev->struct_mutex);
		2963	intel_update_fbc(dev);
		2964	mutex_unlock(&dev->struct_mutex);
		2965
		2966	// intel_crtc_update_cursor(crtc, true);
		2967	}
		2968
		2969	static void ironlake_crtc_disable(struct drm_crtc *crtc)
		2970	{
		2971	struct drm_device *dev = crtc->dev;
		2972	struct drm_i915_private *dev_priv = dev->dev_private;
		2973	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2974	int pipe = intel_crtc->pipe;
		2975	int plane = intel_crtc->plane;
		2976	u32 reg, temp;
		2977
		2978	if (!intel_crtc->active)
		2979	return;
		2980
2336	Serge	2981	ENTER();
		2982
2327	Serge	2983	intel_crtc_wait_for_pending_flips(crtc);
		2984	// drm_vblank_off(dev, pipe);
		2985	// intel_crtc_update_cursor(crtc, false);
		2986
		2987	intel_disable_plane(dev_priv, plane, pipe);
		2988
		2989	if (dev_priv->cfb_plane == plane)
		2990	intel_disable_fbc(dev);
		2991
		2992	intel_disable_pipe(dev_priv, pipe);
		2993
		2994	/* Disable PF */
		2995	I915_WRITE(PF_CTL(pipe), 0);
		2996	I915_WRITE(PF_WIN_SZ(pipe), 0);
		2997
		2998	ironlake_fdi_disable(crtc);
		2999
		3000	/* This is a horrible layering violation; we should be doing this in
		3001	* the connector/encoder ->prepare instead, but we don't always have
		3002	* enough information there about the config to know whether it will
		3003	* actually be necessary or just cause undesired flicker.
		3004	*/
		3005	intel_disable_pch_ports(dev_priv, pipe);
		3006
		3007	intel_disable_transcoder(dev_priv, pipe);
		3008
		3009	if (HAS_PCH_CPT(dev)) {
		3010	/* disable TRANS_DP_CTL */
		3011	reg = TRANS_DP_CTL(pipe);
		3012	temp = I915_READ(reg);
		3013	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
		3014	temp \|= TRANS_DP_PORT_SEL_NONE;
		3015	I915_WRITE(reg, temp);
		3016
		3017	/* disable DPLL_SEL */
		3018	temp = I915_READ(PCH_DPLL_SEL);
		3019	switch (pipe) {
		3020	case 0:
		3021	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
		3022	break;
		3023	case 1:
		3024	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
		3025	break;
		3026	case 2:
		3027	/* FIXME: manage transcoder PLLs? */
		3028	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
		3029	break;
		3030	default:
		3031	BUG(); /* wtf */
		3032	}
		3033	I915_WRITE(PCH_DPLL_SEL, temp);
		3034	}
		3035
		3036	/* disable PCH DPLL */
		3037	intel_disable_pch_pll(dev_priv, pipe);
		3038
		3039	/* Switch from PCDclk to Rawclk */
		3040	reg = FDI_RX_CTL(pipe);
		3041	temp = I915_READ(reg);
		3042	I915_WRITE(reg, temp & ~FDI_PCDCLK);
		3043
		3044	/* Disable CPU FDI TX PLL */
		3045	reg = FDI_TX_CTL(pipe);
		3046	temp = I915_READ(reg);
		3047	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
		3048
		3049	POSTING_READ(reg);
		3050	udelay(100);
		3051
		3052	reg = FDI_RX_CTL(pipe);
		3053	temp = I915_READ(reg);
		3054	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
		3055
		3056	/* Wait for the clocks to turn off. */
		3057	POSTING_READ(reg);
		3058	udelay(100);
		3059
		3060	intel_crtc->active = false;
		3061	intel_update_watermarks(dev);
		3062
		3063	mutex_lock(&dev->struct_mutex);
		3064	intel_update_fbc(dev);
		3065	intel_clear_scanline_wait(dev);
		3066	mutex_unlock(&dev->struct_mutex);
2336	Serge	3067
		3068	LEAVE();
		3069
2327	Serge	3070	}
		3071
		3072	static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
		3073	{
		3074	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3075	int pipe = intel_crtc->pipe;
		3076	int plane = intel_crtc->plane;
		3077
		3078	/* XXX: When our outputs are all unaware of DPMS modes other than off
		3079	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
		3080	*/
		3081	switch (mode) {
		3082	case DRM_MODE_DPMS_ON:
		3083	case DRM_MODE_DPMS_STANDBY:
		3084	case DRM_MODE_DPMS_SUSPEND:
		3085	DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
		3086	ironlake_crtc_enable(crtc);
		3087	break;
		3088
		3089	case DRM_MODE_DPMS_OFF:
		3090	DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
		3091	ironlake_crtc_disable(crtc);
		3092	break;
		3093	}
		3094	}
		3095
		3096	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
		3097	{
		3098	if (!enable && intel_crtc->overlay) {
		3099	struct drm_device *dev = intel_crtc->base.dev;
		3100	struct drm_i915_private *dev_priv = dev->dev_private;
		3101
		3102	mutex_lock(&dev->struct_mutex);
		3103	dev_priv->mm.interruptible = false;
		3104	// (void) intel_overlay_switch_off(intel_crtc->overlay);
		3105	dev_priv->mm.interruptible = true;
		3106	mutex_unlock(&dev->struct_mutex);
		3107	}
		3108
		3109	/* Let userspace switch the overlay on again. In most cases userspace
		3110	* has to recompute where to put it anyway.
		3111	*/
		3112	}
		3113
		3114	static void i9xx_crtc_enable(struct drm_crtc *crtc)
		3115	{
		3116	struct drm_device *dev = crtc->dev;
		3117	struct drm_i915_private *dev_priv = dev->dev_private;
		3118	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3119	int pipe = intel_crtc->pipe;
		3120	int plane = intel_crtc->plane;
		3121
		3122	if (intel_crtc->active)
		3123	return;
		3124
		3125	intel_crtc->active = true;
		3126	intel_update_watermarks(dev);
		3127
		3128	intel_enable_pll(dev_priv, pipe);
		3129	intel_enable_pipe(dev_priv, pipe, false);
		3130	intel_enable_plane(dev_priv, plane, pipe);
		3131
		3132	intel_crtc_load_lut(crtc);
		3133	intel_update_fbc(dev);
		3134
		3135	/* Give the overlay scaler a chance to enable if it's on this pipe */
		3136	intel_crtc_dpms_overlay(intel_crtc, true);
		3137	// intel_crtc_update_cursor(crtc, true);
		3138	}
		3139
		3140	static void i9xx_crtc_disable(struct drm_crtc *crtc)
		3141	{
		3142	struct drm_device *dev = crtc->dev;
		3143	struct drm_i915_private *dev_priv = dev->dev_private;
		3144	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3145	int pipe = intel_crtc->pipe;
		3146	int plane = intel_crtc->plane;
		3147
		3148	if (!intel_crtc->active)
		3149	return;
		3150
		3151	/* Give the overlay scaler a chance to disable if it's on this pipe */
		3152	intel_crtc_wait_for_pending_flips(crtc);
		3153	// drm_vblank_off(dev, pipe);
		3154	intel_crtc_dpms_overlay(intel_crtc, false);
		3155	// intel_crtc_update_cursor(crtc, false);
		3156
		3157	if (dev_priv->cfb_plane == plane)
		3158	intel_disable_fbc(dev);
		3159
		3160	intel_disable_plane(dev_priv, plane, pipe);
		3161	intel_disable_pipe(dev_priv, pipe);
		3162	intel_disable_pll(dev_priv, pipe);
		3163
		3164	intel_crtc->active = false;
		3165	intel_update_fbc(dev);
		3166	intel_update_watermarks(dev);
		3167	intel_clear_scanline_wait(dev);
		3168	}
		3169
		3170	static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
		3171	{
		3172	/* XXX: When our outputs are all unaware of DPMS modes other than off
		3173	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
		3174	*/
		3175	switch (mode) {
		3176	case DRM_MODE_DPMS_ON:
		3177	case DRM_MODE_DPMS_STANDBY:
		3178	case DRM_MODE_DPMS_SUSPEND:
		3179	i9xx_crtc_enable(crtc);
		3180	break;
		3181	case DRM_MODE_DPMS_OFF:
		3182	i9xx_crtc_disable(crtc);
		3183	break;
		3184	}
		3185	}
		3186
2330	Serge	3187	/**
		3188	* Sets the power management mode of the pipe and plane.
		3189	*/
		3190	static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
		3191	{
		3192	struct drm_device *dev = crtc->dev;
		3193	struct drm_i915_private *dev_priv = dev->dev_private;
		3194	struct drm_i915_master_private *master_priv;
		3195	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3196	int pipe = intel_crtc->pipe;
		3197	bool enabled;
2327	Serge	3198
2330	Serge	3199	if (intel_crtc->dpms_mode == mode)
		3200	return;
2327	Serge	3201
2330	Serge	3202	intel_crtc->dpms_mode = mode;
2327	Serge	3203
2330	Serge	3204	dev_priv->display.dpms(crtc, mode);
2327	Serge	3205
2330	Serge	3206	if (!dev->primary->master)
		3207	return;
2327	Serge	3208
2330	Serge	3209	master_priv = dev->primary->master->driver_priv;
		3210	if (!master_priv->sarea_priv)
		3211	return;
2327	Serge	3212
2330	Serge	3213	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2327	Serge	3214
2330	Serge	3215	switch (pipe) {
		3216	case 0:
		3217	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		3218	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		3219	break;
		3220	case 1:
		3221	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		3222	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		3223	break;
		3224	default:
		3225	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
		3226	break;
		3227	}
		3228	}
2327	Serge	3229
2330	Serge	3230	static void intel_crtc_disable(struct drm_crtc *crtc)
		3231	{
		3232	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
		3233	struct drm_device *dev = crtc->dev;
2327	Serge	3234
2330	Serge	3235	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327	Serge	3236
2330	Serge	3237	if (crtc->fb) {
		3238	mutex_lock(&dev->struct_mutex);
		3239	// i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		3240	mutex_unlock(&dev->struct_mutex);
		3241	}
		3242	}
2327	Serge	3243
2330	Serge	3244	/* Prepare for a mode set.
		3245	*
		3246	* Note we could be a lot smarter here. We need to figure out which outputs
		3247	* will be enabled, which disabled (in short, how the config will changes)
		3248	* and perform the minimum necessary steps to accomplish that, e.g. updating
		3249	* watermarks, FBC configuration, making sure PLLs are programmed correctly,
		3250	* panel fitting is in the proper state, etc.
		3251	*/
		3252	static void i9xx_crtc_prepare(struct drm_crtc *crtc)
		3253	{
		3254	i9xx_crtc_disable(crtc);
		3255	}
2327	Serge	3256
2330	Serge	3257	static void i9xx_crtc_commit(struct drm_crtc *crtc)
		3258	{
		3259	i9xx_crtc_enable(crtc);
		3260	}
2327	Serge	3261
2330	Serge	3262	static void ironlake_crtc_prepare(struct drm_crtc *crtc)
		3263	{
		3264	ironlake_crtc_disable(crtc);
		3265	}
2327	Serge	3266
2330	Serge	3267	static void ironlake_crtc_commit(struct drm_crtc *crtc)
		3268	{
		3269	ironlake_crtc_enable(crtc);
		3270	}
2327	Serge	3271
2330	Serge	3272	void intel_encoder_prepare (struct drm_encoder *encoder)
		3273	{
		3274	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		3275	/* lvds has its own version of prepare see intel_lvds_prepare */
		3276	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		3277	}
2327	Serge	3278
2330	Serge	3279	void intel_encoder_commit (struct drm_encoder *encoder)
		3280	{
		3281	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		3282	/* lvds has its own version of commit see intel_lvds_commit */
		3283	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		3284	}
2327	Serge	3285
2330	Serge	3286	void intel_encoder_destroy(struct drm_encoder *encoder)
		3287	{
		3288	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		3289
		3290	drm_encoder_cleanup(encoder);
		3291	kfree(intel_encoder);
		3292	}
		3293
		3294	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
		3295	struct drm_display_mode *mode,
		3296	struct drm_display_mode *adjusted_mode)
		3297	{
		3298	struct drm_device *dev = crtc->dev;
		3299
		3300	if (HAS_PCH_SPLIT(dev)) {
		3301	/* FDI link clock is fixed at 2.7G */
		3302	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
		3303	return false;
		3304	}
		3305
		3306	/* XXX some encoders set the crtcinfo, others don't.
		3307	* Obviously we need some form of conflict resolution here...
		3308	*/
		3309	if (adjusted_mode->crtc_htotal == 0)
		3310	drm_mode_set_crtcinfo(adjusted_mode, 0);
		3311
		3312	return true;
		3313	}
		3314
2327	Serge	3315	static int i945_get_display_clock_speed(struct drm_device *dev)
		3316	{
		3317	return 400000;
		3318	}
		3319
		3320	static int i915_get_display_clock_speed(struct drm_device *dev)
		3321	{
		3322	return 333000;
		3323	}
		3324
		3325	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
		3326	{
		3327	return 200000;
		3328	}
		3329
		3330	static int i915gm_get_display_clock_speed(struct drm_device *dev)
		3331	{
		3332	u16 gcfgc = 0;
		3333
		3334	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
		3335
		3336	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		3337	return 133000;
		3338	else {
		3339	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		3340	case GC_DISPLAY_CLOCK_333_MHZ:
		3341	return 333000;
		3342	default:
		3343	case GC_DISPLAY_CLOCK_190_200_MHZ:
		3344	return 190000;
		3345	}
		3346	}
		3347	}
		3348
		3349	static int i865_get_display_clock_speed(struct drm_device *dev)
		3350	{
		3351	return 266000;
		3352	}
		3353
		3354	static int i855_get_display_clock_speed(struct drm_device *dev)
		3355	{
		3356	u16 hpllcc = 0;
		3357	/* Assume that the hardware is in the high speed state. This
		3358	* should be the default.
		3359	*/
		3360	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
		3361	case GC_CLOCK_133_200:
		3362	case GC_CLOCK_100_200:
		3363	return 200000;
		3364	case GC_CLOCK_166_250:
		3365	return 250000;
		3366	case GC_CLOCK_100_133:
		3367	return 133000;
		3368	}
		3369
		3370	/* Shouldn't happen */
		3371	return 0;
		3372	}
		3373
		3374	static int i830_get_display_clock_speed(struct drm_device *dev)
		3375	{
		3376	return 133000;
		3377	}
		3378
		3379	struct fdi_m_n {
		3380	u32 tu;
		3381	u32 gmch_m;
		3382	u32 gmch_n;
		3383	u32 link_m;
		3384	u32 link_n;
		3385	};
		3386
		3387	static void
		3388	fdi_reduce_ratio(u32 num, u32 den)
		3389	{
		3390	while (num > 0xffffff \|\| den > 0xffffff) {
		3391	*num >>= 1;
		3392	*den >>= 1;
		3393	}
		3394	}
		3395
		3396	static void
		3397	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		3398	int link_clock, struct fdi_m_n *m_n)
		3399	{
		3400	m_n->tu = 64; /* default size */
		3401
		3402	/* BUG_ON(pixel_clock > INT_MAX / 36); */
		3403	m_n->gmch_m = bits_per_pixel * pixel_clock;
		3404	m_n->gmch_n = link_clock * nlanes * 8;
		3405	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
		3406
		3407	m_n->link_m = pixel_clock;
		3408	m_n->link_n = link_clock;
		3409	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
		3410	}
		3411
		3412
		3413	struct intel_watermark_params {
		3414	unsigned long fifo_size;
		3415	unsigned long max_wm;
		3416	unsigned long default_wm;
		3417	unsigned long guard_size;
		3418	unsigned long cacheline_size;
		3419	};
		3420
		3421	/* Pineview has different values for various configs */
		3422	static const struct intel_watermark_params pineview_display_wm = {
		3423	PINEVIEW_DISPLAY_FIFO,
		3424	PINEVIEW_MAX_WM,
		3425	PINEVIEW_DFT_WM,
		3426	PINEVIEW_GUARD_WM,
		3427	PINEVIEW_FIFO_LINE_SIZE
		3428	};
		3429	static const struct intel_watermark_params pineview_display_hplloff_wm = {
		3430	PINEVIEW_DISPLAY_FIFO,
		3431	PINEVIEW_MAX_WM,
		3432	PINEVIEW_DFT_HPLLOFF_WM,
		3433	PINEVIEW_GUARD_WM,
		3434	PINEVIEW_FIFO_LINE_SIZE
		3435	};
		3436	static const struct intel_watermark_params pineview_cursor_wm = {
		3437	PINEVIEW_CURSOR_FIFO,
		3438	PINEVIEW_CURSOR_MAX_WM,
		3439	PINEVIEW_CURSOR_DFT_WM,
		3440	PINEVIEW_CURSOR_GUARD_WM,
		3441	PINEVIEW_FIFO_LINE_SIZE,
		3442	};
		3443	static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
		3444	PINEVIEW_CURSOR_FIFO,
		3445	PINEVIEW_CURSOR_MAX_WM,
		3446	PINEVIEW_CURSOR_DFT_WM,
		3447	PINEVIEW_CURSOR_GUARD_WM,
		3448	PINEVIEW_FIFO_LINE_SIZE
		3449	};
		3450	static const struct intel_watermark_params g4x_wm_info = {
		3451	G4X_FIFO_SIZE,
		3452	G4X_MAX_WM,
		3453	G4X_MAX_WM,
		3454	2,
		3455	G4X_FIFO_LINE_SIZE,
		3456	};
		3457	static const struct intel_watermark_params g4x_cursor_wm_info = {
		3458	I965_CURSOR_FIFO,
		3459	I965_CURSOR_MAX_WM,
		3460	I965_CURSOR_DFT_WM,
		3461	2,
		3462	G4X_FIFO_LINE_SIZE,
		3463	};
		3464	static const struct intel_watermark_params i965_cursor_wm_info = {
		3465	I965_CURSOR_FIFO,
		3466	I965_CURSOR_MAX_WM,
		3467	I965_CURSOR_DFT_WM,
		3468	2,
		3469	I915_FIFO_LINE_SIZE,
		3470	};
		3471	static const struct intel_watermark_params i945_wm_info = {
		3472	I945_FIFO_SIZE,
		3473	I915_MAX_WM,
		3474	1,
		3475	2,
		3476	I915_FIFO_LINE_SIZE
		3477	};
		3478	static const struct intel_watermark_params i915_wm_info = {
		3479	I915_FIFO_SIZE,
		3480	I915_MAX_WM,
		3481	1,
		3482	2,
		3483	I915_FIFO_LINE_SIZE
		3484	};
		3485	static const struct intel_watermark_params i855_wm_info = {
		3486	I855GM_FIFO_SIZE,
		3487	I915_MAX_WM,
		3488	1,
		3489	2,
		3490	I830_FIFO_LINE_SIZE
		3491	};
		3492	static const struct intel_watermark_params i830_wm_info = {
		3493	I830_FIFO_SIZE,
		3494	I915_MAX_WM,
		3495	1,
		3496	2,
		3497	I830_FIFO_LINE_SIZE
		3498	};
		3499
		3500	static const struct intel_watermark_params ironlake_display_wm_info = {
		3501	ILK_DISPLAY_FIFO,
		3502	ILK_DISPLAY_MAXWM,
		3503	ILK_DISPLAY_DFTWM,
		3504	2,
		3505	ILK_FIFO_LINE_SIZE
		3506	};
		3507	static const struct intel_watermark_params ironlake_cursor_wm_info = {
		3508	ILK_CURSOR_FIFO,
		3509	ILK_CURSOR_MAXWM,
		3510	ILK_CURSOR_DFTWM,
		3511	2,
		3512	ILK_FIFO_LINE_SIZE
		3513	};
		3514	static const struct intel_watermark_params ironlake_display_srwm_info = {
		3515	ILK_DISPLAY_SR_FIFO,
		3516	ILK_DISPLAY_MAX_SRWM,
		3517	ILK_DISPLAY_DFT_SRWM,
		3518	2,
		3519	ILK_FIFO_LINE_SIZE
		3520	};
		3521	static const struct intel_watermark_params ironlake_cursor_srwm_info = {
		3522	ILK_CURSOR_SR_FIFO,
		3523	ILK_CURSOR_MAX_SRWM,
		3524	ILK_CURSOR_DFT_SRWM,
		3525	2,
		3526	ILK_FIFO_LINE_SIZE
		3527	};
		3528
		3529	static const struct intel_watermark_params sandybridge_display_wm_info = {
		3530	SNB_DISPLAY_FIFO,
		3531	SNB_DISPLAY_MAXWM,
		3532	SNB_DISPLAY_DFTWM,
		3533	2,
		3534	SNB_FIFO_LINE_SIZE
		3535	};
		3536	static const struct intel_watermark_params sandybridge_cursor_wm_info = {
		3537	SNB_CURSOR_FIFO,
		3538	SNB_CURSOR_MAXWM,
		3539	SNB_CURSOR_DFTWM,
		3540	2,
		3541	SNB_FIFO_LINE_SIZE
		3542	};
		3543	static const struct intel_watermark_params sandybridge_display_srwm_info = {
		3544	SNB_DISPLAY_SR_FIFO,
		3545	SNB_DISPLAY_MAX_SRWM,
		3546	SNB_DISPLAY_DFT_SRWM,
		3547	2,
		3548	SNB_FIFO_LINE_SIZE
		3549	};
		3550	static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
		3551	SNB_CURSOR_SR_FIFO,
		3552	SNB_CURSOR_MAX_SRWM,
		3553	SNB_CURSOR_DFT_SRWM,
		3554	2,
		3555	SNB_FIFO_LINE_SIZE
		3556	};
		3557
		3558
		3559	/**
		3560	* intel_calculate_wm - calculate watermark level
		3561	* @clock_in_khz: pixel clock
		3562	* @wm: chip FIFO params
		3563	* @pixel_size: display pixel size
		3564	* @latency_ns: memory latency for the platform
		3565	*
		3566	* Calculate the watermark level (the level at which the display plane will
		3567	* start fetching from memory again). Each chip has a different display
		3568	* FIFO size and allocation, so the caller needs to figure that out and pass
		3569	* in the correct intel_watermark_params structure.
		3570	*
		3571	* As the pixel clock runs, the FIFO will be drained at a rate that depends
		3572	* on the pixel size. When it reaches the watermark level, it'll start
		3573	* fetching FIFO line sized based chunks from memory until the FIFO fills
		3574	* past the watermark point. If the FIFO drains completely, a FIFO underrun
		3575	* will occur, and a display engine hang could result.
		3576	*/
		3577	static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
		3578	const struct intel_watermark_params *wm,
		3579	int fifo_size,
		3580	int pixel_size,
		3581	unsigned long latency_ns)
		3582	{
		3583	long entries_required, wm_size;
		3584
		3585	/*
		3586	* Note: we need to make sure we don't overflow for various clock &
		3587	* latency values.
		3588	* clocks go from a few thousand to several hundred thousand.
		3589	* latency is usually a few thousand
		3590	*/
		3591	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
		3592	1000;
		3593	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
		3594
		3595	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
		3596
		3597	wm_size = fifo_size - (entries_required + wm->guard_size);
		3598
		3599	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
		3600
		3601	/* Don't promote wm_size to unsigned... */
		3602	if (wm_size > (long)wm->max_wm)
		3603	wm_size = wm->max_wm;
		3604	if (wm_size <= 0)
		3605	wm_size = wm->default_wm;
		3606	return wm_size;
		3607	}
		3608
		3609	struct cxsr_latency {
		3610	int is_desktop;
		3611	int is_ddr3;
		3612	unsigned long fsb_freq;
		3613	unsigned long mem_freq;
		3614	unsigned long display_sr;
		3615	unsigned long display_hpll_disable;
		3616	unsigned long cursor_sr;
		3617	unsigned long cursor_hpll_disable;
		3618	};
		3619
		3620	static const struct cxsr_latency cxsr_latency_table[] = {
		3621	{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
		3622	{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
		3623	{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
		3624	{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
		3625	{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
		3626
		3627	{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
		3628	{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
		3629	{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
		3630	{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
		3631	{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
		3632
		3633	{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
		3634	{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
		3635	{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
		3636	{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
		3637	{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
		3638
		3639	{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
		3640	{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
		3641	{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
		3642	{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
		3643	{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
		3644
		3645	{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
		3646	{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
		3647	{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
		3648	{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
		3649	{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
		3650
		3651	{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
		3652	{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
		3653	{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
		3654	{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
		3655	{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
		3656	};
		3657
		3658	static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
		3659	int is_ddr3,
		3660	int fsb,
		3661	int mem)
		3662	{
		3663	const struct cxsr_latency *latency;
		3664	int i;
		3665
		3666	if (fsb == 0 \|\| mem == 0)
		3667	return NULL;
		3668
		3669	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
		3670	latency = &cxsr_latency_table[i];
		3671	if (is_desktop == latency->is_desktop &&
		3672	is_ddr3 == latency->is_ddr3 &&
		3673	fsb == latency->fsb_freq && mem == latency->mem_freq)
		3674	return latency;
		3675	}
		3676
		3677	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		3678
		3679	return NULL;
		3680	}
		3681
		3682	static void pineview_disable_cxsr(struct drm_device *dev)
		3683	{
		3684	struct drm_i915_private *dev_priv = dev->dev_private;
		3685
		3686	/* deactivate cxsr */
		3687	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
		3688	}
		3689
		3690	/*
		3691	* Latency for FIFO fetches is dependent on several factors:
		3692	* - memory configuration (speed, channels)
		3693	* - chipset
		3694	* - current MCH state
		3695	* It can be fairly high in some situations, so here we assume a fairly
		3696	* pessimal value. It's a tradeoff between extra memory fetches (if we
		3697	* set this value too high, the FIFO will fetch frequently to stay full)
		3698	* and power consumption (set it too low to save power and we might see
		3699	* FIFO underruns and display "flicker").
		3700	*
		3701	* A value of 5us seems to be a good balance; safe for very low end
		3702	* platforms but not overly aggressive on lower latency configs.
		3703	*/
		3704	static const int latency_ns = 5000;
		3705
		3706	static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
		3707	{
		3708	struct drm_i915_private *dev_priv = dev->dev_private;
		3709	uint32_t dsparb = I915_READ(DSPARB);
		3710	int size;
		3711
		3712	size = dsparb & 0x7f;
		3713	if (plane)
		3714	size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
		3715
		3716	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3717	plane ? "B" : "A", size);
		3718
		3719	return size;
		3720	}
		3721
		3722	static int i85x_get_fifo_size(struct drm_device *dev, int plane)
		3723	{
		3724	struct drm_i915_private *dev_priv = dev->dev_private;
		3725	uint32_t dsparb = I915_READ(DSPARB);
		3726	int size;
		3727
		3728	size = dsparb & 0x1ff;
		3729	if (plane)
		3730	size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
		3731	size >>= 1; /* Convert to cachelines */
		3732
		3733	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3734	plane ? "B" : "A", size);
		3735
		3736	return size;
		3737	}
		3738
		3739	static int i845_get_fifo_size(struct drm_device *dev, int plane)
		3740	{
		3741	struct drm_i915_private *dev_priv = dev->dev_private;
		3742	uint32_t dsparb = I915_READ(DSPARB);
		3743	int size;
		3744
		3745	size = dsparb & 0x7f;
		3746	size >>= 2; /* Convert to cachelines */
		3747
		3748	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3749	plane ? "B" : "A",
		3750	size);
		3751
		3752	return size;
		3753	}
		3754
		3755	static int i830_get_fifo_size(struct drm_device *dev, int plane)
		3756	{
		3757	struct drm_i915_private *dev_priv = dev->dev_private;
		3758	uint32_t dsparb = I915_READ(DSPARB);
		3759	int size;
		3760
		3761	size = dsparb & 0x7f;
		3762	size >>= 1; /* Convert to cachelines */
		3763
		3764	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		3765	plane ? "B" : "A", size);
		3766
		3767	return size;
		3768	}
		3769
		3770	static struct drm_crtc single_enabled_crtc(struct drm_device dev)
		3771	{
		3772	struct drm_crtc crtc, enabled = NULL;
		3773
		3774	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		3775	if (crtc->enabled && crtc->fb) {
		3776	if (enabled)
		3777	return NULL;
		3778	enabled = crtc;
		3779	}
		3780	}
		3781
		3782	return enabled;
		3783	}
		3784
		3785	static void pineview_update_wm(struct drm_device *dev)
		3786	{
		3787	struct drm_i915_private *dev_priv = dev->dev_private;
		3788	struct drm_crtc *crtc;
		3789	const struct cxsr_latency *latency;
		3790	u32 reg;
		3791	unsigned long wm;
		3792
		3793	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
		3794	dev_priv->fsb_freq, dev_priv->mem_freq);
		3795	if (!latency) {
		3796	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		3797	pineview_disable_cxsr(dev);
		3798	return;
		3799	}
		3800
		3801	crtc = single_enabled_crtc(dev);
		3802	if (crtc) {
		3803	int clock = crtc->mode.clock;
		3804	int pixel_size = crtc->fb->bits_per_pixel / 8;
		3805
		3806	/* Display SR */
		3807	wm = intel_calculate_wm(clock, &pineview_display_wm,
		3808	pineview_display_wm.fifo_size,
		3809	pixel_size, latency->display_sr);
		3810	reg = I915_READ(DSPFW1);
		3811	reg &= ~DSPFW_SR_MASK;
		3812	reg \|= wm << DSPFW_SR_SHIFT;
		3813	I915_WRITE(DSPFW1, reg);
		3814	DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
		3815
		3816	/* cursor SR */
		3817	wm = intel_calculate_wm(clock, &pineview_cursor_wm,
		3818	pineview_display_wm.fifo_size,
		3819	pixel_size, latency->cursor_sr);
		3820	reg = I915_READ(DSPFW3);
		3821	reg &= ~DSPFW_CURSOR_SR_MASK;
		3822	reg \|= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
		3823	I915_WRITE(DSPFW3, reg);
		3824
		3825	/* Display HPLL off SR */
		3826	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
		3827	pineview_display_hplloff_wm.fifo_size,
		3828	pixel_size, latency->display_hpll_disable);
		3829	reg = I915_READ(DSPFW3);
		3830	reg &= ~DSPFW_HPLL_SR_MASK;
		3831	reg \|= wm & DSPFW_HPLL_SR_MASK;
		3832	I915_WRITE(DSPFW3, reg);
		3833
		3834	/* cursor HPLL off SR */
		3835	wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
		3836	pineview_display_hplloff_wm.fifo_size,
		3837	pixel_size, latency->cursor_hpll_disable);
		3838	reg = I915_READ(DSPFW3);
		3839	reg &= ~DSPFW_HPLL_CURSOR_MASK;
		3840	reg \|= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
		3841	I915_WRITE(DSPFW3, reg);
		3842	DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
		3843
		3844	/* activate cxsr */
		3845	I915_WRITE(DSPFW3,
		3846	I915_READ(DSPFW3) \| PINEVIEW_SELF_REFRESH_EN);
		3847	DRM_DEBUG_KMS("Self-refresh is enabled\n");
		3848	} else {
		3849	pineview_disable_cxsr(dev);
		3850	DRM_DEBUG_KMS("Self-refresh is disabled\n");
		3851	}
		3852	}
		3853
		3854	static bool g4x_compute_wm0(struct drm_device *dev,
		3855	int plane,
		3856	const struct intel_watermark_params *display,
		3857	int display_latency_ns,
		3858	const struct intel_watermark_params *cursor,
		3859	int cursor_latency_ns,
		3860	int *plane_wm,
		3861	int *cursor_wm)
		3862	{
		3863	struct drm_crtc *crtc;
		3864	int htotal, hdisplay, clock, pixel_size;
		3865	int line_time_us, line_count;
		3866	int entries, tlb_miss;
		3867
		3868	crtc = intel_get_crtc_for_plane(dev, plane);
		3869	if (crtc->fb == NULL \|\| !crtc->enabled) {
		3870	*cursor_wm = cursor->guard_size;
		3871	*plane_wm = display->guard_size;
		3872	return false;
		3873	}
		3874
		3875	htotal = crtc->mode.htotal;
		3876	hdisplay = crtc->mode.hdisplay;
		3877	clock = crtc->mode.clock;
		3878	pixel_size = crtc->fb->bits_per_pixel / 8;
		3879
		3880	/* Use the small buffer method to calculate plane watermark */
		3881	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
		3882	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;
		3883	if (tlb_miss > 0)
		3884	entries += tlb_miss;
		3885	entries = DIV_ROUND_UP(entries, display->cacheline_size);
		3886	*plane_wm = entries + display->guard_size;
		3887	if (*plane_wm > (int)display->max_wm)
		3888	*plane_wm = display->max_wm;
		3889
		3890	/* Use the large buffer method to calculate cursor watermark */
		3891	line_time_us = ((htotal * 1000) / clock);
		3892	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
		3893	entries = line_count * 64 * pixel_size;
		3894	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;
		3895	if (tlb_miss > 0)
		3896	entries += tlb_miss;
		3897	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		3898	*cursor_wm = entries + cursor->guard_size;
		3899	if (*cursor_wm > (int)cursor->max_wm)
		3900	*cursor_wm = (int)cursor->max_wm;
		3901
		3902	return true;
		3903	}
		3904
		3905	/*
		3906	* Check the wm result.
		3907	*
		3908	* If any calculated watermark values is larger than the maximum value that
		3909	* can be programmed into the associated watermark register, that watermark
		3910	* must be disabled.
		3911	*/
		3912	static bool g4x_check_srwm(struct drm_device *dev,
		3913	int display_wm, int cursor_wm,
		3914	const struct intel_watermark_params *display,
		3915	const struct intel_watermark_params *cursor)
		3916	{
		3917	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
		3918	display_wm, cursor_wm);
		3919
		3920	if (display_wm > display->max_wm) {
		3921	DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
		3922	display_wm, display->max_wm);
		3923	return false;
		3924	}
		3925
		3926	if (cursor_wm > cursor->max_wm) {
		3927	DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
		3928	cursor_wm, cursor->max_wm);
		3929	return false;
		3930	}
		3931
		3932	if (!(display_wm \|\| cursor_wm)) {
		3933	DRM_DEBUG_KMS("SR latency is 0, disabling\n");
		3934	return false;
		3935	}
		3936
		3937	return true;
		3938	}
		3939
		3940	static bool g4x_compute_srwm(struct drm_device *dev,
		3941	int plane,
		3942	int latency_ns,
		3943	const struct intel_watermark_params *display,
		3944	const struct intel_watermark_params *cursor,
		3945	int display_wm, int cursor_wm)
		3946	{
		3947	struct drm_crtc *crtc;
		3948	int hdisplay, htotal, pixel_size, clock;
		3949	unsigned long line_time_us;
		3950	int line_count, line_size;
		3951	int small, large;
		3952	int entries;
		3953
		3954	if (!latency_ns) {
		3955	display_wm = cursor_wm = 0;
		3956	return false;
		3957	}
		3958
		3959	crtc = intel_get_crtc_for_plane(dev, plane);
		3960	hdisplay = crtc->mode.hdisplay;
		3961	htotal = crtc->mode.htotal;
		3962	clock = crtc->mode.clock;
		3963	pixel_size = crtc->fb->bits_per_pixel / 8;
		3964
		3965	line_time_us = (htotal * 1000) / clock;
		3966	line_count = (latency_ns / line_time_us + 1000) / 1000;
		3967	line_size = hdisplay * pixel_size;
		3968
		3969	/* Use the minimum of the small and large buffer method for primary */
		3970	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
		3971	large = line_count * line_size;
		3972
		3973	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
		3974	*display_wm = entries + display->guard_size;
		3975
		3976	/* calculate the self-refresh watermark for display cursor */
		3977	entries = line_count * pixel_size * 64;
		3978	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		3979	*cursor_wm = entries + cursor->guard_size;
		3980
		3981	return g4x_check_srwm(dev,
		3982	display_wm, cursor_wm,
		3983	display, cursor);
		3984	}
		3985
		3986	#define single_plane_enabled(mask) is_power_of_2(mask)
		3987
		3988	static void g4x_update_wm(struct drm_device *dev)
		3989	{
		3990	static const int sr_latency_ns = 12000;
		3991	struct drm_i915_private *dev_priv = dev->dev_private;
		3992	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
		3993	int plane_sr, cursor_sr;
		3994	unsigned int enabled = 0;
		3995
		3996	if (g4x_compute_wm0(dev, 0,
		3997	&g4x_wm_info, latency_ns,
		3998	&g4x_cursor_wm_info, latency_ns,
		3999	&planea_wm, &cursora_wm))
		4000	enabled \|= 1;
		4001
		4002	if (g4x_compute_wm0(dev, 1,
		4003	&g4x_wm_info, latency_ns,
		4004	&g4x_cursor_wm_info, latency_ns,
		4005	&planeb_wm, &cursorb_wm))
		4006	enabled \|= 2;
		4007
		4008	plane_sr = cursor_sr = 0;
		4009	if (single_plane_enabled(enabled) &&
		4010	g4x_compute_srwm(dev, ffs(enabled) - 1,
		4011	sr_latency_ns,
		4012	&g4x_wm_info,
		4013	&g4x_cursor_wm_info,
		4014	&plane_sr, &cursor_sr))
		4015	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
		4016	else
		4017	I915_WRITE(FW_BLC_SELF,
		4018	I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
		4019
		4020	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
		4021	planea_wm, cursora_wm,
		4022	planeb_wm, cursorb_wm,
		4023	plane_sr, cursor_sr);
		4024
		4025	I915_WRITE(DSPFW1,
		4026	(plane_sr << DSPFW_SR_SHIFT) \|
		4027	(cursorb_wm << DSPFW_CURSORB_SHIFT) \|
		4028	(planeb_wm << DSPFW_PLANEB_SHIFT) \|
		4029	planea_wm);
		4030	I915_WRITE(DSPFW2,
		4031	(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) \|
		4032	(cursora_wm << DSPFW_CURSORA_SHIFT));
		4033	/* HPLL off in SR has some issues on G4x... disable it */
		4034	I915_WRITE(DSPFW3,
		4035	(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) \|
		4036	(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
		4037	}
		4038
		4039	static void i965_update_wm(struct drm_device *dev)
		4040	{
		4041	struct drm_i915_private *dev_priv = dev->dev_private;
		4042	struct drm_crtc *crtc;
		4043	int srwm = 1;
		4044	int cursor_sr = 16;
		4045
		4046	/* Calc sr entries for one plane configs */
		4047	crtc = single_enabled_crtc(dev);
		4048	if (crtc) {
		4049	/* self-refresh has much higher latency */
		4050	static const int sr_latency_ns = 12000;
		4051	int clock = crtc->mode.clock;
		4052	int htotal = crtc->mode.htotal;
		4053	int hdisplay = crtc->mode.hdisplay;
		4054	int pixel_size = crtc->fb->bits_per_pixel / 8;
		4055	unsigned long line_time_us;
		4056	int entries;
		4057
		4058	line_time_us = ((htotal * 1000) / clock);
		4059
		4060	/* Use ns/us then divide to preserve precision */
		4061	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4062	pixel_size * hdisplay;
		4063	entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
		4064	srwm = I965_FIFO_SIZE - entries;
		4065	if (srwm < 0)
		4066	srwm = 1;
		4067	srwm &= 0x1ff;
		4068	DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
		4069	entries, srwm);
		4070
		4071	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4072	pixel_size * 64;
		4073	entries = DIV_ROUND_UP(entries,
		4074	i965_cursor_wm_info.cacheline_size);
		4075	cursor_sr = i965_cursor_wm_info.fifo_size -
		4076	(entries + i965_cursor_wm_info.guard_size);
		4077
		4078	if (cursor_sr > i965_cursor_wm_info.max_wm)
		4079	cursor_sr = i965_cursor_wm_info.max_wm;
		4080
		4081	DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
		4082	"cursor %d\n", srwm, cursor_sr);
		4083
		4084	if (IS_CRESTLINE(dev))
		4085	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
		4086	} else {
		4087	/* Turn off self refresh if both pipes are enabled */
		4088	if (IS_CRESTLINE(dev))
		4089	I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
		4090	& ~FW_BLC_SELF_EN);
		4091	}
		4092
		4093	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
		4094	srwm);
		4095
		4096	/* 965 has limitations... */
		4097	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) \|
		4098	(8 << 16) \| (8 << 8) \| (8 << 0));
		4099	I915_WRITE(DSPFW2, (8 << 8) \| (8 << 0));
		4100	/* update cursor SR watermark */
		4101	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
		4102	}
		4103
		4104	static void i9xx_update_wm(struct drm_device *dev)
		4105	{
		4106	struct drm_i915_private *dev_priv = dev->dev_private;
		4107	const struct intel_watermark_params *wm_info;
		4108	uint32_t fwater_lo;
		4109	uint32_t fwater_hi;
		4110	int cwm, srwm = 1;
		4111	int fifo_size;
		4112	int planea_wm, planeb_wm;
		4113	struct drm_crtc crtc, enabled = NULL;
		4114
		4115	if (IS_I945GM(dev))
		4116	wm_info = &i945_wm_info;
		4117	else if (!IS_GEN2(dev))
		4118	wm_info = &i915_wm_info;
		4119	else
		4120	wm_info = &i855_wm_info;
		4121
		4122	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
		4123	crtc = intel_get_crtc_for_plane(dev, 0);
		4124	if (crtc->enabled && crtc->fb) {
		4125	planea_wm = intel_calculate_wm(crtc->mode.clock,
		4126	wm_info, fifo_size,
		4127	crtc->fb->bits_per_pixel / 8,
		4128	latency_ns);
		4129	enabled = crtc;
		4130	} else
		4131	planea_wm = fifo_size - wm_info->guard_size;
		4132
		4133	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
		4134	crtc = intel_get_crtc_for_plane(dev, 1);
		4135	if (crtc->enabled && crtc->fb) {
		4136	planeb_wm = intel_calculate_wm(crtc->mode.clock,
		4137	wm_info, fifo_size,
		4138	crtc->fb->bits_per_pixel / 8,
		4139	latency_ns);
		4140	if (enabled == NULL)
		4141	enabled = crtc;
		4142	else
		4143	enabled = NULL;
		4144	} else
		4145	planeb_wm = fifo_size - wm_info->guard_size;
		4146
		4147	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
		4148
		4149	/*
		4150	* Overlay gets an aggressive default since video jitter is bad.
		4151	*/
		4152	cwm = 2;
		4153
		4154	/* Play safe and disable self-refresh before adjusting watermarks. */
		4155	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4156	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK \| 0);
		4157	else if (IS_I915GM(dev))
		4158	I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
		4159
		4160	/* Calc sr entries for one plane configs */
		4161	if (HAS_FW_BLC(dev) && enabled) {
		4162	/* self-refresh has much higher latency */
		4163	static const int sr_latency_ns = 6000;
		4164	int clock = enabled->mode.clock;
		4165	int htotal = enabled->mode.htotal;
		4166	int hdisplay = enabled->mode.hdisplay;
		4167	int pixel_size = enabled->fb->bits_per_pixel / 8;
		4168	unsigned long line_time_us;
		4169	int entries;
		4170
		4171	line_time_us = (htotal * 1000) / clock;
		4172
		4173	/* Use ns/us then divide to preserve precision */
		4174	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
		4175	pixel_size * hdisplay;
		4176	entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
		4177	DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
		4178	srwm = wm_info->fifo_size - entries;
		4179	if (srwm < 0)
		4180	srwm = 1;
		4181
		4182	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4183	I915_WRITE(FW_BLC_SELF,
		4184	FW_BLC_SELF_FIFO_MASK \| (srwm & 0xff));
		4185	else if (IS_I915GM(dev))
		4186	I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
		4187	}
		4188
		4189	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
		4190	planea_wm, planeb_wm, cwm, srwm);
		4191
		4192	fwater_lo = ((planeb_wm & 0x3f) << 16) \| (planea_wm & 0x3f);
		4193	fwater_hi = (cwm & 0x1f);
		4194
		4195	/* Set request length to 8 cachelines per fetch */
		4196	fwater_lo = fwater_lo \| (1 << 24) \| (1 << 8);
		4197	fwater_hi = fwater_hi \| (1 << 8);
		4198
		4199	I915_WRITE(FW_BLC, fwater_lo);
		4200	I915_WRITE(FW_BLC2, fwater_hi);
		4201
		4202	if (HAS_FW_BLC(dev)) {
		4203	if (enabled) {
		4204	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		4205	I915_WRITE(FW_BLC_SELF,
		4206	FW_BLC_SELF_EN_MASK \| FW_BLC_SELF_EN);
		4207	else if (IS_I915GM(dev))
		4208	I915_WRITE(INSTPM, I915_READ(INSTPM) \| INSTPM_SELF_EN);
		4209	DRM_DEBUG_KMS("memory self refresh enabled\n");
		4210	} else
		4211	DRM_DEBUG_KMS("memory self refresh disabled\n");
		4212	}
		4213	}
		4214
		4215	static void i830_update_wm(struct drm_device *dev)
		4216	{
		4217	struct drm_i915_private *dev_priv = dev->dev_private;
		4218	struct drm_crtc *crtc;
		4219	uint32_t fwater_lo;
		4220	int planea_wm;
		4221
		4222	crtc = single_enabled_crtc(dev);
		4223	if (crtc == NULL)
		4224	return;
		4225
		4226	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
		4227	dev_priv->display.get_fifo_size(dev, 0),
		4228	crtc->fb->bits_per_pixel / 8,
		4229	latency_ns);
		4230	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
		4231	fwater_lo \|= (3<<8) \| planea_wm;
		4232
		4233	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
		4234
		4235	I915_WRITE(FW_BLC, fwater_lo);
		4236	}
		4237
		4238	#define ILK_LP0_PLANE_LATENCY 700
		4239	#define ILK_LP0_CURSOR_LATENCY 1300
		4240
		4241	/*
		4242	* Check the wm result.
		4243	*
		4244	* If any calculated watermark values is larger than the maximum value that
		4245	* can be programmed into the associated watermark register, that watermark
		4246	* must be disabled.
		4247	*/
		4248	static bool ironlake_check_srwm(struct drm_device *dev, int level,
		4249	int fbc_wm, int display_wm, int cursor_wm,
		4250	const struct intel_watermark_params *display,
		4251	const struct intel_watermark_params *cursor)
		4252	{
		4253	struct drm_i915_private *dev_priv = dev->dev_private;
		4254
		4255	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
		4256	" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
		4257
		4258	if (fbc_wm > SNB_FBC_MAX_SRWM) {
		4259	DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
		4260	fbc_wm, SNB_FBC_MAX_SRWM, level);
		4261
		4262	/* fbc has it's own way to disable FBC WM */
		4263	I915_WRITE(DISP_ARB_CTL,
		4264	I915_READ(DISP_ARB_CTL) \| DISP_FBC_WM_DIS);
		4265	return false;
		4266	}
		4267
		4268	if (display_wm > display->max_wm) {
		4269	DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
		4270	display_wm, SNB_DISPLAY_MAX_SRWM, level);
		4271	return false;
		4272	}
		4273
		4274	if (cursor_wm > cursor->max_wm) {
		4275	DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
		4276	cursor_wm, SNB_CURSOR_MAX_SRWM, level);
		4277	return false;
		4278	}
		4279
		4280	if (!(fbc_wm \|\| display_wm \|\| cursor_wm)) {
		4281	DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
		4282	return false;
		4283	}
		4284
		4285	return true;
		4286	}
		4287
		4288	/*
		4289	* Compute watermark values of WM[1-3],
		4290	*/
		4291	static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
		4292	int latency_ns,
		4293	const struct intel_watermark_params *display,
		4294	const struct intel_watermark_params *cursor,
		4295	int fbc_wm, int display_wm, int *cursor_wm)
		4296	{
		4297	struct drm_crtc *crtc;
		4298	unsigned long line_time_us;
		4299	int hdisplay, htotal, pixel_size, clock;
		4300	int line_count, line_size;
		4301	int small, large;
		4302	int entries;
		4303
		4304	if (!latency_ns) {
		4305	fbc_wm = display_wm = *cursor_wm = 0;
		4306	return false;
		4307	}
		4308
		4309	crtc = intel_get_crtc_for_plane(dev, plane);
		4310	hdisplay = crtc->mode.hdisplay;
		4311	htotal = crtc->mode.htotal;
		4312	clock = crtc->mode.clock;
		4313	pixel_size = crtc->fb->bits_per_pixel / 8;
		4314
		4315	line_time_us = (htotal * 1000) / clock;
		4316	line_count = (latency_ns / line_time_us + 1000) / 1000;
		4317	line_size = hdisplay * pixel_size;
		4318
		4319	/* Use the minimum of the small and large buffer method for primary */
		4320	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
		4321	large = line_count * line_size;
		4322
		4323	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
		4324	*display_wm = entries + display->guard_size;
		4325
		4326	/*
		4327	* Spec says:
		4328	* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
		4329	*/
		4330	fbc_wm = DIV_ROUND_UP(display_wm * 64, line_size) + 2;
		4331
		4332	/* calculate the self-refresh watermark for display cursor */
		4333	entries = line_count * pixel_size * 64;
		4334	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
		4335	*cursor_wm = entries + cursor->guard_size;
		4336
		4337	return ironlake_check_srwm(dev, level,
		4338	fbc_wm, display_wm, *cursor_wm,
		4339	display, cursor);
		4340	}
		4341
		4342	static void ironlake_update_wm(struct drm_device *dev)
		4343	{
		4344	struct drm_i915_private *dev_priv = dev->dev_private;
		4345	int fbc_wm, plane_wm, cursor_wm;
		4346	unsigned int enabled;
		4347
		4348	enabled = 0;
		4349	if (g4x_compute_wm0(dev, 0,
		4350	&ironlake_display_wm_info,
		4351	ILK_LP0_PLANE_LATENCY,
		4352	&ironlake_cursor_wm_info,
		4353	ILK_LP0_CURSOR_LATENCY,
		4354	&plane_wm, &cursor_wm)) {
		4355	I915_WRITE(WM0_PIPEA_ILK,
		4356	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4357	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
		4358	" plane %d, " "cursor: %d\n",
		4359	plane_wm, cursor_wm);
		4360	enabled \|= 1;
		4361	}
		4362
		4363	if (g4x_compute_wm0(dev, 1,
		4364	&ironlake_display_wm_info,
		4365	ILK_LP0_PLANE_LATENCY,
		4366	&ironlake_cursor_wm_info,
		4367	ILK_LP0_CURSOR_LATENCY,
		4368	&plane_wm, &cursor_wm)) {
		4369	I915_WRITE(WM0_PIPEB_ILK,
		4370	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4371	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
		4372	" plane %d, cursor: %d\n",
		4373	plane_wm, cursor_wm);
		4374	enabled \|= 2;
		4375	}
		4376
		4377	/*
		4378	* Calculate and update the self-refresh watermark only when one
		4379	* display plane is used.
		4380	*/
		4381	I915_WRITE(WM3_LP_ILK, 0);
		4382	I915_WRITE(WM2_LP_ILK, 0);
		4383	I915_WRITE(WM1_LP_ILK, 0);
		4384
		4385	if (!single_plane_enabled(enabled))
		4386	return;
		4387	enabled = ffs(enabled) - 1;
		4388
		4389	/* WM1 */
		4390	if (!ironlake_compute_srwm(dev, 1, enabled,
		4391	ILK_READ_WM1_LATENCY() * 500,
		4392	&ironlake_display_srwm_info,
		4393	&ironlake_cursor_srwm_info,
		4394	&fbc_wm, &plane_wm, &cursor_wm))
		4395	return;
		4396
		4397	I915_WRITE(WM1_LP_ILK,
		4398	WM1_LP_SR_EN \|
		4399	(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4400	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4401	(plane_wm << WM1_LP_SR_SHIFT) \|
		4402	cursor_wm);
		4403
		4404	/* WM2 */
		4405	if (!ironlake_compute_srwm(dev, 2, enabled,
		4406	ILK_READ_WM2_LATENCY() * 500,
		4407	&ironlake_display_srwm_info,
		4408	&ironlake_cursor_srwm_info,
		4409	&fbc_wm, &plane_wm, &cursor_wm))
		4410	return;
		4411
		4412	I915_WRITE(WM2_LP_ILK,
		4413	WM2_LP_EN \|
		4414	(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4415	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4416	(plane_wm << WM1_LP_SR_SHIFT) \|
		4417	cursor_wm);
		4418
		4419	/*
		4420	* WM3 is unsupported on ILK, probably because we don't have latency
		4421	* data for that power state
		4422	*/
		4423	}
		4424
		4425	static void sandybridge_update_wm(struct drm_device *dev)
		4426	{
		4427	struct drm_i915_private *dev_priv = dev->dev_private;
		4428	int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
		4429	int fbc_wm, plane_wm, cursor_wm;
		4430	unsigned int enabled;
		4431
2336	Serge	4432	ENTER();
		4433
2327	Serge	4434	enabled = 0;
		4435	if (g4x_compute_wm0(dev, 0,
		4436	&sandybridge_display_wm_info, latency,
		4437	&sandybridge_cursor_wm_info, latency,
		4438	&plane_wm, &cursor_wm)) {
		4439	I915_WRITE(WM0_PIPEA_ILK,
		4440	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4441	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
		4442	" plane %d, " "cursor: %d\n",
		4443	plane_wm, cursor_wm);
		4444	enabled \|= 1;
		4445	}
		4446
		4447	if (g4x_compute_wm0(dev, 1,
		4448	&sandybridge_display_wm_info, latency,
		4449	&sandybridge_cursor_wm_info, latency,
		4450	&plane_wm, &cursor_wm)) {
		4451	I915_WRITE(WM0_PIPEB_ILK,
		4452	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
		4453	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
		4454	" plane %d, cursor: %d\n",
		4455	plane_wm, cursor_wm);
		4456	enabled \|= 2;
		4457	}
		4458
		4459	/*
		4460	* Calculate and update the self-refresh watermark only when one
		4461	* display plane is used.
		4462	*
		4463	* SNB support 3 levels of watermark.
		4464	*
		4465	* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
		4466	* and disabled in the descending order
		4467	*
		4468	*/
		4469	I915_WRITE(WM3_LP_ILK, 0);
		4470	I915_WRITE(WM2_LP_ILK, 0);
		4471	I915_WRITE(WM1_LP_ILK, 0);
		4472
		4473	if (!single_plane_enabled(enabled))
2336	Serge	4474	{
		4475	LEAVE();
2327	Serge	4476	return;
2336	Serge	4477	};
		4478
2327	Serge	4479	enabled = ffs(enabled) - 1;
		4480
2336	Serge	4481	dbgprintf("compute wm1\n");
		4482
2327	Serge	4483	/* WM1 */
		4484	if (!ironlake_compute_srwm(dev, 1, enabled,
		4485	SNB_READ_WM1_LATENCY() * 500,
		4486	&sandybridge_display_srwm_info,
		4487	&sandybridge_cursor_srwm_info,
		4488	&fbc_wm, &plane_wm, &cursor_wm))
		4489	return;
		4490
		4491	I915_WRITE(WM1_LP_ILK,
		4492	WM1_LP_SR_EN \|
		4493	(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4494	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4495	(plane_wm << WM1_LP_SR_SHIFT) \|
		4496	cursor_wm);
		4497
2336	Serge	4498	dbgprintf("compute wm2\n");
		4499
2327	Serge	4500	/* WM2 */
		4501	if (!ironlake_compute_srwm(dev, 2, enabled,
		4502	SNB_READ_WM2_LATENCY() * 500,
		4503	&sandybridge_display_srwm_info,
		4504	&sandybridge_cursor_srwm_info,
		4505	&fbc_wm, &plane_wm, &cursor_wm))
		4506	return;
		4507
		4508	I915_WRITE(WM2_LP_ILK,
		4509	WM2_LP_EN \|
		4510	(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4511	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4512	(plane_wm << WM1_LP_SR_SHIFT) \|
		4513	cursor_wm);
		4514
2336	Serge	4515	dbgprintf("compute wm3\n");
		4516
2327	Serge	4517	/* WM3 */
		4518	if (!ironlake_compute_srwm(dev, 3, enabled,
		4519	SNB_READ_WM3_LATENCY() * 500,
		4520	&sandybridge_display_srwm_info,
		4521	&sandybridge_cursor_srwm_info,
		4522	&fbc_wm, &plane_wm, &cursor_wm))
		4523	return;
		4524
		4525	I915_WRITE(WM3_LP_ILK,
		4526	WM3_LP_EN \|
		4527	(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
		4528	(fbc_wm << WM1_LP_FBC_SHIFT) \|
		4529	(plane_wm << WM1_LP_SR_SHIFT) \|
		4530	cursor_wm);
2336	Serge	4531
		4532	LEAVE();
		4533
2327	Serge	4534	}
		4535
		4536	/**
		4537	* intel_update_watermarks - update FIFO watermark values based on current modes
		4538	*
		4539	* Calculate watermark values for the various WM regs based on current mode
		4540	* and plane configuration.
		4541	*
		4542	* There are several cases to deal with here:
		4543	* - normal (i.e. non-self-refresh)
		4544	* - self-refresh (SR) mode
		4545	* - lines are large relative to FIFO size (buffer can hold up to 2)
		4546	* - lines are small relative to FIFO size (buffer can hold more than 2
		4547	* lines), so need to account for TLB latency
		4548	*
		4549	* The normal calculation is:
		4550	* watermark = dotclock * bytes per pixel * latency
		4551	* where latency is platform & configuration dependent (we assume pessimal
		4552	* values here).
		4553	*
		4554	* The SR calculation is:
		4555	* watermark = (trunc(latency/line time)+1) * surface width *
		4556	* bytes per pixel
		4557	* where
		4558	* line time = htotal / dotclock
		4559	* surface width = hdisplay for normal plane and 64 for cursor
		4560	* and latency is assumed to be high, as above.
		4561	*
		4562	* The final value programmed to the register should always be rounded up,
		4563	* and include an extra 2 entries to account for clock crossings.
		4564	*
		4565	* We don't use the sprite, so we can ignore that. And on Crestline we have
		4566	* to set the non-SR watermarks to 8.
		4567	*/
		4568	static void intel_update_watermarks(struct drm_device *dev)
		4569	{
		4570	struct drm_i915_private *dev_priv = dev->dev_private;
2336	Serge	4571	ENTER();
2327	Serge	4572	if (dev_priv->display.update_wm)
		4573	dev_priv->display.update_wm(dev);
2336	Serge	4574	LEAVE();
2327	Serge	4575	}
		4576
		4577	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
		4578	{
		4579	return dev_priv->lvds_use_ssc && i915_panel_use_ssc
		4580	&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
		4581	}
		4582
		4583	/**
		4584	* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
		4585	* @crtc: CRTC structure
		4586	*
		4587	* A pipe may be connected to one or more outputs. Based on the depth of the
		4588	* attached framebuffer, choose a good color depth to use on the pipe.
		4589	*
		4590	* If possible, match the pipe depth to the fb depth. In some cases, this
		4591	* isn't ideal, because the connected output supports a lesser or restricted
		4592	* set of depths. Resolve that here:
		4593	* LVDS typically supports only 6bpc, so clamp down in that case
		4594	* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
		4595	* Displays may support a restricted set as well, check EDID and clamp as
		4596	* appropriate.
		4597	*
		4598	* RETURNS:
		4599	* Dithering requirement (i.e. false if display bpc and pipe bpc match,
		4600	* true if they don't match).
		4601	*/
		4602	static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
		4603	unsigned int *pipe_bpp)
		4604	{
		4605	struct drm_device *dev = crtc->dev;
		4606	struct drm_i915_private *dev_priv = dev->dev_private;
		4607	struct drm_encoder *encoder;
		4608	struct drm_connector *connector;
		4609	unsigned int display_bpc = UINT_MAX, bpc;
		4610
		4611	/* Walk the encoders & connectors on this crtc, get min bpc */
		4612	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		4613	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
		4614
		4615	if (encoder->crtc != crtc)
		4616	continue;
		4617
		4618	if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
		4619	unsigned int lvds_bpc;
		4620
		4621	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
		4622	LVDS_A3_POWER_UP)
		4623	lvds_bpc = 8;
		4624	else
		4625	lvds_bpc = 6;
		4626
		4627	if (lvds_bpc < display_bpc) {
		4628	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
		4629	display_bpc = lvds_bpc;
		4630	}
		4631	continue;
		4632	}
		4633
		4634	if (intel_encoder->type == INTEL_OUTPUT_EDP) {
		4635	/* Use VBT settings if we have an eDP panel */
		4636	unsigned int edp_bpc = dev_priv->edp.bpp / 3;
		4637
		4638	if (edp_bpc < display_bpc) {
		4639	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
		4640	display_bpc = edp_bpc;
		4641	}
		4642	continue;
		4643	}
		4644
		4645	/* Not one of the known troublemakers, check the EDID */
		4646	list_for_each_entry(connector, &dev->mode_config.connector_list,
		4647	head) {
		4648	if (connector->encoder != encoder)
		4649	continue;
		4650
		4651	/* Don't use an invalid EDID bpc value */
		4652	if (connector->display_info.bpc &&
		4653	connector->display_info.bpc < display_bpc) {
		4654	DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
		4655	display_bpc = connector->display_info.bpc;
		4656	}
		4657	}
		4658
		4659	/*
		4660	* HDMI is either 12 or 8, so if the display lets 10bpc sneak
		4661	* through, clamp it down. (Note: >12bpc will be caught below.)
		4662	*/
		4663	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		4664	if (display_bpc > 8 && display_bpc < 12) {
		4665	DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
		4666	display_bpc = 12;
		4667	} else {
		4668	DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
		4669	display_bpc = 8;
		4670	}
		4671	}
		4672	}
		4673
		4674	/*
		4675	* We could just drive the pipe at the highest bpc all the time and
		4676	* enable dithering as needed, but that costs bandwidth. So choose
		4677	* the minimum value that expresses the full color range of the fb but
		4678	* also stays within the max display bpc discovered above.
		4679	*/
		4680
		4681	switch (crtc->fb->depth) {
		4682	case 8:
		4683	bpc = 8; /* since we go through a colormap */
		4684	break;
		4685	case 15:
		4686	case 16:
		4687	bpc = 6; /* min is 18bpp */
		4688	break;
		4689	case 24:
		4690	bpc = min((unsigned int)8, display_bpc);
		4691	break;
		4692	case 30:
		4693	bpc = min((unsigned int)10, display_bpc);
		4694	break;
		4695	case 48:
		4696	bpc = min((unsigned int)12, display_bpc);
		4697	break;
		4698	default:
		4699	DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		4700	bpc = min((unsigned int)8, display_bpc);
		4701	break;
		4702	}
		4703
		4704	DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
		4705	bpc, display_bpc);
		4706
		4707	pipe_bpp = bpc 3;
		4708
		4709	return display_bpc != bpc;
		4710	}
		4711
		4712	static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
		4713	struct drm_display_mode *mode,
		4714	struct drm_display_mode *adjusted_mode,
		4715	int x, int y,
		4716	struct drm_framebuffer *old_fb)
		4717	{
		4718	struct drm_device *dev = crtc->dev;
		4719	struct drm_i915_private *dev_priv = dev->dev_private;
		4720	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		4721	int pipe = intel_crtc->pipe;
		4722	int plane = intel_crtc->plane;
		4723	int refclk, num_connectors = 0;
		4724	intel_clock_t clock, reduced_clock;
		4725	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
		4726	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
		4727	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
		4728	struct drm_mode_config *mode_config = &dev->mode_config;
		4729	struct intel_encoder *encoder;
		4730	const intel_limit_t *limit;
		4731	int ret;
		4732	u32 temp;
		4733	u32 lvds_sync = 0;
		4734
		4735	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		4736	if (encoder->base.crtc != crtc)
		4737	continue;
		4738
		4739	switch (encoder->type) {
		4740	case INTEL_OUTPUT_LVDS:
		4741	is_lvds = true;
		4742	break;
		4743	case INTEL_OUTPUT_SDVO:
		4744	case INTEL_OUTPUT_HDMI:
		4745	is_sdvo = true;
		4746	if (encoder->needs_tv_clock)
		4747	is_tv = true;
		4748	break;
		4749	case INTEL_OUTPUT_DVO:
		4750	is_dvo = true;
		4751	break;
		4752	case INTEL_OUTPUT_TVOUT:
		4753	is_tv = true;
		4754	break;
		4755	case INTEL_OUTPUT_ANALOG:
		4756	is_crt = true;
		4757	break;
		4758	case INTEL_OUTPUT_DISPLAYPORT:
		4759	is_dp = true;
		4760	break;
		4761	}
		4762
		4763	num_connectors++;
		4764	}
		4765
		4766	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		4767	refclk = dev_priv->lvds_ssc_freq * 1000;
		4768	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		4769	refclk / 1000);
		4770	} else if (!IS_GEN2(dev)) {
		4771	refclk = 96000;
		4772	} else {
		4773	refclk = 48000;
		4774	}
		4775
		4776	/*
		4777	* Returns a set of divisors for the desired target clock with the given
		4778	* refclk, or FALSE. The returned values represent the clock equation:
		4779	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		4780	*/
		4781	limit = intel_limit(crtc, refclk);
		4782	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
		4783	if (!ok) {
		4784	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		4785	return -EINVAL;
		4786	}
		4787
		4788	/* Ensure that the cursor is valid for the new mode before changing... */
		4789	// intel_crtc_update_cursor(crtc, true);
		4790
		4791	if (is_lvds && dev_priv->lvds_downclock_avail) {
		4792	has_reduced_clock = limit->find_pll(limit, crtc,
		4793	dev_priv->lvds_downclock,
		4794	refclk,
		4795	&reduced_clock);
		4796	if (has_reduced_clock && (clock.p != reduced_clock.p)) {
		4797	/*
		4798	* If the different P is found, it means that we can't
		4799	* switch the display clock by using the FP0/FP1.
		4800	* In such case we will disable the LVDS downclock
		4801	* feature.
		4802	*/
		4803	DRM_DEBUG_KMS("Different P is found for "
		4804	"LVDS clock/downclock\n");
		4805	has_reduced_clock = 0;
		4806	}
		4807	}
		4808	/* SDVO TV has fixed PLL values depend on its clock range,
		4809	this mirrors vbios setting. */
		4810	if (is_sdvo && is_tv) {
		4811	if (adjusted_mode->clock >= 100000
		4812	&& adjusted_mode->clock < 140500) {
		4813	clock.p1 = 2;
		4814	clock.p2 = 10;
		4815	clock.n = 3;
		4816	clock.m1 = 16;
		4817	clock.m2 = 8;
		4818	} else if (adjusted_mode->clock >= 140500
		4819	&& adjusted_mode->clock <= 200000) {
		4820	clock.p1 = 1;
		4821	clock.p2 = 10;
		4822	clock.n = 6;
		4823	clock.m1 = 12;
		4824	clock.m2 = 8;
		4825	}
		4826	}
		4827
		4828	if (IS_PINEVIEW(dev)) {
		4829	fp = (1 << clock.n) << 16 \| clock.m1 << 8 \| clock.m2;
		4830	if (has_reduced_clock)
		4831	fp2 = (1 << reduced_clock.n) << 16 \|
		4832	reduced_clock.m1 << 8 \| reduced_clock.m2;
		4833	} else {
		4834	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		4835	if (has_reduced_clock)
		4836	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		4837	reduced_clock.m2;
		4838	}
		4839
		4840	dpll = DPLL_VGA_MODE_DIS;
		4841
		4842	if (!IS_GEN2(dev)) {
		4843	if (is_lvds)
		4844	dpll \|= DPLLB_MODE_LVDS;
		4845	else
		4846	dpll \|= DPLLB_MODE_DAC_SERIAL;
		4847	if (is_sdvo) {
		4848	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		4849	if (pixel_multiplier > 1) {
		4850	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))
		4851	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
		4852	}
		4853	dpll \|= DPLL_DVO_HIGH_SPEED;
		4854	}
		4855	if (is_dp)
		4856	dpll \|= DPLL_DVO_HIGH_SPEED;
		4857
		4858	/* compute bitmask from p1 value */
		4859	if (IS_PINEVIEW(dev))
		4860	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		4861	else {
		4862	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4863	if (IS_G4X(dev) && has_reduced_clock)
		4864	dpll \|= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		4865	}
		4866	switch (clock.p2) {
		4867	case 5:
		4868	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		4869	break;
		4870	case 7:
		4871	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		4872	break;
		4873	case 10:
		4874	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		4875	break;
		4876	case 14:
		4877	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		4878	break;
		4879	}
		4880	if (INTEL_INFO(dev)->gen >= 4)
		4881	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
		4882	} else {
		4883	if (is_lvds) {
		4884	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4885	} else {
		4886	if (clock.p1 == 2)
		4887	dpll \|= PLL_P1_DIVIDE_BY_TWO;
		4888	else
		4889	dpll \|= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		4890	if (clock.p2 == 4)
		4891	dpll \|= PLL_P2_DIVIDE_BY_4;
		4892	}
		4893	}
		4894
		4895	if (is_sdvo && is_tv)
		4896	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		4897	else if (is_tv)
		4898	/* XXX: just matching BIOS for now */
		4899	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		4900	dpll \|= 3;
		4901	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		4902	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		4903	else
		4904	dpll \|= PLL_REF_INPUT_DREFCLK;
		4905
		4906	/* setup pipeconf */
		4907	pipeconf = I915_READ(PIPECONF(pipe));
		4908
		4909	/* Set up the display plane register */
		4910	dspcntr = DISPPLANE_GAMMA_ENABLE;
		4911
		4912	/* Ironlake's plane is forced to pipe, bit 24 is to
		4913	enable color space conversion */
		4914	if (pipe == 0)
		4915	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		4916	else
		4917	dspcntr \|= DISPPLANE_SEL_PIPE_B;
		4918
		4919	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		4920	/* Enable pixel doubling when the dot clock is > 90% of the (display)
		4921	* core speed.
		4922	*
		4923	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		4924	* pipe == 0 check?
		4925	*/
		4926	if (mode->clock >
		4927	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
		4928	pipeconf \|= PIPECONF_DOUBLE_WIDE;
		4929	else
		4930	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
		4931	}
		4932
		4933	dpll \|= DPLL_VCO_ENABLE;
		4934
		4935	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		4936	drm_mode_debug_printmodeline(mode);
		4937
		4938	I915_WRITE(FP0(pipe), fp);
		4939	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		4940
		4941	POSTING_READ(DPLL(pipe));
		4942	udelay(150);
		4943
		4944	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		4945	* This is an exception to the general rule that mode_set doesn't turn
		4946	* things on.
		4947	*/
		4948	if (is_lvds) {
		4949	temp = I915_READ(LVDS);
		4950	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		4951	if (pipe == 1) {
		4952	temp \|= LVDS_PIPEB_SELECT;
		4953	} else {
		4954	temp &= ~LVDS_PIPEB_SELECT;
		4955	}
		4956	/* set the corresponsding LVDS_BORDER bit */
		4957	temp \|= dev_priv->lvds_border_bits;
		4958	/* Set the B0-B3 data pairs corresponding to whether we're going to
		4959	* set the DPLLs for dual-channel mode or not.
		4960	*/
		4961	if (clock.p2 == 7)
		4962	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		4963	else
		4964	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		4965
		4966	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		4967	* appropriately here, but we need to look more thoroughly into how
		4968	* panels behave in the two modes.
		4969	*/
		4970	/* set the dithering flag on LVDS as needed */
		4971	if (INTEL_INFO(dev)->gen >= 4) {
		4972	if (dev_priv->lvds_dither)
		4973	temp \|= LVDS_ENABLE_DITHER;
		4974	else
		4975	temp &= ~LVDS_ENABLE_DITHER;
		4976	}
		4977	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		4978	lvds_sync \|= LVDS_HSYNC_POLARITY;
		4979	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		4980	lvds_sync \|= LVDS_VSYNC_POLARITY;
		4981	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))
		4982	!= lvds_sync) {
		4983	char flags[2] = "-+";
		4984	DRM_INFO("Changing LVDS panel from "
		4985	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
		4986	flags[!(temp & LVDS_HSYNC_POLARITY)],
		4987	flags[!(temp & LVDS_VSYNC_POLARITY)],
		4988	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
		4989	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
		4990	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		4991	temp \|= lvds_sync;
		4992	}
		4993	I915_WRITE(LVDS, temp);
		4994	}
		4995
		4996	if (is_dp) {
		4997	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		4998	}
		4999
		5000	I915_WRITE(DPLL(pipe), dpll);
		5001
		5002	/* Wait for the clocks to stabilize. */
		5003	POSTING_READ(DPLL(pipe));
		5004	udelay(150);
		5005
		5006	if (INTEL_INFO(dev)->gen >= 4) {
		5007	temp = 0;
		5008	if (is_sdvo) {
		5009	temp = intel_mode_get_pixel_multiplier(adjusted_mode);
		5010	if (temp > 1)
		5011	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		5012	else
		5013	temp = 0;
		5014	}
		5015	I915_WRITE(DPLL_MD(pipe), temp);
		5016	} else {
		5017	/* The pixel multiplier can only be updated once the
		5018	* DPLL is enabled and the clocks are stable.
		5019	*
		5020	* So write it again.
		5021	*/
		5022	I915_WRITE(DPLL(pipe), dpll);
		5023	}
		5024
		5025	intel_crtc->lowfreq_avail = false;
		5026	if (is_lvds && has_reduced_clock && i915_powersave) {
		5027	I915_WRITE(FP1(pipe), fp2);
		5028	intel_crtc->lowfreq_avail = true;
		5029	if (HAS_PIPE_CXSR(dev)) {
		5030	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		5031	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		5032	}
		5033	} else {
		5034	I915_WRITE(FP1(pipe), fp);
		5035	if (HAS_PIPE_CXSR(dev)) {
		5036	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		5037	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		5038	}
		5039	}
		5040
		5041	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5042	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		5043	/* the chip adds 2 halflines automatically */
		5044	adjusted_mode->crtc_vdisplay -= 1;
		5045	adjusted_mode->crtc_vtotal -= 1;
		5046	adjusted_mode->crtc_vblank_start -= 1;
		5047	adjusted_mode->crtc_vblank_end -= 1;
		5048	adjusted_mode->crtc_vsync_end -= 1;
		5049	adjusted_mode->crtc_vsync_start -= 1;
		5050	} else
		5051	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
		5052
		5053	I915_WRITE(HTOTAL(pipe),
		5054	(adjusted_mode->crtc_hdisplay - 1) \|
		5055	((adjusted_mode->crtc_htotal - 1) << 16));
		5056	I915_WRITE(HBLANK(pipe),
		5057	(adjusted_mode->crtc_hblank_start - 1) \|
		5058	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5059	I915_WRITE(HSYNC(pipe),
		5060	(adjusted_mode->crtc_hsync_start - 1) \|
		5061	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5062
		5063	I915_WRITE(VTOTAL(pipe),
		5064	(adjusted_mode->crtc_vdisplay - 1) \|
		5065	((adjusted_mode->crtc_vtotal - 1) << 16));
		5066	I915_WRITE(VBLANK(pipe),
		5067	(adjusted_mode->crtc_vblank_start - 1) \|
		5068	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5069	I915_WRITE(VSYNC(pipe),
		5070	(adjusted_mode->crtc_vsync_start - 1) \|
		5071	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5072
		5073	/* pipesrc and dspsize control the size that is scaled from,
		5074	* which should always be the user's requested size.
		5075	*/
		5076	I915_WRITE(DSPSIZE(plane),
		5077	((mode->vdisplay - 1) << 16) \|
		5078	(mode->hdisplay - 1));
		5079	I915_WRITE(DSPPOS(plane), 0);
		5080	I915_WRITE(PIPESRC(pipe),
		5081	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5082
		5083	I915_WRITE(PIPECONF(pipe), pipeconf);
		5084	POSTING_READ(PIPECONF(pipe));
		5085	intel_enable_pipe(dev_priv, pipe, false);
		5086
		5087	intel_wait_for_vblank(dev, pipe);
		5088
		5089	I915_WRITE(DSPCNTR(plane), dspcntr);
		5090	POSTING_READ(DSPCNTR(plane));
		5091	intel_enable_plane(dev_priv, plane, pipe);
		5092
		5093	ret = intel_pipe_set_base(crtc, x, y, old_fb);
		5094
		5095	intel_update_watermarks(dev);
		5096
		5097	return ret;
		5098	}
		5099
		5100	static void ironlake_update_pch_refclk(struct drm_device *dev)
		5101	{
		5102	struct drm_i915_private *dev_priv = dev->dev_private;
		5103	struct drm_mode_config *mode_config = &dev->mode_config;
		5104	struct drm_crtc *crtc;
		5105	struct intel_encoder *encoder;
		5106	struct intel_encoder *has_edp_encoder = NULL;
		5107	u32 temp;
		5108	bool has_lvds = false;
		5109
		5110	/* We need to take the global config into account */
		5111	list_for_each_entry(crtc, &mode_config->crtc_list, head) {
		5112	if (!crtc->enabled)
		5113	continue;
		5114
		5115	list_for_each_entry(encoder, &mode_config->encoder_list,
		5116	base.head) {
		5117	if (encoder->base.crtc != crtc)
		5118	continue;
		5119
		5120	switch (encoder->type) {
		5121	case INTEL_OUTPUT_LVDS:
		5122	has_lvds = true;
		5123	case INTEL_OUTPUT_EDP:
		5124	has_edp_encoder = encoder;
		5125	break;
		5126	}
		5127	}
		5128	}
		5129
		5130	/* Ironlake: try to setup display ref clock before DPLL
		5131	* enabling. This is only under driver's control after
		5132	* PCH B stepping, previous chipset stepping should be
		5133	* ignoring this setting.
		5134	*/
		5135	temp = I915_READ(PCH_DREF_CONTROL);
		5136	/* Always enable nonspread source */
		5137	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
		5138	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;
		5139	temp &= ~DREF_SSC_SOURCE_MASK;
		5140	temp \|= DREF_SSC_SOURCE_ENABLE;
		5141	I915_WRITE(PCH_DREF_CONTROL, temp);
		5142
		5143	POSTING_READ(PCH_DREF_CONTROL);
		5144	udelay(200);
		5145
		5146	if (has_edp_encoder) {
		5147	if (intel_panel_use_ssc(dev_priv)) {
		5148	temp \|= DREF_SSC1_ENABLE;
		5149	I915_WRITE(PCH_DREF_CONTROL, temp);
		5150
		5151	POSTING_READ(PCH_DREF_CONTROL);
		5152	udelay(200);
		5153	}
		5154	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
		5155
		5156	/* Enable CPU source on CPU attached eDP */
		5157	if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5158	if (intel_panel_use_ssc(dev_priv))
		5159	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
		5160	else
		5161	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		5162	} else {
		5163	/* Enable SSC on PCH eDP if needed */
		5164	if (intel_panel_use_ssc(dev_priv)) {
		5165	DRM_ERROR("enabling SSC on PCH\n");
		5166	temp \|= DREF_SUPERSPREAD_SOURCE_ENABLE;
		5167	}
		5168	}
		5169	I915_WRITE(PCH_DREF_CONTROL, temp);
		5170	POSTING_READ(PCH_DREF_CONTROL);
		5171	udelay(200);
		5172	}
		5173	}
		5174
		5175	static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		5176	struct drm_display_mode *mode,
		5177	struct drm_display_mode *adjusted_mode,
		5178	int x, int y,
		5179	struct drm_framebuffer *old_fb)
		5180	{
		5181	struct drm_device *dev = crtc->dev;
		5182	struct drm_i915_private *dev_priv = dev->dev_private;
		5183	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5184	int pipe = intel_crtc->pipe;
		5185	int plane = intel_crtc->plane;
		5186	int refclk, num_connectors = 0;
		5187	intel_clock_t clock, reduced_clock;
		5188	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
		5189	bool ok, has_reduced_clock = false, is_sdvo = false;
		5190	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
		5191	struct intel_encoder *has_edp_encoder = NULL;
		5192	struct drm_mode_config *mode_config = &dev->mode_config;
		5193	struct intel_encoder *encoder;
		5194	const intel_limit_t *limit;
		5195	int ret;
		5196	struct fdi_m_n m_n = {0};
		5197	u32 temp;
		5198	u32 lvds_sync = 0;
		5199	int target_clock, pixel_multiplier, lane, link_bw, factor;
		5200	unsigned int pipe_bpp;
		5201	bool dither;
		5202
2336	Serge	5203	ENTER();
		5204
2327	Serge	5205	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		5206	if (encoder->base.crtc != crtc)
		5207	continue;
		5208
		5209	switch (encoder->type) {
		5210	case INTEL_OUTPUT_LVDS:
		5211	is_lvds = true;
		5212	break;
		5213	case INTEL_OUTPUT_SDVO:
		5214	case INTEL_OUTPUT_HDMI:
		5215	is_sdvo = true;
		5216	if (encoder->needs_tv_clock)
		5217	is_tv = true;
		5218	break;
		5219	case INTEL_OUTPUT_TVOUT:
		5220	is_tv = true;
		5221	break;
		5222	case INTEL_OUTPUT_ANALOG:
		5223	is_crt = true;
		5224	break;
		5225	case INTEL_OUTPUT_DISPLAYPORT:
		5226	is_dp = true;
		5227	break;
		5228	case INTEL_OUTPUT_EDP:
		5229	has_edp_encoder = encoder;
		5230	break;
		5231	}
		5232
		5233	num_connectors++;
		5234	}
		5235
		5236	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		5237	refclk = dev_priv->lvds_ssc_freq * 1000;
		5238	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
		5239	refclk / 1000);
		5240	} else {
		5241	refclk = 96000;
		5242	if (!has_edp_encoder \|\|
		5243	intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5244	refclk = 120000; /* 120Mhz refclk */
		5245	}
		5246
		5247	/*
		5248	* Returns a set of divisors for the desired target clock with the given
		5249	* refclk, or FALSE. The returned values represent the clock equation:
		5250	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
		5251	*/
		5252	limit = intel_limit(crtc, refclk);
		5253	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
		5254	if (!ok) {
		5255	DRM_ERROR("Couldn't find PLL settings for mode!\n");
		5256	return -EINVAL;
		5257	}
		5258
		5259	/* Ensure that the cursor is valid for the new mode before changing... */
		5260	// intel_crtc_update_cursor(crtc, true);
		5261
		5262	if (is_lvds && dev_priv->lvds_downclock_avail) {
		5263	has_reduced_clock = limit->find_pll(limit, crtc,
		5264	dev_priv->lvds_downclock,
		5265	refclk,
		5266	&reduced_clock);
		5267	if (has_reduced_clock && (clock.p != reduced_clock.p)) {
		5268	/*
		5269	* If the different P is found, it means that we can't
		5270	* switch the display clock by using the FP0/FP1.
		5271	* In such case we will disable the LVDS downclock
		5272	* feature.
		5273	*/
		5274	DRM_DEBUG_KMS("Different P is found for "
		5275	"LVDS clock/downclock\n");
		5276	has_reduced_clock = 0;
		5277	}
		5278	}
		5279	/* SDVO TV has fixed PLL values depend on its clock range,
		5280	this mirrors vbios setting. */
		5281	if (is_sdvo && is_tv) {
		5282	if (adjusted_mode->clock >= 100000
		5283	&& adjusted_mode->clock < 140500) {
		5284	clock.p1 = 2;
		5285	clock.p2 = 10;
		5286	clock.n = 3;
		5287	clock.m1 = 16;
		5288	clock.m2 = 8;
		5289	} else if (adjusted_mode->clock >= 140500
		5290	&& adjusted_mode->clock <= 200000) {
		5291	clock.p1 = 1;
		5292	clock.p2 = 10;
		5293	clock.n = 6;
		5294	clock.m1 = 12;
		5295	clock.m2 = 8;
		5296	}
		5297	}
		5298
		5299	/* FDI link */
		5300	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		5301	lane = 0;
		5302	/* CPU eDP doesn't require FDI link, so just set DP M/N
		5303	according to current link config */
		5304	if (has_edp_encoder &&
		5305	!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5306	target_clock = mode->clock;
		5307	intel_edp_link_config(has_edp_encoder,
		5308	&lane, &link_bw);
		5309	} else {
		5310	/* [e]DP over FDI requires target mode clock
		5311	instead of link clock */
		5312	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5313	target_clock = mode->clock;
		5314	else
		5315	target_clock = adjusted_mode->clock;
		5316
		5317	/* FDI is a binary signal running at ~2.7GHz, encoding
		5318	* each output octet as 10 bits. The actual frequency
		5319	* is stored as a divider into a 100MHz clock, and the
		5320	* mode pixel clock is stored in units of 1KHz.
		5321	* Hence the bw of each lane in terms of the mode signal
		5322	* is:
		5323	*/
		5324	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		5325	}
		5326
		5327	/* determine panel color depth */
		5328	temp = I915_READ(PIPECONF(pipe));
		5329	temp &= ~PIPE_BPC_MASK;
		5330	dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
		5331	switch (pipe_bpp) {
		5332	case 18:
		5333	temp \|= PIPE_6BPC;
		5334	break;
		5335	case 24:
		5336	temp \|= PIPE_8BPC;
		5337	break;
		5338	case 30:
		5339	temp \|= PIPE_10BPC;
		5340	break;
		5341	case 36:
		5342	temp \|= PIPE_12BPC;
		5343	break;
		5344	default:
		5345	WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
		5346	pipe_bpp);
		5347	temp \|= PIPE_8BPC;
		5348	pipe_bpp = 24;
		5349	break;
		5350	}
		5351
		5352	intel_crtc->bpp = pipe_bpp;
		5353	I915_WRITE(PIPECONF(pipe), temp);
		5354
		5355	if (!lane) {
		5356	/*
		5357	* Account for spread spectrum to avoid
		5358	* oversubscribing the link. Max center spread
		5359	* is 2.5%; use 5% for safety's sake.
		5360	*/
		5361	u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
		5362	lane = bps / (link_bw * 8) + 1;
		5363	}
		5364
		5365	intel_crtc->fdi_lanes = lane;
		5366
		5367	if (pixel_multiplier > 1)
		5368	link_bw *= pixel_multiplier;
		5369	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
		5370	&m_n);
		5371
		5372	ironlake_update_pch_refclk(dev);
		5373
		5374	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
		5375	if (has_reduced_clock)
		5376	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
		5377	reduced_clock.m2;
		5378
		5379	/* Enable autotuning of the PLL clock (if permissible) */
		5380	factor = 21;
		5381	if (is_lvds) {
		5382	if ((intel_panel_use_ssc(dev_priv) &&
		5383	dev_priv->lvds_ssc_freq == 100) \|\|
		5384	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
		5385	factor = 25;
		5386	} else if (is_sdvo && is_tv)
		5387	factor = 20;
		5388
		5389	if (clock.m < factor * clock.n)
		5390	fp \|= FP_CB_TUNE;
		5391
		5392	dpll = 0;
		5393
		5394	if (is_lvds)
		5395	dpll \|= DPLLB_MODE_LVDS;
		5396	else
		5397	dpll \|= DPLLB_MODE_DAC_SERIAL;
		5398	if (is_sdvo) {
		5399	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		5400	if (pixel_multiplier > 1) {
		5401	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
		5402	}
		5403	dpll \|= DPLL_DVO_HIGH_SPEED;
		5404	}
		5405	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
		5406	dpll \|= DPLL_DVO_HIGH_SPEED;
		5407
		5408	/* compute bitmask from p1 value */
		5409	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		5410	/* also FPA1 */
		5411	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		5412
		5413	switch (clock.p2) {
		5414	case 5:
		5415	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		5416	break;
		5417	case 7:
		5418	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
		5419	break;
		5420	case 10:
		5421	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		5422	break;
		5423	case 14:
		5424	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
		5425	break;
		5426	}
		5427
		5428	if (is_sdvo && is_tv)
		5429	dpll \|= PLL_REF_INPUT_TVCLKINBC;
		5430	else if (is_tv)
		5431	/* XXX: just matching BIOS for now */
		5432	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
		5433	dpll \|= 3;
		5434	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		5435	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
		5436	else
		5437	dpll \|= PLL_REF_INPUT_DREFCLK;
		5438
		5439	/* setup pipeconf */
		5440	pipeconf = I915_READ(PIPECONF(pipe));
		5441
		5442	/* Set up the display plane register */
		5443	dspcntr = DISPPLANE_GAMMA_ENABLE;
		5444
		5445	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
		5446	drm_mode_debug_printmodeline(mode);
		5447
		5448	/* PCH eDP needs FDI, but CPU eDP does not */
		5449	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5450	I915_WRITE(PCH_FP0(pipe), fp);
		5451	I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
		5452
		5453	POSTING_READ(PCH_DPLL(pipe));
		5454	udelay(150);
		5455	}
		5456
		5457	/* enable transcoder DPLL */
		5458	if (HAS_PCH_CPT(dev)) {
		5459	temp = I915_READ(PCH_DPLL_SEL);
		5460	switch (pipe) {
		5461	case 0:
		5462	temp \|= TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL;
		5463	break;
		5464	case 1:
		5465	temp \|= TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL;
		5466	break;
		5467	case 2:
		5468	/* FIXME: manage transcoder PLLs? */
		5469	temp \|= TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL;
		5470	break;
		5471	default:
		5472	BUG();
		5473	}
		5474	I915_WRITE(PCH_DPLL_SEL, temp);
		5475
		5476	POSTING_READ(PCH_DPLL_SEL);
		5477	udelay(150);
		5478	}
		5479
		5480	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
		5481	* This is an exception to the general rule that mode_set doesn't turn
		5482	* things on.
		5483	*/
		5484	if (is_lvds) {
		5485	temp = I915_READ(PCH_LVDS);
		5486	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
		5487	if (pipe == 1) {
		5488	if (HAS_PCH_CPT(dev))
		5489	temp \|= PORT_TRANS_B_SEL_CPT;
		5490	else
		5491	temp \|= LVDS_PIPEB_SELECT;
		5492	} else {
		5493	if (HAS_PCH_CPT(dev))
		5494	temp &= ~PORT_TRANS_SEL_MASK;
		5495	else
		5496	temp &= ~LVDS_PIPEB_SELECT;
		5497	}
		5498	/* set the corresponsding LVDS_BORDER bit */
		5499	temp \|= dev_priv->lvds_border_bits;
		5500	/* Set the B0-B3 data pairs corresponding to whether we're going to
		5501	* set the DPLLs for dual-channel mode or not.
		5502	*/
		5503	if (clock.p2 == 7)
		5504	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
		5505	else
		5506	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
		5507
		5508	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		5509	* appropriately here, but we need to look more thoroughly into how
		5510	* panels behave in the two modes.
		5511	*/
		5512	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
		5513	lvds_sync \|= LVDS_HSYNC_POLARITY;
		5514	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
		5515	lvds_sync \|= LVDS_VSYNC_POLARITY;
		5516	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))
		5517	!= lvds_sync) {
		5518	char flags[2] = "-+";
		5519	DRM_INFO("Changing LVDS panel from "
		5520	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
		5521	flags[!(temp & LVDS_HSYNC_POLARITY)],
		5522	flags[!(temp & LVDS_VSYNC_POLARITY)],
		5523	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
		5524	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
		5525	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
		5526	temp \|= lvds_sync;
		5527	}
		5528	I915_WRITE(PCH_LVDS, temp);
		5529	}
		5530
		5531	pipeconf &= ~PIPECONF_DITHER_EN;
		5532	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
		5533	if ((is_lvds && dev_priv->lvds_dither) \|\| dither) {
		5534	pipeconf \|= PIPECONF_DITHER_EN;
		5535	pipeconf \|= PIPECONF_DITHER_TYPE_ST1;
		5536	}
		5537	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5538	intel_dp_set_m_n(crtc, mode, adjusted_mode);
		5539	} else {
		5540	/* For non-DP output, clear any trans DP clock recovery setting.*/
		5541	I915_WRITE(TRANSDATA_M1(pipe), 0);
		5542	I915_WRITE(TRANSDATA_N1(pipe), 0);
		5543	I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		5544	I915_WRITE(TRANSDPLINK_N1(pipe), 0);
		5545	}
		5546
		5547	if (!has_edp_encoder \|\|
		5548	intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5549	I915_WRITE(PCH_DPLL(pipe), dpll);
		5550
		5551	/* Wait for the clocks to stabilize. */
		5552	POSTING_READ(PCH_DPLL(pipe));
		5553	udelay(150);
		5554
		5555	/* The pixel multiplier can only be updated once the
		5556	* DPLL is enabled and the clocks are stable.
		5557	*
		5558	* So write it again.
		5559	*/
		5560	I915_WRITE(PCH_DPLL(pipe), dpll);
		5561	}
		5562
		5563	intel_crtc->lowfreq_avail = false;
		5564	if (is_lvds && has_reduced_clock && i915_powersave) {
		5565	I915_WRITE(PCH_FP1(pipe), fp2);
		5566	intel_crtc->lowfreq_avail = true;
		5567	if (HAS_PIPE_CXSR(dev)) {
		5568	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
		5569	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
		5570	}
		5571	} else {
		5572	I915_WRITE(PCH_FP1(pipe), fp);
		5573	if (HAS_PIPE_CXSR(dev)) {
		5574	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		5575	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		5576	}
		5577	}
		5578
		5579	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		5580	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		5581	/* the chip adds 2 halflines automatically */
		5582	adjusted_mode->crtc_vdisplay -= 1;
		5583	adjusted_mode->crtc_vtotal -= 1;
		5584	adjusted_mode->crtc_vblank_start -= 1;
		5585	adjusted_mode->crtc_vblank_end -= 1;
		5586	adjusted_mode->crtc_vsync_end -= 1;
		5587	adjusted_mode->crtc_vsync_start -= 1;
		5588	} else
		5589	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
		5590
		5591	I915_WRITE(HTOTAL(pipe),
		5592	(adjusted_mode->crtc_hdisplay - 1) \|
		5593	((adjusted_mode->crtc_htotal - 1) << 16));
		5594	I915_WRITE(HBLANK(pipe),
		5595	(adjusted_mode->crtc_hblank_start - 1) \|
		5596	((adjusted_mode->crtc_hblank_end - 1) << 16));
		5597	I915_WRITE(HSYNC(pipe),
		5598	(adjusted_mode->crtc_hsync_start - 1) \|
		5599	((adjusted_mode->crtc_hsync_end - 1) << 16));
		5600
		5601	I915_WRITE(VTOTAL(pipe),
		5602	(adjusted_mode->crtc_vdisplay - 1) \|
		5603	((adjusted_mode->crtc_vtotal - 1) << 16));
		5604	I915_WRITE(VBLANK(pipe),
		5605	(adjusted_mode->crtc_vblank_start - 1) \|
		5606	((adjusted_mode->crtc_vblank_end - 1) << 16));
		5607	I915_WRITE(VSYNC(pipe),
		5608	(adjusted_mode->crtc_vsync_start - 1) \|
		5609	((adjusted_mode->crtc_vsync_end - 1) << 16));
		5610
		5611	/* pipesrc controls the size that is scaled from, which should
		5612	* always be the user's requested size.
		5613	*/
		5614	I915_WRITE(PIPESRC(pipe),
		5615	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
		5616
		5617	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);
		5618	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		5619	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		5620	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
		5621
		5622	if (has_edp_encoder &&
		5623	!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		5624	ironlake_set_pll_edp(crtc, adjusted_mode->clock);
		5625	}
		5626
		5627	I915_WRITE(PIPECONF(pipe), pipeconf);
		5628	POSTING_READ(PIPECONF(pipe));
		5629
		5630	intel_wait_for_vblank(dev, pipe);
		5631
		5632	if (IS_GEN5(dev)) {
		5633	/* enable address swizzle for tiling buffer */
		5634	temp = I915_READ(DISP_ARB_CTL);
		5635	I915_WRITE(DISP_ARB_CTL, temp \| DISP_TILE_SURFACE_SWIZZLING);
		5636	}
		5637
		5638	I915_WRITE(DSPCNTR(plane), dspcntr);
		5639	POSTING_READ(DSPCNTR(plane));
		5640
		5641	ret = intel_pipe_set_base(crtc, x, y, old_fb);
		5642
2336	Serge	5643	dbgprintf("Set base\n");
		5644
2327	Serge	5645	intel_update_watermarks(dev);
		5646
2336	Serge	5647	LEAVE();
		5648
2327	Serge	5649	return ret;
		5650	}
		5651
2330	Serge	5652	static int intel_crtc_mode_set(struct drm_crtc *crtc,
		5653	struct drm_display_mode *mode,
		5654	struct drm_display_mode *adjusted_mode,
		5655	int x, int y,
		5656	struct drm_framebuffer *old_fb)
		5657	{
		5658	struct drm_device *dev = crtc->dev;
		5659	struct drm_i915_private *dev_priv = dev->dev_private;
		5660	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5661	int pipe = intel_crtc->pipe;
		5662	int ret;
2327	Serge	5663
2330	Serge	5664	// drm_vblank_pre_modeset(dev, pipe);
2336	Serge	5665	ENTER();
2327	Serge	5666
2330	Serge	5667	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
		5668	x, y, old_fb);
2327	Serge	5669
2330	Serge	5670	// drm_vblank_post_modeset(dev, pipe);
2327	Serge	5671
2330	Serge	5672	intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
2336	Serge	5673	LEAVE();
2327	Serge	5674
2330	Serge	5675	return ret;
		5676	}
2327	Serge	5677
		5678	/** Loads the palette/gamma unit for the CRTC with the prepared values */
		5679	void intel_crtc_load_lut(struct drm_crtc *crtc)
		5680	{
		5681	struct drm_device *dev = crtc->dev;
		5682	struct drm_i915_private *dev_priv = dev->dev_private;
		5683	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		5684	int palreg = PALETTE(intel_crtc->pipe);
		5685	int i;
		5686
		5687	/* The clocks have to be on to load the palette. */
		5688	if (!crtc->enabled)
		5689	return;
		5690
		5691	/* use legacy palette for Ironlake */
		5692	if (HAS_PCH_SPLIT(dev))
		5693	palreg = LGC_PALETTE(intel_crtc->pipe);
		5694
		5695	for (i = 0; i < 256; i++) {
		5696	I915_WRITE(palreg + 4 * i,
		5697	(intel_crtc->lut_r[i] << 16) \|
		5698	(intel_crtc->lut_g[i] << 8) \|
		5699	intel_crtc->lut_b[i]);
		5700	}
		5701	}
		5702
		5703
		5704
		5705
		5706
		5707
		5708
		5709
		5710
		5711
		5712
		5713
		5714
		5715
		5716
		5717
		5718
		5719
		5720
		5721
		5722
		5723
		5724
		5725
		5726
		5727
		5728
		5729
		5730
		5731
		5732
		5733
		5734
		5735
		5736
		5737
		5738
2332	Serge	5739	/** Sets the color ramps on behalf of RandR */
		5740	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		5741	u16 blue, int regno)
		5742	{
		5743	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5744
2332	Serge	5745	intel_crtc->lut_r[regno] = red >> 8;
		5746	intel_crtc->lut_g[regno] = green >> 8;
		5747	intel_crtc->lut_b[regno] = blue >> 8;
		5748	}
2327	Serge	5749
2332	Serge	5750	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		5751	u16 *blue, int regno)
		5752	{
		5753	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5754
2332	Serge	5755	*red = intel_crtc->lut_r[regno] << 8;
		5756	*green = intel_crtc->lut_g[regno] << 8;
		5757	*blue = intel_crtc->lut_b[regno] << 8;
		5758	}
2327	Serge	5759
2330	Serge	5760	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
		5761	u16 *blue, uint32_t start, uint32_t size)
		5762	{
		5763	int end = (start + size > 256) ? 256 : start + size, i;
		5764	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	5765
2330	Serge	5766	for (i = start; i < end; i++) {
		5767	intel_crtc->lut_r[i] = red[i] >> 8;
		5768	intel_crtc->lut_g[i] = green[i] >> 8;
		5769	intel_crtc->lut_b[i] = blue[i] >> 8;
		5770	}
2327	Serge	5771
2330	Serge	5772	intel_crtc_load_lut(crtc);
		5773	}
2327	Serge	5774
2330	Serge	5775	/**
		5776	* Get a pipe with a simple mode set on it for doing load-based monitor
		5777	* detection.
		5778	*
		5779	* It will be up to the load-detect code to adjust the pipe as appropriate for
		5780	* its requirements. The pipe will be connected to no other encoders.
		5781	*
		5782	* Currently this code will only succeed if there is a pipe with no encoders
		5783	* configured for it. In the future, it could choose to temporarily disable
		5784	* some outputs to free up a pipe for its use.
		5785	*
		5786	* \return crtc, or NULL if no pipes are available.
		5787	*/
2327	Serge	5788
2330	Serge	5789	/* VESA 640x480x72Hz mode to set on the pipe */
		5790	static struct drm_display_mode load_detect_mode = {
		5791	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		5792	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
		5793	};
2327	Serge	5794
		5795
		5796
		5797
		5798
2330	Serge	5799	static u32
		5800	intel_framebuffer_pitch_for_width(int width, int bpp)
		5801	{
		5802	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
		5803	return ALIGN(pitch, 64);
		5804	}
2327	Serge	5805
2330	Serge	5806	static u32
		5807	intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
		5808	{
		5809	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
		5810	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
		5811	}
2327	Serge	5812
2330	Serge	5813	static struct drm_framebuffer *
		5814	intel_framebuffer_create_for_mode(struct drm_device *dev,
		5815	struct drm_display_mode *mode,
		5816	int depth, int bpp)
		5817	{
		5818	struct drm_i915_gem_object *obj;
		5819	struct drm_mode_fb_cmd mode_cmd;
2327	Serge	5820
2330	Serge	5821	// obj = i915_gem_alloc_object(dev,
		5822	// intel_framebuffer_size_for_mode(mode, bpp));
		5823	// if (obj == NULL)
		5824	return ERR_PTR(-ENOMEM);
2327	Serge	5825
2330	Serge	5826	// mode_cmd.width = mode->hdisplay;
		5827	// mode_cmd.height = mode->vdisplay;
		5828	// mode_cmd.depth = depth;
		5829	// mode_cmd.bpp = bpp;
		5830	// mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
2327	Serge	5831
2330	Serge	5832	// return intel_framebuffer_create(dev, &mode_cmd, obj);
		5833	}
2327	Serge	5834
2330	Serge	5835	static struct drm_framebuffer *
		5836	mode_fits_in_fbdev(struct drm_device *dev,
		5837	struct drm_display_mode *mode)
		5838	{
		5839	struct drm_i915_private *dev_priv = dev->dev_private;
		5840	struct drm_i915_gem_object *obj;
		5841	struct drm_framebuffer *fb;
2327	Serge	5842
2330	Serge	5843	// if (dev_priv->fbdev == NULL)
		5844	// return NULL;
2327	Serge	5845
2330	Serge	5846	// obj = dev_priv->fbdev->ifb.obj;
		5847	// if (obj == NULL)
		5848	// return NULL;
2327	Serge	5849
2330	Serge	5850	// fb = &dev_priv->fbdev->ifb.base;
		5851	// if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
		5852	// fb->bits_per_pixel))
		5853	return NULL;
2327	Serge	5854
2330	Serge	5855	// if (obj->base.size < mode->vdisplay * fb->pitch)
		5856	// return NULL;
2327	Serge	5857
2330	Serge	5858	// return fb;
		5859	}
2327	Serge	5860
2330	Serge	5861	bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
		5862	struct drm_connector *connector,
		5863	struct drm_display_mode *mode,
		5864	struct intel_load_detect_pipe *old)
		5865	{
		5866	struct intel_crtc *intel_crtc;
		5867	struct drm_crtc *possible_crtc;
		5868	struct drm_encoder *encoder = &intel_encoder->base;
		5869	struct drm_crtc *crtc = NULL;
		5870	struct drm_device *dev = encoder->dev;
		5871	struct drm_framebuffer *old_fb;
		5872	int i = -1;
2327	Serge	5873
2330	Serge	5874	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5875	connector->base.id, drm_get_connector_name(connector),
		5876	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5877
2330	Serge	5878	/*
		5879	* Algorithm gets a little messy:
		5880	*
		5881	* - if the connector already has an assigned crtc, use it (but make
		5882	* sure it's on first)
		5883	*
		5884	* - try to find the first unused crtc that can drive this connector,
		5885	* and use that if we find one
		5886	*/
2327	Serge	5887
2330	Serge	5888	/* See if we already have a CRTC for this connector */
		5889	if (encoder->crtc) {
		5890	crtc = encoder->crtc;
2327	Serge	5891
2330	Serge	5892	intel_crtc = to_intel_crtc(crtc);
		5893	old->dpms_mode = intel_crtc->dpms_mode;
		5894	old->load_detect_temp = false;
2327	Serge	5895
2330	Serge	5896	/* Make sure the crtc and connector are running */
		5897	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
		5898	struct drm_encoder_helper_funcs *encoder_funcs;
		5899	struct drm_crtc_helper_funcs *crtc_funcs;
2327	Serge	5900
2330	Serge	5901	crtc_funcs = crtc->helper_private;
		5902	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2327	Serge	5903
2330	Serge	5904	encoder_funcs = encoder->helper_private;
		5905	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		5906	}
2327	Serge	5907
2330	Serge	5908	return true;
		5909	}
2327	Serge	5910
2330	Serge	5911	/* Find an unused one (if possible) */
		5912	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		5913	i++;
		5914	if (!(encoder->possible_crtcs & (1 << i)))
		5915	continue;
		5916	if (!possible_crtc->enabled) {
		5917	crtc = possible_crtc;
		5918	break;
		5919	}
		5920	}
2327	Serge	5921
2330	Serge	5922	/*
		5923	* If we didn't find an unused CRTC, don't use any.
		5924	*/
		5925	if (!crtc) {
		5926	DRM_DEBUG_KMS("no pipe available for load-detect\n");
		5927	return false;
		5928	}
2327	Serge	5929
2330	Serge	5930	encoder->crtc = crtc;
		5931	connector->encoder = encoder;
2327	Serge	5932
2330	Serge	5933	intel_crtc = to_intel_crtc(crtc);
		5934	old->dpms_mode = intel_crtc->dpms_mode;
		5935	old->load_detect_temp = true;
		5936	old->release_fb = NULL;
2327	Serge	5937
2330	Serge	5938	if (!mode)
		5939	mode = &load_detect_mode;
2327	Serge	5940
2330	Serge	5941	old_fb = crtc->fb;
2327	Serge	5942
2330	Serge	5943	/* We need a framebuffer large enough to accommodate all accesses
		5944	* that the plane may generate whilst we perform load detection.
		5945	* We can not rely on the fbcon either being present (we get called
		5946	* during its initialisation to detect all boot displays, or it may
		5947	* not even exist) or that it is large enough to satisfy the
		5948	* requested mode.
		5949	*/
		5950	crtc->fb = mode_fits_in_fbdev(dev, mode);
		5951	if (crtc->fb == NULL) {
		5952	DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
		5953	crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		5954	old->release_fb = crtc->fb;
		5955	} else
		5956	DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
		5957	if (IS_ERR(crtc->fb)) {
		5958	DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
		5959	crtc->fb = old_fb;
		5960	return false;
		5961	}
2327	Serge	5962
2330	Serge	5963	if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
		5964	DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
		5965	if (old->release_fb)
		5966	old->release_fb->funcs->destroy(old->release_fb);
		5967	crtc->fb = old_fb;
		5968	return false;
		5969	}
2327	Serge	5970
2330	Serge	5971	/* let the connector get through one full cycle before testing */
		5972	intel_wait_for_vblank(dev, intel_crtc->pipe);
2327	Serge	5973
2330	Serge	5974	return true;
		5975	}
2327	Serge	5976
2330	Serge	5977	void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
		5978	struct drm_connector *connector,
		5979	struct intel_load_detect_pipe *old)
		5980	{
		5981	struct drm_encoder *encoder = &intel_encoder->base;
		5982	struct drm_device *dev = encoder->dev;
		5983	struct drm_crtc *crtc = encoder->crtc;
		5984	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
		5985	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2327	Serge	5986
2330	Serge	5987	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		5988	connector->base.id, drm_get_connector_name(connector),
		5989	encoder->base.id, drm_get_encoder_name(encoder));
2327	Serge	5990
2330	Serge	5991	if (old->load_detect_temp) {
		5992	connector->encoder = NULL;
		5993	drm_helper_disable_unused_functions(dev);
2327	Serge	5994
2330	Serge	5995	if (old->release_fb)
		5996	old->release_fb->funcs->destroy(old->release_fb);
2327	Serge	5997
2330	Serge	5998	return;
		5999	}
2327	Serge	6000
2330	Serge	6001	/* Switch crtc and encoder back off if necessary */
		6002	if (old->dpms_mode != DRM_MODE_DPMS_ON) {
		6003	encoder_funcs->dpms(encoder, old->dpms_mode);
		6004	crtc_funcs->dpms(crtc, old->dpms_mode);
		6005	}
		6006	}
2327	Serge	6007
2330	Serge	6008	/* Returns the clock of the currently programmed mode of the given pipe. */
		6009	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
		6010	{
		6011	struct drm_i915_private *dev_priv = dev->dev_private;
		6012	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6013	int pipe = intel_crtc->pipe;
		6014	u32 dpll = I915_READ(DPLL(pipe));
		6015	u32 fp;
		6016	intel_clock_t clock;
2327	Serge	6017
2330	Serge	6018	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		6019	fp = I915_READ(FP0(pipe));
		6020	else
		6021	fp = I915_READ(FP1(pipe));
2327	Serge	6022
2330	Serge	6023	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
		6024	if (IS_PINEVIEW(dev)) {
		6025	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		6026	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6027	} else {
		6028	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		6029	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
		6030	}
2327	Serge	6031
2330	Serge	6032	if (!IS_GEN2(dev)) {
		6033	if (IS_PINEVIEW(dev))
		6034	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
		6035	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		6036	else
		6037	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
		6038	DPLL_FPA01_P1_POST_DIV_SHIFT);
2327	Serge	6039
2330	Serge	6040	switch (dpll & DPLL_MODE_MASK) {
		6041	case DPLLB_MODE_DAC_SERIAL:
		6042	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
		6043	5 : 10;
		6044	break;
		6045	case DPLLB_MODE_LVDS:
		6046	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
		6047	7 : 14;
		6048	break;
		6049	default:
		6050	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
		6051	"mode\n", (int)(dpll & DPLL_MODE_MASK));
		6052	return 0;
		6053	}
2327	Serge	6054
2330	Serge	6055	/* XXX: Handle the 100Mhz refclk */
		6056	intel_clock(dev, 96000, &clock);
		6057	} else {
		6058	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2327	Serge	6059
2330	Serge	6060	if (is_lvds) {
		6061	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
		6062	DPLL_FPA01_P1_POST_DIV_SHIFT);
		6063	clock.p2 = 14;
2327	Serge	6064
2330	Serge	6065	if ((dpll & PLL_REF_INPUT_MASK) ==
		6066	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
		6067	/* XXX: might not be 66MHz */
		6068	intel_clock(dev, 66000, &clock);
		6069	} else
		6070	intel_clock(dev, 48000, &clock);
		6071	} else {
		6072	if (dpll & PLL_P1_DIVIDE_BY_TWO)
		6073	clock.p1 = 2;
		6074	else {
		6075	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
		6076	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
		6077	}
		6078	if (dpll & PLL_P2_DIVIDE_BY_4)
		6079	clock.p2 = 4;
		6080	else
		6081	clock.p2 = 2;
2327	Serge	6082
2330	Serge	6083	intel_clock(dev, 48000, &clock);
		6084	}
		6085	}
2327	Serge	6086
2330	Serge	6087	/* XXX: It would be nice to validate the clocks, but we can't reuse
		6088	* i830PllIsValid() because it relies on the xf86_config connector
		6089	* configuration being accurate, which it isn't necessarily.
		6090	*/
2327	Serge	6091
2330	Serge	6092	return clock.dot;
		6093	}
2327	Serge	6094
2330	Serge	6095	/** Returns the currently programmed mode of the given pipe. */
		6096	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
		6097	struct drm_crtc *crtc)
		6098	{
		6099	struct drm_i915_private *dev_priv = dev->dev_private;
		6100	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6101	int pipe = intel_crtc->pipe;
		6102	struct drm_display_mode *mode;
		6103	int htot = I915_READ(HTOTAL(pipe));
		6104	int hsync = I915_READ(HSYNC(pipe));
		6105	int vtot = I915_READ(VTOTAL(pipe));
		6106	int vsync = I915_READ(VSYNC(pipe));
2327	Serge	6107
2330	Serge	6108	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
		6109	if (!mode)
		6110	return NULL;
		6111
		6112	mode->clock = intel_crtc_clock_get(dev, crtc);
		6113	mode->hdisplay = (htot & 0xffff) + 1;
		6114	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
		6115	mode->hsync_start = (hsync & 0xffff) + 1;
		6116	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
		6117	mode->vdisplay = (vtot & 0xffff) + 1;
		6118	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
		6119	mode->vsync_start = (vsync & 0xffff) + 1;
		6120	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
		6121
		6122	drm_mode_set_name(mode);
		6123	drm_mode_set_crtcinfo(mode, 0);
		6124
		6125	return mode;
		6126	}
		6127
		6128	#define GPU_IDLE_TIMEOUT 500 /* ms */
		6129
		6130
		6131
		6132
		6133	#define CRTC_IDLE_TIMEOUT 1000 /* ms */
		6134
		6135
		6136
		6137
2327	Serge	6138	static void intel_increase_pllclock(struct drm_crtc *crtc)
		6139	{
		6140	struct drm_device *dev = crtc->dev;
		6141	drm_i915_private_t *dev_priv = dev->dev_private;
		6142	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6143	int pipe = intel_crtc->pipe;
		6144	int dpll_reg = DPLL(pipe);
		6145	int dpll;
		6146
2336	Serge	6147	ENTER();
		6148
2327	Serge	6149	if (HAS_PCH_SPLIT(dev))
		6150	return;
		6151
		6152	if (!dev_priv->lvds_downclock_avail)
		6153	return;
		6154
		6155	dpll = I915_READ(dpll_reg);
		6156	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		6157	DRM_DEBUG_DRIVER("upclocking LVDS\n");
		6158
		6159	/* Unlock panel regs */
		6160	I915_WRITE(PP_CONTROL,
		6161	I915_READ(PP_CONTROL) \| PANEL_UNLOCK_REGS);
		6162
		6163	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		6164	I915_WRITE(dpll_reg, dpll);
		6165	intel_wait_for_vblank(dev, pipe);
		6166
		6167	dpll = I915_READ(dpll_reg);
		6168	if (dpll & DISPLAY_RATE_SELECT_FPA1)
		6169	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
		6170
		6171	/* ...and lock them again */
		6172	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
		6173	}
		6174
2336	Serge	6175	LEAVE();
		6176
2327	Serge	6177	/* Schedule downclock */
		6178	// mod_timer(&intel_crtc->idle_timer, jiffies +
		6179	// msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
		6180	}
		6181
		6182
		6183
		6184
		6185
		6186
		6187
		6188
		6189
		6190
		6191
		6192
		6193
		6194
		6195
		6196
		6197
		6198
		6199
		6200
		6201
		6202
2330	Serge	6203	static void intel_crtc_destroy(struct drm_crtc *crtc)
		6204	{
		6205	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		6206	struct drm_device *dev = crtc->dev;
		6207	struct intel_unpin_work *work;
		6208	unsigned long flags;
2327	Serge	6209
2330	Serge	6210	spin_lock_irqsave(&dev->event_lock, flags);
		6211	work = intel_crtc->unpin_work;
		6212	intel_crtc->unpin_work = NULL;
		6213	spin_unlock_irqrestore(&dev->event_lock, flags);
2327	Serge	6214
2330	Serge	6215	if (work) {
		6216	// cancel_work_sync(&work->work);
		6217	kfree(work);
		6218	}
2327	Serge	6219
2330	Serge	6220	drm_crtc_cleanup(crtc);
2327	Serge	6221
2330	Serge	6222	kfree(intel_crtc);
		6223	}
2327	Serge	6224
		6225
		6226
		6227
		6228
		6229
		6230
		6231
		6232
		6233
		6234
		6235
		6236
		6237
		6238
		6239
		6240
		6241
		6242
		6243
		6244
		6245
		6246
		6247
		6248
		6249
		6250
		6251
		6252
		6253
		6254
		6255
		6256
		6257
		6258
		6259
		6260
		6261
		6262
		6263
		6264
		6265
		6266
		6267
		6268
		6269
		6270
		6271
		6272
		6273
		6274
		6275
		6276
		6277
		6278
		6279
		6280
		6281
		6282
		6283
		6284
		6285
		6286
		6287
		6288
		6289
2330	Serge	6290	static void intel_sanitize_modesetting(struct drm_device *dev,
		6291	int pipe, int plane)
		6292	{
		6293	struct drm_i915_private *dev_priv = dev->dev_private;
		6294	u32 reg, val;
2327	Serge	6295
2330	Serge	6296	if (HAS_PCH_SPLIT(dev))
		6297	return;
2327	Serge	6298
2330	Serge	6299	/* Who knows what state these registers were left in by the BIOS or
		6300	* grub?
		6301	*
		6302	* If we leave the registers in a conflicting state (e.g. with the
		6303	* display plane reading from the other pipe than the one we intend
		6304	* to use) then when we attempt to teardown the active mode, we will
		6305	* not disable the pipes and planes in the correct order -- leaving
		6306	* a plane reading from a disabled pipe and possibly leading to
		6307	* undefined behaviour.
		6308	*/
2327	Serge	6309
2330	Serge	6310	reg = DSPCNTR(plane);
		6311	val = I915_READ(reg);
2327	Serge	6312
2330	Serge	6313	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		6314	return;
		6315	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
		6316	return;
2327	Serge	6317
2330	Serge	6318	/* This display plane is active and attached to the other CPU pipe. */
		6319	pipe = !pipe;
2327	Serge	6320
2330	Serge	6321	/* Disable the plane and wait for it to stop reading from the pipe. */
		6322	intel_disable_plane(dev_priv, plane, pipe);
		6323	intel_disable_pipe(dev_priv, pipe);
		6324	}
2327	Serge	6325
2330	Serge	6326	static void intel_crtc_reset(struct drm_crtc *crtc)
		6327	{
		6328	struct drm_device *dev = crtc->dev;
		6329	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327	Serge	6330
2330	Serge	6331	/* Reset flags back to the 'unknown' status so that they
		6332	* will be correctly set on the initial modeset.
		6333	*/
		6334	intel_crtc->dpms_mode = -1;
2327	Serge	6335
2330	Serge	6336	/* We need to fix up any BIOS configuration that conflicts with
		6337	* our expectations.
		6338	*/
		6339	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
		6340	}
2327	Serge	6341
2330	Serge	6342	static struct drm_crtc_helper_funcs intel_helper_funcs = {
		6343	.dpms = intel_crtc_dpms,
		6344	.mode_fixup = intel_crtc_mode_fixup,
		6345	.mode_set = intel_crtc_mode_set,
		6346	.mode_set_base = intel_pipe_set_base,
		6347	.mode_set_base_atomic = intel_pipe_set_base_atomic,
		6348	.load_lut = intel_crtc_load_lut,
		6349	.disable = intel_crtc_disable,
		6350	};
2327	Serge	6351
2330	Serge	6352	static const struct drm_crtc_funcs intel_crtc_funcs = {
		6353	.reset = intel_crtc_reset,
		6354	// .cursor_set = intel_crtc_cursor_set,
		6355	// .cursor_move = intel_crtc_cursor_move,
		6356	.gamma_set = intel_crtc_gamma_set,
		6357	.set_config = drm_crtc_helper_set_config,
		6358	.destroy = intel_crtc_destroy,
		6359	// .page_flip = intel_crtc_page_flip,
		6360	};
2327	Serge	6361
2330	Serge	6362	static void intel_crtc_init(struct drm_device *dev, int pipe)
		6363	{
		6364	drm_i915_private_t *dev_priv = dev->dev_private;
		6365	struct intel_crtc *intel_crtc;
		6366	int i;
2327	Serge	6367
2330	Serge	6368	ENTER();
2327	Serge	6369
2330	Serge	6370	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		6371	if (intel_crtc == NULL)
		6372	return;
2327	Serge	6373
2330	Serge	6374	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2327	Serge	6375
2330	Serge	6376	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
		6377	for (i = 0; i < 256; i++) {
		6378	intel_crtc->lut_r[i] = i;
		6379	intel_crtc->lut_g[i] = i;
		6380	intel_crtc->lut_b[i] = i;
		6381	}
2327	Serge	6382
2330	Serge	6383	/* Swap pipes & planes for FBC on pre-965 */
		6384	intel_crtc->pipe = pipe;
		6385	intel_crtc->plane = pipe;
		6386	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		6387	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		6388	intel_crtc->plane = !pipe;
		6389	}
2327	Serge	6390
2330	Serge	6391	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
		6392	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
		6393	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
		6394	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
2327	Serge	6395
2330	Serge	6396	intel_crtc_reset(&intel_crtc->base);
		6397	intel_crtc->active = true; /* force the pipe off on setup_init_config */
		6398	intel_crtc->bpp = 24; /* default for pre-Ironlake */
2327	Serge	6399
2330	Serge	6400	if (HAS_PCH_SPLIT(dev)) {
		6401	intel_helper_funcs.prepare = ironlake_crtc_prepare;
		6402	intel_helper_funcs.commit = ironlake_crtc_commit;
		6403	} else {
		6404	intel_helper_funcs.prepare = i9xx_crtc_prepare;
		6405	intel_helper_funcs.commit = i9xx_crtc_commit;
		6406	}
2327	Serge	6407
2330	Serge	6408	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2327	Serge	6409
2330	Serge	6410	intel_crtc->busy = false;
2327	Serge	6411
2330	Serge	6412	LEAVE();
2327	Serge	6413
2330	Serge	6414	// setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
		6415	// (unsigned long)intel_crtc);
		6416	}
2327	Serge	6417
		6418
		6419
		6420
		6421
		6422
		6423
2330	Serge	6424	static int intel_encoder_clones(struct drm_device *dev, int type_mask)
		6425	{
		6426	struct intel_encoder *encoder;
		6427	int index_mask = 0;
		6428	int entry = 0;
2327	Serge	6429
2330	Serge	6430	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		6431	if (type_mask & encoder->clone_mask)
		6432	index_mask \|= (1 << entry);
		6433	entry++;
		6434	}
2327	Serge	6435
2330	Serge	6436	return index_mask;
		6437	}
2327	Serge	6438
2330	Serge	6439	static bool has_edp_a(struct drm_device *dev)
		6440	{
		6441	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	6442
2330	Serge	6443	if (!IS_MOBILE(dev))
		6444	return false;
2327	Serge	6445
2330	Serge	6446	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		6447	return false;
2327	Serge	6448
2330	Serge	6449	if (IS_GEN5(dev) &&
		6450	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		6451	return false;
2327	Serge	6452
2330	Serge	6453	return true;
		6454	}
2327	Serge	6455
2330	Serge	6456	static void intel_setup_outputs(struct drm_device *dev)
		6457	{
		6458	struct drm_i915_private *dev_priv = dev->dev_private;
		6459	struct intel_encoder *encoder;
		6460	bool dpd_is_edp = false;
		6461	bool has_lvds = false;
2327	Serge	6462
2336	Serge	6463	ENTER();
		6464
2330	Serge	6465	if (IS_MOBILE(dev) && !IS_I830(dev))
		6466	has_lvds = intel_lvds_init(dev);
		6467	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		6468	/* disable the panel fitter on everything but LVDS */
		6469	I915_WRITE(PFIT_CONTROL, 0);
		6470	}
2327	Serge	6471
2330	Serge	6472	if (HAS_PCH_SPLIT(dev)) {
		6473	dpd_is_edp = intel_dpd_is_edp(dev);
2327	Serge	6474
2330	Serge	6475	if (has_edp_a(dev))
		6476	intel_dp_init(dev, DP_A);
2327	Serge	6477
2330	Serge	6478	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
		6479	intel_dp_init(dev, PCH_DP_D);
		6480	}
2327	Serge	6481
2330	Serge	6482	intel_crt_init(dev);
2327	Serge	6483
2330	Serge	6484	if (HAS_PCH_SPLIT(dev)) {
		6485	int found;
2327	Serge	6486
2330	Serge	6487	if (I915_READ(HDMIB) & PORT_DETECTED) {
		6488	/* PCH SDVOB multiplex with HDMIB */
		6489	found = intel_sdvo_init(dev, PCH_SDVOB);
		6490	if (!found)
		6491	intel_hdmi_init(dev, HDMIB);
		6492	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
		6493	intel_dp_init(dev, PCH_DP_B);
		6494	}
2327	Serge	6495
2330	Serge	6496	if (I915_READ(HDMIC) & PORT_DETECTED)
		6497	intel_hdmi_init(dev, HDMIC);
2327	Serge	6498
2330	Serge	6499	if (I915_READ(HDMID) & PORT_DETECTED)
		6500	intel_hdmi_init(dev, HDMID);
2327	Serge	6501
2330	Serge	6502	if (I915_READ(PCH_DP_C) & DP_DETECTED)
		6503	intel_dp_init(dev, PCH_DP_C);
2327	Serge	6504
2330	Serge	6505	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
		6506	intel_dp_init(dev, PCH_DP_D);
2327	Serge	6507
2330	Serge	6508	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		6509	bool found = false;
2327	Serge	6510
2330	Serge	6511	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		6512	DRM_DEBUG_KMS("probing SDVOB\n");
		6513	found = intel_sdvo_init(dev, SDVOB);
		6514	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
		6515	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
		6516	intel_hdmi_init(dev, SDVOB);
		6517	}
2327	Serge	6518
2330	Serge	6519	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
		6520	DRM_DEBUG_KMS("probing DP_B\n");
		6521	intel_dp_init(dev, DP_B);
		6522	}
		6523	}
2327	Serge	6524
2330	Serge	6525	/* Before G4X SDVOC doesn't have its own detect register */
2327	Serge	6526
2330	Serge	6527	if (I915_READ(SDVOB) & SDVO_DETECTED) {
		6528	DRM_DEBUG_KMS("probing SDVOC\n");
		6529	found = intel_sdvo_init(dev, SDVOC);
		6530	}
2327	Serge	6531
2330	Serge	6532	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
2327	Serge	6533
2330	Serge	6534	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
		6535	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
		6536	intel_hdmi_init(dev, SDVOC);
		6537	}
		6538	if (SUPPORTS_INTEGRATED_DP(dev)) {
		6539	DRM_DEBUG_KMS("probing DP_C\n");
		6540	intel_dp_init(dev, DP_C);
		6541	}
		6542	}
2327	Serge	6543
2330	Serge	6544	if (SUPPORTS_INTEGRATED_DP(dev) &&
		6545	(I915_READ(DP_D) & DP_DETECTED)) {
		6546	DRM_DEBUG_KMS("probing DP_D\n");
		6547	intel_dp_init(dev, DP_D);
		6548	}
		6549	} else if (IS_GEN2(dev))
		6550	intel_dvo_init(dev);
2327	Serge	6551
2330	Serge	6552	// if (SUPPORTS_TV(dev))
		6553	// intel_tv_init(dev);
2327	Serge	6554
2330	Serge	6555	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		6556	encoder->base.possible_crtcs = encoder->crtc_mask;
		6557	encoder->base.possible_clones =
		6558	intel_encoder_clones(dev, encoder->clone_mask);
		6559	}
2327	Serge	6560
2330	Serge	6561	/* disable all the possible outputs/crtcs before entering KMS mode */
		6562	// drm_helper_disable_unused_functions(dev);
2336	Serge	6563
		6564	LEAVE();
2330	Serge	6565	}
		6566
		6567
		6568
		6569
2327	Serge	6570	static const struct drm_mode_config_funcs intel_mode_funcs = {
		6571	.fb_create = NULL /intel_user_framebuffer_create/,
		6572	.output_poll_changed = NULL /intel_fb_output_poll_changed/,
		6573	};
		6574
		6575
		6576
		6577
		6578
		6579
		6580
		6581
		6582
		6583
		6584
		6585
		6586
2335	Serge	6587	static const struct drm_framebuffer_funcs intel_fb_funcs = {
		6588	// .destroy = intel_user_framebuffer_destroy,
		6589	// .create_handle = intel_user_framebuffer_create_handle,
		6590	};
2327	Serge	6591
2335	Serge	6592	int intel_framebuffer_init(struct drm_device *dev,
		6593	struct intel_framebuffer *intel_fb,
		6594	struct drm_mode_fb_cmd *mode_cmd,
		6595	struct drm_i915_gem_object *obj)
		6596	{
		6597	int ret;
2327	Serge	6598
2335	Serge	6599	if (obj->tiling_mode == I915_TILING_Y)
		6600	return -EINVAL;
2327	Serge	6601
2335	Serge	6602	if (mode_cmd->pitch & 63)
		6603	return -EINVAL;
2327	Serge	6604
2335	Serge	6605	switch (mode_cmd->bpp) {
		6606	case 8:
		6607	case 16:
		6608	/* Only pre-ILK can handle 5:5:5 */
		6609	if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
		6610	return -EINVAL;
		6611	break;
2327	Serge	6612
2335	Serge	6613	case 24:
		6614	case 32:
		6615	break;
		6616	default:
		6617	return -EINVAL;
		6618	}
2327	Serge	6619
2335	Serge	6620	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
		6621	if (ret) {
		6622	DRM_ERROR("framebuffer init failed %d\n", ret);
		6623	return ret;
		6624	}
2327	Serge	6625
2335	Serge	6626	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
		6627	intel_fb->obj = obj;
		6628	return 0;
		6629	}
2327	Serge	6630
		6631
		6632
		6633
		6634
		6635
		6636
		6637
		6638
		6639
		6640
		6641
2330	Serge	6642	bool ironlake_set_drps(struct drm_device *dev, u8 val)
		6643	{
		6644	struct drm_i915_private *dev_priv = dev->dev_private;
		6645	u16 rgvswctl;
2327	Serge	6646
2330	Serge	6647	rgvswctl = I915_READ16(MEMSWCTL);
		6648	if (rgvswctl & MEMCTL_CMD_STS) {
		6649	DRM_DEBUG("gpu busy, RCS change rejected\n");
		6650	return false; /* still busy with another command */
		6651	}
2327	Serge	6652
2330	Serge	6653	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) \|
		6654	(val << MEMCTL_FREQ_SHIFT) \| MEMCTL_SFCAVM;
		6655	I915_WRITE16(MEMSWCTL, rgvswctl);
		6656	POSTING_READ16(MEMSWCTL);
2327	Serge	6657
2330	Serge	6658	rgvswctl \|= MEMCTL_CMD_STS;
		6659	I915_WRITE16(MEMSWCTL, rgvswctl);
2327	Serge	6660
2330	Serge	6661	return true;
		6662	}
2327	Serge	6663
2330	Serge	6664	void ironlake_enable_drps(struct drm_device *dev)
		6665	{
		6666	struct drm_i915_private *dev_priv = dev->dev_private;
		6667	u32 rgvmodectl = I915_READ(MEMMODECTL);
		6668	u8 fmax, fmin, fstart, vstart;
2327	Serge	6669
2330	Serge	6670	/* Enable temp reporting */
		6671	I915_WRITE16(PMMISC, I915_READ(PMMISC) \| MCPPCE_EN);
		6672	I915_WRITE16(TSC1, I915_READ(TSC1) \| TSE);
2327	Serge	6673
2330	Serge	6674	/* 100ms RC evaluation intervals */
		6675	I915_WRITE(RCUPEI, 100000);
		6676	I915_WRITE(RCDNEI, 100000);
2327	Serge	6677
2330	Serge	6678	/* Set max/min thresholds to 90ms and 80ms respectively */
		6679	I915_WRITE(RCBMAXAVG, 90000);
		6680	I915_WRITE(RCBMINAVG, 80000);
2327	Serge	6681
2330	Serge	6682	I915_WRITE(MEMIHYST, 1);
2327	Serge	6683
2330	Serge	6684	/* Set up min, max, and cur for interrupt handling */
		6685	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
		6686	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
		6687	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
		6688	MEMMODE_FSTART_SHIFT;
2327	Serge	6689
2330	Serge	6690	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
		6691	PXVFREQ_PX_SHIFT;
2327	Serge	6692
2330	Serge	6693	dev_priv->fmax = fmax; /* IPS callback will increase this */
		6694	dev_priv->fstart = fstart;
2327	Serge	6695
2330	Serge	6696	dev_priv->max_delay = fstart;
		6697	dev_priv->min_delay = fmin;
		6698	dev_priv->cur_delay = fstart;
2327	Serge	6699
2330	Serge	6700	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
		6701	fmax, fmin, fstart);
2327	Serge	6702
2330	Serge	6703	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN \| MEMINT_EVAL_CHG_EN);
2327	Serge	6704
2330	Serge	6705	/*
		6706	* Interrupts will be enabled in ironlake_irq_postinstall
		6707	*/
2327	Serge	6708
2330	Serge	6709	I915_WRITE(VIDSTART, vstart);
		6710	POSTING_READ(VIDSTART);
2327	Serge	6711
2330	Serge	6712	rgvmodectl \|= MEMMODE_SWMODE_EN;
		6713	I915_WRITE(MEMMODECTL, rgvmodectl);
2327	Serge	6714
2330	Serge	6715	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
		6716	DRM_ERROR("stuck trying to change perf mode\n");
		6717	msleep(1);
2327	Serge	6718
2330	Serge	6719	ironlake_set_drps(dev, fstart);
2327	Serge	6720
2330	Serge	6721	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
		6722	I915_READ(0x112e0);
		6723	// dev_priv->last_time1 = jiffies_to_msecs(jiffies);
		6724	dev_priv->last_count2 = I915_READ(0x112f4);
		6725	// getrawmonotonic(&dev_priv->last_time2);
		6726	}
2327	Serge	6727
		6728
		6729
		6730
		6731
		6732
		6733
		6734
		6735
		6736
		6737
		6738
		6739
		6740
		6741
2330	Serge	6742	static unsigned long intel_pxfreq(u32 vidfreq)
		6743	{
		6744	unsigned long freq;
		6745	int div = (vidfreq & 0x3f0000) >> 16;
		6746	int post = (vidfreq & 0x3000) >> 12;
		6747	int pre = (vidfreq & 0x7);
2327	Serge	6748
2330	Serge	6749	if (!pre)
		6750	return 0;
2327	Serge	6751
2330	Serge	6752	freq = ((div * 133333) / ((1<
2327	Serge	6753
2330	Serge	6754	return freq;
		6755	}
2327	Serge	6756
2330	Serge	6757	void intel_init_emon(struct drm_device *dev)
		6758	{
		6759	struct drm_i915_private *dev_priv = dev->dev_private;
		6760	u32 lcfuse;
		6761	u8 pxw[16];
		6762	int i;
2327	Serge	6763
2330	Serge	6764	/* Disable to program */
		6765	I915_WRITE(ECR, 0);
		6766	POSTING_READ(ECR);
2327	Serge	6767
2330	Serge	6768	/* Program energy weights for various events */
		6769	I915_WRITE(SDEW, 0x15040d00);
		6770	I915_WRITE(CSIEW0, 0x007f0000);
		6771	I915_WRITE(CSIEW1, 0x1e220004);
		6772	I915_WRITE(CSIEW2, 0x04000004);
2327	Serge	6773
2330	Serge	6774	for (i = 0; i < 5; i++)
		6775	I915_WRITE(PEW + (i * 4), 0);
		6776	for (i = 0; i < 3; i++)
		6777	I915_WRITE(DEW + (i * 4), 0);
2327	Serge	6778
2330	Serge	6779	/* Program P-state weights to account for frequency power adjustment */
		6780	for (i = 0; i < 16; i++) {
		6781	u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
		6782	unsigned long freq = intel_pxfreq(pxvidfreq);
		6783	unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
		6784	PXVFREQ_PX_SHIFT;
		6785	unsigned long val;
2327	Serge	6786
2330	Serge	6787	val = vid * vid;
		6788	val *= (freq / 1000);
		6789	val *= 255;
		6790	val /= (127127900);
		6791	if (val > 0xff)
		6792	DRM_ERROR("bad pxval: %ld\n", val);
		6793	pxw[i] = val;
		6794	}
		6795	/* Render standby states get 0 weight */
		6796	pxw[14] = 0;
		6797	pxw[15] = 0;
2327	Serge	6798
2330	Serge	6799	for (i = 0; i < 4; i++) {
		6800	u32 val = (pxw[i4] << 24) \| (pxw[(i4)+1] << 16) \|
		6801	(pxw[(i4)+2] << 8) \| (pxw[(i4)+3]);
		6802	I915_WRITE(PXW + (i * 4), val);
		6803	}
2327	Serge	6804
2330	Serge	6805	/* Adjust magic regs to magic values (more experimental results) */
		6806	I915_WRITE(OGW0, 0);
		6807	I915_WRITE(OGW1, 0);
		6808	I915_WRITE(EG0, 0x00007f00);
		6809	I915_WRITE(EG1, 0x0000000e);
		6810	I915_WRITE(EG2, 0x000e0000);
		6811	I915_WRITE(EG3, 0x68000300);
		6812	I915_WRITE(EG4, 0x42000000);
		6813	I915_WRITE(EG5, 0x00140031);
		6814	I915_WRITE(EG6, 0);
		6815	I915_WRITE(EG7, 0);
2327	Serge	6816
2330	Serge	6817	for (i = 0; i < 8; i++)
		6818	I915_WRITE(PXWL + (i * 4), 0);
2327	Serge	6819
2330	Serge	6820	/* Enable PMON + select events */
		6821	I915_WRITE(ECR, 0x80000019);
2327	Serge	6822
2330	Serge	6823	lcfuse = I915_READ(LCFUSE02);
		6824
		6825	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
		6826	}
		6827
		6828	void gen6_enable_rps(struct drm_i915_private *dev_priv)
		6829	{
		6830	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		6831	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		6832	u32 pcu_mbox, rc6_mask = 0;
		6833	int cur_freq, min_freq, max_freq;
		6834	int i;
		6835
		6836	/* Here begins a magic sequence of register writes to enable
		6837	* auto-downclocking.
		6838	*
		6839	* Perhaps there might be some value in exposing these to
		6840	* userspace...
		6841	*/
		6842	I915_WRITE(GEN6_RC_STATE, 0);
		6843	mutex_lock(&dev_priv->dev->struct_mutex);
		6844	gen6_gt_force_wake_get(dev_priv);
		6845
		6846	/* disable the counters and set deterministic thresholds */
		6847	I915_WRITE(GEN6_RC_CONTROL, 0);
		6848
		6849	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
		6850	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);
		6851	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
		6852	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
		6853	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
		6854
		6855	for (i = 0; i < I915_NUM_RINGS; i++)
		6856	I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
		6857
		6858	I915_WRITE(GEN6_RC_SLEEP, 0);
		6859	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
		6860	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
		6861	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
		6862	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
		6863
		6864	if (i915_enable_rc6)
		6865	rc6_mask = GEN6_RC_CTL_RC6p_ENABLE \|
		6866	GEN6_RC_CTL_RC6_ENABLE;
		6867
		6868	I915_WRITE(GEN6_RC_CONTROL,
		6869	rc6_mask \|
		6870	GEN6_RC_CTL_EI_MODE(1) \|
		6871	GEN6_RC_CTL_HW_ENABLE);
		6872
		6873	I915_WRITE(GEN6_RPNSWREQ,
		6874	GEN6_FREQUENCY(10) \|
		6875	GEN6_OFFSET(0) \|
		6876	GEN6_AGGRESSIVE_TURBO);
		6877	I915_WRITE(GEN6_RC_VIDEO_FREQ,
		6878	GEN6_FREQUENCY(12));
		6879
		6880	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
		6881	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		6882	18 << 24 \|
		6883	6 << 16);
		6884	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
		6885	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
		6886	I915_WRITE(GEN6_RP_UP_EI, 100000);
		6887	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
		6888	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
		6889	I915_WRITE(GEN6_RP_CONTROL,
		6890	GEN6_RP_MEDIA_TURBO \|
		6891	GEN6_RP_USE_NORMAL_FREQ \|
		6892	GEN6_RP_MEDIA_IS_GFX \|
		6893	GEN6_RP_ENABLE \|
		6894	GEN6_RP_UP_BUSY_AVG \|
		6895	GEN6_RP_DOWN_IDLE_CONT);
		6896
		6897	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6898	500))
		6899	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
		6900
		6901	I915_WRITE(GEN6_PCODE_DATA, 0);
		6902	I915_WRITE(GEN6_PCODE_MAILBOX,
		6903	GEN6_PCODE_READY \|
		6904	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
		6905	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6906	500))
		6907	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
		6908
		6909	min_freq = (rp_state_cap & 0xff0000) >> 16;
		6910	max_freq = rp_state_cap & 0xff;
		6911	cur_freq = (gt_perf_status & 0xff00) >> 8;
		6912
		6913	/* Check for overclock support */
		6914	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6915	500))
		6916	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
		6917	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
		6918	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
		6919	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		6920	500))
		6921	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
		6922	if (pcu_mbox & (1<<31)) { /* OC supported */
		6923	max_freq = pcu_mbox & 0xff;
		6924	DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
		6925	}
		6926
		6927	/* In units of 100MHz */
		6928	dev_priv->max_delay = max_freq;
		6929	dev_priv->min_delay = min_freq;
		6930	dev_priv->cur_delay = cur_freq;
		6931
		6932	/* requires MSI enabled */
		6933	I915_WRITE(GEN6_PMIER,
		6934	GEN6_PM_MBOX_EVENT \|
		6935	GEN6_PM_THERMAL_EVENT \|
		6936	GEN6_PM_RP_DOWN_TIMEOUT \|
		6937	GEN6_PM_RP_UP_THRESHOLD \|
		6938	GEN6_PM_RP_DOWN_THRESHOLD \|
		6939	GEN6_PM_RP_UP_EI_EXPIRED \|
		6940	GEN6_PM_RP_DOWN_EI_EXPIRED);
		6941	// spin_lock_irq(&dev_priv->rps_lock);
		6942	// WARN_ON(dev_priv->pm_iir != 0);
		6943	I915_WRITE(GEN6_PMIMR, 0);
		6944	// spin_unlock_irq(&dev_priv->rps_lock);
		6945	/* enable all PM interrupts */
		6946	I915_WRITE(GEN6_PMINTRMSK, 0);
		6947
		6948	gen6_gt_force_wake_put(dev_priv);
		6949	mutex_unlock(&dev_priv->dev->struct_mutex);
		6950	}
		6951
		6952	void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
		6953	{
		6954	int min_freq = 15;
		6955	int gpu_freq, ia_freq, max_ia_freq;
		6956	int scaling_factor = 180;
		6957
		6958	// max_ia_freq = cpufreq_quick_get_max(0);
		6959	/*
		6960	* Default to measured freq if none found, PCU will ensure we don't go
		6961	* over
		6962	*/
		6963	// if (!max_ia_freq)
		6964	max_ia_freq = 3000000; //tsc_khz;
		6965
		6966	/* Convert from kHz to MHz */
		6967	max_ia_freq /= 1000;
		6968
		6969	mutex_lock(&dev_priv->dev->struct_mutex);
		6970
		6971	/*
		6972	* For each potential GPU frequency, load a ring frequency we'd like
		6973	* to use for memory access. We do this by specifying the IA frequency
		6974	* the PCU should use as a reference to determine the ring frequency.
		6975	*/
		6976	for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
		6977	gpu_freq--) {
		6978	int diff = dev_priv->max_delay - gpu_freq;
		6979
		6980	/*
		6981	* For GPU frequencies less than 750MHz, just use the lowest
		6982	* ring freq.
		6983	*/
		6984	if (gpu_freq < min_freq)
		6985	ia_freq = 800;
		6986	else
		6987	ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
		6988	ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
		6989
		6990	I915_WRITE(GEN6_PCODE_DATA,
		6991	(ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) \|
		6992	gpu_freq);
		6993	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY \|
		6994	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
		6995	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
		6996	GEN6_PCODE_READY) == 0, 10)) {
		6997	DRM_ERROR("pcode write of freq table timed out\n");
		6998	continue;
		6999	}
		7000	}
		7001
		7002	mutex_unlock(&dev_priv->dev->struct_mutex);
		7003	}
		7004
2327	Serge	7005	static void ironlake_init_clock_gating(struct drm_device *dev)
		7006	{
		7007	struct drm_i915_private *dev_priv = dev->dev_private;
		7008	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		7009
		7010	/* Required for FBC */
		7011	dspclk_gate \|= DPFCUNIT_CLOCK_GATE_DISABLE \|
		7012	DPFCRUNIT_CLOCK_GATE_DISABLE \|
		7013	DPFDUNIT_CLOCK_GATE_DISABLE;
		7014	/* Required for CxSR */
		7015	dspclk_gate \|= DPARBUNIT_CLOCK_GATE_DISABLE;
		7016
		7017	I915_WRITE(PCH_3DCGDIS0,
		7018	MARIUNIT_CLOCK_GATE_DISABLE \|
		7019	SVSMUNIT_CLOCK_GATE_DISABLE);
		7020	I915_WRITE(PCH_3DCGDIS1,
		7021	VFMUNIT_CLOCK_GATE_DISABLE);
		7022
		7023	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		7024
		7025	/*
		7026	* According to the spec the following bits should be set in
		7027	* order to enable memory self-refresh
		7028	* The bit 22/21 of 0x42004
		7029	* The bit 5 of 0x42020
		7030	* The bit 15 of 0x45000
		7031	*/
		7032	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7033	(I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7034	ILK_DPARB_GATE \| ILK_VSDPFD_FULL));
		7035	I915_WRITE(ILK_DSPCLK_GATE,
		7036	(I915_READ(ILK_DSPCLK_GATE) \|
		7037	ILK_DPARB_CLK_GATE));
		7038	I915_WRITE(DISP_ARB_CTL,
		7039	(I915_READ(DISP_ARB_CTL) \|
		7040	DISP_FBC_WM_DIS));
		7041	I915_WRITE(WM3_LP_ILK, 0);
		7042	I915_WRITE(WM2_LP_ILK, 0);
		7043	I915_WRITE(WM1_LP_ILK, 0);
		7044
		7045	/*
		7046	* Based on the document from hardware guys the following bits
		7047	* should be set unconditionally in order to enable FBC.
		7048	* The bit 22 of 0x42000
		7049	* The bit 22 of 0x42004
		7050	* The bit 7,8,9 of 0x42020.
		7051	*/
		7052	if (IS_IRONLAKE_M(dev)) {
		7053	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		7054	I915_READ(ILK_DISPLAY_CHICKEN1) \|
		7055	ILK_FBCQ_DIS);
		7056	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7057	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7058	ILK_DPARB_GATE);
		7059	I915_WRITE(ILK_DSPCLK_GATE,
		7060	I915_READ(ILK_DSPCLK_GATE) \|
		7061	ILK_DPFC_DIS1 \|
		7062	ILK_DPFC_DIS2 \|
		7063	ILK_CLK_FBC);
		7064	}
		7065
		7066	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7067	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7068	ILK_ELPIN_409_SELECT);
		7069	I915_WRITE(_3D_CHICKEN2,
		7070	_3D_CHICKEN2_WM_READ_PIPELINED << 16 \|
		7071	_3D_CHICKEN2_WM_READ_PIPELINED);
		7072	}
		7073
		7074	static void gen6_init_clock_gating(struct drm_device *dev)
		7075	{
		7076	struct drm_i915_private *dev_priv = dev->dev_private;
		7077	int pipe;
		7078	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		7079
		7080	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		7081
		7082	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7083	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7084	ILK_ELPIN_409_SELECT);
		7085
		7086	I915_WRITE(WM3_LP_ILK, 0);
		7087	I915_WRITE(WM2_LP_ILK, 0);
		7088	I915_WRITE(WM1_LP_ILK, 0);
		7089
		7090	/*
		7091	* According to the spec the following bits should be
		7092	* set in order to enable memory self-refresh and fbc:
		7093	* The bit21 and bit22 of 0x42000
		7094	* The bit21 and bit22 of 0x42004
		7095	* The bit5 and bit7 of 0x42020
		7096	* The bit14 of 0x70180
		7097	* The bit14 of 0x71180
		7098	*/
		7099	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		7100	I915_READ(ILK_DISPLAY_CHICKEN1) \|
		7101	ILK_FBCQ_DIS \| ILK_PABSTRETCH_DIS);
		7102	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		7103	I915_READ(ILK_DISPLAY_CHICKEN2) \|
		7104	ILK_DPARB_GATE \| ILK_VSDPFD_FULL);
		7105	I915_WRITE(ILK_DSPCLK_GATE,
		7106	I915_READ(ILK_DSPCLK_GATE) \|
		7107	ILK_DPARB_CLK_GATE \|
		7108	ILK_DPFD_CLK_GATE);
		7109
		7110	for_each_pipe(pipe) {
		7111	I915_WRITE(DSPCNTR(pipe),
		7112	I915_READ(DSPCNTR(pipe)) \|
		7113	DISPPLANE_TRICKLE_FEED_DISABLE);
		7114	intel_flush_display_plane(dev_priv, pipe);
		7115	}
		7116	}
		7117
		7118	static void ivybridge_init_clock_gating(struct drm_device *dev)
		7119	{
		7120	struct drm_i915_private *dev_priv = dev->dev_private;
		7121	int pipe;
		7122	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
		7123
		7124	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
		7125
		7126	I915_WRITE(WM3_LP_ILK, 0);
		7127	I915_WRITE(WM2_LP_ILK, 0);
		7128	I915_WRITE(WM1_LP_ILK, 0);
		7129
		7130	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
		7131
		7132	for_each_pipe(pipe) {
		7133	I915_WRITE(DSPCNTR(pipe),
		7134	I915_READ(DSPCNTR(pipe)) \|
		7135	DISPPLANE_TRICKLE_FEED_DISABLE);
		7136	intel_flush_display_plane(dev_priv, pipe);
		7137	}
		7138	}
		7139
		7140	static void g4x_init_clock_gating(struct drm_device *dev)
		7141	{
		7142	struct drm_i915_private *dev_priv = dev->dev_private;
		7143	uint32_t dspclk_gate;
		7144
		7145	I915_WRITE(RENCLK_GATE_D1, 0);
		7146	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE \|
		7147	GS_UNIT_CLOCK_GATE_DISABLE \|
		7148	CL_UNIT_CLOCK_GATE_DISABLE);
		7149	I915_WRITE(RAMCLK_GATE_D, 0);
		7150	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE \|
		7151	OVRUNIT_CLOCK_GATE_DISABLE \|
		7152	OVCUNIT_CLOCK_GATE_DISABLE;
		7153	if (IS_GM45(dev))
		7154	dspclk_gate \|= DSSUNIT_CLOCK_GATE_DISABLE;
		7155	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
		7156	}
		7157
		7158	static void crestline_init_clock_gating(struct drm_device *dev)
		7159	{
		7160	struct drm_i915_private *dev_priv = dev->dev_private;
		7161
		7162	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
		7163	I915_WRITE(RENCLK_GATE_D2, 0);
		7164	I915_WRITE(DSPCLK_GATE_D, 0);
		7165	I915_WRITE(RAMCLK_GATE_D, 0);
		7166	I915_WRITE16(DEUC, 0);
		7167	}
		7168
		7169	static void broadwater_init_clock_gating(struct drm_device *dev)
		7170	{
		7171	struct drm_i915_private *dev_priv = dev->dev_private;
		7172
		7173	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE \|
		7174	I965_RCC_CLOCK_GATE_DISABLE \|
		7175	I965_RCPB_CLOCK_GATE_DISABLE \|
		7176	I965_ISC_CLOCK_GATE_DISABLE \|
		7177	I965_FBC_CLOCK_GATE_DISABLE);
		7178	I915_WRITE(RENCLK_GATE_D2, 0);
		7179	}
		7180
		7181	static void gen3_init_clock_gating(struct drm_device *dev)
		7182	{
		7183	struct drm_i915_private *dev_priv = dev->dev_private;
		7184	u32 dstate = I915_READ(D_STATE);
		7185
		7186	dstate \|= DSTATE_PLL_D3_OFF \| DSTATE_GFX_CLOCK_GATING \|
		7187	DSTATE_DOT_CLOCK_GATING;
		7188	I915_WRITE(D_STATE, dstate);
		7189	}
		7190
		7191	static void i85x_init_clock_gating(struct drm_device *dev)
		7192	{
		7193	struct drm_i915_private *dev_priv = dev->dev_private;
		7194
		7195	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
		7196	}
		7197
		7198	static void i830_init_clock_gating(struct drm_device *dev)
		7199	{
		7200	struct drm_i915_private *dev_priv = dev->dev_private;
		7201
		7202	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
		7203	}
		7204
		7205	static void ibx_init_clock_gating(struct drm_device *dev)
		7206	{
		7207	struct drm_i915_private *dev_priv = dev->dev_private;
		7208
		7209	/*
		7210	* On Ibex Peak and Cougar Point, we need to disable clock
		7211	* gating for the panel power sequencer or it will fail to
		7212	* start up when no ports are active.
		7213	*/
		7214	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
		7215	}
		7216
		7217	static void cpt_init_clock_gating(struct drm_device *dev)
		7218	{
		7219	struct drm_i915_private *dev_priv = dev->dev_private;
		7220	int pipe;
		7221
		7222	/*
		7223	* On Ibex Peak and Cougar Point, we need to disable clock
		7224	* gating for the panel power sequencer or it will fail to
		7225	* start up when no ports are active.
		7226	*/
		7227	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
		7228	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) \|
		7229	DPLS_EDP_PPS_FIX_DIS);
		7230	/* Without this, mode sets may fail silently on FDI */
		7231	for_each_pipe(pipe)
		7232	I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
		7233	}
		7234
2332	Serge	7235	static void ironlake_teardown_rc6(struct drm_device *dev)
		7236	{
		7237	struct drm_i915_private *dev_priv = dev->dev_private;
2327	Serge	7238
2332	Serge	7239	if (dev_priv->renderctx) {
		7240	// i915_gem_object_unpin(dev_priv->renderctx);
		7241	// drm_gem_object_unreference(&dev_priv->renderctx->base);
		7242	dev_priv->renderctx = NULL;
		7243	}
2327	Serge	7244
2332	Serge	7245	if (dev_priv->pwrctx) {
		7246	// i915_gem_object_unpin(dev_priv->pwrctx);
		7247	// drm_gem_object_unreference(&dev_priv->pwrctx->base);
		7248	dev_priv->pwrctx = NULL;
		7249	}
		7250	}
2327	Serge	7251
2339	Serge	7252	static void ironlake_disable_rc6(struct drm_device *dev)
		7253	{
		7254	struct drm_i915_private *dev_priv = dev->dev_private;
2330	Serge	7255
2339	Serge	7256	if (I915_READ(PWRCTXA)) {
		7257	/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
		7258	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) \| RCX_SW_EXIT);
		7259	wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
		7260	50);
2332	Serge	7261
2339	Serge	7262	I915_WRITE(PWRCTXA, 0);
		7263	POSTING_READ(PWRCTXA);
2332	Serge	7264
2339	Serge	7265	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
		7266	POSTING_READ(RSTDBYCTL);
		7267	}
2332	Serge	7268
2339	Serge	7269	ironlake_teardown_rc6(dev);
		7270	}
2332	Serge	7271
		7272	static int ironlake_setup_rc6(struct drm_device *dev)
		7273	{
		7274	struct drm_i915_private *dev_priv = dev->dev_private;
		7275
		7276	if (dev_priv->renderctx == NULL)
		7277	// dev_priv->renderctx = intel_alloc_context_page(dev);
		7278	if (!dev_priv->renderctx)
		7279	return -ENOMEM;
		7280
		7281	if (dev_priv->pwrctx == NULL)
		7282	// dev_priv->pwrctx = intel_alloc_context_page(dev);
		7283	if (!dev_priv->pwrctx) {
		7284	ironlake_teardown_rc6(dev);
		7285	return -ENOMEM;
		7286	}
		7287
		7288	return 0;
		7289	}
		7290
		7291	void ironlake_enable_rc6(struct drm_device *dev)
		7292	{
		7293	struct drm_i915_private *dev_priv = dev->dev_private;
		7294	int ret;
		7295
		7296	/* rc6 disabled by default due to repeated reports of hanging during
		7297	* boot and resume.
		7298	*/
		7299	if (!i915_enable_rc6)
		7300	return;
		7301
		7302	mutex_lock(&dev->struct_mutex);
		7303	ret = ironlake_setup_rc6(dev);
		7304	if (ret) {
		7305	mutex_unlock(&dev->struct_mutex);
		7306	return;
		7307	}
		7308
		7309	/*
		7310	* GPU can automatically power down the render unit if given a page
		7311	* to save state.
		7312	*/
		7313	#if 0
		7314	ret = BEGIN_LP_RING(6);
		7315	if (ret) {
		7316	ironlake_teardown_rc6(dev);
		7317	mutex_unlock(&dev->struct_mutex);
		7318	return;
		7319	}
		7320
		7321	OUT_RING(MI_SUSPEND_FLUSH \| MI_SUSPEND_FLUSH_EN);
		7322	OUT_RING(MI_SET_CONTEXT);
		7323	OUT_RING(dev_priv->renderctx->gtt_offset \|
		7324	MI_MM_SPACE_GTT \|
		7325	MI_SAVE_EXT_STATE_EN \|
		7326	MI_RESTORE_EXT_STATE_EN \|
		7327	MI_RESTORE_INHIBIT);
		7328	OUT_RING(MI_SUSPEND_FLUSH);
		7329	OUT_RING(MI_NOOP);
		7330	OUT_RING(MI_FLUSH);
		7331	ADVANCE_LP_RING();
		7332
		7333	/*
		7334	* Wait for the command parser to advance past MI_SET_CONTEXT. The HW
		7335	* does an implicit flush, combined with MI_FLUSH above, it should be
		7336	* safe to assume that renderctx is valid
		7337	*/
		7338	ret = intel_wait_ring_idle(LP_RING(dev_priv));
		7339	if (ret) {
		7340	DRM_ERROR("failed to enable ironlake power power savings\n");
		7341	ironlake_teardown_rc6(dev);
		7342	mutex_unlock(&dev->struct_mutex);
		7343	return;
		7344	}
		7345	#endif
		7346
		7347	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);
		7348	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
		7349	mutex_unlock(&dev->struct_mutex);
		7350	}
		7351
2330	Serge	7352	void intel_init_clock_gating(struct drm_device *dev)
		7353	{
		7354	struct drm_i915_private *dev_priv = dev->dev_private;
		7355
		7356	dev_priv->display.init_clock_gating(dev);
		7357
		7358	if (dev_priv->display.init_pch_clock_gating)
		7359	dev_priv->display.init_pch_clock_gating(dev);
		7360	}
		7361
2327	Serge	7362	/* Set up chip specific display functions */
		7363	static void intel_init_display(struct drm_device *dev)
		7364	{
		7365	struct drm_i915_private *dev_priv = dev->dev_private;
		7366
		7367	/* We always want a DPMS function */
		7368	if (HAS_PCH_SPLIT(dev)) {
		7369	dev_priv->display.dpms = ironlake_crtc_dpms;
		7370	dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
		7371	dev_priv->display.update_plane = ironlake_update_plane;
		7372	} else {
		7373	dev_priv->display.dpms = i9xx_crtc_dpms;
		7374	dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		7375	dev_priv->display.update_plane = i9xx_update_plane;
		7376	}
		7377
		7378	if (I915_HAS_FBC(dev)) {
		7379	if (HAS_PCH_SPLIT(dev)) {
		7380	dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
		7381	dev_priv->display.enable_fbc = ironlake_enable_fbc;
		7382	dev_priv->display.disable_fbc = ironlake_disable_fbc;
		7383	} else if (IS_GM45(dev)) {
		7384	dev_priv->display.fbc_enabled = g4x_fbc_enabled;
		7385	dev_priv->display.enable_fbc = g4x_enable_fbc;
		7386	dev_priv->display.disable_fbc = g4x_disable_fbc;
		7387	} else if (IS_CRESTLINE(dev)) {
		7388	dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
		7389	dev_priv->display.enable_fbc = i8xx_enable_fbc;
		7390	dev_priv->display.disable_fbc = i8xx_disable_fbc;
		7391	}
		7392	/* 855GM needs testing */
		7393	}
		7394
		7395	/* Returns the core display clock speed */
		7396	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
		7397	dev_priv->display.get_display_clock_speed =
		7398	i945_get_display_clock_speed;
		7399	else if (IS_I915G(dev))
		7400	dev_priv->display.get_display_clock_speed =
		7401	i915_get_display_clock_speed;
		7402	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
		7403	dev_priv->display.get_display_clock_speed =
		7404	i9xx_misc_get_display_clock_speed;
		7405	else if (IS_I915GM(dev))
		7406	dev_priv->display.get_display_clock_speed =
		7407	i915gm_get_display_clock_speed;
		7408	else if (IS_I865G(dev))
		7409	dev_priv->display.get_display_clock_speed =
		7410	i865_get_display_clock_speed;
		7411	else if (IS_I85X(dev))
		7412	dev_priv->display.get_display_clock_speed =
		7413	i855_get_display_clock_speed;
		7414	else /* 852, 830 */
		7415	dev_priv->display.get_display_clock_speed =
		7416	i830_get_display_clock_speed;
		7417
		7418	/* For FIFO watermark updates */
		7419	if (HAS_PCH_SPLIT(dev)) {
		7420	if (HAS_PCH_IBX(dev))
		7421	dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
		7422	else if (HAS_PCH_CPT(dev))
		7423	dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
		7424
		7425	if (IS_GEN5(dev)) {
		7426	if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
		7427	dev_priv->display.update_wm = ironlake_update_wm;
		7428	else {
		7429	DRM_DEBUG_KMS("Failed to get proper latency. "
		7430	"Disable CxSR\n");
		7431	dev_priv->display.update_wm = NULL;
		7432	}
		7433	dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
		7434	dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
		7435	} else if (IS_GEN6(dev)) {
		7436	if (SNB_READ_WM0_LATENCY()) {
		7437	dev_priv->display.update_wm = sandybridge_update_wm;
		7438	} else {
		7439	DRM_DEBUG_KMS("Failed to read display plane latency. "
		7440	"Disable CxSR\n");
		7441	dev_priv->display.update_wm = NULL;
		7442	}
		7443	dev_priv->display.fdi_link_train = gen6_fdi_link_train;
		7444	dev_priv->display.init_clock_gating = gen6_init_clock_gating;
		7445	} else if (IS_IVYBRIDGE(dev)) {
		7446	/* FIXME: detect B0+ stepping and use auto training */
		7447	dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
		7448	if (SNB_READ_WM0_LATENCY()) {
		7449	dev_priv->display.update_wm = sandybridge_update_wm;
		7450	} else {
		7451	DRM_DEBUG_KMS("Failed to read display plane latency. "
		7452	"Disable CxSR\n");
		7453	dev_priv->display.update_wm = NULL;
		7454	}
		7455	dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
		7456
		7457	} else
		7458	dev_priv->display.update_wm = NULL;
		7459	} else if (IS_PINEVIEW(dev)) {
		7460	if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
		7461	dev_priv->is_ddr3,
		7462	dev_priv->fsb_freq,
		7463	dev_priv->mem_freq)) {
		7464	DRM_INFO("failed to find known CxSR latency "
		7465	"(found ddr%s fsb freq %d, mem freq %d), "
		7466	"disabling CxSR\n",
		7467	(dev_priv->is_ddr3 == 1) ? "3": "2",
		7468	dev_priv->fsb_freq, dev_priv->mem_freq);
		7469	/* Disable CxSR and never update its watermark again */
		7470	pineview_disable_cxsr(dev);
		7471	dev_priv->display.update_wm = NULL;
		7472	} else
		7473	dev_priv->display.update_wm = pineview_update_wm;
		7474	dev_priv->display.init_clock_gating = gen3_init_clock_gating;
		7475	} else if (IS_G4X(dev)) {
		7476	dev_priv->display.update_wm = g4x_update_wm;
		7477	dev_priv->display.init_clock_gating = g4x_init_clock_gating;
		7478	} else if (IS_GEN4(dev)) {
		7479	dev_priv->display.update_wm = i965_update_wm;
		7480	if (IS_CRESTLINE(dev))
		7481	dev_priv->display.init_clock_gating = crestline_init_clock_gating;
		7482	else if (IS_BROADWATER(dev))
		7483	dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
		7484	} else if (IS_GEN3(dev)) {
		7485	dev_priv->display.update_wm = i9xx_update_wm;
		7486	dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
		7487	dev_priv->display.init_clock_gating = gen3_init_clock_gating;
		7488	} else if (IS_I865G(dev)) {
		7489	dev_priv->display.update_wm = i830_update_wm;
		7490	dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		7491	dev_priv->display.get_fifo_size = i830_get_fifo_size;
		7492	} else if (IS_I85X(dev)) {
		7493	dev_priv->display.update_wm = i9xx_update_wm;
		7494	dev_priv->display.get_fifo_size = i85x_get_fifo_size;
		7495	dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		7496	} else {
		7497	dev_priv->display.update_wm = i830_update_wm;
		7498	dev_priv->display.init_clock_gating = i830_init_clock_gating;
		7499	if (IS_845G(dev))
		7500	dev_priv->display.get_fifo_size = i845_get_fifo_size;
		7501	else
		7502	dev_priv->display.get_fifo_size = i830_get_fifo_size;
		7503	}
		7504
		7505	/* Default just returns -ENODEV to indicate unsupported */
		7506	// dev_priv->display.queue_flip = intel_default_queue_flip;
		7507
		7508	#if 0
		7509	switch (INTEL_INFO(dev)->gen) {
		7510	case 2:
		7511	dev_priv->display.queue_flip = intel_gen2_queue_flip;
		7512	break;
		7513
		7514	case 3:
		7515	dev_priv->display.queue_flip = intel_gen3_queue_flip;
		7516	break;
		7517
		7518	case 4:
		7519	case 5:
		7520	dev_priv->display.queue_flip = intel_gen4_queue_flip;
		7521	break;
		7522
		7523	case 6:
		7524	dev_priv->display.queue_flip = intel_gen6_queue_flip;
		7525	break;
		7526	case 7:
		7527	dev_priv->display.queue_flip = intel_gen7_queue_flip;
		7528	break;
		7529	}
		7530	#endif
		7531	}
		7532
		7533	/*
		7534	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
		7535	* resume, or other times. This quirk makes sure that's the case for
		7536	* affected systems.
		7537	*/
		7538	static void quirk_pipea_force (struct drm_device *dev)
		7539	{
		7540	struct drm_i915_private *dev_priv = dev->dev_private;
		7541
		7542	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
		7543	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
		7544	}
		7545
		7546	/*
		7547	* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
		7548	*/
		7549	static void quirk_ssc_force_disable(struct drm_device *dev)
		7550	{
		7551	struct drm_i915_private *dev_priv = dev->dev_private;
		7552	dev_priv->quirks \|= QUIRK_LVDS_SSC_DISABLE;
		7553	}
		7554
		7555	struct intel_quirk {
		7556	int device;
		7557	int subsystem_vendor;
		7558	int subsystem_device;
		7559	void (hook)(struct drm_device dev);
		7560	};
		7561
		7562	struct intel_quirk intel_quirks[] = {
		7563	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
		7564	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
		7565	/* HP Mini needs pipe A force quirk (LP: #322104) */
		7566	{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },
		7567
		7568	/* Thinkpad R31 needs pipe A force quirk */
		7569	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
		7570	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
		7571	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
		7572
		7573	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
		7574	{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },
		7575	/* ThinkPad X40 needs pipe A force quirk */
		7576
		7577	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
		7578	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
		7579
		7580	/* 855 & before need to leave pipe A & dpll A up */
		7581	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7582	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
		7583
		7584	/* Lenovo U160 cannot use SSC on LVDS */
		7585	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
		7586
		7587	/* Sony Vaio Y cannot use SSC on LVDS */
		7588	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
		7589	};
		7590
		7591	static void intel_init_quirks(struct drm_device *dev)
		7592	{
		7593	struct pci_dev *d = dev->pdev;
		7594	int i;
		7595
		7596	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		7597	struct intel_quirk *q = &intel_quirks[i];
		7598
		7599	if (d->device == q->device &&
		7600	(d->subsystem_vendor == q->subsystem_vendor \|\|
		7601	q->subsystem_vendor == PCI_ANY_ID) &&
		7602	(d->subsystem_device == q->subsystem_device \|\|
		7603	q->subsystem_device == PCI_ANY_ID))
		7604	q->hook(dev);
		7605	}
		7606	}
		7607
2330	Serge	7608	/* Disable the VGA plane that we never use */
		7609	static void i915_disable_vga(struct drm_device *dev)
		7610	{
		7611	struct drm_i915_private *dev_priv = dev->dev_private;
		7612	u8 sr1;
		7613	u32 vga_reg;
2327	Serge	7614
2330	Serge	7615	if (HAS_PCH_SPLIT(dev))
		7616	vga_reg = CPU_VGACNTRL;
		7617	else
		7618	vga_reg = VGACNTRL;
		7619
		7620	// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		7621	out8(VGA_SR_INDEX, 1);
		7622	sr1 = in8(VGA_SR_DATA);
		7623	out8(VGA_SR_DATA,sr1 \| 1<<5);
		7624	// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
		7625	udelay(300);
		7626
		7627	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
		7628	POSTING_READ(vga_reg);
		7629	}
		7630
2327	Serge	7631	void intel_modeset_init(struct drm_device *dev)
		7632	{
		7633	struct drm_i915_private *dev_priv = dev->dev_private;
		7634	int i;
		7635
		7636	drm_mode_config_init(dev);
		7637
		7638	dev->mode_config.min_width = 0;
		7639	dev->mode_config.min_height = 0;
		7640
		7641	dev->mode_config.funcs = (void *)&intel_mode_funcs;
		7642
		7643	intel_init_quirks(dev);
		7644
		7645	intel_init_display(dev);
		7646
		7647	if (IS_GEN2(dev)) {
		7648	dev->mode_config.max_width = 2048;
		7649	dev->mode_config.max_height = 2048;
		7650	} else if (IS_GEN3(dev)) {
		7651	dev->mode_config.max_width = 4096;
		7652	dev->mode_config.max_height = 4096;
		7653	} else {
		7654	dev->mode_config.max_width = 8192;
		7655	dev->mode_config.max_height = 8192;
		7656	}
		7657	dev->mode_config.fb_base = get_bus_addr();
		7658
		7659	DRM_DEBUG_KMS("%d display pipe%s available.\n",
		7660	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
		7661
		7662	for (i = 0; i < dev_priv->num_pipe; i++) {
		7663	intel_crtc_init(dev, i);
		7664	}
		7665
		7666	/* Just disable it once at startup */
		7667	i915_disable_vga(dev);
		7668	intel_setup_outputs(dev);
		7669
		7670	intel_init_clock_gating(dev);
		7671
		7672	if (IS_IRONLAKE_M(dev)) {
		7673	ironlake_enable_drps(dev);
		7674	intel_init_emon(dev);
		7675	}
		7676
		7677	if (IS_GEN6(dev) \|\| IS_GEN7(dev)) {
		7678	gen6_enable_rps(dev_priv);
		7679	gen6_update_ring_freq(dev_priv);
		7680	}
		7681
2332	Serge	7682	// INIT_WORK(&dev_priv->idle_work, intel_idle_update);
		7683	// setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
		7684	// (unsigned long)dev);
2330	Serge	7685	}
2327	Serge	7686
2332	Serge	7687	void intel_modeset_gem_init(struct drm_device *dev)
		7688	{
		7689	if (IS_IRONLAKE_M(dev))
		7690	ironlake_enable_rc6(dev);
2330	Serge	7691
2332	Serge	7692	// intel_setup_overlay(dev);
		7693	}
		7694
		7695
2330	Serge	7696	/*
		7697	* Return which encoder is currently attached for connector.
		7698	*/
		7699	struct drm_encoder intel_best_encoder(struct drm_connector connector)
		7700	{
		7701	return &intel_attached_encoder(connector)->base;
2327	Serge	7702	}
		7703
2330	Serge	7704	void intel_connector_attach_encoder(struct intel_connector *connector,
		7705	struct intel_encoder *encoder)
		7706	{
		7707	connector->encoder = encoder;
		7708	drm_mode_connector_attach_encoder(&connector->base,
		7709	&encoder->base);
		7710	}
2327	Serge	7711
2330	Serge	7712

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(root)/drivers/video/drm/i915/intel_display.c – Rev 2339