WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_ddi.c

Rev	Author	Line No.	Line
3031	serge	1	/*
		2	* Copyright © 2012 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eugeni Dodonov
		25	*
		26	*/
		27
		28	#include "i915_drv.h"
		29	#include "intel_drv.h"
		30
5354	serge	31	struct ddi_buf_trans {
		32	u32 trans1; /* balance leg enable, de-emph level */
		33	u32 trans2; /* vref sel, vswing */
6084	serge	34	u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
5354	serge	35	};
		36
3031	serge	37	/* HDMI/DVI modes ignore everything but the last 2 items. So we share
		38	* them for both DP and FDI transports, allowing those ports to
		39	* automatically adapt to HDMI connections as well
		40	*/
5354	serge	41	static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
6084	serge	42	{ 0x00FFFFFF, 0x0006000E, 0x0 },
		43	{ 0x00D75FFF, 0x0005000A, 0x0 },
		44	{ 0x00C30FFF, 0x00040006, 0x0 },
		45	{ 0x80AAAFFF, 0x000B0000, 0x0 },
		46	{ 0x00FFFFFF, 0x0005000A, 0x0 },
		47	{ 0x00D75FFF, 0x000C0004, 0x0 },
		48	{ 0x80C30FFF, 0x000B0000, 0x0 },
		49	{ 0x00FFFFFF, 0x00040006, 0x0 },
		50	{ 0x80D75FFF, 0x000B0000, 0x0 },
3031	serge	51	};
		52
5354	serge	53	static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
6084	serge	54	{ 0x00FFFFFF, 0x0007000E, 0x0 },
		55	{ 0x00D75FFF, 0x000F000A, 0x0 },
		56	{ 0x00C30FFF, 0x00060006, 0x0 },
		57	{ 0x00AAAFFF, 0x001E0000, 0x0 },
		58	{ 0x00FFFFFF, 0x000F000A, 0x0 },
		59	{ 0x00D75FFF, 0x00160004, 0x0 },
		60	{ 0x00C30FFF, 0x001E0000, 0x0 },
		61	{ 0x00FFFFFF, 0x00060006, 0x0 },
		62	{ 0x00D75FFF, 0x001E0000, 0x0 },
3031	serge	63	};
		64
5354	serge	65	static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
		66	/* Idx NT mV d T mV d db */
6084	serge	67	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
		68	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
		69	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
		70	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
		71	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
		72	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
		73	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
		74	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
		75	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
		76	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
		77	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
		78	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
4560	Serge	79	};
		80
5354	serge	81	static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
6084	serge	82	{ 0x00FFFFFF, 0x00000012, 0x0 },
		83	{ 0x00EBAFFF, 0x00020011, 0x0 },
		84	{ 0x00C71FFF, 0x0006000F, 0x0 },
		85	{ 0x00AAAFFF, 0x000E000A, 0x0 },
		86	{ 0x00FFFFFF, 0x00020011, 0x0 },
		87	{ 0x00DB6FFF, 0x0005000F, 0x0 },
		88	{ 0x00BEEFFF, 0x000A000C, 0x0 },
		89	{ 0x00FFFFFF, 0x0005000F, 0x0 },
		90	{ 0x00DB6FFF, 0x000A000C, 0x0 },
4560	Serge	91	};
		92
5354	serge	93	static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
6084	serge	94	{ 0x00FFFFFF, 0x0007000E, 0x0 },
		95	{ 0x00D75FFF, 0x000E000A, 0x0 },
		96	{ 0x00BEFFFF, 0x00140006, 0x0 },
		97	{ 0x80B2CFFF, 0x001B0002, 0x0 },
		98	{ 0x00FFFFFF, 0x000E000A, 0x0 },
		99	{ 0x00DB6FFF, 0x00160005, 0x0 },
		100	{ 0x80C71FFF, 0x001A0002, 0x0 },
		101	{ 0x00F7DFFF, 0x00180004, 0x0 },
		102	{ 0x80D75FFF, 0x001B0002, 0x0 },
4560	Serge	103	};
		104
5354	serge	105	static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
6084	serge	106	{ 0x00FFFFFF, 0x0001000E, 0x0 },
		107	{ 0x00D75FFF, 0x0004000A, 0x0 },
		108	{ 0x00C30FFF, 0x00070006, 0x0 },
		109	{ 0x00AAAFFF, 0x000C0000, 0x0 },
		110	{ 0x00FFFFFF, 0x0004000A, 0x0 },
		111	{ 0x00D75FFF, 0x00090004, 0x0 },
		112	{ 0x00C30FFF, 0x000C0000, 0x0 },
		113	{ 0x00FFFFFF, 0x00070006, 0x0 },
		114	{ 0x00D75FFF, 0x000C0000, 0x0 },
4560	Serge	115	};
		116
5354	serge	117	static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
		118	/* Idx NT mV d T mV df db */
6084	serge	119	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
		120	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
		121	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
		122	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
		123	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
		124	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
		125	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
		126	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
		127	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
		128	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
5354	serge	129	};
		130
6084	serge	131	/* Skylake H and S */
5354	serge	132	static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6084	serge	133	{ 0x00002016, 0x000000A0, 0x0 },
		134	{ 0x00005012, 0x0000009B, 0x0 },
		135	{ 0x00007011, 0x00000088, 0x0 },
6937	serge	136	{ 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
6084	serge	137	{ 0x00002016, 0x0000009B, 0x0 },
		138	{ 0x00005012, 0x00000088, 0x0 },
6937	serge	139	{ 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
6084	serge	140	{ 0x00002016, 0x000000DF, 0x0 },
6937	serge	141	{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
5354	serge	142	};
		143
6084	serge	144	/* Skylake U */
		145	static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
		146	{ 0x0000201B, 0x000000A2, 0x0 },
		147	{ 0x00005012, 0x00000088, 0x0 },
		148	{ 0x00007011, 0x00000087, 0x0 },
6937	serge	149	{ 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
6084	serge	150	{ 0x0000201B, 0x0000009D, 0x0 },
6937	serge	151	{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
		152	{ 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
6084	serge	153	{ 0x00002016, 0x00000088, 0x0 },
6937	serge	154	{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
6084	serge	155	};
		156
		157	/* Skylake Y */
		158	static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
		159	{ 0x00000018, 0x000000A2, 0x0 },
		160	{ 0x00005012, 0x00000088, 0x0 },
		161	{ 0x00007011, 0x00000087, 0x0 },
6937	serge	162	{ 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
6084	serge	163	{ 0x00000018, 0x0000009D, 0x0 },
6937	serge	164	{ 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
		165	{ 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
6084	serge	166	{ 0x00000018, 0x00000088, 0x0 },
6937	serge	167	{ 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
6084	serge	168	};
		169
		170	/*
		171	* Skylake H and S
		172	* eDP 1.4 low vswing translation parameters
		173	*/
		174	static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
		175	{ 0x00000018, 0x000000A8, 0x0 },
		176	{ 0x00004013, 0x000000A9, 0x0 },
		177	{ 0x00007011, 0x000000A2, 0x0 },
		178	{ 0x00009010, 0x0000009C, 0x0 },
		179	{ 0x00000018, 0x000000A9, 0x0 },
		180	{ 0x00006013, 0x000000A2, 0x0 },
		181	{ 0x00007011, 0x000000A6, 0x0 },
		182	{ 0x00000018, 0x000000AB, 0x0 },
		183	{ 0x00007013, 0x0000009F, 0x0 },
		184	{ 0x00000018, 0x000000DF, 0x0 },
		185	};
		186
		187	/*
		188	* Skylake U
		189	* eDP 1.4 low vswing translation parameters
		190	*/
		191	static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
		192	{ 0x00000018, 0x000000A8, 0x0 },
		193	{ 0x00004013, 0x000000A9, 0x0 },
		194	{ 0x00007011, 0x000000A2, 0x0 },
		195	{ 0x00009010, 0x0000009C, 0x0 },
		196	{ 0x00000018, 0x000000A9, 0x0 },
		197	{ 0x00006013, 0x000000A2, 0x0 },
		198	{ 0x00007011, 0x000000A6, 0x0 },
		199	{ 0x00002016, 0x000000AB, 0x0 },
		200	{ 0x00005013, 0x0000009F, 0x0 },
		201	{ 0x00000018, 0x000000DF, 0x0 },
		202	};
		203
		204	/*
		205	* Skylake Y
		206	* eDP 1.4 low vswing translation parameters
		207	*/
		208	static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
		209	{ 0x00000018, 0x000000A8, 0x0 },
		210	{ 0x00004013, 0x000000AB, 0x0 },
		211	{ 0x00007011, 0x000000A4, 0x0 },
		212	{ 0x00009010, 0x000000DF, 0x0 },
		213	{ 0x00000018, 0x000000AA, 0x0 },
		214	{ 0x00006013, 0x000000A4, 0x0 },
		215	{ 0x00007011, 0x0000009D, 0x0 },
		216	{ 0x00000018, 0x000000A0, 0x0 },
		217	{ 0x00006012, 0x000000DF, 0x0 },
		218	{ 0x00000018, 0x0000008A, 0x0 },
		219	};
		220
		221	/* Skylake U, H and S */
5354	serge	222	static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
6084	serge	223	{ 0x00000018, 0x000000AC, 0x0 },
		224	{ 0x00005012, 0x0000009D, 0x0 },
		225	{ 0x00007011, 0x00000088, 0x0 },
		226	{ 0x00000018, 0x000000A1, 0x0 },
		227	{ 0x00000018, 0x00000098, 0x0 },
		228	{ 0x00004013, 0x00000088, 0x0 },
		229	{ 0x00006012, 0x00000087, 0x0 },
		230	{ 0x00000018, 0x000000DF, 0x0 },
		231	{ 0x00003015, 0x00000087, 0x0 }, /* Default */
		232	{ 0x00003015, 0x000000C7, 0x0 },
		233	{ 0x00000018, 0x000000C7, 0x0 },
5354	serge	234	};
		235
6084	serge	236	/* Skylake Y */
		237	static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
		238	{ 0x00000018, 0x000000A1, 0x0 },
		239	{ 0x00005012, 0x000000DF, 0x0 },
		240	{ 0x00007011, 0x00000084, 0x0 },
		241	{ 0x00000018, 0x000000A4, 0x0 },
		242	{ 0x00000018, 0x0000009D, 0x0 },
		243	{ 0x00004013, 0x00000080, 0x0 },
		244	{ 0x00006013, 0x000000C7, 0x0 },
		245	{ 0x00000018, 0x0000008A, 0x0 },
		246	{ 0x00003015, 0x000000C7, 0x0 }, /* Default */
		247	{ 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
		248	{ 0x00000018, 0x000000C7, 0x0 },
		249	};
		250
		251	struct bxt_ddi_buf_trans {
		252	u32 margin; /* swing value */
		253	u32 scale; /* scale value */
		254	u32 enable; /* scale enable */
		255	u32 deemphasis;
		256	bool default_index; /* true if the entry represents default value */
		257	};
		258
		259	static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
		260	/* Idx NT mV diff db */
		261	{ 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
		262	{ 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
		263	{ 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
		264	{ 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
		265	{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
		266	{ 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
		267	{ 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
		268	{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
		269	{ 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
		270	{ 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
		271	};
		272
		273	static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
		274	/* Idx NT mV diff db */
		275	{ 26, 0, 0, 128, false }, /* 0: 200 0 */
		276	{ 38, 0, 0, 112, false }, /* 1: 200 1.5 */
		277	{ 48, 0, 0, 96, false }, /* 2: 200 4 */
		278	{ 54, 0, 0, 69, false }, /* 3: 200 6 */
		279	{ 32, 0, 0, 128, false }, /* 4: 250 0 */
		280	{ 48, 0, 0, 104, false }, /* 5: 250 1.5 */
		281	{ 54, 0, 0, 85, false }, /* 6: 250 4 */
		282	{ 43, 0, 0, 128, false }, /* 7: 300 0 */
		283	{ 54, 0, 0, 101, false }, /* 8: 300 1.5 */
		284	{ 48, 0, 0, 128, false }, /* 9: 300 0 */
		285	};
		286
		287	/* BSpec has 2 recommended values - entries 0 and 8.
		288	* Using the entry with higher vswing.
		289	*/
		290	static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
		291	/* Idx NT mV diff db */
		292	{ 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
		293	{ 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
		294	{ 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
		295	{ 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
		296	{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
		297	{ 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
		298	{ 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
		299	{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
		300	{ 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
		301	{ 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
		302	};
		303
		304	static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
		305	enum port port, int type);
		306
		307	static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
		308	struct intel_digital_port **dig_port,
		309	enum port *port)
3243	Serge	310	{
		311	struct drm_encoder *encoder = &intel_encoder->base;
		312
6084	serge	313	switch (intel_encoder->type) {
		314	case INTEL_OUTPUT_DP_MST:
		315	*dig_port = enc_to_mst(encoder)->primary;
		316	port = (dig_port)->port;
		317	break;
		318	case INTEL_OUTPUT_DISPLAYPORT:
		319	case INTEL_OUTPUT_EDP:
		320	case INTEL_OUTPUT_HDMI:
		321	case INTEL_OUTPUT_UNKNOWN:
		322	*dig_port = enc_to_dig_port(encoder);
		323	port = (dig_port)->port;
		324	break;
		325	case INTEL_OUTPUT_ANALOG:
		326	*dig_port = NULL;
		327	*port = PORT_E;
		328	break;
		329	default:
		330	WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
		331	break;
		332	}
		333	}
3243	Serge	334
6084	serge	335	enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
		336	{
		337	struct intel_digital_port *dig_port;
		338	enum port port;
3243	Serge	339
6084	serge	340	ddi_get_encoder_port(intel_encoder, &dig_port, &port);
		341
		342	return port;
		343	}
		344
		345	static bool
		346	intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
		347	{
6937	serge	348	return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
6084	serge	349	}
		350
		351	static const struct ddi_buf_trans skl_get_buf_trans_dp(struct drm_device dev,
		352	int *n_entries)
		353	{
		354	const struct ddi_buf_trans *ddi_translations;
		355
6937	serge	356	if (IS_SKL_ULX(dev) \|\| IS_KBL_ULX(dev)) {
6084	serge	357	ddi_translations = skl_y_ddi_translations_dp;
		358	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
6937	serge	359	} else if (IS_SKL_ULT(dev) \|\| IS_KBL_ULT(dev)) {
6084	serge	360	ddi_translations = skl_u_ddi_translations_dp;
		361	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
3243	Serge	362	} else {
6084	serge	363	ddi_translations = skl_ddi_translations_dp;
		364	*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
3243	Serge	365	}
6084	serge	366
		367	return ddi_translations;
3243	Serge	368	}
		369
6084	serge	370	static const struct ddi_buf_trans skl_get_buf_trans_edp(struct drm_device dev,
		371	int *n_entries)
		372	{
		373	struct drm_i915_private *dev_priv = dev->dev_private;
		374	const struct ddi_buf_trans *ddi_translations;
		375
6937	serge	376	if (IS_SKL_ULX(dev) \|\| IS_KBL_ULX(dev)) {
6084	serge	377	if (dev_priv->edp_low_vswing) {
		378	ddi_translations = skl_y_ddi_translations_edp;
		379	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
		380	} else {
		381	ddi_translations = skl_y_ddi_translations_dp;
		382	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
		383	}
6937	serge	384	} else if (IS_SKL_ULT(dev) \|\| IS_KBL_ULT(dev)) {
6084	serge	385	if (dev_priv->edp_low_vswing) {
		386	ddi_translations = skl_u_ddi_translations_edp;
		387	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
		388	} else {
		389	ddi_translations = skl_u_ddi_translations_dp;
		390	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
		391	}
		392	} else {
		393	if (dev_priv->edp_low_vswing) {
		394	ddi_translations = skl_ddi_translations_edp;
		395	*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
		396	} else {
		397	ddi_translations = skl_ddi_translations_dp;
		398	*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
		399	}
		400	}
		401
		402	return ddi_translations;
		403	}
		404
		405	static const struct ddi_buf_trans *
		406	skl_get_buf_trans_hdmi(struct drm_device *dev,
		407	int *n_entries)
		408	{
		409	const struct ddi_buf_trans *ddi_translations;
		410
6937	serge	411	if (IS_SKL_ULX(dev) \|\| IS_KBL_ULX(dev)) {
6084	serge	412	ddi_translations = skl_y_ddi_translations_hdmi;
		413	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
		414	} else {
		415	ddi_translations = skl_ddi_translations_hdmi;
		416	*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
		417	}
		418
		419	return ddi_translations;
		420	}
		421
4560	Serge	422	/*
		423	* Starting with Haswell, DDI port buffers must be programmed with correct
		424	* values in advance. The buffer values are different for FDI and DP modes,
3031	serge	425	* but the HDMI/DVI fields are shared among those. So we program the DDI
		426	* in either FDI or DP modes only, as HDMI connections will work with both
		427	* of those
		428	*/
6084	serge	429	static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
		430	bool supports_hdmi)
3031	serge	431	{
		432	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	433	u32 iboost_bit = 0;
		434	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
		435	size;
4560	Serge	436	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
5354	serge	437	const struct ddi_buf_trans *ddi_translations_fdi;
		438	const struct ddi_buf_trans *ddi_translations_dp;
		439	const struct ddi_buf_trans *ddi_translations_edp;
		440	const struct ddi_buf_trans *ddi_translations_hdmi;
		441	const struct ddi_buf_trans *ddi_translations;
3031	serge	442
6084	serge	443	if (IS_BROXTON(dev)) {
		444	if (!supports_hdmi)
		445	return;
		446
		447	/* Vswing programming for HDMI */
		448	bxt_ddi_vswing_sequence(dev, hdmi_level, port,
		449	INTEL_OUTPUT_HDMI);
		450	return;
6937	serge	451	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
5354	serge	452	ddi_translations_fdi = NULL;
6084	serge	453	ddi_translations_dp =
		454	skl_get_buf_trans_dp(dev, &n_dp_entries);
		455	ddi_translations_edp =
		456	skl_get_buf_trans_edp(dev, &n_edp_entries);
		457	ddi_translations_hdmi =
		458	skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
		459	hdmi_default_entry = 8;
		460	/* If we're boosting the current, set bit 31 of trans1 */
		461	if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level \|\|
		462	dev_priv->vbt.ddi_port_info[port].dp_boost_level)
		463	iboost_bit = 1<<31;
5354	serge	464	} else if (IS_BROADWELL(dev)) {
4560	Serge	465	ddi_translations_fdi = bdw_ddi_translations_fdi;
		466	ddi_translations_dp = bdw_ddi_translations_dp;
6660	serge	467
		468	if (dev_priv->edp_low_vswing) {
4560	Serge	469	ddi_translations_edp = bdw_ddi_translations_edp;
6660	serge	470	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		471	} else {
		472	ddi_translations_edp = bdw_ddi_translations_dp;
		473	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		474	}
		475
5354	serge	476	ddi_translations_hdmi = bdw_ddi_translations_hdmi;
6660	serge	477
6084	serge	478	n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
5354	serge	479	n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
6084	serge	480	hdmi_default_entry = 7;
4560	Serge	481	} else if (IS_HASWELL(dev)) {
		482	ddi_translations_fdi = hsw_ddi_translations_fdi;
		483	ddi_translations_dp = hsw_ddi_translations_dp;
		484	ddi_translations_edp = hsw_ddi_translations_dp;
5354	serge	485	ddi_translations_hdmi = hsw_ddi_translations_hdmi;
6084	serge	486	n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
5354	serge	487	n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
6084	serge	488	hdmi_default_entry = 6;
4560	Serge	489	} else {
		490	WARN(1, "ddi translation table missing\n");
		491	ddi_translations_edp = bdw_ddi_translations_dp;
		492	ddi_translations_fdi = bdw_ddi_translations_fdi;
		493	ddi_translations_dp = bdw_ddi_translations_dp;
5354	serge	494	ddi_translations_hdmi = bdw_ddi_translations_hdmi;
6084	serge	495	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		496	n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
5354	serge	497	n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
6084	serge	498	hdmi_default_entry = 7;
4560	Serge	499	}
		500
		501	switch (port) {
		502	case PORT_A:
		503	ddi_translations = ddi_translations_edp;
6084	serge	504	size = n_edp_entries;
4560	Serge	505	break;
		506	case PORT_B:
		507	case PORT_C:
		508	ddi_translations = ddi_translations_dp;
6084	serge	509	size = n_dp_entries;
4560	Serge	510	break;
		511	case PORT_D:
6084	serge	512	if (intel_dp_is_edp(dev, PORT_D)) {
4560	Serge	513	ddi_translations = ddi_translations_edp;
6084	serge	514	size = n_edp_entries;
		515	} else {
4560	Serge	516	ddi_translations = ddi_translations_dp;
6084	serge	517	size = n_dp_entries;
		518	}
4560	Serge	519	break;
		520	case PORT_E:
5354	serge	521	if (ddi_translations_fdi)
6084	serge	522	ddi_translations = ddi_translations_fdi;
5354	serge	523	else
		524	ddi_translations = ddi_translations_dp;
6084	serge	525	size = n_dp_entries;
4560	Serge	526	break;
		527	default:
		528	BUG();
		529	}
		530
6084	serge	531	for (i = 0; i < size; i++) {
		532	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
		533	ddi_translations[i].trans1 \| iboost_bit);
		534	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
		535	ddi_translations[i].trans2);
3031	serge	536	}
5354	serge	537
6084	serge	538	if (!supports_hdmi)
		539	return;
		540
5354	serge	541	/* Choose a good default if VBT is badly populated */
		542	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN \|\|
		543	hdmi_level >= n_hdmi_entries)
6084	serge	544	hdmi_level = hdmi_default_entry;
5354	serge	545
4560	Serge	546	/* Entry 9 is for HDMI: */
6084	serge	547	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
		548	ddi_translations_hdmi[hdmi_level].trans1 \| iboost_bit);
		549	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
		550	ddi_translations_hdmi[hdmi_level].trans2);
3031	serge	551	}
		552
		553	/* Program DDI buffers translations for DP. By default, program ports A-D in DP
		554	* mode and port E for FDI.
		555	*/
		556	void intel_prepare_ddi(struct drm_device *dev)
		557	{
6084	serge	558	struct intel_encoder *intel_encoder;
		559	bool visited[I915_MAX_PORTS] = { 0, };
3031	serge	560
3480	Serge	561	if (!HAS_DDI(dev))
		562	return;
		563
6084	serge	564	for_each_intel_encoder(dev, intel_encoder) {
		565	struct intel_digital_port *intel_dig_port;
		566	enum port port;
		567	bool supports_hdmi;
		568
		569	if (intel_encoder->type == INTEL_OUTPUT_DSI)
		570	continue;
		571
		572	ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
		573	if (visited[port])
		574	continue;
		575
		576	supports_hdmi = intel_dig_port &&
		577	intel_dig_port_supports_hdmi(intel_dig_port);
		578
		579	intel_prepare_ddi_buffers(dev, port, supports_hdmi);
		580	visited[port] = true;
		581	}
3031	serge	582	}
		583
3243	Serge	584	static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
		585	enum port port)
		586	{
6937	serge	587	i915_reg_t reg = DDI_BUF_CTL(port);
3243	Serge	588	int i;
3031	serge	589
6084	serge	590	for (i = 0; i < 16; i++) {
3243	Serge	591	udelay(1);
		592	if (I915_READ(reg) & DDI_BUF_IS_IDLE)
		593	return;
		594	}
		595	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
		596	}
		597
3031	serge	598	/* Starting with Haswell, different DDI ports can work in FDI mode for
		599	* connection to the PCH-located connectors. For this, it is necessary to train
		600	* both the DDI port and PCH receiver for the desired DDI buffer settings.
		601	*
		602	* The recommended port to work in FDI mode is DDI E, which we use here. Also,
		603	* please note that when FDI mode is active on DDI E, it shares 2 lines with
		604	* DDI A (which is used for eDP)
		605	*/
		606
		607	void hsw_fdi_link_train(struct drm_crtc *crtc)
		608	{
		609	struct drm_device *dev = crtc->dev;
		610	struct drm_i915_private *dev_priv = dev->dev_private;
		611	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	612	u32 temp, i, rx_ctl_val;
3031	serge	613
3243	Serge	614	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
		615	* mode set "sequence for CRT port" document:
		616	* - TP1 to TP2 time with the default value
		617	* - FDI delay to 90h
4104	Serge	618	*
		619	* WaFDIAutoLinkSetTimingOverrride:hsw
3243	Serge	620	*/
6084	serge	621	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) \|
3243	Serge	622	FDI_RX_PWRDN_LANE0_VAL(2) \|
		623	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
3031	serge	624
3243	Serge	625	/* Enable the PCH Receiver FDI PLL */
3480	Serge	626	rx_ctl_val = dev_priv->fdi_rx_config \| FDI_RX_ENHANCE_FRAME_ENABLE \|
4104	Serge	627	FDI_RX_PLL_ENABLE \|
6084	serge	628	FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
		629	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		630	POSTING_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	631	udelay(220);
3031	serge	632
3243	Serge	633	/* Switch from Rawclk to PCDclk */
		634	rx_ctl_val \|= FDI_PCDCLK;
6084	serge	635	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
3031	serge	636
3243	Serge	637	/* Configure Port Clock Select */
6084	serge	638	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
		639	WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
3243	Serge	640
		641	/* Start the training iterating through available voltages and emphasis,
		642	* testing each value twice. */
5354	serge	643	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
3031	serge	644	/* Configure DP_TP_CTL with auto-training */
		645	I915_WRITE(DP_TP_CTL(PORT_E),
		646	DP_TP_CTL_FDI_AUTOTRAIN \|
		647	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		648	DP_TP_CTL_LINK_TRAIN_PAT1 \|
		649	DP_TP_CTL_ENABLE);
		650
3480	Serge	651	/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		652	* DDI E does not support port reversal, the functionality is
		653	* achieved on the PCH side in FDI_RX_CTL, so no need to set the
		654	* port reversal bit */
3031	serge	655	I915_WRITE(DDI_BUF_CTL(PORT_E),
6084	serge	656	DDI_BUF_CTL_ENABLE \|
		657	((intel_crtc->config->fdi_lanes - 1) << 1) \|
5354	serge	658	DDI_BUF_TRANS_SELECT(i / 2));
3243	Serge	659	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	660
		661	udelay(600);
		662
3243	Serge	663	/* Program PCH FDI Receiver TU */
6084	serge	664	I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
3031	serge	665
3243	Serge	666	/* Enable PCH FDI Receiver with auto-training */
		667	rx_ctl_val \|= FDI_RX_ENABLE \| FDI_LINK_TRAIN_AUTO;
6084	serge	668	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		669	POSTING_READ(FDI_RX_CTL(PIPE_A));
3031	serge	670
3243	Serge	671	/* Wait for FDI receiver lane calibration */
		672	udelay(30);
		673
		674	/* Unset FDI_RX_MISC pwrdn lanes */
6084	serge	675	temp = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	676	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
6084	serge	677	I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		678	POSTING_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	679
		680	/* Wait for FDI auto training time */
		681	udelay(5);
		682
3031	serge	683	temp = I915_READ(DP_TP_STATUS(PORT_E));
		684	if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
3243	Serge	685	DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
6937	serge	686	break;
		687	}
3031	serge	688
6937	serge	689	/*
		690	* Leave things enabled even if we failed to train FDI.
		691	* Results in less fireworks from the state checker.
		692	*/
		693	if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
		694	DRM_ERROR("FDI link training failed!\n");
		695	break;
3031	serge	696	}
		697
3243	Serge	698	temp = I915_READ(DDI_BUF_CTL(PORT_E));
		699	temp &= ~DDI_BUF_CTL_ENABLE;
		700	I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		701	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	702
3243	Serge	703	/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
		704	temp = I915_READ(DP_TP_CTL(PORT_E));
		705	temp &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		706	temp \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		707	I915_WRITE(DP_TP_CTL(PORT_E), temp);
		708	POSTING_READ(DP_TP_CTL(PORT_E));
3031	serge	709
3243	Serge	710	intel_wait_ddi_buf_idle(dev_priv, PORT_E);
		711
		712	rx_ctl_val &= ~FDI_RX_ENABLE;
6084	serge	713	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		714	POSTING_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	715
		716	/* Reset FDI_RX_MISC pwrdn lanes */
6084	serge	717	temp = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	718	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		719	temp \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
6084	serge	720	I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		721	POSTING_READ(FDI_RX_MISC(PIPE_A));
3031	serge	722	}
3243	Serge	723
6937	serge	724	/* Enable normal pixel sending for FDI */
		725	I915_WRITE(DP_TP_CTL(PORT_E),
		726	DP_TP_CTL_FDI_AUTOTRAIN \|
		727	DP_TP_CTL_LINK_TRAIN_NORMAL \|
		728	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		729	DP_TP_CTL_ENABLE);
3031	serge	730	}
		731
5060	serge	732	void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
3031	serge	733	{
5060	serge	734	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		735	struct intel_digital_port *intel_dig_port =
		736	enc_to_dig_port(&encoder->base);
3031	serge	737
5060	serge	738	intel_dp->DP = intel_dig_port->saved_port_bits \|
5354	serge	739	DDI_BUF_CTL_ENABLE \| DDI_BUF_TRANS_SELECT(0);
5060	serge	740	intel_dp->DP \|= DDI_PORT_WIDTH(intel_dp->lane_count);
3243	Serge	741	}
		742
		743	static struct intel_encoder *
		744	intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
		745	{
		746	struct drm_device *dev = crtc->dev;
		747	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		748	struct intel_encoder intel_encoder, ret = NULL;
		749	int num_encoders = 0;
		750
		751	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		752	ret = intel_encoder;
		753	num_encoders++;
		754	}
		755
		756	if (num_encoders != 1)
4104	Serge	757	WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
		758	pipe_name(intel_crtc->pipe));
3243	Serge	759
		760	BUG_ON(ret == NULL);
		761	return ret;
		762	}
		763
6084	serge	764	struct intel_encoder *
		765	intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
5354	serge	766	{
6084	serge	767	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
		768	struct intel_encoder *ret = NULL;
		769	struct drm_atomic_state *state;
		770	struct drm_connector *connector;
		771	struct drm_connector_state *connector_state;
5354	serge	772	int num_encoders = 0;
6084	serge	773	int i;
5354	serge	774
6084	serge	775	state = crtc_state->base.state;
		776
		777	for_each_connector_in_state(state, connector, connector_state, i) {
		778	if (connector_state->crtc != crtc_state->base.crtc)
		779	continue;
		780
		781	ret = to_intel_encoder(connector_state->best_encoder);
		782	num_encoders++;
5354	serge	783	}
		784
		785	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
		786	pipe_name(crtc->pipe));
		787
		788	BUG_ON(ret == NULL);
		789	return ret;
		790	}
		791
4104	Serge	792	#define LC_FREQ 2700
5354	serge	793	#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
4104	Serge	794
		795	#define P_MIN 2
		796	#define P_MAX 64
		797	#define P_INC 2
		798
		799	/* Constraints for PLL good behavior */
		800	#define REF_MIN 48
		801	#define REF_MAX 400
		802	#define VCO_MIN 2400
		803	#define VCO_MAX 4800
		804
5354	serge	805	#define abs_diff(a, b) ({ \
		806	typeof(a) __a = (a); \
		807	typeof(b) __b = (b); \
		808	(void) (&__a == &__b); \
		809	__a > __b ? (__a - __b) : (__b - __a); })
4104	Serge	810
6084	serge	811	struct hsw_wrpll_rnp {
4104	Serge	812	unsigned p, n2, r2;
		813	};
		814
6084	serge	815	static unsigned hsw_wrpll_get_budget_for_freq(int clock)
3243	Serge	816	{
4104	Serge	817	unsigned budget;
3243	Serge	818
4104	Serge	819	switch (clock) {
		820	case 25175000:
		821	case 25200000:
		822	case 27000000:
		823	case 27027000:
		824	case 37762500:
		825	case 37800000:
		826	case 40500000:
		827	case 40541000:
		828	case 54000000:
		829	case 54054000:
		830	case 59341000:
		831	case 59400000:
		832	case 72000000:
		833	case 74176000:
		834	case 74250000:
		835	case 81000000:
		836	case 81081000:
		837	case 89012000:
		838	case 89100000:
		839	case 108000000:
		840	case 108108000:
		841	case 111264000:
		842	case 111375000:
		843	case 148352000:
		844	case 148500000:
		845	case 162000000:
		846	case 162162000:
		847	case 222525000:
		848	case 222750000:
		849	case 296703000:
		850	case 297000000:
		851	budget = 0;
		852	break;
		853	case 233500000:
		854	case 245250000:
		855	case 247750000:
		856	case 253250000:
		857	case 298000000:
		858	budget = 1500;
		859	break;
		860	case 169128000:
		861	case 169500000:
		862	case 179500000:
		863	case 202000000:
		864	budget = 2000;
		865	break;
		866	case 256250000:
		867	case 262500000:
		868	case 270000000:
		869	case 272500000:
		870	case 273750000:
		871	case 280750000:
		872	case 281250000:
		873	case 286000000:
		874	case 291750000:
		875	budget = 4000;
		876	break;
		877	case 267250000:
		878	case 268500000:
		879	budget = 5000;
6084	serge	880	break;
4104	Serge	881	default:
		882	budget = 1000;
		883	break;
		884	}
3031	serge	885
4104	Serge	886	return budget;
		887	}
3031	serge	888
6084	serge	889	static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
		890	unsigned r2, unsigned n2, unsigned p,
		891	struct hsw_wrpll_rnp *best)
4104	Serge	892	{
		893	uint64_t a, b, c, d, diff, diff_best;
3031	serge	894
4104	Serge	895	/* No best (r,n,p) yet */
		896	if (best->p == 0) {
		897	best->p = p;
		898	best->n2 = n2;
		899	best->r2 = r2;
		900	return;
		901	}
3031	serge	902
4104	Serge	903	/*
		904	* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
		905	* freq2k.
		906	*
		907	* delta = 1e6 *
		908	* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
		909	* freq2k;
		910	*
		911	* and we would like delta <= budget.
		912	*
		913	* If the discrepancy is above the PPM-based budget, always prefer to
		914	* improve upon the previous solution. However, if you're within the
		915	* budget, try to maximize Ref * VCO, that is N / (P * R^2).
		916	*/
		917	a = freq2k * budget * p * r2;
		918	b = freq2k * budget * best->p * best->r2;
5354	serge	919	diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
		920	diff_best = abs_diff(freq2k * best->p * best->r2,
		921	LC_FREQ_2K * best->n2);
4104	Serge	922	c = 1000000 * diff;
		923	d = 1000000 * diff_best;
		924
		925	if (a < c && b < d) {
		926	/* If both are above the budget, pick the closer */
		927	if (best->p * best->r2 * diff < p * r2 * diff_best) {
		928	best->p = p;
		929	best->n2 = n2;
		930	best->r2 = r2;
		931	}
		932	} else if (a >= c && b < d) {
		933	/* If A is below the threshold but B is above it? Update. */
		934	best->p = p;
		935	best->n2 = n2;
		936	best->r2 = r2;
		937	} else if (a >= c && b >= d) {
		938	/* Both are below the limit, so pick the higher n2/(r2r2) /
		939	if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
		940	best->p = p;
		941	best->n2 = n2;
		942	best->r2 = r2;
		943	}
		944	}
		945	/* Otherwise a < c && b >= d, do nothing */
3243	Serge	946	}
3031	serge	947
6937	serge	948	static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
		949	i915_reg_t reg)
5060	serge	950	{
		951	int refclk = LC_FREQ;
		952	int n, p, r;
		953	u32 wrpll;
		954
		955	wrpll = I915_READ(reg);
		956	switch (wrpll & WRPLL_PLL_REF_MASK) {
		957	case WRPLL_PLL_SSC:
		958	case WRPLL_PLL_NON_SSC:
		959	/*
		960	* We could calculate spread here, but our checking
		961	* code only cares about 5% accuracy, and spread is a max of
		962	* 0.5% downspread.
		963	*/
		964	refclk = 135;
		965	break;
		966	case WRPLL_PLL_LCPLL:
		967	refclk = LC_FREQ;
		968	break;
		969	default:
		970	WARN(1, "bad wrpll refclk\n");
		971	return 0;
		972	}
		973
		974	r = wrpll & WRPLL_DIVIDER_REF_MASK;
		975	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
		976	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
		977
		978	/* Convert to KHz, p & r have a fixed point portion */
		979	return (refclk * n * 100) / (p * r);
		980	}
		981
5354	serge	982	static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
		983	uint32_t dpll)
		984	{
6937	serge	985	i915_reg_t cfgcr1_reg, cfgcr2_reg;
5354	serge	986	uint32_t cfgcr1_val, cfgcr2_val;
		987	uint32_t p0, p1, p2, dco_freq;
		988
6084	serge	989	cfgcr1_reg = DPLL_CFGCR1(dpll);
		990	cfgcr2_reg = DPLL_CFGCR2(dpll);
5354	serge	991
		992	cfgcr1_val = I915_READ(cfgcr1_reg);
		993	cfgcr2_val = I915_READ(cfgcr2_reg);
		994
		995	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
		996	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
		997
		998	if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
		999	p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
		1000	else
		1001	p1 = 1;
		1002
		1003
		1004	switch (p0) {
		1005	case DPLL_CFGCR2_PDIV_1:
		1006	p0 = 1;
		1007	break;
		1008	case DPLL_CFGCR2_PDIV_2:
		1009	p0 = 2;
		1010	break;
		1011	case DPLL_CFGCR2_PDIV_3:
		1012	p0 = 3;
		1013	break;
		1014	case DPLL_CFGCR2_PDIV_7:
		1015	p0 = 7;
		1016	break;
		1017	}
		1018
		1019	switch (p2) {
		1020	case DPLL_CFGCR2_KDIV_5:
		1021	p2 = 5;
		1022	break;
		1023	case DPLL_CFGCR2_KDIV_2:
		1024	p2 = 2;
		1025	break;
		1026	case DPLL_CFGCR2_KDIV_3:
		1027	p2 = 3;
		1028	break;
		1029	case DPLL_CFGCR2_KDIV_1:
		1030	p2 = 1;
		1031	break;
		1032	}
		1033
		1034	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
		1035
		1036	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1037	1000) / 0x8000;
		1038
		1039	return dco_freq / (p0 * p1 * p2 * 5);
		1040	}
		1041
6084	serge	1042	static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
		1043	{
		1044	int dotclock;
5354	serge	1045
6084	serge	1046	if (pipe_config->has_pch_encoder)
		1047	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
		1048	&pipe_config->fdi_m_n);
		1049	else if (pipe_config->has_dp_encoder)
		1050	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
		1051	&pipe_config->dp_m_n);
		1052	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
		1053	dotclock = pipe_config->port_clock * 2 / 3;
		1054	else
		1055	dotclock = pipe_config->port_clock;
		1056
		1057	if (pipe_config->pixel_multiplier)
		1058	dotclock /= pipe_config->pixel_multiplier;
		1059
		1060	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
		1061	}
		1062
5354	serge	1063	static void skl_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1064	struct intel_crtc_state *pipe_config)
5060	serge	1065	{
		1066	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1067	int link_clock = 0;
5354	serge	1068	uint32_t dpll_ctl1, dpll;
		1069
		1070	dpll = pipe_config->ddi_pll_sel;
		1071
		1072	dpll_ctl1 = I915_READ(DPLL_CTRL1);
		1073
		1074	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		1075	link_clock = skl_calc_wrpll_link(dev_priv, dpll);
		1076	} else {
6084	serge	1077	link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
		1078	link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
5354	serge	1079
		1080	switch (link_clock) {
6084	serge	1081	case DPLL_CTRL1_LINK_RATE_810:
5354	serge	1082	link_clock = 81000;
		1083	break;
6084	serge	1084	case DPLL_CTRL1_LINK_RATE_1080:
		1085	link_clock = 108000;
		1086	break;
		1087	case DPLL_CTRL1_LINK_RATE_1350:
5354	serge	1088	link_clock = 135000;
		1089	break;
6084	serge	1090	case DPLL_CTRL1_LINK_RATE_1620:
		1091	link_clock = 162000;
		1092	break;
		1093	case DPLL_CTRL1_LINK_RATE_2160:
		1094	link_clock = 216000;
		1095	break;
		1096	case DPLL_CTRL1_LINK_RATE_2700:
5354	serge	1097	link_clock = 270000;
		1098	break;
		1099	default:
		1100	WARN(1, "Unsupported link rate\n");
		1101	break;
		1102	}
		1103	link_clock *= 2;
		1104	}
		1105
		1106	pipe_config->port_clock = link_clock;
		1107
6084	serge	1108	ddi_dotclock_get(pipe_config);
5354	serge	1109	}
		1110
		1111	static void hsw_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1112	struct intel_crtc_state *pipe_config)
5354	serge	1113	{
		1114	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1115	int link_clock = 0;
5060	serge	1116	u32 val, pll;
		1117
		1118	val = pipe_config->ddi_pll_sel;
		1119	switch (val & PORT_CLK_SEL_MASK) {
		1120	case PORT_CLK_SEL_LCPLL_810:
		1121	link_clock = 81000;
		1122	break;
		1123	case PORT_CLK_SEL_LCPLL_1350:
		1124	link_clock = 135000;
		1125	break;
		1126	case PORT_CLK_SEL_LCPLL_2700:
		1127	link_clock = 270000;
		1128	break;
		1129	case PORT_CLK_SEL_WRPLL1:
6937	serge	1130	link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
5060	serge	1131	break;
		1132	case PORT_CLK_SEL_WRPLL2:
6937	serge	1133	link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
5060	serge	1134	break;
		1135	case PORT_CLK_SEL_SPLL:
		1136	pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		1137	if (pll == SPLL_PLL_FREQ_810MHz)
		1138	link_clock = 81000;
		1139	else if (pll == SPLL_PLL_FREQ_1350MHz)
		1140	link_clock = 135000;
		1141	else if (pll == SPLL_PLL_FREQ_2700MHz)
		1142	link_clock = 270000;
		1143	else {
		1144	WARN(1, "bad spll freq\n");
		1145	return;
		1146	}
		1147	break;
		1148	default:
		1149	WARN(1, "bad port clock sel\n");
		1150	return;
		1151	}
		1152
		1153	pipe_config->port_clock = link_clock * 2;
		1154
6084	serge	1155	ddi_dotclock_get(pipe_config);
5060	serge	1156	}
		1157
6084	serge	1158	static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
		1159	enum intel_dpll_id dpll)
		1160	{
		1161	struct intel_shared_dpll *pll;
		1162	struct intel_dpll_hw_state *state;
		1163	intel_clock_t clock;
		1164
		1165	/* For DDI ports we always use a shared PLL. */
		1166	if (WARN_ON(dpll == DPLL_ID_PRIVATE))
		1167	return 0;
		1168
		1169	pll = &dev_priv->shared_dplls[dpll];
		1170	state = &pll->config.hw_state;
		1171
		1172	clock.m1 = 2;
		1173	clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
		1174	if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
		1175	clock.m2 \|= state->pll2 & PORT_PLL_M2_FRAC_MASK;
		1176	clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
		1177	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
		1178	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
		1179
		1180	return chv_calc_dpll_params(100000, &clock);
		1181	}
		1182
		1183	static void bxt_ddi_clock_get(struct intel_encoder *encoder,
		1184	struct intel_crtc_state *pipe_config)
		1185	{
		1186	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1187	enum port port = intel_ddi_get_encoder_port(encoder);
		1188	uint32_t dpll = port;
		1189
		1190	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
		1191
		1192	ddi_dotclock_get(pipe_config);
		1193	}
		1194
5354	serge	1195	void intel_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1196	struct intel_crtc_state *pipe_config)
5354	serge	1197	{
6084	serge	1198	struct drm_device *dev = encoder->base.dev;
		1199
		1200	if (INTEL_INFO(dev)->gen <= 8)
		1201	hsw_ddi_clock_get(encoder, pipe_config);
6937	serge	1202	else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
6084	serge	1203	skl_ddi_clock_get(encoder, pipe_config);
		1204	else if (IS_BROXTON(dev))
		1205	bxt_ddi_clock_get(encoder, pipe_config);
5354	serge	1206	}
		1207
4104	Serge	1208	static void
5354	serge	1209	hsw_ddi_calculate_wrpll(int clock /* in Hz */,
6084	serge	1210	unsigned r2_out, unsigned n2_out, unsigned *p_out)
3243	Serge	1211	{
4104	Serge	1212	uint64_t freq2k;
		1213	unsigned p, n2, r2;
6084	serge	1214	struct hsw_wrpll_rnp best = { 0, 0, 0 };
4104	Serge	1215	unsigned budget;
		1216
		1217	freq2k = clock / 100;
		1218
6084	serge	1219	budget = hsw_wrpll_get_budget_for_freq(clock);
4104	Serge	1220
		1221	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
		1222	* and directly pass the LC PLL to it. */
		1223	if (freq2k == 5400000) {
		1224	*n2_out = 2;
		1225	*p_out = 1;
		1226	*r2_out = 2;
		1227	return;
		1228	}
		1229
		1230	/*
		1231	* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
		1232	* the WR PLL.
		1233	*
		1234	* We want R so that REF_MIN <= Ref <= REF_MAX.
		1235	* Injecting R2 = 2 * R gives:
		1236	* REF_MAX * r2 > LC_FREQ * 2 and
		1237	* REF_MIN * r2 < LC_FREQ * 2
		1238	*
		1239	* Which means the desired boundaries for r2 are:
		1240	* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
		1241	*
		1242	*/
		1243	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
		1244	r2 <= LC_FREQ * 2 / REF_MIN;
		1245	r2++) {
		1246
		1247	/*
		1248	* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
		1249	*
		1250	* Once again we want VCO_MIN <= VCO <= VCO_MAX.
		1251	* Injecting R2 = 2 * R and N2 = 2 * N, we get:
		1252	* VCO_MAX * r2 > n2 * LC_FREQ and
		1253	* VCO_MIN * r2 < n2 * LC_FREQ)
		1254	*
		1255	* Which means the desired boundaries for n2 are:
		1256	* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
		1257	*/
		1258	for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
		1259	n2 <= VCO_MAX * r2 / LC_FREQ;
		1260	n2++) {
		1261
		1262	for (p = P_MIN; p <= P_MAX; p += P_INC)
6084	serge	1263	hsw_wrpll_update_rnp(freq2k, budget,
		1264	r2, n2, p, &best);
4104	Serge	1265	}
		1266	}
		1267
		1268	*n2_out = best.n2;
		1269	*p_out = best.p;
		1270	*r2_out = best.r2;
		1271	}
		1272
5354	serge	1273	static bool
		1274	hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
6084	serge	1275	struct intel_crtc_state *crtc_state,
		1276	struct intel_encoder *intel_encoder)
4104	Serge	1277	{
6084	serge	1278	int clock = crtc_state->port_clock;
		1279
5354	serge	1280	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5060	serge	1281	struct intel_shared_dpll *pll;
		1282	uint32_t val;
4104	Serge	1283	unsigned p, n2, r2;
3243	Serge	1284
5354	serge	1285	hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
4560	Serge	1286
5060	serge	1287	val = WRPLL_PLL_ENABLE \| WRPLL_PLL_LCPLL \|
4560	Serge	1288	WRPLL_DIVIDER_REFERENCE(r2) \| WRPLL_DIVIDER_FEEDBACK(n2) \|
		1289	WRPLL_DIVIDER_POST(p);
		1290
6084	serge	1291	memset(&crtc_state->dpll_hw_state, 0,
		1292	sizeof(crtc_state->dpll_hw_state));
3243	Serge	1293
6084	serge	1294	crtc_state->dpll_hw_state.wrpll = val;
		1295
		1296	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
5060	serge	1297	if (pll == NULL) {
		1298	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1299	pipe_name(intel_crtc->pipe));
3746	Serge	1300	return false;
3243	Serge	1301	}
		1302
6084	serge	1303	crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
		1304	} else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
		1305	struct drm_atomic_state *state = crtc_state->base.state;
		1306	struct intel_shared_dpll_config *spll =
		1307	&intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
		1308
		1309	if (spll->crtc_mask &&
		1310	WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
		1311	return false;
		1312
		1313	crtc_state->shared_dpll = DPLL_ID_SPLL;
		1314	spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
		1315	spll->crtc_mask \|= 1 << intel_crtc->pipe;
3243	Serge	1316	}
		1317
		1318	return true;
		1319	}
3031	serge	1320
6084	serge	1321	struct skl_wrpll_context {
		1322	uint64_t min_deviation; /* current minimal deviation */
		1323	uint64_t central_freq; /* chosen central freq */
		1324	uint64_t dco_freq; /* chosen dco freq */
		1325	unsigned int p; /* chosen divider */
		1326	};
		1327
		1328	static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
		1329	{
		1330	memset(ctx, 0, sizeof(*ctx));
		1331
		1332	ctx->min_deviation = U64_MAX;
		1333	}
		1334
		1335	/* DCO freq must be within +1%/-6% of the DCO central freq */
		1336	#define SKL_DCO_MAX_PDEVIATION 100
		1337	#define SKL_DCO_MAX_NDEVIATION 600
		1338
		1339	static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
		1340	uint64_t central_freq,
		1341	uint64_t dco_freq,
		1342	unsigned int divider)
		1343	{
		1344	uint64_t deviation;
		1345
		1346	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
		1347	central_freq);
		1348
		1349	/* positive deviation */
		1350	if (dco_freq >= central_freq) {
		1351	if (deviation < SKL_DCO_MAX_PDEVIATION &&
		1352	deviation < ctx->min_deviation) {
		1353	ctx->min_deviation = deviation;
		1354	ctx->central_freq = central_freq;
		1355	ctx->dco_freq = dco_freq;
		1356	ctx->p = divider;
		1357	}
		1358	/* negative deviation */
		1359	} else if (deviation < SKL_DCO_MAX_NDEVIATION &&
		1360	deviation < ctx->min_deviation) {
		1361	ctx->min_deviation = deviation;
		1362	ctx->central_freq = central_freq;
		1363	ctx->dco_freq = dco_freq;
		1364	ctx->p = divider;
		1365	}
		1366	}
		1367
		1368	static void skl_wrpll_get_multipliers(unsigned int p,
		1369	unsigned int p0 / out */,
		1370	unsigned int p1 / out */,
		1371	unsigned int p2 / out */)
		1372	{
		1373	/* even dividers */
		1374	if (p % 2 == 0) {
		1375	unsigned int half = p / 2;
		1376
		1377	if (half == 1 \|\| half == 2 \|\| half == 3 \|\| half == 5) {
		1378	*p0 = 2;
		1379	*p1 = 1;
		1380	*p2 = half;
		1381	} else if (half % 2 == 0) {
		1382	*p0 = 2;
		1383	*p1 = half / 2;
		1384	*p2 = 2;
		1385	} else if (half % 3 == 0) {
		1386	*p0 = 3;
		1387	*p1 = half / 3;
		1388	*p2 = 2;
		1389	} else if (half % 7 == 0) {
		1390	*p0 = 7;
		1391	*p1 = half / 7;
		1392	*p2 = 2;
		1393	}
		1394	} else if (p == 3 \|\| p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
		1395	*p0 = 3;
		1396	*p1 = 1;
		1397	*p2 = p / 3;
		1398	} else if (p == 5 \|\| p == 7) {
		1399	*p0 = p;
		1400	*p1 = 1;
		1401	*p2 = 1;
		1402	} else if (p == 15) {
		1403	*p0 = 3;
		1404	*p1 = 1;
		1405	*p2 = 5;
		1406	} else if (p == 21) {
		1407	*p0 = 7;
		1408	*p1 = 1;
		1409	*p2 = 3;
		1410	} else if (p == 35) {
		1411	*p0 = 7;
		1412	*p1 = 1;
		1413	*p2 = 5;
		1414	}
		1415	}
		1416
5354	serge	1417	struct skl_wrpll_params {
		1418	uint32_t dco_fraction;
		1419	uint32_t dco_integer;
		1420	uint32_t qdiv_ratio;
		1421	uint32_t qdiv_mode;
		1422	uint32_t kdiv;
		1423	uint32_t pdiv;
		1424	uint32_t central_freq;
		1425	};
		1426
6084	serge	1427	static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
		1428	uint64_t afe_clock,
		1429	uint64_t central_freq,
		1430	uint32_t p0, uint32_t p1, uint32_t p2)
		1431	{
		1432	uint64_t dco_freq;
		1433
		1434	switch (central_freq) {
		1435	case 9600000000ULL:
		1436	params->central_freq = 0;
		1437	break;
		1438	case 9000000000ULL:
		1439	params->central_freq = 1;
		1440	break;
		1441	case 8400000000ULL:
		1442	params->central_freq = 3;
		1443	}
		1444
		1445	switch (p0) {
		1446	case 1:
		1447	params->pdiv = 0;
		1448	break;
		1449	case 2:
		1450	params->pdiv = 1;
		1451	break;
		1452	case 3:
		1453	params->pdiv = 2;
		1454	break;
		1455	case 7:
		1456	params->pdiv = 4;
		1457	break;
		1458	default:
		1459	WARN(1, "Incorrect PDiv\n");
		1460	}
		1461
		1462	switch (p2) {
		1463	case 5:
		1464	params->kdiv = 0;
		1465	break;
		1466	case 2:
		1467	params->kdiv = 1;
		1468	break;
		1469	case 3:
		1470	params->kdiv = 2;
		1471	break;
		1472	case 1:
		1473	params->kdiv = 3;
		1474	break;
		1475	default:
		1476	WARN(1, "Incorrect KDiv\n");
		1477	}
		1478
		1479	params->qdiv_ratio = p1;
		1480	params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
		1481
		1482	dco_freq = p0 * p1 * p2 * afe_clock;
		1483
		1484	/*
		1485	* Intermediate values are in Hz.
		1486	* Divide by MHz to match bsepc
		1487	*/
		1488	params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
		1489	params->dco_fraction =
		1490	div_u64((div_u64(dco_freq, 24) -
		1491	params->dco_integer * MHz(1)) * 0x8000, MHz(1));
		1492	}
		1493
		1494	static bool
5354	serge	1495	skl_ddi_calculate_wrpll(int clock /* in Hz */,
		1496	struct skl_wrpll_params *wrpll_params)
		1497	{
		1498	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
		1499	uint64_t dco_central_freq[3] = {8400000000ULL,
		1500	9000000000ULL,
		1501	9600000000ULL};
6084	serge	1502	static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
		1503	24, 28, 30, 32, 36, 40, 42, 44,
		1504	48, 52, 54, 56, 60, 64, 66, 68,
		1505	70, 72, 76, 78, 80, 84, 88, 90,
		1506	92, 96, 98 };
		1507	static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
		1508	static const struct {
		1509	const int *list;
		1510	int n_dividers;
		1511	} dividers[] = {
		1512	{ even_dividers, ARRAY_SIZE(even_dividers) },
		1513	{ odd_dividers, ARRAY_SIZE(odd_dividers) },
		1514	};
		1515	struct skl_wrpll_context ctx;
		1516	unsigned int dco, d, i;
		1517	unsigned int p0, p1, p2;
5354	serge	1518
6084	serge	1519	skl_wrpll_context_init(&ctx);
5354	serge	1520
6084	serge	1521	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
		1522	for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
		1523	for (i = 0; i < dividers[d].n_dividers; i++) {
		1524	unsigned int p = dividers[d].list[i];
		1525	uint64_t dco_freq = p * afe_clock;
5354	serge	1526
6084	serge	1527	skl_wrpll_try_divider(&ctx,
		1528	dco_central_freq[dco],
		1529	dco_freq,
		1530	p);
		1531	/*
		1532	* Skip the remaining dividers if we're sure to
		1533	* have found the definitive divider, we can't
		1534	* improve a 0 deviation.
		1535	*/
		1536	if (ctx.min_deviation == 0)
		1537	goto skip_remaining_dividers;
5354	serge	1538	}
		1539	}
		1540
6084	serge	1541	skip_remaining_dividers:
		1542	/*
		1543	* If a solution is found with an even divider, prefer
		1544	* this one.
		1545	*/
		1546	if (d == 0 && ctx.p)
		1547	break;
		1548	}
5354	serge	1549
6084	serge	1550	if (!ctx.p) {
		1551	DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
		1552	return false;
5354	serge	1553	}
		1554
6084	serge	1555	/*
		1556	* gcc incorrectly analyses that these can be used without being
		1557	* initialized. To be fair, it's hard to guess.
		1558	*/
		1559	p0 = p1 = p2 = 0;
		1560	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
		1561	skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
		1562	p0, p1, p2);
5354	serge	1563
6084	serge	1564	return true;
5354	serge	1565	}
		1566
		1567	static bool
		1568	skl_ddi_pll_select(struct intel_crtc *intel_crtc,
6084	serge	1569	struct intel_crtc_state *crtc_state,
		1570	struct intel_encoder *intel_encoder)
5354	serge	1571	{
		1572	struct intel_shared_dpll *pll;
		1573	uint32_t ctrl1, cfgcr1, cfgcr2;
6084	serge	1574	int clock = crtc_state->port_clock;
5354	serge	1575
		1576	/*
		1577	* See comment in intel_dpll_hw_state to understand why we always use 0
		1578	* as the DPLL id in this function.
		1579	*/
		1580
		1581	ctrl1 = DPLL_CTRL1_OVERRIDE(0);
		1582
		1583	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		1584	struct skl_wrpll_params wrpll_params = { 0, };
		1585
		1586	ctrl1 \|= DPLL_CTRL1_HDMI_MODE(0);
		1587
6084	serge	1588	if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
		1589	return false;
5354	serge	1590
		1591	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE \|
		1592	DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) \|
		1593	wrpll_params.dco_integer;
		1594
		1595	cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) \|
		1596	DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) \|
		1597	DPLL_CFGCR2_KDIV(wrpll_params.kdiv) \|
		1598	DPLL_CFGCR2_PDIV(wrpll_params.pdiv) \|
		1599	wrpll_params.central_freq;
6320	serge	1600	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1601	intel_encoder->type == INTEL_OUTPUT_DP_MST) {
6084	serge	1602	switch (crtc_state->port_clock / 2) {
		1603	case 81000:
		1604	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
5354	serge	1605	break;
6084	serge	1606	case 135000:
		1607	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
5354	serge	1608	break;
6084	serge	1609	case 270000:
		1610	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
5354	serge	1611	break;
		1612	}
		1613
		1614	cfgcr1 = cfgcr2 = 0;
		1615	} else /* eDP */
		1616	return true;
		1617
6084	serge	1618	memset(&crtc_state->dpll_hw_state, 0,
		1619	sizeof(crtc_state->dpll_hw_state));
5354	serge	1620
6084	serge	1621	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
		1622	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
		1623	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
		1624
		1625	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
5354	serge	1626	if (pll == NULL) {
		1627	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1628	pipe_name(intel_crtc->pipe));
		1629	return false;
		1630	}
		1631
		1632	/* shared DPLL id 0 is DPLL 1 */
6084	serge	1633	crtc_state->ddi_pll_sel = pll->id + 1;
5354	serge	1634
		1635	return true;
		1636	}
		1637
6084	serge	1638	/* bxt clock parameters */
		1639	struct bxt_clk_div {
		1640	int clock;
		1641	uint32_t p1;
		1642	uint32_t p2;
		1643	uint32_t m2_int;
		1644	uint32_t m2_frac;
		1645	bool m2_frac_en;
		1646	uint32_t n;
		1647	};
		1648
		1649	/* pre-calculated values for DP linkrates */
		1650	static const struct bxt_clk_div bxt_dp_clk_val[] = {
		1651	{162000, 4, 2, 32, 1677722, 1, 1},
		1652	{270000, 4, 1, 27, 0, 0, 1},
		1653	{540000, 2, 1, 27, 0, 0, 1},
		1654	{216000, 3, 2, 32, 1677722, 1, 1},
		1655	{243000, 4, 1, 24, 1258291, 1, 1},
		1656	{324000, 4, 1, 32, 1677722, 1, 1},
		1657	{432000, 3, 1, 32, 1677722, 1, 1}
		1658	};
		1659
		1660	static bool
		1661	bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
		1662	struct intel_crtc_state *crtc_state,
		1663	struct intel_encoder *intel_encoder)
		1664	{
		1665	struct intel_shared_dpll *pll;
		1666	struct bxt_clk_div clk_div = {0};
		1667	int vco = 0;
		1668	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
		1669	uint32_t lanestagger;
		1670	int clock = crtc_state->port_clock;
		1671
		1672	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		1673	intel_clock_t best_clock;
		1674
		1675	/* Calculate HDMI div */
		1676	/*
		1677	* FIXME: tie the following calculation into
		1678	* i9xx_crtc_compute_clock
		1679	*/
		1680	if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
		1681	DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
		1682	clock, pipe_name(intel_crtc->pipe));
		1683	return false;
		1684	}
		1685
		1686	clk_div.p1 = best_clock.p1;
		1687	clk_div.p2 = best_clock.p2;
		1688	WARN_ON(best_clock.m1 != 2);
		1689	clk_div.n = best_clock.n;
		1690	clk_div.m2_int = best_clock.m2 >> 22;
		1691	clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
		1692	clk_div.m2_frac_en = clk_div.m2_frac != 0;
		1693
		1694	vco = best_clock.vco;
		1695	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1696	intel_encoder->type == INTEL_OUTPUT_EDP) {
		1697	int i;
		1698
		1699	clk_div = bxt_dp_clk_val[0];
		1700	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
		1701	if (bxt_dp_clk_val[i].clock == clock) {
		1702	clk_div = bxt_dp_clk_val[i];
		1703	break;
		1704	}
		1705	}
		1706	vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
		1707	}
		1708
		1709	if (vco >= 6200000 && vco <= 6700000) {
		1710	prop_coef = 4;
		1711	int_coef = 9;
		1712	gain_ctl = 3;
		1713	targ_cnt = 8;
		1714	} else if ((vco > 5400000 && vco < 6200000) \|\|
		1715	(vco >= 4800000 && vco < 5400000)) {
		1716	prop_coef = 5;
		1717	int_coef = 11;
		1718	gain_ctl = 3;
		1719	targ_cnt = 9;
		1720	} else if (vco == 5400000) {
		1721	prop_coef = 3;
		1722	int_coef = 8;
		1723	gain_ctl = 1;
		1724	targ_cnt = 9;
		1725	} else {
		1726	DRM_ERROR("Invalid VCO\n");
		1727	return false;
		1728	}
		1729
		1730	memset(&crtc_state->dpll_hw_state, 0,
		1731	sizeof(crtc_state->dpll_hw_state));
		1732
		1733	if (clock > 270000)
		1734	lanestagger = 0x18;
		1735	else if (clock > 135000)
		1736	lanestagger = 0x0d;
		1737	else if (clock > 67000)
		1738	lanestagger = 0x07;
		1739	else if (clock > 33000)
		1740	lanestagger = 0x04;
		1741	else
		1742	lanestagger = 0x02;
		1743
		1744	crtc_state->dpll_hw_state.ebb0 =
		1745	PORT_PLL_P1(clk_div.p1) \| PORT_PLL_P2(clk_div.p2);
		1746	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
		1747	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
		1748	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
		1749
		1750	if (clk_div.m2_frac_en)
		1751	crtc_state->dpll_hw_state.pll3 =
		1752	PORT_PLL_M2_FRAC_ENABLE;
		1753
		1754	crtc_state->dpll_hw_state.pll6 =
		1755	prop_coef \| PORT_PLL_INT_COEFF(int_coef);
		1756	crtc_state->dpll_hw_state.pll6 \|=
		1757	PORT_PLL_GAIN_CTL(gain_ctl);
		1758
		1759	crtc_state->dpll_hw_state.pll8 = targ_cnt;
		1760
		1761	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
		1762
		1763	crtc_state->dpll_hw_state.pll10 =
		1764	PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
		1765	\| PORT_PLL_DCO_AMP_OVR_EN_H;
		1766
		1767	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
		1768
		1769	crtc_state->dpll_hw_state.pcsdw12 =
		1770	LANESTAGGER_STRAP_OVRD \| lanestagger;
		1771
		1772	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
		1773	if (pll == NULL) {
		1774	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1775	pipe_name(intel_crtc->pipe));
		1776	return false;
		1777	}
		1778
		1779	/* shared DPLL id 0 is DPLL A */
		1780	crtc_state->ddi_pll_sel = pll->id;
		1781
		1782	return true;
		1783	}
		1784
5354	serge	1785	/*
		1786	* Tries to find a shared PLL for the CRTC and store it in
		1787	* intel_crtc->ddi_pll_sel.
		1788	*
		1789	* For private DPLLs, compute_config() should do the selection for us. This
		1790	* function should be folded into compute_config() eventually.
		1791	*/
6084	serge	1792	bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
		1793	struct intel_crtc_state *crtc_state)
5354	serge	1794	{
		1795	struct drm_device *dev = intel_crtc->base.dev;
		1796	struct intel_encoder *intel_encoder =
6084	serge	1797	intel_ddi_get_crtc_new_encoder(crtc_state);
5354	serge	1798
6937	serge	1799	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
6084	serge	1800	return skl_ddi_pll_select(intel_crtc, crtc_state,
		1801	intel_encoder);
		1802	else if (IS_BROXTON(dev))
		1803	return bxt_ddi_pll_select(intel_crtc, crtc_state,
		1804	intel_encoder);
5354	serge	1805	else
6084	serge	1806	return hsw_ddi_pll_select(intel_crtc, crtc_state,
		1807	intel_encoder);
5354	serge	1808	}
		1809
3243	Serge	1810	void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
		1811	{
		1812	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		1813	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1814	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6084	serge	1815	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	1816	int type = intel_encoder->type;
		1817	uint32_t temp;
		1818
5060	serge	1819	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP \|\| type == INTEL_OUTPUT_DP_MST) {
3243	Serge	1820	temp = TRANS_MSA_SYNC_CLK;
6084	serge	1821	switch (intel_crtc->config->pipe_bpp) {
		1822	case 18:
3243	Serge	1823	temp \|= TRANS_MSA_6_BPC;
6084	serge	1824	break;
		1825	case 24:
3243	Serge	1826	temp \|= TRANS_MSA_8_BPC;
6084	serge	1827	break;
		1828	case 30:
3243	Serge	1829	temp \|= TRANS_MSA_10_BPC;
6084	serge	1830	break;
		1831	case 36:
3243	Serge	1832	temp \|= TRANS_MSA_12_BPC;
6084	serge	1833	break;
		1834	default:
3746	Serge	1835	BUG();
6084	serge	1836	}
3243	Serge	1837	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
		1838	}
		1839	}
3031	serge	1840
5060	serge	1841	void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
		1842	{
		1843	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1844	struct drm_device *dev = crtc->dev;
		1845	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	1846	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5060	serge	1847	uint32_t temp;
		1848	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1849	if (state == true)
		1850	temp \|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
		1851	else
		1852	temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
		1853	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
		1854	}
		1855
3746	Serge	1856	void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
3243	Serge	1857	{
		1858	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1859	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		1860	struct drm_encoder *encoder = &intel_encoder->base;
4560	Serge	1861	struct drm_device *dev = crtc->dev;
		1862	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1863	enum pipe pipe = intel_crtc->pipe;
6084	serge	1864	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	1865	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1866	int type = intel_encoder->type;
		1867	uint32_t temp;
3031	serge	1868
3243	Serge	1869	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
		1870	temp = TRANS_DDI_FUNC_ENABLE;
		1871	temp \|= TRANS_DDI_SELECT_PORT(port);
		1872
6084	serge	1873	switch (intel_crtc->config->pipe_bpp) {
3031	serge	1874	case 18:
3243	Serge	1875	temp \|= TRANS_DDI_BPC_6;
3031	serge	1876	break;
		1877	case 24:
3243	Serge	1878	temp \|= TRANS_DDI_BPC_8;
3031	serge	1879	break;
		1880	case 30:
3243	Serge	1881	temp \|= TRANS_DDI_BPC_10;
3031	serge	1882	break;
		1883	case 36:
3243	Serge	1884	temp \|= TRANS_DDI_BPC_12;
3031	serge	1885	break;
		1886	default:
3746	Serge	1887	BUG();
3031	serge	1888	}
		1889
6084	serge	1890	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
3243	Serge	1891	temp \|= TRANS_DDI_PVSYNC;
6084	serge	1892	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
3243	Serge	1893	temp \|= TRANS_DDI_PHSYNC;
		1894
		1895	if (cpu_transcoder == TRANSCODER_EDP) {
		1896	switch (pipe) {
		1897	case PIPE_A:
4560	Serge	1898	/* On Haswell, can only use the always-on power well for
		1899	* eDP when not using the panel fitter, and when not
		1900	* using motion blur mitigation (which we don't
		1901	* support). */
5060	serge	1902	if (IS_HASWELL(dev) &&
6084	serge	1903	(intel_crtc->config->pch_pfit.enabled \|\|
		1904	intel_crtc->config->pch_pfit.force_thru))
		1905	temp \|= TRANS_DDI_EDP_INPUT_A_ONOFF;
3480	Serge	1906	else
		1907	temp \|= TRANS_DDI_EDP_INPUT_A_ON;
3243	Serge	1908	break;
		1909	case PIPE_B:
		1910	temp \|= TRANS_DDI_EDP_INPUT_B_ONOFF;
		1911	break;
		1912	case PIPE_C:
		1913	temp \|= TRANS_DDI_EDP_INPUT_C_ONOFF;
		1914	break;
		1915	default:
		1916	BUG();
		1917	break;
		1918	}
		1919	}
		1920
		1921	if (type == INTEL_OUTPUT_HDMI) {
6084	serge	1922	if (intel_crtc->config->has_hdmi_sink)
3243	Serge	1923	temp \|= TRANS_DDI_MODE_SELECT_HDMI;
6084	serge	1924	else
3243	Serge	1925	temp \|= TRANS_DDI_MODE_SELECT_DVI;
3031	serge	1926
3243	Serge	1927	} else if (type == INTEL_OUTPUT_ANALOG) {
		1928	temp \|= TRANS_DDI_MODE_SELECT_FDI;
6084	serge	1929	temp \|= (intel_crtc->config->fdi_lanes - 1) << 1;
3031	serge	1930
3243	Serge	1931	} else if (type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1932	type == INTEL_OUTPUT_EDP) {
		1933	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	1934
5060	serge	1935	if (intel_dp->is_mst) {
		1936	temp \|= TRANS_DDI_MODE_SELECT_DP_MST;
		1937	} else
		1938	temp \|= TRANS_DDI_MODE_SELECT_DP_SST;
		1939
6084	serge	1940	temp \|= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
5060	serge	1941	} else if (type == INTEL_OUTPUT_DP_MST) {
		1942	struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
		1943
		1944	if (intel_dp->is_mst) {
		1945	temp \|= TRANS_DDI_MODE_SELECT_DP_MST;
		1946	} else
6084	serge	1947	temp \|= TRANS_DDI_MODE_SELECT_DP_SST;
3243	Serge	1948
6084	serge	1949	temp \|= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
3243	Serge	1950	} else {
4104	Serge	1951	WARN(1, "Invalid encoder type %d for pipe %c\n",
		1952	intel_encoder->type, pipe_name(pipe));
3243	Serge	1953	}
		1954
		1955	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
3031	serge	1956	}
		1957
3243	Serge	1958	void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
		1959	enum transcoder cpu_transcoder)
		1960	{
6937	serge	1961	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3243	Serge	1962	uint32_t val = I915_READ(reg);
		1963
5060	serge	1964	val &= ~(TRANS_DDI_FUNC_ENABLE \| TRANS_DDI_PORT_MASK \| TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3243	Serge	1965	val \|= TRANS_DDI_PORT_NONE;
		1966	I915_WRITE(reg, val);
		1967	}
		1968
		1969	bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
		1970	{
		1971	struct drm_device *dev = intel_connector->base.dev;
		1972	struct drm_i915_private *dev_priv = dev->dev_private;
		1973	struct intel_encoder *intel_encoder = intel_connector->encoder;
		1974	int type = intel_connector->base.connector_type;
		1975	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1976	enum pipe pipe = 0;
		1977	enum transcoder cpu_transcoder;
5060	serge	1978	enum intel_display_power_domain power_domain;
3243	Serge	1979	uint32_t tmp;
6937	serge	1980	bool ret;
3243	Serge	1981
5060	serge	1982	power_domain = intel_display_port_power_domain(intel_encoder);
6937	serge	1983	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
5060	serge	1984	return false;
		1985
6937	serge	1986	if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
		1987	ret = false;
		1988	goto out;
		1989	}
3243	Serge	1990
		1991	if (port == PORT_A)
		1992	cpu_transcoder = TRANSCODER_EDP;
		1993	else
3480	Serge	1994	cpu_transcoder = (enum transcoder) pipe;
3243	Serge	1995
		1996	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1997
		1998	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
		1999	case TRANS_DDI_MODE_SELECT_HDMI:
		2000	case TRANS_DDI_MODE_SELECT_DVI:
6937	serge	2001	ret = type == DRM_MODE_CONNECTOR_HDMIA;
		2002	break;
3243	Serge	2003
		2004	case TRANS_DDI_MODE_SELECT_DP_SST:
6937	serge	2005	ret = type == DRM_MODE_CONNECTOR_eDP \|\|
		2006	type == DRM_MODE_CONNECTOR_DisplayPort;
		2007	break;
		2008
3243	Serge	2009	case TRANS_DDI_MODE_SELECT_DP_MST:
5060	serge	2010	/* if the transcoder is in MST state then
		2011	* connector isn't connected */
6937	serge	2012	ret = false;
		2013	break;
3243	Serge	2014
		2015	case TRANS_DDI_MODE_SELECT_FDI:
6937	serge	2016	ret = type == DRM_MODE_CONNECTOR_VGA;
		2017	break;
3243	Serge	2018
		2019	default:
6937	serge	2020	ret = false;
		2021	break;
3243	Serge	2022	}
6937	serge	2023
		2024	out:
		2025	intel_display_power_put(dev_priv, power_domain);
		2026
		2027	return ret;
3243	Serge	2028	}
		2029
3031	serge	2030	bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
		2031	enum pipe *pipe)
		2032	{
		2033	struct drm_device *dev = encoder->base.dev;
		2034	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2035	enum port port = intel_ddi_get_encoder_port(encoder);
5060	serge	2036	enum intel_display_power_domain power_domain;
3031	serge	2037	u32 tmp;
		2038	int i;
6937	serge	2039	bool ret;
3031	serge	2040
5060	serge	2041	power_domain = intel_display_port_power_domain(encoder);
6937	serge	2042	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
5060	serge	2043	return false;
		2044
6937	serge	2045	ret = false;
		2046
3243	Serge	2047	tmp = I915_READ(DDI_BUF_CTL(port));
3031	serge	2048
		2049	if (!(tmp & DDI_BUF_CTL_ENABLE))
6937	serge	2050	goto out;
3031	serge	2051
3243	Serge	2052	if (port == PORT_A) {
		2053	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
3031	serge	2054
3243	Serge	2055	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		2056	case TRANS_DDI_EDP_INPUT_A_ON:
		2057	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		2058	*pipe = PIPE_A;
		2059	break;
		2060	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		2061	*pipe = PIPE_B;
		2062	break;
		2063	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		2064	*pipe = PIPE_C;
		2065	break;
		2066	}
		2067
6937	serge	2068	ret = true;
		2069
		2070	goto out;
		2071	}
		2072
3243	Serge	2073	for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
		2074	tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
		2075
6937	serge	2076	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
		2077	if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
		2078	TRANS_DDI_MODE_SELECT_DP_MST)
		2079	goto out;
5060	serge	2080
6084	serge	2081	*pipe = i;
6937	serge	2082	ret = true;
		2083
		2084	goto out;
3031	serge	2085	}
		2086	}
		2087
4104	Serge	2088	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
3031	serge	2089
6937	serge	2090	out:
		2091	intel_display_power_put(dev_priv, power_domain);
		2092
		2093	return ret;
3031	serge	2094	}
		2095
3243	Serge	2096	void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
3031	serge	2097	{
3243	Serge	2098	struct drm_crtc *crtc = &intel_crtc->base;
6084	serge	2099	struct drm_device *dev = crtc->dev;
		2100	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2101	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		2102	enum port port = intel_ddi_get_encoder_port(intel_encoder);
6084	serge	2103	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	2104
		2105	if (cpu_transcoder != TRANSCODER_EDP)
		2106	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2107	TRANS_CLK_SEL_PORT(port));
		2108	}
		2109
		2110	void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
		2111	{
		2112	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6084	serge	2113	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	2114
		2115	if (cpu_transcoder != TRANSCODER_EDP)
		2116	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2117	TRANS_CLK_SEL_DISABLED);
		2118	}
		2119
6084	serge	2120	static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
		2121	enum port port, int type)
		2122	{
		2123	struct drm_i915_private *dev_priv = dev->dev_private;
		2124	const struct ddi_buf_trans *ddi_translations;
		2125	uint8_t iboost;
		2126	uint8_t dp_iboost, hdmi_iboost;
		2127	int n_entries;
		2128	u32 reg;
		2129
		2130	/* VBT may override standard boost values */
		2131	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
		2132	hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
		2133
		2134	if (type == INTEL_OUTPUT_DISPLAYPORT) {
		2135	if (dp_iboost) {
		2136	iboost = dp_iboost;
		2137	} else {
		2138	ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
6937	serge	2139	iboost = ddi_translations[level].i_boost;
6084	serge	2140	}
		2141	} else if (type == INTEL_OUTPUT_EDP) {
		2142	if (dp_iboost) {
		2143	iboost = dp_iboost;
		2144	} else {
		2145	ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
6937	serge	2146	iboost = ddi_translations[level].i_boost;
6084	serge	2147	}
		2148	} else if (type == INTEL_OUTPUT_HDMI) {
		2149	if (hdmi_iboost) {
		2150	iboost = hdmi_iboost;
		2151	} else {
		2152	ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
6937	serge	2153	iboost = ddi_translations[level].i_boost;
6084	serge	2154	}
		2155	} else {
		2156	return;
		2157	}
		2158
		2159	/* Make sure that the requested I_boost is valid */
		2160	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
		2161	DRM_ERROR("Invalid I_boost value %u\n", iboost);
		2162	return;
		2163	}
		2164
		2165	reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
		2166	reg &= ~BALANCE_LEG_MASK(port);
		2167	reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
		2168
		2169	if (iboost)
		2170	reg \|= iboost << BALANCE_LEG_SHIFT(port);
		2171	else
		2172	reg \|= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
		2173
		2174	I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
		2175	}
		2176
		2177	static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
		2178	enum port port, int type)
		2179	{
		2180	struct drm_i915_private *dev_priv = dev->dev_private;
		2181	const struct bxt_ddi_buf_trans *ddi_translations;
		2182	u32 n_entries, i;
		2183	uint32_t val;
		2184
		2185	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
		2186	n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
		2187	ddi_translations = bxt_ddi_translations_edp;
		2188	} else if (type == INTEL_OUTPUT_DISPLAYPORT
		2189	\|\| type == INTEL_OUTPUT_EDP) {
		2190	n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
		2191	ddi_translations = bxt_ddi_translations_dp;
		2192	} else if (type == INTEL_OUTPUT_HDMI) {
		2193	n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
		2194	ddi_translations = bxt_ddi_translations_hdmi;
		2195	} else {
		2196	DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
		2197	type);
		2198	return;
		2199	}
		2200
		2201	/* Check if default value has to be used */
		2202	if (level >= n_entries \|\|
		2203	(type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
		2204	for (i = 0; i < n_entries; i++) {
		2205	if (ddi_translations[i].default_index) {
		2206	level = i;
		2207	break;
		2208	}
		2209	}
		2210	}
		2211
		2212	/*
		2213	* While we write to the group register to program all lanes at once we
		2214	* can read only lane registers and we pick lanes 0/1 for that.
		2215	*/
		2216	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
		2217	val &= ~(TX2_SWING_CALC_INIT \| TX1_SWING_CALC_INIT);
		2218	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
		2219
		2220	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
		2221	val &= ~(MARGIN_000 \| UNIQ_TRANS_SCALE);
		2222	val \|= ddi_translations[level].margin << MARGIN_000_SHIFT \|
		2223	ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
		2224	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
		2225
		2226	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
		2227	val &= ~SCALE_DCOMP_METHOD;
		2228	if (ddi_translations[level].enable)
		2229	val \|= SCALE_DCOMP_METHOD;
		2230
		2231	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
		2232	DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
		2233
		2234	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
		2235
		2236	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
		2237	val &= ~DE_EMPHASIS;
		2238	val \|= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
		2239	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
		2240
		2241	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
		2242	val \|= TX2_SWING_CALC_INIT \| TX1_SWING_CALC_INIT;
		2243	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
		2244	}
		2245
		2246	static uint32_t translate_signal_level(int signal_levels)
		2247	{
		2248	uint32_t level;
		2249
		2250	switch (signal_levels) {
		2251	default:
		2252	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
		2253	signal_levels);
		2254	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2255	level = 0;
		2256	break;
		2257	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2258	level = 1;
		2259	break;
		2260	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_2:
		2261	level = 2;
		2262	break;
		2263	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_3:
		2264	level = 3;
		2265	break;
		2266
		2267	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2268	level = 4;
		2269	break;
		2270	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2271	level = 5;
		2272	break;
		2273	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_2:
		2274	level = 6;
		2275	break;
		2276
		2277	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2278	level = 7;
		2279	break;
		2280	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2281	level = 8;
		2282	break;
		2283
		2284	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2285	level = 9;
		2286	break;
		2287	}
		2288
		2289	return level;
		2290	}
		2291
		2292	uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
		2293	{
		2294	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		2295	struct drm_device *dev = dport->base.base.dev;
		2296	struct intel_encoder *encoder = &dport->base;
		2297	uint8_t train_set = intel_dp->train_set[0];
		2298	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2299	DP_TRAIN_PRE_EMPHASIS_MASK);
		2300	enum port port = dport->port;
		2301	uint32_t level;
		2302
		2303	level = translate_signal_level(signal_levels);
		2304
6937	serge	2305	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
6084	serge	2306	skl_ddi_set_iboost(dev, level, port, encoder->type);
		2307	else if (IS_BROXTON(dev))
		2308	bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
		2309
		2310	return DDI_BUF_TRANS_SELECT(level);
		2311	}
		2312
6937	serge	2313	void intel_ddi_clk_select(struct intel_encoder *encoder,
		2314	const struct intel_crtc_state *pipe_config)
3243	Serge	2315	{
6937	serge	2316	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		2317	enum port port = intel_ddi_get_encoder_port(encoder);
3243	Serge	2318
6937	serge	2319	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {
		2320	uint32_t dpll = pipe_config->ddi_pll_sel;
5354	serge	2321	uint32_t val;
		2322
		2323	/*
		2324	* DPLL0 is used for eDP and is the only "private" DPLL (as
		2325	* opposed to shared) on SKL
		2326	*/
6937	serge	2327	if (encoder->type == INTEL_OUTPUT_EDP) {
5354	serge	2328	WARN_ON(dpll != SKL_DPLL0);
		2329
		2330	val = I915_READ(DPLL_CTRL1);
		2331
		2332	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) \|
		2333	DPLL_CTRL1_SSC(dpll) \|
6084	serge	2334	DPLL_CTRL1_LINK_RATE_MASK(dpll));
6937	serge	2335	val \|= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
5354	serge	2336
		2337	I915_WRITE(DPLL_CTRL1, val);
		2338	POSTING_READ(DPLL_CTRL1);
6084	serge	2339	}
5354	serge	2340
		2341	/* DDI -> PLL mapping */
		2342	val = I915_READ(DPLL_CTRL2);
		2343
		2344	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) \|
		2345	DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
		2346	val \|= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) \|
		2347	DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
		2348
		2349	I915_WRITE(DPLL_CTRL2, val);
		2350
6937	serge	2351	} else if (INTEL_INFO(dev_priv)->gen < 9) {
		2352	WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
		2353	I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
5354	serge	2354	}
6937	serge	2355	}
3243	Serge	2356
6937	serge	2357	static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
		2358	{
		2359	struct drm_encoder *encoder = &intel_encoder->base;
		2360	struct drm_device *dev = encoder->dev;
		2361	struct drm_i915_private *dev_priv = dev->dev_private;
		2362	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
		2363	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2364	int type = intel_encoder->type;
		2365	int hdmi_level;
		2366
		2367	if (type == INTEL_OUTPUT_EDP) {
		2368	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2369	intel_edp_panel_on(intel_dp);
		2370	}
		2371
		2372	intel_ddi_clk_select(intel_encoder, crtc->config);
		2373
3243	Serge	2374	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
		2375	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2376
6084	serge	2377	intel_dp_set_link_params(intel_dp, crtc->config);
		2378
5060	serge	2379	intel_ddi_init_dp_buf_reg(intel_encoder);
		2380
3243	Serge	2381	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
		2382	intel_dp_start_link_train(intel_dp);
5354	serge	2383	if (port != PORT_A \|\| INTEL_INFO(dev)->gen >= 9)
3746	Serge	2384	intel_dp_stop_link_train(intel_dp);
5060	serge	2385	} else if (type == INTEL_OUTPUT_HDMI) {
		2386	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
		2387
6084	serge	2388	if (IS_BROXTON(dev)) {
		2389	hdmi_level = dev_priv->vbt.
		2390	ddi_port_info[port].hdmi_level_shift;
		2391	bxt_ddi_vswing_sequence(dev, hdmi_level, port,
		2392	INTEL_OUTPUT_HDMI);
		2393	}
5060	serge	2394	intel_hdmi->set_infoframes(encoder,
6084	serge	2395	crtc->config->has_hdmi_sink,
		2396	&crtc->config->base.adjusted_mode);
3243	Serge	2397	}
		2398	}
		2399
		2400	static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
		2401	{
		2402	struct drm_encoder *encoder = &intel_encoder->base;
5354	serge	2403	struct drm_device *dev = encoder->dev;
		2404	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2405	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2406	int type = intel_encoder->type;
		2407	uint32_t val;
		2408	bool wait = false;
		2409
		2410	val = I915_READ(DDI_BUF_CTL(port));
		2411	if (val & DDI_BUF_CTL_ENABLE) {
		2412	val &= ~DDI_BUF_CTL_ENABLE;
		2413	I915_WRITE(DDI_BUF_CTL(port), val);
		2414	wait = true;
		2415	}
		2416
		2417	val = I915_READ(DP_TP_CTL(port));
		2418	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		2419	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		2420	I915_WRITE(DP_TP_CTL(port), val);
		2421
		2422	if (wait)
		2423	intel_wait_ddi_buf_idle(dev_priv, port);
		2424
4560	Serge	2425	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
3243	Serge	2426	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4560	Serge	2427	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
5060	serge	2428	intel_edp_panel_vdd_on(intel_dp);
		2429	intel_edp_panel_off(intel_dp);
3243	Serge	2430	}
		2431
6937	serge	2432	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
5354	serge	2433	I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) \|
		2434	DPLL_CTRL2_DDI_CLK_OFF(port)));
6084	serge	2435	else if (INTEL_INFO(dev)->gen < 9)
		2436	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3243	Serge	2437	}
		2438
		2439	static void intel_enable_ddi(struct intel_encoder *intel_encoder)
		2440	{
		2441	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	2442	struct drm_crtc *crtc = encoder->crtc;
		2443	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	2444	struct drm_device *dev = encoder->dev;
3031	serge	2445	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2446	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2447	int type = intel_encoder->type;
3031	serge	2448
3243	Serge	2449	if (type == INTEL_OUTPUT_HDMI) {
3480	Serge	2450	struct intel_digital_port *intel_dig_port =
		2451	enc_to_dig_port(encoder);
		2452
3243	Serge	2453	/* In HDMI/DVI mode, the port width, and swing/emphasis values
		2454	* are ignored so nothing special needs to be done besides
		2455	* enabling the port.
		2456	*/
3480	Serge	2457	I915_WRITE(DDI_BUF_CTL(port),
4104	Serge	2458	intel_dig_port->saved_port_bits \|
		2459	DDI_BUF_CTL_ENABLE);
3243	Serge	2460	} else if (type == INTEL_OUTPUT_EDP) {
		2461	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	2462
5354	serge	2463	if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3746	Serge	2464	intel_dp_stop_link_train(intel_dp);
		2465
5060	serge	2466	intel_edp_backlight_on(intel_dp);
5354	serge	2467	intel_psr_enable(intel_dp);
6084	serge	2468	intel_edp_drrs_enable(intel_dp);
3243	Serge	2469	}
3480	Serge	2470
6084	serge	2471	if (intel_crtc->config->has_audio) {
5060	serge	2472	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5354	serge	2473	intel_audio_codec_enable(intel_encoder);
3480	Serge	2474	}
3031	serge	2475	}
3243	Serge	2476
		2477	static void intel_disable_ddi(struct intel_encoder *intel_encoder)
		2478	{
		2479	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	2480	struct drm_crtc *crtc = encoder->crtc;
		2481	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	2482	int type = intel_encoder->type;
3480	Serge	2483	struct drm_device *dev = encoder->dev;
		2484	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2485
6084	serge	2486	if (intel_crtc->config->has_audio) {
5354	serge	2487	intel_audio_codec_disable(intel_encoder);
5060	serge	2488	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
4104	Serge	2489	}
3746	Serge	2490
3243	Serge	2491	if (type == INTEL_OUTPUT_EDP) {
		2492	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2493
6084	serge	2494	intel_edp_drrs_disable(intel_dp);
5354	serge	2495	intel_psr_disable(intel_dp);
5060	serge	2496	intel_edp_backlight_off(intel_dp);
3243	Serge	2497	}
		2498	}
		2499
6084	serge	2500	static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
		2501	struct intel_shared_dpll *pll)
3243	Serge	2502	{
6084	serge	2503	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
		2504	POSTING_READ(WRPLL_CTL(pll->id));
		2505	udelay(20);
5354	serge	2506	}
		2507
6084	serge	2508	static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
		2509	struct intel_shared_dpll *pll)
5354	serge	2510	{
6084	serge	2511	I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
		2512	POSTING_READ(SPLL_CTL);
		2513	udelay(20);
3243	Serge	2514	}
		2515
6084	serge	2516	static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
		2517	struct intel_shared_dpll *pll)
5354	serge	2518	{
6084	serge	2519	uint32_t val;
5354	serge	2520
6084	serge	2521	val = I915_READ(WRPLL_CTL(pll->id));
		2522	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
		2523	POSTING_READ(WRPLL_CTL(pll->id));
5354	serge	2524	}
		2525
6084	serge	2526	static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
		2527	struct intel_shared_dpll *pll)
5354	serge	2528	{
6084	serge	2529	uint32_t val;
5354	serge	2530
6084	serge	2531	val = I915_READ(SPLL_CTL);
		2532	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
		2533	POSTING_READ(SPLL_CTL);
5354	serge	2534	}
		2535
6084	serge	2536	static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
		2537	struct intel_shared_dpll *pll,
		2538	struct intel_dpll_hw_state *hw_state)
5060	serge	2539	{
		2540	uint32_t val;
		2541
6937	serge	2542	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
6084	serge	2543	return false;
		2544
5060	serge	2545	val = I915_READ(WRPLL_CTL(pll->id));
6084	serge	2546	hw_state->wrpll = val;
		2547
6937	serge	2548	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		2549
6084	serge	2550	return val & WRPLL_PLL_ENABLE;
5060	serge	2551	}
		2552
6084	serge	2553	static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
		2554	struct intel_shared_dpll *pll,
		2555	struct intel_dpll_hw_state *hw_state)
5060	serge	2556	{
		2557	uint32_t val;
		2558
6937	serge	2559	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
5060	serge	2560	return false;
		2561
6084	serge	2562	val = I915_READ(SPLL_CTL);
		2563	hw_state->spll = val;
5060	serge	2564
6937	serge	2565	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		2566
6084	serge	2567	return val & SPLL_PLL_ENABLE;
5060	serge	2568	}
		2569
6084	serge	2570
5060	serge	2571	static const char * const hsw_ddi_pll_names[] = {
		2572	"WRPLL 1",
		2573	"WRPLL 2",
6084	serge	2574	"SPLL"
5060	serge	2575	};
		2576
5354	serge	2577	static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
3243	Serge	2578	{
5060	serge	2579	int i;
3243	Serge	2580
6084	serge	2581	dev_priv->num_shared_dpll = 3;
5060	serge	2582
6084	serge	2583	for (i = 0; i < 2; i++) {
5060	serge	2584	dev_priv->shared_dplls[i].id = i;
		2585	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
6084	serge	2586	dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
		2587	dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
5060	serge	2588	dev_priv->shared_dplls[i].get_hw_state =
6084	serge	2589	hsw_ddi_wrpll_get_hw_state;
5060	serge	2590	}
6084	serge	2591
		2592	/* SPLL is special, but needs to be initialized anyway.. */
		2593	dev_priv->shared_dplls[i].id = i;
		2594	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
		2595	dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
		2596	dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
		2597	dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
		2598
5354	serge	2599	}
5060	serge	2600
5354	serge	2601	static const char * const skl_ddi_pll_names[] = {
		2602	"DPLL 1",
		2603	"DPLL 2",
		2604	"DPLL 3",
		2605	};
3243	Serge	2606
5354	serge	2607	struct skl_dpll_regs {
6937	serge	2608	i915_reg_t ctl, cfgcr1, cfgcr2;
5354	serge	2609	};
		2610
		2611	/* this array is indexed by the shared pll id */
		2612	static const struct skl_dpll_regs skl_dpll_regs[3] = {
		2613	{
		2614	/* DPLL 1 */
		2615	.ctl = LCPLL2_CTL,
6084	serge	2616	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
		2617	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
5354	serge	2618	},
		2619	{
		2620	/* DPLL 2 */
6937	serge	2621	.ctl = WRPLL_CTL(0),
6084	serge	2622	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
		2623	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
5354	serge	2624	},
		2625	{
		2626	/* DPLL 3 */
6937	serge	2627	.ctl = WRPLL_CTL(1),
6084	serge	2628	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
		2629	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
5354	serge	2630	},
		2631	};
		2632
		2633	static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
		2634	struct intel_shared_dpll *pll)
		2635	{
		2636	uint32_t val;
		2637	unsigned int dpll;
		2638	const struct skl_dpll_regs *regs = skl_dpll_regs;
		2639
		2640	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
		2641	dpll = pll->id + 1;
		2642
		2643	val = I915_READ(DPLL_CTRL1);
		2644
		2645	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) \| DPLL_CTRL1_SSC(dpll) \|
6084	serge	2646	DPLL_CTRL1_LINK_RATE_MASK(dpll));
5354	serge	2647	val \|= pll->config.hw_state.ctrl1 << (dpll * 6);
		2648
		2649	I915_WRITE(DPLL_CTRL1, val);
		2650	POSTING_READ(DPLL_CTRL1);
		2651
		2652	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
		2653	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
		2654	POSTING_READ(regs[pll->id].cfgcr1);
		2655	POSTING_READ(regs[pll->id].cfgcr2);
		2656
		2657	/* the enable bit is always bit 31 */
		2658	I915_WRITE(regs[pll->id].ctl,
		2659	I915_READ(regs[pll->id].ctl) \| LCPLL_PLL_ENABLE);
		2660
		2661	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
		2662	DRM_ERROR("DPLL %d not locked\n", dpll);
		2663	}
		2664
		2665	static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
		2666	struct intel_shared_dpll *pll)
		2667	{
		2668	const struct skl_dpll_regs *regs = skl_dpll_regs;
		2669
		2670	/* the enable bit is always bit 31 */
		2671	I915_WRITE(regs[pll->id].ctl,
		2672	I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
		2673	POSTING_READ(regs[pll->id].ctl);
		2674	}
		2675
		2676	static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
		2677	struct intel_shared_dpll *pll,
		2678	struct intel_dpll_hw_state *hw_state)
		2679	{
		2680	uint32_t val;
		2681	unsigned int dpll;
		2682	const struct skl_dpll_regs *regs = skl_dpll_regs;
6937	serge	2683	bool ret;
5354	serge	2684
6937	serge	2685	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
5354	serge	2686	return false;
		2687
6937	serge	2688	ret = false;
		2689
5354	serge	2690	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
		2691	dpll = pll->id + 1;
		2692
		2693	val = I915_READ(regs[pll->id].ctl);
		2694	if (!(val & LCPLL_PLL_ENABLE))
6937	serge	2695	goto out;
5354	serge	2696
		2697	val = I915_READ(DPLL_CTRL1);
		2698	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
		2699
		2700	/* avoid reading back stale values if HDMI mode is not enabled */
		2701	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
		2702	hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
		2703	hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
		2704	}
6937	serge	2705	ret = true;
5354	serge	2706
6937	serge	2707	out:
		2708	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		2709
		2710	return ret;
5354	serge	2711	}
		2712
		2713	static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
		2714	{
		2715	int i;
		2716
		2717	dev_priv->num_shared_dpll = 3;
		2718
		2719	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		2720	dev_priv->shared_dplls[i].id = i;
		2721	dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
		2722	dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
		2723	dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
		2724	dev_priv->shared_dplls[i].get_hw_state =
		2725	skl_ddi_pll_get_hw_state;
		2726	}
		2727	}
		2728
6084	serge	2729	static void broxton_phy_init(struct drm_i915_private *dev_priv,
		2730	enum dpio_phy phy)
		2731	{
		2732	enum port port;
		2733	uint32_t val;
		2734
		2735	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
		2736	val \|= GT_DISPLAY_POWER_ON(phy);
		2737	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
		2738
		2739	/* Considering 10ms timeout until BSpec is updated */
		2740	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
		2741	DRM_ERROR("timeout during PHY%d power on\n", phy);
		2742
		2743	for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
		2744	port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
		2745	int lane;
		2746
		2747	for (lane = 0; lane < 4; lane++) {
		2748	val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
		2749	/*
		2750	* Note that on CHV this flag is called UPAR, but has
		2751	* the same function.
		2752	*/
		2753	val &= ~LATENCY_OPTIM;
		2754	if (lane != 1)
		2755	val \|= LATENCY_OPTIM;
		2756
		2757	I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
		2758	}
		2759	}
		2760
		2761	/* Program PLL Rcomp code offset */
		2762	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
		2763	val &= ~IREF0RC_OFFSET_MASK;
		2764	val \|= 0xE4 << IREF0RC_OFFSET_SHIFT;
		2765	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
		2766
		2767	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
		2768	val &= ~IREF1RC_OFFSET_MASK;
		2769	val \|= 0xE4 << IREF1RC_OFFSET_SHIFT;
		2770	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
		2771
		2772	/* Program power gating */
		2773	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
		2774	val \|= OCL1_POWER_DOWN_EN \| DW28_OLDO_DYN_PWR_DOWN_EN \|
		2775	SUS_CLK_CONFIG;
		2776	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
		2777
		2778	if (phy == DPIO_PHY0) {
		2779	val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
		2780	val \|= DW6_OLDO_DYN_PWR_DOWN_EN;
		2781	I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
		2782	}
		2783
		2784	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
		2785	val &= ~OCL2_LDOFUSE_PWR_DIS;
		2786	/*
		2787	* On PHY1 disable power on the second channel, since no port is
		2788	* connected there. On PHY0 both channels have a port, so leave it
		2789	* enabled.
		2790	* TODO: port C is only connected on BXT-P, so on BXT0/1 we should
		2791	* power down the second channel on PHY0 as well.
		2792	*/
		2793	if (phy == DPIO_PHY1)
		2794	val \|= OCL2_LDOFUSE_PWR_DIS;
		2795	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
		2796
		2797	if (phy == DPIO_PHY0) {
		2798	uint32_t grc_code;
		2799	/*
		2800	* PHY0 isn't connected to an RCOMP resistor so copy over
		2801	* the corresponding calibrated value from PHY1, and disable
		2802	* the automatic calibration on PHY0.
		2803	*/
		2804	if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
		2805	10))
		2806	DRM_ERROR("timeout waiting for PHY1 GRC\n");
		2807
		2808	val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
		2809	val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
		2810	grc_code = val << GRC_CODE_FAST_SHIFT \|
		2811	val << GRC_CODE_SLOW_SHIFT \|
		2812	val;
		2813	I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
		2814
		2815	val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
		2816	val \|= GRC_DIS \| GRC_RDY_OVRD;
		2817	I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
		2818	}
		2819
		2820	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
		2821	val \|= COMMON_RESET_DIS;
		2822	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
		2823	}
		2824
		2825	void broxton_ddi_phy_init(struct drm_device *dev)
		2826	{
		2827	/* Enable PHY1 first since it provides Rcomp for PHY0 */
		2828	broxton_phy_init(dev->dev_private, DPIO_PHY1);
		2829	broxton_phy_init(dev->dev_private, DPIO_PHY0);
		2830	}
		2831
		2832	static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
		2833	enum dpio_phy phy)
		2834	{
		2835	uint32_t val;
		2836
		2837	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
		2838	val &= ~COMMON_RESET_DIS;
		2839	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
		2840	}
		2841
		2842	void broxton_ddi_phy_uninit(struct drm_device *dev)
		2843	{
		2844	struct drm_i915_private *dev_priv = dev->dev_private;
		2845
		2846	broxton_phy_uninit(dev_priv, DPIO_PHY1);
		2847	broxton_phy_uninit(dev_priv, DPIO_PHY0);
		2848
		2849	/* FIXME: do this in broxton_phy_uninit per phy */
		2850	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
		2851	}
		2852
		2853	static const char * const bxt_ddi_pll_names[] = {
		2854	"PORT PLL A",
		2855	"PORT PLL B",
		2856	"PORT PLL C",
		2857	};
		2858
		2859	static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
		2860	struct intel_shared_dpll *pll)
		2861	{
		2862	uint32_t temp;
		2863	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2864
		2865	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2866	temp &= ~PORT_PLL_REF_SEL;
		2867	/* Non-SSC reference */
		2868	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2869
		2870	/* Disable 10 bit clock */
		2871	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2872	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
		2873	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2874
		2875	/* Write P1 & P2 */
		2876	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
		2877	temp &= ~(PORT_PLL_P1_MASK \| PORT_PLL_P2_MASK);
		2878	temp \|= pll->config.hw_state.ebb0;
		2879	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
		2880
		2881	/* Write M2 integer */
		2882	temp = I915_READ(BXT_PORT_PLL(port, 0));
		2883	temp &= ~PORT_PLL_M2_MASK;
		2884	temp \|= pll->config.hw_state.pll0;
		2885	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
		2886
		2887	/* Write N */
		2888	temp = I915_READ(BXT_PORT_PLL(port, 1));
		2889	temp &= ~PORT_PLL_N_MASK;
		2890	temp \|= pll->config.hw_state.pll1;
		2891	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
		2892
		2893	/* Write M2 fraction */
		2894	temp = I915_READ(BXT_PORT_PLL(port, 2));
		2895	temp &= ~PORT_PLL_M2_FRAC_MASK;
		2896	temp \|= pll->config.hw_state.pll2;
		2897	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
		2898
		2899	/* Write M2 fraction enable */
		2900	temp = I915_READ(BXT_PORT_PLL(port, 3));
		2901	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
		2902	temp \|= pll->config.hw_state.pll3;
		2903	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
		2904
		2905	/* Write coeff */
		2906	temp = I915_READ(BXT_PORT_PLL(port, 6));
		2907	temp &= ~PORT_PLL_PROP_COEFF_MASK;
		2908	temp &= ~PORT_PLL_INT_COEFF_MASK;
		2909	temp &= ~PORT_PLL_GAIN_CTL_MASK;
		2910	temp \|= pll->config.hw_state.pll6;
		2911	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
		2912
		2913	/* Write calibration val */
		2914	temp = I915_READ(BXT_PORT_PLL(port, 8));
		2915	temp &= ~PORT_PLL_TARGET_CNT_MASK;
		2916	temp \|= pll->config.hw_state.pll8;
		2917	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
		2918
		2919	temp = I915_READ(BXT_PORT_PLL(port, 9));
		2920	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
		2921	temp \|= pll->config.hw_state.pll9;
		2922	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
		2923
		2924	temp = I915_READ(BXT_PORT_PLL(port, 10));
		2925	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
		2926	temp &= ~PORT_PLL_DCO_AMP_MASK;
		2927	temp \|= pll->config.hw_state.pll10;
		2928	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
		2929
		2930	/* Recalibrate with new settings */
		2931	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2932	temp \|= PORT_PLL_RECALIBRATE;
		2933	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2934	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
		2935	temp \|= pll->config.hw_state.ebb4;
		2936	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2937
		2938	/* Enable PLL */
		2939	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2940	temp \|= PORT_PLL_ENABLE;
		2941	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2942	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
		2943
		2944	if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
		2945	PORT_PLL_LOCK), 200))
		2946	DRM_ERROR("PLL %d not locked\n", port);
		2947
		2948	/*
		2949	* While we write to the group register to program all lanes at once we
		2950	* can read only lane registers and we pick lanes 0/1 for that.
		2951	*/
		2952	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
		2953	temp &= ~LANE_STAGGER_MASK;
		2954	temp &= ~LANESTAGGER_STRAP_OVRD;
		2955	temp \|= pll->config.hw_state.pcsdw12;
		2956	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
		2957	}
		2958
		2959	static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
		2960	struct intel_shared_dpll *pll)
		2961	{
		2962	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2963	uint32_t temp;
		2964
		2965	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2966	temp &= ~PORT_PLL_ENABLE;
		2967	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2968	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
		2969	}
		2970
		2971	static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
		2972	struct intel_shared_dpll *pll,
		2973	struct intel_dpll_hw_state *hw_state)
		2974	{
		2975	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2976	uint32_t val;
6937	serge	2977	bool ret;
6084	serge	2978
6937	serge	2979	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
6084	serge	2980	return false;
		2981
6937	serge	2982	ret = false;
		2983
6084	serge	2984	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2985	if (!(val & PORT_PLL_ENABLE))
6937	serge	2986	goto out;
6084	serge	2987
		2988	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
		2989	hw_state->ebb0 &= PORT_PLL_P1_MASK \| PORT_PLL_P2_MASK;
		2990
		2991	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2992	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
		2993
		2994	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
		2995	hw_state->pll0 &= PORT_PLL_M2_MASK;
		2996
		2997	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
		2998	hw_state->pll1 &= PORT_PLL_N_MASK;
		2999
		3000	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
		3001	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
		3002
		3003	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
		3004	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
		3005
		3006	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
		3007	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK \|
		3008	PORT_PLL_INT_COEFF_MASK \|
		3009	PORT_PLL_GAIN_CTL_MASK;
		3010
		3011	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
		3012	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
		3013
		3014	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
		3015	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
		3016
		3017	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
		3018	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H \|
		3019	PORT_PLL_DCO_AMP_MASK;
		3020
		3021	/*
		3022	* While we write to the group register to program all lanes at once we
		3023	* can read only lane registers. We configure all lanes the same way, so
		3024	* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
		3025	*/
		3026	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
		3027	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
		3028	DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
		3029	hw_state->pcsdw12,
		3030	I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
		3031	hw_state->pcsdw12 &= LANE_STAGGER_MASK \| LANESTAGGER_STRAP_OVRD;
		3032
6937	serge	3033	ret = true;
		3034
		3035	out:
		3036	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		3037
		3038	return ret;
6084	serge	3039	}
		3040
		3041	static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
		3042	{
		3043	int i;
		3044
		3045	dev_priv->num_shared_dpll = 3;
		3046
		3047	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		3048	dev_priv->shared_dplls[i].id = i;
		3049	dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
		3050	dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
		3051	dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
		3052	dev_priv->shared_dplls[i].get_hw_state =
		3053	bxt_ddi_pll_get_hw_state;
		3054	}
		3055	}
		3056
5354	serge	3057	void intel_ddi_pll_init(struct drm_device *dev)
		3058	{
		3059	struct drm_i915_private *dev_priv = dev->dev_private;
		3060	uint32_t val = I915_READ(LCPLL_CTL);
		3061
6937	serge	3062	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
5354	serge	3063	skl_shared_dplls_init(dev_priv);
6084	serge	3064	else if (IS_BROXTON(dev))
		3065	bxt_shared_dplls_init(dev_priv);
5354	serge	3066	else
		3067	hsw_shared_dplls_init(dev_priv);
		3068
6937	serge	3069	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
6084	serge	3070	int cdclk_freq;
3243	Serge	3071
6084	serge	3072	cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
		3073	dev_priv->skl_boot_cdclk = cdclk_freq;
6937	serge	3074	if (skl_sanitize_cdclk(dev_priv))
		3075	DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
5354	serge	3076	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
		3077	DRM_ERROR("LCPLL1 is disabled\n");
6084	serge	3078	} else if (IS_BROXTON(dev)) {
		3079	broxton_init_cdclk(dev);
		3080	broxton_ddi_phy_init(dev);
5354	serge	3081	} else {
		3082	/*
		3083	* The LCPLL register should be turned on by the BIOS. For now
		3084	* let's just check its state and print errors in case
		3085	* something is wrong. Don't even try to turn it on.
		3086	*/
		3087
6084	serge	3088	if (val & LCPLL_CD_SOURCE_FCLK)
		3089	DRM_ERROR("CDCLK source is not LCPLL\n");
3243	Serge	3090
6084	serge	3091	if (val & LCPLL_PLL_DISABLE)
		3092	DRM_ERROR("LCPLL is disabled\n");
5354	serge	3093	}
3243	Serge	3094	}
		3095
6937	serge	3096	void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3243	Serge	3097	{
6937	serge	3098	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		3099	struct drm_i915_private *dev_priv =
		3100	to_i915(intel_dig_port->base.base.dev);
3243	Serge	3101	enum port port = intel_dig_port->port;
		3102	uint32_t val;
3480	Serge	3103	bool wait = false;
3243	Serge	3104
		3105	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		3106	val = I915_READ(DDI_BUF_CTL(port));
		3107	if (val & DDI_BUF_CTL_ENABLE) {
		3108	val &= ~DDI_BUF_CTL_ENABLE;
		3109	I915_WRITE(DDI_BUF_CTL(port), val);
		3110	wait = true;
		3111	}
		3112
		3113	val = I915_READ(DP_TP_CTL(port));
		3114	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		3115	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		3116	I915_WRITE(DP_TP_CTL(port), val);
		3117	POSTING_READ(DP_TP_CTL(port));
		3118
		3119	if (wait)
		3120	intel_wait_ddi_buf_idle(dev_priv, port);
		3121	}
		3122
5060	serge	3123	val = DP_TP_CTL_ENABLE \|
3243	Serge	3124	DP_TP_CTL_LINK_TRAIN_PAT1 \| DP_TP_CTL_SCRAMBLE_DISABLE;
5060	serge	3125	if (intel_dp->is_mst)
		3126	val \|= DP_TP_CTL_MODE_MST;
		3127	else {
		3128	val \|= DP_TP_CTL_MODE_SST;
6084	serge	3129	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		3130	val \|= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
5060	serge	3131	}
3243	Serge	3132	I915_WRITE(DP_TP_CTL(port), val);
		3133	POSTING_READ(DP_TP_CTL(port));
		3134
		3135	intel_dp->DP \|= DDI_BUF_CTL_ENABLE;
		3136	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
		3137	POSTING_READ(DDI_BUF_CTL(port));
		3138
		3139	udelay(600);
		3140	}
		3141
		3142	void intel_ddi_fdi_disable(struct drm_crtc *crtc)
		3143	{
		3144	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		3145	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		3146	uint32_t val;
		3147
		3148	intel_ddi_post_disable(intel_encoder);
		3149
6084	serge	3150	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3151	val &= ~FDI_RX_ENABLE;
6084	serge	3152	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3153
6084	serge	3154	val = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	3155	val &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		3156	val \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
6084	serge	3157	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3243	Serge	3158
6084	serge	3159	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3160	val &= ~FDI_PCDCLK;
6084	serge	3161	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3162
6084	serge	3163	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3164	val &= ~FDI_RX_PLL_ENABLE;
6084	serge	3165	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3166	}
		3167
4280	Serge	3168	void intel_ddi_get_config(struct intel_encoder *encoder,
6084	serge	3169	struct intel_crtc_state *pipe_config)
4104	Serge	3170	{
		3171	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		3172	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
6084	serge	3173	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5354	serge	3174	struct intel_hdmi *intel_hdmi;
4104	Serge	3175	u32 temp, flags = 0;
		3176
		3177	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		3178	if (temp & TRANS_DDI_PHSYNC)
		3179	flags \|= DRM_MODE_FLAG_PHSYNC;
		3180	else
		3181	flags \|= DRM_MODE_FLAG_NHSYNC;
		3182	if (temp & TRANS_DDI_PVSYNC)
		3183	flags \|= DRM_MODE_FLAG_PVSYNC;
		3184	else
		3185	flags \|= DRM_MODE_FLAG_NVSYNC;
		3186
6084	serge	3187	pipe_config->base.adjusted_mode.flags \|= flags;
4280	Serge	3188
		3189	switch (temp & TRANS_DDI_BPC_MASK) {
		3190	case TRANS_DDI_BPC_6:
		3191	pipe_config->pipe_bpp = 18;
		3192	break;
		3193	case TRANS_DDI_BPC_8:
		3194	pipe_config->pipe_bpp = 24;
		3195	break;
		3196	case TRANS_DDI_BPC_10:
		3197	pipe_config->pipe_bpp = 30;
		3198	break;
		3199	case TRANS_DDI_BPC_12:
		3200	pipe_config->pipe_bpp = 36;
		3201	break;
		3202	default:
		3203	break;
		3204	}
4371	Serge	3205
4560	Serge	3206	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
		3207	case TRANS_DDI_MODE_SELECT_HDMI:
5060	serge	3208	pipe_config->has_hdmi_sink = true;
5354	serge	3209	intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		3210
6937	serge	3211	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
5354	serge	3212	pipe_config->has_infoframe = true;
		3213	break;
4560	Serge	3214	case TRANS_DDI_MODE_SELECT_DVI:
		3215	case TRANS_DDI_MODE_SELECT_FDI:
		3216	break;
		3217	case TRANS_DDI_MODE_SELECT_DP_SST:
		3218	case TRANS_DDI_MODE_SELECT_DP_MST:
		3219	pipe_config->has_dp_encoder = true;
6084	serge	3220	pipe_config->lane_count =
		3221	((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4560	Serge	3222	intel_dp_get_m_n(intel_crtc, pipe_config);
		3223	break;
		3224	default:
		3225	break;
		3226	}
		3227
5354	serge	3228	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
5060	serge	3229	temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5354	serge	3230	if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
5060	serge	3231	pipe_config->has_audio = true;
		3232	}
		3233
4371	Serge	3234	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
		3235	pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		3236	/*
		3237	* This is a big fat ugly hack.
		3238	*
		3239	* Some machines in UEFI boot mode provide us a VBT that has 18
		3240	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		3241	* unknown we fail to light up. Yet the same BIOS boots up with
		3242	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		3243	* max, not what it tells us to use.
		3244	*
		3245	* Note: This will still be broken if the eDP panel is not lit
		3246	* up by the BIOS, and thus we can't get the mode at module
		3247	* load.
		3248	*/
		3249	DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
		3250	pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		3251	dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
		3252	}
5060	serge	3253
6084	serge	3254	intel_ddi_clock_get(encoder, pipe_config);
4104	Serge	3255	}
		3256
3746	Serge	3257	static bool intel_ddi_compute_config(struct intel_encoder *encoder,
6084	serge	3258	struct intel_crtc_state *pipe_config)
3243	Serge	3259	{
3746	Serge	3260	int type = encoder->type;
4104	Serge	3261	int port = intel_ddi_get_encoder_port(encoder);
3243	Serge	3262
3746	Serge	3263	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3243	Serge	3264
4104	Serge	3265	if (port == PORT_A)
		3266	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		3267
3243	Serge	3268	if (type == INTEL_OUTPUT_HDMI)
3746	Serge	3269	return intel_hdmi_compute_config(encoder, pipe_config);
3243	Serge	3270	else
3746	Serge	3271	return intel_dp_compute_config(encoder, pipe_config);
3243	Serge	3272	}
		3273
		3274	static const struct drm_encoder_funcs intel_ddi_funcs = {
6660	serge	3275	.reset = intel_dp_encoder_reset,
		3276	.destroy = intel_dp_encoder_destroy,
3243	Serge	3277	};
		3278
4560	Serge	3279	static struct intel_connector *
		3280	intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
		3281	{
		3282	struct intel_connector *connector;
		3283	enum port port = intel_dig_port->port;
		3284
6084	serge	3285	connector = intel_connector_alloc();
4560	Serge	3286	if (!connector)
		3287	return NULL;
		3288
		3289	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
		3290	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		3291	kfree(connector);
		3292	return NULL;
		3293	}
		3294
		3295	return connector;
		3296	}
		3297
		3298	static struct intel_connector *
		3299	intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
		3300	{
		3301	struct intel_connector *connector;
		3302	enum port port = intel_dig_port->port;
		3303
6084	serge	3304	connector = intel_connector_alloc();
4560	Serge	3305	if (!connector)
		3306	return NULL;
		3307
		3308	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
		3309	intel_hdmi_init_connector(intel_dig_port, connector);
		3310
		3311	return connector;
		3312	}
		3313
3243	Serge	3314	void intel_ddi_init(struct drm_device *dev, enum port port)
		3315	{
3480	Serge	3316	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3317	struct intel_digital_port *intel_dig_port;
		3318	struct intel_encoder *intel_encoder;
		3319	struct drm_encoder *encoder;
4560	Serge	3320	bool init_hdmi, init_dp;
3243	Serge	3321
4560	Serge	3322	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi \|\|
		3323	dev_priv->vbt.ddi_port_info[port].supports_hdmi);
		3324	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
		3325	if (!init_dp && !init_hdmi) {
6084	serge	3326	DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4560	Serge	3327	port_name(port));
6084	serge	3328	return;
4560	Serge	3329	}
		3330
		3331	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	3332	if (!intel_dig_port)
		3333	return;
		3334
		3335	intel_encoder = &intel_dig_port->base;
		3336	encoder = &intel_encoder->base;
		3337
		3338	drm_encoder_init(dev, encoder, &intel_ddi_funcs,
6937	serge	3339	DRM_MODE_ENCODER_TMDS, NULL);
3243	Serge	3340
3746	Serge	3341	intel_encoder->compute_config = intel_ddi_compute_config;
3243	Serge	3342	intel_encoder->enable = intel_enable_ddi;
		3343	intel_encoder->pre_enable = intel_ddi_pre_enable;
		3344	intel_encoder->disable = intel_disable_ddi;
		3345	intel_encoder->post_disable = intel_ddi_post_disable;
		3346	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4104	Serge	3347	intel_encoder->get_config = intel_ddi_get_config;
6660	serge	3348	intel_encoder->suspend = intel_dp_encoder_suspend;
3243	Serge	3349
		3350	intel_dig_port->port = port;
4104	Serge	3351	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
		3352	(DDI_BUF_PORT_REVERSAL \|
		3353	DDI_A_4_LANES);
3243	Serge	3354
6937	serge	3355	/*
		3356	* Bspec says that DDI_A_4_LANES is the only supported configuration
		3357	* for Broxton. Yet some BIOS fail to set this bit on port A if eDP
		3358	* wasn't lit up at boot. Force this bit on in our internal
		3359	* configuration so that we use the proper lane count for our
		3360	* calculations.
		3361	*/
		3362	if (IS_BROXTON(dev) && port == PORT_A) {
		3363	if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
		3364	DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
		3365	intel_dig_port->saved_port_bits \|= DDI_A_4_LANES;
		3366	}
		3367	}
		3368
3243	Serge	3369	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
6084	serge	3370	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
5060	serge	3371	intel_encoder->cloneable = 0;
3243	Serge	3372
5060	serge	3373	if (init_dp) {
		3374	if (!intel_ddi_init_dp_connector(intel_dig_port))
		3375	goto err;
4560	Serge	3376
5060	serge	3377	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6084	serge	3378	/*
		3379	* On BXT A0/A1, sw needs to activate DDIA HPD logic and
		3380	* interrupts to check the external panel connection.
		3381	*/
6937	serge	3382	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
6084	serge	3383	dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
		3384	else
		3385	dev_priv->hotplug.irq_port[port] = intel_dig_port;
5060	serge	3386	}
		3387
4560	Serge	3388	/* In theory we don't need the encoder->type check, but leave it just in
		3389	* case we have some really bad VBTs... */
5060	serge	3390	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		3391	if (!intel_ddi_init_hdmi_connector(intel_dig_port))
		3392	goto err;
		3393	}
4560	Serge	3394
5060	serge	3395	return;
		3396
		3397	err:
6084	serge	3398	drm_encoder_cleanup(encoder);
		3399	kfree(intel_dig_port);
3243	Serge	3400	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ddi.c – Rev 6937