WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_ddi.c

Rev	Author	Line No.	Line
3031	serge	1	/*
		2	* Copyright © 2012 Intel Corporation
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice (including the next
		12	* paragraph) shall be included in all copies or substantial portions of the
		13	* Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
		21	* IN THE SOFTWARE.
		22	*
		23	* Authors:
		24	* Eugeni Dodonov
		25	*
		26	*/
		27
		28	#include "i915_drv.h"
		29	#include "intel_drv.h"
		30
5354	serge	31	struct ddi_buf_trans {
		32	u32 trans1; /* balance leg enable, de-emph level */
		33	u32 trans2; /* vref sel, vswing */
6084	serge	34	u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
5354	serge	35	};
		36
3031	serge	37	/* HDMI/DVI modes ignore everything but the last 2 items. So we share
		38	* them for both DP and FDI transports, allowing those ports to
		39	* automatically adapt to HDMI connections as well
		40	*/
5354	serge	41	static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
6084	serge	42	{ 0x00FFFFFF, 0x0006000E, 0x0 },
		43	{ 0x00D75FFF, 0x0005000A, 0x0 },
		44	{ 0x00C30FFF, 0x00040006, 0x0 },
		45	{ 0x80AAAFFF, 0x000B0000, 0x0 },
		46	{ 0x00FFFFFF, 0x0005000A, 0x0 },
		47	{ 0x00D75FFF, 0x000C0004, 0x0 },
		48	{ 0x80C30FFF, 0x000B0000, 0x0 },
		49	{ 0x00FFFFFF, 0x00040006, 0x0 },
		50	{ 0x80D75FFF, 0x000B0000, 0x0 },
3031	serge	51	};
		52
5354	serge	53	static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
6084	serge	54	{ 0x00FFFFFF, 0x0007000E, 0x0 },
		55	{ 0x00D75FFF, 0x000F000A, 0x0 },
		56	{ 0x00C30FFF, 0x00060006, 0x0 },
		57	{ 0x00AAAFFF, 0x001E0000, 0x0 },
		58	{ 0x00FFFFFF, 0x000F000A, 0x0 },
		59	{ 0x00D75FFF, 0x00160004, 0x0 },
		60	{ 0x00C30FFF, 0x001E0000, 0x0 },
		61	{ 0x00FFFFFF, 0x00060006, 0x0 },
		62	{ 0x00D75FFF, 0x001E0000, 0x0 },
3031	serge	63	};
		64
5354	serge	65	static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
		66	/* Idx NT mV d T mV d db */
6084	serge	67	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
		68	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
		69	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
		70	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
		71	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
		72	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
		73	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
		74	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
		75	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
		76	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
		77	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
		78	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
4560	Serge	79	};
		80
5354	serge	81	static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
6084	serge	82	{ 0x00FFFFFF, 0x00000012, 0x0 },
		83	{ 0x00EBAFFF, 0x00020011, 0x0 },
		84	{ 0x00C71FFF, 0x0006000F, 0x0 },
		85	{ 0x00AAAFFF, 0x000E000A, 0x0 },
		86	{ 0x00FFFFFF, 0x00020011, 0x0 },
		87	{ 0x00DB6FFF, 0x0005000F, 0x0 },
		88	{ 0x00BEEFFF, 0x000A000C, 0x0 },
		89	{ 0x00FFFFFF, 0x0005000F, 0x0 },
		90	{ 0x00DB6FFF, 0x000A000C, 0x0 },
4560	Serge	91	};
		92
5354	serge	93	static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
6084	serge	94	{ 0x00FFFFFF, 0x0007000E, 0x0 },
		95	{ 0x00D75FFF, 0x000E000A, 0x0 },
		96	{ 0x00BEFFFF, 0x00140006, 0x0 },
		97	{ 0x80B2CFFF, 0x001B0002, 0x0 },
		98	{ 0x00FFFFFF, 0x000E000A, 0x0 },
		99	{ 0x00DB6FFF, 0x00160005, 0x0 },
		100	{ 0x80C71FFF, 0x001A0002, 0x0 },
		101	{ 0x00F7DFFF, 0x00180004, 0x0 },
		102	{ 0x80D75FFF, 0x001B0002, 0x0 },
4560	Serge	103	};
		104
5354	serge	105	static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
6084	serge	106	{ 0x00FFFFFF, 0x0001000E, 0x0 },
		107	{ 0x00D75FFF, 0x0004000A, 0x0 },
		108	{ 0x00C30FFF, 0x00070006, 0x0 },
		109	{ 0x00AAAFFF, 0x000C0000, 0x0 },
		110	{ 0x00FFFFFF, 0x0004000A, 0x0 },
		111	{ 0x00D75FFF, 0x00090004, 0x0 },
		112	{ 0x00C30FFF, 0x000C0000, 0x0 },
		113	{ 0x00FFFFFF, 0x00070006, 0x0 },
		114	{ 0x00D75FFF, 0x000C0000, 0x0 },
4560	Serge	115	};
		116
5354	serge	117	static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
		118	/* Idx NT mV d T mV df db */
6084	serge	119	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
		120	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
		121	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
		122	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
		123	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
		124	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
		125	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
		126	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
		127	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
		128	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
5354	serge	129	};
		130
6084	serge	131	/* Skylake H and S */
5354	serge	132	static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6084	serge	133	{ 0x00002016, 0x000000A0, 0x0 },
		134	{ 0x00005012, 0x0000009B, 0x0 },
		135	{ 0x00007011, 0x00000088, 0x0 },
		136	{ 0x00009010, 0x000000C7, 0x0 },
		137	{ 0x00002016, 0x0000009B, 0x0 },
		138	{ 0x00005012, 0x00000088, 0x0 },
		139	{ 0x00007011, 0x000000C7, 0x0 },
		140	{ 0x00002016, 0x000000DF, 0x0 },
		141	{ 0x00005012, 0x000000C7, 0x0 },
5354	serge	142	};
		143
6084	serge	144	/* Skylake U */
		145	static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
		146	{ 0x0000201B, 0x000000A2, 0x0 },
		147	{ 0x00005012, 0x00000088, 0x0 },
		148	{ 0x00007011, 0x00000087, 0x0 },
		149	{ 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
		150	{ 0x0000201B, 0x0000009D, 0x0 },
		151	{ 0x00005012, 0x000000C7, 0x0 },
		152	{ 0x00007011, 0x000000C7, 0x0 },
		153	{ 0x00002016, 0x00000088, 0x0 },
		154	{ 0x00005012, 0x000000C7, 0x0 },
		155	};
		156
		157	/* Skylake Y */
		158	static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
		159	{ 0x00000018, 0x000000A2, 0x0 },
		160	{ 0x00005012, 0x00000088, 0x0 },
		161	{ 0x00007011, 0x00000087, 0x0 },
		162	{ 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
		163	{ 0x00000018, 0x0000009D, 0x0 },
		164	{ 0x00005012, 0x000000C7, 0x0 },
		165	{ 0x00007011, 0x000000C7, 0x0 },
		166	{ 0x00000018, 0x00000088, 0x0 },
		167	{ 0x00005012, 0x000000C7, 0x0 },
		168	};
		169
		170	/*
		171	* Skylake H and S
		172	* eDP 1.4 low vswing translation parameters
		173	*/
		174	static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
		175	{ 0x00000018, 0x000000A8, 0x0 },
		176	{ 0x00004013, 0x000000A9, 0x0 },
		177	{ 0x00007011, 0x000000A2, 0x0 },
		178	{ 0x00009010, 0x0000009C, 0x0 },
		179	{ 0x00000018, 0x000000A9, 0x0 },
		180	{ 0x00006013, 0x000000A2, 0x0 },
		181	{ 0x00007011, 0x000000A6, 0x0 },
		182	{ 0x00000018, 0x000000AB, 0x0 },
		183	{ 0x00007013, 0x0000009F, 0x0 },
		184	{ 0x00000018, 0x000000DF, 0x0 },
		185	};
		186
		187	/*
		188	* Skylake U
		189	* eDP 1.4 low vswing translation parameters
		190	*/
		191	static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
		192	{ 0x00000018, 0x000000A8, 0x0 },
		193	{ 0x00004013, 0x000000A9, 0x0 },
		194	{ 0x00007011, 0x000000A2, 0x0 },
		195	{ 0x00009010, 0x0000009C, 0x0 },
		196	{ 0x00000018, 0x000000A9, 0x0 },
		197	{ 0x00006013, 0x000000A2, 0x0 },
		198	{ 0x00007011, 0x000000A6, 0x0 },
		199	{ 0x00002016, 0x000000AB, 0x0 },
		200	{ 0x00005013, 0x0000009F, 0x0 },
		201	{ 0x00000018, 0x000000DF, 0x0 },
		202	};
		203
		204	/*
		205	* Skylake Y
		206	* eDP 1.4 low vswing translation parameters
		207	*/
		208	static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
		209	{ 0x00000018, 0x000000A8, 0x0 },
		210	{ 0x00004013, 0x000000AB, 0x0 },
		211	{ 0x00007011, 0x000000A4, 0x0 },
		212	{ 0x00009010, 0x000000DF, 0x0 },
		213	{ 0x00000018, 0x000000AA, 0x0 },
		214	{ 0x00006013, 0x000000A4, 0x0 },
		215	{ 0x00007011, 0x0000009D, 0x0 },
		216	{ 0x00000018, 0x000000A0, 0x0 },
		217	{ 0x00006012, 0x000000DF, 0x0 },
		218	{ 0x00000018, 0x0000008A, 0x0 },
		219	};
		220
		221	/* Skylake U, H and S */
5354	serge	222	static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
6084	serge	223	{ 0x00000018, 0x000000AC, 0x0 },
		224	{ 0x00005012, 0x0000009D, 0x0 },
		225	{ 0x00007011, 0x00000088, 0x0 },
		226	{ 0x00000018, 0x000000A1, 0x0 },
		227	{ 0x00000018, 0x00000098, 0x0 },
		228	{ 0x00004013, 0x00000088, 0x0 },
		229	{ 0x00006012, 0x00000087, 0x0 },
		230	{ 0x00000018, 0x000000DF, 0x0 },
		231	{ 0x00003015, 0x00000087, 0x0 }, /* Default */
		232	{ 0x00003015, 0x000000C7, 0x0 },
		233	{ 0x00000018, 0x000000C7, 0x0 },
5354	serge	234	};
		235
6084	serge	236	/* Skylake Y */
		237	static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
		238	{ 0x00000018, 0x000000A1, 0x0 },
		239	{ 0x00005012, 0x000000DF, 0x0 },
		240	{ 0x00007011, 0x00000084, 0x0 },
		241	{ 0x00000018, 0x000000A4, 0x0 },
		242	{ 0x00000018, 0x0000009D, 0x0 },
		243	{ 0x00004013, 0x00000080, 0x0 },
		244	{ 0x00006013, 0x000000C7, 0x0 },
		245	{ 0x00000018, 0x0000008A, 0x0 },
		246	{ 0x00003015, 0x000000C7, 0x0 }, /* Default */
		247	{ 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
		248	{ 0x00000018, 0x000000C7, 0x0 },
		249	};
		250
		251	struct bxt_ddi_buf_trans {
		252	u32 margin; /* swing value */
		253	u32 scale; /* scale value */
		254	u32 enable; /* scale enable */
		255	u32 deemphasis;
		256	bool default_index; /* true if the entry represents default value */
		257	};
		258
		259	static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
		260	/* Idx NT mV diff db */
		261	{ 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
		262	{ 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
		263	{ 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
		264	{ 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
		265	{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
		266	{ 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
		267	{ 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
		268	{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
		269	{ 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
		270	{ 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
		271	};
		272
		273	static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
		274	/* Idx NT mV diff db */
		275	{ 26, 0, 0, 128, false }, /* 0: 200 0 */
		276	{ 38, 0, 0, 112, false }, /* 1: 200 1.5 */
		277	{ 48, 0, 0, 96, false }, /* 2: 200 4 */
		278	{ 54, 0, 0, 69, false }, /* 3: 200 6 */
		279	{ 32, 0, 0, 128, false }, /* 4: 250 0 */
		280	{ 48, 0, 0, 104, false }, /* 5: 250 1.5 */
		281	{ 54, 0, 0, 85, false }, /* 6: 250 4 */
		282	{ 43, 0, 0, 128, false }, /* 7: 300 0 */
		283	{ 54, 0, 0, 101, false }, /* 8: 300 1.5 */
		284	{ 48, 0, 0, 128, false }, /* 9: 300 0 */
		285	};
		286
		287	/* BSpec has 2 recommended values - entries 0 and 8.
		288	* Using the entry with higher vswing.
		289	*/
		290	static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
		291	/* Idx NT mV diff db */
		292	{ 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
		293	{ 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
		294	{ 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
		295	{ 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
		296	{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
		297	{ 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
		298	{ 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
		299	{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
		300	{ 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
		301	{ 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
		302	};
		303
		304	static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
		305	enum port port, int type);
		306
		307	static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
		308	struct intel_digital_port **dig_port,
		309	enum port *port)
3243	Serge	310	{
		311	struct drm_encoder *encoder = &intel_encoder->base;
		312
6084	serge	313	switch (intel_encoder->type) {
		314	case INTEL_OUTPUT_DP_MST:
		315	*dig_port = enc_to_mst(encoder)->primary;
		316	port = (dig_port)->port;
		317	break;
		318	case INTEL_OUTPUT_DISPLAYPORT:
		319	case INTEL_OUTPUT_EDP:
		320	case INTEL_OUTPUT_HDMI:
		321	case INTEL_OUTPUT_UNKNOWN:
		322	*dig_port = enc_to_dig_port(encoder);
		323	port = (dig_port)->port;
		324	break;
		325	case INTEL_OUTPUT_ANALOG:
		326	*dig_port = NULL;
		327	*port = PORT_E;
		328	break;
		329	default:
		330	WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
		331	break;
		332	}
		333	}
3243	Serge	334
6084	serge	335	enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
		336	{
		337	struct intel_digital_port *dig_port;
		338	enum port port;
3243	Serge	339
6084	serge	340	ddi_get_encoder_port(intel_encoder, &dig_port, &port);
		341
		342	return port;
		343	}
		344
		345	static bool
		346	intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
		347	{
		348	return intel_dig_port->hdmi.hdmi_reg;
		349	}
		350
		351	static const struct ddi_buf_trans skl_get_buf_trans_dp(struct drm_device dev,
		352	int *n_entries)
		353	{
		354	const struct ddi_buf_trans *ddi_translations;
		355
		356	if (IS_SKL_ULX(dev)) {
		357	ddi_translations = skl_y_ddi_translations_dp;
		358	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
		359	} else if (IS_SKL_ULT(dev)) {
		360	ddi_translations = skl_u_ddi_translations_dp;
		361	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
3243	Serge	362	} else {
6084	serge	363	ddi_translations = skl_ddi_translations_dp;
		364	*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
3243	Serge	365	}
6084	serge	366
		367	return ddi_translations;
3243	Serge	368	}
		369
6084	serge	370	static const struct ddi_buf_trans skl_get_buf_trans_edp(struct drm_device dev,
		371	int *n_entries)
		372	{
		373	struct drm_i915_private *dev_priv = dev->dev_private;
		374	const struct ddi_buf_trans *ddi_translations;
		375
		376	if (IS_SKL_ULX(dev)) {
		377	if (dev_priv->edp_low_vswing) {
		378	ddi_translations = skl_y_ddi_translations_edp;
		379	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
		380	} else {
		381	ddi_translations = skl_y_ddi_translations_dp;
		382	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
		383	}
		384	} else if (IS_SKL_ULT(dev)) {
		385	if (dev_priv->edp_low_vswing) {
		386	ddi_translations = skl_u_ddi_translations_edp;
		387	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
		388	} else {
		389	ddi_translations = skl_u_ddi_translations_dp;
		390	*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
		391	}
		392	} else {
		393	if (dev_priv->edp_low_vswing) {
		394	ddi_translations = skl_ddi_translations_edp;
		395	*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
		396	} else {
		397	ddi_translations = skl_ddi_translations_dp;
		398	*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
		399	}
		400	}
		401
		402	return ddi_translations;
		403	}
		404
		405	static const struct ddi_buf_trans *
		406	skl_get_buf_trans_hdmi(struct drm_device *dev,
		407	int *n_entries)
		408	{
		409	const struct ddi_buf_trans *ddi_translations;
		410
		411	if (IS_SKL_ULX(dev)) {
		412	ddi_translations = skl_y_ddi_translations_hdmi;
		413	*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
		414	} else {
		415	ddi_translations = skl_ddi_translations_hdmi;
		416	*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
		417	}
		418
		419	return ddi_translations;
		420	}
		421
4560	Serge	422	/*
		423	* Starting with Haswell, DDI port buffers must be programmed with correct
		424	* values in advance. The buffer values are different for FDI and DP modes,
3031	serge	425	* but the HDMI/DVI fields are shared among those. So we program the DDI
		426	* in either FDI or DP modes only, as HDMI connections will work with both
		427	* of those
		428	*/
6084	serge	429	static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
		430	bool supports_hdmi)
3031	serge	431	{
		432	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	433	u32 iboost_bit = 0;
		434	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
		435	size;
4560	Serge	436	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
5354	serge	437	const struct ddi_buf_trans *ddi_translations_fdi;
		438	const struct ddi_buf_trans *ddi_translations_dp;
		439	const struct ddi_buf_trans *ddi_translations_edp;
		440	const struct ddi_buf_trans *ddi_translations_hdmi;
		441	const struct ddi_buf_trans *ddi_translations;
3031	serge	442
6084	serge	443	if (IS_BROXTON(dev)) {
		444	if (!supports_hdmi)
		445	return;
		446
		447	/* Vswing programming for HDMI */
		448	bxt_ddi_vswing_sequence(dev, hdmi_level, port,
		449	INTEL_OUTPUT_HDMI);
		450	return;
		451	} else if (IS_SKYLAKE(dev)) {
5354	serge	452	ddi_translations_fdi = NULL;
6084	serge	453	ddi_translations_dp =
		454	skl_get_buf_trans_dp(dev, &n_dp_entries);
		455	ddi_translations_edp =
		456	skl_get_buf_trans_edp(dev, &n_edp_entries);
		457	ddi_translations_hdmi =
		458	skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
		459	hdmi_default_entry = 8;
		460	/* If we're boosting the current, set bit 31 of trans1 */
		461	if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level \|\|
		462	dev_priv->vbt.ddi_port_info[port].dp_boost_level)
		463	iboost_bit = 1<<31;
5354	serge	464	} else if (IS_BROADWELL(dev)) {
4560	Serge	465	ddi_translations_fdi = bdw_ddi_translations_fdi;
		466	ddi_translations_dp = bdw_ddi_translations_dp;
6660	serge	467
		468	if (dev_priv->edp_low_vswing) {
4560	Serge	469	ddi_translations_edp = bdw_ddi_translations_edp;
6660	serge	470	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		471	} else {
		472	ddi_translations_edp = bdw_ddi_translations_dp;
		473	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		474	}
		475
5354	serge	476	ddi_translations_hdmi = bdw_ddi_translations_hdmi;
6660	serge	477
6084	serge	478	n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
5354	serge	479	n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
6084	serge	480	hdmi_default_entry = 7;
4560	Serge	481	} else if (IS_HASWELL(dev)) {
		482	ddi_translations_fdi = hsw_ddi_translations_fdi;
		483	ddi_translations_dp = hsw_ddi_translations_dp;
		484	ddi_translations_edp = hsw_ddi_translations_dp;
5354	serge	485	ddi_translations_hdmi = hsw_ddi_translations_hdmi;
6084	serge	486	n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
5354	serge	487	n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
6084	serge	488	hdmi_default_entry = 6;
4560	Serge	489	} else {
		490	WARN(1, "ddi translation table missing\n");
		491	ddi_translations_edp = bdw_ddi_translations_dp;
		492	ddi_translations_fdi = bdw_ddi_translations_fdi;
		493	ddi_translations_dp = bdw_ddi_translations_dp;
5354	serge	494	ddi_translations_hdmi = bdw_ddi_translations_hdmi;
6084	serge	495	n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		496	n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
5354	serge	497	n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
6084	serge	498	hdmi_default_entry = 7;
4560	Serge	499	}
		500
		501	switch (port) {
		502	case PORT_A:
		503	ddi_translations = ddi_translations_edp;
6084	serge	504	size = n_edp_entries;
4560	Serge	505	break;
		506	case PORT_B:
		507	case PORT_C:
		508	ddi_translations = ddi_translations_dp;
6084	serge	509	size = n_dp_entries;
4560	Serge	510	break;
		511	case PORT_D:
6084	serge	512	if (intel_dp_is_edp(dev, PORT_D)) {
4560	Serge	513	ddi_translations = ddi_translations_edp;
6084	serge	514	size = n_edp_entries;
		515	} else {
4560	Serge	516	ddi_translations = ddi_translations_dp;
6084	serge	517	size = n_dp_entries;
		518	}
4560	Serge	519	break;
		520	case PORT_E:
5354	serge	521	if (ddi_translations_fdi)
6084	serge	522	ddi_translations = ddi_translations_fdi;
5354	serge	523	else
		524	ddi_translations = ddi_translations_dp;
6084	serge	525	size = n_dp_entries;
4560	Serge	526	break;
		527	default:
		528	BUG();
		529	}
		530
6084	serge	531	for (i = 0; i < size; i++) {
		532	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
		533	ddi_translations[i].trans1 \| iboost_bit);
		534	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
		535	ddi_translations[i].trans2);
3031	serge	536	}
5354	serge	537
6084	serge	538	if (!supports_hdmi)
		539	return;
		540
5354	serge	541	/* Choose a good default if VBT is badly populated */
		542	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN \|\|
		543	hdmi_level >= n_hdmi_entries)
6084	serge	544	hdmi_level = hdmi_default_entry;
5354	serge	545
4560	Serge	546	/* Entry 9 is for HDMI: */
6084	serge	547	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
		548	ddi_translations_hdmi[hdmi_level].trans1 \| iboost_bit);
		549	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
		550	ddi_translations_hdmi[hdmi_level].trans2);
3031	serge	551	}
		552
		553	/* Program DDI buffers translations for DP. By default, program ports A-D in DP
		554	* mode and port E for FDI.
		555	*/
		556	void intel_prepare_ddi(struct drm_device *dev)
		557	{
6084	serge	558	struct intel_encoder *intel_encoder;
		559	bool visited[I915_MAX_PORTS] = { 0, };
3031	serge	560
3480	Serge	561	if (!HAS_DDI(dev))
		562	return;
		563
6084	serge	564	for_each_intel_encoder(dev, intel_encoder) {
		565	struct intel_digital_port *intel_dig_port;
		566	enum port port;
		567	bool supports_hdmi;
		568
		569	if (intel_encoder->type == INTEL_OUTPUT_DSI)
		570	continue;
		571
		572	ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
		573	if (visited[port])
		574	continue;
		575
		576	supports_hdmi = intel_dig_port &&
		577	intel_dig_port_supports_hdmi(intel_dig_port);
		578
		579	intel_prepare_ddi_buffers(dev, port, supports_hdmi);
		580	visited[port] = true;
		581	}
3031	serge	582	}
		583
3243	Serge	584	static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
		585	enum port port)
		586	{
		587	uint32_t reg = DDI_BUF_CTL(port);
		588	int i;
3031	serge	589
6084	serge	590	for (i = 0; i < 16; i++) {
3243	Serge	591	udelay(1);
		592	if (I915_READ(reg) & DDI_BUF_IS_IDLE)
		593	return;
		594	}
		595	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
		596	}
		597
3031	serge	598	/* Starting with Haswell, different DDI ports can work in FDI mode for
		599	* connection to the PCH-located connectors. For this, it is necessary to train
		600	* both the DDI port and PCH receiver for the desired DDI buffer settings.
		601	*
		602	* The recommended port to work in FDI mode is DDI E, which we use here. Also,
		603	* please note that when FDI mode is active on DDI E, it shares 2 lines with
		604	* DDI A (which is used for eDP)
		605	*/
		606
		607	void hsw_fdi_link_train(struct drm_crtc *crtc)
		608	{
		609	struct drm_device *dev = crtc->dev;
		610	struct drm_i915_private *dev_priv = dev->dev_private;
		611	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	612	u32 temp, i, rx_ctl_val;
3031	serge	613
3243	Serge	614	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
		615	* mode set "sequence for CRT port" document:
		616	* - TP1 to TP2 time with the default value
		617	* - FDI delay to 90h
4104	Serge	618	*
		619	* WaFDIAutoLinkSetTimingOverrride:hsw
3243	Serge	620	*/
6084	serge	621	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) \|
3243	Serge	622	FDI_RX_PWRDN_LANE0_VAL(2) \|
		623	FDI_RX_TP1_TO_TP2_48 \| FDI_RX_FDI_DELAY_90);
3031	serge	624
3243	Serge	625	/* Enable the PCH Receiver FDI PLL */
3480	Serge	626	rx_ctl_val = dev_priv->fdi_rx_config \| FDI_RX_ENHANCE_FRAME_ENABLE \|
4104	Serge	627	FDI_RX_PLL_ENABLE \|
6084	serge	628	FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
		629	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		630	POSTING_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	631	udelay(220);
3031	serge	632
3243	Serge	633	/* Switch from Rawclk to PCDclk */
		634	rx_ctl_val \|= FDI_PCDCLK;
6084	serge	635	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
3031	serge	636
3243	Serge	637	/* Configure Port Clock Select */
6084	serge	638	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
		639	WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
3243	Serge	640
		641	/* Start the training iterating through available voltages and emphasis,
		642	* testing each value twice. */
5354	serge	643	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
3031	serge	644	/* Configure DP_TP_CTL with auto-training */
		645	I915_WRITE(DP_TP_CTL(PORT_E),
		646	DP_TP_CTL_FDI_AUTOTRAIN \|
		647	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		648	DP_TP_CTL_LINK_TRAIN_PAT1 \|
		649	DP_TP_CTL_ENABLE);
		650
3480	Serge	651	/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		652	* DDI E does not support port reversal, the functionality is
		653	* achieved on the PCH side in FDI_RX_CTL, so no need to set the
		654	* port reversal bit */
3031	serge	655	I915_WRITE(DDI_BUF_CTL(PORT_E),
6084	serge	656	DDI_BUF_CTL_ENABLE \|
		657	((intel_crtc->config->fdi_lanes - 1) << 1) \|
5354	serge	658	DDI_BUF_TRANS_SELECT(i / 2));
3243	Serge	659	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	660
		661	udelay(600);
		662
3243	Serge	663	/* Program PCH FDI Receiver TU */
6084	serge	664	I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
3031	serge	665
3243	Serge	666	/* Enable PCH FDI Receiver with auto-training */
		667	rx_ctl_val \|= FDI_RX_ENABLE \| FDI_LINK_TRAIN_AUTO;
6084	serge	668	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		669	POSTING_READ(FDI_RX_CTL(PIPE_A));
3031	serge	670
3243	Serge	671	/* Wait for FDI receiver lane calibration */
		672	udelay(30);
		673
		674	/* Unset FDI_RX_MISC pwrdn lanes */
6084	serge	675	temp = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	676	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
6084	serge	677	I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		678	POSTING_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	679
		680	/* Wait for FDI auto training time */
		681	udelay(5);
		682
3031	serge	683	temp = I915_READ(DP_TP_STATUS(PORT_E));
		684	if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
3243	Serge	685	DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
3031	serge	686
		687	/* Enable normal pixel sending for FDI */
		688	I915_WRITE(DP_TP_CTL(PORT_E),
6084	serge	689	DP_TP_CTL_FDI_AUTOTRAIN \|
		690	DP_TP_CTL_LINK_TRAIN_NORMAL \|
		691	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
		692	DP_TP_CTL_ENABLE);
3031	serge	693
3243	Serge	694	return;
3031	serge	695	}
		696
3243	Serge	697	temp = I915_READ(DDI_BUF_CTL(PORT_E));
		698	temp &= ~DDI_BUF_CTL_ENABLE;
		699	I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		700	POSTING_READ(DDI_BUF_CTL(PORT_E));
3031	serge	701
3243	Serge	702	/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
		703	temp = I915_READ(DP_TP_CTL(PORT_E));
		704	temp &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		705	temp \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		706	I915_WRITE(DP_TP_CTL(PORT_E), temp);
		707	POSTING_READ(DP_TP_CTL(PORT_E));
3031	serge	708
3243	Serge	709	intel_wait_ddi_buf_idle(dev_priv, PORT_E);
		710
		711	rx_ctl_val &= ~FDI_RX_ENABLE;
6084	serge	712	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		713	POSTING_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	714
		715	/* Reset FDI_RX_MISC pwrdn lanes */
6084	serge	716	temp = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	717	temp &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		718	temp \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
6084	serge	719	I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		720	POSTING_READ(FDI_RX_MISC(PIPE_A));
3031	serge	721	}
3243	Serge	722
		723	DRM_ERROR("FDI link training failed!\n");
3031	serge	724	}
		725
5060	serge	726	void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
3031	serge	727	{
5060	serge	728	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		729	struct intel_digital_port *intel_dig_port =
		730	enc_to_dig_port(&encoder->base);
3031	serge	731
5060	serge	732	intel_dp->DP = intel_dig_port->saved_port_bits \|
5354	serge	733	DDI_BUF_CTL_ENABLE \| DDI_BUF_TRANS_SELECT(0);
5060	serge	734	intel_dp->DP \|= DDI_PORT_WIDTH(intel_dp->lane_count);
3243	Serge	735	}
		736
		737	static struct intel_encoder *
		738	intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
		739	{
		740	struct drm_device *dev = crtc->dev;
		741	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		742	struct intel_encoder intel_encoder, ret = NULL;
		743	int num_encoders = 0;
		744
		745	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		746	ret = intel_encoder;
		747	num_encoders++;
		748	}
		749
		750	if (num_encoders != 1)
4104	Serge	751	WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
		752	pipe_name(intel_crtc->pipe));
3243	Serge	753
		754	BUG_ON(ret == NULL);
		755	return ret;
		756	}
		757
6084	serge	758	struct intel_encoder *
		759	intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
5354	serge	760	{
6084	serge	761	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
		762	struct intel_encoder *ret = NULL;
		763	struct drm_atomic_state *state;
		764	struct drm_connector *connector;
		765	struct drm_connector_state *connector_state;
5354	serge	766	int num_encoders = 0;
6084	serge	767	int i;
5354	serge	768
6084	serge	769	state = crtc_state->base.state;
		770
		771	for_each_connector_in_state(state, connector, connector_state, i) {
		772	if (connector_state->crtc != crtc_state->base.crtc)
		773	continue;
		774
		775	ret = to_intel_encoder(connector_state->best_encoder);
		776	num_encoders++;
5354	serge	777	}
		778
		779	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
		780	pipe_name(crtc->pipe));
		781
		782	BUG_ON(ret == NULL);
		783	return ret;
		784	}
		785
4104	Serge	786	#define LC_FREQ 2700
5354	serge	787	#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
4104	Serge	788
		789	#define P_MIN 2
		790	#define P_MAX 64
		791	#define P_INC 2
		792
		793	/* Constraints for PLL good behavior */
		794	#define REF_MIN 48
		795	#define REF_MAX 400
		796	#define VCO_MIN 2400
		797	#define VCO_MAX 4800
		798
5354	serge	799	#define abs_diff(a, b) ({ \
		800	typeof(a) __a = (a); \
		801	typeof(b) __b = (b); \
		802	(void) (&__a == &__b); \
		803	__a > __b ? (__a - __b) : (__b - __a); })
4104	Serge	804
6084	serge	805	struct hsw_wrpll_rnp {
4104	Serge	806	unsigned p, n2, r2;
		807	};
		808
6084	serge	809	static unsigned hsw_wrpll_get_budget_for_freq(int clock)
3243	Serge	810	{
4104	Serge	811	unsigned budget;
3243	Serge	812
4104	Serge	813	switch (clock) {
		814	case 25175000:
		815	case 25200000:
		816	case 27000000:
		817	case 27027000:
		818	case 37762500:
		819	case 37800000:
		820	case 40500000:
		821	case 40541000:
		822	case 54000000:
		823	case 54054000:
		824	case 59341000:
		825	case 59400000:
		826	case 72000000:
		827	case 74176000:
		828	case 74250000:
		829	case 81000000:
		830	case 81081000:
		831	case 89012000:
		832	case 89100000:
		833	case 108000000:
		834	case 108108000:
		835	case 111264000:
		836	case 111375000:
		837	case 148352000:
		838	case 148500000:
		839	case 162000000:
		840	case 162162000:
		841	case 222525000:
		842	case 222750000:
		843	case 296703000:
		844	case 297000000:
		845	budget = 0;
		846	break;
		847	case 233500000:
		848	case 245250000:
		849	case 247750000:
		850	case 253250000:
		851	case 298000000:
		852	budget = 1500;
		853	break;
		854	case 169128000:
		855	case 169500000:
		856	case 179500000:
		857	case 202000000:
		858	budget = 2000;
		859	break;
		860	case 256250000:
		861	case 262500000:
		862	case 270000000:
		863	case 272500000:
		864	case 273750000:
		865	case 280750000:
		866	case 281250000:
		867	case 286000000:
		868	case 291750000:
		869	budget = 4000;
		870	break;
		871	case 267250000:
		872	case 268500000:
		873	budget = 5000;
6084	serge	874	break;
4104	Serge	875	default:
		876	budget = 1000;
		877	break;
		878	}
3031	serge	879
4104	Serge	880	return budget;
		881	}
3031	serge	882
6084	serge	883	static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
		884	unsigned r2, unsigned n2, unsigned p,
		885	struct hsw_wrpll_rnp *best)
4104	Serge	886	{
		887	uint64_t a, b, c, d, diff, diff_best;
3031	serge	888
4104	Serge	889	/* No best (r,n,p) yet */
		890	if (best->p == 0) {
		891	best->p = p;
		892	best->n2 = n2;
		893	best->r2 = r2;
		894	return;
		895	}
3031	serge	896
4104	Serge	897	/*
		898	* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
		899	* freq2k.
		900	*
		901	* delta = 1e6 *
		902	* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
		903	* freq2k;
		904	*
		905	* and we would like delta <= budget.
		906	*
		907	* If the discrepancy is above the PPM-based budget, always prefer to
		908	* improve upon the previous solution. However, if you're within the
		909	* budget, try to maximize Ref * VCO, that is N / (P * R^2).
		910	*/
		911	a = freq2k * budget * p * r2;
		912	b = freq2k * budget * best->p * best->r2;
5354	serge	913	diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
		914	diff_best = abs_diff(freq2k * best->p * best->r2,
		915	LC_FREQ_2K * best->n2);
4104	Serge	916	c = 1000000 * diff;
		917	d = 1000000 * diff_best;
		918
		919	if (a < c && b < d) {
		920	/* If both are above the budget, pick the closer */
		921	if (best->p * best->r2 * diff < p * r2 * diff_best) {
		922	best->p = p;
		923	best->n2 = n2;
		924	best->r2 = r2;
		925	}
		926	} else if (a >= c && b < d) {
		927	/* If A is below the threshold but B is above it? Update. */
		928	best->p = p;
		929	best->n2 = n2;
		930	best->r2 = r2;
		931	} else if (a >= c && b >= d) {
		932	/* Both are below the limit, so pick the higher n2/(r2r2) /
		933	if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
		934	best->p = p;
		935	best->n2 = n2;
		936	best->r2 = r2;
		937	}
		938	}
		939	/* Otherwise a < c && b >= d, do nothing */
3243	Serge	940	}
3031	serge	941
6084	serge	942	static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
5060	serge	943	{
		944	int refclk = LC_FREQ;
		945	int n, p, r;
		946	u32 wrpll;
		947
		948	wrpll = I915_READ(reg);
		949	switch (wrpll & WRPLL_PLL_REF_MASK) {
		950	case WRPLL_PLL_SSC:
		951	case WRPLL_PLL_NON_SSC:
		952	/*
		953	* We could calculate spread here, but our checking
		954	* code only cares about 5% accuracy, and spread is a max of
		955	* 0.5% downspread.
		956	*/
		957	refclk = 135;
		958	break;
		959	case WRPLL_PLL_LCPLL:
		960	refclk = LC_FREQ;
		961	break;
		962	default:
		963	WARN(1, "bad wrpll refclk\n");
		964	return 0;
		965	}
		966
		967	r = wrpll & WRPLL_DIVIDER_REF_MASK;
		968	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
		969	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
		970
		971	/* Convert to KHz, p & r have a fixed point portion */
		972	return (refclk * n * 100) / (p * r);
		973	}
		974
5354	serge	975	static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
		976	uint32_t dpll)
		977	{
		978	uint32_t cfgcr1_reg, cfgcr2_reg;
		979	uint32_t cfgcr1_val, cfgcr2_val;
		980	uint32_t p0, p1, p2, dco_freq;
		981
6084	serge	982	cfgcr1_reg = DPLL_CFGCR1(dpll);
		983	cfgcr2_reg = DPLL_CFGCR2(dpll);
5354	serge	984
		985	cfgcr1_val = I915_READ(cfgcr1_reg);
		986	cfgcr2_val = I915_READ(cfgcr2_reg);
		987
		988	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
		989	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
		990
		991	if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
		992	p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
		993	else
		994	p1 = 1;
		995
		996
		997	switch (p0) {
		998	case DPLL_CFGCR2_PDIV_1:
		999	p0 = 1;
		1000	break;
		1001	case DPLL_CFGCR2_PDIV_2:
		1002	p0 = 2;
		1003	break;
		1004	case DPLL_CFGCR2_PDIV_3:
		1005	p0 = 3;
		1006	break;
		1007	case DPLL_CFGCR2_PDIV_7:
		1008	p0 = 7;
		1009	break;
		1010	}
		1011
		1012	switch (p2) {
		1013	case DPLL_CFGCR2_KDIV_5:
		1014	p2 = 5;
		1015	break;
		1016	case DPLL_CFGCR2_KDIV_2:
		1017	p2 = 2;
		1018	break;
		1019	case DPLL_CFGCR2_KDIV_3:
		1020	p2 = 3;
		1021	break;
		1022	case DPLL_CFGCR2_KDIV_1:
		1023	p2 = 1;
		1024	break;
		1025	}
		1026
		1027	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
		1028
		1029	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1030	1000) / 0x8000;
		1031
		1032	return dco_freq / (p0 * p1 * p2 * 5);
		1033	}
		1034
6084	serge	1035	static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
		1036	{
		1037	int dotclock;
5354	serge	1038
6084	serge	1039	if (pipe_config->has_pch_encoder)
		1040	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
		1041	&pipe_config->fdi_m_n);
		1042	else if (pipe_config->has_dp_encoder)
		1043	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
		1044	&pipe_config->dp_m_n);
		1045	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
		1046	dotclock = pipe_config->port_clock * 2 / 3;
		1047	else
		1048	dotclock = pipe_config->port_clock;
		1049
		1050	if (pipe_config->pixel_multiplier)
		1051	dotclock /= pipe_config->pixel_multiplier;
		1052
		1053	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
		1054	}
		1055
5354	serge	1056	static void skl_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1057	struct intel_crtc_state *pipe_config)
5060	serge	1058	{
		1059	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1060	int link_clock = 0;
5354	serge	1061	uint32_t dpll_ctl1, dpll;
		1062
		1063	dpll = pipe_config->ddi_pll_sel;
		1064
		1065	dpll_ctl1 = I915_READ(DPLL_CTRL1);
		1066
		1067	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		1068	link_clock = skl_calc_wrpll_link(dev_priv, dpll);
		1069	} else {
6084	serge	1070	link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
		1071	link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
5354	serge	1072
		1073	switch (link_clock) {
6084	serge	1074	case DPLL_CTRL1_LINK_RATE_810:
5354	serge	1075	link_clock = 81000;
		1076	break;
6084	serge	1077	case DPLL_CTRL1_LINK_RATE_1080:
		1078	link_clock = 108000;
		1079	break;
		1080	case DPLL_CTRL1_LINK_RATE_1350:
5354	serge	1081	link_clock = 135000;
		1082	break;
6084	serge	1083	case DPLL_CTRL1_LINK_RATE_1620:
		1084	link_clock = 162000;
		1085	break;
		1086	case DPLL_CTRL1_LINK_RATE_2160:
		1087	link_clock = 216000;
		1088	break;
		1089	case DPLL_CTRL1_LINK_RATE_2700:
5354	serge	1090	link_clock = 270000;
		1091	break;
		1092	default:
		1093	WARN(1, "Unsupported link rate\n");
		1094	break;
		1095	}
		1096	link_clock *= 2;
		1097	}
		1098
		1099	pipe_config->port_clock = link_clock;
		1100
6084	serge	1101	ddi_dotclock_get(pipe_config);
5354	serge	1102	}
		1103
		1104	static void hsw_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1105	struct intel_crtc_state *pipe_config)
5354	serge	1106	{
		1107	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1108	int link_clock = 0;
5060	serge	1109	u32 val, pll;
		1110
		1111	val = pipe_config->ddi_pll_sel;
		1112	switch (val & PORT_CLK_SEL_MASK) {
		1113	case PORT_CLK_SEL_LCPLL_810:
		1114	link_clock = 81000;
		1115	break;
		1116	case PORT_CLK_SEL_LCPLL_1350:
		1117	link_clock = 135000;
		1118	break;
		1119	case PORT_CLK_SEL_LCPLL_2700:
		1120	link_clock = 270000;
		1121	break;
		1122	case PORT_CLK_SEL_WRPLL1:
6084	serge	1123	link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
5060	serge	1124	break;
		1125	case PORT_CLK_SEL_WRPLL2:
6084	serge	1126	link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
5060	serge	1127	break;
		1128	case PORT_CLK_SEL_SPLL:
		1129	pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		1130	if (pll == SPLL_PLL_FREQ_810MHz)
		1131	link_clock = 81000;
		1132	else if (pll == SPLL_PLL_FREQ_1350MHz)
		1133	link_clock = 135000;
		1134	else if (pll == SPLL_PLL_FREQ_2700MHz)
		1135	link_clock = 270000;
		1136	else {
		1137	WARN(1, "bad spll freq\n");
		1138	return;
		1139	}
		1140	break;
		1141	default:
		1142	WARN(1, "bad port clock sel\n");
		1143	return;
		1144	}
		1145
		1146	pipe_config->port_clock = link_clock * 2;
		1147
6084	serge	1148	ddi_dotclock_get(pipe_config);
5060	serge	1149	}
		1150
6084	serge	1151	static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
		1152	enum intel_dpll_id dpll)
		1153	{
		1154	struct intel_shared_dpll *pll;
		1155	struct intel_dpll_hw_state *state;
		1156	intel_clock_t clock;
		1157
		1158	/* For DDI ports we always use a shared PLL. */
		1159	if (WARN_ON(dpll == DPLL_ID_PRIVATE))
		1160	return 0;
		1161
		1162	pll = &dev_priv->shared_dplls[dpll];
		1163	state = &pll->config.hw_state;
		1164
		1165	clock.m1 = 2;
		1166	clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
		1167	if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
		1168	clock.m2 \|= state->pll2 & PORT_PLL_M2_FRAC_MASK;
		1169	clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
		1170	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
		1171	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
		1172
		1173	return chv_calc_dpll_params(100000, &clock);
		1174	}
		1175
		1176	static void bxt_ddi_clock_get(struct intel_encoder *encoder,
		1177	struct intel_crtc_state *pipe_config)
		1178	{
		1179	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		1180	enum port port = intel_ddi_get_encoder_port(encoder);
		1181	uint32_t dpll = port;
		1182
		1183	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
		1184
		1185	ddi_dotclock_get(pipe_config);
		1186	}
		1187
5354	serge	1188	void intel_ddi_clock_get(struct intel_encoder *encoder,
6084	serge	1189	struct intel_crtc_state *pipe_config)
5354	serge	1190	{
6084	serge	1191	struct drm_device *dev = encoder->base.dev;
		1192
		1193	if (INTEL_INFO(dev)->gen <= 8)
		1194	hsw_ddi_clock_get(encoder, pipe_config);
		1195	else if (IS_SKYLAKE(dev))
		1196	skl_ddi_clock_get(encoder, pipe_config);
		1197	else if (IS_BROXTON(dev))
		1198	bxt_ddi_clock_get(encoder, pipe_config);
5354	serge	1199	}
		1200
4104	Serge	1201	static void
5354	serge	1202	hsw_ddi_calculate_wrpll(int clock /* in Hz */,
6084	serge	1203	unsigned r2_out, unsigned n2_out, unsigned *p_out)
3243	Serge	1204	{
4104	Serge	1205	uint64_t freq2k;
		1206	unsigned p, n2, r2;
6084	serge	1207	struct hsw_wrpll_rnp best = { 0, 0, 0 };
4104	Serge	1208	unsigned budget;
		1209
		1210	freq2k = clock / 100;
		1211
6084	serge	1212	budget = hsw_wrpll_get_budget_for_freq(clock);
4104	Serge	1213
		1214	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
		1215	* and directly pass the LC PLL to it. */
		1216	if (freq2k == 5400000) {
		1217	*n2_out = 2;
		1218	*p_out = 1;
		1219	*r2_out = 2;
		1220	return;
		1221	}
		1222
		1223	/*
		1224	* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
		1225	* the WR PLL.
		1226	*
		1227	* We want R so that REF_MIN <= Ref <= REF_MAX.
		1228	* Injecting R2 = 2 * R gives:
		1229	* REF_MAX * r2 > LC_FREQ * 2 and
		1230	* REF_MIN * r2 < LC_FREQ * 2
		1231	*
		1232	* Which means the desired boundaries for r2 are:
		1233	* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
		1234	*
		1235	*/
		1236	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
		1237	r2 <= LC_FREQ * 2 / REF_MIN;
		1238	r2++) {
		1239
		1240	/*
		1241	* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
		1242	*
		1243	* Once again we want VCO_MIN <= VCO <= VCO_MAX.
		1244	* Injecting R2 = 2 * R and N2 = 2 * N, we get:
		1245	* VCO_MAX * r2 > n2 * LC_FREQ and
		1246	* VCO_MIN * r2 < n2 * LC_FREQ)
		1247	*
		1248	* Which means the desired boundaries for n2 are:
		1249	* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
		1250	*/
		1251	for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
		1252	n2 <= VCO_MAX * r2 / LC_FREQ;
		1253	n2++) {
		1254
		1255	for (p = P_MIN; p <= P_MAX; p += P_INC)
6084	serge	1256	hsw_wrpll_update_rnp(freq2k, budget,
		1257	r2, n2, p, &best);
4104	Serge	1258	}
		1259	}
		1260
		1261	*n2_out = best.n2;
		1262	*p_out = best.p;
		1263	*r2_out = best.r2;
		1264	}
		1265
5354	serge	1266	static bool
		1267	hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
6084	serge	1268	struct intel_crtc_state *crtc_state,
		1269	struct intel_encoder *intel_encoder)
4104	Serge	1270	{
6084	serge	1271	int clock = crtc_state->port_clock;
		1272
5354	serge	1273	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5060	serge	1274	struct intel_shared_dpll *pll;
		1275	uint32_t val;
4104	Serge	1276	unsigned p, n2, r2;
3243	Serge	1277
5354	serge	1278	hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
4560	Serge	1279
5060	serge	1280	val = WRPLL_PLL_ENABLE \| WRPLL_PLL_LCPLL \|
4560	Serge	1281	WRPLL_DIVIDER_REFERENCE(r2) \| WRPLL_DIVIDER_FEEDBACK(n2) \|
		1282	WRPLL_DIVIDER_POST(p);
		1283
6084	serge	1284	memset(&crtc_state->dpll_hw_state, 0,
		1285	sizeof(crtc_state->dpll_hw_state));
3243	Serge	1286
6084	serge	1287	crtc_state->dpll_hw_state.wrpll = val;
		1288
		1289	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
5060	serge	1290	if (pll == NULL) {
		1291	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1292	pipe_name(intel_crtc->pipe));
3746	Serge	1293	return false;
3243	Serge	1294	}
		1295
6084	serge	1296	crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
		1297	} else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
		1298	struct drm_atomic_state *state = crtc_state->base.state;
		1299	struct intel_shared_dpll_config *spll =
		1300	&intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
		1301
		1302	if (spll->crtc_mask &&
		1303	WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
		1304	return false;
		1305
		1306	crtc_state->shared_dpll = DPLL_ID_SPLL;
		1307	spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
		1308	spll->crtc_mask \|= 1 << intel_crtc->pipe;
3243	Serge	1309	}
		1310
		1311	return true;
		1312	}
3031	serge	1313
6084	serge	1314	struct skl_wrpll_context {
		1315	uint64_t min_deviation; /* current minimal deviation */
		1316	uint64_t central_freq; /* chosen central freq */
		1317	uint64_t dco_freq; /* chosen dco freq */
		1318	unsigned int p; /* chosen divider */
		1319	};
		1320
		1321	static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
		1322	{
		1323	memset(ctx, 0, sizeof(*ctx));
		1324
		1325	ctx->min_deviation = U64_MAX;
		1326	}
		1327
		1328	/* DCO freq must be within +1%/-6% of the DCO central freq */
		1329	#define SKL_DCO_MAX_PDEVIATION 100
		1330	#define SKL_DCO_MAX_NDEVIATION 600
		1331
		1332	static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
		1333	uint64_t central_freq,
		1334	uint64_t dco_freq,
		1335	unsigned int divider)
		1336	{
		1337	uint64_t deviation;
		1338
		1339	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
		1340	central_freq);
		1341
		1342	/* positive deviation */
		1343	if (dco_freq >= central_freq) {
		1344	if (deviation < SKL_DCO_MAX_PDEVIATION &&
		1345	deviation < ctx->min_deviation) {
		1346	ctx->min_deviation = deviation;
		1347	ctx->central_freq = central_freq;
		1348	ctx->dco_freq = dco_freq;
		1349	ctx->p = divider;
		1350	}
		1351	/* negative deviation */
		1352	} else if (deviation < SKL_DCO_MAX_NDEVIATION &&
		1353	deviation < ctx->min_deviation) {
		1354	ctx->min_deviation = deviation;
		1355	ctx->central_freq = central_freq;
		1356	ctx->dco_freq = dco_freq;
		1357	ctx->p = divider;
		1358	}
		1359	}
		1360
		1361	static void skl_wrpll_get_multipliers(unsigned int p,
		1362	unsigned int p0 / out */,
		1363	unsigned int p1 / out */,
		1364	unsigned int p2 / out */)
		1365	{
		1366	/* even dividers */
		1367	if (p % 2 == 0) {
		1368	unsigned int half = p / 2;
		1369
		1370	if (half == 1 \|\| half == 2 \|\| half == 3 \|\| half == 5) {
		1371	*p0 = 2;
		1372	*p1 = 1;
		1373	*p2 = half;
		1374	} else if (half % 2 == 0) {
		1375	*p0 = 2;
		1376	*p1 = half / 2;
		1377	*p2 = 2;
		1378	} else if (half % 3 == 0) {
		1379	*p0 = 3;
		1380	*p1 = half / 3;
		1381	*p2 = 2;
		1382	} else if (half % 7 == 0) {
		1383	*p0 = 7;
		1384	*p1 = half / 7;
		1385	*p2 = 2;
		1386	}
		1387	} else if (p == 3 \|\| p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
		1388	*p0 = 3;
		1389	*p1 = 1;
		1390	*p2 = p / 3;
		1391	} else if (p == 5 \|\| p == 7) {
		1392	*p0 = p;
		1393	*p1 = 1;
		1394	*p2 = 1;
		1395	} else if (p == 15) {
		1396	*p0 = 3;
		1397	*p1 = 1;
		1398	*p2 = 5;
		1399	} else if (p == 21) {
		1400	*p0 = 7;
		1401	*p1 = 1;
		1402	*p2 = 3;
		1403	} else if (p == 35) {
		1404	*p0 = 7;
		1405	*p1 = 1;
		1406	*p2 = 5;
		1407	}
		1408	}
		1409
5354	serge	1410	struct skl_wrpll_params {
		1411	uint32_t dco_fraction;
		1412	uint32_t dco_integer;
		1413	uint32_t qdiv_ratio;
		1414	uint32_t qdiv_mode;
		1415	uint32_t kdiv;
		1416	uint32_t pdiv;
		1417	uint32_t central_freq;
		1418	};
		1419
6084	serge	1420	static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
		1421	uint64_t afe_clock,
		1422	uint64_t central_freq,
		1423	uint32_t p0, uint32_t p1, uint32_t p2)
		1424	{
		1425	uint64_t dco_freq;
		1426
		1427	switch (central_freq) {
		1428	case 9600000000ULL:
		1429	params->central_freq = 0;
		1430	break;
		1431	case 9000000000ULL:
		1432	params->central_freq = 1;
		1433	break;
		1434	case 8400000000ULL:
		1435	params->central_freq = 3;
		1436	}
		1437
		1438	switch (p0) {
		1439	case 1:
		1440	params->pdiv = 0;
		1441	break;
		1442	case 2:
		1443	params->pdiv = 1;
		1444	break;
		1445	case 3:
		1446	params->pdiv = 2;
		1447	break;
		1448	case 7:
		1449	params->pdiv = 4;
		1450	break;
		1451	default:
		1452	WARN(1, "Incorrect PDiv\n");
		1453	}
		1454
		1455	switch (p2) {
		1456	case 5:
		1457	params->kdiv = 0;
		1458	break;
		1459	case 2:
		1460	params->kdiv = 1;
		1461	break;
		1462	case 3:
		1463	params->kdiv = 2;
		1464	break;
		1465	case 1:
		1466	params->kdiv = 3;
		1467	break;
		1468	default:
		1469	WARN(1, "Incorrect KDiv\n");
		1470	}
		1471
		1472	params->qdiv_ratio = p1;
		1473	params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
		1474
		1475	dco_freq = p0 * p1 * p2 * afe_clock;
		1476
		1477	/*
		1478	* Intermediate values are in Hz.
		1479	* Divide by MHz to match bsepc
		1480	*/
		1481	params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
		1482	params->dco_fraction =
		1483	div_u64((div_u64(dco_freq, 24) -
		1484	params->dco_integer * MHz(1)) * 0x8000, MHz(1));
		1485	}
		1486
		1487	static bool
5354	serge	1488	skl_ddi_calculate_wrpll(int clock /* in Hz */,
		1489	struct skl_wrpll_params *wrpll_params)
		1490	{
		1491	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
		1492	uint64_t dco_central_freq[3] = {8400000000ULL,
		1493	9000000000ULL,
		1494	9600000000ULL};
6084	serge	1495	static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
		1496	24, 28, 30, 32, 36, 40, 42, 44,
		1497	48, 52, 54, 56, 60, 64, 66, 68,
		1498	70, 72, 76, 78, 80, 84, 88, 90,
		1499	92, 96, 98 };
		1500	static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
		1501	static const struct {
		1502	const int *list;
		1503	int n_dividers;
		1504	} dividers[] = {
		1505	{ even_dividers, ARRAY_SIZE(even_dividers) },
		1506	{ odd_dividers, ARRAY_SIZE(odd_dividers) },
		1507	};
		1508	struct skl_wrpll_context ctx;
		1509	unsigned int dco, d, i;
		1510	unsigned int p0, p1, p2;
5354	serge	1511
6084	serge	1512	skl_wrpll_context_init(&ctx);
5354	serge	1513
6084	serge	1514	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
		1515	for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
		1516	for (i = 0; i < dividers[d].n_dividers; i++) {
		1517	unsigned int p = dividers[d].list[i];
		1518	uint64_t dco_freq = p * afe_clock;
5354	serge	1519
6084	serge	1520	skl_wrpll_try_divider(&ctx,
		1521	dco_central_freq[dco],
		1522	dco_freq,
		1523	p);
		1524	/*
		1525	* Skip the remaining dividers if we're sure to
		1526	* have found the definitive divider, we can't
		1527	* improve a 0 deviation.
		1528	*/
		1529	if (ctx.min_deviation == 0)
		1530	goto skip_remaining_dividers;
5354	serge	1531	}
		1532	}
		1533
6084	serge	1534	skip_remaining_dividers:
		1535	/*
		1536	* If a solution is found with an even divider, prefer
		1537	* this one.
		1538	*/
		1539	if (d == 0 && ctx.p)
		1540	break;
		1541	}
5354	serge	1542
6084	serge	1543	if (!ctx.p) {
		1544	DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
		1545	return false;
5354	serge	1546	}
		1547
6084	serge	1548	/*
		1549	* gcc incorrectly analyses that these can be used without being
		1550	* initialized. To be fair, it's hard to guess.
		1551	*/
		1552	p0 = p1 = p2 = 0;
		1553	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
		1554	skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
		1555	p0, p1, p2);
5354	serge	1556
6084	serge	1557	return true;
5354	serge	1558	}
		1559
		1560	static bool
		1561	skl_ddi_pll_select(struct intel_crtc *intel_crtc,
6084	serge	1562	struct intel_crtc_state *crtc_state,
		1563	struct intel_encoder *intel_encoder)
5354	serge	1564	{
		1565	struct intel_shared_dpll *pll;
		1566	uint32_t ctrl1, cfgcr1, cfgcr2;
6084	serge	1567	int clock = crtc_state->port_clock;
5354	serge	1568
		1569	/*
		1570	* See comment in intel_dpll_hw_state to understand why we always use 0
		1571	* as the DPLL id in this function.
		1572	*/
		1573
		1574	ctrl1 = DPLL_CTRL1_OVERRIDE(0);
		1575
		1576	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		1577	struct skl_wrpll_params wrpll_params = { 0, };
		1578
		1579	ctrl1 \|= DPLL_CTRL1_HDMI_MODE(0);
		1580
6084	serge	1581	if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
		1582	return false;
5354	serge	1583
		1584	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE \|
		1585	DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) \|
		1586	wrpll_params.dco_integer;
		1587
		1588	cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) \|
		1589	DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) \|
		1590	DPLL_CFGCR2_KDIV(wrpll_params.kdiv) \|
		1591	DPLL_CFGCR2_PDIV(wrpll_params.pdiv) \|
		1592	wrpll_params.central_freq;
6320	serge	1593	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1594	intel_encoder->type == INTEL_OUTPUT_DP_MST) {
6084	serge	1595	switch (crtc_state->port_clock / 2) {
		1596	case 81000:
		1597	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
5354	serge	1598	break;
6084	serge	1599	case 135000:
		1600	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
5354	serge	1601	break;
6084	serge	1602	case 270000:
		1603	ctrl1 \|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
5354	serge	1604	break;
		1605	}
		1606
		1607	cfgcr1 = cfgcr2 = 0;
		1608	} else /* eDP */
		1609	return true;
		1610
6084	serge	1611	memset(&crtc_state->dpll_hw_state, 0,
		1612	sizeof(crtc_state->dpll_hw_state));
5354	serge	1613
6084	serge	1614	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
		1615	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
		1616	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
		1617
		1618	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
5354	serge	1619	if (pll == NULL) {
		1620	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1621	pipe_name(intel_crtc->pipe));
		1622	return false;
		1623	}
		1624
		1625	/* shared DPLL id 0 is DPLL 1 */
6084	serge	1626	crtc_state->ddi_pll_sel = pll->id + 1;
5354	serge	1627
		1628	return true;
		1629	}
		1630
6084	serge	1631	/* bxt clock parameters */
		1632	struct bxt_clk_div {
		1633	int clock;
		1634	uint32_t p1;
		1635	uint32_t p2;
		1636	uint32_t m2_int;
		1637	uint32_t m2_frac;
		1638	bool m2_frac_en;
		1639	uint32_t n;
		1640	};
		1641
		1642	/* pre-calculated values for DP linkrates */
		1643	static const struct bxt_clk_div bxt_dp_clk_val[] = {
		1644	{162000, 4, 2, 32, 1677722, 1, 1},
		1645	{270000, 4, 1, 27, 0, 0, 1},
		1646	{540000, 2, 1, 27, 0, 0, 1},
		1647	{216000, 3, 2, 32, 1677722, 1, 1},
		1648	{243000, 4, 1, 24, 1258291, 1, 1},
		1649	{324000, 4, 1, 32, 1677722, 1, 1},
		1650	{432000, 3, 1, 32, 1677722, 1, 1}
		1651	};
		1652
		1653	static bool
		1654	bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
		1655	struct intel_crtc_state *crtc_state,
		1656	struct intel_encoder *intel_encoder)
		1657	{
		1658	struct intel_shared_dpll *pll;
		1659	struct bxt_clk_div clk_div = {0};
		1660	int vco = 0;
		1661	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
		1662	uint32_t lanestagger;
		1663	int clock = crtc_state->port_clock;
		1664
		1665	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		1666	intel_clock_t best_clock;
		1667
		1668	/* Calculate HDMI div */
		1669	/*
		1670	* FIXME: tie the following calculation into
		1671	* i9xx_crtc_compute_clock
		1672	*/
		1673	if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
		1674	DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
		1675	clock, pipe_name(intel_crtc->pipe));
		1676	return false;
		1677	}
		1678
		1679	clk_div.p1 = best_clock.p1;
		1680	clk_div.p2 = best_clock.p2;
		1681	WARN_ON(best_clock.m1 != 2);
		1682	clk_div.n = best_clock.n;
		1683	clk_div.m2_int = best_clock.m2 >> 22;
		1684	clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
		1685	clk_div.m2_frac_en = clk_div.m2_frac != 0;
		1686
		1687	vco = best_clock.vco;
		1688	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1689	intel_encoder->type == INTEL_OUTPUT_EDP) {
		1690	int i;
		1691
		1692	clk_div = bxt_dp_clk_val[0];
		1693	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
		1694	if (bxt_dp_clk_val[i].clock == clock) {
		1695	clk_div = bxt_dp_clk_val[i];
		1696	break;
		1697	}
		1698	}
		1699	vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
		1700	}
		1701
		1702	if (vco >= 6200000 && vco <= 6700000) {
		1703	prop_coef = 4;
		1704	int_coef = 9;
		1705	gain_ctl = 3;
		1706	targ_cnt = 8;
		1707	} else if ((vco > 5400000 && vco < 6200000) \|\|
		1708	(vco >= 4800000 && vco < 5400000)) {
		1709	prop_coef = 5;
		1710	int_coef = 11;
		1711	gain_ctl = 3;
		1712	targ_cnt = 9;
		1713	} else if (vco == 5400000) {
		1714	prop_coef = 3;
		1715	int_coef = 8;
		1716	gain_ctl = 1;
		1717	targ_cnt = 9;
		1718	} else {
		1719	DRM_ERROR("Invalid VCO\n");
		1720	return false;
		1721	}
		1722
		1723	memset(&crtc_state->dpll_hw_state, 0,
		1724	sizeof(crtc_state->dpll_hw_state));
		1725
		1726	if (clock > 270000)
		1727	lanestagger = 0x18;
		1728	else if (clock > 135000)
		1729	lanestagger = 0x0d;
		1730	else if (clock > 67000)
		1731	lanestagger = 0x07;
		1732	else if (clock > 33000)
		1733	lanestagger = 0x04;
		1734	else
		1735	lanestagger = 0x02;
		1736
		1737	crtc_state->dpll_hw_state.ebb0 =
		1738	PORT_PLL_P1(clk_div.p1) \| PORT_PLL_P2(clk_div.p2);
		1739	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
		1740	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
		1741	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
		1742
		1743	if (clk_div.m2_frac_en)
		1744	crtc_state->dpll_hw_state.pll3 =
		1745	PORT_PLL_M2_FRAC_ENABLE;
		1746
		1747	crtc_state->dpll_hw_state.pll6 =
		1748	prop_coef \| PORT_PLL_INT_COEFF(int_coef);
		1749	crtc_state->dpll_hw_state.pll6 \|=
		1750	PORT_PLL_GAIN_CTL(gain_ctl);
		1751
		1752	crtc_state->dpll_hw_state.pll8 = targ_cnt;
		1753
		1754	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
		1755
		1756	crtc_state->dpll_hw_state.pll10 =
		1757	PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
		1758	\| PORT_PLL_DCO_AMP_OVR_EN_H;
		1759
		1760	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
		1761
		1762	crtc_state->dpll_hw_state.pcsdw12 =
		1763	LANESTAGGER_STRAP_OVRD \| lanestagger;
		1764
		1765	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
		1766	if (pll == NULL) {
		1767	DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
		1768	pipe_name(intel_crtc->pipe));
		1769	return false;
		1770	}
		1771
		1772	/* shared DPLL id 0 is DPLL A */
		1773	crtc_state->ddi_pll_sel = pll->id;
		1774
		1775	return true;
		1776	}
		1777
5354	serge	1778	/*
		1779	* Tries to find a shared PLL for the CRTC and store it in
		1780	* intel_crtc->ddi_pll_sel.
		1781	*
		1782	* For private DPLLs, compute_config() should do the selection for us. This
		1783	* function should be folded into compute_config() eventually.
		1784	*/
6084	serge	1785	bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
		1786	struct intel_crtc_state *crtc_state)
5354	serge	1787	{
		1788	struct drm_device *dev = intel_crtc->base.dev;
		1789	struct intel_encoder *intel_encoder =
6084	serge	1790	intel_ddi_get_crtc_new_encoder(crtc_state);
5354	serge	1791
		1792	if (IS_SKYLAKE(dev))
6084	serge	1793	return skl_ddi_pll_select(intel_crtc, crtc_state,
		1794	intel_encoder);
		1795	else if (IS_BROXTON(dev))
		1796	return bxt_ddi_pll_select(intel_crtc, crtc_state,
		1797	intel_encoder);
5354	serge	1798	else
6084	serge	1799	return hsw_ddi_pll_select(intel_crtc, crtc_state,
		1800	intel_encoder);
5354	serge	1801	}
		1802
3243	Serge	1803	void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
		1804	{
		1805	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		1806	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1807	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6084	serge	1808	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	1809	int type = intel_encoder->type;
		1810	uint32_t temp;
		1811
5060	serge	1812	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP \|\| type == INTEL_OUTPUT_DP_MST) {
3243	Serge	1813	temp = TRANS_MSA_SYNC_CLK;
6084	serge	1814	switch (intel_crtc->config->pipe_bpp) {
		1815	case 18:
3243	Serge	1816	temp \|= TRANS_MSA_6_BPC;
6084	serge	1817	break;
		1818	case 24:
3243	Serge	1819	temp \|= TRANS_MSA_8_BPC;
6084	serge	1820	break;
		1821	case 30:
3243	Serge	1822	temp \|= TRANS_MSA_10_BPC;
6084	serge	1823	break;
		1824	case 36:
3243	Serge	1825	temp \|= TRANS_MSA_12_BPC;
6084	serge	1826	break;
		1827	default:
3746	Serge	1828	BUG();
6084	serge	1829	}
3243	Serge	1830	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
		1831	}
		1832	}
3031	serge	1833
5060	serge	1834	void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
		1835	{
		1836	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1837	struct drm_device *dev = crtc->dev;
		1838	struct drm_i915_private *dev_priv = dev->dev_private;
6084	serge	1839	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5060	serge	1840	uint32_t temp;
		1841	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1842	if (state == true)
		1843	temp \|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
		1844	else
		1845	temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
		1846	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
		1847	}
		1848
3746	Serge	1849	void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
3243	Serge	1850	{
		1851	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1852	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		1853	struct drm_encoder *encoder = &intel_encoder->base;
4560	Serge	1854	struct drm_device *dev = crtc->dev;
		1855	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	1856	enum pipe pipe = intel_crtc->pipe;
6084	serge	1857	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	1858	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1859	int type = intel_encoder->type;
		1860	uint32_t temp;
3031	serge	1861
3243	Serge	1862	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
		1863	temp = TRANS_DDI_FUNC_ENABLE;
		1864	temp \|= TRANS_DDI_SELECT_PORT(port);
		1865
6084	serge	1866	switch (intel_crtc->config->pipe_bpp) {
3031	serge	1867	case 18:
3243	Serge	1868	temp \|= TRANS_DDI_BPC_6;
3031	serge	1869	break;
		1870	case 24:
3243	Serge	1871	temp \|= TRANS_DDI_BPC_8;
3031	serge	1872	break;
		1873	case 30:
3243	Serge	1874	temp \|= TRANS_DDI_BPC_10;
3031	serge	1875	break;
		1876	case 36:
3243	Serge	1877	temp \|= TRANS_DDI_BPC_12;
3031	serge	1878	break;
		1879	default:
3746	Serge	1880	BUG();
3031	serge	1881	}
		1882
6084	serge	1883	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
3243	Serge	1884	temp \|= TRANS_DDI_PVSYNC;
6084	serge	1885	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
3243	Serge	1886	temp \|= TRANS_DDI_PHSYNC;
		1887
		1888	if (cpu_transcoder == TRANSCODER_EDP) {
		1889	switch (pipe) {
		1890	case PIPE_A:
4560	Serge	1891	/* On Haswell, can only use the always-on power well for
		1892	* eDP when not using the panel fitter, and when not
		1893	* using motion blur mitigation (which we don't
		1894	* support). */
5060	serge	1895	if (IS_HASWELL(dev) &&
6084	serge	1896	(intel_crtc->config->pch_pfit.enabled \|\|
		1897	intel_crtc->config->pch_pfit.force_thru))
		1898	temp \|= TRANS_DDI_EDP_INPUT_A_ONOFF;
3480	Serge	1899	else
		1900	temp \|= TRANS_DDI_EDP_INPUT_A_ON;
3243	Serge	1901	break;
		1902	case PIPE_B:
		1903	temp \|= TRANS_DDI_EDP_INPUT_B_ONOFF;
		1904	break;
		1905	case PIPE_C:
		1906	temp \|= TRANS_DDI_EDP_INPUT_C_ONOFF;
		1907	break;
		1908	default:
		1909	BUG();
		1910	break;
		1911	}
		1912	}
		1913
		1914	if (type == INTEL_OUTPUT_HDMI) {
6084	serge	1915	if (intel_crtc->config->has_hdmi_sink)
3243	Serge	1916	temp \|= TRANS_DDI_MODE_SELECT_HDMI;
6084	serge	1917	else
3243	Serge	1918	temp \|= TRANS_DDI_MODE_SELECT_DVI;
3031	serge	1919
3243	Serge	1920	} else if (type == INTEL_OUTPUT_ANALOG) {
		1921	temp \|= TRANS_DDI_MODE_SELECT_FDI;
6084	serge	1922	temp \|= (intel_crtc->config->fdi_lanes - 1) << 1;
3031	serge	1923
3243	Serge	1924	} else if (type == INTEL_OUTPUT_DISPLAYPORT \|\|
		1925	type == INTEL_OUTPUT_EDP) {
		1926	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	1927
5060	serge	1928	if (intel_dp->is_mst) {
		1929	temp \|= TRANS_DDI_MODE_SELECT_DP_MST;
		1930	} else
		1931	temp \|= TRANS_DDI_MODE_SELECT_DP_SST;
		1932
6084	serge	1933	temp \|= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
5060	serge	1934	} else if (type == INTEL_OUTPUT_DP_MST) {
		1935	struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
		1936
		1937	if (intel_dp->is_mst) {
		1938	temp \|= TRANS_DDI_MODE_SELECT_DP_MST;
		1939	} else
6084	serge	1940	temp \|= TRANS_DDI_MODE_SELECT_DP_SST;
3243	Serge	1941
6084	serge	1942	temp \|= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
3243	Serge	1943	} else {
4104	Serge	1944	WARN(1, "Invalid encoder type %d for pipe %c\n",
		1945	intel_encoder->type, pipe_name(pipe));
3243	Serge	1946	}
		1947
		1948	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
3031	serge	1949	}
		1950
3243	Serge	1951	void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
		1952	enum transcoder cpu_transcoder)
		1953	{
		1954	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
		1955	uint32_t val = I915_READ(reg);
		1956
5060	serge	1957	val &= ~(TRANS_DDI_FUNC_ENABLE \| TRANS_DDI_PORT_MASK \| TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3243	Serge	1958	val \|= TRANS_DDI_PORT_NONE;
		1959	I915_WRITE(reg, val);
		1960	}
		1961
		1962	bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
		1963	{
		1964	struct drm_device *dev = intel_connector->base.dev;
		1965	struct drm_i915_private *dev_priv = dev->dev_private;
		1966	struct intel_encoder *intel_encoder = intel_connector->encoder;
		1967	int type = intel_connector->base.connector_type;
		1968	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		1969	enum pipe pipe = 0;
		1970	enum transcoder cpu_transcoder;
5060	serge	1971	enum intel_display_power_domain power_domain;
3243	Serge	1972	uint32_t tmp;
		1973
5060	serge	1974	power_domain = intel_display_port_power_domain(intel_encoder);
5354	serge	1975	if (!intel_display_power_is_enabled(dev_priv, power_domain))
5060	serge	1976	return false;
		1977
3243	Serge	1978	if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
		1979	return false;
		1980
		1981	if (port == PORT_A)
		1982	cpu_transcoder = TRANSCODER_EDP;
		1983	else
3480	Serge	1984	cpu_transcoder = (enum transcoder) pipe;
3243	Serge	1985
		1986	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		1987
		1988	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
		1989	case TRANS_DDI_MODE_SELECT_HDMI:
		1990	case TRANS_DDI_MODE_SELECT_DVI:
		1991	return (type == DRM_MODE_CONNECTOR_HDMIA);
		1992
		1993	case TRANS_DDI_MODE_SELECT_DP_SST:
		1994	if (type == DRM_MODE_CONNECTOR_eDP)
		1995	return true;
5060	serge	1996	return (type == DRM_MODE_CONNECTOR_DisplayPort);
3243	Serge	1997	case TRANS_DDI_MODE_SELECT_DP_MST:
5060	serge	1998	/* if the transcoder is in MST state then
		1999	* connector isn't connected */
		2000	return false;
3243	Serge	2001
		2002	case TRANS_DDI_MODE_SELECT_FDI:
		2003	return (type == DRM_MODE_CONNECTOR_VGA);
		2004
		2005	default:
		2006	return false;
		2007	}
		2008	}
		2009
3031	serge	2010	bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
		2011	enum pipe *pipe)
		2012	{
		2013	struct drm_device *dev = encoder->base.dev;
		2014	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2015	enum port port = intel_ddi_get_encoder_port(encoder);
5060	serge	2016	enum intel_display_power_domain power_domain;
3031	serge	2017	u32 tmp;
		2018	int i;
		2019
5060	serge	2020	power_domain = intel_display_port_power_domain(encoder);
5354	serge	2021	if (!intel_display_power_is_enabled(dev_priv, power_domain))
5060	serge	2022	return false;
		2023
3243	Serge	2024	tmp = I915_READ(DDI_BUF_CTL(port));
3031	serge	2025
		2026	if (!(tmp & DDI_BUF_CTL_ENABLE))
		2027	return false;
		2028
3243	Serge	2029	if (port == PORT_A) {
		2030	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
3031	serge	2031
3243	Serge	2032	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		2033	case TRANS_DDI_EDP_INPUT_A_ON:
		2034	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		2035	*pipe = PIPE_A;
		2036	break;
		2037	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		2038	*pipe = PIPE_B;
		2039	break;
		2040	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		2041	*pipe = PIPE_C;
		2042	break;
		2043	}
		2044
		2045	return true;
		2046	} else {
		2047	for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
		2048	tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
		2049
		2050	if ((tmp & TRANS_DDI_PORT_MASK)
		2051	== TRANS_DDI_SELECT_PORT(port)) {
5060	serge	2052	if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
		2053	return false;
		2054
6084	serge	2055	*pipe = i;
		2056	return true;
		2057	}
3031	serge	2058	}
		2059	}
		2060
4104	Serge	2061	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
3031	serge	2062
3746	Serge	2063	return false;
3031	serge	2064	}
		2065
3243	Serge	2066	void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
3031	serge	2067	{
3243	Serge	2068	struct drm_crtc *crtc = &intel_crtc->base;
6084	serge	2069	struct drm_device *dev = crtc->dev;
		2070	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2071	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		2072	enum port port = intel_ddi_get_encoder_port(intel_encoder);
6084	serge	2073	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	2074
		2075	if (cpu_transcoder != TRANSCODER_EDP)
		2076	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2077	TRANS_CLK_SEL_PORT(port));
		2078	}
		2079
		2080	void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
		2081	{
		2082	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6084	serge	2083	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3243	Serge	2084
		2085	if (cpu_transcoder != TRANSCODER_EDP)
		2086	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2087	TRANS_CLK_SEL_DISABLED);
		2088	}
		2089
6084	serge	2090	static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
		2091	enum port port, int type)
		2092	{
		2093	struct drm_i915_private *dev_priv = dev->dev_private;
		2094	const struct ddi_buf_trans *ddi_translations;
		2095	uint8_t iboost;
		2096	uint8_t dp_iboost, hdmi_iboost;
		2097	int n_entries;
		2098	u32 reg;
		2099
		2100	/* VBT may override standard boost values */
		2101	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
		2102	hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
		2103
		2104	if (type == INTEL_OUTPUT_DISPLAYPORT) {
		2105	if (dp_iboost) {
		2106	iboost = dp_iboost;
		2107	} else {
		2108	ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
		2109	iboost = ddi_translations[port].i_boost;
		2110	}
		2111	} else if (type == INTEL_OUTPUT_EDP) {
		2112	if (dp_iboost) {
		2113	iboost = dp_iboost;
		2114	} else {
		2115	ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
		2116	iboost = ddi_translations[port].i_boost;
		2117	}
		2118	} else if (type == INTEL_OUTPUT_HDMI) {
		2119	if (hdmi_iboost) {
		2120	iboost = hdmi_iboost;
		2121	} else {
		2122	ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
		2123	iboost = ddi_translations[port].i_boost;
		2124	}
		2125	} else {
		2126	return;
		2127	}
		2128
		2129	/* Make sure that the requested I_boost is valid */
		2130	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
		2131	DRM_ERROR("Invalid I_boost value %u\n", iboost);
		2132	return;
		2133	}
		2134
		2135	reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
		2136	reg &= ~BALANCE_LEG_MASK(port);
		2137	reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
		2138
		2139	if (iboost)
		2140	reg \|= iboost << BALANCE_LEG_SHIFT(port);
		2141	else
		2142	reg \|= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
		2143
		2144	I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
		2145	}
		2146
		2147	static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
		2148	enum port port, int type)
		2149	{
		2150	struct drm_i915_private *dev_priv = dev->dev_private;
		2151	const struct bxt_ddi_buf_trans *ddi_translations;
		2152	u32 n_entries, i;
		2153	uint32_t val;
		2154
		2155	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
		2156	n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
		2157	ddi_translations = bxt_ddi_translations_edp;
		2158	} else if (type == INTEL_OUTPUT_DISPLAYPORT
		2159	\|\| type == INTEL_OUTPUT_EDP) {
		2160	n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
		2161	ddi_translations = bxt_ddi_translations_dp;
		2162	} else if (type == INTEL_OUTPUT_HDMI) {
		2163	n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
		2164	ddi_translations = bxt_ddi_translations_hdmi;
		2165	} else {
		2166	DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
		2167	type);
		2168	return;
		2169	}
		2170
		2171	/* Check if default value has to be used */
		2172	if (level >= n_entries \|\|
		2173	(type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
		2174	for (i = 0; i < n_entries; i++) {
		2175	if (ddi_translations[i].default_index) {
		2176	level = i;
		2177	break;
		2178	}
		2179	}
		2180	}
		2181
		2182	/*
		2183	* While we write to the group register to program all lanes at once we
		2184	* can read only lane registers and we pick lanes 0/1 for that.
		2185	*/
		2186	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
		2187	val &= ~(TX2_SWING_CALC_INIT \| TX1_SWING_CALC_INIT);
		2188	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
		2189
		2190	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
		2191	val &= ~(MARGIN_000 \| UNIQ_TRANS_SCALE);
		2192	val \|= ddi_translations[level].margin << MARGIN_000_SHIFT \|
		2193	ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
		2194	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
		2195
		2196	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
		2197	val &= ~SCALE_DCOMP_METHOD;
		2198	if (ddi_translations[level].enable)
		2199	val \|= SCALE_DCOMP_METHOD;
		2200
		2201	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
		2202	DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
		2203
		2204	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
		2205
		2206	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
		2207	val &= ~DE_EMPHASIS;
		2208	val \|= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
		2209	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
		2210
		2211	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
		2212	val \|= TX2_SWING_CALC_INIT \| TX1_SWING_CALC_INIT;
		2213	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
		2214	}
		2215
		2216	static uint32_t translate_signal_level(int signal_levels)
		2217	{
		2218	uint32_t level;
		2219
		2220	switch (signal_levels) {
		2221	default:
		2222	DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
		2223	signal_levels);
		2224	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2225	level = 0;
		2226	break;
		2227	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2228	level = 1;
		2229	break;
		2230	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_2:
		2231	level = 2;
		2232	break;
		2233	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \| DP_TRAIN_PRE_EMPH_LEVEL_3:
		2234	level = 3;
		2235	break;
		2236
		2237	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2238	level = 4;
		2239	break;
		2240	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2241	level = 5;
		2242	break;
		2243	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 \| DP_TRAIN_PRE_EMPH_LEVEL_2:
		2244	level = 6;
		2245	break;
		2246
		2247	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2248	level = 7;
		2249	break;
		2250	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 \| DP_TRAIN_PRE_EMPH_LEVEL_1:
		2251	level = 8;
		2252	break;
		2253
		2254	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 \| DP_TRAIN_PRE_EMPH_LEVEL_0:
		2255	level = 9;
		2256	break;
		2257	}
		2258
		2259	return level;
		2260	}
		2261
		2262	uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
		2263	{
		2264	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
		2265	struct drm_device *dev = dport->base.base.dev;
		2266	struct intel_encoder *encoder = &dport->base;
		2267	uint8_t train_set = intel_dp->train_set[0];
		2268	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK \|
		2269	DP_TRAIN_PRE_EMPHASIS_MASK);
		2270	enum port port = dport->port;
		2271	uint32_t level;
		2272
		2273	level = translate_signal_level(signal_levels);
		2274
		2275	if (IS_SKYLAKE(dev))
		2276	skl_ddi_set_iboost(dev, level, port, encoder->type);
		2277	else if (IS_BROXTON(dev))
		2278	bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
		2279
		2280	return DDI_BUF_TRANS_SELECT(level);
		2281	}
		2282
3243	Serge	2283	static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
		2284	{
		2285	struct drm_encoder *encoder = &intel_encoder->base;
5354	serge	2286	struct drm_device *dev = encoder->dev;
		2287	struct drm_i915_private *dev_priv = dev->dev_private;
5060	serge	2288	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
3243	Serge	2289	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2290	int type = intel_encoder->type;
6084	serge	2291	int hdmi_level;
3243	Serge	2292
		2293	if (type == INTEL_OUTPUT_EDP) {
		2294	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5060	serge	2295	intel_edp_panel_on(intel_dp);
3243	Serge	2296	}
		2297
5354	serge	2298	if (IS_SKYLAKE(dev)) {
6084	serge	2299	uint32_t dpll = crtc->config->ddi_pll_sel;
5354	serge	2300	uint32_t val;
		2301
		2302	/*
		2303	* DPLL0 is used for eDP and is the only "private" DPLL (as
		2304	* opposed to shared) on SKL
		2305	*/
6084	serge	2306	if (type == INTEL_OUTPUT_EDP) {
5354	serge	2307	WARN_ON(dpll != SKL_DPLL0);
		2308
		2309	val = I915_READ(DPLL_CTRL1);
		2310
		2311	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) \|
		2312	DPLL_CTRL1_SSC(dpll) \|
6084	serge	2313	DPLL_CTRL1_LINK_RATE_MASK(dpll));
		2314	val \|= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5354	serge	2315
		2316	I915_WRITE(DPLL_CTRL1, val);
		2317	POSTING_READ(DPLL_CTRL1);
6084	serge	2318	}
5354	serge	2319
		2320	/* DDI -> PLL mapping */
		2321	val = I915_READ(DPLL_CTRL2);
		2322
		2323	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) \|
		2324	DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
		2325	val \|= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) \|
		2326	DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
		2327
		2328	I915_WRITE(DPLL_CTRL2, val);
		2329
6084	serge	2330	} else if (INTEL_INFO(dev)->gen < 9) {
		2331	WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
		2332	I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
5354	serge	2333	}
3243	Serge	2334
		2335	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
		2336	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2337
6084	serge	2338	intel_dp_set_link_params(intel_dp, crtc->config);
		2339
5060	serge	2340	intel_ddi_init_dp_buf_reg(intel_encoder);
		2341
3243	Serge	2342	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
		2343	intel_dp_start_link_train(intel_dp);
5354	serge	2344	if (port != PORT_A \|\| INTEL_INFO(dev)->gen >= 9)
3746	Serge	2345	intel_dp_stop_link_train(intel_dp);
5060	serge	2346	} else if (type == INTEL_OUTPUT_HDMI) {
		2347	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
		2348
6084	serge	2349	if (IS_BROXTON(dev)) {
		2350	hdmi_level = dev_priv->vbt.
		2351	ddi_port_info[port].hdmi_level_shift;
		2352	bxt_ddi_vswing_sequence(dev, hdmi_level, port,
		2353	INTEL_OUTPUT_HDMI);
		2354	}
5060	serge	2355	intel_hdmi->set_infoframes(encoder,
6084	serge	2356	crtc->config->has_hdmi_sink,
		2357	&crtc->config->base.adjusted_mode);
3243	Serge	2358	}
		2359	}
		2360
		2361	static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
		2362	{
		2363	struct drm_encoder *encoder = &intel_encoder->base;
5354	serge	2364	struct drm_device *dev = encoder->dev;
		2365	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2366	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2367	int type = intel_encoder->type;
		2368	uint32_t val;
		2369	bool wait = false;
		2370
		2371	val = I915_READ(DDI_BUF_CTL(port));
		2372	if (val & DDI_BUF_CTL_ENABLE) {
		2373	val &= ~DDI_BUF_CTL_ENABLE;
		2374	I915_WRITE(DDI_BUF_CTL(port), val);
		2375	wait = true;
		2376	}
		2377
		2378	val = I915_READ(DP_TP_CTL(port));
		2379	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		2380	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		2381	I915_WRITE(DP_TP_CTL(port), val);
		2382
		2383	if (wait)
		2384	intel_wait_ddi_buf_idle(dev_priv, port);
		2385
4560	Serge	2386	if (type == INTEL_OUTPUT_DISPLAYPORT \|\| type == INTEL_OUTPUT_EDP) {
3243	Serge	2387	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4560	Serge	2388	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
5060	serge	2389	intel_edp_panel_vdd_on(intel_dp);
		2390	intel_edp_panel_off(intel_dp);
3243	Serge	2391	}
		2392
5354	serge	2393	if (IS_SKYLAKE(dev))
		2394	I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) \|
		2395	DPLL_CTRL2_DDI_CLK_OFF(port)));
6084	serge	2396	else if (INTEL_INFO(dev)->gen < 9)
		2397	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3243	Serge	2398	}
		2399
		2400	static void intel_enable_ddi(struct intel_encoder *intel_encoder)
		2401	{
		2402	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	2403	struct drm_crtc *crtc = encoder->crtc;
		2404	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	2405	struct drm_device *dev = encoder->dev;
3031	serge	2406	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2407	enum port port = intel_ddi_get_encoder_port(intel_encoder);
		2408	int type = intel_encoder->type;
3031	serge	2409
3243	Serge	2410	if (type == INTEL_OUTPUT_HDMI) {
3480	Serge	2411	struct intel_digital_port *intel_dig_port =
		2412	enc_to_dig_port(encoder);
		2413
3243	Serge	2414	/* In HDMI/DVI mode, the port width, and swing/emphasis values
		2415	* are ignored so nothing special needs to be done besides
		2416	* enabling the port.
		2417	*/
3480	Serge	2418	I915_WRITE(DDI_BUF_CTL(port),
4104	Serge	2419	intel_dig_port->saved_port_bits \|
		2420	DDI_BUF_CTL_ENABLE);
3243	Serge	2421	} else if (type == INTEL_OUTPUT_EDP) {
		2422	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3031	serge	2423
5354	serge	2424	if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3746	Serge	2425	intel_dp_stop_link_train(intel_dp);
		2426
5060	serge	2427	intel_edp_backlight_on(intel_dp);
5354	serge	2428	intel_psr_enable(intel_dp);
6084	serge	2429	intel_edp_drrs_enable(intel_dp);
3243	Serge	2430	}
3480	Serge	2431
6084	serge	2432	if (intel_crtc->config->has_audio) {
5060	serge	2433	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5354	serge	2434	intel_audio_codec_enable(intel_encoder);
3480	Serge	2435	}
3031	serge	2436	}
3243	Serge	2437
		2438	static void intel_disable_ddi(struct intel_encoder *intel_encoder)
		2439	{
		2440	struct drm_encoder *encoder = &intel_encoder->base;
3480	Serge	2441	struct drm_crtc *crtc = encoder->crtc;
		2442	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243	Serge	2443	int type = intel_encoder->type;
3480	Serge	2444	struct drm_device *dev = encoder->dev;
		2445	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	2446
6084	serge	2447	if (intel_crtc->config->has_audio) {
5354	serge	2448	intel_audio_codec_disable(intel_encoder);
5060	serge	2449	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
4104	Serge	2450	}
3746	Serge	2451
3243	Serge	2452	if (type == INTEL_OUTPUT_EDP) {
		2453	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
		2454
6084	serge	2455	intel_edp_drrs_disable(intel_dp);
5354	serge	2456	intel_psr_disable(intel_dp);
5060	serge	2457	intel_edp_backlight_off(intel_dp);
3243	Serge	2458	}
		2459	}
		2460
6084	serge	2461	static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
		2462	struct intel_shared_dpll *pll)
3243	Serge	2463	{
6084	serge	2464	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
		2465	POSTING_READ(WRPLL_CTL(pll->id));
		2466	udelay(20);
5354	serge	2467	}
		2468
6084	serge	2469	static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
		2470	struct intel_shared_dpll *pll)
5354	serge	2471	{
6084	serge	2472	I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
		2473	POSTING_READ(SPLL_CTL);
		2474	udelay(20);
3243	Serge	2475	}
		2476
6084	serge	2477	static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
		2478	struct intel_shared_dpll *pll)
5354	serge	2479	{
6084	serge	2480	uint32_t val;
5354	serge	2481
6084	serge	2482	val = I915_READ(WRPLL_CTL(pll->id));
		2483	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
		2484	POSTING_READ(WRPLL_CTL(pll->id));
5354	serge	2485	}
		2486
6084	serge	2487	static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
		2488	struct intel_shared_dpll *pll)
5354	serge	2489	{
6084	serge	2490	uint32_t val;
5354	serge	2491
6084	serge	2492	val = I915_READ(SPLL_CTL);
		2493	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
		2494	POSTING_READ(SPLL_CTL);
5354	serge	2495	}
		2496
6084	serge	2497	static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
		2498	struct intel_shared_dpll *pll,
		2499	struct intel_dpll_hw_state *hw_state)
5060	serge	2500	{
		2501	uint32_t val;
		2502
6084	serge	2503	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
		2504	return false;
		2505
5060	serge	2506	val = I915_READ(WRPLL_CTL(pll->id));
6084	serge	2507	hw_state->wrpll = val;
		2508
		2509	return val & WRPLL_PLL_ENABLE;
5060	serge	2510	}
		2511
6084	serge	2512	static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
		2513	struct intel_shared_dpll *pll,
		2514	struct intel_dpll_hw_state *hw_state)
5060	serge	2515	{
		2516	uint32_t val;
		2517
5354	serge	2518	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
5060	serge	2519	return false;
		2520
6084	serge	2521	val = I915_READ(SPLL_CTL);
		2522	hw_state->spll = val;
5060	serge	2523
6084	serge	2524	return val & SPLL_PLL_ENABLE;
5060	serge	2525	}
		2526
6084	serge	2527
5060	serge	2528	static const char * const hsw_ddi_pll_names[] = {
		2529	"WRPLL 1",
		2530	"WRPLL 2",
6084	serge	2531	"SPLL"
5060	serge	2532	};
		2533
5354	serge	2534	static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
3243	Serge	2535	{
5060	serge	2536	int i;
3243	Serge	2537
6084	serge	2538	dev_priv->num_shared_dpll = 3;
5060	serge	2539
6084	serge	2540	for (i = 0; i < 2; i++) {
5060	serge	2541	dev_priv->shared_dplls[i].id = i;
		2542	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
6084	serge	2543	dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
		2544	dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
5060	serge	2545	dev_priv->shared_dplls[i].get_hw_state =
6084	serge	2546	hsw_ddi_wrpll_get_hw_state;
5060	serge	2547	}
6084	serge	2548
		2549	/* SPLL is special, but needs to be initialized anyway.. */
		2550	dev_priv->shared_dplls[i].id = i;
		2551	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
		2552	dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
		2553	dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
		2554	dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
		2555
5354	serge	2556	}
5060	serge	2557
5354	serge	2558	static const char * const skl_ddi_pll_names[] = {
		2559	"DPLL 1",
		2560	"DPLL 2",
		2561	"DPLL 3",
		2562	};
3243	Serge	2563
5354	serge	2564	struct skl_dpll_regs {
		2565	u32 ctl, cfgcr1, cfgcr2;
		2566	};
		2567
		2568	/* this array is indexed by the shared pll id */
		2569	static const struct skl_dpll_regs skl_dpll_regs[3] = {
		2570	{
		2571	/* DPLL 1 */
		2572	.ctl = LCPLL2_CTL,
6084	serge	2573	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
		2574	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
5354	serge	2575	},
		2576	{
		2577	/* DPLL 2 */
		2578	.ctl = WRPLL_CTL1,
6084	serge	2579	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
		2580	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
5354	serge	2581	},
		2582	{
		2583	/* DPLL 3 */
		2584	.ctl = WRPLL_CTL2,
6084	serge	2585	.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
		2586	.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
5354	serge	2587	},
		2588	};
		2589
		2590	static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
		2591	struct intel_shared_dpll *pll)
		2592	{
		2593	uint32_t val;
		2594	unsigned int dpll;
		2595	const struct skl_dpll_regs *regs = skl_dpll_regs;
		2596
		2597	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
		2598	dpll = pll->id + 1;
		2599
		2600	val = I915_READ(DPLL_CTRL1);
		2601
		2602	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) \| DPLL_CTRL1_SSC(dpll) \|
6084	serge	2603	DPLL_CTRL1_LINK_RATE_MASK(dpll));
5354	serge	2604	val \|= pll->config.hw_state.ctrl1 << (dpll * 6);
		2605
		2606	I915_WRITE(DPLL_CTRL1, val);
		2607	POSTING_READ(DPLL_CTRL1);
		2608
		2609	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
		2610	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
		2611	POSTING_READ(regs[pll->id].cfgcr1);
		2612	POSTING_READ(regs[pll->id].cfgcr2);
		2613
		2614	/* the enable bit is always bit 31 */
		2615	I915_WRITE(regs[pll->id].ctl,
		2616	I915_READ(regs[pll->id].ctl) \| LCPLL_PLL_ENABLE);
		2617
		2618	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
		2619	DRM_ERROR("DPLL %d not locked\n", dpll);
		2620	}
		2621
		2622	static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
		2623	struct intel_shared_dpll *pll)
		2624	{
		2625	const struct skl_dpll_regs *regs = skl_dpll_regs;
		2626
		2627	/* the enable bit is always bit 31 */
		2628	I915_WRITE(regs[pll->id].ctl,
		2629	I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
		2630	POSTING_READ(regs[pll->id].ctl);
		2631	}
		2632
		2633	static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
		2634	struct intel_shared_dpll *pll,
		2635	struct intel_dpll_hw_state *hw_state)
		2636	{
		2637	uint32_t val;
		2638	unsigned int dpll;
		2639	const struct skl_dpll_regs *regs = skl_dpll_regs;
		2640
		2641	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
		2642	return false;
		2643
		2644	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
		2645	dpll = pll->id + 1;
		2646
		2647	val = I915_READ(regs[pll->id].ctl);
		2648	if (!(val & LCPLL_PLL_ENABLE))
		2649	return false;
		2650
		2651	val = I915_READ(DPLL_CTRL1);
		2652	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
		2653
		2654	/* avoid reading back stale values if HDMI mode is not enabled */
		2655	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
		2656	hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
		2657	hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
		2658	}
		2659
		2660	return true;
		2661	}
		2662
		2663	static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
		2664	{
		2665	int i;
		2666
		2667	dev_priv->num_shared_dpll = 3;
		2668
		2669	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		2670	dev_priv->shared_dplls[i].id = i;
		2671	dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
		2672	dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
		2673	dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
		2674	dev_priv->shared_dplls[i].get_hw_state =
		2675	skl_ddi_pll_get_hw_state;
		2676	}
		2677	}
		2678
6084	serge	2679	static void broxton_phy_init(struct drm_i915_private *dev_priv,
		2680	enum dpio_phy phy)
		2681	{
		2682	enum port port;
		2683	uint32_t val;
		2684
		2685	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
		2686	val \|= GT_DISPLAY_POWER_ON(phy);
		2687	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
		2688
		2689	/* Considering 10ms timeout until BSpec is updated */
		2690	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
		2691	DRM_ERROR("timeout during PHY%d power on\n", phy);
		2692
		2693	for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
		2694	port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
		2695	int lane;
		2696
		2697	for (lane = 0; lane < 4; lane++) {
		2698	val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
		2699	/*
		2700	* Note that on CHV this flag is called UPAR, but has
		2701	* the same function.
		2702	*/
		2703	val &= ~LATENCY_OPTIM;
		2704	if (lane != 1)
		2705	val \|= LATENCY_OPTIM;
		2706
		2707	I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
		2708	}
		2709	}
		2710
		2711	/* Program PLL Rcomp code offset */
		2712	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
		2713	val &= ~IREF0RC_OFFSET_MASK;
		2714	val \|= 0xE4 << IREF0RC_OFFSET_SHIFT;
		2715	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
		2716
		2717	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
		2718	val &= ~IREF1RC_OFFSET_MASK;
		2719	val \|= 0xE4 << IREF1RC_OFFSET_SHIFT;
		2720	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
		2721
		2722	/* Program power gating */
		2723	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
		2724	val \|= OCL1_POWER_DOWN_EN \| DW28_OLDO_DYN_PWR_DOWN_EN \|
		2725	SUS_CLK_CONFIG;
		2726	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
		2727
		2728	if (phy == DPIO_PHY0) {
		2729	val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
		2730	val \|= DW6_OLDO_DYN_PWR_DOWN_EN;
		2731	I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
		2732	}
		2733
		2734	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
		2735	val &= ~OCL2_LDOFUSE_PWR_DIS;
		2736	/*
		2737	* On PHY1 disable power on the second channel, since no port is
		2738	* connected there. On PHY0 both channels have a port, so leave it
		2739	* enabled.
		2740	* TODO: port C is only connected on BXT-P, so on BXT0/1 we should
		2741	* power down the second channel on PHY0 as well.
		2742	*/
		2743	if (phy == DPIO_PHY1)
		2744	val \|= OCL2_LDOFUSE_PWR_DIS;
		2745	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
		2746
		2747	if (phy == DPIO_PHY0) {
		2748	uint32_t grc_code;
		2749	/*
		2750	* PHY0 isn't connected to an RCOMP resistor so copy over
		2751	* the corresponding calibrated value from PHY1, and disable
		2752	* the automatic calibration on PHY0.
		2753	*/
		2754	if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
		2755	10))
		2756	DRM_ERROR("timeout waiting for PHY1 GRC\n");
		2757
		2758	val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
		2759	val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
		2760	grc_code = val << GRC_CODE_FAST_SHIFT \|
		2761	val << GRC_CODE_SLOW_SHIFT \|
		2762	val;
		2763	I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
		2764
		2765	val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
		2766	val \|= GRC_DIS \| GRC_RDY_OVRD;
		2767	I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
		2768	}
		2769
		2770	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
		2771	val \|= COMMON_RESET_DIS;
		2772	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
		2773	}
		2774
		2775	void broxton_ddi_phy_init(struct drm_device *dev)
		2776	{
		2777	/* Enable PHY1 first since it provides Rcomp for PHY0 */
		2778	broxton_phy_init(dev->dev_private, DPIO_PHY1);
		2779	broxton_phy_init(dev->dev_private, DPIO_PHY0);
		2780	}
		2781
		2782	static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
		2783	enum dpio_phy phy)
		2784	{
		2785	uint32_t val;
		2786
		2787	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
		2788	val &= ~COMMON_RESET_DIS;
		2789	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
		2790	}
		2791
		2792	void broxton_ddi_phy_uninit(struct drm_device *dev)
		2793	{
		2794	struct drm_i915_private *dev_priv = dev->dev_private;
		2795
		2796	broxton_phy_uninit(dev_priv, DPIO_PHY1);
		2797	broxton_phy_uninit(dev_priv, DPIO_PHY0);
		2798
		2799	/* FIXME: do this in broxton_phy_uninit per phy */
		2800	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
		2801	}
		2802
		2803	static const char * const bxt_ddi_pll_names[] = {
		2804	"PORT PLL A",
		2805	"PORT PLL B",
		2806	"PORT PLL C",
		2807	};
		2808
		2809	static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
		2810	struct intel_shared_dpll *pll)
		2811	{
		2812	uint32_t temp;
		2813	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2814
		2815	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2816	temp &= ~PORT_PLL_REF_SEL;
		2817	/* Non-SSC reference */
		2818	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2819
		2820	/* Disable 10 bit clock */
		2821	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2822	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
		2823	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2824
		2825	/* Write P1 & P2 */
		2826	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
		2827	temp &= ~(PORT_PLL_P1_MASK \| PORT_PLL_P2_MASK);
		2828	temp \|= pll->config.hw_state.ebb0;
		2829	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
		2830
		2831	/* Write M2 integer */
		2832	temp = I915_READ(BXT_PORT_PLL(port, 0));
		2833	temp &= ~PORT_PLL_M2_MASK;
		2834	temp \|= pll->config.hw_state.pll0;
		2835	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
		2836
		2837	/* Write N */
		2838	temp = I915_READ(BXT_PORT_PLL(port, 1));
		2839	temp &= ~PORT_PLL_N_MASK;
		2840	temp \|= pll->config.hw_state.pll1;
		2841	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
		2842
		2843	/* Write M2 fraction */
		2844	temp = I915_READ(BXT_PORT_PLL(port, 2));
		2845	temp &= ~PORT_PLL_M2_FRAC_MASK;
		2846	temp \|= pll->config.hw_state.pll2;
		2847	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
		2848
		2849	/* Write M2 fraction enable */
		2850	temp = I915_READ(BXT_PORT_PLL(port, 3));
		2851	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
		2852	temp \|= pll->config.hw_state.pll3;
		2853	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
		2854
		2855	/* Write coeff */
		2856	temp = I915_READ(BXT_PORT_PLL(port, 6));
		2857	temp &= ~PORT_PLL_PROP_COEFF_MASK;
		2858	temp &= ~PORT_PLL_INT_COEFF_MASK;
		2859	temp &= ~PORT_PLL_GAIN_CTL_MASK;
		2860	temp \|= pll->config.hw_state.pll6;
		2861	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
		2862
		2863	/* Write calibration val */
		2864	temp = I915_READ(BXT_PORT_PLL(port, 8));
		2865	temp &= ~PORT_PLL_TARGET_CNT_MASK;
		2866	temp \|= pll->config.hw_state.pll8;
		2867	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
		2868
		2869	temp = I915_READ(BXT_PORT_PLL(port, 9));
		2870	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
		2871	temp \|= pll->config.hw_state.pll9;
		2872	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
		2873
		2874	temp = I915_READ(BXT_PORT_PLL(port, 10));
		2875	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
		2876	temp &= ~PORT_PLL_DCO_AMP_MASK;
		2877	temp \|= pll->config.hw_state.pll10;
		2878	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
		2879
		2880	/* Recalibrate with new settings */
		2881	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2882	temp \|= PORT_PLL_RECALIBRATE;
		2883	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2884	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
		2885	temp \|= pll->config.hw_state.ebb4;
		2886	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
		2887
		2888	/* Enable PLL */
		2889	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2890	temp \|= PORT_PLL_ENABLE;
		2891	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2892	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
		2893
		2894	if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
		2895	PORT_PLL_LOCK), 200))
		2896	DRM_ERROR("PLL %d not locked\n", port);
		2897
		2898	/*
		2899	* While we write to the group register to program all lanes at once we
		2900	* can read only lane registers and we pick lanes 0/1 for that.
		2901	*/
		2902	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
		2903	temp &= ~LANE_STAGGER_MASK;
		2904	temp &= ~LANESTAGGER_STRAP_OVRD;
		2905	temp \|= pll->config.hw_state.pcsdw12;
		2906	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
		2907	}
		2908
		2909	static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
		2910	struct intel_shared_dpll *pll)
		2911	{
		2912	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2913	uint32_t temp;
		2914
		2915	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2916	temp &= ~PORT_PLL_ENABLE;
		2917	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
		2918	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
		2919	}
		2920
		2921	static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
		2922	struct intel_shared_dpll *pll,
		2923	struct intel_dpll_hw_state *hw_state)
		2924	{
		2925	enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
		2926	uint32_t val;
		2927
		2928	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
		2929	return false;
		2930
		2931	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
		2932	if (!(val & PORT_PLL_ENABLE))
		2933	return false;
		2934
		2935	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
		2936	hw_state->ebb0 &= PORT_PLL_P1_MASK \| PORT_PLL_P2_MASK;
		2937
		2938	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
		2939	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
		2940
		2941	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
		2942	hw_state->pll0 &= PORT_PLL_M2_MASK;
		2943
		2944	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
		2945	hw_state->pll1 &= PORT_PLL_N_MASK;
		2946
		2947	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
		2948	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
		2949
		2950	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
		2951	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
		2952
		2953	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
		2954	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK \|
		2955	PORT_PLL_INT_COEFF_MASK \|
		2956	PORT_PLL_GAIN_CTL_MASK;
		2957
		2958	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
		2959	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
		2960
		2961	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
		2962	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
		2963
		2964	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
		2965	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H \|
		2966	PORT_PLL_DCO_AMP_MASK;
		2967
		2968	/*
		2969	* While we write to the group register to program all lanes at once we
		2970	* can read only lane registers. We configure all lanes the same way, so
		2971	* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
		2972	*/
		2973	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
		2974	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
		2975	DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
		2976	hw_state->pcsdw12,
		2977	I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
		2978	hw_state->pcsdw12 &= LANE_STAGGER_MASK \| LANESTAGGER_STRAP_OVRD;
		2979
		2980	return true;
		2981	}
		2982
		2983	static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
		2984	{
		2985	int i;
		2986
		2987	dev_priv->num_shared_dpll = 3;
		2988
		2989	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		2990	dev_priv->shared_dplls[i].id = i;
		2991	dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
		2992	dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
		2993	dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
		2994	dev_priv->shared_dplls[i].get_hw_state =
		2995	bxt_ddi_pll_get_hw_state;
		2996	}
		2997	}
		2998
5354	serge	2999	void intel_ddi_pll_init(struct drm_device *dev)
		3000	{
		3001	struct drm_i915_private *dev_priv = dev->dev_private;
		3002	uint32_t val = I915_READ(LCPLL_CTL);
		3003
		3004	if (IS_SKYLAKE(dev))
		3005	skl_shared_dplls_init(dev_priv);
6084	serge	3006	else if (IS_BROXTON(dev))
		3007	bxt_shared_dplls_init(dev_priv);
5354	serge	3008	else
		3009	hsw_shared_dplls_init(dev_priv);
		3010
6084	serge	3011	if (IS_SKYLAKE(dev)) {
		3012	int cdclk_freq;
3243	Serge	3013
6084	serge	3014	cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
		3015	dev_priv->skl_boot_cdclk = cdclk_freq;
5354	serge	3016	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
		3017	DRM_ERROR("LCPLL1 is disabled\n");
6084	serge	3018	else
		3019	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		3020	} else if (IS_BROXTON(dev)) {
		3021	broxton_init_cdclk(dev);
		3022	broxton_ddi_phy_init(dev);
5354	serge	3023	} else {
		3024	/*
		3025	* The LCPLL register should be turned on by the BIOS. For now
		3026	* let's just check its state and print errors in case
		3027	* something is wrong. Don't even try to turn it on.
		3028	*/
		3029
6084	serge	3030	if (val & LCPLL_CD_SOURCE_FCLK)
		3031	DRM_ERROR("CDCLK source is not LCPLL\n");
3243	Serge	3032
6084	serge	3033	if (val & LCPLL_PLL_DISABLE)
		3034	DRM_ERROR("LCPLL is disabled\n");
5354	serge	3035	}
3243	Serge	3036	}
		3037
		3038	void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
		3039	{
		3040	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
		3041	struct intel_dp *intel_dp = &intel_dig_port->dp;
		3042	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
		3043	enum port port = intel_dig_port->port;
		3044	uint32_t val;
3480	Serge	3045	bool wait = false;
3243	Serge	3046
		3047	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		3048	val = I915_READ(DDI_BUF_CTL(port));
		3049	if (val & DDI_BUF_CTL_ENABLE) {
		3050	val &= ~DDI_BUF_CTL_ENABLE;
		3051	I915_WRITE(DDI_BUF_CTL(port), val);
		3052	wait = true;
		3053	}
		3054
		3055	val = I915_READ(DP_TP_CTL(port));
		3056	val &= ~(DP_TP_CTL_ENABLE \| DP_TP_CTL_LINK_TRAIN_MASK);
		3057	val \|= DP_TP_CTL_LINK_TRAIN_PAT1;
		3058	I915_WRITE(DP_TP_CTL(port), val);
		3059	POSTING_READ(DP_TP_CTL(port));
		3060
		3061	if (wait)
		3062	intel_wait_ddi_buf_idle(dev_priv, port);
		3063	}
		3064
5060	serge	3065	val = DP_TP_CTL_ENABLE \|
3243	Serge	3066	DP_TP_CTL_LINK_TRAIN_PAT1 \| DP_TP_CTL_SCRAMBLE_DISABLE;
5060	serge	3067	if (intel_dp->is_mst)
		3068	val \|= DP_TP_CTL_MODE_MST;
		3069	else {
		3070	val \|= DP_TP_CTL_MODE_SST;
6084	serge	3071	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		3072	val \|= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
5060	serge	3073	}
3243	Serge	3074	I915_WRITE(DP_TP_CTL(port), val);
		3075	POSTING_READ(DP_TP_CTL(port));
		3076
		3077	intel_dp->DP \|= DDI_BUF_CTL_ENABLE;
		3078	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
		3079	POSTING_READ(DDI_BUF_CTL(port));
		3080
		3081	udelay(600);
		3082	}
		3083
		3084	void intel_ddi_fdi_disable(struct drm_crtc *crtc)
		3085	{
		3086	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
		3087	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
		3088	uint32_t val;
		3089
		3090	intel_ddi_post_disable(intel_encoder);
		3091
6084	serge	3092	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3093	val &= ~FDI_RX_ENABLE;
6084	serge	3094	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3095
6084	serge	3096	val = I915_READ(FDI_RX_MISC(PIPE_A));
3243	Serge	3097	val &= ~(FDI_RX_PWRDN_LANE1_MASK \| FDI_RX_PWRDN_LANE0_MASK);
		3098	val \|= FDI_RX_PWRDN_LANE1_VAL(2) \| FDI_RX_PWRDN_LANE0_VAL(2);
6084	serge	3099	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3243	Serge	3100
6084	serge	3101	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3102	val &= ~FDI_PCDCLK;
6084	serge	3103	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3104
6084	serge	3105	val = I915_READ(FDI_RX_CTL(PIPE_A));
3243	Serge	3106	val &= ~FDI_RX_PLL_ENABLE;
6084	serge	3107	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3243	Serge	3108	}
		3109
4280	Serge	3110	void intel_ddi_get_config(struct intel_encoder *encoder,
6084	serge	3111	struct intel_crtc_state *pipe_config)
4104	Serge	3112	{
		3113	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
		3114	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
6084	serge	3115	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5354	serge	3116	struct intel_hdmi *intel_hdmi;
4104	Serge	3117	u32 temp, flags = 0;
		3118
		3119	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
		3120	if (temp & TRANS_DDI_PHSYNC)
		3121	flags \|= DRM_MODE_FLAG_PHSYNC;
		3122	else
		3123	flags \|= DRM_MODE_FLAG_NHSYNC;
		3124	if (temp & TRANS_DDI_PVSYNC)
		3125	flags \|= DRM_MODE_FLAG_PVSYNC;
		3126	else
		3127	flags \|= DRM_MODE_FLAG_NVSYNC;
		3128
6084	serge	3129	pipe_config->base.adjusted_mode.flags \|= flags;
4280	Serge	3130
		3131	switch (temp & TRANS_DDI_BPC_MASK) {
		3132	case TRANS_DDI_BPC_6:
		3133	pipe_config->pipe_bpp = 18;
		3134	break;
		3135	case TRANS_DDI_BPC_8:
		3136	pipe_config->pipe_bpp = 24;
		3137	break;
		3138	case TRANS_DDI_BPC_10:
		3139	pipe_config->pipe_bpp = 30;
		3140	break;
		3141	case TRANS_DDI_BPC_12:
		3142	pipe_config->pipe_bpp = 36;
		3143	break;
		3144	default:
		3145	break;
		3146	}
4371	Serge	3147
4560	Serge	3148	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
		3149	case TRANS_DDI_MODE_SELECT_HDMI:
5060	serge	3150	pipe_config->has_hdmi_sink = true;
5354	serge	3151	intel_hdmi = enc_to_intel_hdmi(&encoder->base);
		3152
		3153	if (intel_hdmi->infoframe_enabled(&encoder->base))
		3154	pipe_config->has_infoframe = true;
		3155	break;
4560	Serge	3156	case TRANS_DDI_MODE_SELECT_DVI:
		3157	case TRANS_DDI_MODE_SELECT_FDI:
		3158	break;
		3159	case TRANS_DDI_MODE_SELECT_DP_SST:
		3160	case TRANS_DDI_MODE_SELECT_DP_MST:
		3161	pipe_config->has_dp_encoder = true;
6084	serge	3162	pipe_config->lane_count =
		3163	((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4560	Serge	3164	intel_dp_get_m_n(intel_crtc, pipe_config);
		3165	break;
		3166	default:
		3167	break;
		3168	}
		3169
5354	serge	3170	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
5060	serge	3171	temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5354	serge	3172	if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
5060	serge	3173	pipe_config->has_audio = true;
		3174	}
		3175
4371	Serge	3176	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
		3177	pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		3178	/*
		3179	* This is a big fat ugly hack.
		3180	*
		3181	* Some machines in UEFI boot mode provide us a VBT that has 18
		3182	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		3183	* unknown we fail to light up. Yet the same BIOS boots up with
		3184	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		3185	* max, not what it tells us to use.
		3186	*
		3187	* Note: This will still be broken if the eDP panel is not lit
		3188	* up by the BIOS, and thus we can't get the mode at module
		3189	* load.
		3190	*/
		3191	DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
		3192	pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		3193	dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
		3194	}
5060	serge	3195
6084	serge	3196	intel_ddi_clock_get(encoder, pipe_config);
4104	Serge	3197	}
		3198
3746	Serge	3199	static bool intel_ddi_compute_config(struct intel_encoder *encoder,
6084	serge	3200	struct intel_crtc_state *pipe_config)
3243	Serge	3201	{
3746	Serge	3202	int type = encoder->type;
4104	Serge	3203	int port = intel_ddi_get_encoder_port(encoder);
3243	Serge	3204
3746	Serge	3205	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3243	Serge	3206
4104	Serge	3207	if (port == PORT_A)
		3208	pipe_config->cpu_transcoder = TRANSCODER_EDP;
		3209
3243	Serge	3210	if (type == INTEL_OUTPUT_HDMI)
3746	Serge	3211	return intel_hdmi_compute_config(encoder, pipe_config);
3243	Serge	3212	else
3746	Serge	3213	return intel_dp_compute_config(encoder, pipe_config);
3243	Serge	3214	}
		3215
		3216	static const struct drm_encoder_funcs intel_ddi_funcs = {
6660	serge	3217	.reset = intel_dp_encoder_reset,
		3218	.destroy = intel_dp_encoder_destroy,
3243	Serge	3219	};
		3220
4560	Serge	3221	static struct intel_connector *
		3222	intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
		3223	{
		3224	struct intel_connector *connector;
		3225	enum port port = intel_dig_port->port;
		3226
6084	serge	3227	connector = intel_connector_alloc();
4560	Serge	3228	if (!connector)
		3229	return NULL;
		3230
		3231	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
		3232	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		3233	kfree(connector);
		3234	return NULL;
		3235	}
		3236
		3237	return connector;
		3238	}
		3239
		3240	static struct intel_connector *
		3241	intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
		3242	{
		3243	struct intel_connector *connector;
		3244	enum port port = intel_dig_port->port;
		3245
6084	serge	3246	connector = intel_connector_alloc();
4560	Serge	3247	if (!connector)
		3248	return NULL;
		3249
		3250	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
		3251	intel_hdmi_init_connector(intel_dig_port, connector);
		3252
		3253	return connector;
		3254	}
		3255
3243	Serge	3256	void intel_ddi_init(struct drm_device *dev, enum port port)
		3257	{
3480	Serge	3258	struct drm_i915_private *dev_priv = dev->dev_private;
3243	Serge	3259	struct intel_digital_port *intel_dig_port;
		3260	struct intel_encoder *intel_encoder;
		3261	struct drm_encoder *encoder;
4560	Serge	3262	bool init_hdmi, init_dp;
3243	Serge	3263
4560	Serge	3264	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi \|\|
		3265	dev_priv->vbt.ddi_port_info[port].supports_hdmi);
		3266	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
		3267	if (!init_dp && !init_hdmi) {
6084	serge	3268	DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4560	Serge	3269	port_name(port));
6084	serge	3270	return;
4560	Serge	3271	}
		3272
		3273	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3243	Serge	3274	if (!intel_dig_port)
		3275	return;
		3276
		3277	intel_encoder = &intel_dig_port->base;
		3278	encoder = &intel_encoder->base;
		3279
		3280	drm_encoder_init(dev, encoder, &intel_ddi_funcs,
		3281	DRM_MODE_ENCODER_TMDS);
		3282
3746	Serge	3283	intel_encoder->compute_config = intel_ddi_compute_config;
3243	Serge	3284	intel_encoder->enable = intel_enable_ddi;
		3285	intel_encoder->pre_enable = intel_ddi_pre_enable;
		3286	intel_encoder->disable = intel_disable_ddi;
		3287	intel_encoder->post_disable = intel_ddi_post_disable;
		3288	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4104	Serge	3289	intel_encoder->get_config = intel_ddi_get_config;
6660	serge	3290	intel_encoder->suspend = intel_dp_encoder_suspend;
3243	Serge	3291
		3292	intel_dig_port->port = port;
4104	Serge	3293	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
		3294	(DDI_BUF_PORT_REVERSAL \|
		3295	DDI_A_4_LANES);
3243	Serge	3296
		3297	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
6084	serge	3298	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
5060	serge	3299	intel_encoder->cloneable = 0;
3243	Serge	3300
5060	serge	3301	if (init_dp) {
		3302	if (!intel_ddi_init_dp_connector(intel_dig_port))
		3303	goto err;
4560	Serge	3304
5060	serge	3305	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6084	serge	3306	/*
		3307	* On BXT A0/A1, sw needs to activate DDIA HPD logic and
		3308	* interrupts to check the external panel connection.
		3309	*/
		3310	if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
		3311	&& port == PORT_B)
		3312	dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
		3313	else
		3314	dev_priv->hotplug.irq_port[port] = intel_dig_port;
5060	serge	3315	}
		3316
4560	Serge	3317	/* In theory we don't need the encoder->type check, but leave it just in
		3318	* case we have some really bad VBTs... */
5060	serge	3319	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		3320	if (!intel_ddi_init_hdmi_connector(intel_dig_port))
		3321	goto err;
		3322	}
4560	Serge	3323
5060	serge	3324	return;
		3325
		3326	err:
6084	serge	3327	drm_encoder_cleanup(encoder);
		3328	kfree(intel_dig_port);
3243	Serge	3329	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ddi.c – Rev 6660