Rev 6937 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
||
3 | * |
||
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
5 | * copy of this software and associated documentation files (the "Software"), |
||
6 | * to deal in the Software without restriction, including without limitation |
||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
8 | * and/or sell copies of the Software, and to permit persons to whom the |
||
9 | * Software is furnished to do so, subject to the following conditions: |
||
10 | * |
||
11 | * The above copyright notice and this permission notice (including the next |
||
12 | * paragraph) shall be included in all copies or substantial portions of the |
||
13 | * Software. |
||
14 | * |
||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
||
21 | * DEALINGS IN THE SOFTWARE. |
||
22 | * |
||
23 | * Authors: |
||
24 | * Eric Anholt |
||
25 | */ |
||
26 | |||
5097 | serge | 27 | #include |
2330 | Serge | 28 | #include |
29 | #include |
||
3031 | serge | 30 | #include |
6084 | serge | 31 | #include |
3031 | serge | 32 | #include |
33 | #include |
||
34 | #include |
||
2330 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2330 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | /* Here's the desired hotplug mode */ |
||
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
||
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
||
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
||
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
||
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
||
45 | ADPA_CRT_HOTPLUG_ENABLE) |
||
46 | |||
47 | struct intel_crt { |
||
48 | struct intel_encoder base; |
||
3480 | Serge | 49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ |
||
51 | struct intel_connector *connector; |
||
2330 | Serge | 52 | bool force_hotplug_required; |
6937 | serge | 53 | i915_reg_t adpa_reg; |
2330 | Serge | 54 | }; |
55 | |||
4104 | Serge | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 57 | { |
4104 | Serge | 58 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 59 | } |
60 | |||
4104 | Serge | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 62 | { |
4104 | Serge | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 64 | } |
65 | |||
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
||
67 | enum pipe *pipe) |
||
68 | { |
||
69 | struct drm_device *dev = encoder->base.dev; |
||
2330 | Serge | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
5060 | serge | 72 | enum intel_display_power_domain power_domain; |
3031 | serge | 73 | u32 tmp; |
6937 | serge | 74 | bool ret; |
2330 | Serge | 75 | |
5060 | serge | 76 | power_domain = intel_display_port_power_domain(encoder); |
6937 | serge | 77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
5060 | serge | 78 | return false; |
79 | |||
6937 | serge | 80 | ret = false; |
81 | |||
3031 | serge | 82 | tmp = I915_READ(crt->adpa_reg); |
83 | |||
84 | if (!(tmp & ADPA_DAC_ENABLE)) |
||
6937 | serge | 85 | goto out; |
3031 | serge | 86 | |
87 | if (HAS_PCH_CPT(dev)) |
||
88 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
2330 | Serge | 89 | else |
3031 | serge | 90 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 91 | |
6937 | serge | 92 | ret = true; |
93 | out: |
||
94 | intel_display_power_put(dev_priv, power_domain); |
||
95 | |||
96 | return ret; |
||
3031 | serge | 97 | } |
98 | |||
4280 | Serge | 99 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
4104 | Serge | 100 | { |
101 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
102 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
||
103 | u32 tmp, flags = 0; |
||
104 | |||
105 | tmp = I915_READ(crt->adpa_reg); |
||
106 | |||
107 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
||
108 | flags |= DRM_MODE_FLAG_PHSYNC; |
||
109 | else |
||
110 | flags |= DRM_MODE_FLAG_NHSYNC; |
||
111 | |||
112 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
||
113 | flags |= DRM_MODE_FLAG_PVSYNC; |
||
114 | else |
||
115 | flags |= DRM_MODE_FLAG_NVSYNC; |
||
116 | |||
4280 | Serge | 117 | return flags; |
4104 | Serge | 118 | } |
119 | |||
4280 | Serge | 120 | static void intel_crt_get_config(struct intel_encoder *encoder, |
6084 | serge | 121 | struct intel_crtc_state *pipe_config) |
4280 | Serge | 122 | { |
4560 | Serge | 123 | struct drm_device *dev = encoder->base.dev; |
124 | int dotclock; |
||
125 | |||
6084 | serge | 126 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4560 | Serge | 127 | |
128 | dotclock = pipe_config->port_clock; |
||
129 | |||
130 | if (HAS_PCH_SPLIT(dev)) |
||
131 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
||
132 | |||
6084 | serge | 133 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
4280 | Serge | 134 | } |
135 | |||
136 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
||
6084 | serge | 137 | struct intel_crtc_state *pipe_config) |
4280 | Serge | 138 | { |
139 | intel_ddi_get_config(encoder, pipe_config); |
||
140 | |||
6084 | serge | 141 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
4280 | Serge | 142 | DRM_MODE_FLAG_NHSYNC | |
143 | DRM_MODE_FLAG_PVSYNC | |
||
144 | DRM_MODE_FLAG_NVSYNC); |
||
6084 | serge | 145 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4280 | Serge | 146 | } |
147 | |||
3031 | serge | 148 | /* Note: The caller is required to filter out dpms modes not supported by the |
149 | * platform. */ |
||
150 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
||
151 | { |
||
152 | struct drm_device *dev = encoder->base.dev; |
||
153 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
154 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
||
5060 | serge | 155 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6084 | serge | 156 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 157 | u32 adpa; |
3031 | serge | 158 | |
5060 | serge | 159 | if (INTEL_INFO(dev)->gen >= 5) |
160 | adpa = ADPA_HOTPLUG_BITS; |
||
161 | else |
||
162 | adpa = 0; |
||
3031 | serge | 163 | |
5060 | serge | 164 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
165 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
||
166 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
167 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
||
168 | |||
169 | /* For CPT allow 3 pipe config, for others just use A or B */ |
||
170 | if (HAS_PCH_LPT(dev)) |
||
171 | ; /* Those bits don't exist here */ |
||
172 | else if (HAS_PCH_CPT(dev)) |
||
173 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
||
174 | else if (crtc->pipe == 0) |
||
175 | adpa |= ADPA_PIPE_A_SELECT; |
||
176 | else |
||
177 | adpa |= ADPA_PIPE_B_SELECT; |
||
178 | |||
179 | if (!HAS_PCH_SPLIT(dev)) |
||
180 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
||
181 | |||
2342 | Serge | 182 | switch (mode) { |
2330 | Serge | 183 | case DRM_MODE_DPMS_ON: |
5060 | serge | 184 | adpa |= ADPA_DAC_ENABLE; |
2330 | Serge | 185 | break; |
186 | case DRM_MODE_DPMS_STANDBY: |
||
5060 | serge | 187 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
2330 | Serge | 188 | break; |
189 | case DRM_MODE_DPMS_SUSPEND: |
||
5060 | serge | 190 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 191 | break; |
192 | case DRM_MODE_DPMS_OFF: |
||
5060 | serge | 193 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 194 | break; |
195 | } |
||
196 | |||
5060 | serge | 197 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 198 | } |
199 | |||
3480 | Serge | 200 | static void intel_disable_crt(struct intel_encoder *encoder) |
201 | { |
||
202 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
203 | } |
||
204 | |||
6084 | serge | 205 | static void pch_disable_crt(struct intel_encoder *encoder) |
206 | { |
||
207 | } |
||
5060 | serge | 208 | |
6084 | serge | 209 | static void pch_post_disable_crt(struct intel_encoder *encoder) |
5060 | serge | 210 | { |
6084 | serge | 211 | intel_disable_crt(encoder); |
5060 | serge | 212 | } |
213 | |||
3480 | Serge | 214 | static void intel_enable_crt(struct intel_encoder *encoder) |
215 | { |
||
7144 | serge | 216 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON); |
3480 | Serge | 217 | } |
218 | |||
4560 | Serge | 219 | static enum drm_mode_status |
220 | intel_crt_mode_valid(struct drm_connector *connector, |
||
5060 | serge | 221 | struct drm_display_mode *mode) |
2330 | Serge | 222 | { |
223 | struct drm_device *dev = connector->dev; |
||
7144 | serge | 224 | int max_dotclk = to_i915(dev)->max_dotclk_freq; |
2330 | Serge | 225 | |
226 | int max_clock = 0; |
||
227 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
228 | return MODE_NO_DBLESCAN; |
||
229 | |||
230 | if (mode->clock < 25000) |
||
231 | return MODE_CLOCK_LOW; |
||
232 | |||
233 | if (IS_GEN2(dev)) |
||
234 | max_clock = 350000; |
||
235 | else |
||
236 | max_clock = 400000; |
||
237 | if (mode->clock > max_clock) |
||
238 | return MODE_CLOCK_HIGH; |
||
239 | |||
7144 | serge | 240 | if (mode->clock > max_dotclk) |
241 | return MODE_CLOCK_HIGH; |
||
242 | |||
3243 | Serge | 243 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
244 | if (HAS_PCH_LPT(dev) && |
||
245 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
||
246 | return MODE_CLOCK_HIGH; |
||
247 | |||
2330 | Serge | 248 | return MODE_OK; |
249 | } |
||
250 | |||
3746 | Serge | 251 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
6084 | serge | 252 | struct intel_crtc_state *pipe_config) |
2330 | Serge | 253 | { |
3746 | Serge | 254 | struct drm_device *dev = encoder->base.dev; |
255 | |||
256 | if (HAS_PCH_SPLIT(dev)) |
||
257 | pipe_config->has_pch_encoder = true; |
||
258 | |||
4104 | Serge | 259 | /* LPT FDI RX only supports 8bpc. */ |
6660 | serge | 260 | if (HAS_PCH_LPT(dev)) { |
261 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
||
262 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); |
||
263 | return false; |
||
264 | } |
||
265 | |||
4104 | Serge | 266 | pipe_config->pipe_bpp = 24; |
6660 | serge | 267 | } |
4104 | Serge | 268 | |
5060 | serge | 269 | /* FDI must always be 2.7 GHz */ |
270 | if (HAS_DDI(dev)) { |
||
271 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
||
272 | pipe_config->port_clock = 135000 * 2; |
||
6084 | serge | 273 | |
274 | pipe_config->dpll_hw_state.wrpll = 0; |
||
275 | pipe_config->dpll_hw_state.spll = |
||
276 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
||
5060 | serge | 277 | } |
278 | |||
2330 | Serge | 279 | return true; |
280 | } |
||
281 | |||
282 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
||
283 | { |
||
284 | struct drm_device *dev = connector->dev; |
||
285 | struct intel_crt *crt = intel_attached_crt(connector); |
||
286 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
287 | u32 adpa; |
||
288 | bool ret; |
||
289 | |||
290 | /* The first time through, trigger an explicit detection cycle */ |
||
291 | if (crt->force_hotplug_required) { |
||
292 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
||
293 | u32 save_adpa; |
||
294 | |||
295 | crt->force_hotplug_required = 0; |
||
296 | |||
3480 | Serge | 297 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 298 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
299 | |||
300 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
||
301 | if (turn_off_dac) |
||
302 | adpa &= ~ADPA_DAC_ENABLE; |
||
303 | |||
3480 | Serge | 304 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 305 | |
3480 | Serge | 306 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 307 | 1000)) |
308 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
||
309 | |||
310 | if (turn_off_dac) { |
||
3480 | Serge | 311 | I915_WRITE(crt->adpa_reg, save_adpa); |
312 | POSTING_READ(crt->adpa_reg); |
||
2330 | Serge | 313 | } |
314 | } |
||
315 | |||
316 | /* Check the status to see if both blue and green are on now */ |
||
3480 | Serge | 317 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 318 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
319 | ret = true; |
||
320 | else |
||
321 | ret = false; |
||
322 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
||
323 | |||
324 | return ret; |
||
325 | } |
||
326 | |||
3031 | serge | 327 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
328 | { |
||
329 | struct drm_device *dev = connector->dev; |
||
3480 | Serge | 330 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 331 | struct drm_i915_private *dev_priv = dev->dev_private; |
332 | u32 adpa; |
||
333 | bool ret; |
||
334 | u32 save_adpa; |
||
335 | |||
3480 | Serge | 336 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 337 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
338 | |||
339 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
||
340 | |||
3480 | Serge | 341 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 342 | |
3480 | Serge | 343 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 344 | 1000)) { |
345 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
||
3480 | Serge | 346 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 347 | } |
348 | |||
349 | /* Check the status to see if both blue and green are on now */ |
||
3480 | Serge | 350 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 351 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
352 | ret = true; |
||
353 | else |
||
354 | ret = false; |
||
355 | |||
356 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
||
357 | |||
358 | return ret; |
||
359 | } |
||
360 | |||
2330 | Serge | 361 | /** |
362 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
||
363 | * |
||
364 | * Not for i915G/i915GM |
||
365 | * |
||
366 | * \return true if CRT is connected. |
||
367 | * \return false if CRT is disconnected. |
||
368 | */ |
||
369 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
||
370 | { |
||
371 | struct drm_device *dev = connector->dev; |
||
372 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 373 | u32 stat; |
2330 | Serge | 374 | bool ret = false; |
375 | int i, tries = 0; |
||
376 | |||
377 | if (HAS_PCH_SPLIT(dev)) |
||
378 | return intel_ironlake_crt_detect_hotplug(connector); |
||
379 | |||
3031 | serge | 380 | if (IS_VALLEYVIEW(dev)) |
381 | return valleyview_crt_detect_hotplug(connector); |
||
382 | |||
2330 | Serge | 383 | /* |
384 | * On 4 series desktop, CRT detect sequence need to be done twice |
||
385 | * to get a reliable result. |
||
386 | */ |
||
387 | |||
388 | if (IS_G4X(dev) && !IS_GM45(dev)) |
||
389 | tries = 2; |
||
390 | else |
||
391 | tries = 1; |
||
392 | |||
393 | for (i = 0; i < tries ; i++) { |
||
394 | /* turn on the FORCE_DETECT */ |
||
6084 | serge | 395 | i915_hotplug_interrupt_update(dev_priv, |
396 | CRT_HOTPLUG_FORCE_DETECT, |
||
397 | CRT_HOTPLUG_FORCE_DETECT); |
||
2330 | Serge | 398 | /* wait for FORCE_DETECT to go off */ |
399 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
||
400 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
||
401 | 1000)) |
||
402 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
||
403 | } |
||
404 | |||
405 | stat = I915_READ(PORT_HOTPLUG_STAT); |
||
406 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
||
407 | ret = true; |
||
408 | |||
409 | /* clear the interrupt we just generated, if any */ |
||
410 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
||
411 | |||
6084 | serge | 412 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
2330 | Serge | 413 | |
414 | return ret; |
||
415 | } |
||
416 | |||
3031 | serge | 417 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
418 | struct i2c_adapter *i2c) |
||
419 | { |
||
420 | struct edid *edid; |
||
421 | |||
422 | edid = drm_get_edid(connector, i2c); |
||
423 | |||
424 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
||
425 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
||
426 | intel_gmbus_force_bit(i2c, true); |
||
427 | edid = drm_get_edid(connector, i2c); |
||
428 | intel_gmbus_force_bit(i2c, false); |
||
429 | } |
||
430 | |||
431 | return edid; |
||
432 | } |
||
433 | |||
434 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
||
435 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
||
436 | struct i2c_adapter *adapter) |
||
437 | { |
||
438 | struct edid *edid; |
||
3243 | Serge | 439 | int ret; |
3031 | serge | 440 | |
441 | edid = intel_crt_get_edid(connector, adapter); |
||
442 | if (!edid) |
||
443 | return 0; |
||
444 | |||
3243 | Serge | 445 | ret = intel_connector_update_modes(connector, edid); |
446 | kfree(edid); |
||
447 | |||
448 | return ret; |
||
3031 | serge | 449 | } |
450 | |||
2330 | Serge | 451 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
452 | { |
||
453 | struct intel_crt *crt = intel_attached_crt(connector); |
||
454 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
||
3031 | serge | 455 | struct edid *edid; |
456 | struct i2c_adapter *i2c; |
||
2330 | Serge | 457 | |
3031 | serge | 458 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 459 | |
4104 | Serge | 460 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 461 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 462 | |
3031 | serge | 463 | if (edid) { |
464 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
||
465 | |||
2330 | Serge | 466 | /* |
467 | * This may be a DVI-I connector with a shared DDC |
||
468 | * link between analog and digital outputs, so we |
||
469 | * have to check the EDID input spec of the attached device. |
||
470 | */ |
||
471 | if (!is_digital) { |
||
472 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
||
6937 | serge | 473 | return true; |
474 | } |
||
475 | |||
7144 | serge | 476 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
5060 | serge | 477 | } else { |
3031 | serge | 478 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
5060 | serge | 479 | } |
2330 | Serge | 480 | |
3031 | serge | 481 | kfree(edid); |
482 | |||
6937 | serge | 483 | return false; |
2330 | Serge | 484 | } |
485 | |||
486 | static enum drm_connector_status |
||
7144 | serge | 487 | intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) |
2330 | Serge | 488 | { |
489 | struct drm_device *dev = crt->base.base.dev; |
||
490 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
491 | uint32_t save_bclrpat; |
||
492 | uint32_t save_vtotal; |
||
493 | uint32_t vtotal, vactive; |
||
494 | uint32_t vsample; |
||
495 | uint32_t vblank, vblank_start, vblank_end; |
||
496 | uint32_t dsl; |
||
6937 | serge | 497 | i915_reg_t bclrpat_reg, vtotal_reg, |
498 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; |
||
2330 | Serge | 499 | uint8_t st00; |
500 | enum drm_connector_status status; |
||
501 | |||
502 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
503 | |||
504 | bclrpat_reg = BCLRPAT(pipe); |
||
505 | vtotal_reg = VTOTAL(pipe); |
||
506 | vblank_reg = VBLANK(pipe); |
||
507 | vsync_reg = VSYNC(pipe); |
||
508 | pipeconf_reg = PIPECONF(pipe); |
||
509 | pipe_dsl_reg = PIPEDSL(pipe); |
||
510 | |||
511 | save_bclrpat = I915_READ(bclrpat_reg); |
||
512 | save_vtotal = I915_READ(vtotal_reg); |
||
513 | vblank = I915_READ(vblank_reg); |
||
514 | |||
515 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
516 | vactive = (save_vtotal & 0x7ff) + 1; |
||
517 | |||
518 | vblank_start = (vblank & 0xfff) + 1; |
||
519 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
520 | |||
521 | /* Set the border color to purple. */ |
||
522 | I915_WRITE(bclrpat_reg, 0x500050); |
||
523 | |||
524 | if (!IS_GEN2(dev)) { |
||
525 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
526 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
527 | POSTING_READ(pipeconf_reg); |
||
528 | /* Wait for next Vblank to substitue |
||
529 | * border color for Color info */ |
||
530 | intel_wait_for_vblank(dev, pipe); |
||
6937 | serge | 531 | st00 = I915_READ8(_VGA_MSR_WRITE); |
2330 | Serge | 532 | status = ((st00 & (1 << 4)) != 0) ? |
533 | connector_status_connected : |
||
534 | connector_status_disconnected; |
||
535 | |||
536 | I915_WRITE(pipeconf_reg, pipeconf); |
||
537 | } else { |
||
538 | bool restore_vblank = false; |
||
539 | int count, detect; |
||
540 | |||
541 | /* |
||
542 | * If there isn't any border, add some. |
||
543 | * Yes, this will flicker |
||
544 | */ |
||
545 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
546 | uint32_t vsync = I915_READ(vsync_reg); |
||
547 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
548 | |||
549 | vblank_start = vsync_start; |
||
550 | I915_WRITE(vblank_reg, |
||
551 | (vblank_start - 1) | |
||
552 | ((vblank_end - 1) << 16)); |
||
553 | restore_vblank = true; |
||
554 | } |
||
555 | /* sample in the vertical border, selecting the larger one */ |
||
556 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
557 | vsample = (vblank_start + vactive) >> 1; |
||
558 | else |
||
559 | vsample = (vtotal + vblank_end) >> 1; |
||
560 | |||
561 | /* |
||
562 | * Wait for the border to be displayed |
||
563 | */ |
||
564 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
565 | ; |
||
566 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
567 | ; |
||
568 | /* |
||
569 | * Watch ST00 for an entire scanline |
||
570 | */ |
||
571 | detect = 0; |
||
572 | count = 0; |
||
573 | do { |
||
574 | count++; |
||
575 | /* Read the ST00 VGA status register */ |
||
6937 | serge | 576 | st00 = I915_READ8(_VGA_MSR_WRITE); |
2330 | Serge | 577 | if (st00 & (1 << 4)) |
578 | detect++; |
||
579 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
580 | |||
581 | /* restore vblank if necessary */ |
||
582 | if (restore_vblank) |
||
583 | I915_WRITE(vblank_reg, vblank); |
||
584 | /* |
||
585 | * If more than 3/4 of the scanline detected a monitor, |
||
586 | * then it is assumed to be present. This works even on i830, |
||
587 | * where there isn't any way to force the border color across |
||
588 | * the screen |
||
589 | */ |
||
590 | status = detect * 4 > count * 3 ? |
||
591 | connector_status_connected : |
||
592 | connector_status_disconnected; |
||
593 | } |
||
594 | |||
595 | /* Restore previous settings */ |
||
596 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
597 | |||
598 | return status; |
||
599 | } |
||
600 | |||
601 | static enum drm_connector_status |
||
602 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
603 | { |
||
604 | struct drm_device *dev = connector->dev; |
||
5060 | serge | 605 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 606 | struct intel_crt *crt = intel_attached_crt(connector); |
5060 | serge | 607 | struct intel_encoder *intel_encoder = &crt->base; |
608 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 609 | enum drm_connector_status status; |
3031 | serge | 610 | struct intel_load_detect_pipe tmp; |
5060 | serge | 611 | struct drm_modeset_acquire_ctx ctx; |
2330 | Serge | 612 | |
4104 | Serge | 613 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
5060 | serge | 614 | connector->base.id, connector->name, |
4104 | Serge | 615 | force); |
616 | |||
5060 | serge | 617 | power_domain = intel_display_port_power_domain(intel_encoder); |
618 | intel_display_power_get(dev_priv, power_domain); |
||
619 | |||
2330 | Serge | 620 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 621 | /* We can not rely on the HPD pin always being correctly wired |
622 | * up, for example many KVM do not pass it through, and so |
||
623 | * only trust an assertion that the monitor is connected. |
||
624 | */ |
||
2330 | Serge | 625 | if (intel_crt_detect_hotplug(connector)) { |
626 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
5060 | serge | 627 | status = connector_status_connected; |
628 | goto out; |
||
3031 | serge | 629 | } else |
2330 | Serge | 630 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
631 | } |
||
632 | |||
5060 | serge | 633 | if (intel_crt_detect_ddc(connector)) { |
634 | status = connector_status_connected; |
||
635 | goto out; |
||
636 | } |
||
2330 | Serge | 637 | |
3031 | serge | 638 | /* Load detection is broken on HPD capable machines. Whoever wants a |
639 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
640 | * to have the right resistors for HP detection) needs to fix this up. |
||
641 | * For now just bail out. */ |
||
6084 | serge | 642 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
5060 | serge | 643 | status = connector_status_disconnected; |
644 | goto out; |
||
645 | } |
||
3031 | serge | 646 | |
5060 | serge | 647 | if (!force) { |
648 | status = connector->status; |
||
649 | goto out; |
||
650 | } |
||
2330 | Serge | 651 | |
5060 | serge | 652 | drm_modeset_acquire_init(&ctx, 0); |
653 | |||
2330 | Serge | 654 | /* for pre-945g platforms use load detect */ |
5060 | serge | 655 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
656 | if (intel_crt_detect_ddc(connector)) |
||
657 | status = connector_status_connected; |
||
6084 | serge | 658 | else if (INTEL_INFO(dev)->gen < 4) |
7144 | serge | 659 | status = intel_crt_load_detect(crt, |
660 | to_intel_crtc(connector->state->crtc)->pipe); |
||
5060 | serge | 661 | else |
6084 | serge | 662 | status = connector_status_unknown; |
663 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
||
5060 | serge | 664 | } else |
665 | status = connector_status_unknown; |
||
2330 | Serge | 666 | |
5060 | serge | 667 | drm_modeset_drop_locks(&ctx); |
668 | drm_modeset_acquire_fini(&ctx); |
||
669 | |||
670 | out: |
||
671 | intel_display_power_put(dev_priv, power_domain); |
||
2330 | Serge | 672 | return status; |
673 | } |
||
674 | |||
675 | static void intel_crt_destroy(struct drm_connector *connector) |
||
676 | { |
||
677 | drm_connector_cleanup(connector); |
||
678 | kfree(connector); |
||
679 | } |
||
680 | |||
681 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
682 | { |
||
683 | struct drm_device *dev = connector->dev; |
||
684 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 685 | struct intel_crt *crt = intel_attached_crt(connector); |
686 | struct intel_encoder *intel_encoder = &crt->base; |
||
687 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 688 | int ret; |
3031 | serge | 689 | struct i2c_adapter *i2c; |
2330 | Serge | 690 | |
5060 | serge | 691 | power_domain = intel_display_port_power_domain(intel_encoder); |
692 | intel_display_power_get(dev_priv, power_domain); |
||
693 | |||
4104 | Serge | 694 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 695 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 696 | if (ret || !IS_G4X(dev)) |
5060 | serge | 697 | goto out; |
2330 | Serge | 698 | |
699 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
6084 | serge | 700 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
5060 | serge | 701 | ret = intel_crt_ddc_get_modes(connector, i2c); |
702 | |||
703 | out: |
||
704 | intel_display_power_put(dev_priv, power_domain); |
||
705 | |||
706 | return ret; |
||
2330 | Serge | 707 | } |
708 | |||
709 | static int intel_crt_set_property(struct drm_connector *connector, |
||
710 | struct drm_property *property, |
||
711 | uint64_t value) |
||
712 | { |
||
713 | return 0; |
||
714 | } |
||
715 | |||
716 | static void intel_crt_reset(struct drm_connector *connector) |
||
717 | { |
||
718 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 719 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 720 | struct intel_crt *crt = intel_attached_crt(connector); |
721 | |||
4104 | Serge | 722 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 723 | u32 adpa; |
724 | |||
3480 | Serge | 725 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 726 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
727 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 728 | I915_WRITE(crt->adpa_reg, adpa); |
729 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 730 | |
5354 | serge | 731 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
2330 | Serge | 732 | crt->force_hotplug_required = 1; |
3243 | Serge | 733 | } |
734 | |||
2330 | Serge | 735 | } |
736 | |||
737 | /* |
||
738 | * Routines for controlling stuff on the analog port |
||
739 | */ |
||
740 | |||
741 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
742 | .reset = intel_crt_reset, |
||
6084 | serge | 743 | .dpms = drm_atomic_helper_connector_dpms, |
2330 | Serge | 744 | .detect = intel_crt_detect, |
745 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
746 | .destroy = intel_crt_destroy, |
||
747 | .set_property = intel_crt_set_property, |
||
6084 | serge | 748 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
749 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
||
750 | .atomic_get_property = intel_connector_atomic_get_property, |
||
2330 | Serge | 751 | }; |
752 | |||
753 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
754 | .mode_valid = intel_crt_mode_valid, |
||
755 | .get_modes = intel_crt_get_modes, |
||
756 | .best_encoder = intel_best_encoder, |
||
757 | }; |
||
758 | |||
759 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
760 | .destroy = intel_encoder_destroy, |
||
761 | }; |
||
762 | |||
5097 | serge | 763 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
764 | { |
||
765 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
||
766 | return 1; |
||
767 | } |
||
768 | |||
769 | static const struct dmi_system_id intel_no_crt[] = { |
||
770 | { |
||
771 | .callback = intel_no_crt_dmi_callback, |
||
772 | .ident = "ACER ZGB", |
||
773 | .matches = { |
||
774 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
||
775 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
||
776 | }, |
||
777 | }, |
||
778 | { |
||
779 | .callback = intel_no_crt_dmi_callback, |
||
780 | .ident = "DELL XPS 8700", |
||
781 | .matches = { |
||
782 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
783 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
||
784 | }, |
||
785 | }, |
||
786 | { } |
||
787 | }; |
||
788 | |||
2330 | Serge | 789 | void intel_crt_init(struct drm_device *dev) |
790 | { |
||
791 | struct drm_connector *connector; |
||
792 | struct intel_crt *crt; |
||
793 | struct intel_connector *intel_connector; |
||
794 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6937 | serge | 795 | i915_reg_t adpa_reg; |
796 | u32 adpa; |
||
2330 | Serge | 797 | |
5097 | serge | 798 | /* Skip machines without VGA that falsely report hotplug events */ |
799 | if (dmi_check_system(intel_no_crt)) |
||
800 | return; |
||
801 | |||
6937 | serge | 802 | if (HAS_PCH_SPLIT(dev)) |
803 | adpa_reg = PCH_ADPA; |
||
804 | else if (IS_VALLEYVIEW(dev)) |
||
805 | adpa_reg = VLV_ADPA; |
||
806 | else |
||
807 | adpa_reg = ADPA; |
||
808 | |||
809 | adpa = I915_READ(adpa_reg); |
||
810 | if ((adpa & ADPA_DAC_ENABLE) == 0) { |
||
811 | /* |
||
812 | * On some machines (some IVB at least) CRT can be |
||
813 | * fused off, but there's no known fuse bit to |
||
814 | * indicate that. On these machine the ADPA register |
||
815 | * works normally, except the DAC enable bit won't |
||
816 | * take. So the only way to tell is attempt to enable |
||
817 | * it and see what happens. |
||
818 | */ |
||
819 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | |
||
820 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
||
821 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) |
||
822 | return; |
||
823 | I915_WRITE(adpa_reg, adpa); |
||
824 | } |
||
825 | |||
2330 | Serge | 826 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
827 | if (!crt) |
||
828 | return; |
||
829 | |||
6084 | serge | 830 | intel_connector = intel_connector_alloc(); |
2330 | Serge | 831 | if (!intel_connector) { |
832 | kfree(crt); |
||
833 | return; |
||
834 | } |
||
835 | |||
836 | connector = &intel_connector->base; |
||
3480 | Serge | 837 | crt->connector = intel_connector; |
2330 | Serge | 838 | drm_connector_init(dev, &intel_connector->base, |
839 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
840 | |||
841 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
6937 | serge | 842 | DRM_MODE_ENCODER_DAC, NULL); |
2330 | Serge | 843 | |
844 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
845 | |||
846 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
5060 | serge | 847 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
3243 | Serge | 848 | if (IS_I830(dev)) |
3031 | serge | 849 | crt->base.crtc_mask = (1 << 0); |
850 | else |
||
851 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
852 | |||
853 | if (IS_GEN2(dev)) |
||
854 | connector->interlace_allowed = 0; |
||
855 | else |
||
6084 | serge | 856 | connector->interlace_allowed = 1; |
2330 | Serge | 857 | connector->doublescan_allowed = 0; |
858 | |||
6937 | serge | 859 | crt->adpa_reg = adpa_reg; |
3031 | serge | 860 | |
3746 | Serge | 861 | crt->base.compute_config = intel_crt_compute_config; |
6937 | serge | 862 | if (HAS_PCH_SPLIT(dev)) { |
6084 | serge | 863 | crt->base.disable = pch_disable_crt; |
864 | crt->base.post_disable = pch_post_disable_crt; |
||
865 | } else { |
||
866 | crt->base.disable = intel_disable_crt; |
||
867 | } |
||
3031 | serge | 868 | crt->base.enable = intel_enable_crt; |
3746 | Serge | 869 | if (I915_HAS_HOTPLUG(dev)) |
870 | crt->base.hpd_pin = HPD_CRT; |
||
4560 | Serge | 871 | if (HAS_DDI(dev)) { |
872 | crt->base.get_config = hsw_crt_get_config; |
||
3243 | Serge | 873 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
4560 | Serge | 874 | } else { |
875 | crt->base.get_config = intel_crt_get_config; |
||
6084 | serge | 876 | crt->base.get_hw_state = intel_crt_get_hw_state; |
4560 | Serge | 877 | } |
3031 | serge | 878 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 879 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 880 | |
2330 | Serge | 881 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
882 | |||
5060 | serge | 883 | drm_connector_register(connector); |
2330 | Serge | 884 | |
3746 | Serge | 885 | if (!I915_HAS_HOTPLUG(dev)) |
886 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 887 | |
888 | /* |
||
889 | * Configure the automatic hotplug detection stuff |
||
890 | */ |
||
891 | crt->force_hotplug_required = 0; |
||
892 | |||
3243 | Serge | 893 | /* |
3480 | Serge | 894 | * TODO: find a proper way to discover whether we need to set the the |
895 | * polarity and link reversal bits or not, instead of relying on the |
||
896 | * BIOS. |
||
3243 | Serge | 897 | */ |
3480 | Serge | 898 | if (HAS_PCH_LPT(dev)) { |
899 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
900 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
901 | |||
6084 | serge | 902 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3480 | Serge | 903 | } |
5060 | serge | 904 | |
905 | intel_crt_reset(connector); |
||
2330 | Serge | 906 | }><>><>><>><>><>><>>><>=>><>=>><>>>> |