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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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2330 | Serge | 33 | #include "intel_drv.h" |
3031 | serge | 34 | #include |
2330 | Serge | 35 | #include "i915_drv.h" |
36 | |||
37 | /* Here's the desired hotplug mode */ |
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38 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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39 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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40 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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41 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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42 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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43 | ADPA_CRT_HOTPLUG_ENABLE) |
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44 | |||
45 | struct intel_crt { |
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46 | struct intel_encoder base; |
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3480 | Serge | 47 | /* DPMS state is stored in the connector, which we need in the |
48 | * encoder's enable/disable callbacks */ |
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49 | struct intel_connector *connector; |
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2330 | Serge | 50 | bool force_hotplug_required; |
3031 | serge | 51 | u32 adpa_reg; |
2330 | Serge | 52 | }; |
53 | |||
4104 | Serge | 54 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 55 | { |
4104 | Serge | 56 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 57 | } |
58 | |||
4104 | Serge | 59 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 60 | { |
4104 | Serge | 61 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 62 | } |
63 | |||
64 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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65 | enum pipe *pipe) |
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66 | { |
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67 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 68 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 69 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
5060 | serge | 70 | enum intel_display_power_domain power_domain; |
3031 | serge | 71 | u32 tmp; |
2330 | Serge | 72 | |
5060 | serge | 73 | power_domain = intel_display_port_power_domain(encoder); |
74 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
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75 | return false; |
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76 | |||
3031 | serge | 77 | tmp = I915_READ(crt->adpa_reg); |
78 | |||
79 | if (!(tmp & ADPA_DAC_ENABLE)) |
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80 | return false; |
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81 | |||
82 | if (HAS_PCH_CPT(dev)) |
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83 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 84 | else |
3031 | serge | 85 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 86 | |
3031 | serge | 87 | return true; |
88 | } |
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89 | |||
4280 | Serge | 90 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
4104 | Serge | 91 | { |
92 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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93 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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94 | u32 tmp, flags = 0; |
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95 | |||
96 | tmp = I915_READ(crt->adpa_reg); |
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97 | |||
98 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
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99 | flags |= DRM_MODE_FLAG_PHSYNC; |
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100 | else |
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101 | flags |= DRM_MODE_FLAG_NHSYNC; |
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102 | |||
103 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
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104 | flags |= DRM_MODE_FLAG_PVSYNC; |
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105 | else |
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106 | flags |= DRM_MODE_FLAG_NVSYNC; |
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107 | |||
4280 | Serge | 108 | return flags; |
4104 | Serge | 109 | } |
110 | |||
4280 | Serge | 111 | static void intel_crt_get_config(struct intel_encoder *encoder, |
112 | struct intel_crtc_config *pipe_config) |
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113 | { |
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4560 | Serge | 114 | struct drm_device *dev = encoder->base.dev; |
115 | int dotclock; |
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116 | |||
4280 | Serge | 117 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4560 | Serge | 118 | |
119 | dotclock = pipe_config->port_clock; |
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120 | |||
121 | if (HAS_PCH_SPLIT(dev)) |
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122 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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123 | |||
124 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
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4280 | Serge | 125 | } |
126 | |||
127 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
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128 | struct intel_crtc_config *pipe_config) |
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129 | { |
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130 | intel_ddi_get_config(encoder, pipe_config); |
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131 | |||
132 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
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133 | DRM_MODE_FLAG_NHSYNC | |
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134 | DRM_MODE_FLAG_PVSYNC | |
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135 | DRM_MODE_FLAG_NVSYNC); |
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136 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
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137 | } |
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138 | |||
5060 | serge | 139 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
140 | { |
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141 | struct drm_device *dev = encoder->base.dev; |
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142 | struct drm_i915_private *dev_priv = dev->dev_private; |
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143 | |||
144 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); |
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145 | I915_WRITE(SPLL_CTL, |
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146 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); |
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147 | POSTING_READ(SPLL_CTL); |
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148 | udelay(20); |
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149 | } |
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150 | |||
3031 | serge | 151 | /* Note: The caller is required to filter out dpms modes not supported by the |
152 | * platform. */ |
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153 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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154 | { |
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155 | struct drm_device *dev = encoder->base.dev; |
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156 | struct drm_i915_private *dev_priv = dev->dev_private; |
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157 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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5060 | serge | 158 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
159 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
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160 | u32 adpa; |
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3031 | serge | 161 | |
5060 | serge | 162 | if (INTEL_INFO(dev)->gen >= 5) |
163 | adpa = ADPA_HOTPLUG_BITS; |
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164 | else |
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165 | adpa = 0; |
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3031 | serge | 166 | |
5060 | serge | 167 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
168 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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170 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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171 | |||
172 | /* For CPT allow 3 pipe config, for others just use A or B */ |
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173 | if (HAS_PCH_LPT(dev)) |
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174 | ; /* Those bits don't exist here */ |
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175 | else if (HAS_PCH_CPT(dev)) |
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176 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
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177 | else if (crtc->pipe == 0) |
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178 | adpa |= ADPA_PIPE_A_SELECT; |
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179 | else |
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180 | adpa |= ADPA_PIPE_B_SELECT; |
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181 | |||
182 | if (!HAS_PCH_SPLIT(dev)) |
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183 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
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184 | |||
2342 | Serge | 185 | switch (mode) { |
2330 | Serge | 186 | case DRM_MODE_DPMS_ON: |
5060 | serge | 187 | adpa |= ADPA_DAC_ENABLE; |
2330 | Serge | 188 | break; |
189 | case DRM_MODE_DPMS_STANDBY: |
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5060 | serge | 190 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
2330 | Serge | 191 | break; |
192 | case DRM_MODE_DPMS_SUSPEND: |
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5060 | serge | 193 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 194 | break; |
195 | case DRM_MODE_DPMS_OFF: |
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5060 | serge | 196 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
2330 | Serge | 197 | break; |
198 | } |
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199 | |||
5060 | serge | 200 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 201 | } |
202 | |||
3480 | Serge | 203 | static void intel_disable_crt(struct intel_encoder *encoder) |
204 | { |
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205 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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206 | } |
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207 | |||
5060 | serge | 208 | |
209 | static void hsw_crt_post_disable(struct intel_encoder *encoder) |
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210 | { |
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211 | struct drm_device *dev = encoder->base.dev; |
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212 | struct drm_i915_private *dev_priv = dev->dev_private; |
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213 | uint32_t val; |
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214 | |||
215 | DRM_DEBUG_KMS("Disabling SPLL\n"); |
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216 | val = I915_READ(SPLL_CTL); |
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217 | WARN_ON(!(val & SPLL_PLL_ENABLE)); |
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218 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
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219 | POSTING_READ(SPLL_CTL); |
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220 | } |
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221 | |||
3480 | Serge | 222 | static void intel_enable_crt(struct intel_encoder *encoder) |
223 | { |
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224 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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225 | |||
226 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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227 | } |
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228 | |||
4104 | Serge | 229 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 230 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
231 | { |
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232 | struct drm_device *dev = connector->dev; |
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233 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
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234 | struct drm_crtc *crtc; |
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235 | int old_dpms; |
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236 | |||
237 | /* PCH platforms and VLV only support on/off. */ |
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3120 | serge | 238 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
3031 | serge | 239 | mode = DRM_MODE_DPMS_OFF; |
240 | |||
241 | if (mode == connector->dpms) |
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242 | return; |
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243 | |||
244 | old_dpms = connector->dpms; |
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245 | connector->dpms = mode; |
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246 | |||
247 | /* Only need to change hw state when actually enabled */ |
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248 | crtc = encoder->base.crtc; |
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249 | if (!crtc) { |
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250 | encoder->connectors_active = false; |
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251 | return; |
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252 | } |
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253 | |||
254 | /* We need the pipe to run for anything but OFF. */ |
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255 | if (mode == DRM_MODE_DPMS_OFF) |
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256 | encoder->connectors_active = false; |
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257 | else |
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258 | encoder->connectors_active = true; |
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259 | |||
4104 | Serge | 260 | /* We call connector dpms manually below in case pipe dpms doesn't |
261 | * change due to cloning. */ |
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3031 | serge | 262 | if (mode < old_dpms) { |
263 | /* From off to on, enable the pipe first. */ |
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264 | intel_crtc_update_dpms(crtc); |
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265 | |||
266 | intel_crt_set_dpms(encoder, mode); |
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267 | } else { |
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268 | intel_crt_set_dpms(encoder, mode); |
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269 | |||
270 | intel_crtc_update_dpms(crtc); |
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271 | } |
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272 | |||
273 | intel_modeset_check_state(connector->dev); |
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274 | } |
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275 | |||
4560 | Serge | 276 | static enum drm_mode_status |
277 | intel_crt_mode_valid(struct drm_connector *connector, |
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5060 | serge | 278 | struct drm_display_mode *mode) |
2330 | Serge | 279 | { |
280 | struct drm_device *dev = connector->dev; |
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281 | |||
282 | int max_clock = 0; |
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283 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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284 | return MODE_NO_DBLESCAN; |
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285 | |||
286 | if (mode->clock < 25000) |
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287 | return MODE_CLOCK_LOW; |
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288 | |||
289 | if (IS_GEN2(dev)) |
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290 | max_clock = 350000; |
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291 | else |
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292 | max_clock = 400000; |
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293 | if (mode->clock > max_clock) |
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294 | return MODE_CLOCK_HIGH; |
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295 | |||
3243 | Serge | 296 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
297 | if (HAS_PCH_LPT(dev) && |
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298 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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299 | return MODE_CLOCK_HIGH; |
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300 | |||
2330 | Serge | 301 | return MODE_OK; |
302 | } |
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303 | |||
3746 | Serge | 304 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
305 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 306 | { |
3746 | Serge | 307 | struct drm_device *dev = encoder->base.dev; |
308 | |||
309 | if (HAS_PCH_SPLIT(dev)) |
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310 | pipe_config->has_pch_encoder = true; |
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311 | |||
4104 | Serge | 312 | /* LPT FDI RX only supports 8bpc. */ |
313 | if (HAS_PCH_LPT(dev)) |
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314 | pipe_config->pipe_bpp = 24; |
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315 | |||
5060 | serge | 316 | /* FDI must always be 2.7 GHz */ |
317 | if (HAS_DDI(dev)) { |
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318 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
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319 | pipe_config->port_clock = 135000 * 2; |
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320 | } |
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321 | |||
2330 | Serge | 322 | return true; |
323 | } |
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324 | |||
325 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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326 | { |
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327 | struct drm_device *dev = connector->dev; |
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328 | struct intel_crt *crt = intel_attached_crt(connector); |
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329 | struct drm_i915_private *dev_priv = dev->dev_private; |
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330 | u32 adpa; |
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331 | bool ret; |
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332 | |||
333 | /* The first time through, trigger an explicit detection cycle */ |
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334 | if (crt->force_hotplug_required) { |
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335 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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336 | u32 save_adpa; |
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337 | |||
338 | crt->force_hotplug_required = 0; |
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339 | |||
3480 | Serge | 340 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 341 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
342 | |||
343 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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344 | if (turn_off_dac) |
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345 | adpa &= ~ADPA_DAC_ENABLE; |
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346 | |||
3480 | Serge | 347 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 348 | |
3480 | Serge | 349 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 350 | 1000)) |
351 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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352 | |||
353 | if (turn_off_dac) { |
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3480 | Serge | 354 | I915_WRITE(crt->adpa_reg, save_adpa); |
355 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 356 | } |
357 | } |
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358 | |||
359 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 360 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 361 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
362 | ret = true; |
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363 | else |
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364 | ret = false; |
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365 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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366 | |||
367 | return ret; |
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368 | } |
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369 | |||
3031 | serge | 370 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
371 | { |
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372 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 373 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 374 | struct drm_i915_private *dev_priv = dev->dev_private; |
375 | u32 adpa; |
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376 | bool ret; |
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377 | u32 save_adpa; |
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378 | |||
3480 | Serge | 379 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 380 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
381 | |||
382 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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383 | |||
3480 | Serge | 384 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 385 | |
3480 | Serge | 386 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 387 | 1000)) { |
388 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 389 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 390 | } |
391 | |||
392 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 393 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 394 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
395 | ret = true; |
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396 | else |
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397 | ret = false; |
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398 | |||
399 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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400 | |||
401 | return ret; |
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402 | } |
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403 | |||
2330 | Serge | 404 | /** |
405 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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406 | * |
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407 | * Not for i915G/i915GM |
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408 | * |
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409 | * \return true if CRT is connected. |
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410 | * \return false if CRT is disconnected. |
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411 | */ |
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412 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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413 | { |
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414 | struct drm_device *dev = connector->dev; |
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415 | struct drm_i915_private *dev_priv = dev->dev_private; |
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416 | u32 hotplug_en, orig, stat; |
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417 | bool ret = false; |
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418 | int i, tries = 0; |
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419 | |||
420 | if (HAS_PCH_SPLIT(dev)) |
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421 | return intel_ironlake_crt_detect_hotplug(connector); |
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422 | |||
3031 | serge | 423 | if (IS_VALLEYVIEW(dev)) |
424 | return valleyview_crt_detect_hotplug(connector); |
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425 | |||
2330 | Serge | 426 | /* |
427 | * On 4 series desktop, CRT detect sequence need to be done twice |
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428 | * to get a reliable result. |
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429 | */ |
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430 | |||
431 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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432 | tries = 2; |
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433 | else |
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434 | tries = 1; |
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435 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
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436 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
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437 | |||
438 | for (i = 0; i < tries ; i++) { |
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439 | /* turn on the FORCE_DETECT */ |
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440 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
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441 | /* wait for FORCE_DETECT to go off */ |
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442 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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443 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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444 | 1000)) |
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445 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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446 | } |
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447 | |||
448 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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449 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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450 | ret = true; |
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451 | |||
452 | /* clear the interrupt we just generated, if any */ |
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453 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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454 | |||
455 | /* and put the bits back */ |
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456 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
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457 | |||
458 | return ret; |
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459 | } |
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460 | |||
3031 | serge | 461 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
462 | struct i2c_adapter *i2c) |
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463 | { |
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464 | struct edid *edid; |
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465 | |||
466 | edid = drm_get_edid(connector, i2c); |
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467 | |||
468 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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469 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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470 | intel_gmbus_force_bit(i2c, true); |
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471 | edid = drm_get_edid(connector, i2c); |
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472 | intel_gmbus_force_bit(i2c, false); |
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473 | } |
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474 | |||
475 | return edid; |
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476 | } |
||
477 | |||
478 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
||
479 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
||
480 | struct i2c_adapter *adapter) |
||
481 | { |
||
482 | struct edid *edid; |
||
3243 | Serge | 483 | int ret; |
3031 | serge | 484 | |
485 | edid = intel_crt_get_edid(connector, adapter); |
||
486 | if (!edid) |
||
487 | return 0; |
||
488 | |||
3243 | Serge | 489 | ret = intel_connector_update_modes(connector, edid); |
490 | kfree(edid); |
||
491 | |||
492 | return ret; |
||
3031 | serge | 493 | } |
494 | |||
2330 | Serge | 495 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
496 | { |
||
497 | struct intel_crt *crt = intel_attached_crt(connector); |
||
498 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
||
3031 | serge | 499 | struct edid *edid; |
500 | struct i2c_adapter *i2c; |
||
2330 | Serge | 501 | |
3031 | serge | 502 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 503 | |
4104 | Serge | 504 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 505 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 506 | |
3031 | serge | 507 | if (edid) { |
508 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
||
509 | |||
2330 | Serge | 510 | /* |
511 | * This may be a DVI-I connector with a shared DDC |
||
512 | * link between analog and digital outputs, so we |
||
513 | * have to check the EDID input spec of the attached device. |
||
514 | */ |
||
515 | if (!is_digital) { |
||
516 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
||
517 | return true; |
||
3031 | serge | 518 | } |
519 | |||
520 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
||
5060 | serge | 521 | } else { |
3031 | serge | 522 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
5060 | serge | 523 | } |
2330 | Serge | 524 | |
3031 | serge | 525 | kfree(edid); |
526 | |||
2330 | Serge | 527 | return false; |
528 | } |
||
529 | |||
530 | static enum drm_connector_status |
||
531 | intel_crt_load_detect(struct intel_crt *crt) |
||
532 | { |
||
533 | struct drm_device *dev = crt->base.base.dev; |
||
534 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
535 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
||
536 | uint32_t save_bclrpat; |
||
537 | uint32_t save_vtotal; |
||
538 | uint32_t vtotal, vactive; |
||
539 | uint32_t vsample; |
||
540 | uint32_t vblank, vblank_start, vblank_end; |
||
541 | uint32_t dsl; |
||
542 | uint32_t bclrpat_reg; |
||
543 | uint32_t vtotal_reg; |
||
544 | uint32_t vblank_reg; |
||
545 | uint32_t vsync_reg; |
||
546 | uint32_t pipeconf_reg; |
||
547 | uint32_t pipe_dsl_reg; |
||
548 | uint8_t st00; |
||
549 | enum drm_connector_status status; |
||
550 | |||
551 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
552 | |||
553 | bclrpat_reg = BCLRPAT(pipe); |
||
554 | vtotal_reg = VTOTAL(pipe); |
||
555 | vblank_reg = VBLANK(pipe); |
||
556 | vsync_reg = VSYNC(pipe); |
||
557 | pipeconf_reg = PIPECONF(pipe); |
||
558 | pipe_dsl_reg = PIPEDSL(pipe); |
||
559 | |||
560 | save_bclrpat = I915_READ(bclrpat_reg); |
||
561 | save_vtotal = I915_READ(vtotal_reg); |
||
562 | vblank = I915_READ(vblank_reg); |
||
563 | |||
564 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
565 | vactive = (save_vtotal & 0x7ff) + 1; |
||
566 | |||
567 | vblank_start = (vblank & 0xfff) + 1; |
||
568 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
569 | |||
570 | /* Set the border color to purple. */ |
||
571 | I915_WRITE(bclrpat_reg, 0x500050); |
||
572 | |||
573 | if (!IS_GEN2(dev)) { |
||
574 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
575 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
576 | POSTING_READ(pipeconf_reg); |
||
577 | /* Wait for next Vblank to substitue |
||
578 | * border color for Color info */ |
||
579 | intel_wait_for_vblank(dev, pipe); |
||
580 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
581 | status = ((st00 & (1 << 4)) != 0) ? |
||
582 | connector_status_connected : |
||
583 | connector_status_disconnected; |
||
584 | |||
585 | I915_WRITE(pipeconf_reg, pipeconf); |
||
586 | } else { |
||
587 | bool restore_vblank = false; |
||
588 | int count, detect; |
||
589 | |||
590 | /* |
||
591 | * If there isn't any border, add some. |
||
592 | * Yes, this will flicker |
||
593 | */ |
||
594 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
595 | uint32_t vsync = I915_READ(vsync_reg); |
||
596 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
597 | |||
598 | vblank_start = vsync_start; |
||
599 | I915_WRITE(vblank_reg, |
||
600 | (vblank_start - 1) | |
||
601 | ((vblank_end - 1) << 16)); |
||
602 | restore_vblank = true; |
||
603 | } |
||
604 | /* sample in the vertical border, selecting the larger one */ |
||
605 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
606 | vsample = (vblank_start + vactive) >> 1; |
||
607 | else |
||
608 | vsample = (vtotal + vblank_end) >> 1; |
||
609 | |||
610 | /* |
||
611 | * Wait for the border to be displayed |
||
612 | */ |
||
613 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
614 | ; |
||
615 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
616 | ; |
||
617 | /* |
||
618 | * Watch ST00 for an entire scanline |
||
619 | */ |
||
620 | detect = 0; |
||
621 | count = 0; |
||
622 | do { |
||
623 | count++; |
||
624 | /* Read the ST00 VGA status register */ |
||
625 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
626 | if (st00 & (1 << 4)) |
||
627 | detect++; |
||
628 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
629 | |||
630 | /* restore vblank if necessary */ |
||
631 | if (restore_vblank) |
||
632 | I915_WRITE(vblank_reg, vblank); |
||
633 | /* |
||
634 | * If more than 3/4 of the scanline detected a monitor, |
||
635 | * then it is assumed to be present. This works even on i830, |
||
636 | * where there isn't any way to force the border color across |
||
637 | * the screen |
||
638 | */ |
||
639 | status = detect * 4 > count * 3 ? |
||
640 | connector_status_connected : |
||
641 | connector_status_disconnected; |
||
642 | } |
||
643 | |||
644 | /* Restore previous settings */ |
||
645 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
646 | |||
647 | return status; |
||
648 | } |
||
649 | |||
650 | static enum drm_connector_status |
||
651 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
652 | { |
||
653 | struct drm_device *dev = connector->dev; |
||
5060 | serge | 654 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 655 | struct intel_crt *crt = intel_attached_crt(connector); |
5060 | serge | 656 | struct intel_encoder *intel_encoder = &crt->base; |
657 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 658 | enum drm_connector_status status; |
3031 | serge | 659 | struct intel_load_detect_pipe tmp; |
5060 | serge | 660 | struct drm_modeset_acquire_ctx ctx; |
2330 | Serge | 661 | |
4104 | Serge | 662 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
5060 | serge | 663 | connector->base.id, connector->name, |
4104 | Serge | 664 | force); |
665 | |||
5060 | serge | 666 | power_domain = intel_display_port_power_domain(intel_encoder); |
667 | intel_display_power_get(dev_priv, power_domain); |
||
668 | |||
2330 | Serge | 669 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 670 | /* We can not rely on the HPD pin always being correctly wired |
671 | * up, for example many KVM do not pass it through, and so |
||
672 | * only trust an assertion that the monitor is connected. |
||
673 | */ |
||
2330 | Serge | 674 | if (intel_crt_detect_hotplug(connector)) { |
675 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
5060 | serge | 676 | status = connector_status_connected; |
677 | goto out; |
||
3031 | serge | 678 | } else |
2330 | Serge | 679 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
680 | } |
||
681 | |||
5060 | serge | 682 | if (intel_crt_detect_ddc(connector)) { |
683 | status = connector_status_connected; |
||
684 | goto out; |
||
685 | } |
||
2330 | Serge | 686 | |
3031 | serge | 687 | /* Load detection is broken on HPD capable machines. Whoever wants a |
688 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
689 | * to have the right resistors for HP detection) needs to fix this up. |
||
690 | * For now just bail out. */ |
||
5060 | serge | 691 | if (I915_HAS_HOTPLUG(dev)) { |
692 | status = connector_status_disconnected; |
||
693 | goto out; |
||
694 | } |
||
3031 | serge | 695 | |
5060 | serge | 696 | if (!force) { |
697 | status = connector->status; |
||
698 | goto out; |
||
699 | } |
||
2330 | Serge | 700 | |
5060 | serge | 701 | drm_modeset_acquire_init(&ctx, 0); |
702 | |||
2330 | Serge | 703 | /* for pre-945g platforms use load detect */ |
5060 | serge | 704 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
705 | if (intel_crt_detect_ddc(connector)) |
||
706 | status = connector_status_connected; |
||
707 | else |
||
708 | status = intel_crt_load_detect(crt); |
||
3031 | serge | 709 | intel_release_load_detect_pipe(connector, &tmp); |
5060 | serge | 710 | } else |
711 | status = connector_status_unknown; |
||
2330 | Serge | 712 | |
5060 | serge | 713 | drm_modeset_drop_locks(&ctx); |
714 | drm_modeset_acquire_fini(&ctx); |
||
715 | |||
716 | out: |
||
717 | intel_display_power_put(dev_priv, power_domain); |
||
2330 | Serge | 718 | return status; |
719 | } |
||
720 | |||
721 | static void intel_crt_destroy(struct drm_connector *connector) |
||
722 | { |
||
723 | drm_connector_cleanup(connector); |
||
724 | kfree(connector); |
||
725 | } |
||
726 | |||
727 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
728 | { |
||
729 | struct drm_device *dev = connector->dev; |
||
730 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
5060 | serge | 731 | struct intel_crt *crt = intel_attached_crt(connector); |
732 | struct intel_encoder *intel_encoder = &crt->base; |
||
733 | enum intel_display_power_domain power_domain; |
||
2330 | Serge | 734 | int ret; |
3031 | serge | 735 | struct i2c_adapter *i2c; |
2330 | Serge | 736 | |
5060 | serge | 737 | power_domain = intel_display_port_power_domain(intel_encoder); |
738 | intel_display_power_get(dev_priv, power_domain); |
||
739 | |||
4104 | Serge | 740 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 741 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 742 | if (ret || !IS_G4X(dev)) |
5060 | serge | 743 | goto out; |
2330 | Serge | 744 | |
745 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
3031 | serge | 746 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
5060 | serge | 747 | ret = intel_crt_ddc_get_modes(connector, i2c); |
748 | |||
749 | out: |
||
750 | intel_display_power_put(dev_priv, power_domain); |
||
751 | |||
752 | return ret; |
||
2330 | Serge | 753 | } |
754 | |||
755 | static int intel_crt_set_property(struct drm_connector *connector, |
||
756 | struct drm_property *property, |
||
757 | uint64_t value) |
||
758 | { |
||
759 | return 0; |
||
760 | } |
||
761 | |||
762 | static void intel_crt_reset(struct drm_connector *connector) |
||
763 | { |
||
764 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 765 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 766 | struct intel_crt *crt = intel_attached_crt(connector); |
767 | |||
4104 | Serge | 768 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 769 | u32 adpa; |
770 | |||
3480 | Serge | 771 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 772 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
773 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 774 | I915_WRITE(crt->adpa_reg, adpa); |
775 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 776 | |
777 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
||
2330 | Serge | 778 | crt->force_hotplug_required = 1; |
3243 | Serge | 779 | } |
780 | |||
2330 | Serge | 781 | } |
782 | |||
783 | /* |
||
784 | * Routines for controlling stuff on the analog port |
||
785 | */ |
||
786 | |||
787 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
788 | .reset = intel_crt_reset, |
||
3031 | serge | 789 | .dpms = intel_crt_dpms, |
2330 | Serge | 790 | .detect = intel_crt_detect, |
791 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
792 | .destroy = intel_crt_destroy, |
||
793 | .set_property = intel_crt_set_property, |
||
794 | }; |
||
795 | |||
796 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
797 | .mode_valid = intel_crt_mode_valid, |
||
798 | .get_modes = intel_crt_get_modes, |
||
799 | .best_encoder = intel_best_encoder, |
||
800 | }; |
||
801 | |||
802 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
803 | .destroy = intel_encoder_destroy, |
||
804 | }; |
||
805 | |||
806 | void intel_crt_init(struct drm_device *dev) |
||
807 | { |
||
808 | struct drm_connector *connector; |
||
809 | struct intel_crt *crt; |
||
810 | struct intel_connector *intel_connector; |
||
811 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
812 | |||
813 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
||
814 | if (!crt) |
||
815 | return; |
||
816 | |||
4560 | Serge | 817 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
2330 | Serge | 818 | if (!intel_connector) { |
819 | kfree(crt); |
||
820 | return; |
||
821 | } |
||
822 | |||
823 | connector = &intel_connector->base; |
||
3480 | Serge | 824 | crt->connector = intel_connector; |
2330 | Serge | 825 | drm_connector_init(dev, &intel_connector->base, |
826 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
827 | |||
828 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
829 | DRM_MODE_ENCODER_DAC); |
||
830 | |||
831 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
832 | |||
833 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
5060 | serge | 834 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
3243 | Serge | 835 | if (IS_I830(dev)) |
3031 | serge | 836 | crt->base.crtc_mask = (1 << 0); |
837 | else |
||
838 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
839 | |||
840 | if (IS_GEN2(dev)) |
||
841 | connector->interlace_allowed = 0; |
||
842 | else |
||
2330 | Serge | 843 | connector->interlace_allowed = 1; |
844 | connector->doublescan_allowed = 0; |
||
845 | |||
3031 | serge | 846 | if (HAS_PCH_SPLIT(dev)) |
847 | crt->adpa_reg = PCH_ADPA; |
||
848 | else if (IS_VALLEYVIEW(dev)) |
||
849 | crt->adpa_reg = VLV_ADPA; |
||
850 | else |
||
851 | crt->adpa_reg = ADPA; |
||
852 | |||
3746 | Serge | 853 | crt->base.compute_config = intel_crt_compute_config; |
3031 | serge | 854 | crt->base.disable = intel_disable_crt; |
855 | crt->base.enable = intel_enable_crt; |
||
3746 | Serge | 856 | if (I915_HAS_HOTPLUG(dev)) |
857 | crt->base.hpd_pin = HPD_CRT; |
||
4560 | Serge | 858 | if (HAS_DDI(dev)) { |
859 | crt->base.get_config = hsw_crt_get_config; |
||
3243 | Serge | 860 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
5060 | serge | 861 | crt->base.pre_enable = hsw_crt_pre_enable; |
862 | crt->base.post_disable = hsw_crt_post_disable; |
||
4560 | Serge | 863 | } else { |
864 | crt->base.get_config = intel_crt_get_config; |
||
3031 | serge | 865 | crt->base.get_hw_state = intel_crt_get_hw_state; |
4560 | Serge | 866 | } |
3031 | serge | 867 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 868 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 869 | |
2330 | Serge | 870 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
871 | |||
5060 | serge | 872 | drm_connector_register(connector); |
2330 | Serge | 873 | |
3746 | Serge | 874 | if (!I915_HAS_HOTPLUG(dev)) |
875 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 876 | |
877 | /* |
||
878 | * Configure the automatic hotplug detection stuff |
||
879 | */ |
||
880 | crt->force_hotplug_required = 0; |
||
881 | |||
3243 | Serge | 882 | /* |
3480 | Serge | 883 | * TODO: find a proper way to discover whether we need to set the the |
884 | * polarity and link reversal bits or not, instead of relying on the |
||
885 | * BIOS. |
||
3243 | Serge | 886 | */ |
3480 | Serge | 887 | if (HAS_PCH_LPT(dev)) { |
888 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
889 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
890 | |||
891 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
||
892 | } |
||
5060 | serge | 893 | |
894 | intel_crt_reset(connector); |
||
2330 | Serge | 895 | }><>><>><>><>><>><>><>=>><>=>><>>>> |