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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | */ |
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26 | |||
27 | #include |
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28 | #include |
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3031 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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2330 | Serge | 33 | #include "intel_drv.h" |
3031 | serge | 34 | #include |
2330 | Serge | 35 | #include "i915_drv.h" |
36 | |||
37 | /* Here's the desired hotplug mode */ |
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38 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
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39 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
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40 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
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41 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
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42 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
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43 | ADPA_CRT_HOTPLUG_ENABLE) |
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44 | |||
45 | struct intel_crt { |
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46 | struct intel_encoder base; |
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3480 | Serge | 47 | /* DPMS state is stored in the connector, which we need in the |
48 | * encoder's enable/disable callbacks */ |
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49 | struct intel_connector *connector; |
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2330 | Serge | 50 | bool force_hotplug_required; |
3031 | serge | 51 | u32 adpa_reg; |
2330 | Serge | 52 | }; |
53 | |||
4104 | Serge | 54 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
2330 | Serge | 55 | { |
4104 | Serge | 56 | return container_of(encoder, struct intel_crt, base); |
2330 | Serge | 57 | } |
58 | |||
4104 | Serge | 59 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
2330 | Serge | 60 | { |
4104 | Serge | 61 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
3031 | serge | 62 | } |
63 | |||
64 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
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65 | enum pipe *pipe) |
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66 | { |
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67 | struct drm_device *dev = encoder->base.dev; |
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2330 | Serge | 68 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 69 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
70 | u32 tmp; |
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2330 | Serge | 71 | |
3031 | serge | 72 | tmp = I915_READ(crt->adpa_reg); |
73 | |||
74 | if (!(tmp & ADPA_DAC_ENABLE)) |
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75 | return false; |
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76 | |||
77 | if (HAS_PCH_CPT(dev)) |
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78 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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2330 | Serge | 79 | else |
3031 | serge | 80 | *pipe = PORT_TO_PIPE(tmp); |
2330 | Serge | 81 | |
3031 | serge | 82 | return true; |
83 | } |
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84 | |||
4280 | Serge | 85 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
4104 | Serge | 86 | { |
87 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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88 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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89 | u32 tmp, flags = 0; |
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90 | |||
91 | tmp = I915_READ(crt->adpa_reg); |
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92 | |||
93 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
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94 | flags |= DRM_MODE_FLAG_PHSYNC; |
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95 | else |
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96 | flags |= DRM_MODE_FLAG_NHSYNC; |
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97 | |||
98 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
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99 | flags |= DRM_MODE_FLAG_PVSYNC; |
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100 | else |
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101 | flags |= DRM_MODE_FLAG_NVSYNC; |
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102 | |||
4280 | Serge | 103 | return flags; |
4104 | Serge | 104 | } |
105 | |||
4280 | Serge | 106 | static void intel_crt_get_config(struct intel_encoder *encoder, |
107 | struct intel_crtc_config *pipe_config) |
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108 | { |
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4560 | Serge | 109 | struct drm_device *dev = encoder->base.dev; |
110 | int dotclock; |
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111 | |||
4280 | Serge | 112 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
4560 | Serge | 113 | |
114 | dotclock = pipe_config->port_clock; |
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115 | |||
116 | if (HAS_PCH_SPLIT(dev)) |
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117 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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118 | |||
119 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
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4280 | Serge | 120 | } |
121 | |||
122 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
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123 | struct intel_crtc_config *pipe_config) |
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124 | { |
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125 | intel_ddi_get_config(encoder, pipe_config); |
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126 | |||
127 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
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128 | DRM_MODE_FLAG_NHSYNC | |
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129 | DRM_MODE_FLAG_PVSYNC | |
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130 | DRM_MODE_FLAG_NVSYNC); |
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131 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
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132 | } |
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133 | |||
3031 | serge | 134 | /* Note: The caller is required to filter out dpms modes not supported by the |
135 | * platform. */ |
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136 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
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137 | { |
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138 | struct drm_device *dev = encoder->base.dev; |
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139 | struct drm_i915_private *dev_priv = dev->dev_private; |
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140 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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141 | u32 temp; |
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142 | |||
143 | temp = I915_READ(crt->adpa_reg); |
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144 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
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145 | temp &= ~ADPA_DAC_ENABLE; |
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146 | |||
2342 | Serge | 147 | switch (mode) { |
2330 | Serge | 148 | case DRM_MODE_DPMS_ON: |
149 | temp |= ADPA_DAC_ENABLE; |
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150 | break; |
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151 | case DRM_MODE_DPMS_STANDBY: |
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152 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
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153 | break; |
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154 | case DRM_MODE_DPMS_SUSPEND: |
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155 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
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156 | break; |
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157 | case DRM_MODE_DPMS_OFF: |
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158 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
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159 | break; |
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160 | } |
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161 | |||
3031 | serge | 162 | I915_WRITE(crt->adpa_reg, temp); |
2330 | Serge | 163 | } |
164 | |||
3480 | Serge | 165 | static void intel_disable_crt(struct intel_encoder *encoder) |
166 | { |
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167 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
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168 | } |
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169 | |||
170 | static void intel_enable_crt(struct intel_encoder *encoder) |
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171 | { |
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172 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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173 | |||
174 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
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175 | } |
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176 | |||
4104 | Serge | 177 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
3031 | serge | 178 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
179 | { |
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180 | struct drm_device *dev = connector->dev; |
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181 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
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182 | struct drm_crtc *crtc; |
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183 | int old_dpms; |
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184 | |||
185 | /* PCH platforms and VLV only support on/off. */ |
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3120 | serge | 186 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
3031 | serge | 187 | mode = DRM_MODE_DPMS_OFF; |
188 | |||
189 | if (mode == connector->dpms) |
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190 | return; |
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191 | |||
192 | old_dpms = connector->dpms; |
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193 | connector->dpms = mode; |
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194 | |||
195 | /* Only need to change hw state when actually enabled */ |
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196 | crtc = encoder->base.crtc; |
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197 | if (!crtc) { |
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198 | encoder->connectors_active = false; |
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199 | return; |
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200 | } |
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201 | |||
202 | /* We need the pipe to run for anything but OFF. */ |
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203 | if (mode == DRM_MODE_DPMS_OFF) |
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204 | encoder->connectors_active = false; |
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205 | else |
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206 | encoder->connectors_active = true; |
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207 | |||
4104 | Serge | 208 | /* We call connector dpms manually below in case pipe dpms doesn't |
209 | * change due to cloning. */ |
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3031 | serge | 210 | if (mode < old_dpms) { |
211 | /* From off to on, enable the pipe first. */ |
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212 | intel_crtc_update_dpms(crtc); |
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213 | |||
214 | intel_crt_set_dpms(encoder, mode); |
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215 | } else { |
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216 | intel_crt_set_dpms(encoder, mode); |
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217 | |||
218 | intel_crtc_update_dpms(crtc); |
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219 | } |
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220 | |||
221 | intel_modeset_check_state(connector->dev); |
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222 | } |
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223 | |||
4560 | Serge | 224 | static enum drm_mode_status |
225 | intel_crt_mode_valid(struct drm_connector *connector, |
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2330 | Serge | 226 | struct drm_display_mode *mode) |
227 | { |
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228 | struct drm_device *dev = connector->dev; |
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229 | |||
230 | int max_clock = 0; |
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231 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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232 | return MODE_NO_DBLESCAN; |
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233 | |||
234 | if (mode->clock < 25000) |
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235 | return MODE_CLOCK_LOW; |
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236 | |||
237 | if (IS_GEN2(dev)) |
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238 | max_clock = 350000; |
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239 | else |
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240 | max_clock = 400000; |
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241 | if (mode->clock > max_clock) |
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242 | return MODE_CLOCK_HIGH; |
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243 | |||
3243 | Serge | 244 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
245 | if (HAS_PCH_LPT(dev) && |
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246 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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247 | return MODE_CLOCK_HIGH; |
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248 | |||
2330 | Serge | 249 | return MODE_OK; |
250 | } |
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251 | |||
3746 | Serge | 252 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
253 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 254 | { |
3746 | Serge | 255 | struct drm_device *dev = encoder->base.dev; |
256 | |||
257 | if (HAS_PCH_SPLIT(dev)) |
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258 | pipe_config->has_pch_encoder = true; |
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259 | |||
4104 | Serge | 260 | /* LPT FDI RX only supports 8bpc. */ |
261 | if (HAS_PCH_LPT(dev)) |
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262 | pipe_config->pipe_bpp = 24; |
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263 | |||
2330 | Serge | 264 | return true; |
265 | } |
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266 | |||
4104 | Serge | 267 | static void intel_crt_mode_set(struct intel_encoder *encoder) |
2330 | Serge | 268 | { |
269 | |||
4104 | Serge | 270 | struct drm_device *dev = encoder->base.dev; |
271 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
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272 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
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2330 | Serge | 273 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | Serge | 274 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
3031 | serge | 275 | u32 adpa; |
2330 | Serge | 276 | |
4560 | Serge | 277 | if (INTEL_INFO(dev)->gen >= 5) |
2330 | Serge | 278 | adpa = ADPA_HOTPLUG_BITS; |
3243 | Serge | 279 | else |
280 | adpa = 0; |
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281 | |||
2330 | Serge | 282 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
283 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
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284 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
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285 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
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286 | |||
2342 | Serge | 287 | /* For CPT allow 3 pipe config, for others just use A or B */ |
3243 | Serge | 288 | if (HAS_PCH_LPT(dev)) |
289 | ; /* Those bits don't exist here */ |
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290 | else if (HAS_PCH_CPT(dev)) |
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4104 | Serge | 291 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
292 | else if (crtc->pipe == 0) |
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2330 | Serge | 293 | adpa |= ADPA_PIPE_A_SELECT; |
294 | else |
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295 | adpa |= ADPA_PIPE_B_SELECT; |
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296 | |||
297 | if (!HAS_PCH_SPLIT(dev)) |
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4104 | Serge | 298 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
2330 | Serge | 299 | |
3031 | serge | 300 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 301 | } |
302 | |||
303 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
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304 | { |
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305 | struct drm_device *dev = connector->dev; |
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306 | struct intel_crt *crt = intel_attached_crt(connector); |
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307 | struct drm_i915_private *dev_priv = dev->dev_private; |
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308 | u32 adpa; |
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309 | bool ret; |
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310 | |||
311 | /* The first time through, trigger an explicit detection cycle */ |
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312 | if (crt->force_hotplug_required) { |
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313 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
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314 | u32 save_adpa; |
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315 | |||
316 | crt->force_hotplug_required = 0; |
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317 | |||
3480 | Serge | 318 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 319 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
320 | |||
321 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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322 | if (turn_off_dac) |
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323 | adpa &= ~ADPA_DAC_ENABLE; |
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324 | |||
3480 | Serge | 325 | I915_WRITE(crt->adpa_reg, adpa); |
2330 | Serge | 326 | |
3480 | Serge | 327 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
2330 | Serge | 328 | 1000)) |
329 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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330 | |||
331 | if (turn_off_dac) { |
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3480 | Serge | 332 | I915_WRITE(crt->adpa_reg, save_adpa); |
333 | POSTING_READ(crt->adpa_reg); |
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2330 | Serge | 334 | } |
335 | } |
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336 | |||
337 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 338 | adpa = I915_READ(crt->adpa_reg); |
2330 | Serge | 339 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
340 | ret = true; |
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341 | else |
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342 | ret = false; |
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343 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
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344 | |||
345 | return ret; |
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346 | } |
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347 | |||
3031 | serge | 348 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
349 | { |
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350 | struct drm_device *dev = connector->dev; |
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3480 | Serge | 351 | struct intel_crt *crt = intel_attached_crt(connector); |
3031 | serge | 352 | struct drm_i915_private *dev_priv = dev->dev_private; |
353 | u32 adpa; |
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354 | bool ret; |
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355 | u32 save_adpa; |
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356 | |||
3480 | Serge | 357 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 358 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
359 | |||
360 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
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361 | |||
3480 | Serge | 362 | I915_WRITE(crt->adpa_reg, adpa); |
3031 | serge | 363 | |
3480 | Serge | 364 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
3031 | serge | 365 | 1000)) { |
366 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
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3480 | Serge | 367 | I915_WRITE(crt->adpa_reg, save_adpa); |
3031 | serge | 368 | } |
369 | |||
370 | /* Check the status to see if both blue and green are on now */ |
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3480 | Serge | 371 | adpa = I915_READ(crt->adpa_reg); |
3031 | serge | 372 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
373 | ret = true; |
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374 | else |
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375 | ret = false; |
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376 | |||
377 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
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378 | |||
379 | return ret; |
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380 | } |
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381 | |||
2330 | Serge | 382 | /** |
383 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
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384 | * |
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385 | * Not for i915G/i915GM |
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386 | * |
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387 | * \return true if CRT is connected. |
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388 | * \return false if CRT is disconnected. |
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389 | */ |
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390 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
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391 | { |
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392 | struct drm_device *dev = connector->dev; |
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393 | struct drm_i915_private *dev_priv = dev->dev_private; |
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394 | u32 hotplug_en, orig, stat; |
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395 | bool ret = false; |
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396 | int i, tries = 0; |
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397 | |||
398 | if (HAS_PCH_SPLIT(dev)) |
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399 | return intel_ironlake_crt_detect_hotplug(connector); |
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400 | |||
3031 | serge | 401 | if (IS_VALLEYVIEW(dev)) |
402 | return valleyview_crt_detect_hotplug(connector); |
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403 | |||
2330 | Serge | 404 | /* |
405 | * On 4 series desktop, CRT detect sequence need to be done twice |
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406 | * to get a reliable result. |
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407 | */ |
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408 | |||
409 | if (IS_G4X(dev) && !IS_GM45(dev)) |
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410 | tries = 2; |
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411 | else |
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412 | tries = 1; |
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413 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
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414 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
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415 | |||
416 | for (i = 0; i < tries ; i++) { |
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417 | /* turn on the FORCE_DETECT */ |
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418 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
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419 | /* wait for FORCE_DETECT to go off */ |
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420 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
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421 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
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422 | 1000)) |
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423 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
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424 | } |
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425 | |||
426 | stat = I915_READ(PORT_HOTPLUG_STAT); |
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427 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
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428 | ret = true; |
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429 | |||
430 | /* clear the interrupt we just generated, if any */ |
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431 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
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432 | |||
433 | /* and put the bits back */ |
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434 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
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435 | |||
436 | return ret; |
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437 | } |
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438 | |||
3031 | serge | 439 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
440 | struct i2c_adapter *i2c) |
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441 | { |
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442 | struct edid *edid; |
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443 | |||
444 | edid = drm_get_edid(connector, i2c); |
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445 | |||
446 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
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447 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
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448 | intel_gmbus_force_bit(i2c, true); |
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449 | edid = drm_get_edid(connector, i2c); |
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450 | intel_gmbus_force_bit(i2c, false); |
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451 | } |
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452 | |||
453 | return edid; |
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454 | } |
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455 | |||
456 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
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457 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
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458 | struct i2c_adapter *adapter) |
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459 | { |
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460 | struct edid *edid; |
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3243 | Serge | 461 | int ret; |
3031 | serge | 462 | |
463 | edid = intel_crt_get_edid(connector, adapter); |
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464 | if (!edid) |
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465 | return 0; |
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466 | |||
3243 | Serge | 467 | ret = intel_connector_update_modes(connector, edid); |
468 | kfree(edid); |
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469 | |||
470 | return ret; |
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3031 | serge | 471 | } |
472 | |||
2330 | Serge | 473 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
474 | { |
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475 | struct intel_crt *crt = intel_attached_crt(connector); |
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476 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
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3031 | serge | 477 | struct edid *edid; |
478 | struct i2c_adapter *i2c; |
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2330 | Serge | 479 | |
3031 | serge | 480 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
2330 | Serge | 481 | |
4104 | Serge | 482 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 483 | edid = intel_crt_get_edid(connector, i2c); |
2330 | Serge | 484 | |
3031 | serge | 485 | if (edid) { |
486 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
||
487 | |||
2330 | Serge | 488 | /* |
489 | * This may be a DVI-I connector with a shared DDC |
||
490 | * link between analog and digital outputs, so we |
||
491 | * have to check the EDID input spec of the attached device. |
||
492 | */ |
||
493 | if (!is_digital) { |
||
494 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
||
495 | return true; |
||
3031 | serge | 496 | } |
497 | |||
498 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
||
2330 | Serge | 499 | } else { |
3031 | serge | 500 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
2330 | Serge | 501 | } |
502 | |||
3031 | serge | 503 | kfree(edid); |
504 | |||
2330 | Serge | 505 | return false; |
506 | } |
||
507 | |||
508 | static enum drm_connector_status |
||
509 | intel_crt_load_detect(struct intel_crt *crt) |
||
510 | { |
||
511 | struct drm_device *dev = crt->base.base.dev; |
||
512 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
513 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
||
514 | uint32_t save_bclrpat; |
||
515 | uint32_t save_vtotal; |
||
516 | uint32_t vtotal, vactive; |
||
517 | uint32_t vsample; |
||
518 | uint32_t vblank, vblank_start, vblank_end; |
||
519 | uint32_t dsl; |
||
520 | uint32_t bclrpat_reg; |
||
521 | uint32_t vtotal_reg; |
||
522 | uint32_t vblank_reg; |
||
523 | uint32_t vsync_reg; |
||
524 | uint32_t pipeconf_reg; |
||
525 | uint32_t pipe_dsl_reg; |
||
526 | uint8_t st00; |
||
527 | enum drm_connector_status status; |
||
528 | |||
529 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
||
530 | |||
531 | bclrpat_reg = BCLRPAT(pipe); |
||
532 | vtotal_reg = VTOTAL(pipe); |
||
533 | vblank_reg = VBLANK(pipe); |
||
534 | vsync_reg = VSYNC(pipe); |
||
535 | pipeconf_reg = PIPECONF(pipe); |
||
536 | pipe_dsl_reg = PIPEDSL(pipe); |
||
537 | |||
538 | save_bclrpat = I915_READ(bclrpat_reg); |
||
539 | save_vtotal = I915_READ(vtotal_reg); |
||
540 | vblank = I915_READ(vblank_reg); |
||
541 | |||
542 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
||
543 | vactive = (save_vtotal & 0x7ff) + 1; |
||
544 | |||
545 | vblank_start = (vblank & 0xfff) + 1; |
||
546 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
||
547 | |||
548 | /* Set the border color to purple. */ |
||
549 | I915_WRITE(bclrpat_reg, 0x500050); |
||
550 | |||
551 | if (!IS_GEN2(dev)) { |
||
552 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
||
553 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
||
554 | POSTING_READ(pipeconf_reg); |
||
555 | /* Wait for next Vblank to substitue |
||
556 | * border color for Color info */ |
||
557 | intel_wait_for_vblank(dev, pipe); |
||
558 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
559 | status = ((st00 & (1 << 4)) != 0) ? |
||
560 | connector_status_connected : |
||
561 | connector_status_disconnected; |
||
562 | |||
563 | I915_WRITE(pipeconf_reg, pipeconf); |
||
564 | } else { |
||
565 | bool restore_vblank = false; |
||
566 | int count, detect; |
||
567 | |||
568 | /* |
||
569 | * If there isn't any border, add some. |
||
570 | * Yes, this will flicker |
||
571 | */ |
||
572 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
||
573 | uint32_t vsync = I915_READ(vsync_reg); |
||
574 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
||
575 | |||
576 | vblank_start = vsync_start; |
||
577 | I915_WRITE(vblank_reg, |
||
578 | (vblank_start - 1) | |
||
579 | ((vblank_end - 1) << 16)); |
||
580 | restore_vblank = true; |
||
581 | } |
||
582 | /* sample in the vertical border, selecting the larger one */ |
||
583 | if (vblank_start - vactive >= vtotal - vblank_end) |
||
584 | vsample = (vblank_start + vactive) >> 1; |
||
585 | else |
||
586 | vsample = (vtotal + vblank_end) >> 1; |
||
587 | |||
588 | /* |
||
589 | * Wait for the border to be displayed |
||
590 | */ |
||
591 | while (I915_READ(pipe_dsl_reg) >= vactive) |
||
592 | ; |
||
593 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
||
594 | ; |
||
595 | /* |
||
596 | * Watch ST00 for an entire scanline |
||
597 | */ |
||
598 | detect = 0; |
||
599 | count = 0; |
||
600 | do { |
||
601 | count++; |
||
602 | /* Read the ST00 VGA status register */ |
||
603 | st00 = I915_READ8(VGA_MSR_WRITE); |
||
604 | if (st00 & (1 << 4)) |
||
605 | detect++; |
||
606 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
||
607 | |||
608 | /* restore vblank if necessary */ |
||
609 | if (restore_vblank) |
||
610 | I915_WRITE(vblank_reg, vblank); |
||
611 | /* |
||
612 | * If more than 3/4 of the scanline detected a monitor, |
||
613 | * then it is assumed to be present. This works even on i830, |
||
614 | * where there isn't any way to force the border color across |
||
615 | * the screen |
||
616 | */ |
||
617 | status = detect * 4 > count * 3 ? |
||
618 | connector_status_connected : |
||
619 | connector_status_disconnected; |
||
620 | } |
||
621 | |||
622 | /* Restore previous settings */ |
||
623 | I915_WRITE(bclrpat_reg, save_bclrpat); |
||
624 | |||
625 | return status; |
||
626 | } |
||
627 | |||
628 | static enum drm_connector_status |
||
629 | intel_crt_detect(struct drm_connector *connector, bool force) |
||
630 | { |
||
631 | struct drm_device *dev = connector->dev; |
||
632 | struct intel_crt *crt = intel_attached_crt(connector); |
||
633 | enum drm_connector_status status; |
||
3031 | serge | 634 | struct intel_load_detect_pipe tmp; |
2330 | Serge | 635 | |
4104 | Serge | 636 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
637 | connector->base.id, drm_get_connector_name(connector), |
||
638 | force); |
||
639 | |||
2330 | Serge | 640 | if (I915_HAS_HOTPLUG(dev)) { |
3031 | serge | 641 | /* We can not rely on the HPD pin always being correctly wired |
642 | * up, for example many KVM do not pass it through, and so |
||
643 | * only trust an assertion that the monitor is connected. |
||
644 | */ |
||
2330 | Serge | 645 | if (intel_crt_detect_hotplug(connector)) { |
646 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
||
647 | return connector_status_connected; |
||
3031 | serge | 648 | } else |
2330 | Serge | 649 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
650 | } |
||
651 | |||
652 | if (intel_crt_detect_ddc(connector)) |
||
653 | return connector_status_connected; |
||
654 | |||
3031 | serge | 655 | /* Load detection is broken on HPD capable machines. Whoever wants a |
656 | * broken monitor (without edid) to work behind a broken kvm (that fails |
||
657 | * to have the right resistors for HP detection) needs to fix this up. |
||
658 | * For now just bail out. */ |
||
659 | if (I915_HAS_HOTPLUG(dev)) |
||
660 | return connector_status_disconnected; |
||
661 | |||
2330 | Serge | 662 | if (!force) |
663 | return connector->status; |
||
664 | |||
665 | /* for pre-945g platforms use load detect */ |
||
3031 | serge | 666 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
2330 | Serge | 667 | if (intel_crt_detect_ddc(connector)) |
668 | status = connector_status_connected; |
||
669 | else |
||
670 | status = intel_crt_load_detect(crt); |
||
3031 | serge | 671 | intel_release_load_detect_pipe(connector, &tmp); |
2330 | Serge | 672 | } else |
673 | status = connector_status_unknown; |
||
674 | |||
675 | return status; |
||
676 | } |
||
677 | |||
678 | static void intel_crt_destroy(struct drm_connector *connector) |
||
679 | { |
||
680 | drm_connector_cleanup(connector); |
||
681 | kfree(connector); |
||
682 | } |
||
683 | |||
684 | static int intel_crt_get_modes(struct drm_connector *connector) |
||
685 | { |
||
686 | struct drm_device *dev = connector->dev; |
||
687 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
688 | int ret; |
||
3031 | serge | 689 | struct i2c_adapter *i2c; |
2330 | Serge | 690 | |
4104 | Serge | 691 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
3031 | serge | 692 | ret = intel_crt_ddc_get_modes(connector, i2c); |
2330 | Serge | 693 | if (ret || !IS_G4X(dev)) |
694 | return ret; |
||
695 | |||
696 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
||
3031 | serge | 697 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
698 | return intel_crt_ddc_get_modes(connector, i2c); |
||
2330 | Serge | 699 | } |
700 | |||
701 | static int intel_crt_set_property(struct drm_connector *connector, |
||
702 | struct drm_property *property, |
||
703 | uint64_t value) |
||
704 | { |
||
705 | return 0; |
||
706 | } |
||
707 | |||
708 | static void intel_crt_reset(struct drm_connector *connector) |
||
709 | { |
||
710 | struct drm_device *dev = connector->dev; |
||
3243 | Serge | 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 712 | struct intel_crt *crt = intel_attached_crt(connector); |
713 | |||
4104 | Serge | 714 | if (INTEL_INFO(dev)->gen >= 5) { |
3243 | Serge | 715 | u32 adpa; |
716 | |||
3480 | Serge | 717 | adpa = I915_READ(crt->adpa_reg); |
3243 | Serge | 718 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
719 | adpa |= ADPA_HOTPLUG_BITS; |
||
3480 | Serge | 720 | I915_WRITE(crt->adpa_reg, adpa); |
721 | POSTING_READ(crt->adpa_reg); |
||
3243 | Serge | 722 | |
723 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
||
2330 | Serge | 724 | crt->force_hotplug_required = 1; |
3243 | Serge | 725 | } |
726 | |||
2330 | Serge | 727 | } |
728 | |||
729 | /* |
||
730 | * Routines for controlling stuff on the analog port |
||
731 | */ |
||
732 | |||
733 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
||
734 | .reset = intel_crt_reset, |
||
3031 | serge | 735 | .dpms = intel_crt_dpms, |
2330 | Serge | 736 | .detect = intel_crt_detect, |
737 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
738 | .destroy = intel_crt_destroy, |
||
739 | .set_property = intel_crt_set_property, |
||
740 | }; |
||
741 | |||
742 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
||
743 | .mode_valid = intel_crt_mode_valid, |
||
744 | .get_modes = intel_crt_get_modes, |
||
745 | .best_encoder = intel_best_encoder, |
||
746 | }; |
||
747 | |||
748 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
||
749 | .destroy = intel_encoder_destroy, |
||
750 | }; |
||
751 | |||
752 | void intel_crt_init(struct drm_device *dev) |
||
753 | { |
||
754 | struct drm_connector *connector; |
||
755 | struct intel_crt *crt; |
||
756 | struct intel_connector *intel_connector; |
||
757 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
758 | |||
759 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
||
760 | if (!crt) |
||
761 | return; |
||
762 | |||
4560 | Serge | 763 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
2330 | Serge | 764 | if (!intel_connector) { |
765 | kfree(crt); |
||
766 | return; |
||
767 | } |
||
768 | |||
769 | connector = &intel_connector->base; |
||
3480 | Serge | 770 | crt->connector = intel_connector; |
2330 | Serge | 771 | drm_connector_init(dev, &intel_connector->base, |
772 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
||
773 | |||
774 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
||
775 | DRM_MODE_ENCODER_DAC); |
||
776 | |||
777 | intel_connector_attach_encoder(intel_connector, &crt->base); |
||
778 | |||
779 | crt->base.type = INTEL_OUTPUT_ANALOG; |
||
3031 | serge | 780 | crt->base.cloneable = true; |
3243 | Serge | 781 | if (IS_I830(dev)) |
3031 | serge | 782 | crt->base.crtc_mask = (1 << 0); |
783 | else |
||
784 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
785 | |||
786 | if (IS_GEN2(dev)) |
||
787 | connector->interlace_allowed = 0; |
||
788 | else |
||
2330 | Serge | 789 | connector->interlace_allowed = 1; |
790 | connector->doublescan_allowed = 0; |
||
791 | |||
3031 | serge | 792 | if (HAS_PCH_SPLIT(dev)) |
793 | crt->adpa_reg = PCH_ADPA; |
||
794 | else if (IS_VALLEYVIEW(dev)) |
||
795 | crt->adpa_reg = VLV_ADPA; |
||
796 | else |
||
797 | crt->adpa_reg = ADPA; |
||
798 | |||
3746 | Serge | 799 | crt->base.compute_config = intel_crt_compute_config; |
4104 | Serge | 800 | crt->base.mode_set = intel_crt_mode_set; |
3031 | serge | 801 | crt->base.disable = intel_disable_crt; |
802 | crt->base.enable = intel_enable_crt; |
||
3746 | Serge | 803 | if (I915_HAS_HOTPLUG(dev)) |
804 | crt->base.hpd_pin = HPD_CRT; |
||
4560 | Serge | 805 | if (HAS_DDI(dev)) { |
806 | crt->base.get_config = hsw_crt_get_config; |
||
3243 | Serge | 807 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
4560 | Serge | 808 | } else { |
809 | crt->base.get_config = intel_crt_get_config; |
||
3031 | serge | 810 | crt->base.get_hw_state = intel_crt_get_hw_state; |
4560 | Serge | 811 | } |
3031 | serge | 812 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
813 | |||
2330 | Serge | 814 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
815 | |||
816 | drm_sysfs_connector_add(connector); |
||
817 | |||
3746 | Serge | 818 | if (!I915_HAS_HOTPLUG(dev)) |
819 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2330 | Serge | 820 | |
821 | /* |
||
822 | * Configure the automatic hotplug detection stuff |
||
823 | */ |
||
824 | crt->force_hotplug_required = 0; |
||
825 | |||
3243 | Serge | 826 | /* |
3480 | Serge | 827 | * TODO: find a proper way to discover whether we need to set the the |
828 | * polarity and link reversal bits or not, instead of relying on the |
||
829 | * BIOS. |
||
3243 | Serge | 830 | */ |
3480 | Serge | 831 | if (HAS_PCH_LPT(dev)) { |
832 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
||
833 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
||
834 | |||
835 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
||
836 | } |
||
2330 | Serge | 837 | }><>><>><>><>><>=>><>=>><>>>> |