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2325 Serge 1
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2
 * All Rights Reserved.
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the
6
 * "Software"), to deal in the Software without restriction, including
7
 * without limitation the rights to use, copy, modify, merge, publish,
8
 * distribute, sub license, and/or sell copies of the Software, and to
9
 * permit persons to whom the Software is furnished to do so, subject to
10
 * the following conditions:
11
 *
12
 * The above copyright notice and this permission notice (including the
13
 * next paragraph) shall be included in all copies or substantial portions
14
 * of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23
 */
24
 
25
#ifndef _I915_REG_H_
26
#define _I915_REG_H_
27
 
6937 serge 28
typedef struct {
29
	uint32_t reg;
30
} i915_reg_t;
31
 
32
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
33
 
34
#define INVALID_MMIO_REG _MMIO(0)
35
 
36
static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
37
{
38
	return reg.reg;
39
}
40
 
41
static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
42
{
43
	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
44
}
45
 
46
static inline bool i915_mmio_reg_valid(i915_reg_t reg)
47
{
48
	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
49
}
50
 
2325 Serge 51
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
6937 serge 52
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
5354 serge 53
#define _PLANE(plane, a, b) _PIPE(plane, a, b)
6937 serge 54
#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
55
#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
56
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
3031 serge 57
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
6937 serge 58
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
5060 serge 59
#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
60
			       (pipe) == PIPE_B ? (b) : (c))
6937 serge 61
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
6084 serge 62
#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
63
			       (port) == PORT_B ? (b) : (c))
6937 serge 64
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
3031 serge 65
 
5354 serge 66
#define _MASKED_FIELD(mask, value) ({					   \
67
	if (__builtin_constant_p(mask))					   \
68
		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
69
	if (__builtin_constant_p(value))				   \
70
		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
71
	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
72
		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
73
				 "Incorrect value for mask");		   \
74
	(mask) << 16 | (value); })
75
#define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
76
#define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
3031 serge 77
 
5354 serge 78
 
79
 
2325 Serge 80
/* PCI config space */
81
 
6084 serge 82
#define HPLLCC	0xc0 /* 85x only */
83
#define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
2325 Serge 84
#define   GC_CLOCK_133_200		(0 << 0)
85
#define   GC_CLOCK_100_200		(1 << 0)
86
#define   GC_CLOCK_100_133		(2 << 0)
6084 serge 87
#define   GC_CLOCK_133_266		(3 << 0)
88
#define   GC_CLOCK_133_200_2		(4 << 0)
89
#define   GC_CLOCK_133_266_2		(5 << 0)
90
#define   GC_CLOCK_166_266		(6 << 0)
91
#define   GC_CLOCK_166_250		(7 << 0)
92
 
2325 Serge 93
#define GCFGC2	0xda
94
#define GCFGC	0xf0 /* 915+ only */
95
#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
96
#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
97
#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
4104 Serge 98
#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
99
#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
100
#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
101
#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
102
#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
103
#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
2325 Serge 104
#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
105
#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
106
#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
107
#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
108
#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
109
#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
110
#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
111
#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
112
#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
113
#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
114
#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
115
#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
116
#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
117
#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
118
#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
119
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
120
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
121
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
122
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
123
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
5354 serge 124
#define GCDGMBUS 0xcc
5060 serge 125
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
2325 Serge 126
 
5060 serge 127
 
2325 Serge 128
/* Graphics reset regs */
5354 serge 129
#define I915_GDRST 0xc0 /* PCI config register */
2325 Serge 130
#define  GRDOM_FULL	(0<<2)
131
#define  GRDOM_RENDER	(1<<2)
132
#define  GRDOM_MEDIA	(3<<2)
3746 Serge 133
#define  GRDOM_MASK	(3<<2)
5354 serge 134
#define  GRDOM_RESET_STATUS (1<<1)
3031 serge 135
#define  GRDOM_RESET_ENABLE (1<<0)
2325 Serge 136
 
6937 serge 137
#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
5060 serge 138
#define  ILK_GRDOM_FULL		(0<<1)
139
#define  ILK_GRDOM_RENDER	(1<<1)
140
#define  ILK_GRDOM_MEDIA	(3<<1)
141
#define  ILK_GRDOM_MASK		(3<<1)
142
#define  ILK_GRDOM_RESET_ENABLE (1<<0)
143
 
6937 serge 144
#define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
2325 Serge 145
#define   GEN6_MBC_SNPCR_SHIFT	21
146
#define   GEN6_MBC_SNPCR_MASK	(3<<21)
147
#define   GEN6_MBC_SNPCR_MAX	(0<<21)
148
#define   GEN6_MBC_SNPCR_MED	(1<<21)
149
#define   GEN6_MBC_SNPCR_LOW	(2<<21)
150
#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
151
 
6937 serge 152
#define VLV_G3DCTL		_MMIO(0x9024)
153
#define VLV_GSCKGCTL		_MMIO(0x9028)
5060 serge 154
 
6937 serge 155
#define GEN6_MBCTL		_MMIO(0x0907c)
3031 serge 156
#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
157
#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
158
#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
159
#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
160
#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
161
 
6937 serge 162
#define GEN6_GDRST	_MMIO(0x941c)
2325 Serge 163
#define  GEN6_GRDOM_FULL		(1 << 0)
164
#define  GEN6_GRDOM_RENDER		(1 << 1)
165
#define  GEN6_GRDOM_MEDIA		(1 << 2)
166
#define  GEN6_GRDOM_BLT			(1 << 3)
167
 
6937 serge 168
#define RING_PP_DIR_BASE(ring)		_MMIO((ring)->mmio_base+0x228)
169
#define RING_PP_DIR_BASE_READ(ring)	_MMIO((ring)->mmio_base+0x518)
170
#define RING_PP_DIR_DCLV(ring)		_MMIO((ring)->mmio_base+0x220)
3031 serge 171
#define   PP_DIR_DCLV_2G		0xffffffff
172
 
6937 serge 173
#define GEN8_RING_PDP_UDW(ring, n)	_MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4)
174
#define GEN8_RING_PDP_LDW(ring, n)	_MMIO((ring)->mmio_base+0x270 + (n) * 8)
4560 Serge 175
 
6937 serge 176
#define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
6084 serge 177
#define   GEN8_RPCS_ENABLE		(1 << 31)
178
#define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
179
#define   GEN8_RPCS_S_CNT_SHIFT		15
180
#define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
181
#define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
182
#define   GEN8_RPCS_SS_CNT_SHIFT	8
183
#define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
184
#define   GEN8_RPCS_EU_MAX_SHIFT	4
185
#define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
186
#define   GEN8_RPCS_EU_MIN_SHIFT	0
187
#define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
188
 
6937 serge 189
#define GAM_ECOCHK			_MMIO(0x4090)
6084 serge 190
#define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
3031 serge 191
#define   ECOCHK_SNB_BIT		(1<<10)
6084 serge 192
#define   ECOCHK_DIS_TLB		(1<<8)
3746 Serge 193
#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
3031 serge 194
#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
195
#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
3746 Serge 196
#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
197
#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
198
#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
199
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
200
#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
3031 serge 201
 
6937 serge 202
#define GAC_ECO_BITS			_MMIO(0x14090)
3746 Serge 203
#define   ECOBITS_SNB_BIT		(1<<13)
3031 serge 204
#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
205
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
206
 
6937 serge 207
#define GAB_CTL				_MMIO(0x24000)
3031 serge 208
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
209
 
6937 serge 210
#define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
6084 serge 211
#define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
212
#define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
213
#define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
214
#define GEN6_STOLEN_RESERVED_1M		(0 << 4)
215
#define GEN6_STOLEN_RESERVED_512K	(1 << 4)
216
#define GEN6_STOLEN_RESERVED_256K	(2 << 4)
217
#define GEN6_STOLEN_RESERVED_128K	(3 << 4)
218
#define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
219
#define GEN7_STOLEN_RESERVED_1M		(0 << 5)
220
#define GEN7_STOLEN_RESERVED_256K	(1 << 5)
221
#define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
222
#define GEN8_STOLEN_RESERVED_1M		(0 << 7)
223
#define GEN8_STOLEN_RESERVED_2M		(1 << 7)
224
#define GEN8_STOLEN_RESERVED_4M		(2 << 7)
225
#define GEN8_STOLEN_RESERVED_8M		(3 << 7)
5354 serge 226
 
2325 Serge 227
/* VGA stuff */
228
 
229
#define VGA_ST01_MDA 0x3ba
230
#define VGA_ST01_CGA 0x3da
231
 
6937 serge 232
#define _VGA_MSR_WRITE _MMIO(0x3c2)
2325 Serge 233
#define VGA_MSR_WRITE 0x3c2
234
#define VGA_MSR_READ 0x3cc
235
#define   VGA_MSR_MEM_EN (1<<1)
236
#define   VGA_MSR_CGA_MODE (1<<0)
237
 
4104 Serge 238
#define VGA_SR_INDEX 0x3c4
3480 Serge 239
#define SR01			1
4104 Serge 240
#define VGA_SR_DATA 0x3c5
2325 Serge 241
 
242
#define VGA_AR_INDEX 0x3c0
243
#define   VGA_AR_VID_EN (1<<5)
244
#define VGA_AR_DATA_WRITE 0x3c0
245
#define VGA_AR_DATA_READ 0x3c1
246
 
247
#define VGA_GR_INDEX 0x3ce
248
#define VGA_GR_DATA 0x3cf
249
/* GR05 */
250
#define   VGA_GR_MEM_READ_MODE_SHIFT 3
251
#define     VGA_GR_MEM_READ_MODE_PLANE 1
252
/* GR06 */
253
#define   VGA_GR_MEM_MODE_MASK 0xc
254
#define   VGA_GR_MEM_MODE_SHIFT 2
255
#define   VGA_GR_MEM_A0000_AFFFF 0
256
#define   VGA_GR_MEM_A0000_BFFFF 1
257
#define   VGA_GR_MEM_B0000_B7FFF 2
258
#define   VGA_GR_MEM_B0000_BFFFF 3
259
 
260
#define VGA_DACMASK 0x3c6
261
#define VGA_DACRX 0x3c7
262
#define VGA_DACWX 0x3c8
263
#define VGA_DACDATA 0x3c9
264
 
265
#define VGA_CR_INDEX_MDA 0x3b4
266
#define VGA_CR_DATA_MDA 0x3b5
267
#define VGA_CR_INDEX_CGA 0x3d4
268
#define VGA_CR_DATA_CGA 0x3d5
269
 
270
/*
5060 serge 271
 * Instruction field definitions used by the command parser
272
 */
273
#define INSTR_CLIENT_SHIFT      29
274
#define INSTR_CLIENT_MASK       0xE0000000
275
#define   INSTR_MI_CLIENT       0x0
276
#define   INSTR_BC_CLIENT       0x2
277
#define   INSTR_RC_CLIENT       0x3
278
#define INSTR_SUBCLIENT_SHIFT   27
279
#define INSTR_SUBCLIENT_MASK    0x18000000
280
#define   INSTR_MEDIA_SUBCLIENT 0x2
6084 serge 281
#define INSTR_26_TO_24_MASK	0x7000000
282
#define   INSTR_26_TO_24_SHIFT	24
5060 serge 283
 
284
/*
2325 Serge 285
 * Memory interface instructions used by the kernel
286
 */
287
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
5060 serge 288
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
289
#define  MI_GLOBAL_GTT    (1<<22)
2325 Serge 290
 
291
#define MI_NOOP			MI_INSTR(0, 0)
292
#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
293
#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
294
#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
295
#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
296
#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
297
#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
298
#define MI_FLUSH		MI_INSTR(0x04, 0)
299
#define   MI_READ_FLUSH		(1 << 0)
300
#define   MI_EXE_FLUSH		(1 << 1)
301
#define   MI_NO_WRITE_FLUSH	(1 << 2)
302
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
303
#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
304
#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
4560 Serge 305
#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
306
#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
307
#define   MI_ARB_ENABLE			(1<<0)
308
#define   MI_ARB_DISABLE		(0<<0)
2325 Serge 309
#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
310
#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
311
#define   MI_SUSPEND_FLUSH_EN	(1<<0)
6084 serge 312
#define MI_SET_APPID		MI_INSTR(0x0e, 0)
2342 Serge 313
#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
2325 Serge 314
#define   MI_OVERLAY_CONTINUE	(0x0<<21)
315
#define   MI_OVERLAY_ON		(0x1<<21)
316
#define   MI_OVERLAY_OFF	(0x2<<21)
317
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
318
#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
319
#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
320
#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
3031 serge 321
/* IVB has funny definitions for which plane to flip. */
322
#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
323
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
324
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
325
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
326
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
327
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
5354 serge 328
/* SKL ones */
329
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
330
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
331
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
332
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
333
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
334
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
335
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
336
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
337
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
5060 serge 338
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
4560 Serge 339
#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
340
#define   MI_SEMAPHORE_UPDATE	    (1<<21)
341
#define   MI_SEMAPHORE_COMPARE	    (1<<20)
342
#define   MI_SEMAPHORE_REGISTER	    (1<<18)
343
#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
344
#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
345
#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
346
#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
347
#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
348
#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
349
#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
350
#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
351
#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
352
#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
353
#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
354
#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
6084 serge 355
#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
5060 serge 356
#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
2325 Serge 357
#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
358
#define   MI_MM_SPACE_GTT		(1<<8)
359
#define   MI_MM_SPACE_PHYSICAL		(0<<8)
360
#define   MI_SAVE_EXT_STATE_EN		(1<<3)
361
#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
362
#define   MI_FORCE_RESTORE		(1<<1)
363
#define   MI_RESTORE_INHIBIT		(1<<0)
6084 serge 364
#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
365
#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
5060 serge 366
#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
367
#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
368
#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
369
#define   MI_SEMAPHORE_POLL		(1<<15)
370
#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
2325 Serge 371
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
6084 serge 372
#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
373
#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
374
#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
2325 Serge 375
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
376
#define   MI_STORE_DWORD_INDEX_SHIFT 2
377
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
378
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
379
 *   simply ignores the register load under certain conditions.
380
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
381
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
382
 */
5060 serge 383
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
5354 serge 384
#define   MI_LRI_FORCE_POSTED		(1<<12)
6084 serge 385
#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
386
#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
4560 Serge 387
#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
2325 Serge 388
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
3243 Serge 389
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
6084 serge 390
#define   MI_INVALIDATE_TLB		(1<<18)
3243 Serge 391
#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
5060 serge 392
#define   MI_FLUSH_DW_OP_MASK		(3<<14)
393
#define   MI_FLUSH_DW_NOTIFY		(1<<8)
6084 serge 394
#define   MI_INVALIDATE_BSD		(1<<7)
3243 Serge 395
#define   MI_FLUSH_DW_USE_GTT		(1<<2)
396
#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
6084 serge 397
#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
398
#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
2325 Serge 399
#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
6084 serge 400
#define   MI_BATCH_NON_SECURE		(1)
3243 Serge 401
/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
6084 serge 402
#define   MI_BATCH_NON_SECURE_I965	(1<<8)
3243 Serge 403
#define   MI_BATCH_PPGTT_HSW		(1<<8)
6084 serge 404
#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
2325 Serge 405
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
3031 serge 406
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
4560 Serge 407
#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
6084 serge 408
#define   MI_BATCH_RESOURCE_STREAMER (1<<10)
4560 Serge 409
 
6937 serge 410
#define MI_PREDICATE_SRC0	_MMIO(0x2400)
411
#define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
412
#define MI_PREDICATE_SRC1	_MMIO(0x2408)
413
#define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
4560 Serge 414
 
6937 serge 415
#define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
4560 Serge 416
#define  LOWER_SLICE_ENABLED	(1<<0)
417
#define  LOWER_SLICE_DISABLED	(0<<0)
418
 
2325 Serge 419
/*
420
 * 3D instructions used by the kernel
421
 */
422
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
423
 
424
#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
425
#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
426
#define   SC_UPDATE_SCISSOR       (0x1<<1)
427
#define   SC_ENABLE_MASK          (0x1<<0)
428
#define   SC_ENABLE               (0x1<<0)
429
#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
430
#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
431
#define   SCI_YMIN_MASK      (0xffff<<16)
432
#define   SCI_XMIN_MASK      (0xffff<<0)
433
#define   SCI_YMAX_MASK      (0xffff<<16)
434
#define   SCI_XMAX_MASK      (0xffff<<0)
435
#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
436
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
437
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
438
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
439
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
440
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
441
#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
442
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
443
#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
5128 serge 444
 
445
#define COLOR_BLT_CMD			(2<<29 | 0x40<<22 | (5-2))
6084 serge 446
#define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|4)
2325 Serge 447
#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
448
#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
5128 serge 449
#define   BLT_WRITE_A			(2<<20)
450
#define   BLT_WRITE_RGB			(1<<20)
451
#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
2325 Serge 452
#define   BLT_DEPTH_8			(0<<24)
453
#define   BLT_DEPTH_16_565		(1<<24)
454
#define   BLT_DEPTH_16_1555		(2<<24)
455
#define   BLT_DEPTH_32			(3<<24)
5128 serge 456
#define   BLT_ROP_SRC_COPY		(0xcc<<16)
457
#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
2325 Serge 458
#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
459
#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
460
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
461
#define   ASYNC_FLIP                (1<<22)
462
#define   DISPLAY_PLANE_A           (0<<20)
463
#define   DISPLAY_PLANE_B           (1<<20)
6084 serge 464
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
465
#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
3480 Serge 466
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
5060 serge 467
#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
468
#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
2342 Serge 469
#define   PIPE_CONTROL_CS_STALL				(1<<20)
3031 serge 470
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
5354 serge 471
#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
6084 serge 472
#define   PIPE_CONTROL_QW_WRITE				(1<<14)
5060 serge 473
#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
6084 serge 474
#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
2342 Serge 475
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
476
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
477
#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
478
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
479
#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
6084 serge 480
#define   PIPE_CONTROL_NOTIFY				(1<<8)
5060 serge 481
#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
6084 serge 482
#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
2342 Serge 483
#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
484
#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
485
#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
486
#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
487
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
2325 Serge 488
#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
489
 
5060 serge 490
/*
491
 * Commands used only by the command parser
492
 */
493
#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
494
#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
495
#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
496
#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
497
#define MI_PREDICATE            MI_INSTR(0x0C, 0)
498
#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
499
#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
500
#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
501
#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
502
#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
503
#define MI_CLFLUSH              MI_INSTR(0x27, 0)
504
#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
505
#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
506
#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
507
#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
508
#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
509
#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
510
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
2325 Serge 511
 
5060 serge 512
#define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
513
#define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
514
#define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
515
#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
516
#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
517
#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
518
#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
519
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
520
#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
521
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
522
#define GFX_OP_3DSTATE_SO_DECL_LIST \
523
	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
524
 
525
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
526
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
527
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
528
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
529
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
530
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
531
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
532
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
533
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
534
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
535
 
536
#define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
537
 
538
#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
539
#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
540
 
2325 Serge 541
/*
5060 serge 542
 * Registers used only by the command parser
543
 */
6937 serge 544
#define BCS_SWCTRL _MMIO(0x22200)
5060 serge 545
 
6937 serge 546
#define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
547
#define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
548
#define HS_INVOCATION_COUNT             _MMIO(0x2300)
549
#define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
550
#define DS_INVOCATION_COUNT             _MMIO(0x2308)
551
#define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
552
#define IA_VERTICES_COUNT               _MMIO(0x2310)
553
#define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
554
#define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
555
#define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
556
#define VS_INVOCATION_COUNT             _MMIO(0x2320)
557
#define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
558
#define GS_INVOCATION_COUNT             _MMIO(0x2328)
559
#define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
560
#define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
561
#define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
562
#define CL_INVOCATION_COUNT             _MMIO(0x2338)
563
#define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
564
#define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
565
#define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
566
#define PS_INVOCATION_COUNT             _MMIO(0x2348)
567
#define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
568
#define PS_DEPTH_COUNT                  _MMIO(0x2350)
569
#define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
5060 serge 570
 
571
/* There are the 4 64-bit counter registers, one for each stream output */
6937 serge 572
#define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
573
#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
5060 serge 574
 
6937 serge 575
#define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
576
#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
5060 serge 577
 
6937 serge 578
#define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
579
#define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
580
#define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
581
#define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
582
#define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
583
#define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
5060 serge 584
 
6937 serge 585
#define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
586
#define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
587
#define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
6084 serge 588
 
6937 serge 589
#define OACONTROL _MMIO(0x2360)
5060 serge 590
 
591
#define _GEN7_PIPEA_DE_LOAD_SL	0x70068
592
#define _GEN7_PIPEB_DE_LOAD_SL	0x71068
6937 serge 593
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
5060 serge 594
 
595
/*
2325 Serge 596
 * Reset registers
597
 */
6937 serge 598
#define DEBUG_RESET_I830		_MMIO(0x6070)
2325 Serge 599
#define  DEBUG_RESET_FULL		(1<<7)
600
#define  DEBUG_RESET_RENDER		(1<<8)
601
#define  DEBUG_RESET_DISPLAY		(1<<9)
602
 
3031 serge 603
/*
4104 Serge 604
 * IOSF sideband
605
 */
6937 serge 606
#define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
4104 Serge 607
#define   IOSF_DEVFN_SHIFT			24
608
#define   IOSF_OPCODE_SHIFT			16
609
#define   IOSF_PORT_SHIFT			8
610
#define   IOSF_BYTE_ENABLES_SHIFT		4
611
#define   IOSF_BAR_SHIFT			1
612
#define   IOSF_SB_BUSY				(1<<0)
4560 Serge 613
#define   IOSF_PORT_BUNIT			0x3
4104 Serge 614
#define   IOSF_PORT_PUNIT			0x4
615
#define   IOSF_PORT_NC				0x11
616
#define   IOSF_PORT_DPIO			0x12
5060 serge 617
#define   IOSF_PORT_DPIO_2			0x1a
4560 Serge 618
#define   IOSF_PORT_GPIO_NC			0x13
619
#define   IOSF_PORT_CCK				0x14
620
#define   IOSF_PORT_CCU				0xA9
621
#define   IOSF_PORT_GPS_CORE			0x48
622
#define   IOSF_PORT_FLISDSI			0x1B
6937 serge 623
#define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
624
#define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
4104 Serge 625
 
4560 Serge 626
/* See configdb bunit SB addr map */
627
#define BUNIT_REG_BISOC				0x11
628
 
629
#define PUNIT_REG_DSPFREQ			0x36
5354 serge 630
#define   DSPFREQSTAT_SHIFT_CHV			24
631
#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
632
#define   DSPFREQGUAR_SHIFT_CHV			8
633
#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
4560 Serge 634
#define   DSPFREQSTAT_SHIFT			30
635
#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
636
#define   DSPFREQGUAR_SHIFT			14
637
#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
6084 serge 638
#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
639
#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
640
#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
5354 serge 641
#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
642
#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
643
#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
644
#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
645
#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
646
#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
647
#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
648
#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
649
#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
650
#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
651
#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
652
#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
5060 serge 653
 
654
/* See the PUNIT HAS v0.8 for the below bits */
655
enum punit_power_well {
6937 serge 656
	/* These numbers are fixed and must match the position of the pw bits */
5060 serge 657
	PUNIT_POWER_WELL_RENDER			= 0,
658
	PUNIT_POWER_WELL_MEDIA			= 1,
659
	PUNIT_POWER_WELL_DISP2D			= 3,
660
	PUNIT_POWER_WELL_DPIO_CMN_BC		= 5,
661
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_01	= 6,
662
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
663
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
664
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
665
	PUNIT_POWER_WELL_DPIO_RX0		= 10,
666
	PUNIT_POWER_WELL_DPIO_RX1		= 11,
5354 serge 667
	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
5060 serge 668
 
6937 serge 669
	/* Not actual bit groups. Used as IDs for lookup_power_well() */
670
	PUNIT_POWER_WELL_ALWAYS_ON,
5060 serge 671
};
672
 
6084 serge 673
enum skl_disp_power_wells {
6937 serge 674
	/* These numbers are fixed and must match the position of the pw bits */
6084 serge 675
	SKL_DISP_PW_MISC_IO,
676
	SKL_DISP_PW_DDI_A_E,
677
	SKL_DISP_PW_DDI_B,
678
	SKL_DISP_PW_DDI_C,
679
	SKL_DISP_PW_DDI_D,
680
	SKL_DISP_PW_1 = 14,
681
	SKL_DISP_PW_2,
6937 serge 682
 
683
	/* Not actual bit groups. Used as IDs for lookup_power_well() */
684
	SKL_DISP_PW_ALWAYS_ON,
685
	SKL_DISP_PW_DC_OFF,
6084 serge 686
};
687
 
688
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
689
#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
690
 
4560 Serge 691
#define PUNIT_REG_PWRGT_CTRL			0x60
692
#define PUNIT_REG_PWRGT_STATUS			0x61
5060 serge 693
#define   PUNIT_PWRGT_MASK(power_well)		(3 << ((power_well) * 2))
694
#define   PUNIT_PWRGT_PWR_ON(power_well)	(0 << ((power_well) * 2))
695
#define   PUNIT_PWRGT_CLK_GATE(power_well)	(1 << ((power_well) * 2))
696
#define   PUNIT_PWRGT_RESET(power_well)		(2 << ((power_well) * 2))
697
#define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))
4560 Serge 698
 
4104 Serge 699
#define PUNIT_REG_GPU_LFM			0xd3
700
#define PUNIT_REG_GPU_FREQ_REQ			0xd4
701
#define PUNIT_REG_GPU_FREQ_STS			0xd8
5354 serge 702
#define   GPLLENABLE				(1<<4)
4104 Serge 703
#define   GENFREQSTATUS				(1<<0)
704
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
5060 serge 705
#define PUNIT_REG_CZ_TIMESTAMP			0xce
4104 Serge 706
 
707
#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
708
#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
709
 
6084 serge 710
#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
711
#define FB_GFX_FREQ_FUSE_MASK			0xff
712
#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
713
#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
714
#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
715
 
716
#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
717
#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
718
 
719
#define PUNIT_REG_DDR_SETUP2			0x139
720
#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
721
#define   FORCE_DDR_LOW_FREQ			(1 << 1)
722
#define   FORCE_DDR_HIGH_FREQ			(1 << 0)
723
 
5060 serge 724
#define PUNIT_GPU_STATUS_REG			0xdb
725
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
726
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
727
#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
728
#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
729
 
730
#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
731
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
732
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
733
 
4104 Serge 734
#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
735
#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
736
#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
737
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
738
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
739
#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
740
#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
741
#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
742
#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
743
#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
744
 
6084 serge 745
#define VLV_TURBO_SOC_OVERRIDE	0x04
746
#define 	VLV_OVERRIDE_EN	1
747
#define 	VLV_SOC_TDP_EN	(1 << 1)
748
#define 	VLV_BIAS_CPU_125_SOC_875 (6 << 2)
749
#define 	CHV_BIAS_CPU_50_SOC_50 (3 << 2)
750
 
5060 serge 751
#define VLV_CZ_CLOCK_TO_MILLI_SEC		100000
752
 
4560 Serge 753
/* vlv2 north clock has */
754
#define CCK_FUSE_REG				0x8
755
#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
756
#define CCK_REG_DSI_PLL_FUSE			0x44
757
#define CCK_REG_DSI_PLL_CONTROL			0x48
758
#define  DSI_PLL_VCO_EN				(1 << 31)
759
#define  DSI_PLL_LDO_GATE			(1 << 30)
760
#define  DSI_PLL_P1_POST_DIV_SHIFT		17
761
#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
762
#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
763
#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
764
#define  DSI_PLL_MUX_MASK			(3 << 9)
765
#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
766
#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
767
#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
768
#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
769
#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
770
#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
771
#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
772
#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
773
#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
774
#define  DSI_PLL_LOCK				(1 << 0)
775
#define CCK_REG_DSI_PLL_DIVIDER			0x4c
776
#define  DSI_PLL_LFSR				(1 << 31)
777
#define  DSI_PLL_FRACTION_EN			(1 << 30)
778
#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
779
#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
780
#define  DSI_PLL_USYNC_CNT_SHIFT		18
781
#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
782
#define  DSI_PLL_N1_DIV_SHIFT			16
783
#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
784
#define  DSI_PLL_M1_DIV_SHIFT			0
785
#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
6084 serge 786
#define CCK_CZ_CLOCK_CONTROL			0x62
4560 Serge 787
#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
6084 serge 788
#define  CCK_TRUNK_FORCE_ON			(1 << 17)
789
#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
790
#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
791
#define  CCK_FREQUENCY_STATUS_SHIFT		8
792
#define  CCK_FREQUENCY_VALUES			(0x1f << 0)
4560 Serge 793
 
5060 serge 794
/**
795
 * DOC: DPIO
3480 Serge 796
 *
6084 serge 797
 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
5060 serge 798
 * ports. DPIO is the name given to such a display PHY. These PHYs
799
 * don't follow the standard programming model using direct MMIO
800
 * registers, and instead their registers must be accessed trough IOSF
801
 * sideband. VLV has one such PHY for driving ports B and C, and CHV
802
 * adds another PHY for driving port D. Each PHY responds to specific
803
 * IOSF-SB port.
4104 Serge 804
 *
5060 serge 805
 * Each display PHY is made up of one or two channels. Each channel
806
 * houses a common lane part which contains the PLL and other common
807
 * logic. CH0 common lane also contains the IOSF-SB logic for the
808
 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
809
 * must be running when any DPIO registers are accessed.
810
 *
811
 * In addition to having their own registers, the PHYs are also
812
 * controlled through some dedicated signals from the display
813
 * controller. These include PLL reference clock enable, PLL enable,
814
 * and CRI clock selection, for example.
815
 *
816
 * Eeach channel also has two splines (also called data lanes), and
817
 * each spline is made up of one Physical Access Coding Sub-Layer
818
 * (PCS) block and two TX lanes. So each channel has two PCS blocks
819
 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
820
 * data/clock pairs depending on the output type.
821
 *
822
 * Additionally the PHY also contains an AUX lane with AUX blocks
823
 * for each channel. This is used for DP AUX communication, but
824
 * this fact isn't really relevant for the driver since AUX is
825
 * controlled from the display controller side. No DPIO registers
826
 * need to be accessed during AUX communication,
827
 *
6084 serge 828
 * Generally on VLV/CHV the common lane corresponds to the pipe and
5354 serge 829
 * the spline (PCS/TX) corresponds to the port.
5060 serge 830
 *
831
 * For dual channel PHY (VLV/CHV):
832
 *
833
 *  pipe A == CMN/PLL/REF CH0
834
 *
835
 *  pipe B == CMN/PLL/REF CH1
836
 *
837
 *  port B == PCS/TX CH0
838
 *
839
 *  port C == PCS/TX CH1
840
 *
841
 * This is especially important when we cross the streams
842
 * ie. drive port B with pipe B, or port C with pipe A.
843
 *
844
 * For single channel PHY (CHV):
845
 *
846
 *  pipe C == CMN/PLL/REF CH0
847
 *
848
 *  port D == PCS/TX CH0
849
 *
6084 serge 850
 * On BXT the entire PHY channel corresponds to the port. That means
851
 * the PLL is also now associated with the port rather than the pipe,
852
 * and so the clock needs to be routed to the appropriate transcoder.
853
 * Port A PLL is directly connected to transcoder EDP and port B/C
854
 * PLLs can be routed to any transcoder A/B/C.
855
 *
856
 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
857
 * digital port D (CHV) or port A (BXT).
6937 serge 858
 *
859
 *
6084 serge 860
 * Dual channel PHY (VLV/CHV/BXT)
5060 serge 861
 * ---------------------------------
862
 * |      CH0      |      CH1      |
863
 * |  CMN/PLL/REF  |  CMN/PLL/REF  |
864
 * |---------------|---------------| Display PHY
865
 * | PCS01 | PCS23 | PCS01 | PCS23 |
866
 * |-------|-------|-------|-------|
867
 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
868
 * ---------------------------------
869
 * |     DDI0      |     DDI1      | DP/HDMI ports
870
 * ---------------------------------
871
 *
6084 serge 872
 * Single channel PHY (CHV/BXT)
5060 serge 873
 * -----------------
874
 * |      CH0      |
875
 * |  CMN/PLL/REF  |
876
 * |---------------| Display PHY
877
 * | PCS01 | PCS23 |
878
 * |-------|-------|
879
 * |TX0|TX1|TX2|TX3|
880
 * -----------------
881
 * |     DDI2      | DP/HDMI port
882
 * -----------------
883
 */
4104 Serge 884
#define DPIO_DEVFN			0
885
 
6937 serge 886
#define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
3031 serge 887
#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
888
#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
889
#define  DPIO_SFR_BYPASS		(1<<1)
4560 Serge 890
#define  DPIO_CMNRST			(1<<0)
2325 Serge 891
 
4560 Serge 892
#define DPIO_PHY(pipe)			((pipe) >> 1)
893
#define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
4104 Serge 894
 
895
/*
896
 * Per pipe/PLL DPIO regs
897
 */
4560 Serge 898
#define _VLV_PLL_DW3_CH0		0x800c
3031 serge 899
#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
4104 Serge 900
#define   DPIO_POST_DIV_DAC		0
901
#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
902
#define   DPIO_POST_DIV_LVDS1		2
903
#define   DPIO_POST_DIV_LVDS2		3
3031 serge 904
#define   DPIO_K_SHIFT			(24) /* 4 bits */
905
#define   DPIO_P1_SHIFT			(21) /* 3 bits */
906
#define   DPIO_P2_SHIFT			(16) /* 5 bits */
907
#define   DPIO_N_SHIFT			(12) /* 4 bits */
908
#define   DPIO_ENABLE_CALIBRATION	(1<<11)
909
#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
910
#define   DPIO_M2DIV_MASK		0xff
4560 Serge 911
#define _VLV_PLL_DW3_CH1		0x802c
912
#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
3031 serge 913
 
4560 Serge 914
#define _VLV_PLL_DW5_CH0		0x8014
3031 serge 915
#define   DPIO_REFSEL_OVERRIDE		27
916
#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
917
#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
918
#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
3243 Serge 919
#define   DPIO_PLL_REFCLK_SEL_MASK	3
3031 serge 920
#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
921
#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
4560 Serge 922
#define _VLV_PLL_DW5_CH1		0x8034
923
#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
3031 serge 924
 
4560 Serge 925
#define _VLV_PLL_DW7_CH0		0x801c
926
#define _VLV_PLL_DW7_CH1		0x803c
927
#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
3031 serge 928
 
4560 Serge 929
#define _VLV_PLL_DW8_CH0		0x8040
930
#define _VLV_PLL_DW8_CH1		0x8060
931
#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
3031 serge 932
 
4560 Serge 933
#define VLV_PLL_DW9_BCAST		0xc044
934
#define _VLV_PLL_DW9_CH0		0x8044
935
#define _VLV_PLL_DW9_CH1		0x8064
936
#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
4104 Serge 937
 
4560 Serge 938
#define _VLV_PLL_DW10_CH0		0x8048
939
#define _VLV_PLL_DW10_CH1		0x8068
940
#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
4104 Serge 941
 
4560 Serge 942
#define _VLV_PLL_DW11_CH0		0x804c
943
#define _VLV_PLL_DW11_CH1		0x806c
944
#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
4104 Serge 945
 
4560 Serge 946
/* Spec for ref block start counts at DW10 */
947
#define VLV_REF_DW13			0x80ac
4104 Serge 948
 
4560 Serge 949
#define VLV_CMN_DW0			0x8100
3031 serge 950
 
4104 Serge 951
/*
952
 * Per DDI channel DPIO regs
953
 */
954
 
4560 Serge 955
#define _VLV_PCS_DW0_CH0		0x8200
956
#define _VLV_PCS_DW0_CH1		0x8400
4104 Serge 957
#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
958
#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
5354 serge 959
#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
960
#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
4560 Serge 961
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
4104 Serge 962
 
5060 serge 963
#define _VLV_PCS01_DW0_CH0		0x200
964
#define _VLV_PCS23_DW0_CH0		0x400
965
#define _VLV_PCS01_DW0_CH1		0x2600
966
#define _VLV_PCS23_DW0_CH1		0x2800
967
#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
968
#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
969
 
4560 Serge 970
#define _VLV_PCS_DW1_CH0		0x8204
971
#define _VLV_PCS_DW1_CH1		0x8404
5060 serge 972
#define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
4104 Serge 973
#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
974
#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
975
#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
976
#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
4560 Serge 977
#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
4104 Serge 978
 
5060 serge 979
#define _VLV_PCS01_DW1_CH0		0x204
980
#define _VLV_PCS23_DW1_CH0		0x404
981
#define _VLV_PCS01_DW1_CH1		0x2604
982
#define _VLV_PCS23_DW1_CH1		0x2804
983
#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
984
#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
985
 
4560 Serge 986
#define _VLV_PCS_DW8_CH0		0x8220
987
#define _VLV_PCS_DW8_CH1		0x8420
5060 serge 988
#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
989
#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
4560 Serge 990
#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
4104 Serge 991
 
4560 Serge 992
#define _VLV_PCS01_DW8_CH0		0x0220
993
#define _VLV_PCS23_DW8_CH0		0x0420
994
#define _VLV_PCS01_DW8_CH1		0x2620
995
#define _VLV_PCS23_DW8_CH1		0x2820
996
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
997
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
4104 Serge 998
 
4560 Serge 999
#define _VLV_PCS_DW9_CH0		0x8224
1000
#define _VLV_PCS_DW9_CH1		0x8424
5354 serge 1001
#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
1002
#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
1003
#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
1004
#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
1005
#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
1006
#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
4560 Serge 1007
#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
4104 Serge 1008
 
5354 serge 1009
#define _VLV_PCS01_DW9_CH0		0x224
1010
#define _VLV_PCS23_DW9_CH0		0x424
1011
#define _VLV_PCS01_DW9_CH1		0x2624
1012
#define _VLV_PCS23_DW9_CH1		0x2824
1013
#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1014
#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1015
 
5060 serge 1016
#define _CHV_PCS_DW10_CH0		0x8228
1017
#define _CHV_PCS_DW10_CH1		0x8428
1018
#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
1019
#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
5354 serge 1020
#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
1021
#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
1022
#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
1023
#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
1024
#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
1025
#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
5060 serge 1026
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1027
 
1028
#define _VLV_PCS01_DW10_CH0		0x0228
1029
#define _VLV_PCS23_DW10_CH0		0x0428
1030
#define _VLV_PCS01_DW10_CH1		0x2628
1031
#define _VLV_PCS23_DW10_CH1		0x2828
1032
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1033
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1034
 
4560 Serge 1035
#define _VLV_PCS_DW11_CH0		0x822c
1036
#define _VLV_PCS_DW11_CH1		0x842c
6084 serge 1037
#define   DPIO_TX2_STAGGER_MASK(x)	((x)<<24)
5354 serge 1038
#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
1039
#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
1040
#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
4560 Serge 1041
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
4104 Serge 1042
 
5354 serge 1043
#define _VLV_PCS01_DW11_CH0		0x022c
1044
#define _VLV_PCS23_DW11_CH0		0x042c
1045
#define _VLV_PCS01_DW11_CH1		0x262c
1046
#define _VLV_PCS23_DW11_CH1		0x282c
1047
#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1048
#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1049
 
6084 serge 1050
#define _VLV_PCS01_DW12_CH0		0x0230
1051
#define _VLV_PCS23_DW12_CH0		0x0430
1052
#define _VLV_PCS01_DW12_CH1		0x2630
1053
#define _VLV_PCS23_DW12_CH1		0x2830
1054
#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1055
#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1056
 
4560 Serge 1057
#define _VLV_PCS_DW12_CH0		0x8230
1058
#define _VLV_PCS_DW12_CH1		0x8430
6084 serge 1059
#define   DPIO_TX2_STAGGER_MULT(x)	((x)<<20)
1060
#define   DPIO_TX1_STAGGER_MULT(x)	((x)<<16)
1061
#define   DPIO_TX1_STAGGER_MASK(x)	((x)<<8)
1062
#define   DPIO_LANESTAGGER_STRAP_OVRD	(1<<6)
1063
#define   DPIO_LANESTAGGER_STRAP(x)	((x)<<0)
4560 Serge 1064
#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
4104 Serge 1065
 
4560 Serge 1066
#define _VLV_PCS_DW14_CH0		0x8238
1067
#define _VLV_PCS_DW14_CH1		0x8438
1068
#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
4104 Serge 1069
 
4560 Serge 1070
#define _VLV_PCS_DW23_CH0		0x825c
1071
#define _VLV_PCS_DW23_CH1		0x845c
1072
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
4104 Serge 1073
 
4560 Serge 1074
#define _VLV_TX_DW2_CH0			0x8288
1075
#define _VLV_TX_DW2_CH1			0x8488
5354 serge 1076
#define   DPIO_SWING_MARGIN000_SHIFT	16
1077
#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
5060 serge 1078
#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
4560 Serge 1079
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
4104 Serge 1080
 
4560 Serge 1081
#define _VLV_TX_DW3_CH0			0x828c
1082
#define _VLV_TX_DW3_CH1			0x848c
5060 serge 1083
/* The following bit for CHV phy */
1084
#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
5354 serge 1085
#define   DPIO_SWING_MARGIN101_SHIFT	16
1086
#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
4560 Serge 1087
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
4104 Serge 1088
 
4560 Serge 1089
#define _VLV_TX_DW4_CH0			0x8290
1090
#define _VLV_TX_DW4_CH1			0x8490
5060 serge 1091
#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
1092
#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
5354 serge 1093
#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1094
#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
4560 Serge 1095
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
4104 Serge 1096
 
4560 Serge 1097
#define _VLV_TX3_DW4_CH0		0x690
1098
#define _VLV_TX3_DW4_CH1		0x2a90
1099
#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
4104 Serge 1100
 
4560 Serge 1101
#define _VLV_TX_DW5_CH0			0x8294
1102
#define _VLV_TX_DW5_CH1			0x8494
1103
#define   DPIO_TX_OCALINIT_EN		(1<<31)
1104
#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
4104 Serge 1105
 
4560 Serge 1106
#define _VLV_TX_DW11_CH0		0x82ac
1107
#define _VLV_TX_DW11_CH1		0x84ac
1108
#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
3243 Serge 1109
 
4560 Serge 1110
#define _VLV_TX_DW14_CH0		0x82b8
1111
#define _VLV_TX_DW14_CH1		0x84b8
1112
#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1113
 
5060 serge 1114
/* CHV dpPhy registers */
1115
#define _CHV_PLL_DW0_CH0		0x8000
1116
#define _CHV_PLL_DW0_CH1		0x8180
1117
#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1118
 
1119
#define _CHV_PLL_DW1_CH0		0x8004
1120
#define _CHV_PLL_DW1_CH1		0x8184
1121
#define   DPIO_CHV_N_DIV_SHIFT		8
1122
#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1123
#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1124
 
1125
#define _CHV_PLL_DW2_CH0		0x8008
1126
#define _CHV_PLL_DW2_CH1		0x8188
1127
#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1128
 
1129
#define _CHV_PLL_DW3_CH0		0x800c
1130
#define _CHV_PLL_DW3_CH1		0x818c
1131
#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
1132
#define  DPIO_CHV_FIRST_MOD		(0 << 8)
1133
#define  DPIO_CHV_SECOND_MOD		(1 << 8)
1134
#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
6084 serge 1135
#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
5060 serge 1136
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1137
 
1138
#define _CHV_PLL_DW6_CH0		0x8018
1139
#define _CHV_PLL_DW6_CH1		0x8198
1140
#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
1141
#define	  DPIO_CHV_INT_COEFF_SHIFT	8
1142
#define   DPIO_CHV_PROP_COEFF_SHIFT	0
1143
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1144
 
6084 serge 1145
#define _CHV_PLL_DW8_CH0		0x8020
1146
#define _CHV_PLL_DW8_CH1		0x81A0
1147
#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1148
#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1149
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1150
 
1151
#define _CHV_PLL_DW9_CH0		0x8024
1152
#define _CHV_PLL_DW9_CH1		0x81A4
1153
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
1154
#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
1155
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1156
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1157
 
1158
#define _CHV_CMN_DW0_CH0               0x8100
1159
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
1160
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
1161
#define   DPIO_ALLDL_POWERDOWN			(1 << 1)
1162
#define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1163
 
5060 serge 1164
#define _CHV_CMN_DW5_CH0               0x8114
1165
#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1166
#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
1167
#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
1168
#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
1169
#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1170
#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
1171
#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
1172
#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
1173
 
1174
#define _CHV_CMN_DW13_CH0		0x8134
1175
#define _CHV_CMN_DW0_CH1		0x8080
1176
#define   DPIO_CHV_S1_DIV_SHIFT		21
1177
#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
1178
#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
1179
#define   DPIO_CHV_K_DIV_SHIFT		4
1180
#define   DPIO_PLL_FREQLOCK		(1 << 1)
1181
#define   DPIO_PLL_LOCK			(1 << 0)
1182
#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1183
 
1184
#define _CHV_CMN_DW14_CH0		0x8138
1185
#define _CHV_CMN_DW1_CH1		0x8084
1186
#define   DPIO_AFC_RECAL		(1 << 14)
1187
#define   DPIO_DCLKP_EN			(1 << 13)
1188
#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1189
#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
1190
#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
1191
#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
1192
#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1193
#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
1194
#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
1195
#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
1196
#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1197
 
1198
#define _CHV_CMN_DW19_CH0		0x814c
1199
#define _CHV_CMN_DW6_CH1		0x8098
6084 serge 1200
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
1201
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
1202
#define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
5060 serge 1203
#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
6084 serge 1204
 
5060 serge 1205
#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1206
 
6084 serge 1207
#define CHV_CMN_DW28			0x8170
1208
#define   DPIO_CL1POWERDOWNEN		(1 << 23)
1209
#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
1210
#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1211
#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1212
#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1213
#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1214
 
5060 serge 1215
#define CHV_CMN_DW30			0x8178
6084 serge 1216
#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
5060 serge 1217
#define   DPIO_LRC_BYPASS		(1 << 3)
1218
 
1219
#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1220
					(lane) * 0x200 + (offset))
1221
 
1222
#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1223
#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1224
#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1225
#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1226
#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1227
#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1228
#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1229
#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1230
#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1231
#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1232
#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1233
#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1234
#define   DPIO_FRC_LATENCY_SHFIT	8
1235
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1236
#define   DPIO_UPAR_SHIFT		30
6084 serge 1237
 
1238
/* BXT PHY registers */
6937 serge 1239
#define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
6084 serge 1240
 
6937 serge 1241
#define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
6084 serge 1242
#define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
1243
 
1244
#define _PHY_CTL_FAMILY_EDP		0x64C80
1245
#define _PHY_CTL_FAMILY_DDI		0x64C90
1246
#define   COMMON_RESET_DIS		(1 << 31)
1247
#define BXT_PHY_CTL_FAMILY(phy)		_BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1248
							_PHY_CTL_FAMILY_EDP)
1249
 
1250
/* BXT PHY PLL registers */
1251
#define _PORT_PLL_A			0x46074
1252
#define _PORT_PLL_B			0x46078
1253
#define _PORT_PLL_C			0x4607c
1254
#define   PORT_PLL_ENABLE		(1 << 31)
1255
#define   PORT_PLL_LOCK			(1 << 30)
1256
#define   PORT_PLL_REF_SEL		(1 << 27)
6937 serge 1257
#define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
6084 serge 1258
 
1259
#define _PORT_PLL_EBB_0_A		0x162034
1260
#define _PORT_PLL_EBB_0_B		0x6C034
1261
#define _PORT_PLL_EBB_0_C		0x6C340
1262
#define   PORT_PLL_P1_SHIFT		13
1263
#define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1264
#define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
1265
#define   PORT_PLL_P2_SHIFT		8
1266
#define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1267
#define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
6937 serge 1268
#define BXT_PORT_PLL_EBB_0(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
6084 serge 1269
						_PORT_PLL_EBB_0_B,	\
1270
						_PORT_PLL_EBB_0_C)
1271
 
1272
#define _PORT_PLL_EBB_4_A		0x162038
1273
#define _PORT_PLL_EBB_4_B		0x6C038
1274
#define _PORT_PLL_EBB_4_C		0x6C344
1275
#define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
1276
#define   PORT_PLL_RECALIBRATE		(1 << 14)
6937 serge 1277
#define BXT_PORT_PLL_EBB_4(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
6084 serge 1278
						_PORT_PLL_EBB_4_B,	\
1279
						_PORT_PLL_EBB_4_C)
1280
 
1281
#define _PORT_PLL_0_A			0x162100
1282
#define _PORT_PLL_0_B			0x6C100
1283
#define _PORT_PLL_0_C			0x6C380
1284
/* PORT_PLL_0_A */
1285
#define   PORT_PLL_M2_MASK		0xFF
1286
/* PORT_PLL_1_A */
1287
#define   PORT_PLL_N_SHIFT		8
1288
#define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1289
#define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
1290
/* PORT_PLL_2_A */
1291
#define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1292
/* PORT_PLL_3_A */
1293
#define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
1294
/* PORT_PLL_6_A */
1295
#define   PORT_PLL_PROP_COEFF_MASK	0xF
1296
#define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1297
#define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
1298
#define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1299
#define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
1300
/* PORT_PLL_8_A */
1301
#define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1302
/* PORT_PLL_9_A */
1303
#define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
1304
#define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1305
/* PORT_PLL_10_A */
1306
#define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)
1307
#define  PORT_PLL_DCO_AMP_DEFAULT	15
1308
#define  PORT_PLL_DCO_AMP_MASK		0x3c00
1309
#define  PORT_PLL_DCO_AMP(x)		((x)<<10)
1310
#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
1311
						_PORT_PLL_0_B,		\
1312
						_PORT_PLL_0_C)
6937 serge 1313
#define BXT_PORT_PLL(port, idx)		_MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
6084 serge 1314
 
1315
/* BXT PHY common lane registers */
1316
#define _PORT_CL1CM_DW0_A		0x162000
1317
#define _PORT_CL1CM_DW0_BC		0x6C000
1318
#define   PHY_POWER_GOOD		(1 << 16)
1319
#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1320
							_PORT_CL1CM_DW0_A)
1321
 
1322
#define _PORT_CL1CM_DW9_A		0x162024
1323
#define _PORT_CL1CM_DW9_BC		0x6C024
1324
#define   IREF0RC_OFFSET_SHIFT		8
1325
#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1326
#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1327
							_PORT_CL1CM_DW9_A)
1328
 
1329
#define _PORT_CL1CM_DW10_A		0x162028
1330
#define _PORT_CL1CM_DW10_BC		0x6C028
1331
#define   IREF1RC_OFFSET_SHIFT		8
1332
#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1333
#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1334
							_PORT_CL1CM_DW10_A)
1335
 
1336
#define _PORT_CL1CM_DW28_A		0x162070
1337
#define _PORT_CL1CM_DW28_BC		0x6C070
1338
#define   OCL1_POWER_DOWN_EN		(1 << 23)
1339
#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
1340
#define   SUS_CLK_CONFIG		0x3
1341
#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1342
							_PORT_CL1CM_DW28_A)
1343
 
1344
#define _PORT_CL1CM_DW30_A		0x162078
1345
#define _PORT_CL1CM_DW30_BC		0x6C078
1346
#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
1347
#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1348
							_PORT_CL1CM_DW30_A)
1349
 
1350
/* Defined for PHY0 only */
6937 serge 1351
#define BXT_PORT_CL2CM_DW6_BC		_MMIO(0x6C358)
6084 serge 1352
#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
1353
 
1354
/* BXT PHY Ref registers */
1355
#define _PORT_REF_DW3_A			0x16218C
1356
#define _PORT_REF_DW3_BC		0x6C18C
1357
#define   GRC_DONE			(1 << 22)
1358
#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
1359
							_PORT_REF_DW3_A)
1360
 
1361
#define _PORT_REF_DW6_A			0x162198
1362
#define _PORT_REF_DW6_BC		0x6C198
2325 Serge 1363
/*
6084 serge 1364
 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1365
 * after testing.
1366
 */
1367
#define   GRC_CODE_SHIFT		23
1368
#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
1369
#define   GRC_CODE_FAST_SHIFT		16
1370
#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
1371
#define   GRC_CODE_SLOW_SHIFT		8
1372
#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
1373
#define   GRC_CODE_NOM_MASK		0xFF
1374
#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
1375
						      _PORT_REF_DW6_A)
1376
 
1377
#define _PORT_REF_DW8_A			0x1621A0
1378
#define _PORT_REF_DW8_BC		0x6C1A0
1379
#define   GRC_DIS			(1 << 15)
1380
#define   GRC_RDY_OVRD			(1 << 1)
1381
#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
1382
						      _PORT_REF_DW8_A)
1383
 
1384
/* BXT PHY PCS registers */
1385
#define _PORT_PCS_DW10_LN01_A		0x162428
1386
#define _PORT_PCS_DW10_LN01_B		0x6C428
1387
#define _PORT_PCS_DW10_LN01_C		0x6C828
1388
#define _PORT_PCS_DW10_GRP_A		0x162C28
1389
#define _PORT_PCS_DW10_GRP_B		0x6CC28
1390
#define _PORT_PCS_DW10_GRP_C		0x6CE28
6937 serge 1391
#define BXT_PORT_PCS_DW10_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
6084 serge 1392
						     _PORT_PCS_DW10_LN01_B, \
1393
						     _PORT_PCS_DW10_LN01_C)
6937 serge 1394
#define BXT_PORT_PCS_DW10_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
6084 serge 1395
						     _PORT_PCS_DW10_GRP_B,  \
1396
						     _PORT_PCS_DW10_GRP_C)
1397
#define   TX2_SWING_CALC_INIT		(1 << 31)
1398
#define   TX1_SWING_CALC_INIT		(1 << 30)
1399
 
1400
#define _PORT_PCS_DW12_LN01_A		0x162430
1401
#define _PORT_PCS_DW12_LN01_B		0x6C430
1402
#define _PORT_PCS_DW12_LN01_C		0x6C830
1403
#define _PORT_PCS_DW12_LN23_A		0x162630
1404
#define _PORT_PCS_DW12_LN23_B		0x6C630
1405
#define _PORT_PCS_DW12_LN23_C		0x6CA30
1406
#define _PORT_PCS_DW12_GRP_A		0x162c30
1407
#define _PORT_PCS_DW12_GRP_B		0x6CC30
1408
#define _PORT_PCS_DW12_GRP_C		0x6CE30
1409
#define   LANESTAGGER_STRAP_OVRD	(1 << 6)
1410
#define   LANE_STAGGER_MASK		0x1F
6937 serge 1411
#define BXT_PORT_PCS_DW12_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
6084 serge 1412
						     _PORT_PCS_DW12_LN01_B, \
1413
						     _PORT_PCS_DW12_LN01_C)
6937 serge 1414
#define BXT_PORT_PCS_DW12_LN23(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
6084 serge 1415
						     _PORT_PCS_DW12_LN23_B, \
1416
						     _PORT_PCS_DW12_LN23_C)
6937 serge 1417
#define BXT_PORT_PCS_DW12_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
6084 serge 1418
						     _PORT_PCS_DW12_GRP_B, \
1419
						     _PORT_PCS_DW12_GRP_C)
1420
 
1421
/* BXT PHY TX registers */
1422
#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
1423
					  ((lane) & 1) * 0x80)
1424
 
1425
#define _PORT_TX_DW2_LN0_A		0x162508
1426
#define _PORT_TX_DW2_LN0_B		0x6C508
1427
#define _PORT_TX_DW2_LN0_C		0x6C908
1428
#define _PORT_TX_DW2_GRP_A		0x162D08
1429
#define _PORT_TX_DW2_GRP_B		0x6CD08
1430
#define _PORT_TX_DW2_GRP_C		0x6CF08
6937 serge 1431
#define BXT_PORT_TX_DW2_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW2_GRP_A,  \
6084 serge 1432
						     _PORT_TX_DW2_GRP_B,  \
1433
						     _PORT_TX_DW2_GRP_C)
6937 serge 1434
#define BXT_PORT_TX_DW2_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW2_LN0_A,  \
6084 serge 1435
						     _PORT_TX_DW2_LN0_B,  \
1436
						     _PORT_TX_DW2_LN0_C)
1437
#define   MARGIN_000_SHIFT		16
1438
#define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
1439
#define   UNIQ_TRANS_SCALE_SHIFT	8
1440
#define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
1441
 
1442
#define _PORT_TX_DW3_LN0_A		0x16250C
1443
#define _PORT_TX_DW3_LN0_B		0x6C50C
1444
#define _PORT_TX_DW3_LN0_C		0x6C90C
1445
#define _PORT_TX_DW3_GRP_A		0x162D0C
1446
#define _PORT_TX_DW3_GRP_B		0x6CD0C
1447
#define _PORT_TX_DW3_GRP_C		0x6CF0C
6937 serge 1448
#define BXT_PORT_TX_DW3_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW3_GRP_A,  \
6084 serge 1449
						     _PORT_TX_DW3_GRP_B,  \
1450
						     _PORT_TX_DW3_GRP_C)
6937 serge 1451
#define BXT_PORT_TX_DW3_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW3_LN0_A,  \
6084 serge 1452
						     _PORT_TX_DW3_LN0_B,  \
1453
						     _PORT_TX_DW3_LN0_C)
1454
#define   SCALE_DCOMP_METHOD		(1 << 26)
1455
#define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
1456
 
1457
#define _PORT_TX_DW4_LN0_A		0x162510
1458
#define _PORT_TX_DW4_LN0_B		0x6C510
1459
#define _PORT_TX_DW4_LN0_C		0x6C910
1460
#define _PORT_TX_DW4_GRP_A		0x162D10
1461
#define _PORT_TX_DW4_GRP_B		0x6CD10
1462
#define _PORT_TX_DW4_GRP_C		0x6CF10
6937 serge 1463
#define BXT_PORT_TX_DW4_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW4_LN0_A,  \
6084 serge 1464
						     _PORT_TX_DW4_LN0_B,  \
1465
						     _PORT_TX_DW4_LN0_C)
6937 serge 1466
#define BXT_PORT_TX_DW4_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW4_GRP_A,  \
6084 serge 1467
						     _PORT_TX_DW4_GRP_B,  \
1468
						     _PORT_TX_DW4_GRP_C)
1469
#define   DEEMPH_SHIFT			24
1470
#define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
1471
 
1472
#define _PORT_TX_DW14_LN0_A		0x162538
1473
#define _PORT_TX_DW14_LN0_B		0x6C538
1474
#define _PORT_TX_DW14_LN0_C		0x6C938
1475
#define   LATENCY_OPTIM_SHIFT		30
1476
#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
6937 serge 1477
#define BXT_PORT_TX_DW14_LN(port, lane)	_MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
6084 serge 1478
							_PORT_TX_DW14_LN0_B,   \
1479
							_PORT_TX_DW14_LN0_C) + \
1480
					 _BXT_LANE_OFFSET(lane))
1481
 
1482
/* UAIMI scratch pad register 1 */
6937 serge 1483
#define UAIMI_SPR1			_MMIO(0x4F074)
6084 serge 1484
/* SKL VccIO mask */
1485
#define SKL_VCCIO_MASK			0x1
1486
/* SKL balance leg register */
6937 serge 1487
#define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
6084 serge 1488
/* I_boost values */
1489
#define BALANCE_LEG_SHIFT(port)		(8+3*(port))
1490
#define BALANCE_LEG_MASK(port)		(7<<(8+3*(port)))
1491
/* Balance leg disable bits */
1492
#define BALANCE_LEG_DISABLE_SHIFT	23
1493
 
1494
/*
2325 Serge 1495
 * Fence registers
6084 serge 1496
 * [0-7]  @ 0x2000 gen2,gen3
1497
 * [8-15] @ 0x3000 945,g33,pnv
1498
 *
1499
 * [0-15] @ 0x3000 gen4,gen5
1500
 *
1501
 * [0-15] @ 0x100000 gen6,vlv,chv
1502
 * [0-31] @ 0x100000 gen7+
2325 Serge 1503
 */
6937 serge 1504
#define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2325 Serge 1505
#define   I830_FENCE_START_MASK		0x07f80000
1506
#define   I830_FENCE_TILING_Y_SHIFT	12
1507
#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
1508
#define   I830_FENCE_PITCH_SHIFT	4
1509
#define   I830_FENCE_REG_VALID		(1<<0)
1510
#define   I915_FENCE_MAX_PITCH_VAL	4
1511
#define   I830_FENCE_MAX_PITCH_VAL	6
1512
#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
1513
 
1514
#define   I915_FENCE_START_MASK		0x0ff00000
1515
#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
1516
 
6937 serge 1517
#define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
1518
#define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2325 Serge 1519
#define   I965_FENCE_PITCH_SHIFT	2
1520
#define   I965_FENCE_TILING_Y_SHIFT	1
1521
#define   I965_FENCE_REG_VALID		(1<<0)
1522
#define   I965_FENCE_MAX_PITCH_VAL	0x0400
1523
 
6937 serge 1524
#define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
1525
#define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
6084 serge 1526
#define   GEN6_FENCE_PITCH_SHIFT	32
3746 Serge 1527
#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2325 Serge 1528
 
5060 serge 1529
 
3031 serge 1530
/* control register for cpu gtt access */
6937 serge 1531
#define TILECTL				_MMIO(0x101000)
3031 serge 1532
#define   TILECTL_SWZCTL			(1 << 0)
6084 serge 1533
#define   TILECTL_TLBPF			(1 << 1)
3031 serge 1534
#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
1535
#define   TILECTL_BACKSNOOP_DIS		(1 << 3)
1536
 
2325 Serge 1537
/*
1538
 * Instruction and interrupt control regs
1539
 */
6937 serge 1540
#define PGTBL_CTL	_MMIO(0x02020)
5060 serge 1541
#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
1542
#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
6937 serge 1543
#define PGTBL_ER	_MMIO(0x02024)
5354 serge 1544
#define PRB0_BASE (0x2030-0x30)
1545
#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1546
#define PRB2_BASE (0x2050-0x30) /* gen3 */
1547
#define SRB0_BASE (0x2100-0x30) /* gen2 */
1548
#define SRB1_BASE (0x2110-0x30) /* gen2 */
1549
#define SRB2_BASE (0x2120-0x30) /* 830 */
1550
#define SRB3_BASE (0x2130-0x30) /* 830 */
2325 Serge 1551
#define RENDER_RING_BASE	0x02000
1552
#define BSD_RING_BASE		0x04000
1553
#define GEN6_BSD_RING_BASE	0x12000
5060 serge 1554
#define GEN8_BSD2_RING_BASE	0x1c000
4104 Serge 1555
#define VEBOX_RING_BASE		0x1a000
2325 Serge 1556
#define BLT_RING_BASE		0x22000
6937 serge 1557
#define RING_TAIL(base)		_MMIO((base)+0x30)
1558
#define RING_HEAD(base)		_MMIO((base)+0x34)
1559
#define RING_START(base)	_MMIO((base)+0x38)
1560
#define RING_CTL(base)		_MMIO((base)+0x3c)
1561
#define RING_SYNC_0(base)	_MMIO((base)+0x40)
1562
#define RING_SYNC_1(base)	_MMIO((base)+0x44)
1563
#define RING_SYNC_2(base)	_MMIO((base)+0x48)
6084 serge 1564
#define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
1565
#define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
4104 Serge 1566
#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
1567
#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
6084 serge 1568
#define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
4104 Serge 1569
#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
6084 serge 1570
#define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
1571
#define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
4104 Serge 1572
#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
1573
#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
1574
#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
1575
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
6937 serge 1576
#define GEN6_NOSYNC	INVALID_MMIO_REG
1577
#define RING_PSMI_CTL(base)	_MMIO((base)+0x50)
1578
#define RING_MAX_IDLE(base)	_MMIO((base)+0x54)
1579
#define RING_HWS_PGA(base)	_MMIO((base)+0x80)
1580
#define RING_HWS_PGA_GEN6(base)	_MMIO((base)+0x2080)
1581
#define RING_RESET_CTL(base)	_MMIO((base)+0xd0)
6084 serge 1582
#define   RESET_CTL_REQUEST_RESET  (1 << 0)
1583
#define   RESET_CTL_READY_TO_RESET (1 << 1)
5060 serge 1584
 
6937 serge 1585
#define HSW_GTT_CACHE_EN	_MMIO(0x4024)
6084 serge 1586
#define   GTT_CACHE_EN_ALL	0xF0007FFF
6937 serge 1587
#define GEN7_WR_WATERMARK	_MMIO(0x4028)
1588
#define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
1589
#define ARB_MODE		_MMIO(0x4030)
3031 serge 1590
#define   ARB_MODE_SWIZZLE_SNB	(1<<4)
1591
#define   ARB_MODE_SWIZZLE_IVB	(1<<5)
6937 serge 1592
#define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
1593
#define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
5060 serge 1594
/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
6937 serge 1595
#define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
5060 serge 1596
#define GEN7_LRA_LIMITS_REG_NUM	13
6937 serge 1597
#define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
1598
#define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
5060 serge 1599
 
6937 serge 1600
#define GAMTARBMODE		_MMIO(0x04a08)
4560 Serge 1601
#define   ARB_MODE_BWGTLB_DISABLE (1<<9)
1602
#define   ARB_MODE_SWIZZLE_BDW	(1<<1)
6937 serge 1603
#define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
1604
#define RING_FAULT_REG(ring)	_MMIO(0x4094 + 0x100*(ring)->id)
4280 Serge 1605
#define   RING_FAULT_GTTSEL_MASK (1<<11)
6084 serge 1606
#define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
1607
#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
4280 Serge 1608
#define   RING_FAULT_VALID	(1<<0)
6937 serge 1609
#define DONE_REG		_MMIO(0x40b0)
1610
#define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
1611
#define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
1612
#define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
1613
#define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
1614
#define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
1615
#define RING_ACTHD(base)	_MMIO((base)+0x74)
1616
#define RING_ACTHD_UDW(base)	_MMIO((base)+0x5c)
1617
#define RING_NOPID(base)	_MMIO((base)+0x94)
1618
#define RING_IMR(base)		_MMIO((base)+0xa8)
1619
#define RING_HWSTAM(base)	_MMIO((base)+0x98)
1620
#define RING_TIMESTAMP(base)		_MMIO((base)+0x358)
1621
#define RING_TIMESTAMP_UDW(base)	_MMIO((base)+0x358 + 4)
2325 Serge 1622
#define   TAIL_ADDR		0x001FFFF8
1623
#define   HEAD_WRAP_COUNT	0xFFE00000
1624
#define   HEAD_WRAP_ONE		0x00200000
1625
#define   HEAD_ADDR		0x001FFFFC
1626
#define   RING_NR_PAGES		0x001FF000
1627
#define   RING_REPORT_MASK	0x00000006
1628
#define   RING_REPORT_64K	0x00000002
1629
#define   RING_REPORT_128K	0x00000004
1630
#define   RING_NO_REPORT	0x00000000
1631
#define   RING_VALID_MASK	0x00000001
1632
#define   RING_VALID		0x00000001
1633
#define   RING_INVALID		0x00000000
1634
#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
1635
#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
1636
#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
5060 serge 1637
 
6937 serge 1638
#define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
5060 serge 1639
 
2325 Serge 1640
#if 0
6937 serge 1641
#define PRB0_TAIL	_MMIO(0x2030)
1642
#define PRB0_HEAD	_MMIO(0x2034)
1643
#define PRB0_START	_MMIO(0x2038)
1644
#define PRB0_CTL	_MMIO(0x203c)
1645
#define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
1646
#define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
1647
#define PRB1_START	_MMIO(0x2048) /* 915+ only */
1648
#define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2325 Serge 1649
#endif
6937 serge 1650
#define IPEIR_I965	_MMIO(0x2064)
1651
#define IPEHR_I965	_MMIO(0x2068)
1652
#define GEN7_SC_INSTDONE	_MMIO(0x7100)
1653
#define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
1654
#define GEN7_ROW_INSTDONE	_MMIO(0xe164)
3031 serge 1655
#define I915_NUM_INSTDONE_REG	4
6937 serge 1656
#define RING_IPEIR(base)	_MMIO((base)+0x64)
1657
#define RING_IPEHR(base)	_MMIO((base)+0x68)
6084 serge 1658
/*
1659
 * On GEN4, only the render ring INSTDONE exists and has a different
1660
 * layout than the GEN7+ version.
1661
 * The GEN2 counterpart of this register is GEN2_INSTDONE.
1662
 */
6937 serge 1663
#define RING_INSTDONE(base)	_MMIO((base)+0x6c)
1664
#define RING_INSTPS(base)	_MMIO((base)+0x70)
1665
#define RING_DMA_FADD(base)	_MMIO((base)+0x78)
1666
#define RING_DMA_FADD_UDW(base)	_MMIO((base)+0x60) /* gen8+ */
1667
#define RING_INSTPM(base)	_MMIO((base)+0xc0)
1668
#define RING_MI_MODE(base)	_MMIO((base)+0x9c)
1669
#define INSTPS		_MMIO(0x2070) /* 965+ only */
1670
#define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
1671
#define ACTHD_I965	_MMIO(0x2074)
1672
#define HWS_PGA		_MMIO(0x2080)
2325 Serge 1673
#define HWS_ADDRESS_MASK	0xfffff000
1674
#define HWS_START_ADDRESS_SHIFT	4
6937 serge 1675
#define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2325 Serge 1676
#define   PWRCTX_EN	(1<<0)
6937 serge 1677
#define IPEIR		_MMIO(0x2088)
1678
#define IPEHR		_MMIO(0x208c)
1679
#define GEN2_INSTDONE	_MMIO(0x2090)
1680
#define NOPID		_MMIO(0x2094)
1681
#define HWSTAM		_MMIO(0x2098)
1682
#define DMA_FADD_I8XX	_MMIO(0x20d0)
1683
#define RING_BBSTATE(base)	_MMIO((base)+0x110)
1684
#define   RING_BB_PPGTT		(1 << 5)
1685
#define RING_SBBADDR(base)	_MMIO((base)+0x114) /* hsw+ */
1686
#define RING_SBBSTATE(base)	_MMIO((base)+0x118) /* hsw+ */
1687
#define RING_SBBADDR_UDW(base)	_MMIO((base)+0x11c) /* gen8+ */
1688
#define RING_BBADDR(base)	_MMIO((base)+0x140)
1689
#define RING_BBADDR_UDW(base)	_MMIO((base)+0x168) /* gen8+ */
1690
#define RING_BB_PER_CTX_PTR(base)	_MMIO((base)+0x1c0) /* gen8+ */
1691
#define RING_INDIRECT_CTX(base)		_MMIO((base)+0x1c4) /* gen8+ */
1692
#define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base)+0x1c8) /* gen8+ */
1693
#define RING_CTX_TIMESTAMP(base)	_MMIO((base)+0x3a8) /* gen8+ */
2325 Serge 1694
 
6937 serge 1695
#define ERROR_GEN6	_MMIO(0x40a0)
1696
#define GEN7_ERR_INT	_MMIO(0x44040)
4104 Serge 1697
#define   ERR_INT_POISON		(1<<31)
6084 serge 1698
#define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
4560 Serge 1699
#define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)
4104 Serge 1700
#define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)
4560 Serge 1701
#define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)
4104 Serge 1702
#define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
4560 Serge 1703
#define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)
6084 serge 1704
#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + (pipe)*3))
4104 Serge 1705
#define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
6084 serge 1706
#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
2325 Serge 1707
 
6937 serge 1708
#define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
1709
#define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
6084 serge 1710
 
6937 serge 1711
#define FPGA_DBG		_MMIO(0x42300)
3746 Serge 1712
#define   FPGA_DBG_RM_NOCLAIM	(1<<31)
1713
 
6937 serge 1714
#define DERRMR		_MMIO(0x44050)
4560 Serge 1715
/* Note that HBLANK events are reserved on bdw+ */
4104 Serge 1716
#define   DERRMR_PIPEA_SCANLINE		(1<<0)
1717
#define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
1718
#define   DERRMR_PIPEA_SPR_FLIP_DONE	(1<<2)
1719
#define   DERRMR_PIPEA_VBLANK		(1<<3)
1720
#define   DERRMR_PIPEA_HBLANK		(1<<5)
1721
#define   DERRMR_PIPEB_SCANLINE 	(1<<8)
1722
#define   DERRMR_PIPEB_PRI_FLIP_DONE	(1<<9)
1723
#define   DERRMR_PIPEB_SPR_FLIP_DONE	(1<<10)
1724
#define   DERRMR_PIPEB_VBLANK		(1<<11)
1725
#define   DERRMR_PIPEB_HBLANK		(1<<13)
1726
/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1727
#define   DERRMR_PIPEC_SCANLINE		(1<<14)
1728
#define   DERRMR_PIPEC_PRI_FLIP_DONE	(1<<15)
1729
#define   DERRMR_PIPEC_SPR_FLIP_DONE	(1<<20)
1730
#define   DERRMR_PIPEC_VBLANK		(1<<21)
1731
#define   DERRMR_PIPEC_HBLANK		(1<<22)
3243 Serge 1732
 
4104 Serge 1733
 
2325 Serge 1734
/* GM45+ chicken bits -- debug workaround bits that may be required
1735
 * for various sorts of correct behavior.  The top 16 bits of each are
1736
 * the enables for writing to the corresponding low bit.
1737
 */
6937 serge 1738
#define _3D_CHICKEN	_MMIO(0x2084)
3243 Serge 1739
#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
6937 serge 1740
#define _3D_CHICKEN2	_MMIO(0x208c)
2325 Serge 1741
/* Disables pipelining of read flushes past the SF-WIZ interface.
1742
 * Required on all Ironlake steppings according to the B-Spec, but the
1743
 * particular danger of not doing so is not specified.
1744
 */
1745
# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
6937 serge 1746
#define _3D_CHICKEN3	_MMIO(0x2090)
3243 Serge 1747
#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
3031 serge 1748
#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
5060 serge 1749
#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
1750
#define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
2325 Serge 1751
 
6937 serge 1752
#define MI_MODE		_MMIO(0x209c)
2325 Serge 1753
# define VS_TIMER_DISPATCH				(1 << 6)
3031 serge 1754
# define MI_FLUSH_ENABLE				(1 << 12)
3243 Serge 1755
# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
5060 serge 1756
# define MODE_IDLE					(1 << 9)
1757
# define STOP_RING					(1 << 8)
2325 Serge 1758
 
6937 serge 1759
#define GEN6_GT_MODE	_MMIO(0x20d0)
1760
#define GEN7_GT_MODE	_MMIO(0x7008)
5060 serge 1761
#define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
1762
#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
1763
#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
1764
#define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
5354 serge 1765
#define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
3243 Serge 1766
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
6084 serge 1767
#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
1768
#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
3031 serge 1769
 
6937 serge 1770
#define GFX_MODE	_MMIO(0x2520)
1771
#define GFX_MODE_GEN7	_MMIO(0x229c)
1772
#define RING_MODE_GEN7(ring)	_MMIO((ring)->mmio_base+0x29c)
2325 Serge 1773
#define   GFX_RUN_LIST_ENABLE		(1<<15)
6084 serge 1774
#define   GFX_INTERRUPT_STEERING	(1<<14)
5060 serge 1775
#define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)
2325 Serge 1776
#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
1777
#define   GFX_REPLAY_MODE		(1<<11)
1778
#define   GFX_PSMI_GRANULARITY		(1<<10)
1779
#define   GFX_PPGTT_ENABLE		(1<<9)
6084 serge 1780
#define   GEN8_GFX_PPGTT_48B		(1<<7)
2325 Serge 1781
 
6084 serge 1782
#define   GFX_FORWARD_VBLANK_MASK	(3<<5)
1783
#define   GFX_FORWARD_VBLANK_NEVER	(0<<5)
1784
#define   GFX_FORWARD_VBLANK_ALWAYS	(1<<5)
1785
#define   GFX_FORWARD_VBLANK_COND	(2<<5)
1786
 
3031 serge 1787
#define VLV_DISPLAY_BASE 0x180000
5060 serge 1788
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
2325 Serge 1789
 
6937 serge 1790
#define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
1791
#define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
1792
#define SCPD0		_MMIO(0x209c) /* 915+ only */
1793
#define IER		_MMIO(0x20a0)
1794
#define IIR		_MMIO(0x20a4)
1795
#define IMR		_MMIO(0x20a8)
1796
#define ISR		_MMIO(0x20ac)
1797
#define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
5060 serge 1798
#define   GINT_DIS		(1<<22)
3243 Serge 1799
#define   GCFG_DIS		(1<<8)
6937 serge 1800
#define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
1801
#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
1802
#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
1803
#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
1804
#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
1805
#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
1806
#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
5060 serge 1807
#define VLV_PCBR_ADDR_SHIFT	12
1808
 
3746 Serge 1809
#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
6937 serge 1810
#define EIR		_MMIO(0x20b0)
1811
#define EMR		_MMIO(0x20b4)
1812
#define ESR		_MMIO(0x20b8)
2325 Serge 1813
#define   GM45_ERROR_PAGE_TABLE				(1<<5)
1814
#define   GM45_ERROR_MEM_PRIV				(1<<4)
1815
#define   I915_ERROR_PAGE_TABLE				(1<<4)
1816
#define   GM45_ERROR_CP_PRIV				(1<<3)
1817
#define   I915_ERROR_MEMORY_REFRESH			(1<<1)
1818
#define   I915_ERROR_INSTRUCTION			(1<<0)
6937 serge 1819
#define INSTPM	        _MMIO(0x20c0)
2325 Serge 1820
#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
5060 serge 1821
#define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
2325 Serge 1822
					will not assert AGPBUSY# and will only
1823
					be delivered when out of C3. */
2342 Serge 1824
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
4104 Serge 1825
#define   INSTPM_TLB_INVALIDATE	(1<<9)
1826
#define   INSTPM_SYNC_FLUSH	(1<<5)
6937 serge 1827
#define ACTHD	        _MMIO(0x20c8)
1828
#define MEM_MODE	_MMIO(0x20cc)
5354 serge 1829
#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1830
#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1831
#define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
6937 serge 1832
#define FW_BLC		_MMIO(0x20d8)
1833
#define FW_BLC2		_MMIO(0x20dc)
1834
#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2325 Serge 1835
#define   FW_BLC_SELF_EN_MASK      (1<<31)
1836
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
1837
#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
1838
#define MM_BURST_LENGTH     0x00700000
1839
#define MM_FIFO_WATERMARK   0x0001F000
1840
#define LM_BURST_LENGTH     0x00000700
1841
#define LM_FIFO_WATERMARK   0x0000001F
6937 serge 1842
#define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2325 Serge 1843
 
1844
/* Make render/texture TLB fetches lower priorty than associated data
1845
 *   fetches. This is not turned on by default
1846
 */
1847
#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
1848
 
1849
/* Isoch request wait on GTT enable (Display A/B/C streams).
1850
 * Make isoch requests stall on the TLB update. May cause
1851
 * display underruns (test mode only)
1852
 */
1853
#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
1854
 
1855
/* Block grant count for isoch requests when block count is
1856
 * set to a finite value.
1857
 */
1858
#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
1859
#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
1860
#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
1861
#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
1862
#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
1863
 
1864
/* Enable render writes to complete in C2/C3/C4 power states.
1865
 * If this isn't enabled, render writes are prevented in low
1866
 * power states. That seems bad to me.
1867
 */
1868
#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
1869
 
1870
/* This acknowledges an async flip immediately instead
1871
 * of waiting for 2TLB fetches.
1872
 */
1873
#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
1874
 
1875
/* Enables non-sequential data reads through arbiter
1876
 */
6084 serge 1877
#define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
2325 Serge 1878
 
1879
/* Disable FSB snooping of cacheable write cycles from binner/render
1880
 * command stream
1881
 */
1882
#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
1883
 
1884
/* Arbiter time slice for non-isoch streams */
1885
#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
1886
#define   MI_ARB_TIME_SLICE_1			(0 << 5)
1887
#define   MI_ARB_TIME_SLICE_2			(1 << 5)
1888
#define   MI_ARB_TIME_SLICE_4			(2 << 5)
1889
#define   MI_ARB_TIME_SLICE_6			(3 << 5)
1890
#define   MI_ARB_TIME_SLICE_8			(4 << 5)
1891
#define   MI_ARB_TIME_SLICE_10			(5 << 5)
1892
#define   MI_ARB_TIME_SLICE_14			(6 << 5)
1893
#define   MI_ARB_TIME_SLICE_16			(7 << 5)
1894
 
1895
/* Low priority grace period page size */
1896
#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
1897
#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
1898
 
1899
/* Disable display A/B trickle feed */
1900
#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
1901
 
1902
/* Set display plane priority */
1903
#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
1904
#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
1905
 
6937 serge 1906
#define MI_STATE	_MMIO(0x20e4) /* gen2 only */
5060 serge 1907
#define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
1908
#define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
1909
 
6937 serge 1910
#define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
3243 Serge 1911
#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2325 Serge 1912
#define   CM0_IZ_OPT_DISABLE      (1<<6)
1913
#define   CM0_ZR_OPT_DISABLE      (1<<5)
3031 serge 1914
#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
2325 Serge 1915
#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
1916
#define   CM0_COLOR_EVICT_DISABLE (1<<3)
1917
#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
1918
#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
6937 serge 1919
#define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
1920
#define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
3243 Serge 1921
#define   GFX_FLSH_CNTL_EN	(1<<0)
6937 serge 1922
#define ECOSKPD		_MMIO(0x21d0)
2325 Serge 1923
#define   ECO_GATING_CX_ONLY	(1<<3)
1924
#define   ECO_FLIP_DONE		(1<<0)
1925
 
6937 serge 1926
#define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
5060 serge 1927
#define RC_OP_FLUSH_ENABLE (1<<0)
1928
#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
6937 serge 1929
#define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
6084 serge 1930
#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
5060 serge 1931
#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
6084 serge 1932
#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
3031 serge 1933
 
6937 serge 1934
#define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
2325 Serge 1935
#define   GEN6_BLITTER_LOCK_SHIFT			16
1936
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
1937
 
6937 serge 1938
#define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
5354 serge 1939
#define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
5060 serge 1940
#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
1941
#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
1942
 
6084 serge 1943
/* Fuse readout registers for GT */
6937 serge 1944
#define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
6084 serge 1945
#define   CHV_FGT_DISABLE_SS0		(1 << 10)
1946
#define   CHV_FGT_DISABLE_SS1		(1 << 11)
1947
#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
1948
#define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1949
#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
1950
#define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1951
#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
1952
#define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1953
#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
1954
#define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1955
 
6937 serge 1956
#define GEN8_FUSE2			_MMIO(0x9120)
6084 serge 1957
#define   GEN8_F2_SS_DIS_SHIFT		21
1958
#define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
1959
#define   GEN8_F2_S_ENA_SHIFT		25
1960
#define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
1961
 
1962
#define   GEN9_F2_SS_DIS_SHIFT		20
1963
#define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
1964
 
6937 serge 1965
#define GEN8_EU_DISABLE0		_MMIO(0x9134)
6084 serge 1966
#define   GEN8_EU_DIS0_S0_MASK		0xffffff
1967
#define   GEN8_EU_DIS0_S1_SHIFT		24
1968
#define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
1969
 
6937 serge 1970
#define GEN8_EU_DISABLE1		_MMIO(0x9138)
6084 serge 1971
#define   GEN8_EU_DIS1_S1_MASK		0xffff
1972
#define   GEN8_EU_DIS1_S2_SHIFT		16
1973
#define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
1974
 
6937 serge 1975
#define GEN8_EU_DISABLE2		_MMIO(0x913c)
6084 serge 1976
#define   GEN8_EU_DIS2_S2_MASK		0xff
1977
 
6937 serge 1978
#define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
6084 serge 1979
 
6937 serge 1980
#define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
3031 serge 1981
#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
1982
#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
1983
#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
1984
#define   GEN6_BSD_GO_INDICATOR		(1 << 4)
2325 Serge 1985
 
4104 Serge 1986
/* On modern GEN architectures interrupt control consists of two sets
1987
 * of registers. The first set pertains to the ring generating the
1988
 * interrupt. The second control is for the functional block generating the
1989
 * interrupt. These are PM, GT, DE, etc.
1990
 *
1991
 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1992
 * GT interrupt bits, so we don't need to duplicate the defines.
1993
 *
1994
 * These defines should cover us well from SNB->HSW with minor exceptions
1995
 * it can also work on ILK.
1996
 */
1997
#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
1998
#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
1999
#define GT_BLT_USER_INTERRUPT			(1 << 22)
2000
#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
2001
#define GT_BSD_USER_INTERRUPT			(1 << 12)
4560 Serge 2002
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
5354 serge 2003
#define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
4104 Serge 2004
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
2005
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
2006
#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
2007
#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
2008
#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
2009
#define GT_RENDER_USER_INTERRUPT		(1 <<  0)
2325 Serge 2010
 
4104 Serge 2011
#define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
2012
#define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
2013
 
4560 Serge 2014
#define GT_PARITY_ERROR(dev) \
2015
	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2016
	 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2017
 
4104 Serge 2018
/* These are all the "old" interrupts */
2019
#define ILK_BSD_USER_INTERRUPT				(1<<5)
5060 serge 2020
 
2021
#define I915_PM_INTERRUPT				(1<<31)
2022
#define I915_ISP_INTERRUPT				(1<<22)
2023
#define I915_LPE_PIPE_B_INTERRUPT			(1<<21)
2024
#define I915_LPE_PIPE_A_INTERRUPT			(1<<20)
6084 serge 2025
#define I915_MIPIC_INTERRUPT				(1<<19)
5060 serge 2026
#define I915_MIPIA_INTERRUPT				(1<<18)
4104 Serge 2027
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
2028
#define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
5060 serge 2029
#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1<<16)
2030
#define I915_MASTER_ERROR_INTERRUPT			(1<<15)
4104 Serge 2031
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
5060 serge 2032
#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1<<14)
4104 Serge 2033
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
5060 serge 2034
#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1<<13)
4104 Serge 2035
#define I915_HWB_OOM_INTERRUPT				(1<<13)
5060 serge 2036
#define I915_LPE_PIPE_C_INTERRUPT			(1<<12)
4104 Serge 2037
#define I915_SYNC_STATUS_INTERRUPT			(1<<12)
5060 serge 2038
#define I915_MISC_INTERRUPT				(1<<11)
4104 Serge 2039
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
5060 serge 2040
#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1<<10)
4104 Serge 2041
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
5060 serge 2042
#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1<<9)
4104 Serge 2043
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
5060 serge 2044
#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1<<8)
4104 Serge 2045
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
2046
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
2047
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
2048
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
2049
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
5060 serge 2050
#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1<<3)
2051
#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1<<2)
4104 Serge 2052
#define I915_DEBUG_INTERRUPT				(1<<2)
5060 serge 2053
#define I915_WINVALID_INTERRUPT				(1<<1)
4104 Serge 2054
#define I915_USER_INTERRUPT				(1<<1)
2055
#define I915_ASLE_INTERRUPT				(1<<0)
5060 serge 2056
#define I915_BSD_USER_INTERRUPT				(1<<25)
4104 Serge 2057
 
6937 serge 2058
#define GEN6_BSD_RNCID			_MMIO(0x12198)
2325 Serge 2059
 
6937 serge 2060
#define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
3031 serge 2061
#define   GEN7_FF_SCHED_MASK		0x0077070
4560 Serge 2062
#define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
3031 serge 2063
#define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
2064
#define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
2065
#define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
2066
#define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
3480 Serge 2067
#define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
3031 serge 2068
#define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
2069
#define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
2070
#define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
2071
#define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
2072
#define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
2073
#define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
2074
#define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
2075
#define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
2076
 
2325 Serge 2077
/*
2078
 * Framebuffer compression (915+ only)
2079
 */
2080
 
6937 serge 2081
#define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
2082
#define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
2083
#define FBC_CONTROL		_MMIO(0x3208)
2325 Serge 2084
#define   FBC_CTL_EN		(1<<31)
2085
#define   FBC_CTL_PERIODIC	(1<<30)
2086
#define   FBC_CTL_INTERVAL_SHIFT (16)
2087
#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
2088
#define   FBC_CTL_C3_IDLE	(1<<13)
2089
#define   FBC_CTL_STRIDE_SHIFT	(5)
4560 Serge 2090
#define   FBC_CTL_FENCENO_SHIFT	(0)
6937 serge 2091
#define FBC_COMMAND		_MMIO(0x320c)
2325 Serge 2092
#define   FBC_CMD_COMPRESS	(1<<0)
6937 serge 2093
#define FBC_STATUS		_MMIO(0x3210)
2325 Serge 2094
#define   FBC_STAT_COMPRESSING	(1<<31)
2095
#define   FBC_STAT_COMPRESSED	(1<<30)
2096
#define   FBC_STAT_MODIFIED	(1<<29)
4560 Serge 2097
#define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
6937 serge 2098
#define FBC_CONTROL2		_MMIO(0x3214)
2325 Serge 2099
#define   FBC_CTL_FENCE_DBL	(0<<4)
2100
#define   FBC_CTL_IDLE_IMM	(0<<2)
2101
#define   FBC_CTL_IDLE_FULL	(1<<2)
2102
#define   FBC_CTL_IDLE_LINE	(2<<2)
2103
#define   FBC_CTL_IDLE_DEBUG	(3<<2)
2104
#define   FBC_CTL_CPU_FENCE	(1<<1)
5060 serge 2105
#define   FBC_CTL_PLANE(plane)	((plane)<<0)
6937 serge 2106
#define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
2107
#define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
2325 Serge 2108
 
6937 serge 2109
#define FBC_STATUS2		_MMIO(0x43214)
6084 serge 2110
#define  FBC_COMPRESSION_MASK	0x7ff
2111
 
2325 Serge 2112
#define FBC_LL_SIZE		(1536)
2113
 
2114
/* Framebuffer compression for GM45+ */
6937 serge 2115
#define DPFC_CB_BASE		_MMIO(0x3200)
2116
#define DPFC_CONTROL		_MMIO(0x3208)
2325 Serge 2117
#define   DPFC_CTL_EN		(1<<31)
5060 serge 2118
#define   DPFC_CTL_PLANE(plane)	((plane)<<30)
2119
#define   IVB_DPFC_CTL_PLANE(plane)	((plane)<<29)
2325 Serge 2120
#define   DPFC_CTL_FENCE_EN	(1<<29)
4104 Serge 2121
#define   IVB_DPFC_CTL_FENCE_EN	(1<<28)
2325 Serge 2122
#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
2123
#define   DPFC_SR_EN		(1<<10)
2124
#define   DPFC_CTL_LIMIT_1X	(0<<6)
2125
#define   DPFC_CTL_LIMIT_2X	(1<<6)
2126
#define   DPFC_CTL_LIMIT_4X	(2<<6)
6937 serge 2127
#define DPFC_RECOMP_CTL		_MMIO(0x320c)
2325 Serge 2128
#define   DPFC_RECOMP_STALL_EN	(1<<27)
2129
#define   DPFC_RECOMP_STALL_WM_SHIFT (16)
2130
#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2131
#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2132
#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
6937 serge 2133
#define DPFC_STATUS		_MMIO(0x3210)
2325 Serge 2134
#define   DPFC_INVAL_SEG_SHIFT  (16)
2135
#define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
2136
#define   DPFC_COMP_SEG_SHIFT	(0)
2137
#define   DPFC_COMP_SEG_MASK	(0x000003ff)
6937 serge 2138
#define DPFC_STATUS2		_MMIO(0x3214)
2139
#define DPFC_FENCE_YOFF		_MMIO(0x3218)
2140
#define DPFC_CHICKEN		_MMIO(0x3224)
2325 Serge 2141
#define   DPFC_HT_MODIFY	(1<<31)
2142
 
2143
/* Framebuffer compression for Ironlake */
6937 serge 2144
#define ILK_DPFC_CB_BASE	_MMIO(0x43200)
2145
#define ILK_DPFC_CONTROL	_MMIO(0x43208)
5354 serge 2146
#define   FBC_CTL_FALSE_COLOR	(1<<10)
2325 Serge 2147
/* The bit 28-8 is reserved */
2148
#define   DPFC_RESERVED		(0x1FFFFF00)
6937 serge 2149
#define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
2150
#define ILK_DPFC_STATUS		_MMIO(0x43210)
2151
#define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
2152
#define ILK_DPFC_CHICKEN	_MMIO(0x43224)
2153
#define ILK_FBC_RT_BASE		_MMIO(0x2128)
2325 Serge 2154
#define   ILK_FBC_RT_VALID	(1<<0)
4104 Serge 2155
#define   SNB_FBC_FRONT_BUFFER	(1<<1)
2325 Serge 2156
 
6937 serge 2157
#define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
2325 Serge 2158
#define   ILK_FBCQ_DIS		(1<<22)
6084 serge 2159
#define	  ILK_PABSTRETCH_DIS	(1<<21)
2325 Serge 2160
 
2161
 
2162
/*
2163
 * Framebuffer compression for Sandybridge
2164
 *
2165
 * The following two registers are of type GTTMMADR
2166
 */
6937 serge 2167
#define SNB_DPFC_CTL_SA		_MMIO(0x100100)
2325 Serge 2168
#define   SNB_CPU_FENCE_ENABLE	(1<<29)
6937 serge 2169
#define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
2325 Serge 2170
 
4104 Serge 2171
/* Framebuffer compression for Ivybridge */
6937 serge 2172
#define IVB_FBC_RT_BASE			_MMIO(0x7020)
2325 Serge 2173
 
6937 serge 2174
#define IPS_CTL		_MMIO(0x43408)
4104 Serge 2175
#define   IPS_ENABLE	(1 << 31)
2176
 
6937 serge 2177
#define MSG_FBC_REND_STATE	_MMIO(0x50380)
4104 Serge 2178
#define   FBC_REND_NUKE		(1<<2)
2179
#define   FBC_REND_CACHE_CLEAN	(1<<1)
2180
 
2325 Serge 2181
/*
2182
 * GPIO regs
2183
 */
6937 serge 2184
#define GPIOA			_MMIO(0x5010)
2185
#define GPIOB			_MMIO(0x5014)
2186
#define GPIOC			_MMIO(0x5018)
2187
#define GPIOD			_MMIO(0x501c)
2188
#define GPIOE			_MMIO(0x5020)
2189
#define GPIOF			_MMIO(0x5024)
2190
#define GPIOG			_MMIO(0x5028)
2191
#define GPIOH			_MMIO(0x502c)
2325 Serge 2192
# define GPIO_CLOCK_DIR_MASK		(1 << 0)
2193
# define GPIO_CLOCK_DIR_IN		(0 << 1)
2194
# define GPIO_CLOCK_DIR_OUT		(1 << 1)
2195
# define GPIO_CLOCK_VAL_MASK		(1 << 2)
2196
# define GPIO_CLOCK_VAL_OUT		(1 << 3)
2197
# define GPIO_CLOCK_VAL_IN		(1 << 4)
2198
# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
2199
# define GPIO_DATA_DIR_MASK		(1 << 8)
2200
# define GPIO_DATA_DIR_IN		(0 << 9)
2201
# define GPIO_DATA_DIR_OUT		(1 << 9)
2202
# define GPIO_DATA_VAL_MASK		(1 << 10)
2203
# define GPIO_DATA_VAL_OUT		(1 << 11)
2204
# define GPIO_DATA_VAL_IN		(1 << 12)
2205
# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
2206
 
6937 serge 2207
#define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2325 Serge 2208
#define   GMBUS_RATE_100KHZ	(0<<8)
2209
#define   GMBUS_RATE_50KHZ	(1<<8)
2210
#define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
2211
#define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
2212
#define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
6084 serge 2213
#define   GMBUS_PIN_DISABLED	0
2214
#define   GMBUS_PIN_SSC		1
2215
#define   GMBUS_PIN_VGADDC	2
2216
#define   GMBUS_PIN_PANEL	3
2217
#define   GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */
2218
#define   GMBUS_PIN_DPC		4 /* HDMIC */
2219
#define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
2220
#define   GMBUS_PIN_DPD		6 /* HDMID */
2221
#define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
2222
#define   GMBUS_PIN_1_BXT	1
2223
#define   GMBUS_PIN_2_BXT	2
2224
#define   GMBUS_PIN_3_BXT	3
2225
#define   GMBUS_NUM_PINS	7 /* including 0 */
6937 serge 2226
#define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2325 Serge 2227
#define   GMBUS_SW_CLR_INT	(1<<31)
2228
#define   GMBUS_SW_RDY		(1<<30)
2229
#define   GMBUS_ENT		(1<<29) /* enable timeout */
2230
#define   GMBUS_CYCLE_NONE	(0<<25)
2231
#define   GMBUS_CYCLE_WAIT	(1<<25)
2232
#define   GMBUS_CYCLE_INDEX	(2<<25)
2233
#define   GMBUS_CYCLE_STOP	(4<<25)
2234
#define   GMBUS_BYTE_COUNT_SHIFT 16
6084 serge 2235
#define   GMBUS_BYTE_COUNT_MAX   256U
2325 Serge 2236
#define   GMBUS_SLAVE_INDEX_SHIFT 8
2237
#define   GMBUS_SLAVE_ADDR_SHIFT 1
2238
#define   GMBUS_SLAVE_READ	(1<<0)
2239
#define   GMBUS_SLAVE_WRITE	(0<<0)
6937 serge 2240
#define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
2325 Serge 2241
#define   GMBUS_INUSE		(1<<15)
2242
#define   GMBUS_HW_WAIT_PHASE	(1<<14)
2243
#define   GMBUS_STALL_TIMEOUT	(1<<13)
2244
#define   GMBUS_INT		(1<<12)
2245
#define   GMBUS_HW_RDY		(1<<11)
2246
#define   GMBUS_SATOER		(1<<10)
2247
#define   GMBUS_ACTIVE		(1<<9)
6937 serge 2248
#define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2249
#define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2325 Serge 2250
#define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2251
#define   GMBUS_NAK_EN		(1<<3)
2252
#define   GMBUS_IDLE_EN		(1<<2)
2253
#define   GMBUS_HW_WAIT_EN	(1<<1)
2254
#define   GMBUS_HW_RDY_EN	(1<<0)
6937 serge 2255
#define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2325 Serge 2256
#define   GMBUS_2BYTE_INDEX_EN	(1<<31)
2257
 
2258
/*
2259
 * Clock control & power management
2260
 */
5060 serge 2261
#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2262
#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2263
#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
6937 serge 2264
#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2325 Serge 2265
 
6937 serge 2266
#define VGA0	_MMIO(0x6000)
2267
#define VGA1	_MMIO(0x6004)
2268
#define VGA_PD	_MMIO(0x6010)
2325 Serge 2269
#define   VGA0_PD_P2_DIV_4	(1 << 7)
2270
#define   VGA0_PD_P1_DIV_2	(1 << 5)
2271
#define   VGA0_PD_P1_SHIFT	0
2272
#define   VGA0_PD_P1_MASK	(0x1f << 0)
2273
#define   VGA1_PD_P2_DIV_4	(1 << 15)
2274
#define   VGA1_PD_P1_DIV_2	(1 << 13)
2275
#define   VGA1_PD_P1_SHIFT	8
2276
#define   VGA1_PD_P1_MASK	(0x1f << 8)
2277
#define   DPLL_VCO_ENABLE		(1 << 31)
4104 Serge 2278
#define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
2279
#define   DPLL_DVO_2X_MODE		(1 << 30)
3031 serge 2280
#define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
2325 Serge 2281
#define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
6084 serge 2282
#define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
2325 Serge 2283
#define   DPLL_VGA_MODE_DIS		(1 << 28)
2284
#define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
2285
#define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
2286
#define   DPLL_MODE_MASK		(3 << 26)
2287
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2288
#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2289
#define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
2290
#define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
2291
#define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
2292
#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
2293
#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3031 serge 2294
#define   DPLL_LOCK_VLV			(1<<15)
4104 Serge 2295
#define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
6084 serge 2296
#define   DPLL_INTEGRATED_REF_CLK_VLV	(1<<13)
2297
#define   DPLL_SSC_REF_CLK_CHV		(1<<13)
4104 Serge 2298
#define   DPLL_PORTC_READY_MASK		(0xf << 4)
2299
#define   DPLL_PORTB_READY_MASK		(0xf)
2325 Serge 2300
 
2301
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
5060 serge 2302
 
2303
/* Additional CHV pll/phy registers */
6937 serge 2304
#define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
5060 serge 2305
#define   DPLL_PORTD_READY_MASK		(0xf)
6937 serge 2306
#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
6084 serge 2307
#define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2*(phy)+(ch)+27))
2308
#define   PHY_LDO_DELAY_0NS			0x0
2309
#define   PHY_LDO_DELAY_200NS			0x1
2310
#define   PHY_LDO_DELAY_600NS			0x2
2311
#define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2*(phy)+23))
2312
#define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8*(phy)+4*(ch)+11))
2313
#define   PHY_CH_SU_PSR				0x1
2314
#define   PHY_CH_DEEP_PSR			0x7
2315
#define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6*(phy)+3*(ch)+2))
2316
#define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
6937 serge 2317
#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
5354 serge 2318
#define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
6084 serge 2319
#define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6-(6*(phy)+3*(ch))))
2320
#define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8-(6*(phy)+3*(ch)+(spline))))
5060 serge 2321
 
2325 Serge 2322
/*
2323
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2324
 * this field (only one bit may be set).
2325
 */
2326
#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
2327
#define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
2328
#define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2329
/* i830, required in DVO non-gang */
2330
#define   PLL_P2_DIVIDE_BY_4		(1 << 23)
2331
#define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
2332
#define   PLL_REF_INPUT_DREFCLK		(0 << 13)
2333
#define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
2334
#define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
2335
#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2336
#define   PLL_REF_INPUT_MASK		(3 << 13)
2337
#define   PLL_LOAD_PULSE_PHASE_SHIFT		9
2338
/* Ironlake */
2339
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
2340
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
2341
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
2342
# define DPLL_FPA1_P1_POST_DIV_SHIFT            0
2343
# define DPLL_FPA1_P1_POST_DIV_MASK             0xff
2344
 
2345
/*
2346
 * Parallel to Serial Load Pulse phase selection.
2347
 * Selects the phase for the 10X DPLL clock for the PCIe
2348
 * digital display port. The range is 4 to 13; 10 or more
2349
 * is just a flip delay. The default is 6
2350
 */
2351
#define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2352
#define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
2353
/*
2354
 * SDVO multiplier for 945G/GM. Not used on 965.
2355
 */
2356
#define   SDVO_MULTIPLIER_MASK			0x000000ff
2357
#define   SDVO_MULTIPLIER_SHIFT_HIRES		4
2358
#define   SDVO_MULTIPLIER_SHIFT_VGA		0
5060 serge 2359
 
2360
#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2361
#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2362
#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
6937 serge 2363
#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
5060 serge 2364
 
2325 Serge 2365
/*
2366
 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2367
 *
2368
 * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
2369
 */
2370
#define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
2371
#define   DPLL_MD_UDI_DIVIDER_SHIFT		24
2372
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2373
#define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
2374
#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
2375
/*
2376
 * SDVO/UDI pixel multiplier.
2377
 *
2378
 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2379
 * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
2380
 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2381
 * dummy bytes in the datastream at an increased clock rate, with both sides of
2382
 * the link knowing how many bytes are fill.
2383
 *
2384
 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2385
 * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
2386
 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2387
 * through an SDVO command.
2388
 *
2389
 * This register field has values of multiplication factor minus 1, with
2390
 * a maximum multiplier of 5 for SDVO.
2391
 */
2392
#define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
2393
#define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
2394
/*
2395
 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2396
 * This best be set to the default value (3) or the CRT won't work. No,
2397
 * I don't entirely understand what this does...
2398
 */
2399
#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
2400
#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3031 serge 2401
 
6937 serge 2402
#define _FPA0	0x6040
2403
#define _FPA1	0x6044
2404
#define _FPB0	0x6048
2405
#define _FPB1	0x604c
2406
#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
2407
#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
2325 Serge 2408
#define   FP_N_DIV_MASK		0x003f0000
2409
#define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
2410
#define   FP_N_DIV_SHIFT		16
2411
#define   FP_M1_DIV_MASK	0x00003f00
2412
#define   FP_M1_DIV_SHIFT		 8
2413
#define   FP_M2_DIV_MASK	0x0000003f
2414
#define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
2415
#define   FP_M2_DIV_SHIFT		 0
6937 serge 2416
#define DPLL_TEST	_MMIO(0x606c)
2325 Serge 2417
#define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
2418
#define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
2419
#define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
2420
#define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
2421
#define   DPLLB_TEST_N_BYPASS		(1 << 19)
2422
#define   DPLLB_TEST_M_BYPASS		(1 << 18)
2423
#define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
2424
#define   DPLLA_TEST_N_BYPASS		(1 << 3)
2425
#define   DPLLA_TEST_M_BYPASS		(1 << 2)
2426
#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
6937 serge 2427
#define D_STATE		_MMIO(0x6104)
2325 Serge 2428
#define  DSTATE_GFX_RESET_I830			(1<<6)
2429
#define  DSTATE_PLL_D3_OFF			(1<<3)
2430
#define  DSTATE_GFX_CLOCK_GATING		(1<<1)
2431
#define  DSTATE_DOT_CLOCK_GATING		(1<<0)
6937 serge 2432
#define DSPCLK_GATE_D	_MMIO(dev_priv->info.display_mmio_offset + 0x6200)
2325 Serge 2433
# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
2434
# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
2435
# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
2436
# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
2437
# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
2438
# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
2439
# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
2440
# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
2441
# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
2442
# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
2443
# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
2444
# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
2445
# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
2446
# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
2447
# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
2448
# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
2449
# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
2450
# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
2451
# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
2452
# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
2453
# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
2454
# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
2455
# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
2456
# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
2457
# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
2458
# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
2459
# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
2460
# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
5060 serge 2461
/*
2325 Serge 2462
 * This bit must be set on the 830 to prevent hangs when turning off the
2463
 * overlay scaler.
2464
 */
2465
# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
2466
# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
2467
# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
2468
# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
2469
# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
2470
 
6937 serge 2471
#define RENCLK_GATE_D1		_MMIO(0x6204)
2325 Serge 2472
# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
2473
# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
2474
# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
2475
# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
2476
# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
2477
# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
2478
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
2479
# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
2480
# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
5060 serge 2481
/* This bit must be unset on 855,865 */
2325 Serge 2482
# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
2483
# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
2484
# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
2485
# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
5060 serge 2486
/* This bit must be set on 855,865. */
2325 Serge 2487
# define SV_CLOCK_GATE_DISABLE			(1 << 0)
2488
# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
2489
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
2490
# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
2491
# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
2492
# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
2493
# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
2494
# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
2495
# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
2496
# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
2497
# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
2498
# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
2499
# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
2500
# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
2501
# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
2502
# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
2503
# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
2504
# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
2505
 
2506
# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
5060 serge 2507
/* This bit must always be set on 965G/965GM */
2325 Serge 2508
# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
2509
# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
2510
# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
2511
# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
2512
# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
2513
# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
5060 serge 2514
/* This bit must always be set on 965G */
2325 Serge 2515
# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
2516
# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
2517
# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
2518
# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
2519
# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
2520
# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
2521
# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
2522
# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
2523
# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
2524
# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
2525
# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
2526
# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
2527
# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
2528
# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
2529
# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
2530
# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
2531
# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
2532
# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
2533
# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
2534
 
6937 serge 2535
#define RENCLK_GATE_D2		_MMIO(0x6208)
2325 Serge 2536
#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
2537
#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
2538
#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
5060 serge 2539
 
6937 serge 2540
#define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
5060 serge 2541
#define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
2542
 
6937 serge 2543
#define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
2544
#define DEUC			_MMIO(0x6214)          /* CRL only */
2325 Serge 2545
 
6937 serge 2546
#define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3031 serge 2547
#define  FW_CSPWRDWNEN		(1<<15)
2548
 
6937 serge 2549
#define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
4104 Serge 2550
 
6937 serge 2551
#define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
4560 Serge 2552
#define   CDCLK_FREQ_SHIFT	4
2553
#define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
2554
#define   CZCLK_FREQ_MASK	0xf
6084 serge 2555
 
6937 serge 2556
#define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
6084 serge 2557
#define   PFI_CREDIT_63		(9 << 28)		/* chv only */
2558
#define   PFI_CREDIT_31		(8 << 28)		/* chv only */
2559
#define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
2560
#define   PFI_CREDIT_RESEND	(1 << 27)
2561
#define   VGA_FAST_MODE_DISABLE	(1 << 14)
2562
 
6937 serge 2563
#define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
4560 Serge 2564
 
2325 Serge 2565
/*
2566
 * Palette regs
2567
 */
5060 serge 2568
#define PALETTE_A_OFFSET 0xa000
2569
#define PALETTE_B_OFFSET 0xa800
2570
#define CHV_PALETTE_C_OFFSET 0xc000
6937 serge 2571
#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] +	\
6084 serge 2572
			  dev_priv->info.display_mmio_offset + (i) * 4)
2325 Serge 2573
 
2574
/* MCH MMIO space */
2575
 
2576
/*
2577
 * MCHBAR mirror.
2578
 *
2579
 * This mirrors the MCHBAR MMIO space whose location is determined by
2580
 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2581
 * every way.  It is not accessible from the CP register read instructions.
2582
 *
4560 Serge 2583
 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2584
 * just read.
2325 Serge 2585
 */
2586
#define MCHBAR_MIRROR_BASE	0x10000
2587
 
2588
#define MCHBAR_MIRROR_BASE_SNB	0x140000
2589
 
6937 serge 2590
#define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
2591
#define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
6084 serge 2592
#define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
2593
#define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
2594
 
3746 Serge 2595
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
6937 serge 2596
#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3746 Serge 2597
 
5060 serge 2598
/* 915-945 and GM965 MCH register controlling DRAM channel access */
6937 serge 2599
#define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
2325 Serge 2600
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
2601
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
2602
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
2603
#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
2604
#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
2605
#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
6937 serge 2606
#define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
5354 serge 2607
#define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
2325 Serge 2608
 
5060 serge 2609
/* Pineview MCH register contains DDR3 setting */
6937 serge 2610
#define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
2325 Serge 2611
#define CSHRDDR3CTL_DDR3       (1 << 2)
2612
 
5060 serge 2613
/* 965 MCH register controlling DRAM channel configuration */
6937 serge 2614
#define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
2615
#define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
2325 Serge 2616
 
5060 serge 2617
/* snb MCH registers for reading the DRAM channel configuration */
6937 serge 2618
#define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2619
#define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2620
#define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3031 serge 2621
#define   MAD_DIMM_ECC_MASK		(0x3 << 24)
2622
#define   MAD_DIMM_ECC_OFF		(0x0 << 24)
2623
#define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
2624
#define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
2625
#define   MAD_DIMM_ECC_ON		(0x3 << 24)
2626
#define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
2627
#define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
2628
#define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
2629
#define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
2630
#define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
2631
#define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
2632
#define   MAD_DIMM_A_SELECT		(0x1 << 16)
2633
/* DIMM sizes are in multiples of 256mb. */
2634
#define   MAD_DIMM_B_SIZE_SHIFT		8
2635
#define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
2636
#define   MAD_DIMM_A_SIZE_SHIFT		0
2637
#define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
2638
 
5060 serge 2639
/* snb MCH registers for priority tuning */
6937 serge 2640
#define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3480 Serge 2641
#define   MCH_SSKPD_WM0_MASK		0x3f
2642
#define   MCH_SSKPD_WM0_VAL		0xc
3031 serge 2643
 
6937 serge 2644
#define MCH_SECP_NRG_STTS		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
4104 Serge 2645
 
2325 Serge 2646
/* Clocking configuration register */
6937 serge 2647
#define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
2325 Serge 2648
#define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
2649
#define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
2650
#define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
2651
#define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
2652
#define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
2653
#define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
2654
/* Note, below two are guess */
2655
#define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
2656
#define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
2657
#define CLKCFG_FSB_MASK					(7 << 0)
2658
#define CLKCFG_MEM_533					(1 << 4)
2659
#define CLKCFG_MEM_667					(2 << 4)
2660
#define CLKCFG_MEM_800					(3 << 4)
2661
#define CLKCFG_MEM_MASK					(7 << 4)
2662
 
6937 serge 2663
#define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
2664
#define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
6084 serge 2665
 
6937 serge 2666
#define TSC1			_MMIO(0x11001)
2325 Serge 2667
#define   TSE			(1<<0)
6937 serge 2668
#define TR1			_MMIO(0x11006)
2669
#define TSFS			_MMIO(0x11020)
2325 Serge 2670
#define   TSFS_SLOPE_MASK	0x0000ff00
2671
#define   TSFS_SLOPE_SHIFT	8
2672
#define   TSFS_INTR_MASK	0x000000ff
2673
 
6937 serge 2674
#define CRSTANDVID		_MMIO(0x11100)
2675
#define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2325 Serge 2676
#define   PXVFREQ_PX_MASK	0x7f000000
2677
#define   PXVFREQ_PX_SHIFT	24
6937 serge 2678
#define VIDFREQ_BASE		_MMIO(0x11110)
2679
#define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2680
#define VIDFREQ2		_MMIO(0x11114)
2681
#define VIDFREQ3		_MMIO(0x11118)
2682
#define VIDFREQ4		_MMIO(0x1111c)
2325 Serge 2683
#define   VIDFREQ_P0_MASK	0x1f000000
2684
#define   VIDFREQ_P0_SHIFT	24
2685
#define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
2686
#define   VIDFREQ_P0_CSCLK_SHIFT 20
2687
#define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
2688
#define   VIDFREQ_P0_CRCLK_SHIFT 16
2689
#define   VIDFREQ_P1_MASK	0x00001f00
2690
#define   VIDFREQ_P1_SHIFT	8
2691
#define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
2692
#define   VIDFREQ_P1_CSCLK_SHIFT 4
2693
#define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
6937 serge 2694
#define INTTOEXT_BASE_ILK	_MMIO(0x11300)
2695
#define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
2325 Serge 2696
#define   INTTOEXT_MAP3_SHIFT	24
2697
#define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
2698
#define   INTTOEXT_MAP2_SHIFT	16
2699
#define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
2700
#define   INTTOEXT_MAP1_SHIFT	8
2701
#define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
2702
#define   INTTOEXT_MAP0_SHIFT	0
2703
#define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
6937 serge 2704
#define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
2325 Serge 2705
#define   MEMCTL_CMD_MASK	0xe000
2706
#define   MEMCTL_CMD_SHIFT	13
2707
#define   MEMCTL_CMD_RCLK_OFF	0
2708
#define   MEMCTL_CMD_RCLK_ON	1
2709
#define   MEMCTL_CMD_CHFREQ	2
2710
#define   MEMCTL_CMD_CHVID	3
2711
#define   MEMCTL_CMD_VMMOFF	4
2712
#define   MEMCTL_CMD_VMMON	5
2713
#define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
2714
					   when command complete */
2715
#define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
2716
#define   MEMCTL_FREQ_SHIFT	8
2717
#define   MEMCTL_SFCAVM		(1<<7)
2718
#define   MEMCTL_TGT_VID_MASK	0x007f
6937 serge 2719
#define MEMIHYST		_MMIO(0x1117c)
2720
#define MEMINTREN		_MMIO(0x11180) /* 16 bits */
2325 Serge 2721
#define   MEMINT_RSEXIT_EN	(1<<8)
2722
#define   MEMINT_CX_SUPR_EN	(1<<7)
2723
#define   MEMINT_CONT_BUSY_EN	(1<<6)
2724
#define   MEMINT_AVG_BUSY_EN	(1<<5)
2725
#define   MEMINT_EVAL_CHG_EN	(1<<4)
2726
#define   MEMINT_MON_IDLE_EN	(1<<3)
2727
#define   MEMINT_UP_EVAL_EN	(1<<2)
2728
#define   MEMINT_DOWN_EVAL_EN	(1<<1)
2729
#define   MEMINT_SW_CMD_EN	(1<<0)
6937 serge 2730
#define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
2325 Serge 2731
#define   MEM_RSEXIT_MASK	0xc000
2732
#define   MEM_RSEXIT_SHIFT	14
2733
#define   MEM_CONT_BUSY_MASK	0x3000
2734
#define   MEM_CONT_BUSY_SHIFT	12
2735
#define   MEM_AVG_BUSY_MASK	0x0c00
2736
#define   MEM_AVG_BUSY_SHIFT	10
2737
#define   MEM_EVAL_CHG_MASK	0x0300
2738
#define   MEM_EVAL_BUSY_SHIFT	8
2739
#define   MEM_MON_IDLE_MASK	0x00c0
2740
#define   MEM_MON_IDLE_SHIFT	6
2741
#define   MEM_UP_EVAL_MASK	0x0030
2742
#define   MEM_UP_EVAL_SHIFT	4
2743
#define   MEM_DOWN_EVAL_MASK	0x000c
2744
#define   MEM_DOWN_EVAL_SHIFT	2
2745
#define   MEM_SW_CMD_MASK	0x0003
2746
#define   MEM_INT_STEER_GFX	0
2747
#define   MEM_INT_STEER_CMR	1
2748
#define   MEM_INT_STEER_SMI	2
2749
#define   MEM_INT_STEER_SCI	3
6937 serge 2750
#define MEMINTRSTS		_MMIO(0x11184)
2325 Serge 2751
#define   MEMINT_RSEXIT		(1<<7)
2752
#define   MEMINT_CONT_BUSY	(1<<6)
2753
#define   MEMINT_AVG_BUSY	(1<<5)
2754
#define   MEMINT_EVAL_CHG	(1<<4)
2755
#define   MEMINT_MON_IDLE	(1<<3)
2756
#define   MEMINT_UP_EVAL	(1<<2)
2757
#define   MEMINT_DOWN_EVAL	(1<<1)
2758
#define   MEMINT_SW_CMD		(1<<0)
6937 serge 2759
#define MEMMODECTL		_MMIO(0x11190)
2325 Serge 2760
#define   MEMMODE_BOOST_EN	(1<<31)
2761
#define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2762
#define   MEMMODE_BOOST_FREQ_SHIFT 24
2763
#define   MEMMODE_IDLE_MODE_MASK 0x00030000
2764
#define   MEMMODE_IDLE_MODE_SHIFT 16
2765
#define   MEMMODE_IDLE_MODE_EVAL 0
2766
#define   MEMMODE_IDLE_MODE_CONT 1
2767
#define   MEMMODE_HWIDLE_EN	(1<<15)
2768
#define   MEMMODE_SWMODE_EN	(1<<14)
2769
#define   MEMMODE_RCLK_GATE	(1<<13)
2770
#define   MEMMODE_HW_UPDATE	(1<<12)
2771
#define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
2772
#define   MEMMODE_FSTART_SHIFT	8
2773
#define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
2774
#define   MEMMODE_FMAX_SHIFT	4
2775
#define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
6937 serge 2776
#define RCBMAXAVG		_MMIO(0x1119c)
2777
#define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
2325 Serge 2778
#define   SWMEMCMD_RENDER_OFF	(0 << 13)
2779
#define   SWMEMCMD_RENDER_ON	(1 << 13)
2780
#define   SWMEMCMD_SWFREQ	(2 << 13)
2781
#define   SWMEMCMD_TARVID	(3 << 13)
2782
#define   SWMEMCMD_VRM_OFF	(4 << 13)
2783
#define   SWMEMCMD_VRM_ON	(5 << 13)
2784
#define   CMDSTS		(1<<12)
2785
#define   SFCAVM		(1<<11)
2786
#define   SWFREQ_MASK		0x0380 /* P0-7 */
2787
#define   SWFREQ_SHIFT		7
2788
#define   TARVID_MASK		0x001f
6937 serge 2789
#define MEMSTAT_CTG		_MMIO(0x111a0)
2790
#define RCBMINAVG		_MMIO(0x111a0)
2791
#define RCUPEI			_MMIO(0x111b0)
2792
#define RCDNEI			_MMIO(0x111b4)
2793
#define RSTDBYCTL		_MMIO(0x111b8)
2325 Serge 2794
#define   RS1EN			(1<<31)
2795
#define   RS2EN			(1<<30)
2796
#define   RS3EN			(1<<29)
2797
#define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
2798
#define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
2799
#define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
2800
#define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
2801
#define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
2802
#define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
2803
#define   RSX_STATUS_MASK	(7<<20)
2804
#define   RSX_STATUS_ON		(0<<20)
2805
#define   RSX_STATUS_RC1	(1<<20)
2806
#define   RSX_STATUS_RC1E	(2<<20)
2807
#define   RSX_STATUS_RS1	(3<<20)
2808
#define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
2809
#define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
2810
#define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
2811
#define   RSX_STATUS_RSVD2	(7<<20)
2812
#define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
2813
#define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
2814
#define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
2815
#define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
2816
#define   RS1CONTSAV_MASK	(3<<14)
2817
#define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
2818
#define   RS1CONTSAV_RSVD	(1<<14)
2819
#define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
2820
#define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
2821
#define   NORMSLEXLAT_MASK	(3<<12)
2822
#define   SLOW_RS123		(0<<12)
2823
#define   SLOW_RS23		(1<<12)
2824
#define   SLOW_RS3		(2<<12)
2825
#define   NORMAL_RS123		(3<<12)
2826
#define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
2827
#define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2828
#define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
2829
#define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
2830
#define   RS_CSTATE_MASK	(3<<4)
2831
#define   RS_CSTATE_C367_RS1	(0<<4)
2832
#define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2833
#define   RS_CSTATE_RSVD	(2<<4)
2834
#define   RS_CSTATE_C367_RS2	(3<<4)
2835
#define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
2836
#define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
6937 serge 2837
#define VIDCTL			_MMIO(0x111c0)
2838
#define VIDSTS			_MMIO(0x111c8)
2839
#define VIDSTART		_MMIO(0x111cc) /* 8 bits */
2840
#define MEMSTAT_ILK		_MMIO(0x111f8)
2325 Serge 2841
#define   MEMSTAT_VID_MASK	0x7f00
2842
#define   MEMSTAT_VID_SHIFT	8
2843
#define   MEMSTAT_PSTATE_MASK	0x00f8
2844
#define   MEMSTAT_PSTATE_SHIFT  3
2845
#define   MEMSTAT_MON_ACTV	(1<<2)
2846
#define   MEMSTAT_SRC_CTL_MASK	0x0003
2847
#define   MEMSTAT_SRC_CTL_CORE	0
2848
#define   MEMSTAT_SRC_CTL_TRB	1
2849
#define   MEMSTAT_SRC_CTL_THM	2
2850
#define   MEMSTAT_SRC_CTL_STDBY 3
6937 serge 2851
#define RCPREVBSYTUPAVG		_MMIO(0x113b8)
2852
#define RCPREVBSYTDNAVG		_MMIO(0x113bc)
2853
#define PMMISC			_MMIO(0x11214)
2325 Serge 2854
#define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
6937 serge 2855
#define SDEW			_MMIO(0x1124c)
2856
#define CSIEW0			_MMIO(0x11250)
2857
#define CSIEW1			_MMIO(0x11254)
2858
#define CSIEW2			_MMIO(0x11258)
2859
#define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
2860
#define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
2861
#define MCHAFE			_MMIO(0x112c0)
2862
#define CSIEC			_MMIO(0x112e0)
2863
#define DMIEC			_MMIO(0x112e4)
2864
#define DDREC			_MMIO(0x112e8)
2865
#define PEG0EC			_MMIO(0x112ec)
2866
#define PEG1EC			_MMIO(0x112f0)
2867
#define GFXEC			_MMIO(0x112f4)
2868
#define RPPREVBSYTUPAVG		_MMIO(0x113b8)
2869
#define RPPREVBSYTDNAVG		_MMIO(0x113bc)
2870
#define ECR			_MMIO(0x11600)
2325 Serge 2871
#define   ECR_GPFE		(1<<31)
2872
#define   ECR_IMONE		(1<<30)
2873
#define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
6937 serge 2874
#define OGW0			_MMIO(0x11608)
2875
#define OGW1			_MMIO(0x1160c)
2876
#define EG0			_MMIO(0x11610)
2877
#define EG1			_MMIO(0x11614)
2878
#define EG2			_MMIO(0x11618)
2879
#define EG3			_MMIO(0x1161c)
2880
#define EG4			_MMIO(0x11620)
2881
#define EG5			_MMIO(0x11624)
2882
#define EG6			_MMIO(0x11628)
2883
#define EG7			_MMIO(0x1162c)
2884
#define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
2885
#define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
2886
#define LCFUSE02		_MMIO(0x116c0)
2325 Serge 2887
#define   LCFUSE_HIV_MASK	0x000000ff
6937 serge 2888
#define CSIPLL0			_MMIO(0x12c10)
2889
#define DDRMPLL1		_MMIO(0X12c20)
2890
#define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
2325 Serge 2891
 
6937 serge 2892
#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3031 serge 2893
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2894
 
6937 serge 2895
#define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2896
#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
2897
#define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2898
#define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2899
#define BXT_RP_STATE_CAP        _MMIO(0x138170)
2325 Serge 2900
 
6660 serge 2901
/*
2902
 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2903
 * 8300) freezing up around GPU hangs. Looks as if even
2904
 * scheduling/timer interrupts start misbehaving if the RPS
2905
 * EI/thresholds are "bad", leading to a very sluggish or even
2906
 * frozen machine.
2907
 */
2908
#define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
6084 serge 2909
#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
2910
#define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
2911
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2912
				(IS_BROXTON(dev_priv) ? \
2913
				INTERVAL_0_833_US(us) : \
2914
				INTERVAL_1_33_US(us)) : \
2915
				INTERVAL_1_28_US(us))
2916
 
2325 Serge 2917
/*
2918
 * Logical Context regs
2919
 */
6937 serge 2920
#define CCID			_MMIO(0x2180)
2325 Serge 2921
#define   CCID_EN		(1<<0)
4104 Serge 2922
/*
2923
 * Notes on SNB/IVB/VLV context size:
2924
 * - Power context is saved elsewhere (LLC or stolen)
2925
 * - Ring/execlist context is saved on SNB, not on IVB
2926
 * - Extended context size already includes render context size
2927
 * - We always need to follow the extended context size.
2928
 *   SNB BSpec has comments indicating that we should use the
2929
 *   render context size instead if execlists are disabled, but
2930
 *   based on empirical testing that's just nonsense.
2931
 * - Pipelined/VF state is saved on SNB/IVB respectively
2932
 * - GT1 size just indicates how much of render context
2933
 *   doesn't need saving on GT1
2934
 */
6937 serge 2935
#define CXT_SIZE		_MMIO(0x21a0)
6084 serge 2936
#define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
2937
#define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
2938
#define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
2939
#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
2940
#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
4104 Serge 2941
#define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
3031 serge 2942
					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2943
					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
6937 serge 2944
#define GEN7_CXT_SIZE		_MMIO(0x21a8)
6084 serge 2945
#define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
2946
#define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
2947
#define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
2948
#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
2949
#define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
2950
#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
4104 Serge 2951
#define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3031 serge 2952
					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4104 Serge 2953
/* Haswell does have the CXT_SIZE register however it does not appear to be
2954
 * valid. Now, docs explain in dwords what is in the context object. The full
2955
 * size is 70720 bytes, however, the power context and execlist context will
2956
 * never be saved (power context is stored elsewhere, and execlists don't work
6084 serge 2957
 * on HSW) - so the final size, including the extra state required for the
2958
 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
4104 Serge 2959
 */
2960
#define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
4560 Serge 2961
/* Same as Haswell, but 72064 bytes now. */
2962
#define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
3031 serge 2963
 
6937 serge 2964
#define CHV_CLK_CTL1			_MMIO(0x101100)
2965
#define VLV_CLK_CTL2			_MMIO(0x101104)
4560 Serge 2966
#define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
2967
 
2325 Serge 2968
/*
2969
 * Overlay regs
2970
 */
2971
 
6937 serge 2972
#define OVADD			_MMIO(0x30000)
2973
#define DOVSTA			_MMIO(0x30008)
2325 Serge 2974
#define OC_BUF			(0x3<<20)
6937 serge 2975
#define OGAMC5			_MMIO(0x30010)
2976
#define OGAMC4			_MMIO(0x30014)
2977
#define OGAMC3			_MMIO(0x30018)
2978
#define OGAMC2			_MMIO(0x3001c)
2979
#define OGAMC1			_MMIO(0x30020)
2980
#define OGAMC0			_MMIO(0x30024)
2325 Serge 2981
 
2982
/*
6937 serge 2983
 * GEN9 clock gating regs
2984
 */
2985
#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
2986
#define   PWM2_GATING_DIS		(1 << 14)
2987
#define   PWM1_GATING_DIS		(1 << 13)
2988
 
2989
/*
2325 Serge 2990
 * Display engine regs
2991
 */
2992
 
4560 Serge 2993
/* Pipe A CRC regs */
5060 serge 2994
#define _PIPE_CRC_CTL_A			0x60050
4560 Serge 2995
#define   PIPE_CRC_ENABLE		(1 << 31)
2996
/* ivb+ source selection */
2997
#define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
2998
#define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
2999
#define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
3000
/* ilk+ source selection */
3001
#define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
3002
#define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
3003
#define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
3004
/* embedded DP port on the north display block, reserved on ivb */
3005
#define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
3006
#define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
3007
/* vlv source selection */
3008
#define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
3009
#define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
3010
#define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
3011
/* with DP port the pipe source is invalid */
3012
#define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
3013
#define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
3014
#define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
3015
/* gen3+ source selection */
3016
#define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
3017
#define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
3018
#define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
3019
/* with DP/TV port the pipe source is invalid */
3020
#define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
3021
#define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
3022
#define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
3023
#define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
3024
#define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
3025
/* gen2 doesn't have source selection bits */
3026
#define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
3027
 
3028
#define _PIPE_CRC_RES_1_A_IVB		0x60064
3029
#define _PIPE_CRC_RES_2_A_IVB		0x60068
3030
#define _PIPE_CRC_RES_3_A_IVB		0x6006c
3031
#define _PIPE_CRC_RES_4_A_IVB		0x60070
3032
#define _PIPE_CRC_RES_5_A_IVB		0x60074
3033
 
5060 serge 3034
#define _PIPE_CRC_RES_RED_A		0x60060
3035
#define _PIPE_CRC_RES_GREEN_A		0x60064
3036
#define _PIPE_CRC_RES_BLUE_A		0x60068
3037
#define _PIPE_CRC_RES_RES1_A_I915	0x6006c
3038
#define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4560 Serge 3039
 
3040
/* Pipe B CRC regs */
3041
#define _PIPE_CRC_RES_1_B_IVB		0x61064
3042
#define _PIPE_CRC_RES_2_B_IVB		0x61068
3043
#define _PIPE_CRC_RES_3_B_IVB		0x6106c
3044
#define _PIPE_CRC_RES_4_B_IVB		0x61070
3045
#define _PIPE_CRC_RES_5_B_IVB		0x61074
3046
 
6937 serge 3047
#define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3048
#define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3049
#define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3050
#define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3051
#define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3052
#define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4560 Serge 3053
 
6937 serge 3054
#define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3055
#define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3056
#define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3057
#define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3058
#define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4560 Serge 3059
 
2325 Serge 3060
/* Pipe A timing regs */
5060 serge 3061
#define _HTOTAL_A	0x60000
3062
#define _HBLANK_A	0x60004
3063
#define _HSYNC_A	0x60008
3064
#define _VTOTAL_A	0x6000c
3065
#define _VBLANK_A	0x60010
3066
#define _VSYNC_A	0x60014
3067
#define _PIPEASRC	0x6001c
3068
#define _BCLRPAT_A	0x60020
3069
#define _VSYNCSHIFT_A	0x60028
5354 serge 3070
#define _PIPE_MULT_A	0x6002c
2325 Serge 3071
 
3072
/* Pipe B timing regs */
5060 serge 3073
#define _HTOTAL_B	0x61000
3074
#define _HBLANK_B	0x61004
3075
#define _HSYNC_B	0x61008
3076
#define _VTOTAL_B	0x6100c
3077
#define _VBLANK_B	0x61010
3078
#define _VSYNC_B	0x61014
3079
#define _PIPEBSRC	0x6101c
3080
#define _BCLRPAT_B	0x61020
3081
#define _VSYNCSHIFT_B	0x61028
5354 serge 3082
#define _PIPE_MULT_B	0x6102c
2325 Serge 3083
 
5060 serge 3084
#define TRANSCODER_A_OFFSET 0x60000
3085
#define TRANSCODER_B_OFFSET 0x61000
3086
#define TRANSCODER_C_OFFSET 0x62000
3087
#define CHV_TRANSCODER_C_OFFSET 0x63000
3088
#define TRANSCODER_EDP_OFFSET 0x6f000
2325 Serge 3089
 
6937 serge 3090
#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
5060 serge 3091
	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3092
	dev_priv->info.display_mmio_offset)
3093
 
6937 serge 3094
#define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
3095
#define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
3096
#define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
3097
#define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
3098
#define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
3099
#define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
3100
#define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
3101
#define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
3102
#define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
3103
#define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
5060 serge 3104
 
6084 serge 3105
/* VLV eDP PSR registers */
3106
#define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
3107
#define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
3108
#define  VLV_EDP_PSR_ENABLE			(1<<0)
3109
#define  VLV_EDP_PSR_RESET			(1<<1)
3110
#define  VLV_EDP_PSR_MODE_MASK			(7<<2)
3111
#define  VLV_EDP_PSR_MODE_HW_TIMER		(1<<3)
3112
#define  VLV_EDP_PSR_MODE_SW_TIMER		(1<<2)
3113
#define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1<<7)
3114
#define  VLV_EDP_PSR_ACTIVE_ENTRY		(1<<8)
3115
#define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1<<9)
3116
#define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
3117
#define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
3118
#define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
6937 serge 3119
#define VLV_PSRCTL(pipe)	_MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
6084 serge 3120
 
3121
#define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
3122
#define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
3123
#define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
3124
#define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
3125
#define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
6937 serge 3126
#define VLV_VSCSDP(pipe)	_MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
6084 serge 3127
 
3128
#define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
3129
#define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
3130
#define  VLV_EDP_PSR_LAST_STATE_MASK	(7<<3)
3131
#define  VLV_EDP_PSR_CURR_STATE_MASK	7
3132
#define  VLV_EDP_PSR_DISABLED		(0<<0)
3133
#define  VLV_EDP_PSR_INACTIVE		(1<<0)
3134
#define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2<<0)
3135
#define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3<<0)
3136
#define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
3137
#define  VLV_EDP_PSR_EXIT		(5<<0)
3138
#define  VLV_EDP_PSR_IN_TRANS		(1<<7)
6937 serge 3139
#define VLV_PSRSTAT(pipe)	_MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
6084 serge 3140
 
4560 Serge 3141
/* HSW+ eDP PSR registers */
6937 serge 3142
#define HSW_EDP_PSR_BASE	0x64800
3143
#define BDW_EDP_PSR_BASE	0x6f800
3144
#define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)
4104 Serge 3145
#define   EDP_PSR_ENABLE			(1<<31)
5060 serge 3146
#define   BDW_PSR_SINGLE_FRAME			(1<<30)
4104 Serge 3147
#define   EDP_PSR_LINK_STANDBY			(1<<27)
3148
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
3149
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
3150
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1<<25)
3151
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2<<25)
3152
#define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3<<25)
3153
#define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
3154
#define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
3155
#define   EDP_PSR_TP1_TP2_SEL			(0<<11)
3156
#define   EDP_PSR_TP1_TP3_SEL			(1<<11)
3157
#define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
3158
#define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
3159
#define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
3160
#define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
3161
#define   EDP_PSR_TP1_TIME_500us		(0<<4)
3162
#define   EDP_PSR_TP1_TIME_100us		(1<<4)
3163
#define   EDP_PSR_TP1_TIME_2500us		(2<<4)
3164
#define   EDP_PSR_TP1_TIME_0us			(3<<4)
3165
#define   EDP_PSR_IDLE_FRAME_SHIFT		0
3166
 
6937 serge 3167
#define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
3168
#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4104 Serge 3169
 
6937 serge 3170
#define EDP_PSR_STATUS_CTL			_MMIO(dev_priv->psr_mmio_base + 0x40)
4104 Serge 3171
#define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
3172
#define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
3173
#define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
3174
#define   EDP_PSR_STATUS_STATE_SRDENT		(2<<29)
3175
#define   EDP_PSR_STATUS_STATE_BUFOFF		(3<<29)
3176
#define   EDP_PSR_STATUS_STATE_BUFON		(4<<29)
3177
#define   EDP_PSR_STATUS_STATE_AUXACK		(5<<29)
3178
#define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6<<29)
3179
#define   EDP_PSR_STATUS_LINK_MASK		(3<<26)
3180
#define   EDP_PSR_STATUS_LINK_FULL_OFF		(0<<26)
3181
#define   EDP_PSR_STATUS_LINK_FULL_ON		(1<<26)
3182
#define   EDP_PSR_STATUS_LINK_STANDBY		(2<<26)
3183
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
3184
#define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
3185
#define   EDP_PSR_STATUS_COUNT_SHIFT		16
3186
#define   EDP_PSR_STATUS_COUNT_MASK		0xf
3187
#define   EDP_PSR_STATUS_AUX_ERROR		(1<<15)
3188
#define   EDP_PSR_STATUS_AUX_SENDING		(1<<12)
3189
#define   EDP_PSR_STATUS_SENDING_IDLE		(1<<9)
3190
#define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1<<8)
3191
#define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
3192
#define   EDP_PSR_STATUS_IDLE_MASK		0xf
3193
 
6937 serge 3194
#define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
4104 Serge 3195
#define   EDP_PSR_PERF_CNT_MASK		0xffffff
3196
 
6937 serge 3197
#define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
4104 Serge 3198
#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
3199
#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
3200
#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
3201
 
6937 serge 3202
#define EDP_PSR2_CTL			_MMIO(0x6f900)
6084 serge 3203
#define   EDP_PSR2_ENABLE		(1<<31)
3204
#define   EDP_SU_TRACK_ENABLE		(1<<30)
3205
#define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
3206
#define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
3207
#define   EDP_PSR2_TP2_TIME_500		(0<<8)
3208
#define   EDP_PSR2_TP2_TIME_100		(1<<8)
3209
#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
3210
#define   EDP_PSR2_TP2_TIME_50		(3<<8)
3211
#define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
3212
#define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3213
#define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
3214
#define   EDP_PSR2_IDLE_MASK		0xf
3215
 
2325 Serge 3216
/* VGA port control */
6937 serge 3217
#define ADPA			_MMIO(0x61100)
3218
#define PCH_ADPA                _MMIO(0xe1100)
3219
#define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
3031 serge 3220
 
2325 Serge 3221
#define   ADPA_DAC_ENABLE	(1<<31)
3222
#define   ADPA_DAC_DISABLE	0
3223
#define   ADPA_PIPE_SELECT_MASK	(1<<30)
3224
#define   ADPA_PIPE_A_SELECT	0
3225
#define   ADPA_PIPE_B_SELECT	(1<<30)
3226
#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3031 serge 3227
/* CPT uses bits 29:30 for pch transcoder select */
3228
#define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
3229
#define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
3230
#define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
3231
#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3232
#define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
3233
#define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
3234
#define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
3235
#define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
3236
#define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
3237
#define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
3238
#define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
3239
#define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
3240
#define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
3241
#define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
3242
#define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
3243
#define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
3244
#define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
3245
#define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
3246
#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2325 Serge 3247
#define   ADPA_USE_VGA_HVPOLARITY (1<<15)
3248
#define   ADPA_SETS_HVPOLARITY	0
3480 Serge 3249
#define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
2325 Serge 3250
#define   ADPA_VSYNC_CNTL_ENABLE 0
3480 Serge 3251
#define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
2325 Serge 3252
#define   ADPA_HSYNC_CNTL_ENABLE 0
3253
#define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3254
#define   ADPA_VSYNC_ACTIVE_LOW	0
3255
#define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3256
#define   ADPA_HSYNC_ACTIVE_LOW	0
3257
#define   ADPA_DPMS_MASK	(~(3<<10))
3258
#define   ADPA_DPMS_ON		(0<<10)
3259
#define   ADPA_DPMS_SUSPEND	(1<<10)
3260
#define   ADPA_DPMS_STANDBY	(2<<10)
3261
#define   ADPA_DPMS_OFF		(3<<10)
3262
 
3263
 
3264
/* Hotplug control (945+ only) */
6937 serge 3265
#define PORT_HOTPLUG_EN		_MMIO(dev_priv->info.display_mmio_offset + 0x61110)
3480 Serge 3266
#define   PORTB_HOTPLUG_INT_EN			(1 << 29)
3267
#define   PORTC_HOTPLUG_INT_EN			(1 << 28)
3268
#define   PORTD_HOTPLUG_INT_EN			(1 << 27)
2325 Serge 3269
#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
3270
#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
3271
#define   TV_HOTPLUG_INT_EN			(1 << 18)
3272
#define   CRT_HOTPLUG_INT_EN			(1 << 9)
3746 Serge 3273
#define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
3274
						 PORTC_HOTPLUG_INT_EN | \
3275
						 PORTD_HOTPLUG_INT_EN | \
3276
						 SDVOC_HOTPLUG_INT_EN | \
3277
						 SDVOB_HOTPLUG_INT_EN | \
3278
						 CRT_HOTPLUG_INT_EN)
2325 Serge 3279
#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
3280
#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
3281
/* must use period 64 on GM45 according to docs */
3282
#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
3283
#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
3284
#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
3285
#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
3286
#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
3287
#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
3288
#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
3289
#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
3290
#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
3291
#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
3292
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
3293
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
3294
 
6937 serge 3295
#define PORT_HOTPLUG_STAT	_MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4104 Serge 3296
/*
6660 serge 3297
 * HDMI/DP bits are g4x+
4104 Serge 3298
 *
3299
 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3300
 * Please check the detailed lore in the commit message for for experimental
3301
 * evidence.
3302
 */
6660 serge 3303
/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3304
#define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
3305
#define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
3306
#define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
3307
/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3308
#define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
4560 Serge 3309
#define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
6660 serge 3310
#define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
3480 Serge 3311
#define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
5060 serge 3312
#define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
3313
#define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
3480 Serge 3314
#define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
5060 serge 3315
#define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
3316
#define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
3480 Serge 3317
#define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
5060 serge 3318
#define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
3319
#define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
3031 serge 3320
/* CRT/TV common between gen3+ */
2325 Serge 3321
#define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
3322
#define   TV_HOTPLUG_INT_STATUS			(1 << 10)
3323
#define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
3324
#define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
3325
#define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
3326
#define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4560 Serge 3327
#define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
3328
#define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
3329
#define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
3330
#define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
3331
 
3031 serge 3332
/* SDVO is different across gen3/4 */
3333
#define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
3334
#define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4104 Serge 3335
/*
3336
 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3337
 * since reality corrobates that they're the same as on gen3. But keep these
3338
 * bits here (and the comment!) to help any other lost wanderers back onto the
3339
 * right tracks.
3340
 */
3031 serge 3341
#define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
3342
#define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
3343
#define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
3344
#define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
3746 Serge 3345
#define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
3346
						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3347
						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3348
						 PORTB_HOTPLUG_INT_STATUS | \
3349
						 PORTC_HOTPLUG_INT_STATUS | \
3350
						 PORTD_HOTPLUG_INT_STATUS)
2325 Serge 3351
 
3746 Serge 3352
#define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
3353
						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3354
						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3355
						 PORTB_HOTPLUG_INT_STATUS | \
3356
						 PORTC_HOTPLUG_INT_STATUS | \
3357
						 PORTD_HOTPLUG_INT_STATUS)
3358
 
3359
/* SDVO and HDMI port control.
3360
 * The same register may be used for SDVO or HDMI */
6937 serge 3361
#define _GEN3_SDVOB	0x61140
3362
#define _GEN3_SDVOC	0x61160
3363
#define GEN3_SDVOB	_MMIO(_GEN3_SDVOB)
3364
#define GEN3_SDVOC	_MMIO(_GEN3_SDVOC)
3746 Serge 3365
#define GEN4_HDMIB	GEN3_SDVOB
3366
#define GEN4_HDMIC	GEN3_SDVOC
6937 serge 3367
#define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
3368
#define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
3369
#define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
3370
#define PCH_SDVOB	_MMIO(0xe1140)
3746 Serge 3371
#define PCH_HDMIB	PCH_SDVOB
6937 serge 3372
#define PCH_HDMIC	_MMIO(0xe1150)
3373
#define PCH_HDMID	_MMIO(0xe1160)
3746 Serge 3374
 
6937 serge 3375
#define PORT_DFT_I9XX				_MMIO(0x61150)
4560 Serge 3376
#define   DC_BALANCE_RESET			(1 << 25)
6937 serge 3377
#define PORT_DFT2_G4X		_MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4560 Serge 3378
#define   DC_BALANCE_RESET_VLV			(1 << 31)
6084 serge 3379
#define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
3380
#define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
4560 Serge 3381
#define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
3382
#define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
3383
 
3746 Serge 3384
/* Gen 3 SDVO bits: */
6084 serge 3385
#define   SDVO_ENABLE				(1 << 31)
3746 Serge 3386
#define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
3387
#define   SDVO_PIPE_SEL_MASK			(1 << 30)
6084 serge 3388
#define   SDVO_PIPE_B_SELECT			(1 << 30)
3389
#define   SDVO_STALL_SELECT			(1 << 29)
3390
#define   SDVO_INTERRUPT_ENABLE			(1 << 26)
5060 serge 3391
/*
2325 Serge 3392
 * 915G/GM SDVO pixel multiplier.
3393
 * Programmed value is multiplier - 1, up to 5x.
3394
 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3395
 */
6084 serge 3396
#define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
2325 Serge 3397
#define   SDVO_PORT_MULTIPLY_SHIFT		23
6084 serge 3398
#define   SDVO_PHASE_SELECT_MASK		(15 << 19)
3399
#define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
3400
#define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
3746 Serge 3401
#define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
3402
#define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
3403
#define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
3404
#define   SDVO_DETECTED				(1 << 2)
3405
/* Bits to be preserved when writing */
3406
#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3407
			       SDVO_INTERRUPT_ENABLE)
3408
#define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3409
 
3410
/* Gen 4 SDVO/HDMI bits: */
3411
#define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
4560 Serge 3412
#define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
3746 Serge 3413
#define   SDVO_ENCODING_SDVO			(0 << 10)
3414
#define   SDVO_ENCODING_HDMI			(2 << 10)
3415
#define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
3416
#define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
3417
#define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
6084 serge 3418
#define   SDVO_AUDIO_ENABLE			(1 << 6)
3746 Serge 3419
/* VSYNC/HSYNC bits new with 965, default is to be set */
6084 serge 3420
#define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
3421
#define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
2325 Serge 3422
 
3746 Serge 3423
/* Gen 5 (IBX) SDVO/HDMI bits: */
3424
#define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
3425
#define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
3426
 
3427
/* Gen 6 (CPT) SDVO/HDMI bits: */
3428
#define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
3429
#define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
3430
 
5060 serge 3431
/* CHV SDVO/HDMI bits: */
3432
#define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
3433
#define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
3746 Serge 3434
 
5060 serge 3435
 
2325 Serge 3436
/* DVO port control */
6937 serge 3437
#define _DVOA			0x61120
3438
#define DVOA			_MMIO(_DVOA)
3439
#define _DVOB			0x61140
3440
#define DVOB			_MMIO(_DVOB)
3441
#define _DVOC			0x61160
3442
#define DVOC			_MMIO(_DVOC)
2325 Serge 3443
#define   DVO_ENABLE			(1 << 31)
3444
#define   DVO_PIPE_B_SELECT		(1 << 30)
3445
#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
3446
#define   DVO_PIPE_STALL		(1 << 28)
3447
#define   DVO_PIPE_STALL_TV		(2 << 28)
3448
#define   DVO_PIPE_STALL_MASK		(3 << 28)
3449
#define   DVO_USE_VGA_SYNC		(1 << 15)
3450
#define   DVO_DATA_ORDER_I740		(0 << 14)
3451
#define   DVO_DATA_ORDER_FP		(1 << 14)
3452
#define   DVO_VSYNC_DISABLE		(1 << 11)
3453
#define   DVO_HSYNC_DISABLE		(1 << 10)
3454
#define   DVO_VSYNC_TRISTATE		(1 << 9)
3455
#define   DVO_HSYNC_TRISTATE		(1 << 8)
3456
#define   DVO_BORDER_ENABLE		(1 << 7)
3457
#define   DVO_DATA_ORDER_GBRG		(1 << 6)
3458
#define   DVO_DATA_ORDER_RGGB		(0 << 6)
3459
#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
3460
#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
3461
#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
3462
#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
3463
#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
3464
#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
3465
#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
3466
#define   DVO_PRESERVE_MASK		(0x7<<24)
6937 serge 3467
#define DVOA_SRCDIM		_MMIO(0x61124)
3468
#define DVOB_SRCDIM		_MMIO(0x61144)
3469
#define DVOC_SRCDIM		_MMIO(0x61164)
2325 Serge 3470
#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
3471
#define   DVO_SRCDIM_VERTICAL_SHIFT	0
3472
 
3473
/* LVDS port control */
6937 serge 3474
#define LVDS			_MMIO(0x61180)
2325 Serge 3475
/*
3476
 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
3477
 * the DPLL semantics change when the LVDS is assigned to that pipe.
3478
 */
3479
#define   LVDS_PORT_EN			(1 << 31)
3480
/* Selects pipe B for LVDS data.  Must be set on pre-965. */
3481
#define   LVDS_PIPEB_SELECT		(1 << 30)
3482
#define   LVDS_PIPE_MASK		(1 << 30)
3483
#define   LVDS_PIPE(pipe)		((pipe) << 30)
3484
/* LVDS dithering flag on 965/g4x platform */
3485
#define   LVDS_ENABLE_DITHER		(1 << 25)
3486
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
3487
#define   LVDS_VSYNC_POLARITY		(1 << 21)
3488
#define   LVDS_HSYNC_POLARITY		(1 << 20)
3489
 
3490
/* Enable border for unscaled (or aspect-scaled) display */
3491
#define   LVDS_BORDER_ENABLE		(1 << 15)
3492
/*
3493
 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3494
 * pixel.
3495
 */
3496
#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
3497
#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
3498
#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
3499
/*
3500
 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3501
 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3502
 * on.
3503
 */
3504
#define   LVDS_A3_POWER_MASK		(3 << 6)
3505
#define   LVDS_A3_POWER_DOWN		(0 << 6)
3506
#define   LVDS_A3_POWER_UP		(3 << 6)
3507
/*
3508
 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
3509
 * is set.
3510
 */
3511
#define   LVDS_CLKB_POWER_MASK		(3 << 4)
3512
#define   LVDS_CLKB_POWER_DOWN		(0 << 4)
3513
#define   LVDS_CLKB_POWER_UP		(3 << 4)
3514
/*
3515
 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
3516
 * setting for whether we are in dual-channel mode.  The B3 pair will
3517
 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3518
 */
3519
#define   LVDS_B0B3_POWER_MASK		(3 << 2)
3520
#define   LVDS_B0B3_POWER_DOWN		(0 << 2)
3521
#define   LVDS_B0B3_POWER_UP		(3 << 2)
3522
 
3523
/* Video Data Island Packet control */
6937 serge 3524
#define VIDEO_DIP_DATA		_MMIO(0x61178)
6084 serge 3525
/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3031 serge 3526
 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3527
 * of the infoframe structure specified by CEA-861. */
3528
#define   VIDEO_DIP_DATA_SIZE	32
4104 Serge 3529
#define   VIDEO_DIP_VSC_DATA_SIZE	36
6937 serge 3530
#define VIDEO_DIP_CTL		_MMIO(0x61170)
3031 serge 3531
/* Pre HSW: */
2325 Serge 3532
#define   VIDEO_DIP_ENABLE		(1 << 31)
5060 serge 3533
#define   VIDEO_DIP_PORT(port)		((port) << 29)
3031 serge 3534
#define   VIDEO_DIP_PORT_MASK		(3 << 29)
3535
#define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
2325 Serge 3536
#define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
3537
#define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
3031 serge 3538
#define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
2325 Serge 3539
#define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
3540
#define   VIDEO_DIP_SELECT_AVI		(0 << 19)
3541
#define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
3542
#define   VIDEO_DIP_SELECT_SPD		(3 << 19)
3543
#define   VIDEO_DIP_SELECT_MASK		(3 << 19)
3544
#define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
3545
#define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
3546
#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
3031 serge 3547
#define   VIDEO_DIP_FREQ_MASK		(3 << 16)
3548
/* HSW and later: */
3549
#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
3550
#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
3551
#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
3552
#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
3553
#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
3554
#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2325 Serge 3555
 
3556
/* Panel power sequencing */
6937 serge 3557
#define PP_STATUS	_MMIO(0x61200)
2325 Serge 3558
#define   PP_ON		(1 << 31)
3559
/*
3560
 * Indicates that all dependencies of the panel are on:
3561
 *
3562
 * - PLL enabled
3563
 * - pipe enabled
3564
 * - LVDS/DVOB/DVOC on
3565
 */
3566
#define   PP_READY		(1 << 30)
3567
#define   PP_SEQUENCE_NONE	(0 << 28)
2342 Serge 3568
#define   PP_SEQUENCE_POWER_UP	(1 << 28)
3569
#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
3570
#define   PP_SEQUENCE_MASK	(3 << 28)
3571
#define   PP_SEQUENCE_SHIFT	28
2325 Serge 3572
#define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
3573
#define   PP_SEQUENCE_STATE_MASK 0x0000000f
2342 Serge 3574
#define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
3575
#define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
3576
#define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
3577
#define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
3578
#define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
3579
#define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
3580
#define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
3581
#define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
3582
#define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
6937 serge 3583
#define PP_CONTROL	_MMIO(0x61204)
2325 Serge 3584
#define   POWER_TARGET_ON	(1 << 0)
6937 serge 3585
#define PP_ON_DELAYS	_MMIO(0x61208)
3586
#define PP_OFF_DELAYS	_MMIO(0x6120c)
3587
#define PP_DIVISOR	_MMIO(0x61210)
2325 Serge 3588
 
3589
/* Panel fitting */
6937 serge 3590
#define PFIT_CONTROL	_MMIO(dev_priv->info.display_mmio_offset + 0x61230)
2325 Serge 3591
#define   PFIT_ENABLE		(1 << 31)
3592
#define   PFIT_PIPE_MASK	(3 << 29)
3593
#define   PFIT_PIPE_SHIFT	29
3594
#define   VERT_INTERP_DISABLE	(0 << 10)
3595
#define   VERT_INTERP_BILINEAR	(1 << 10)
3596
#define   VERT_INTERP_MASK	(3 << 10)
3597
#define   VERT_AUTO_SCALE	(1 << 9)
3598
#define   HORIZ_INTERP_DISABLE	(0 << 6)
3599
#define   HORIZ_INTERP_BILINEAR	(1 << 6)
3600
#define   HORIZ_INTERP_MASK	(3 << 6)
3601
#define   HORIZ_AUTO_SCALE	(1 << 5)
3602
#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
3603
#define   PFIT_FILTER_FUZZY	(0 << 24)
3604
#define   PFIT_SCALING_AUTO	(0 << 26)
3605
#define   PFIT_SCALING_PROGRAMMED (1 << 26)
3606
#define   PFIT_SCALING_PILLAR	(2 << 26)
3607
#define   PFIT_SCALING_LETTER	(3 << 26)
6937 serge 3608
#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
2325 Serge 3609
/* Pre-965 */
3610
#define		PFIT_VERT_SCALE_SHIFT		20
3611
#define		PFIT_VERT_SCALE_MASK		0xfff00000
3612
#define		PFIT_HORIZ_SCALE_SHIFT		4
3613
#define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
3614
/* 965+ */
3615
#define		PFIT_VERT_SCALE_SHIFT_965	16
3616
#define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
3617
#define		PFIT_HORIZ_SCALE_SHIFT_965	0
3618
#define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
3619
 
6937 serge 3620
#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
2325 Serge 3621
 
5060 serge 3622
#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3623
#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
6937 serge 3624
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4560 Serge 3625
				     _VLV_BLC_PWM_CTL2_B)
3626
 
5060 serge 3627
#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3628
#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
6937 serge 3629
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4560 Serge 3630
				    _VLV_BLC_PWM_CTL_B)
3631
 
5060 serge 3632
#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3633
#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
6937 serge 3634
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4560 Serge 3635
				     _VLV_BLC_HIST_CTL_B)
3636
 
2325 Serge 3637
/* Backlight control */
6937 serge 3638
#define BLC_PWM_CTL2	_MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3031 serge 3639
#define   BLM_PWM_ENABLE		(1 << 31)
3640
#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
3641
#define   BLM_PIPE_SELECT		(1 << 29)
3642
#define   BLM_PIPE_SELECT_IVB		(3 << 29)
3643
#define   BLM_PIPE_A			(0 << 29)
3644
#define   BLM_PIPE_B			(1 << 29)
3645
#define   BLM_PIPE_C			(2 << 29) /* ivb + */
4104 Serge 3646
#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
3647
#define   BLM_TRANSCODER_B		BLM_PIPE_B
3648
#define   BLM_TRANSCODER_C		BLM_PIPE_C
3649
#define   BLM_TRANSCODER_EDP		(3 << 29)
3031 serge 3650
#define   BLM_PIPE(pipe)		((pipe) << 29)
3651
#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
3652
#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
3653
#define   BLM_PHASE_IN_ENABLE		(1 << 25)
3654
#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
3655
#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
3656
#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
3657
#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
3658
#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
3659
#define   BLM_PHASE_IN_INCR_SHIFT	(0)
3660
#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
6937 serge 3661
#define BLC_PWM_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61254)
2325 Serge 3662
/*
3663
 * This is the most significant 15 bits of the number of backlight cycles in a
3664
 * complete cycle of the modulated backlight control.
3665
 *
3666
 * The actual value is this field multiplied by two.
3667
 */
3031 serge 3668
#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
6084 serge 3669
#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
3031 serge 3670
#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
2325 Serge 3671
/*
3672
 * This is the number of cycles out of the backlight modulation cycle for which
3673
 * the backlight is on.
3674
 *
3675
 * This field must be no greater than the number of cycles in the complete
3676
 * backlight modulation cycle.
3677
 */
3678
#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
3679
#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
3031 serge 3680
#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
3681
#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
2325 Serge 3682
 
6937 serge 3683
#define BLC_HIST_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61260)
6084 serge 3684
#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
2325 Serge 3685
 
3031 serge 3686
/* New registers for PCH-split platforms. Safe where new bits show up, the
3687
 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
6937 serge 3688
#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
3689
#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
3031 serge 3690
 
6937 serge 3691
#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
4104 Serge 3692
 
3031 serge 3693
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3694
 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
6937 serge 3695
#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
3031 serge 3696
#define   BLM_PCH_PWM_ENABLE			(1 << 31)
3697
#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
3698
#define   BLM_PCH_POLARITY			(1 << 29)
6937 serge 3699
#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
3031 serge 3700
 
6937 serge 3701
#define UTIL_PIN_CTL		_MMIO(0x48400)
4104 Serge 3702
#define   UTIL_PIN_ENABLE	(1 << 31)
3703
 
6084 serge 3704
#define   UTIL_PIN_PIPE(x)     ((x) << 29)
3705
#define   UTIL_PIN_PIPE_MASK   (3 << 29)
3706
#define   UTIL_PIN_MODE_PWM    (1 << 24)
3707
#define   UTIL_PIN_MODE_MASK   (0xf << 24)
3708
#define   UTIL_PIN_POLARITY    (1 << 22)
3709
 
3710
/* BXT backlight register definition. */
3711
#define _BXT_BLC_PWM_CTL1			0xC8250
3712
#define   BXT_BLC_PWM_ENABLE			(1 << 31)
3713
#define   BXT_BLC_PWM_POLARITY			(1 << 29)
3714
#define _BXT_BLC_PWM_FREQ1			0xC8254
3715
#define _BXT_BLC_PWM_DUTY1			0xC8258
3716
 
3717
#define _BXT_BLC_PWM_CTL2			0xC8350
3718
#define _BXT_BLC_PWM_FREQ2			0xC8354
3719
#define _BXT_BLC_PWM_DUTY2			0xC8358
3720
 
6937 serge 3721
#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
6084 serge 3722
					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
6937 serge 3723
#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
6084 serge 3724
					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
6937 serge 3725
#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
6084 serge 3726
					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3727
 
6937 serge 3728
#define PCH_GTC_CTL		_MMIO(0xe7000)
4104 Serge 3729
#define   PCH_GTC_ENABLE	(1 << 31)
3730
 
2325 Serge 3731
/* TV port control */
6937 serge 3732
#define TV_CTL			_MMIO(0x68000)
5060 serge 3733
/* Enables the TV encoder */
2325 Serge 3734
# define TV_ENC_ENABLE			(1 << 31)
5060 serge 3735
/* Sources the TV encoder input from pipe B instead of A. */
2325 Serge 3736
# define TV_ENC_PIPEB_SELECT		(1 << 30)
5060 serge 3737
/* Outputs composite video (DAC A only) */
2325 Serge 3738
# define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
5060 serge 3739
/* Outputs SVideo video (DAC B/C) */
2325 Serge 3740
# define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
5060 serge 3741
/* Outputs Component video (DAC A/B/C) */
2325 Serge 3742
# define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
5060 serge 3743
/* Outputs Composite and SVideo (DAC A/B/C) */
2325 Serge 3744
# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
3745
# define TV_TRILEVEL_SYNC		(1 << 21)
5060 serge 3746
/* Enables slow sync generation (945GM only) */
2325 Serge 3747
# define TV_SLOW_SYNC			(1 << 20)
5060 serge 3748
/* Selects 4x oversampling for 480i and 576p */
2325 Serge 3749
# define TV_OVERSAMPLE_4X		(0 << 18)
5060 serge 3750
/* Selects 2x oversampling for 720p and 1080i */
2325 Serge 3751
# define TV_OVERSAMPLE_2X		(1 << 18)
5060 serge 3752
/* Selects no oversampling for 1080p */
2325 Serge 3753
# define TV_OVERSAMPLE_NONE		(2 << 18)
5060 serge 3754
/* Selects 8x oversampling */
2325 Serge 3755
# define TV_OVERSAMPLE_8X		(3 << 18)
5060 serge 3756
/* Selects progressive mode rather than interlaced */
2325 Serge 3757
# define TV_PROGRESSIVE			(1 << 17)
5060 serge 3758
/* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
2325 Serge 3759
# define TV_PAL_BURST			(1 << 16)
5060 serge 3760
/* Field for setting delay of Y compared to C */
2325 Serge 3761
# define TV_YC_SKEW_MASK		(7 << 12)
5060 serge 3762
/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
2325 Serge 3763
# define TV_ENC_SDP_FIX			(1 << 11)
5060 serge 3764
/*
2325 Serge 3765
 * Enables a fix for the 915GM only.
3766
 *
3767
 * Not sure what it does.
3768
 */
3769
# define TV_ENC_C0_FIX			(1 << 10)
5060 serge 3770
/* Bits that must be preserved by software */
2325 Serge 3771
# define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3772
# define TV_FUSE_STATE_MASK		(3 << 4)
5060 serge 3773
/* Read-only state that reports all features enabled */
2325 Serge 3774
# define TV_FUSE_STATE_ENABLED		(0 << 4)
5060 serge 3775
/* Read-only state that reports that Macrovision is disabled in hardware*/
2325 Serge 3776
# define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
5060 serge 3777
/* Read-only state that reports that TV-out is disabled in hardware. */
2325 Serge 3778
# define TV_FUSE_STATE_DISABLED		(2 << 4)
5060 serge 3779
/* Normal operation */
2325 Serge 3780
# define TV_TEST_MODE_NORMAL		(0 << 0)
5060 serge 3781
/* Encoder test pattern 1 - combo pattern */
2325 Serge 3782
# define TV_TEST_MODE_PATTERN_1		(1 << 0)
5060 serge 3783
/* Encoder test pattern 2 - full screen vertical 75% color bars */
2325 Serge 3784
# define TV_TEST_MODE_PATTERN_2		(2 << 0)
5060 serge 3785
/* Encoder test pattern 3 - full screen horizontal 75% color bars */
2325 Serge 3786
# define TV_TEST_MODE_PATTERN_3		(3 << 0)
5060 serge 3787
/* Encoder test pattern 4 - random noise */
2325 Serge 3788
# define TV_TEST_MODE_PATTERN_4		(4 << 0)
5060 serge 3789
/* Encoder test pattern 5 - linear color ramps */
2325 Serge 3790
# define TV_TEST_MODE_PATTERN_5		(5 << 0)
5060 serge 3791
/*
2325 Serge 3792
 * This test mode forces the DACs to 50% of full output.
3793
 *
3794
 * This is used for load detection in combination with TVDAC_SENSE_MASK
3795
 */
3796
# define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
3797
# define TV_TEST_MODE_MASK		(7 << 0)
3798
 
6937 serge 3799
#define TV_DAC			_MMIO(0x68004)
2325 Serge 3800
# define TV_DAC_SAVE		0x00ffff00
5060 serge 3801
/*
2325 Serge 3802
 * Reports that DAC state change logic has reported change (RO).
3803
 *
3804
 * This gets cleared when TV_DAC_STATE_EN is cleared
3805
*/
3806
# define TVDAC_STATE_CHG		(1 << 31)
3807
# define TVDAC_SENSE_MASK		(7 << 28)
5060 serge 3808
/* Reports that DAC A voltage is above the detect threshold */
2325 Serge 3809
# define TVDAC_A_SENSE			(1 << 30)
5060 serge 3810
/* Reports that DAC B voltage is above the detect threshold */
2325 Serge 3811
# define TVDAC_B_SENSE			(1 << 29)
5060 serge 3812
/* Reports that DAC C voltage is above the detect threshold */
2325 Serge 3813
# define TVDAC_C_SENSE			(1 << 28)
5060 serge 3814
/*
2325 Serge 3815
 * Enables DAC state detection logic, for load-based TV detection.
3816
 *
3817
 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3818
 * to off, for load detection to work.
3819
 */
3820
# define TVDAC_STATE_CHG_EN		(1 << 27)
5060 serge 3821
/* Sets the DAC A sense value to high */
2325 Serge 3822
# define TVDAC_A_SENSE_CTL		(1 << 26)
5060 serge 3823
/* Sets the DAC B sense value to high */
2325 Serge 3824
# define TVDAC_B_SENSE_CTL		(1 << 25)
5060 serge 3825
/* Sets the DAC C sense value to high */
2325 Serge 3826
# define TVDAC_C_SENSE_CTL		(1 << 24)
5060 serge 3827
/* Overrides the ENC_ENABLE and DAC voltage levels */
2325 Serge 3828
# define DAC_CTL_OVERRIDE		(1 << 7)
5060 serge 3829
/* Sets the slew rate.  Must be preserved in software */
2325 Serge 3830
# define ENC_TVDAC_SLEW_FAST		(1 << 6)
3831
# define DAC_A_1_3_V			(0 << 4)
3832
# define DAC_A_1_1_V			(1 << 4)
3833
# define DAC_A_0_7_V			(2 << 4)
3834
# define DAC_A_MASK			(3 << 4)
3835
# define DAC_B_1_3_V			(0 << 2)
3836
# define DAC_B_1_1_V			(1 << 2)
3837
# define DAC_B_0_7_V			(2 << 2)
3838
# define DAC_B_MASK			(3 << 2)
3839
# define DAC_C_1_3_V			(0 << 0)
3840
# define DAC_C_1_1_V			(1 << 0)
3841
# define DAC_C_0_7_V			(2 << 0)
3842
# define DAC_C_MASK			(3 << 0)
3843
 
5060 serge 3844
/*
2325 Serge 3845
 * CSC coefficients are stored in a floating point format with 9 bits of
3846
 * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
3847
 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3848
 * -1 (0x3) being the only legal negative value.
3849
 */
6937 serge 3850
#define TV_CSC_Y		_MMIO(0x68010)
2325 Serge 3851
# define TV_RY_MASK			0x07ff0000
3852
# define TV_RY_SHIFT			16
3853
# define TV_GY_MASK			0x00000fff
3854
# define TV_GY_SHIFT			0
3855
 
6937 serge 3856
#define TV_CSC_Y2		_MMIO(0x68014)
2325 Serge 3857
# define TV_BY_MASK			0x07ff0000
3858
# define TV_BY_SHIFT			16
5060 serge 3859
/*
2325 Serge 3860
 * Y attenuation for component video.
3861
 *
3862
 * Stored in 1.9 fixed point.
3863
 */
3864
# define TV_AY_MASK			0x000003ff
3865
# define TV_AY_SHIFT			0
3866
 
6937 serge 3867
#define TV_CSC_U		_MMIO(0x68018)
2325 Serge 3868
# define TV_RU_MASK			0x07ff0000
3869
# define TV_RU_SHIFT			16
3870
# define TV_GU_MASK			0x000007ff
3871
# define TV_GU_SHIFT			0
3872
 
6937 serge 3873
#define TV_CSC_U2		_MMIO(0x6801c)
2325 Serge 3874
# define TV_BU_MASK			0x07ff0000
3875
# define TV_BU_SHIFT			16
5060 serge 3876
/*
2325 Serge 3877
 * U attenuation for component video.
3878
 *
3879
 * Stored in 1.9 fixed point.
3880
 */
3881
# define TV_AU_MASK			0x000003ff
3882
# define TV_AU_SHIFT			0
3883
 
6937 serge 3884
#define TV_CSC_V		_MMIO(0x68020)
2325 Serge 3885
# define TV_RV_MASK			0x0fff0000
3886
# define TV_RV_SHIFT			16
3887
# define TV_GV_MASK			0x000007ff
3888
# define TV_GV_SHIFT			0
3889
 
6937 serge 3890
#define TV_CSC_V2		_MMIO(0x68024)
2325 Serge 3891
# define TV_BV_MASK			0x07ff0000
3892
# define TV_BV_SHIFT			16
5060 serge 3893
/*
2325 Serge 3894
 * V attenuation for component video.
3895
 *
3896
 * Stored in 1.9 fixed point.
3897
 */
3898
# define TV_AV_MASK			0x000007ff
3899
# define TV_AV_SHIFT			0
3900
 
6937 serge 3901
#define TV_CLR_KNOBS		_MMIO(0x68028)
5060 serge 3902
/* 2s-complement brightness adjustment */
2325 Serge 3903
# define TV_BRIGHTNESS_MASK		0xff000000
3904
# define TV_BRIGHTNESS_SHIFT		24
5060 serge 3905
/* Contrast adjustment, as a 2.6 unsigned floating point number */
2325 Serge 3906
# define TV_CONTRAST_MASK		0x00ff0000
3907
# define TV_CONTRAST_SHIFT		16
5060 serge 3908
/* Saturation adjustment, as a 2.6 unsigned floating point number */
2325 Serge 3909
# define TV_SATURATION_MASK		0x0000ff00
3910
# define TV_SATURATION_SHIFT		8
5060 serge 3911
/* Hue adjustment, as an integer phase angle in degrees */
2325 Serge 3912
# define TV_HUE_MASK			0x000000ff
3913
# define TV_HUE_SHIFT			0
3914
 
6937 serge 3915
#define TV_CLR_LEVEL		_MMIO(0x6802c)
5060 serge 3916
/* Controls the DAC level for black */
2325 Serge 3917
# define TV_BLACK_LEVEL_MASK		0x01ff0000
3918
# define TV_BLACK_LEVEL_SHIFT		16
5060 serge 3919
/* Controls the DAC level for blanking */
2325 Serge 3920
# define TV_BLANK_LEVEL_MASK		0x000001ff
3921
# define TV_BLANK_LEVEL_SHIFT		0
3922
 
6937 serge 3923
#define TV_H_CTL_1		_MMIO(0x68030)
5060 serge 3924
/* Number of pixels in the hsync. */
2325 Serge 3925
# define TV_HSYNC_END_MASK		0x1fff0000
3926
# define TV_HSYNC_END_SHIFT		16
5060 serge 3927
/* Total number of pixels minus one in the line (display and blanking). */
2325 Serge 3928
# define TV_HTOTAL_MASK			0x00001fff
3929
# define TV_HTOTAL_SHIFT		0
3930
 
6937 serge 3931
#define TV_H_CTL_2		_MMIO(0x68034)
5060 serge 3932
/* Enables the colorburst (needed for non-component color) */
2325 Serge 3933
# define TV_BURST_ENA			(1 << 31)
5060 serge 3934
/* Offset of the colorburst from the start of hsync, in pixels minus one. */
2325 Serge 3935
# define TV_HBURST_START_SHIFT		16
3936
# define TV_HBURST_START_MASK		0x1fff0000
5060 serge 3937
/* Length of the colorburst */
2325 Serge 3938
# define TV_HBURST_LEN_SHIFT		0
3939
# define TV_HBURST_LEN_MASK		0x0001fff
3940
 
6937 serge 3941
#define TV_H_CTL_3		_MMIO(0x68038)
5060 serge 3942
/* End of hblank, measured in pixels minus one from start of hsync */
2325 Serge 3943
# define TV_HBLANK_END_SHIFT		16
3944
# define TV_HBLANK_END_MASK		0x1fff0000
5060 serge 3945
/* Start of hblank, measured in pixels minus one from start of hsync */
2325 Serge 3946
# define TV_HBLANK_START_SHIFT		0
3947
# define TV_HBLANK_START_MASK		0x0001fff
3948
 
6937 serge 3949
#define TV_V_CTL_1		_MMIO(0x6803c)
5060 serge 3950
/* XXX */
2325 Serge 3951
# define TV_NBR_END_SHIFT		16
3952
# define TV_NBR_END_MASK		0x07ff0000
5060 serge 3953
/* XXX */
2325 Serge 3954
# define TV_VI_END_F1_SHIFT		8
3955
# define TV_VI_END_F1_MASK		0x00003f00
5060 serge 3956
/* XXX */
2325 Serge 3957
# define TV_VI_END_F2_SHIFT		0
3958
# define TV_VI_END_F2_MASK		0x0000003f
3959
 
6937 serge 3960
#define TV_V_CTL_2		_MMIO(0x68040)
5060 serge 3961
/* Length of vsync, in half lines */
2325 Serge 3962
# define TV_VSYNC_LEN_MASK		0x07ff0000
3963
# define TV_VSYNC_LEN_SHIFT		16
5060 serge 3964
/* Offset of the start of vsync in field 1, measured in one less than the
2325 Serge 3965
 * number of half lines.
3966
 */
3967
# define TV_VSYNC_START_F1_MASK		0x00007f00
3968
# define TV_VSYNC_START_F1_SHIFT	8
5060 serge 3969
/*
2325 Serge 3970
 * Offset of the start of vsync in field 2, measured in one less than the
3971
 * number of half lines.
3972
 */
3973
# define TV_VSYNC_START_F2_MASK		0x0000007f
3974
# define TV_VSYNC_START_F2_SHIFT	0
3975
 
6937 serge 3976
#define TV_V_CTL_3		_MMIO(0x68044)
5060 serge 3977
/* Enables generation of the equalization signal */
2325 Serge 3978
# define TV_EQUAL_ENA			(1 << 31)
5060 serge 3979
/* Length of vsync, in half lines */
2325 Serge 3980
# define TV_VEQ_LEN_MASK		0x007f0000
3981
# define TV_VEQ_LEN_SHIFT		16
5060 serge 3982
/* Offset of the start of equalization in field 1, measured in one less than
2325 Serge 3983
 * the number of half lines.
3984
 */
3985
# define TV_VEQ_START_F1_MASK		0x0007f00
3986
# define TV_VEQ_START_F1_SHIFT		8
5060 serge 3987
/*
2325 Serge 3988
 * Offset of the start of equalization in field 2, measured in one less than
3989
 * the number of half lines.
3990
 */
3991
# define TV_VEQ_START_F2_MASK		0x000007f
3992
# define TV_VEQ_START_F2_SHIFT		0
3993
 
6937 serge 3994
#define TV_V_CTL_4		_MMIO(0x68048)
5060 serge 3995
/*
2325 Serge 3996
 * Offset to start of vertical colorburst, measured in one less than the
3997
 * number of lines from vertical start.
3998
 */
3999
# define TV_VBURST_START_F1_MASK	0x003f0000
4000
# define TV_VBURST_START_F1_SHIFT	16
5060 serge 4001
/*
2325 Serge 4002
 * Offset to the end of vertical colorburst, measured in one less than the
4003
 * number of lines from the start of NBR.
4004
 */
4005
# define TV_VBURST_END_F1_MASK		0x000000ff
4006
# define TV_VBURST_END_F1_SHIFT		0
4007
 
6937 serge 4008
#define TV_V_CTL_5		_MMIO(0x6804c)
5060 serge 4009
/*
2325 Serge 4010
 * Offset to start of vertical colorburst, measured in one less than the
4011
 * number of lines from vertical start.
4012
 */
4013
# define TV_VBURST_START_F2_MASK	0x003f0000
4014
# define TV_VBURST_START_F2_SHIFT	16
5060 serge 4015
/*
2325 Serge 4016
 * Offset to the end of vertical colorburst, measured in one less than the
4017
 * number of lines from the start of NBR.
4018
 */
4019
# define TV_VBURST_END_F2_MASK		0x000000ff
4020
# define TV_VBURST_END_F2_SHIFT		0
4021
 
6937 serge 4022
#define TV_V_CTL_6		_MMIO(0x68050)
5060 serge 4023
/*
2325 Serge 4024
 * Offset to start of vertical colorburst, measured in one less than the
4025
 * number of lines from vertical start.
4026
 */
4027
# define TV_VBURST_START_F3_MASK	0x003f0000
4028
# define TV_VBURST_START_F3_SHIFT	16
5060 serge 4029
/*
2325 Serge 4030
 * Offset to the end of vertical colorburst, measured in one less than the
4031
 * number of lines from the start of NBR.
4032
 */
4033
# define TV_VBURST_END_F3_MASK		0x000000ff
4034
# define TV_VBURST_END_F3_SHIFT		0
4035
 
6937 serge 4036
#define TV_V_CTL_7		_MMIO(0x68054)
5060 serge 4037
/*
2325 Serge 4038
 * Offset to start of vertical colorburst, measured in one less than the
4039
 * number of lines from vertical start.
4040
 */
4041
# define TV_VBURST_START_F4_MASK	0x003f0000
4042
# define TV_VBURST_START_F4_SHIFT	16
5060 serge 4043
/*
2325 Serge 4044
 * Offset to the end of vertical colorburst, measured in one less than the
4045
 * number of lines from the start of NBR.
4046
 */
4047
# define TV_VBURST_END_F4_MASK		0x000000ff
4048
# define TV_VBURST_END_F4_SHIFT		0
4049
 
6937 serge 4050
#define TV_SC_CTL_1		_MMIO(0x68060)
5060 serge 4051
/* Turns on the first subcarrier phase generation DDA */
2325 Serge 4052
# define TV_SC_DDA1_EN			(1 << 31)
5060 serge 4053
/* Turns on the first subcarrier phase generation DDA */
2325 Serge 4054
# define TV_SC_DDA2_EN			(1 << 30)
5060 serge 4055
/* Turns on the first subcarrier phase generation DDA */
2325 Serge 4056
# define TV_SC_DDA3_EN			(1 << 29)
5060 serge 4057
/* Sets the subcarrier DDA to reset frequency every other field */
2325 Serge 4058
# define TV_SC_RESET_EVERY_2		(0 << 24)
5060 serge 4059
/* Sets the subcarrier DDA to reset frequency every fourth field */
2325 Serge 4060
# define TV_SC_RESET_EVERY_4		(1 << 24)
5060 serge 4061
/* Sets the subcarrier DDA to reset frequency every eighth field */
2325 Serge 4062
# define TV_SC_RESET_EVERY_8		(2 << 24)
5060 serge 4063
/* Sets the subcarrier DDA to never reset the frequency */
2325 Serge 4064
# define TV_SC_RESET_NEVER		(3 << 24)
5060 serge 4065
/* Sets the peak amplitude of the colorburst.*/
2325 Serge 4066
# define TV_BURST_LEVEL_MASK		0x00ff0000
4067
# define TV_BURST_LEVEL_SHIFT		16
5060 serge 4068
/* Sets the increment of the first subcarrier phase generation DDA */
2325 Serge 4069
# define TV_SCDDA1_INC_MASK		0x00000fff
4070
# define TV_SCDDA1_INC_SHIFT		0
4071
 
6937 serge 4072
#define TV_SC_CTL_2		_MMIO(0x68064)
5060 serge 4073
/* Sets the rollover for the second subcarrier phase generation DDA */
2325 Serge 4074
# define TV_SCDDA2_SIZE_MASK		0x7fff0000
4075
# define TV_SCDDA2_SIZE_SHIFT		16
5060 serge 4076
/* Sets the increent of the second subcarrier phase generation DDA */
2325 Serge 4077
# define TV_SCDDA2_INC_MASK		0x00007fff
4078
# define TV_SCDDA2_INC_SHIFT		0
4079
 
6937 serge 4080
#define TV_SC_CTL_3		_MMIO(0x68068)
5060 serge 4081
/* Sets the rollover for the third subcarrier phase generation DDA */
2325 Serge 4082
# define TV_SCDDA3_SIZE_MASK		0x7fff0000
4083
# define TV_SCDDA3_SIZE_SHIFT		16
5060 serge 4084
/* Sets the increent of the third subcarrier phase generation DDA */
2325 Serge 4085
# define TV_SCDDA3_INC_MASK		0x00007fff
4086
# define TV_SCDDA3_INC_SHIFT		0
4087
 
6937 serge 4088
#define TV_WIN_POS		_MMIO(0x68070)
5060 serge 4089
/* X coordinate of the display from the start of horizontal active */
2325 Serge 4090
# define TV_XPOS_MASK			0x1fff0000
4091
# define TV_XPOS_SHIFT			16
5060 serge 4092
/* Y coordinate of the display from the start of vertical active (NBR) */
2325 Serge 4093
# define TV_YPOS_MASK			0x00000fff
4094
# define TV_YPOS_SHIFT			0
4095
 
6937 serge 4096
#define TV_WIN_SIZE		_MMIO(0x68074)
5060 serge 4097
/* Horizontal size of the display window, measured in pixels*/
2325 Serge 4098
# define TV_XSIZE_MASK			0x1fff0000
4099
# define TV_XSIZE_SHIFT			16
5060 serge 4100
/*
2325 Serge 4101
 * Vertical size of the display window, measured in pixels.
4102
 *
4103
 * Must be even for interlaced modes.
4104
 */
4105
# define TV_YSIZE_MASK			0x00000fff
4106
# define TV_YSIZE_SHIFT			0
4107
 
6937 serge 4108
#define TV_FILTER_CTL_1		_MMIO(0x68080)
5060 serge 4109
/*
2325 Serge 4110
 * Enables automatic scaling calculation.
4111
 *
4112
 * If set, the rest of the registers are ignored, and the calculated values can
4113
 * be read back from the register.
4114
 */
4115
# define TV_AUTO_SCALE			(1 << 31)
5060 serge 4116
/*
2325 Serge 4117
 * Disables the vertical filter.
4118
 *
4119
 * This is required on modes more than 1024 pixels wide */
4120
# define TV_V_FILTER_BYPASS		(1 << 29)
5060 serge 4121
/* Enables adaptive vertical filtering */
2325 Serge 4122
# define TV_VADAPT			(1 << 28)
4123
# define TV_VADAPT_MODE_MASK		(3 << 26)
5060 serge 4124
/* Selects the least adaptive vertical filtering mode */
2325 Serge 4125
# define TV_VADAPT_MODE_LEAST		(0 << 26)
5060 serge 4126
/* Selects the moderately adaptive vertical filtering mode */
2325 Serge 4127
# define TV_VADAPT_MODE_MODERATE	(1 << 26)
5060 serge 4128
/* Selects the most adaptive vertical filtering mode */
2325 Serge 4129
# define TV_VADAPT_MODE_MOST		(3 << 26)
5060 serge 4130
/*
2325 Serge 4131
 * Sets the horizontal scaling factor.
4132
 *
4133
 * This should be the fractional part of the horizontal scaling factor divided
4134
 * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
4135
 *
4136
 * (src width - 1) / ((oversample * dest width) - 1)
4137
 */
4138
# define TV_HSCALE_FRAC_MASK		0x00003fff
4139
# define TV_HSCALE_FRAC_SHIFT		0
4140
 
6937 serge 4141
#define TV_FILTER_CTL_2		_MMIO(0x68084)
5060 serge 4142
/*
2325 Serge 4143
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4144
 *
4145
 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4146
 */
4147
# define TV_VSCALE_INT_MASK		0x00038000
4148
# define TV_VSCALE_INT_SHIFT		15
5060 serge 4149
/*
2325 Serge 4150
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4151
 *
4152
 * \sa TV_VSCALE_INT_MASK
4153
 */
4154
# define TV_VSCALE_FRAC_MASK		0x00007fff
4155
# define TV_VSCALE_FRAC_SHIFT		0
4156
 
6937 serge 4157
#define TV_FILTER_CTL_3		_MMIO(0x68088)
5060 serge 4158
/*
2325 Serge 4159
 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4160
 *
4161
 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4162
 *
4163
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4164
 */
4165
# define TV_VSCALE_IP_INT_MASK		0x00038000
4166
# define TV_VSCALE_IP_INT_SHIFT		15
5060 serge 4167
/*
2325 Serge 4168
 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4169
 *
4170
 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4171
 *
4172
 * \sa TV_VSCALE_IP_INT_MASK
4173
 */
4174
# define TV_VSCALE_IP_FRAC_MASK		0x00007fff
4175
# define TV_VSCALE_IP_FRAC_SHIFT		0
4176
 
6937 serge 4177
#define TV_CC_CONTROL		_MMIO(0x68090)
2325 Serge 4178
# define TV_CC_ENABLE			(1 << 31)
5060 serge 4179
/*
2325 Serge 4180
 * Specifies which field to send the CC data in.
4181
 *
4182
 * CC data is usually sent in field 0.
4183
 */
4184
# define TV_CC_FID_MASK			(1 << 27)
4185
# define TV_CC_FID_SHIFT		27
5060 serge 4186
/* Sets the horizontal position of the CC data.  Usually 135. */
2325 Serge 4187
# define TV_CC_HOFF_MASK		0x03ff0000
4188
# define TV_CC_HOFF_SHIFT		16
5060 serge 4189
/* Sets the vertical position of the CC data.  Usually 21 */
2325 Serge 4190
# define TV_CC_LINE_MASK		0x0000003f
4191
# define TV_CC_LINE_SHIFT		0
4192
 
6937 serge 4193
#define TV_CC_DATA		_MMIO(0x68094)
2325 Serge 4194
# define TV_CC_RDY			(1 << 31)
5060 serge 4195
/* Second word of CC data to be transmitted. */
2325 Serge 4196
# define TV_CC_DATA_2_MASK		0x007f0000
4197
# define TV_CC_DATA_2_SHIFT		16
5060 serge 4198
/* First word of CC data to be transmitted. */
2325 Serge 4199
# define TV_CC_DATA_1_MASK		0x0000007f
4200
# define TV_CC_DATA_1_SHIFT		0
4201
 
6937 serge 4202
#define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
4203
#define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
4204
#define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
4205
#define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
2325 Serge 4206
 
4207
/* Display Port */
6937 serge 4208
#define DP_A			_MMIO(0x64000) /* eDP */
4209
#define DP_B			_MMIO(0x64100)
4210
#define DP_C			_MMIO(0x64200)
4211
#define DP_D			_MMIO(0x64300)
2325 Serge 4212
 
6937 serge 4213
#define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
4214
#define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
4215
#define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
6084 serge 4216
 
2325 Serge 4217
#define   DP_PORT_EN			(1 << 31)
4218
#define   DP_PIPEB_SELECT		(1 << 30)
4219
#define   DP_PIPE_MASK			(1 << 30)
5060 serge 4220
#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
4221
#define   DP_PIPE_MASK_CHV		(3 << 16)
2325 Serge 4222
 
4223
/* Link training mode - select a suitable mode for each stage */
4224
#define   DP_LINK_TRAIN_PAT_1		(0 << 28)
4225
#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
4226
#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
4227
#define   DP_LINK_TRAIN_OFF		(3 << 28)
4228
#define   DP_LINK_TRAIN_MASK		(3 << 28)
4229
#define   DP_LINK_TRAIN_SHIFT		28
5354 serge 4230
#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
4231
#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
2325 Serge 4232
 
4233
/* CPT Link training mode */
4234
#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
4235
#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
4236
#define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
4237
#define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
4238
#define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
4239
#define   DP_LINK_TRAIN_SHIFT_CPT	8
4240
 
4241
/* Signal voltages. These are mostly controlled by the other end */
4242
#define   DP_VOLTAGE_0_4		(0 << 25)
4243
#define   DP_VOLTAGE_0_6		(1 << 25)
4244
#define   DP_VOLTAGE_0_8		(2 << 25)
4245
#define   DP_VOLTAGE_1_2		(3 << 25)
4246
#define   DP_VOLTAGE_MASK		(7 << 25)
4247
#define   DP_VOLTAGE_SHIFT		25
4248
 
4249
/* Signal pre-emphasis levels, like voltages, the other end tells us what
4250
 * they want
4251
 */
4252
#define   DP_PRE_EMPHASIS_0		(0 << 22)
4253
#define   DP_PRE_EMPHASIS_3_5		(1 << 22)
4254
#define   DP_PRE_EMPHASIS_6		(2 << 22)
4255
#define   DP_PRE_EMPHASIS_9_5		(3 << 22)
4256
#define   DP_PRE_EMPHASIS_MASK		(7 << 22)
4257
#define   DP_PRE_EMPHASIS_SHIFT		22
4258
 
4259
/* How many wires to use. I guess 3 was too hard */
4104 Serge 4260
#define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
2325 Serge 4261
#define   DP_PORT_WIDTH_MASK		(7 << 19)
6084 serge 4262
#define   DP_PORT_WIDTH_SHIFT		19
2325 Serge 4263
 
4264
/* Mystic DPCD version 1.1 special mode */
4265
#define   DP_ENHANCED_FRAMING		(1 << 18)
4266
 
4267
/* eDP */
4268
#define   DP_PLL_FREQ_270MHZ		(0 << 16)
6937 serge 4269
#define   DP_PLL_FREQ_162MHZ		(1 << 16)
2325 Serge 4270
#define   DP_PLL_FREQ_MASK		(3 << 16)
4271
 
5060 serge 4272
/* locked once port is enabled */
2325 Serge 4273
#define   DP_PORT_REVERSAL		(1 << 15)
4274
 
4275
/* eDP */
4276
#define   DP_PLL_ENABLE			(1 << 14)
4277
 
5060 serge 4278
/* sends the clock on lane 15 of the PEG for debug */
2325 Serge 4279
#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
4280
 
4281
#define   DP_SCRAMBLING_DISABLE		(1 << 12)
4282
#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
4283
 
5060 serge 4284
/* limit RGB values to avoid confusing TVs */
2325 Serge 4285
#define   DP_COLOR_RANGE_16_235		(1 << 8)
4286
 
5060 serge 4287
/* Turn on the audio link */
2325 Serge 4288
#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
4289
 
5060 serge 4290
/* vs and hs sync polarity */
2325 Serge 4291
#define   DP_SYNC_VS_HIGH		(1 << 4)
4292
#define   DP_SYNC_HS_HIGH		(1 << 3)
4293
 
5060 serge 4294
/* A fantasy */
2325 Serge 4295
#define   DP_DETECTED			(1 << 2)
4296
 
5060 serge 4297
/* The aux channel provides a way to talk to the
2325 Serge 4298
 * signal sink for DDC etc. Max packet size supported
4299
 * is 20 bytes in each direction, hence the 5 fixed
4300
 * data registers
4301
 */
6937 serge 4302
#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
4303
#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
4304
#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
4305
#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
4306
#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
4307
#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
2325 Serge 4308
 
6937 serge 4309
#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
4310
#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
4311
#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
4312
#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
4313
#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
4314
#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
2325 Serge 4315
 
6937 serge 4316
#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
4317
#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
4318
#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
4319
#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
4320
#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
4321
#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
2325 Serge 4322
 
6937 serge 4323
#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
4324
#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
4325
#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
4326
#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
4327
#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
4328
#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
2325 Serge 4329
 
6937 serge 4330
#define DP_AUX_CH_CTL(port)	_MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
4331
#define DP_AUX_CH_DATA(port, i)	_MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
4332
 
2325 Serge 4333
#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
4334
#define   DP_AUX_CH_CTL_DONE		    (1 << 30)
4335
#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
4336
#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
4337
#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
4338
#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
4339
#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
4340
#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
4341
#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
4342
#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
4343
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
4344
#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
4345
#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
4346
#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
4347
#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
4348
#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
4349
#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
4350
#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
4351
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
4352
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
4353
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
6084 serge 4354
#define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
4355
#define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
4356
#define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
4357
#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
4358
#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5354 serge 4359
#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
2325 Serge 4360
 
4361
/*
4362
 * Computing GMCH M and N values for the Display Port link
4363
 *
4364
 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4365
 *
4366
 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4367
 *
4368
 * The GMCH value is used internally
4369
 *
4370
 * bytes_per_pixel is the number of bytes coming out of the plane,
4371
 * which is after the LUTs, so we want the bytes for our color format.
4372
 * For our current usage, this is always 3, one byte for R, G and B.
4373
 */
4104 Serge 4374
#define _PIPEA_DATA_M_G4X	0x70050
4375
#define _PIPEB_DATA_M_G4X	0x71050
2325 Serge 4376
 
4377
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3746 Serge 4378
#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
4104 Serge 4379
#define  TU_SIZE_SHIFT		25
3746 Serge 4380
#define  TU_SIZE_MASK           (0x3f << 25)
2325 Serge 4381
 
3746 Serge 4382
#define  DATA_LINK_M_N_MASK	(0xffffff)
4383
#define  DATA_LINK_N_MAX	(0x800000)
2325 Serge 4384
 
4104 Serge 4385
#define _PIPEA_DATA_N_G4X	0x70054
4386
#define _PIPEB_DATA_N_G4X	0x71054
4387
#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
2325 Serge 4388
 
4389
/*
4390
 * Computing Link M and N values for the Display Port link
4391
 *
4392
 * Link M / N = pixel_clock / ls_clk
4393
 *
4394
 * (the DP spec calls pixel_clock the 'strm_clk')
4395
 *
4396
 * The Link value is transmitted in the Main Stream
4397
 * Attributes and VB-ID.
4398
 */
4399
 
4104 Serge 4400
#define _PIPEA_LINK_M_G4X	0x70060
4401
#define _PIPEB_LINK_M_G4X	0x71060
4402
#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
2325 Serge 4403
 
4104 Serge 4404
#define _PIPEA_LINK_N_G4X	0x70064
4405
#define _PIPEB_LINK_N_G4X	0x71064
4406
#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
2325 Serge 4407
 
6937 serge 4408
#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4409
#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4410
#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4411
#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2325 Serge 4412
 
4413
/* Display & cursor control */
4414
 
4415
/* Pipe A */
5060 serge 4416
#define _PIPEADSL		0x70000
3031 serge 4417
#define   DSL_LINEMASK_GEN2	0x00000fff
4418
#define   DSL_LINEMASK_GEN3	0x00001fff
5060 serge 4419
#define _PIPEACONF		0x70008
2325 Serge 4420
#define   PIPECONF_ENABLE	(1<<31)
4421
#define   PIPECONF_DISABLE	0
4422
#define   PIPECONF_DOUBLE_WIDE	(1<<30)
4423
#define   I965_PIPECONF_ACTIVE	(1<<30)
4560 Serge 4424
#define   PIPECONF_DSI_PLL_LOCKED	(1<<29) /* vlv & pipe A only */
3031 serge 4425
#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2325 Serge 4426
#define   PIPECONF_SINGLE_WIDE	0
4427
#define   PIPECONF_PIPE_UNLOCKED 0
4428
#define   PIPECONF_PIPE_LOCKED	(1<<25)
4429
#define   PIPECONF_PALETTE	0
4430
#define   PIPECONF_GAMMA		(1<<24)
4431
#define   PIPECONF_FORCE_BORDER	(1<<25)
3031 serge 4432
#define   PIPECONF_INTERLACE_MASK	(7 << 21)
3243 Serge 4433
#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
3031 serge 4434
/* Note that pre-gen3 does not support interlaced display directly. Panel
4435
 * fitting must be disabled on pre-ilk for interlaced. */
6084 serge 4436
#define   PIPECONF_PROGRESSIVE			(0 << 21)
3031 serge 4437
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
4438
#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2325 Serge 4439
#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
3031 serge 4440
#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
4441
/* Ironlake and later have a complete new set of values for interlaced. PFIT
4442
 * means panel fitter required, PF means progressive fetch, DBL means power
4443
 * saving pixel doubling. */
4444
#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
4445
#define   PIPECONF_INTERLACED_ILK		(3 << 21)
4446
#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
4447
#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
4104 Serge 4448
#define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
5060 serge 4449
#define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
2325 Serge 4450
#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
6084 serge 4451
#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
3480 Serge 4452
#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
4453
#define   PIPECONF_BPC_MASK	(0x7 << 5)
4454
#define   PIPECONF_8BPC		(0<<5)
4455
#define   PIPECONF_10BPC	(1<<5)
4456
#define   PIPECONF_6BPC		(2<<5)
4457
#define   PIPECONF_12BPC	(3<<5)
2325 Serge 4458
#define   PIPECONF_DITHER_EN	(1<<4)
4459
#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4460
#define   PIPECONF_DITHER_TYPE_SP (0<<2)
4461
#define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
4462
#define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
4463
#define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
5060 serge 4464
#define _PIPEASTAT		0x70024
2325 Serge 4465
#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
5060 serge 4466
#define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL<<30)
2325 Serge 4467
#define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
4468
#define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
5060 serge 4469
#define   PERF_COUNTER2_INTERRUPT_EN		(1UL<<27)
2325 Serge 4470
#define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
3031 serge 4471
#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
2325 Serge 4472
#define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
4473
#define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
4474
#define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
4475
#define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
3480 Serge 4476
#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<22)
2325 Serge 4477
#define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
4478
#define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
4479
#define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
5060 serge 4480
#define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL<<19)
4481
#define   PERF_COUNTER_INTERRUPT_EN		(1UL<<19)
2325 Serge 4482
#define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
4483
#define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
5060 serge 4484
#define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL<<17)
2325 Serge 4485
#define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
3031 serge 4486
#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
2325 Serge 4487
#define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
5060 serge 4488
#define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL<<15)
4489
#define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL<<14)
2325 Serge 4490
#define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
4491
#define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
5060 serge 4492
#define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL<<11)
2325 Serge 4493
#define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
5060 serge 4494
#define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
2325 Serge 4495
#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
4496
#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
4497
#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
4498
#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
5060 serge 4499
#define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
4500
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
2325 Serge 4501
#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
4502
#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
5060 serge 4503
#define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
4504
#define   PERF_COUNTER_INTERRUPT_STATUS		(1UL<<3)
2325 Serge 4505
#define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
4506
#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
5060 serge 4507
#define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL<<1)
2325 Serge 4508
#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
5060 serge 4509
#define   PIPE_HBLANK_INT_STATUS		(1UL<<0)
2325 Serge 4510
#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
4511
 
5060 serge 4512
#define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
4513
#define PIPESTAT_INT_STATUS_MASK		0x0000ffff
2325 Serge 4514
 
6084 serge 4515
#define PIPE_A_OFFSET		0x70000
4516
#define PIPE_B_OFFSET		0x71000
4517
#define PIPE_C_OFFSET		0x72000
5060 serge 4518
#define CHV_PIPE_C_OFFSET	0x74000
4519
/*
4520
 * There's actually no pipe EDP. Some pipe registers have
4521
 * simply shifted from the pipe to the transcoder, while
4522
 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4523
 * to access such registers in transcoder EDP.
4524
 */
4525
#define PIPE_EDP_OFFSET	0x7f000
4526
 
6937 serge 4527
#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5060 serge 4528
	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4529
	dev_priv->info.display_mmio_offset)
4530
 
6937 serge 4531
#define PIPECONF(pipe)		_MMIO_PIPE2(pipe, _PIPEACONF)
4532
#define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
4533
#define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
4534
#define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
4535
#define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
5060 serge 4536
 
4560 Serge 4537
#define _PIPE_MISC_A			0x70030
4538
#define _PIPE_MISC_B			0x71030
4539
#define   PIPEMISC_DITHER_BPC_MASK	(7<<5)
4540
#define   PIPEMISC_DITHER_8_BPC		(0<<5)
4541
#define   PIPEMISC_DITHER_10_BPC	(1<<5)
4542
#define   PIPEMISC_DITHER_6_BPC		(2<<5)
4543
#define   PIPEMISC_DITHER_12_BPC	(3<<5)
4544
#define   PIPEMISC_DITHER_ENABLE	(1<<4)
4545
#define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
4546
#define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
6937 serge 4547
#define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
4560 Serge 4548
 
6937 serge 4549
#define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
3031 serge 4550
#define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
4551
#define   PIPEB_HLINE_INT_EN			(1<<28)
4552
#define   PIPEB_VBLANK_INT_EN			(1<<27)
5060 serge 4553
#define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
4554
#define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
4555
#define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
4556
#define   PIPE_PSR_INT_EN			(1<<22)
3031 serge 4557
#define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
4558
#define   PIPEA_HLINE_INT_EN			(1<<20)
4559
#define   PIPEA_VBLANK_INT_EN			(1<<19)
5060 serge 4560
#define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
4561
#define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
3031 serge 4562
#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
5060 serge 4563
#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
4564
#define   PIPEC_HLINE_INT_EN			(1<<12)
4565
#define   PIPEC_VBLANK_INT_EN			(1<<11)
4566
#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
4567
#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
4568
#define   PLANEC_FLIPDONE_INT_EN		(1<<8)
3031 serge 4569
 
6937 serge 4570
#define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5060 serge 4571
#define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
4572
#define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
4573
#define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
4574
#define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
3031 serge 4575
#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
4576
#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
4577
#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
4578
#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
4579
#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
4580
#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
4581
#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
4582
#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
4583
#define   DPINVGTT_EN_MASK			0xff0000
5060 serge 4584
#define   DPINVGTT_EN_MASK_CHV			0xfff0000
4585
#define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
4586
#define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
4587
#define   PLANEC_INVALID_GTT_STATUS		(1<<9)
4588
#define   CURSORC_INVALID_GTT_STATUS		(1<<8)
3031 serge 4589
#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
4590
#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
4591
#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
4592
#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
4593
#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
4594
#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
4595
#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
4596
#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
4597
#define   DPINVGTT_STATUS_MASK			0xff
5060 serge 4598
#define   DPINVGTT_STATUS_MASK_CHV		0xfff
3031 serge 4599
 
6937 serge 4600
#define DSPARB			_MMIO(dev_priv->info.display_mmio_offset + 0x70030)
2325 Serge 4601
#define   DSPARB_CSTART_MASK	(0x7f << 7)
4602
#define   DSPARB_CSTART_SHIFT	7
4603
#define   DSPARB_BSTART_MASK	(0x7f)
4604
#define   DSPARB_BSTART_SHIFT	0
4605
#define   DSPARB_BEND_SHIFT	9 /* on 855 */
4606
#define   DSPARB_AEND_SHIFT	0
6084 serge 4607
#define   DSPARB_SPRITEA_SHIFT_VLV	0
4608
#define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
4609
#define   DSPARB_SPRITEB_SHIFT_VLV	8
4610
#define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
4611
#define   DSPARB_SPRITEC_SHIFT_VLV	16
4612
#define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
4613
#define   DSPARB_SPRITED_SHIFT_VLV	24
4614
#define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
6937 serge 4615
#define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
6084 serge 4616
#define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
4617
#define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
4618
#define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
4619
#define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
4620
#define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
4621
#define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
4622
#define   DSPARB_SPRITED_HI_SHIFT_VLV	12
4623
#define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
4624
#define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
4625
#define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
4626
#define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
4627
#define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
6937 serge 4628
#define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
6084 serge 4629
#define   DSPARB_SPRITEE_SHIFT_VLV	0
4630
#define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
4631
#define   DSPARB_SPRITEF_SHIFT_VLV	8
4632
#define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
2325 Serge 4633
 
5354 serge 4634
/* pnv/gen4/g4x/vlv/chv */
6937 serge 4635
#define DSPFW1		_MMIO(dev_priv->info.display_mmio_offset + 0x70034)
6084 serge 4636
#define   DSPFW_SR_SHIFT		23
4637
#define   DSPFW_SR_MASK			(0x1ff<<23)
4638
#define   DSPFW_CURSORB_SHIFT		16
4639
#define   DSPFW_CURSORB_MASK		(0x3f<<16)
4640
#define   DSPFW_PLANEB_SHIFT		8
4641
#define   DSPFW_PLANEB_MASK		(0x7f<<8)
5354 serge 4642
#define   DSPFW_PLANEB_MASK_VLV		(0xff<<8) /* vlv/chv */
4643
#define   DSPFW_PLANEA_SHIFT		0
4644
#define   DSPFW_PLANEA_MASK		(0x7f<<0)
4645
#define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
6937 serge 4646
#define DSPFW2		_MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5354 serge 4647
#define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
4648
#define   DSPFW_FBC_SR_SHIFT		28
4649
#define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
4650
#define   DSPFW_FBC_HPLL_SR_SHIFT	24
4651
#define   DSPFW_FBC_HPLL_SR_MASK	(0xf<<24) /* g4x */
4652
#define   DSPFW_SPRITEB_SHIFT		(16)
4653
#define   DSPFW_SPRITEB_MASK		(0x7f<<16) /* g4x */
4654
#define   DSPFW_SPRITEB_MASK_VLV	(0xff<<16) /* vlv/chv */
6084 serge 4655
#define   DSPFW_CURSORA_SHIFT		8
5354 serge 4656
#define   DSPFW_CURSORA_MASK		(0x3f<<8)
6084 serge 4657
#define   DSPFW_PLANEC_OLD_SHIFT	0
4658
#define   DSPFW_PLANEC_OLD_MASK		(0x7f<<0) /* pre-gen4 sprite C */
5354 serge 4659
#define   DSPFW_SPRITEA_SHIFT		0
4660
#define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
4661
#define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
6937 serge 4662
#define DSPFW3		_MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
6084 serge 4663
#define   DSPFW_HPLL_SR_EN		(1<<31)
5354 serge 4664
#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
6084 serge 4665
#define   DSPFW_CURSOR_SR_SHIFT		24
2325 Serge 4666
#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
4667
#define   DSPFW_HPLL_CURSOR_SHIFT	16
4668
#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
5354 serge 4669
#define   DSPFW_HPLL_SR_SHIFT		0
4670
#define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
2325 Serge 4671
 
5354 serge 4672
/* vlv/chv */
6937 serge 4673
#define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
5354 serge 4674
#define   DSPFW_SPRITEB_WM1_SHIFT	16
4675
#define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
4676
#define   DSPFW_CURSORA_WM1_SHIFT	8
4677
#define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
4678
#define   DSPFW_SPRITEA_WM1_SHIFT	0
4679
#define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
6937 serge 4680
#define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
5354 serge 4681
#define   DSPFW_PLANEB_WM1_SHIFT	24
4682
#define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
4683
#define   DSPFW_PLANEA_WM1_SHIFT	16
4684
#define   DSPFW_PLANEA_WM1_MASK		(0xff<<16)
4685
#define   DSPFW_CURSORB_WM1_SHIFT	8
4686
#define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
4687
#define   DSPFW_CURSOR_SR_WM1_SHIFT	0
4688
#define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
6937 serge 4689
#define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
5354 serge 4690
#define   DSPFW_SR_WM1_SHIFT		0
4691
#define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
6937 serge 4692
#define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
4693
#define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5354 serge 4694
#define   DSPFW_SPRITED_WM1_SHIFT	24
4695
#define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
4696
#define   DSPFW_SPRITED_SHIFT		16
6084 serge 4697
#define   DSPFW_SPRITED_MASK_VLV	(0xff<<16)
5354 serge 4698
#define   DSPFW_SPRITEC_WM1_SHIFT	8
4699
#define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
4700
#define   DSPFW_SPRITEC_SHIFT		0
6084 serge 4701
#define   DSPFW_SPRITEC_MASK_VLV	(0xff<<0)
6937 serge 4702
#define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
5354 serge 4703
#define   DSPFW_SPRITEF_WM1_SHIFT	24
4704
#define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
4705
#define   DSPFW_SPRITEF_SHIFT		16
6084 serge 4706
#define   DSPFW_SPRITEF_MASK_VLV	(0xff<<16)
5354 serge 4707
#define   DSPFW_SPRITEE_WM1_SHIFT	8
4708
#define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
4709
#define   DSPFW_SPRITEE_SHIFT		0
6084 serge 4710
#define   DSPFW_SPRITEE_MASK_VLV	(0xff<<0)
6937 serge 4711
#define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5354 serge 4712
#define   DSPFW_PLANEC_WM1_SHIFT	24
4713
#define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
4714
#define   DSPFW_PLANEC_SHIFT		16
6084 serge 4715
#define   DSPFW_PLANEC_MASK_VLV		(0xff<<16)
5354 serge 4716
#define   DSPFW_CURSORC_WM1_SHIFT	8
4717
#define   DSPFW_CURSORC_WM1_MASK	(0x3f<<16)
4718
#define   DSPFW_CURSORC_SHIFT		0
4719
#define   DSPFW_CURSORC_MASK		(0x3f<<0)
4720
 
4721
/* vlv/chv high order bits */
6937 serge 4722
#define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
5354 serge 4723
#define   DSPFW_SR_HI_SHIFT		24
6084 serge 4724
#define   DSPFW_SR_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
5354 serge 4725
#define   DSPFW_SPRITEF_HI_SHIFT	23
4726
#define   DSPFW_SPRITEF_HI_MASK		(1<<23)
4727
#define   DSPFW_SPRITEE_HI_SHIFT	22
4728
#define   DSPFW_SPRITEE_HI_MASK		(1<<22)
4729
#define   DSPFW_PLANEC_HI_SHIFT		21
4730
#define   DSPFW_PLANEC_HI_MASK		(1<<21)
4731
#define   DSPFW_SPRITED_HI_SHIFT	20
4732
#define   DSPFW_SPRITED_HI_MASK		(1<<20)
4733
#define   DSPFW_SPRITEC_HI_SHIFT	16
4734
#define   DSPFW_SPRITEC_HI_MASK		(1<<16)
4735
#define   DSPFW_PLANEB_HI_SHIFT		12
4736
#define   DSPFW_PLANEB_HI_MASK		(1<<12)
4737
#define   DSPFW_SPRITEB_HI_SHIFT	8
4738
#define   DSPFW_SPRITEB_HI_MASK		(1<<8)
4739
#define   DSPFW_SPRITEA_HI_SHIFT	4
4740
#define   DSPFW_SPRITEA_HI_MASK		(1<<4)
4741
#define   DSPFW_PLANEA_HI_SHIFT		0
4742
#define   DSPFW_PLANEA_HI_MASK		(1<<0)
6937 serge 4743
#define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
5354 serge 4744
#define   DSPFW_SR_WM1_HI_SHIFT		24
6084 serge 4745
#define   DSPFW_SR_WM1_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
5354 serge 4746
#define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
4747
#define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
4748
#define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
4749
#define   DSPFW_SPRITEE_WM1_HI_MASK	(1<<22)
4750
#define   DSPFW_PLANEC_WM1_HI_SHIFT	21
4751
#define   DSPFW_PLANEC_WM1_HI_MASK	(1<<21)
4752
#define   DSPFW_SPRITED_WM1_HI_SHIFT	20
4753
#define   DSPFW_SPRITED_WM1_HI_MASK	(1<<20)
4754
#define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
4755
#define   DSPFW_SPRITEC_WM1_HI_MASK	(1<<16)
4756
#define   DSPFW_PLANEB_WM1_HI_SHIFT	12
4757
#define   DSPFW_PLANEB_WM1_HI_MASK	(1<<12)
4758
#define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
4759
#define   DSPFW_SPRITEB_WM1_HI_MASK	(1<<8)
4760
#define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
4761
#define   DSPFW_SPRITEA_WM1_HI_MASK	(1<<4)
4762
#define   DSPFW_PLANEA_WM1_HI_SHIFT	0
4763
#define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
4764
 
3031 serge 4765
/* drain latency register values*/
6937 serge 4766
#define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5354 serge 4767
#define DDL_CURSOR_SHIFT		24
4768
#define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
4769
#define DDL_PLANE_SHIFT			0
6084 serge 4770
#define DDL_PRECISION_HIGH		(1<<7)
4771
#define DDL_PRECISION_LOW		(0<<7)
5354 serge 4772
#define DRAIN_LATENCY_MASK		0x7f
5060 serge 4773
 
6937 serge 4774
#define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
6084 serge 4775
#define  CBR_PND_DEADLINE_DISABLE	(1<<31)
4776
#define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)
4777
 
2325 Serge 4778
/* FIFO watermark sizes etc */
4779
#define G4X_FIFO_LINE_SIZE	64
4780
#define I915_FIFO_LINE_SIZE	64
4781
#define I830_FIFO_LINE_SIZE	32
4782
 
3031 serge 4783
#define VALLEYVIEW_FIFO_SIZE	255
2325 Serge 4784
#define G4X_FIFO_SIZE		127
4785
#define I965_FIFO_SIZE		512
4786
#define I945_FIFO_SIZE		127
4787
#define I915_FIFO_SIZE		95
4788
#define I855GM_FIFO_SIZE	127 /* In cachelines */
4789
#define I830_FIFO_SIZE		95
4790
 
3031 serge 4791
#define VALLEYVIEW_MAX_WM	0xff
2325 Serge 4792
#define G4X_MAX_WM		0x3f
4793
#define I915_MAX_WM		0x3f
4794
 
4795
#define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
4796
#define PINEVIEW_FIFO_LINE_SIZE	64
4797
#define PINEVIEW_MAX_WM		0x1ff
4798
#define PINEVIEW_DFT_WM		0x3f
4799
#define PINEVIEW_DFT_HPLLOFF_WM	0
4800
#define PINEVIEW_GUARD_WM		10
4801
#define PINEVIEW_CURSOR_FIFO		64
4802
#define PINEVIEW_CURSOR_MAX_WM	0x3f
4803
#define PINEVIEW_CURSOR_DFT_WM	0
4804
#define PINEVIEW_CURSOR_GUARD_WM	5
4805
 
3031 serge 4806
#define VALLEYVIEW_CURSOR_MAX_WM 64
2325 Serge 4807
#define I965_CURSOR_FIFO	64
4808
#define I965_CURSOR_MAX_WM	32
4809
#define I965_CURSOR_DFT_WM	8
4810
 
5354 serge 4811
/* Watermark register definitions for SKL */
6937 serge 4812
#define _CUR_WM_A_0		0x70140
4813
#define _CUR_WM_B_0		0x71140
4814
#define _PLANE_WM_1_A_0		0x70240
4815
#define _PLANE_WM_1_B_0		0x71240
4816
#define _PLANE_WM_2_A_0		0x70340
4817
#define _PLANE_WM_2_B_0		0x71340
4818
#define _PLANE_WM_TRANS_1_A_0	0x70268
4819
#define _PLANE_WM_TRANS_1_B_0	0x71268
4820
#define _PLANE_WM_TRANS_2_A_0	0x70368
4821
#define _PLANE_WM_TRANS_2_B_0	0x71368
4822
#define _CUR_WM_TRANS_A_0	0x70168
4823
#define _CUR_WM_TRANS_B_0	0x71168
5354 serge 4824
#define   PLANE_WM_EN		(1 << 31)
4825
#define   PLANE_WM_LINES_SHIFT	14
4826
#define   PLANE_WM_LINES_MASK	0x1f
4827
#define   PLANE_WM_BLOCKS_MASK	0x3ff
4828
 
6937 serge 4829
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
4830
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4831
#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5354 serge 4832
 
6937 serge 4833
#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4834
#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5354 serge 4835
#define _PLANE_WM_BASE(pipe, plane)	\
4836
			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4837
#define PLANE_WM(pipe, plane, level)	\
6937 serge 4838
			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5354 serge 4839
#define _PLANE_WM_TRANS_1(pipe)	\
6937 serge 4840
			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5354 serge 4841
#define _PLANE_WM_TRANS_2(pipe)	\
6937 serge 4842
			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5354 serge 4843
#define PLANE_WM_TRANS(pipe, plane)	\
6937 serge 4844
	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5354 serge 4845
 
2325 Serge 4846
/* define the Watermark register on Ironlake */
6937 serge 4847
#define WM0_PIPEA_ILK		_MMIO(0x45100)
4560 Serge 4848
#define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
2325 Serge 4849
#define  WM0_PIPE_PLANE_SHIFT	16
4560 Serge 4850
#define  WM0_PIPE_SPRITE_MASK	(0xff<<8)
2325 Serge 4851
#define  WM0_PIPE_SPRITE_SHIFT	8
4560 Serge 4852
#define  WM0_PIPE_CURSOR_MASK	(0xff)
2325 Serge 4853
 
6937 serge 4854
#define WM0_PIPEB_ILK		_MMIO(0x45104)
4855
#define WM0_PIPEC_IVB		_MMIO(0x45200)
4856
#define WM1_LP_ILK		_MMIO(0x45108)
2325 Serge 4857
#define  WM1_LP_SR_EN		(1<<31)
4858
#define  WM1_LP_LATENCY_SHIFT	24
4859
#define  WM1_LP_LATENCY_MASK	(0x7f<<24)
4860
#define  WM1_LP_FBC_MASK	(0xf<<20)
4861
#define  WM1_LP_FBC_SHIFT	20
4560 Serge 4862
#define  WM1_LP_FBC_SHIFT_BDW	19
4863
#define  WM1_LP_SR_MASK		(0x7ff<<8)
2325 Serge 4864
#define  WM1_LP_SR_SHIFT	8
4560 Serge 4865
#define  WM1_LP_CURSOR_MASK	(0xff)
6937 serge 4866
#define WM2_LP_ILK		_MMIO(0x4510c)
2325 Serge 4867
#define  WM2_LP_EN		(1<<31)
6937 serge 4868
#define WM3_LP_ILK		_MMIO(0x45110)
2325 Serge 4869
#define  WM3_LP_EN		(1<<31)
6937 serge 4870
#define WM1S_LP_ILK		_MMIO(0x45120)
4871
#define WM2S_LP_IVB		_MMIO(0x45124)
4872
#define WM3S_LP_IVB		_MMIO(0x45128)
2325 Serge 4873
#define  WM1S_LP_EN		(1<<31)
4874
 
4104 Serge 4875
#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4876
	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4877
	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4878
 
2325 Serge 4879
/* Memory latency timer register */
6937 serge 4880
#define MLTR_ILK		_MMIO(0x11222)
2325 Serge 4881
#define  MLTR_WM1_SHIFT		0
4882
#define  MLTR_WM2_SHIFT		8
4883
/* the unit of memory self-refresh latency time is 0.5us */
4884
#define  ILK_SRLT_MASK		0x3f
4885
 
4886
 
4887
/* the address where we get all kinds of latency value */
6937 serge 4888
#define SSKPD			_MMIO(0x5d10)
2325 Serge 4889
#define SSKPD_WM_MASK		0x3f
4890
#define SSKPD_WM0_SHIFT		0
4891
#define SSKPD_WM1_SHIFT		8
4892
#define SSKPD_WM2_SHIFT		16
4893
#define SSKPD_WM3_SHIFT		24
4894
 
4895
/*
4896
 * The two pipe frame counter registers are not synchronized, so
4897
 * reading a stable value is somewhat tricky. The following code
4898
 * should work:
4899
 *
4900
 *  do {
4901
 *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4902
 *             PIPE_FRAME_HIGH_SHIFT;
4903
 *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4904
 *             PIPE_FRAME_LOW_SHIFT);
4905
 *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4906
 *             PIPE_FRAME_HIGH_SHIFT);
4907
 *  } while (high1 != high2);
4908
 *  frame = (high1 << 8) | low1;
4909
 */
4560 Serge 4910
#define _PIPEAFRAMEHIGH          0x70040
2325 Serge 4911
#define   PIPE_FRAME_HIGH_MASK    0x0000ffff
4912
#define   PIPE_FRAME_HIGH_SHIFT   0
4560 Serge 4913
#define _PIPEAFRAMEPIXEL         0x70044
2325 Serge 4914
#define   PIPE_FRAME_LOW_MASK     0xff000000
4915
#define   PIPE_FRAME_LOW_SHIFT    24
4916
#define   PIPE_PIXEL_MASK         0x00ffffff
4917
#define   PIPE_PIXEL_SHIFT        0
4918
/* GM45+ just has to be different */
6084 serge 4919
#define _PIPEA_FRMCOUNT_G4X	0x70040
4920
#define _PIPEA_FLIPCOUNT_G4X	0x70044
6937 serge 4921
#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4922
#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
2325 Serge 4923
 
4924
/* Cursor A & B regs */
5060 serge 4925
#define _CURACNTR		0x70080
2325 Serge 4926
/* Old style CUR*CNTR flags (desktop 8xx) */
4927
#define   CURSOR_ENABLE		0x80000000
4928
#define   CURSOR_GAMMA_ENABLE	0x40000000
5354 serge 4929
#define   CURSOR_STRIDE_SHIFT	28
4930
#define   CURSOR_STRIDE(x)	((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
3480 Serge 4931
#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
2325 Serge 4932
#define   CURSOR_FORMAT_SHIFT	24
4933
#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
4934
#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
4935
#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
4936
#define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
4937
#define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
4938
#define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
4939
/* New style CUR*CNTR flags */
4940
#define   CURSOR_MODE		0x27
4941
#define   CURSOR_MODE_DISABLE   0x00
5060 serge 4942
#define   CURSOR_MODE_128_32B_AX 0x02
4943
#define   CURSOR_MODE_256_32B_AX 0x03
2325 Serge 4944
#define   CURSOR_MODE_64_32B_AX 0x07
5060 serge 4945
#define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4946
#define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
2325 Serge 4947
#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4948
#define   MCURSOR_PIPE_SELECT	(1 << 28)
4949
#define   MCURSOR_PIPE_A	0x00
4950
#define   MCURSOR_PIPE_B	(1 << 28)
4951
#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
5354 serge 4952
#define   CURSOR_ROTATE_180	(1<<15)
4104 Serge 4953
#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
5060 serge 4954
#define _CURABASE		0x70084
4955
#define _CURAPOS		0x70088
2325 Serge 4956
#define   CURSOR_POS_MASK       0x007FF
4957
#define   CURSOR_POS_SIGN       0x8000
4958
#define   CURSOR_X_SHIFT        0
4959
#define   CURSOR_Y_SHIFT        16
6937 serge 4960
#define CURSIZE			_MMIO(0x700a0)
5060 serge 4961
#define _CURBCNTR		0x700c0
4962
#define _CURBBASE		0x700c4
4963
#define _CURBPOS		0x700c8
2325 Serge 4964
 
2342 Serge 4965
#define _CURBCNTR_IVB		0x71080
4966
#define _CURBBASE_IVB		0x71084
4967
#define _CURBPOS_IVB		0x71088
4968
 
6937 serge 4969
#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
5060 serge 4970
	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4971
	dev_priv->info.display_mmio_offset)
2325 Serge 4972
 
5060 serge 4973
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4974
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4975
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
2342 Serge 4976
 
5060 serge 4977
#define CURSOR_A_OFFSET 0x70080
4978
#define CURSOR_B_OFFSET 0x700c0
4979
#define CHV_CURSOR_C_OFFSET 0x700e0
4980
#define IVB_CURSOR_B_OFFSET 0x71080
4981
#define IVB_CURSOR_C_OFFSET 0x72080
4982
 
2325 Serge 4983
/* Display A control */
5060 serge 4984
#define _DSPACNTR				0x70180
2325 Serge 4985
#define   DISPLAY_PLANE_ENABLE			(1<<31)
4986
#define   DISPLAY_PLANE_DISABLE			0
4987
#define   DISPPLANE_GAMMA_ENABLE		(1<<30)
4988
#define   DISPPLANE_GAMMA_DISABLE		0
4989
#define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
3243 Serge 4990
#define   DISPPLANE_YUV422			(0x0<<26)
2325 Serge 4991
#define   DISPPLANE_8BPP			(0x2<<26)
3243 Serge 4992
#define   DISPPLANE_BGRA555			(0x3<<26)
4993
#define   DISPPLANE_BGRX555			(0x4<<26)
4994
#define   DISPPLANE_BGRX565			(0x5<<26)
4995
#define   DISPPLANE_BGRX888			(0x6<<26)
4996
#define   DISPPLANE_BGRA888			(0x7<<26)
4997
#define   DISPPLANE_RGBX101010			(0x8<<26)
4998
#define   DISPPLANE_RGBA101010			(0x9<<26)
4999
#define   DISPPLANE_BGRX101010			(0xa<<26)
5000
#define   DISPPLANE_RGBX161616			(0xc<<26)
5001
#define   DISPPLANE_RGBX888			(0xe<<26)
5002
#define   DISPPLANE_RGBA888			(0xf<<26)
2325 Serge 5003
#define   DISPPLANE_STEREO_ENABLE		(1<<25)
5004
#define   DISPPLANE_STEREO_DISABLE		0
3480 Serge 5005
#define   DISPPLANE_PIPE_CSC_ENABLE		(1<<24)
2325 Serge 5006
#define   DISPPLANE_SEL_PIPE_SHIFT		24
5007
#define   DISPPLANE_SEL_PIPE_MASK		(3<
5008
#define   DISPPLANE_SEL_PIPE_A			0
5009
#define   DISPPLANE_SEL_PIPE_B			(1<
5010
#define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
5011
#define   DISPPLANE_SRC_KEY_DISABLE		0
5012
#define   DISPPLANE_LINE_DOUBLE			(1<<20)
5013
#define   DISPPLANE_NO_LINE_DOUBLE		0
5014
#define   DISPPLANE_STEREO_POLARITY_FIRST	0
5015
#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
5354 serge 5016
#define   DISPPLANE_ALPHA_PREMULTIPLY		(1<<16) /* CHV pipe B */
5017
#define   DISPPLANE_ROTATE_180			(1<<15)
2325 Serge 5018
#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
5019
#define   DISPPLANE_TILED			(1<<10)
5354 serge 5020
#define   DISPPLANE_MIRROR			(1<<8) /* CHV pipe B */
5060 serge 5021
#define _DSPAADDR				0x70184
5022
#define _DSPASTRIDE				0x70188
5023
#define _DSPAPOS				0x7018C /* reserved */
5024
#define _DSPASIZE				0x70190
5025
#define _DSPASURF				0x7019C /* 965+ only */
5026
#define _DSPATILEOFF				0x701A4 /* 965+ only */
5027
#define _DSPAOFFSET				0x701A4 /* HSW */
5028
#define _DSPASURFLIVE				0x701AC
2325 Serge 5029
 
6937 serge 5030
#define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
5031
#define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
5032
#define DSPSTRIDE(plane)	_MMIO_PIPE2(plane, _DSPASTRIDE)
5033
#define DSPPOS(plane)		_MMIO_PIPE2(plane, _DSPAPOS)
5034
#define DSPSIZE(plane)		_MMIO_PIPE2(plane, _DSPASIZE)
5035
#define DSPSURF(plane)		_MMIO_PIPE2(plane, _DSPASURF)
5036
#define DSPTILEOFF(plane)	_MMIO_PIPE2(plane, _DSPATILEOFF)
3031 serge 5037
#define DSPLINOFF(plane) DSPADDR(plane)
6937 serge 5038
#define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
5039
#define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
2325 Serge 5040
 
5354 serge 5041
/* CHV pipe B blender and primary plane */
5042
#define _CHV_BLEND_A		0x60a00
5043
#define   CHV_BLEND_LEGACY		(0<<30)
5044
#define   CHV_BLEND_ANDROID		(1<<30)
5045
#define   CHV_BLEND_MPO			(2<<30)
5046
#define   CHV_BLEND_MASK		(3<<30)
5047
#define _CHV_CANVAS_A		0x60a04
5048
#define _PRIMPOS_A		0x60a08
5049
#define _PRIMSIZE_A		0x60a0c
5050
#define _PRIMCNSTALPHA_A	0x60a10
5051
#define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
5052
 
6937 serge 5053
#define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
5054
#define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
5055
#define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
5056
#define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
5057
#define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
5354 serge 5058
 
3031 serge 5059
/* Display/Sprite base address macros */
5060
#define DISP_BASEADDR_MASK	(0xfffff000)
5061
#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
5062
#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
5063
 
6084 serge 5064
/*
5065
 * VBIOS flags
5066
 * gen2:
5067
 * [00:06] alm,mgm
5068
 * [10:16] all
5069
 * [30:32] alm,mgm
5070
 * gen3+:
5071
 * [00:0f] all
5072
 * [10:1f] all
5073
 * [30:32] all
5074
 */
6937 serge 5075
#define SWF0(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5076
#define SWF1(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5077
#define SWF3(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5078
#define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
2325 Serge 5079
 
5080
/* Pipe B */
5060 serge 5081
#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
5082
#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
5083
#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
4560 Serge 5084
#define _PIPEBFRAMEHIGH		0x71040
5085
#define _PIPEBFRAMEPIXEL	0x71044
6084 serge 5086
#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
5087
#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
2325 Serge 5088
 
5089
 
5090
/* Display B control */
5060 serge 5091
#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
2325 Serge 5092
#define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
5093
#define   DISPPLANE_ALPHA_TRANS_DISABLE		0
5094
#define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
5095
#define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
5060 serge 5096
#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
5097
#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
5098
#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
5099
#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
5100
#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
5101
#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
5102
#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
5103
#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
2325 Serge 5104
 
2342 Serge 5105
/* Sprite A control */
5106
#define _DVSACNTR		0x72180
5107
#define   DVS_ENABLE		(1<<31)
5108
#define   DVS_GAMMA_ENABLE	(1<<30)
5109
#define   DVS_PIXFORMAT_MASK	(3<<25)
5110
#define   DVS_FORMAT_YUV422	(0<<25)
5111
#define   DVS_FORMAT_RGBX101010	(1<<25)
5112
#define   DVS_FORMAT_RGBX888	(2<<25)
5113
#define   DVS_FORMAT_RGBX161616	(3<<25)
3480 Serge 5114
#define   DVS_PIPE_CSC_ENABLE   (1<<24)
2342 Serge 5115
#define   DVS_SOURCE_KEY	(1<<22)
3031 serge 5116
#define   DVS_RGB_ORDER_XBGR	(1<<20)
2342 Serge 5117
#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
5118
#define   DVS_YUV_ORDER_YUYV	(0<<16)
5119
#define   DVS_YUV_ORDER_UYVY	(1<<16)
5120
#define   DVS_YUV_ORDER_YVYU	(2<<16)
5121
#define   DVS_YUV_ORDER_VYUY	(3<<16)
5354 serge 5122
#define   DVS_ROTATE_180	(1<<15)
2342 Serge 5123
#define   DVS_DEST_KEY		(1<<2)
5124
#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
5125
#define   DVS_TILED		(1<<10)
5126
#define _DVSALINOFF		0x72184
5127
#define _DVSASTRIDE		0x72188
5128
#define _DVSAPOS		0x7218c
5129
#define _DVSASIZE		0x72190
5130
#define _DVSAKEYVAL		0x72194
5131
#define _DVSAKEYMSK		0x72198
5132
#define _DVSASURF		0x7219c
5133
#define _DVSAKEYMAXVAL		0x721a0
5134
#define _DVSATILEOFF		0x721a4
5135
#define _DVSASURFLIVE		0x721ac
5136
#define _DVSASCALE		0x72204
5137
#define   DVS_SCALE_ENABLE	(1<<31)
5138
#define   DVS_FILTER_MASK	(3<<29)
5139
#define   DVS_FILTER_MEDIUM	(0<<29)
5140
#define   DVS_FILTER_ENHANCING	(1<<29)
5141
#define   DVS_FILTER_SOFTENING	(2<<29)
5142
#define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5143
#define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5144
#define _DVSAGAMC		0x72300
5145
 
5146
#define _DVSBCNTR		0x73180
5147
#define _DVSBLINOFF		0x73184
5148
#define _DVSBSTRIDE		0x73188
5149
#define _DVSBPOS		0x7318c
5150
#define _DVSBSIZE		0x73190
5151
#define _DVSBKEYVAL		0x73194
5152
#define _DVSBKEYMSK		0x73198
5153
#define _DVSBSURF		0x7319c
5154
#define _DVSBKEYMAXVAL		0x731a0
5155
#define _DVSBTILEOFF		0x731a4
5156
#define _DVSBSURFLIVE		0x731ac
5157
#define _DVSBSCALE		0x73204
5158
#define _DVSBGAMC		0x73300
5159
 
6937 serge 5160
#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5161
#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5162
#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5163
#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
5164
#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
5165
#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5166
#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5167
#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5168
#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5169
#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5170
#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5171
#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
2342 Serge 5172
 
5173
#define _SPRA_CTL		0x70280
5174
#define   SPRITE_ENABLE			(1<<31)
5175
#define   SPRITE_GAMMA_ENABLE		(1<<30)
5176
#define   SPRITE_PIXFORMAT_MASK		(7<<25)
5177
#define   SPRITE_FORMAT_YUV422		(0<<25)
5178
#define   SPRITE_FORMAT_RGBX101010	(1<<25)
5179
#define   SPRITE_FORMAT_RGBX888		(2<<25)
5180
#define   SPRITE_FORMAT_RGBX161616	(3<<25)
5181
#define   SPRITE_FORMAT_YUV444		(4<<25)
5182
#define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
3480 Serge 5183
#define   SPRITE_PIPE_CSC_ENABLE	(1<<24)
2342 Serge 5184
#define   SPRITE_SOURCE_KEY		(1<<22)
5185
#define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
5186
#define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
5187
#define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
5188
#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
5189
#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
5190
#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
5191
#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
5192
#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
5354 serge 5193
#define   SPRITE_ROTATE_180		(1<<15)
2342 Serge 5194
#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
5195
#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
5196
#define   SPRITE_TILED			(1<<10)
5197
#define   SPRITE_DEST_KEY		(1<<2)
5198
#define _SPRA_LINOFF		0x70284
5199
#define _SPRA_STRIDE		0x70288
5200
#define _SPRA_POS		0x7028c
5201
#define _SPRA_SIZE		0x70290
5202
#define _SPRA_KEYVAL		0x70294
5203
#define _SPRA_KEYMSK		0x70298
5204
#define _SPRA_SURF		0x7029c
5205
#define _SPRA_KEYMAX		0x702a0
5206
#define _SPRA_TILEOFF		0x702a4
3243 Serge 5207
#define _SPRA_OFFSET		0x702a4
5208
#define _SPRA_SURFLIVE		0x702ac
2342 Serge 5209
#define _SPRA_SCALE		0x70304
5210
#define   SPRITE_SCALE_ENABLE	(1<<31)
5211
#define   SPRITE_FILTER_MASK	(3<<29)
5212
#define   SPRITE_FILTER_MEDIUM	(0<<29)
5213
#define   SPRITE_FILTER_ENHANCING	(1<<29)
5214
#define   SPRITE_FILTER_SOFTENING	(2<<29)
5215
#define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
5216
#define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
5217
#define _SPRA_GAMC		0x70400
5218
 
5219
#define _SPRB_CTL		0x71280
5220
#define _SPRB_LINOFF		0x71284
5221
#define _SPRB_STRIDE		0x71288
5222
#define _SPRB_POS		0x7128c
5223
#define _SPRB_SIZE		0x71290
5224
#define _SPRB_KEYVAL		0x71294
5225
#define _SPRB_KEYMSK		0x71298
5226
#define _SPRB_SURF		0x7129c
5227
#define _SPRB_KEYMAX		0x712a0
5228
#define _SPRB_TILEOFF		0x712a4
3243 Serge 5229
#define _SPRB_OFFSET		0x712a4
5230
#define _SPRB_SURFLIVE		0x712ac
2342 Serge 5231
#define _SPRB_SCALE		0x71304
5232
#define _SPRB_GAMC		0x71400
5233
 
6937 serge 5234
#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5235
#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5236
#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5237
#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
5238
#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5239
#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5240
#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5241
#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5242
#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5243
#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5244
#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5245
#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5246
#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5247
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
2342 Serge 5248
 
4104 Serge 5249
#define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
3746 Serge 5250
#define   SP_ENABLE			(1<<31)
4560 Serge 5251
#define   SP_GAMMA_ENABLE		(1<<30)
3746 Serge 5252
#define   SP_PIXFORMAT_MASK		(0xf<<26)
5253
#define   SP_FORMAT_YUV422		(0<<26)
5254
#define   SP_FORMAT_BGR565		(5<<26)
5255
#define   SP_FORMAT_BGRX8888		(6<<26)
5256
#define   SP_FORMAT_BGRA8888		(7<<26)
5257
#define   SP_FORMAT_RGBX1010102		(8<<26)
5258
#define   SP_FORMAT_RGBA1010102		(9<<26)
5259
#define   SP_FORMAT_RGBX8888		(0xe<<26)
5260
#define   SP_FORMAT_RGBA8888		(0xf<<26)
5354 serge 5261
#define   SP_ALPHA_PREMULTIPLY		(1<<23) /* CHV pipe B */
3746 Serge 5262
#define   SP_SOURCE_KEY			(1<<22)
5263
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
5264
#define   SP_YUV_ORDER_YUYV		(0<<16)
5265
#define   SP_YUV_ORDER_UYVY		(1<<16)
5266
#define   SP_YUV_ORDER_YVYU		(2<<16)
5267
#define   SP_YUV_ORDER_VYUY		(3<<16)
5354 serge 5268
#define   SP_ROTATE_180			(1<<15)
3746 Serge 5269
#define   SP_TILED			(1<<10)
5354 serge 5270
#define   SP_MIRROR			(1<<8) /* CHV pipe B */
4104 Serge 5271
#define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
5272
#define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
5273
#define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
5274
#define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
5275
#define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
5276
#define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
5277
#define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
5278
#define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
5279
#define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
5280
#define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
5354 serge 5281
#define   SP_CONST_ALPHA_ENABLE		(1<<31)
4104 Serge 5282
#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
3746 Serge 5283
 
4104 Serge 5284
#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
5285
#define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
5286
#define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
5287
#define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
5288
#define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
5289
#define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
5290
#define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
5291
#define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
5292
#define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
5293
#define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
5294
#define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
5295
#define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
3746 Serge 5296
 
6937 serge 5297
#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5298
#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5299
#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5300
#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5301
#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5302
#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5303
#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5304
#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5305
#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5306
#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5307
#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5308
#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
3746 Serge 5309
 
5354 serge 5310
/*
5311
 * CHV pipe B sprite CSC
5312
 *
5313
 * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
5314
 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5315
 * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
5316
 */
6937 serge 5317
#define SPCSCYGOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5318
#define SPCSCCBOFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5319
#define SPCSCCROFF(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5354 serge 5320
#define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
5321
#define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
5322
 
6937 serge 5323
#define SPCSCC01(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5324
#define SPCSCC23(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5325
#define SPCSCC45(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5326
#define SPCSCC67(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5327
#define SPCSCC8(sprite)		_MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5354 serge 5328
#define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
5329
#define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
5330
 
6937 serge 5331
#define SPCSCYGICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5332
#define SPCSCCBICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5333
#define SPCSCCRICLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5354 serge 5334
#define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
5335
#define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
5336
 
6937 serge 5337
#define SPCSCYGOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5338
#define SPCSCCBOCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5339
#define SPCSCCROCLAMP(sprite)	_MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5354 serge 5340
#define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
5341
#define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
5342
 
5343
/* Skylake plane registers */
5344
 
5345
#define _PLANE_CTL_1_A				0x70180
5346
#define _PLANE_CTL_2_A				0x70280
5347
#define _PLANE_CTL_3_A				0x70380
5348
#define   PLANE_CTL_ENABLE			(1 << 31)
5349
#define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)
5350
#define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
5351
#define   PLANE_CTL_FORMAT_YUV422		(  0 << 24)
5352
#define   PLANE_CTL_FORMAT_NV12			(  1 << 24)
5353
#define   PLANE_CTL_FORMAT_XRGB_2101010		(  2 << 24)
5354
#define   PLANE_CTL_FORMAT_XRGB_8888		(  4 << 24)
5355
#define   PLANE_CTL_FORMAT_XRGB_16161616F	(  6 << 24)
5356
#define   PLANE_CTL_FORMAT_AYUV			(  8 << 24)
5357
#define   PLANE_CTL_FORMAT_INDEXED		( 12 << 24)
5358
#define   PLANE_CTL_FORMAT_RGB_565		( 14 << 24)
5359
#define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23)
5360
#define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
5361
#define   PLANE_CTL_KEY_ENABLE_SOURCE		(  1 << 21)
5362
#define   PLANE_CTL_KEY_ENABLE_DESTINATION	(  2 << 21)
5363
#define   PLANE_CTL_ORDER_BGRX			(0 << 20)
5364
#define   PLANE_CTL_ORDER_RGBX			(1 << 20)
5365
#define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
5366
#define   PLANE_CTL_YUV422_YUYV			(  0 << 16)
5367
#define   PLANE_CTL_YUV422_UYVY			(  1 << 16)
5368
#define   PLANE_CTL_YUV422_YVYU			(  2 << 16)
5369
#define   PLANE_CTL_YUV422_VYUY			(  3 << 16)
5370
#define   PLANE_CTL_DECOMPRESSION_ENABLE	(1 << 15)
5371
#define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
5372
#define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13)
5373
#define   PLANE_CTL_TILED_MASK			(0x7 << 10)
5374
#define   PLANE_CTL_TILED_LINEAR		(  0 << 10)
5375
#define   PLANE_CTL_TILED_X			(  1 << 10)
5376
#define   PLANE_CTL_TILED_Y			(  4 << 10)
5377
#define   PLANE_CTL_TILED_YF			(  5 << 10)
5378
#define   PLANE_CTL_ALPHA_MASK			(0x3 << 4)
5379
#define   PLANE_CTL_ALPHA_DISABLE		(  0 << 4)
5380
#define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(  2 << 4)
5381
#define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(  3 << 4)
5382
#define   PLANE_CTL_ROTATE_MASK			0x3
5383
#define   PLANE_CTL_ROTATE_0			0x0
6084 serge 5384
#define   PLANE_CTL_ROTATE_90			0x1
5354 serge 5385
#define   PLANE_CTL_ROTATE_180			0x2
6084 serge 5386
#define   PLANE_CTL_ROTATE_270			0x3
5354 serge 5387
#define _PLANE_STRIDE_1_A			0x70188
5388
#define _PLANE_STRIDE_2_A			0x70288
5389
#define _PLANE_STRIDE_3_A			0x70388
5390
#define _PLANE_POS_1_A				0x7018c
5391
#define _PLANE_POS_2_A				0x7028c
5392
#define _PLANE_POS_3_A				0x7038c
5393
#define _PLANE_SIZE_1_A				0x70190
5394
#define _PLANE_SIZE_2_A				0x70290
5395
#define _PLANE_SIZE_3_A				0x70390
5396
#define _PLANE_SURF_1_A				0x7019c
5397
#define _PLANE_SURF_2_A				0x7029c
5398
#define _PLANE_SURF_3_A				0x7039c
5399
#define _PLANE_OFFSET_1_A			0x701a4
5400
#define _PLANE_OFFSET_2_A			0x702a4
5401
#define _PLANE_OFFSET_3_A			0x703a4
5402
#define _PLANE_KEYVAL_1_A			0x70194
5403
#define _PLANE_KEYVAL_2_A			0x70294
5404
#define _PLANE_KEYMSK_1_A			0x70198
5405
#define _PLANE_KEYMSK_2_A			0x70298
5406
#define _PLANE_KEYMAX_1_A			0x701a0
5407
#define _PLANE_KEYMAX_2_A			0x702a0
5408
#define _PLANE_BUF_CFG_1_A			0x7027c
5409
#define _PLANE_BUF_CFG_2_A			0x7037c
6084 serge 5410
#define _PLANE_NV12_BUF_CFG_1_A		0x70278
5411
#define _PLANE_NV12_BUF_CFG_2_A		0x70378
5354 serge 5412
 
5413
#define _PLANE_CTL_1_B				0x71180
5414
#define _PLANE_CTL_2_B				0x71280
5415
#define _PLANE_CTL_3_B				0x71380
5416
#define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5417
#define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5418
#define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5419
#define PLANE_CTL(pipe, plane)	\
6937 serge 5420
	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5354 serge 5421
 
5422
#define _PLANE_STRIDE_1_B			0x71188
5423
#define _PLANE_STRIDE_2_B			0x71288
5424
#define _PLANE_STRIDE_3_B			0x71388
5425
#define _PLANE_STRIDE_1(pipe)	\
5426
	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5427
#define _PLANE_STRIDE_2(pipe)	\
5428
	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5429
#define _PLANE_STRIDE_3(pipe)	\
5430
	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5431
#define PLANE_STRIDE(pipe, plane)	\
6937 serge 5432
	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5354 serge 5433
 
5434
#define _PLANE_POS_1_B				0x7118c
5435
#define _PLANE_POS_2_B				0x7128c
5436
#define _PLANE_POS_3_B				0x7138c
5437
#define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5438
#define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5439
#define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5440
#define PLANE_POS(pipe, plane)	\
6937 serge 5441
	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5354 serge 5442
 
5443
#define _PLANE_SIZE_1_B				0x71190
5444
#define _PLANE_SIZE_2_B				0x71290
5445
#define _PLANE_SIZE_3_B				0x71390
5446
#define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5447
#define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5448
#define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5449
#define PLANE_SIZE(pipe, plane)	\
6937 serge 5450
	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5354 serge 5451
 
5452
#define _PLANE_SURF_1_B				0x7119c
5453
#define _PLANE_SURF_2_B				0x7129c
5454
#define _PLANE_SURF_3_B				0x7139c
5455
#define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5456
#define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5457
#define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5458
#define PLANE_SURF(pipe, plane)	\
6937 serge 5459
	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5354 serge 5460
 
5461
#define _PLANE_OFFSET_1_B			0x711a4
5462
#define _PLANE_OFFSET_2_B			0x712a4
5463
#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5464
#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5465
#define PLANE_OFFSET(pipe, plane)	\
6937 serge 5466
	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5354 serge 5467
 
5468
#define _PLANE_KEYVAL_1_B			0x71194
5469
#define _PLANE_KEYVAL_2_B			0x71294
5470
#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5471
#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5472
#define PLANE_KEYVAL(pipe, plane)	\
6937 serge 5473
	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5354 serge 5474
 
5475
#define _PLANE_KEYMSK_1_B			0x71198
5476
#define _PLANE_KEYMSK_2_B			0x71298
5477
#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5478
#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5479
#define PLANE_KEYMSK(pipe, plane)	\
6937 serge 5480
	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5354 serge 5481
 
5482
#define _PLANE_KEYMAX_1_B			0x711a0
5483
#define _PLANE_KEYMAX_2_B			0x712a0
5484
#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5485
#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5486
#define PLANE_KEYMAX(pipe, plane)	\
6937 serge 5487
	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5354 serge 5488
 
5489
#define _PLANE_BUF_CFG_1_B			0x7127c
5490
#define _PLANE_BUF_CFG_2_B			0x7137c
5491
#define _PLANE_BUF_CFG_1(pipe)	\
5492
	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5493
#define _PLANE_BUF_CFG_2(pipe)	\
5494
	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5495
#define PLANE_BUF_CFG(pipe, plane)	\
6937 serge 5496
	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5354 serge 5497
 
6084 serge 5498
#define _PLANE_NV12_BUF_CFG_1_B		0x71278
5499
#define _PLANE_NV12_BUF_CFG_2_B		0x71378
5500
#define _PLANE_NV12_BUF_CFG_1(pipe)	\
5501
	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5502
#define _PLANE_NV12_BUF_CFG_2(pipe)	\
5503
	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5504
#define PLANE_NV12_BUF_CFG(pipe, plane)	\
6937 serge 5505
	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6084 serge 5506
 
5354 serge 5507
/* SKL new cursor registers */
5508
#define _CUR_BUF_CFG_A				0x7017c
5509
#define _CUR_BUF_CFG_B				0x7117c
6937 serge 5510
#define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5354 serge 5511
 
2325 Serge 5512
/* VBIOS regs */
6937 serge 5513
#define VGACNTRL		_MMIO(0x71400)
2325 Serge 5514
# define VGA_DISP_DISABLE			(1 << 31)
5515
# define VGA_2X_MODE				(1 << 30)
5516
# define VGA_PIPE_B_SELECT			(1 << 29)
5517
 
6937 serge 5518
#define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
3480 Serge 5519
 
2325 Serge 5520
/* Ironlake */
5521
 
6937 serge 5522
#define CPU_VGACNTRL	_MMIO(0x41000)
2325 Serge 5523
 
6937 serge 5524
#define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
6084 serge 5525
#define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
5526
#define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
5527
#define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
5528
#define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
5529
#define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
5530
#define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
5531
#define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
5532
#define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
5533
#define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
5534
#define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
2325 Serge 5535
 
5536
/* refresh rate hardware control */
6937 serge 5537
#define RR_HW_CTL       _MMIO(0x45300)
2325 Serge 5538
#define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
5539
#define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
5540
 
6937 serge 5541
#define FDI_PLL_BIOS_0  _MMIO(0x46000)
2325 Serge 5542
#define  FDI_PLL_FB_CLOCK_MASK  0xff
6937 serge 5543
#define FDI_PLL_BIOS_1  _MMIO(0x46004)
5544
#define FDI_PLL_BIOS_2  _MMIO(0x46008)
5545
#define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
5546
#define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
5547
#define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
2325 Serge 5548
 
6937 serge 5549
#define PCH_3DCGDIS0		_MMIO(0x46020)
2325 Serge 5550
# define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
5551
# define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
5552
 
6937 serge 5553
#define PCH_3DCGDIS1		_MMIO(0x46024)
2325 Serge 5554
# define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
5555
 
6937 serge 5556
#define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
2325 Serge 5557
#define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
5558
#define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
5559
#define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
5560
 
5561
 
5060 serge 5562
#define _PIPEA_DATA_M1		0x60030
2325 Serge 5563
#define  PIPE_DATA_M1_OFFSET    0
5060 serge 5564
#define _PIPEA_DATA_N1		0x60034
2325 Serge 5565
#define  PIPE_DATA_N1_OFFSET    0
5566
 
5060 serge 5567
#define _PIPEA_DATA_M2		0x60038
2325 Serge 5568
#define  PIPE_DATA_M2_OFFSET    0
5060 serge 5569
#define _PIPEA_DATA_N2		0x6003c
2325 Serge 5570
#define  PIPE_DATA_N2_OFFSET    0
5571
 
5060 serge 5572
#define _PIPEA_LINK_M1		0x60040
2325 Serge 5573
#define  PIPE_LINK_M1_OFFSET    0
5060 serge 5574
#define _PIPEA_LINK_N1		0x60044
2325 Serge 5575
#define  PIPE_LINK_N1_OFFSET    0
5576
 
5060 serge 5577
#define _PIPEA_LINK_M2		0x60048
2325 Serge 5578
#define  PIPE_LINK_M2_OFFSET    0
5060 serge 5579
#define _PIPEA_LINK_N2		0x6004c
2325 Serge 5580
#define  PIPE_LINK_N2_OFFSET    0
5581
 
5582
/* PIPEB timing regs are same start from 0x61000 */
5583
 
5060 serge 5584
#define _PIPEB_DATA_M1		0x61030
5585
#define _PIPEB_DATA_N1		0x61034
5586
#define _PIPEB_DATA_M2		0x61038
5587
#define _PIPEB_DATA_N2		0x6103c
5588
#define _PIPEB_LINK_M1		0x61040
5589
#define _PIPEB_LINK_N1		0x61044
5590
#define _PIPEB_LINK_M2		0x61048
5591
#define _PIPEB_LINK_N2		0x6104c
2325 Serge 5592
 
6937 serge 5593
#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5594
#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5595
#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5596
#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5597
#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5598
#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5599
#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5600
#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
2325 Serge 5601
 
5602
/* CPU panel fitter */
5603
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5604
#define _PFA_CTL_1               0x68080
5605
#define _PFB_CTL_1               0x68880
5606
#define  PF_ENABLE              (1<<31)
3243 Serge 5607
#define  PF_PIPE_SEL_MASK_IVB	(3<<29)
5608
#define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
2325 Serge 5609
#define  PF_FILTER_MASK		(3<<23)
5610
#define  PF_FILTER_PROGRAMMED	(0<<23)
5611
#define  PF_FILTER_MED_3x3	(1<<23)
5612
#define  PF_FILTER_EDGE_ENHANCE	(2<<23)
5613
#define  PF_FILTER_EDGE_SOFTEN	(3<<23)
5614
#define _PFA_WIN_SZ		0x68074
5615
#define _PFB_WIN_SZ		0x68874
5616
#define _PFA_WIN_POS		0x68070
5617
#define _PFB_WIN_POS		0x68870
5618
#define _PFA_VSCALE		0x68084
5619
#define _PFB_VSCALE		0x68884
5620
#define _PFA_HSCALE		0x68090
5621
#define _PFB_HSCALE		0x68890
5622
 
6937 serge 5623
#define PF_CTL(pipe)		_MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5624
#define PF_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5625
#define PF_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5626
#define PF_VSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5627
#define PF_HSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2325 Serge 5628
 
5354 serge 5629
#define _PSA_CTL		0x68180
5630
#define _PSB_CTL		0x68980
5631
#define PS_ENABLE		(1<<31)
5632
#define _PSA_WIN_SZ		0x68174
5633
#define _PSB_WIN_SZ		0x68974
5634
#define _PSA_WIN_POS		0x68170
5635
#define _PSB_WIN_POS		0x68970
5636
 
6937 serge 5637
#define PS_CTL(pipe)		_MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5638
#define PS_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5639
#define PS_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5354 serge 5640
 
6084 serge 5641
/*
5642
 * Skylake scalers
5643
 */
5644
#define _PS_1A_CTRL      0x68180
5645
#define _PS_2A_CTRL      0x68280
5646
#define _PS_1B_CTRL      0x68980
5647
#define _PS_2B_CTRL      0x68A80
5648
#define _PS_1C_CTRL      0x69180
5649
#define PS_SCALER_EN        (1 << 31)
5650
#define PS_SCALER_MODE_MASK (3 << 28)
5651
#define PS_SCALER_MODE_DYN  (0 << 28)
5652
#define PS_SCALER_MODE_HQ  (1 << 28)
5653
#define PS_PLANE_SEL_MASK  (7 << 25)
5654
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5655
#define PS_FILTER_MASK         (3 << 23)
5656
#define PS_FILTER_MEDIUM       (0 << 23)
5657
#define PS_FILTER_EDGE_ENHANCE (2 << 23)
5658
#define PS_FILTER_BILINEAR     (3 << 23)
5659
#define PS_VERT3TAP            (1 << 21)
5660
#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5661
#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5662
#define PS_PWRUP_PROGRESS         (1 << 17)
5663
#define PS_V_FILTER_BYPASS        (1 << 8)
5664
#define PS_VADAPT_EN              (1 << 7)
5665
#define PS_VADAPT_MODE_MASK        (3 << 5)
5666
#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5667
#define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
5668
#define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
5669
 
5670
#define _PS_PWR_GATE_1A     0x68160
5671
#define _PS_PWR_GATE_2A     0x68260
5672
#define _PS_PWR_GATE_1B     0x68960
5673
#define _PS_PWR_GATE_2B     0x68A60
5674
#define _PS_PWR_GATE_1C     0x69160
5675
#define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
5676
#define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
5677
#define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
5678
#define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
5679
#define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
5680
#define PS_PWR_GATE_SLPEN_8             0
5681
#define PS_PWR_GATE_SLPEN_16            1
5682
#define PS_PWR_GATE_SLPEN_24            2
5683
#define PS_PWR_GATE_SLPEN_32            3
5684
 
5685
#define _PS_WIN_POS_1A      0x68170
5686
#define _PS_WIN_POS_2A      0x68270
5687
#define _PS_WIN_POS_1B      0x68970
5688
#define _PS_WIN_POS_2B      0x68A70
5689
#define _PS_WIN_POS_1C      0x69170
5690
 
5691
#define _PS_WIN_SZ_1A       0x68174
5692
#define _PS_WIN_SZ_2A       0x68274
5693
#define _PS_WIN_SZ_1B       0x68974
5694
#define _PS_WIN_SZ_2B       0x68A74
5695
#define _PS_WIN_SZ_1C       0x69174
5696
 
5697
#define _PS_VSCALE_1A       0x68184
5698
#define _PS_VSCALE_2A       0x68284
5699
#define _PS_VSCALE_1B       0x68984
5700
#define _PS_VSCALE_2B       0x68A84
5701
#define _PS_VSCALE_1C       0x69184
5702
 
5703
#define _PS_HSCALE_1A       0x68190
5704
#define _PS_HSCALE_2A       0x68290
5705
#define _PS_HSCALE_1B       0x68990
5706
#define _PS_HSCALE_2B       0x68A90
5707
#define _PS_HSCALE_1C       0x69190
5708
 
5709
#define _PS_VPHASE_1A       0x68188
5710
#define _PS_VPHASE_2A       0x68288
5711
#define _PS_VPHASE_1B       0x68988
5712
#define _PS_VPHASE_2B       0x68A88
5713
#define _PS_VPHASE_1C       0x69188
5714
 
5715
#define _PS_HPHASE_1A       0x68194
5716
#define _PS_HPHASE_2A       0x68294
5717
#define _PS_HPHASE_1B       0x68994
5718
#define _PS_HPHASE_2B       0x68A94
5719
#define _PS_HPHASE_1C       0x69194
5720
 
5721
#define _PS_ECC_STAT_1A     0x681D0
5722
#define _PS_ECC_STAT_2A     0x682D0
5723
#define _PS_ECC_STAT_1B     0x689D0
5724
#define _PS_ECC_STAT_2B     0x68AD0
5725
#define _PS_ECC_STAT_1C     0x691D0
5726
 
5727
#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
6937 serge 5728
#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
6084 serge 5729
			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
5730
			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6937 serge 5731
#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
6084 serge 5732
			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5733
			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6937 serge 5734
#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
6084 serge 5735
			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5736
			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6937 serge 5737
#define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5738
			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
5739
			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6937 serge 5740
#define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5741
			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
5742
			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6937 serge 5743
#define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5744
			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
5745
			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6937 serge 5746
#define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5747
			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
5748
			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6937 serge 5749
#define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5750
			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
5751
			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6937 serge 5752
#define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
6084 serge 5753
			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
6937 serge 5754
			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6084 serge 5755
 
2325 Serge 5756
/* legacy palette */
5757
#define _LGC_PALETTE_A           0x4a000
5758
#define _LGC_PALETTE_B           0x4a800
6937 serge 5759
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
2325 Serge 5760
 
4104 Serge 5761
#define _GAMMA_MODE_A		0x4a480
5762
#define _GAMMA_MODE_B		0x4ac80
6937 serge 5763
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4104 Serge 5764
#define GAMMA_MODE_MODE_MASK	(3 << 0)
5765
#define GAMMA_MODE_MODE_8BIT	(0 << 0)
5766
#define GAMMA_MODE_MODE_10BIT	(1 << 0)
5767
#define GAMMA_MODE_MODE_12BIT	(2 << 0)
5768
#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
5769
 
6937 serge 5770
/* DMC/CSR */
5771
#define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
5772
#define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
5773
#define CSR_HTP_ADDR_SKL	0x00500034
5774
#define CSR_SSP_BASE		_MMIO(0x8F074)
5775
#define CSR_HTP_SKL		_MMIO(0x8F004)
5776
#define CSR_LAST_WRITE		_MMIO(0x8F034)
5777
#define CSR_LAST_WRITE_VALUE	0xc003b400
5778
/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
5779
#define CSR_MMIO_START_RANGE	0x80000
5780
#define CSR_MMIO_END_RANGE	0x8FFFF
5781
#define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
5782
#define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
5783
#define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
5784
 
2325 Serge 5785
/* interrupts */
5786
#define DE_MASTER_IRQ_CONTROL   (1 << 31)
5787
#define DE_SPRITEB_FLIP_DONE    (1 << 29)
5788
#define DE_SPRITEA_FLIP_DONE    (1 << 28)
5789
#define DE_PLANEB_FLIP_DONE     (1 << 27)
5790
#define DE_PLANEA_FLIP_DONE     (1 << 26)
4560 Serge 5791
#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
2325 Serge 5792
#define DE_PCU_EVENT            (1 << 25)
5793
#define DE_GTT_FAULT            (1 << 24)
5794
#define DE_POISON               (1 << 23)
5795
#define DE_PERFORM_COUNTER      (1 << 22)
5796
#define DE_PCH_EVENT            (1 << 21)
5797
#define DE_AUX_CHANNEL_A        (1 << 20)
5798
#define DE_DP_A_HOTPLUG         (1 << 19)
5799
#define DE_GSE                  (1 << 18)
5800
#define DE_PIPEB_VBLANK         (1 << 15)
5801
#define DE_PIPEB_EVEN_FIELD     (1 << 14)
5802
#define DE_PIPEB_ODD_FIELD      (1 << 13)
5803
#define DE_PIPEB_LINE_COMPARE   (1 << 12)
5804
#define DE_PIPEB_VSYNC          (1 << 11)
4560 Serge 5805
#define DE_PIPEB_CRC_DONE	(1 << 10)
2325 Serge 5806
#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
5807
#define DE_PIPEA_VBLANK         (1 << 7)
4560 Serge 5808
#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8*(pipe)))
2325 Serge 5809
#define DE_PIPEA_EVEN_FIELD     (1 << 6)
5810
#define DE_PIPEA_ODD_FIELD      (1 << 5)
5811
#define DE_PIPEA_LINE_COMPARE   (1 << 4)
5812
#define DE_PIPEA_VSYNC          (1 << 3)
4560 Serge 5813
#define DE_PIPEA_CRC_DONE	(1 << 2)
5814
#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8*(pipe)))
2325 Serge 5815
#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
4560 Serge 5816
#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8*(pipe)))
2325 Serge 5817
 
5818
/* More Ivybridge lolz */
4104 Serge 5819
#define DE_ERR_INT_IVB			(1<<30)
2325 Serge 5820
#define DE_GSE_IVB			(1<<29)
5821
#define DE_PCH_EVENT_IVB		(1<<28)
5822
#define DE_DP_A_HOTPLUG_IVB		(1<<27)
5823
#define DE_AUX_CHANNEL_A_IVB		(1<<26)
3031 serge 5824
#define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
5825
#define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
5826
#define DE_PIPEC_VBLANK_IVB		(1<<10)
2325 Serge 5827
#define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3031 serge 5828
#define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
5829
#define DE_PIPEB_VBLANK_IVB		(1<<5)
2325 Serge 5830
#define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
5831
#define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
4560 Serge 5832
#define DE_PLANE_FLIP_DONE_IVB(plane)	(1<< (3 + 5*(plane)))
2325 Serge 5833
#define DE_PIPEA_VBLANK_IVB		(1<<0)
6084 serge 5834
#define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
4104 Serge 5835
 
6937 serge 5836
#define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
3031 serge 5837
#define   MASTER_INTERRUPT_ENABLE	(1<<31)
5838
 
6937 serge 5839
#define DEISR   _MMIO(0x44000)
5840
#define DEIMR   _MMIO(0x44004)
5841
#define DEIIR   _MMIO(0x44008)
5842
#define DEIER   _MMIO(0x4400c)
2325 Serge 5843
 
6937 serge 5844
#define GTISR   _MMIO(0x44010)
5845
#define GTIMR   _MMIO(0x44014)
5846
#define GTIIR   _MMIO(0x44018)
5847
#define GTIER   _MMIO(0x4401c)
2325 Serge 5848
 
6937 serge 5849
#define GEN8_MASTER_IRQ			_MMIO(0x44200)
4560 Serge 5850
#define  GEN8_MASTER_IRQ_CONTROL	(1<<31)
5851
#define  GEN8_PCU_IRQ			(1<<30)
5852
#define  GEN8_DE_PCH_IRQ		(1<<23)
5853
#define  GEN8_DE_MISC_IRQ		(1<<22)
5854
#define  GEN8_DE_PORT_IRQ		(1<<20)
5855
#define  GEN8_DE_PIPE_C_IRQ		(1<<18)
5856
#define  GEN8_DE_PIPE_B_IRQ		(1<<17)
5857
#define  GEN8_DE_PIPE_A_IRQ		(1<<16)
6084 serge 5858
#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+(pipe)))
4560 Serge 5859
#define  GEN8_GT_VECS_IRQ		(1<<6)
5060 serge 5860
#define  GEN8_GT_PM_IRQ			(1<<4)
4560 Serge 5861
#define  GEN8_GT_VCS2_IRQ		(1<<3)
5862
#define  GEN8_GT_VCS1_IRQ		(1<<2)
5863
#define  GEN8_GT_BCS_IRQ		(1<<1)
5864
#define  GEN8_GT_RCS_IRQ		(1<<0)
5865
 
6937 serge 5866
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5867
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5868
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5869
#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
4560 Serge 5870
 
6084 serge 5871
#define GEN8_RCS_IRQ_SHIFT 0
4560 Serge 5872
#define GEN8_BCS_IRQ_SHIFT 16
6084 serge 5873
#define GEN8_VCS1_IRQ_SHIFT 0
4560 Serge 5874
#define GEN8_VCS2_IRQ_SHIFT 16
5875
#define GEN8_VECS_IRQ_SHIFT 0
6084 serge 5876
#define GEN8_WD_IRQ_SHIFT 16
4560 Serge 5877
 
6937 serge 5878
#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5879
#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5880
#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5881
#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
4560 Serge 5882
#define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
5883
#define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
5884
#define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
5885
#define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
5886
#define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
5887
#define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
5888
#define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
5060 serge 5889
#define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
4560 Serge 5890
#define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
5891
#define  GEN8_PIPE_VSYNC		(1 << 1)
5892
#define  GEN8_PIPE_VBLANK		(1 << 0)
5354 serge 5893
#define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
6084 serge 5894
#define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
5354 serge 5895
#define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
5896
#define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
5897
#define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
6084 serge 5898
#define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
5354 serge 5899
#define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
5900
#define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
5901
#define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
6084 serge 5902
#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
4560 Serge 5903
#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5904
	(GEN8_PIPE_CURSOR_FAULT | \
5905
	 GEN8_PIPE_SPRITE_FAULT | \
5906
	 GEN8_PIPE_PRIMARY_FAULT)
5354 serge 5907
#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5908
	(GEN9_PIPE_CURSOR_FAULT | \
6084 serge 5909
	 GEN9_PIPE_PLANE4_FAULT | \
5354 serge 5910
	 GEN9_PIPE_PLANE3_FAULT | \
5911
	 GEN9_PIPE_PLANE2_FAULT | \
5912
	 GEN9_PIPE_PLANE1_FAULT)
4560 Serge 5913
 
6937 serge 5914
#define GEN8_DE_PORT_ISR _MMIO(0x44440)
5915
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
5916
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
5917
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
5354 serge 5918
#define  GEN9_AUX_CHANNEL_D		(1 << 27)
5919
#define  GEN9_AUX_CHANNEL_C		(1 << 26)
5920
#define  GEN9_AUX_CHANNEL_B		(1 << 25)
6084 serge 5921
#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
5922
#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
5923
#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
5924
#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
5925
					 BXT_DE_PORT_HP_DDIB | \
5926
					 BXT_DE_PORT_HP_DDIC)
5927
#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
5928
#define  BXT_DE_PORT_GMBUS		(1 << 1)
4560 Serge 5929
#define  GEN8_AUX_CHANNEL_A		(1 << 0)
5930
 
6937 serge 5931
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
5932
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
5933
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
5934
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
4560 Serge 5935
#define  GEN8_DE_MISC_GSE		(1 << 27)
5936
 
6937 serge 5937
#define GEN8_PCU_ISR _MMIO(0x444e0)
5938
#define GEN8_PCU_IMR _MMIO(0x444e4)
5939
#define GEN8_PCU_IIR _MMIO(0x444e8)
5940
#define GEN8_PCU_IER _MMIO(0x444ec)
4560 Serge 5941
 
6937 serge 5942
#define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
2325 Serge 5943
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
5944
#define  ILK_ELPIN_409_SELECT	(1 << 25)
5945
#define  ILK_DPARB_GATE	(1<<22)
5946
#define  ILK_VSDPFD_FULL	(1<<21)
6937 serge 5947
#define FUSE_STRAP			_MMIO(0x42014)
5060 serge 5948
#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
5949
#define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
5950
#define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
5951
#define  ILK_HDCP_DISABLE		(1 << 25)
5952
#define  ILK_eDP_A_DISABLE		(1 << 24)
5953
#define  HSW_CDCLK_LIMIT		(1 << 24)
5954
#define  ILK_DESKTOP			(1 << 23)
2325 Serge 5955
 
6937 serge 5956
#define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
3243 Serge 5957
#define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
5958
#define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
5959
#define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
5960
#define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
5961
#define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
2325 Serge 5962
 
6937 serge 5963
#define IVB_CHICKEN3	_MMIO(0x4200c)
2342 Serge 5964
# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
5965
# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
5966
 
6937 serge 5967
#define CHICKEN_PAR1_1		_MMIO(0x42080)
4560 Serge 5968
#define  DPA_MASK_VBLANK_SRD	(1 << 15)
4104 Serge 5969
#define  FORCE_ARB_IDLE_PLANES	(1 << 14)
5970
 
4560 Serge 5971
#define _CHICKEN_PIPESL_1_A	0x420b0
5972
#define _CHICKEN_PIPESL_1_B	0x420b4
5060 serge 5973
#define  HSW_FBCQ_DIS			(1 << 22)
5974
#define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
6937 serge 5975
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4560 Serge 5976
 
6937 serge 5977
#define DISP_ARB_CTL	_MMIO(0x45000)
2325 Serge 5978
#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
5979
#define  DISP_FBC_WM_DIS		(1<<15)
6937 serge 5980
#define DISP_ARB_CTL2	_MMIO(0x45004)
4560 Serge 5981
#define  DISP_DATA_PARTITION_5_6	(1<<6)
6937 serge 5982
#define DBUF_CTL	_MMIO(0x45008)
6084 serge 5983
#define  DBUF_POWER_REQUEST		(1<<31)
5984
#define  DBUF_POWER_STATE		(1<<30)
6937 serge 5985
#define GEN7_MSG_CTL	_MMIO(0x45010)
3746 Serge 5986
#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
5987
#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
6937 serge 5988
#define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
5060 serge 5989
#define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
2325 Serge 5990
 
6937 serge 5991
#define SKL_DFSM			_MMIO(0x51000)
6084 serge 5992
#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
5993
#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
5994
#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
5995
#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
5996
#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
5997
 
6937 serge 5998
#define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
6084 serge 5999
#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
6000
 
3031 serge 6001
/* GEN7 chicken */
6937 serge 6002
#define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
3031 serge 6003
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
6084 serge 6004
# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
6937 serge 6005
#define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
4560 Serge 6006
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
3031 serge 6007
 
6937 serge 6008
#define HIZ_CHICKEN					_MMIO(0x7018)
6084 serge 6009
# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
6010
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
6011
 
6937 serge 6012
#define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
6084 serge 6013
#define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
6014
 
6937 serge 6015
#define GEN7_L3SQCREG1				_MMIO(0xB010)
5060 serge 6016
#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
6017
 
6937 serge 6018
#define GEN8_L3SQCREG1				_MMIO(0xB100)
6084 serge 6019
#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
6020
 
6937 serge 6021
#define GEN7_L3CNTLREG1				_MMIO(0xB01C)
5060 serge 6022
#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
3243 Serge 6023
#define  GEN7_L3AGDIS				(1<<19)
6937 serge 6024
#define GEN7_L3CNTLREG2				_MMIO(0xB020)
6025
#define GEN7_L3CNTLREG3				_MMIO(0xB024)
3031 serge 6026
 
6937 serge 6027
#define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
3031 serge 6028
#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
6029
 
6937 serge 6030
#define GEN7_L3SQCREG4				_MMIO(0xb034)
3243 Serge 6031
#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
6032
 
6937 serge 6033
#define GEN8_L3SQCREG4				_MMIO(0xb118)
6084 serge 6034
#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
6035
#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
6036
 
4560 Serge 6037
/* GEN8 chicken */
6937 serge 6038
#define HDC_CHICKEN0				_MMIO(0x7300)
6084 serge 6039
#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
6040
#define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
6041
#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
6042
#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
4560 Serge 6043
#define  HDC_FORCE_NON_COHERENT			(1<<4)
6084 serge 6044
#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
4560 Serge 6045
 
6084 serge 6046
/* GEN9 chicken */
6937 serge 6047
#define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
6084 serge 6048
#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
6049
 
3031 serge 6050
/* WaCatErrorRejectionIssue */
6937 serge 6051
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
3031 serge 6052
#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
6053
 
6937 serge 6054
#define HSW_SCRATCH1				_MMIO(0xb038)
4104 Serge 6055
#define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
6056
 
6937 serge 6057
#define BDW_SCRATCH1					_MMIO(0xb11c)
6084 serge 6058
#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
6059
 
2325 Serge 6060
/* PCH */
6061
 
3031 serge 6062
/* south display engine interrupt: IBX */
2325 Serge 6063
#define SDE_AUDIO_POWER_D	(1 << 27)
6064
#define SDE_AUDIO_POWER_C	(1 << 26)
6065
#define SDE_AUDIO_POWER_B	(1 << 25)
6066
#define SDE_AUDIO_POWER_SHIFT	(25)
6067
#define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
6068
#define SDE_GMBUS		(1 << 24)
6069
#define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
6070
#define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
6071
#define SDE_AUDIO_HDCP_MASK	(3 << 22)
6072
#define SDE_AUDIO_TRANSB	(1 << 21)
6073
#define SDE_AUDIO_TRANSA	(1 << 20)
6074
#define SDE_AUDIO_TRANS_MASK	(3 << 20)
6075
#define SDE_POISON		(1 << 19)
6076
/* 18 reserved */
6077
#define SDE_FDI_RXB		(1 << 17)
6078
#define SDE_FDI_RXA		(1 << 16)
6079
#define SDE_FDI_MASK		(3 << 16)
6080
#define SDE_AUXD		(1 << 15)
6081
#define SDE_AUXC		(1 << 14)
6082
#define SDE_AUXB		(1 << 13)
6083
#define SDE_AUX_MASK		(7 << 13)
6084
/* 12 reserved */
6085
#define SDE_CRT_HOTPLUG         (1 << 11)
6086
#define SDE_PORTD_HOTPLUG       (1 << 10)
6087
#define SDE_PORTC_HOTPLUG       (1 << 9)
6088
#define SDE_PORTB_HOTPLUG       (1 << 8)
6089
#define SDE_SDVOB_HOTPLUG       (1 << 6)
3746 Serge 6090
#define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
6091
				 SDE_SDVOB_HOTPLUG |	\
6092
				 SDE_PORTB_HOTPLUG |	\
6093
				 SDE_PORTC_HOTPLUG |	\
6094
				 SDE_PORTD_HOTPLUG)
2325 Serge 6095
#define SDE_TRANSB_CRC_DONE	(1 << 5)
6096
#define SDE_TRANSB_CRC_ERR	(1 << 4)
6097
#define SDE_TRANSB_FIFO_UNDER	(1 << 3)
6098
#define SDE_TRANSA_CRC_DONE	(1 << 2)
6099
#define SDE_TRANSA_CRC_ERR	(1 << 1)
6100
#define SDE_TRANSA_FIFO_UNDER	(1 << 0)
6101
#define SDE_TRANS_MASK		(0x3f)
3031 serge 6102
 
6103
/* south display engine interrupt: CPT/PPT */
6104
#define SDE_AUDIO_POWER_D_CPT	(1 << 31)
6105
#define SDE_AUDIO_POWER_C_CPT	(1 << 30)
6106
#define SDE_AUDIO_POWER_B_CPT	(1 << 29)
6107
#define SDE_AUDIO_POWER_SHIFT_CPT   29
6108
#define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
6109
#define SDE_AUXD_CPT		(1 << 27)
6110
#define SDE_AUXC_CPT		(1 << 26)
6111
#define SDE_AUXB_CPT		(1 << 25)
6112
#define SDE_AUX_MASK_CPT	(7 << 25)
6084 serge 6113
#define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
6114
#define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
2325 Serge 6115
#define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
6116
#define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
6117
#define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3031 serge 6118
#define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3746 Serge 6119
#define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
2325 Serge 6120
#define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3746 Serge 6121
				 SDE_SDVOB_HOTPLUG_CPT |	\
2325 Serge 6122
				 SDE_PORTD_HOTPLUG_CPT |	\
6123
				 SDE_PORTC_HOTPLUG_CPT |	\
6124
				 SDE_PORTB_HOTPLUG_CPT)
6084 serge 6125
#define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
6126
				 SDE_PORTD_HOTPLUG_CPT |	\
6127
				 SDE_PORTC_HOTPLUG_CPT |	\
6128
				 SDE_PORTB_HOTPLUG_CPT |	\
6129
				 SDE_PORTA_HOTPLUG_SPT)
3031 serge 6130
#define SDE_GMBUS_CPT		(1 << 17)
4104 Serge 6131
#define SDE_ERROR_CPT		(1 << 16)
3031 serge 6132
#define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
6133
#define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
6134
#define SDE_FDI_RXC_CPT		(1 << 8)
6135
#define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
6136
#define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
6137
#define SDE_FDI_RXB_CPT		(1 << 4)
6138
#define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
6139
#define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
6140
#define SDE_FDI_RXA_CPT		(1 << 0)
6141
#define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
6142
				 SDE_AUDIO_CP_REQ_B_CPT | \
6143
				 SDE_AUDIO_CP_REQ_A_CPT)
6144
#define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
6145
				 SDE_AUDIO_CP_CHG_B_CPT | \
6146
				 SDE_AUDIO_CP_CHG_A_CPT)
6147
#define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
6148
				 SDE_FDI_RXB_CPT | \
6149
				 SDE_FDI_RXA_CPT)
2325 Serge 6150
 
6937 serge 6151
#define SDEISR  _MMIO(0xc4000)
6152
#define SDEIMR  _MMIO(0xc4004)
6153
#define SDEIIR  _MMIO(0xc4008)
6154
#define SDEIER  _MMIO(0xc400c)
2325 Serge 6155
 
6937 serge 6156
#define SERR_INT			_MMIO(0xc4040)
4104 Serge 6157
#define  SERR_INT_POISON		(1<<31)
6158
#define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
6159
#define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
6160
#define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
6084 serge 6161
#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
4104 Serge 6162
 
2325 Serge 6163
/* digital port hotplug */
6937 serge 6164
#define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
6084 serge 6165
#define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
6166
#define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
6167
#define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
6168
#define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
6169
#define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
6170
#define  PORTD_HOTPLUG_ENABLE		(1 << 20)
6171
#define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
6172
#define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
6173
#define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
6174
#define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
6175
#define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
6176
#define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
3480 Serge 6177
#define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
6084 serge 6178
#define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
3480 Serge 6179
#define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
6084 serge 6180
#define  PORTC_HOTPLUG_ENABLE		(1 << 12)
6181
#define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
6182
#define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
6183
#define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
6184
#define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
6185
#define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
6186
#define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
3480 Serge 6187
#define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
6084 serge 6188
#define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
3480 Serge 6189
#define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
6084 serge 6190
#define  PORTB_HOTPLUG_ENABLE		(1 << 4)
6191
#define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
6192
#define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
6193
#define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
6194
#define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
6195
#define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
6196
#define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
3480 Serge 6197
#define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
6084 serge 6198
#define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
3480 Serge 6199
#define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
2325 Serge 6200
 
6937 serge 6201
#define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
6084 serge 6202
#define  PORTE_HOTPLUG_ENABLE		(1 << 4)
6203
#define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
6204
#define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
6205
#define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
6206
#define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
6207
 
6937 serge 6208
#define PCH_GPIOA               _MMIO(0xc5010)
6209
#define PCH_GPIOB               _MMIO(0xc5014)
6210
#define PCH_GPIOC               _MMIO(0xc5018)
6211
#define PCH_GPIOD               _MMIO(0xc501c)
6212
#define PCH_GPIOE               _MMIO(0xc5020)
6213
#define PCH_GPIOF               _MMIO(0xc5024)
2325 Serge 6214
 
6937 serge 6215
#define PCH_GMBUS0		_MMIO(0xc5100)
6216
#define PCH_GMBUS1		_MMIO(0xc5104)
6217
#define PCH_GMBUS2		_MMIO(0xc5108)
6218
#define PCH_GMBUS3		_MMIO(0xc510c)
6219
#define PCH_GMBUS4		_MMIO(0xc5110)
6220
#define PCH_GMBUS5		_MMIO(0xc5120)
2325 Serge 6221
 
6222
#define _PCH_DPLL_A              0xc6014
6223
#define _PCH_DPLL_B              0xc6018
6937 serge 6224
#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
2325 Serge 6225
 
6226
#define _PCH_FPA0                0xc6040
6227
#define  FP_CB_TUNE		(0x3<<22)
6228
#define _PCH_FPA1                0xc6044
6229
#define _PCH_FPB0                0xc6048
6230
#define _PCH_FPB1                0xc604c
6937 serge 6231
#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6232
#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
2325 Serge 6233
 
6937 serge 6234
#define PCH_DPLL_TEST           _MMIO(0xc606c)
2325 Serge 6235
 
6937 serge 6236
#define PCH_DREF_CONTROL        _MMIO(0xC6200)
2325 Serge 6237
#define  DREF_CONTROL_MASK      0x7fc3
6238
#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
6239
#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
6240
#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
6241
#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
6242
#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
6243
#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
6244
#define  DREF_SSC_SOURCE_MASK			(3<<11)
6245
#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
6246
#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
6247
#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
6248
#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
6249
#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
6250
#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
6251
#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
6252
#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
6253
#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
6254
#define  DREF_SSC1_DISABLE                      (0<<1)
6255
#define  DREF_SSC1_ENABLE                       (1<<1)
6256
#define  DREF_SSC4_DISABLE                      (0)
6257
#define  DREF_SSC4_ENABLE                       (1)
6258
 
6937 serge 6259
#define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
2325 Serge 6260
#define  FDL_TP1_TIMER_SHIFT    12
6261
#define  FDL_TP1_TIMER_MASK     (3<<12)
6262
#define  FDL_TP2_TIMER_SHIFT    10
6263
#define  FDL_TP2_TIMER_MASK     (3<<10)
6264
#define  RAWCLK_FREQ_MASK       0x3ff
6265
 
6937 serge 6266
#define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
2325 Serge 6267
 
6937 serge 6268
#define PCH_SSC4_PARMS          _MMIO(0xc6210)
6269
#define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
2325 Serge 6270
 
6937 serge 6271
#define PCH_DPLL_SEL		_MMIO(0xc7000)
6084 serge 6272
#define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
4104 Serge 6273
#define	 TRANS_DPLLA_SEL(pipe)		0
6084 serge 6274
#define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
2325 Serge 6275
 
6276
/* transcoder */
6277
 
4104 Serge 6278
#define _PCH_TRANS_HTOTAL_A		0xe0000
6084 serge 6279
#define  TRANS_HTOTAL_SHIFT		16
6280
#define  TRANS_HACTIVE_SHIFT		0
4104 Serge 6281
#define _PCH_TRANS_HBLANK_A		0xe0004
6084 serge 6282
#define  TRANS_HBLANK_END_SHIFT		16
6283
#define  TRANS_HBLANK_START_SHIFT	0
4104 Serge 6284
#define _PCH_TRANS_HSYNC_A		0xe0008
6084 serge 6285
#define  TRANS_HSYNC_END_SHIFT		16
6286
#define  TRANS_HSYNC_START_SHIFT	0
4104 Serge 6287
#define _PCH_TRANS_VTOTAL_A		0xe000c
6084 serge 6288
#define  TRANS_VTOTAL_SHIFT		16
6289
#define  TRANS_VACTIVE_SHIFT		0
4104 Serge 6290
#define _PCH_TRANS_VBLANK_A		0xe0010
6084 serge 6291
#define  TRANS_VBLANK_END_SHIFT		16
6292
#define  TRANS_VBLANK_START_SHIFT	0
4104 Serge 6293
#define _PCH_TRANS_VSYNC_A		0xe0014
6084 serge 6294
#define  TRANS_VSYNC_END_SHIFT	 	16
6295
#define  TRANS_VSYNC_START_SHIFT	0
4104 Serge 6296
#define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
2325 Serge 6297
 
4104 Serge 6298
#define _PCH_TRANSA_DATA_M1	0xe0030
6299
#define _PCH_TRANSA_DATA_N1	0xe0034
6300
#define _PCH_TRANSA_DATA_M2	0xe0038
6301
#define _PCH_TRANSA_DATA_N2	0xe003c
6302
#define _PCH_TRANSA_LINK_M1	0xe0040
6303
#define _PCH_TRANSA_LINK_N1	0xe0044
6304
#define _PCH_TRANSA_LINK_M2	0xe0048
6305
#define _PCH_TRANSA_LINK_N2	0xe004c
2325 Serge 6306
 
5060 serge 6307
/* Per-transcoder DIP controls (PCH) */
2325 Serge 6308
#define _VIDEO_DIP_CTL_A         0xe0200
6309
#define _VIDEO_DIP_DATA_A        0xe0208
6310
#define _VIDEO_DIP_GCP_A         0xe0210
6084 serge 6311
#define  GCP_COLOR_INDICATION		(1 << 2)
6312
#define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
6313
#define  GCP_AV_MUTE			(1 << 0)
2325 Serge 6314
 
6315
#define _VIDEO_DIP_CTL_B         0xe1200
6316
#define _VIDEO_DIP_DATA_B        0xe1208
6317
#define _VIDEO_DIP_GCP_B         0xe1210
6318
 
6937 serge 6319
#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6320
#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6321
#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
2325 Serge 6322
 
5060 serge 6323
/* Per-transcoder DIP controls (VLV) */
6937 serge 6324
#define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
6325
#define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
6326
#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
3031 serge 6327
 
6937 serge 6328
#define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
6329
#define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
6330
#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
3031 serge 6331
 
6937 serge 6332
#define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
6333
#define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
6334
#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
5060 serge 6335
 
3031 serge 6336
#define VLV_TVIDEO_DIP_CTL(pipe) \
6937 serge 6337
	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6338
	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
3031 serge 6339
#define VLV_TVIDEO_DIP_DATA(pipe) \
6937 serge 6340
	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6341
	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
3031 serge 6342
#define VLV_TVIDEO_DIP_GCP(pipe) \
6937 serge 6343
	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6344
		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
3031 serge 6345
 
6346
/* Haswell DIP controls */
6347
 
6937 serge 6348
#define _HSW_VIDEO_DIP_CTL_A		0x60200
6349
#define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
6350
#define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
6351
#define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
6352
#define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
6353
#define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
6354
#define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
6355
#define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
6356
#define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
6357
#define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
6358
#define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
6359
#define _HSW_VIDEO_DIP_GCP_A		0x60210
3031 serge 6360
 
6937 serge 6361
#define _HSW_VIDEO_DIP_CTL_B		0x61200
6362
#define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
6363
#define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
6364
#define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
6365
#define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
6366
#define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
6367
#define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
6368
#define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
6369
#define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
6370
#define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
6371
#define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
6372
#define _HSW_VIDEO_DIP_GCP_B		0x61210
3031 serge 6373
 
6937 serge 6374
#define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6375
#define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6376
#define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6377
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6378
#define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6379
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6380
 
6381
#define _HSW_STEREO_3D_CTL_A		0x70020
4104 Serge 6382
#define   S3D_ENABLE		(1<<31)
6937 serge 6383
#define _HSW_STEREO_3D_CTL_B		0x71020
2325 Serge 6384
 
6937 serge 6385
#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
2325 Serge 6386
 
4104 Serge 6387
#define _PCH_TRANS_HTOTAL_B          0xe1000
6388
#define _PCH_TRANS_HBLANK_B          0xe1004
6389
#define _PCH_TRANS_HSYNC_B           0xe1008
6390
#define _PCH_TRANS_VTOTAL_B          0xe100c
6391
#define _PCH_TRANS_VBLANK_B          0xe1010
6392
#define _PCH_TRANS_VSYNC_B           0xe1014
6393
#define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
2325 Serge 6394
 
6937 serge 6395
#define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6396
#define PCH_TRANS_HBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6397
#define PCH_TRANS_HSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6398
#define PCH_TRANS_VTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6399
#define PCH_TRANS_VBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6400
#define PCH_TRANS_VSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6401
#define PCH_TRANS_VSYNCSHIFT(pipe)	_MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
2325 Serge 6402
 
4104 Serge 6403
#define _PCH_TRANSB_DATA_M1	0xe1030
6404
#define _PCH_TRANSB_DATA_N1	0xe1034
6405
#define _PCH_TRANSB_DATA_M2	0xe1038
6406
#define _PCH_TRANSB_DATA_N2	0xe103c
6407
#define _PCH_TRANSB_LINK_M1	0xe1040
6408
#define _PCH_TRANSB_LINK_N1	0xe1044
6409
#define _PCH_TRANSB_LINK_M2	0xe1048
6410
#define _PCH_TRANSB_LINK_N2	0xe104c
6411
 
6937 serge 6412
#define PCH_TRANS_DATA_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6413
#define PCH_TRANS_DATA_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6414
#define PCH_TRANS_DATA_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6415
#define PCH_TRANS_DATA_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6416
#define PCH_TRANS_LINK_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6417
#define PCH_TRANS_LINK_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6418
#define PCH_TRANS_LINK_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6419
#define PCH_TRANS_LINK_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4104 Serge 6420
 
6421
#define _PCH_TRANSACONF              0xf0008
6422
#define _PCH_TRANSBCONF              0xf1008
6937 serge 6423
#define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6424
#define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
2325 Serge 6425
#define  TRANS_DISABLE          (0<<31)
6426
#define  TRANS_ENABLE           (1<<31)
6427
#define  TRANS_STATE_MASK       (1<<30)
6428
#define  TRANS_STATE_DISABLE    (0<<30)
6429
#define  TRANS_STATE_ENABLE     (1<<30)
6430
#define  TRANS_FSYNC_DELAY_HB1  (0<<27)
6431
#define  TRANS_FSYNC_DELAY_HB2  (1<<27)
6432
#define  TRANS_FSYNC_DELAY_HB3  (2<<27)
6433
#define  TRANS_FSYNC_DELAY_HB4  (3<<27)
3031 serge 6434
#define  TRANS_INTERLACE_MASK   (7<<21)
2325 Serge 6435
#define  TRANS_PROGRESSIVE      (0<<21)
3031 serge 6436
#define  TRANS_INTERLACED       (3<<21)
6437
#define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
2325 Serge 6438
#define  TRANS_8BPC             (0<<5)
6439
#define  TRANS_10BPC            (1<<5)
6440
#define  TRANS_6BPC             (2<<5)
6441
#define  TRANS_12BPC            (3<<5)
6442
 
3243 Serge 6443
#define _TRANSA_CHICKEN1	 0xf0060
6444
#define _TRANSB_CHICKEN1	 0xf1060
6937 serge 6445
#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6084 serge 6446
#define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1<<10)
3243 Serge 6447
#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
2325 Serge 6448
#define _TRANSA_CHICKEN2	 0xf0064
6449
#define _TRANSB_CHICKEN2	 0xf1064
6937 serge 6450
#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6084 serge 6451
#define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1<<31)
3746 Serge 6452
#define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
6453
#define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
6454
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
6455
#define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
2325 Serge 6456
 
6937 serge 6457
#define SOUTH_CHICKEN1		_MMIO(0xc2000)
2325 Serge 6458
#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
6459
#define  FDIA_PHASE_SYNC_SHIFT_EN	18
6084 serge 6460
#define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6461
#define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3243 Serge 6462
#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
6084 serge 6463
#define  SPT_PWM_GRANULARITY		(1<<0)
6937 serge 6464
#define SOUTH_CHICKEN2		_MMIO(0xc2004)
3243 Serge 6465
#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
6466
#define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
6084 serge 6467
#define  LPT_PWM_GRANULARITY		(1<<5)
6468
#define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
2325 Serge 6469
 
6470
#define _FDI_RXA_CHICKEN         0xc200c
6471
#define _FDI_RXB_CHICKEN         0xc2010
6472
#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
6473
#define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
6937 serge 6474
#define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
2325 Serge 6475
 
6937 serge 6476
#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
4280 Serge 6477
#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
2325 Serge 6478
#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4280 Serge 6479
#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
3243 Serge 6480
#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
2325 Serge 6481
 
6482
/* CPU: FDI_TX */
6483
#define _FDI_TXA_CTL             0x60100
6484
#define _FDI_TXB_CTL             0x61100
6937 serge 6485
#define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
2325 Serge 6486
#define  FDI_TX_DISABLE         (0<<31)
6487
#define  FDI_TX_ENABLE          (1<<31)
6488
#define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
6489
#define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
6490
#define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
6491
#define  FDI_LINK_TRAIN_NONE            (3<<28)
6492
#define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
6493
#define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
6494
#define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
6495
#define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
6496
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6497
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6498
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
6499
#define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
6500
/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6501
   SNB has different settings. */
6502
/* SNB A-stepping */
6503
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
6504
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
6505
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
6506
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
6507
/* SNB B-stepping */
6508
#define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
6509
#define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
6510
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
6511
#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
6512
#define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
4104 Serge 6513
#define  FDI_DP_PORT_WIDTH_SHIFT		19
6514
#define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
6515
#define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
2325 Serge 6516
#define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
6517
/* Ironlake: hardwired to 1 */
6518
#define  FDI_TX_PLL_ENABLE              (1<<14)
6519
 
6520
/* Ivybridge has different bits for lolz */
6521
#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
6522
#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
6523
#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
6524
#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
6525
 
6526
/* both Tx and Rx */
2342 Serge 6527
#define  FDI_COMPOSITE_SYNC		(1<<11)
2325 Serge 6528
#define  FDI_LINK_TRAIN_AUTO		(1<<10)
6529
#define  FDI_SCRAMBLING_ENABLE          (0<<7)
6530
#define  FDI_SCRAMBLING_DISABLE         (1<<7)
6531
 
6532
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6533
#define _FDI_RXA_CTL             0xf000c
6534
#define _FDI_RXB_CTL             0xf100c
6937 serge 6535
#define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
2325 Serge 6536
#define  FDI_RX_ENABLE          (1<<31)
6537
/* train, dp width same as FDI_TX */
6538
#define  FDI_FS_ERRC_ENABLE		(1<<27)
6539
#define  FDI_FE_ERRC_ENABLE		(1<<26)
3243 Serge 6540
#define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
2325 Serge 6541
#define  FDI_8BPC                       (0<<16)
6542
#define  FDI_10BPC                      (1<<16)
6543
#define  FDI_6BPC                       (2<<16)
6544
#define  FDI_12BPC                      (3<<16)
3480 Serge 6545
#define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
2325 Serge 6546
#define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
6547
#define  FDI_RX_PLL_ENABLE              (1<<13)
6548
#define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
6549
#define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
6550
#define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
6551
#define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
6552
#define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
6553
#define  FDI_PCDCLK	                (1<<4)
6554
/* CPT */
6555
#define  FDI_AUTO_TRAINING			(1<<10)
6556
#define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
6557
#define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
6558
#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
6559
#define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
6560
#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
6561
 
6084 serge 6562
#define _FDI_RXA_MISC			0xf0010
6563
#define _FDI_RXB_MISC			0xf1010
3243 Serge 6564
#define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
6565
#define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
6566
#define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
6567
#define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
6568
#define  FDI_RX_TP1_TO_TP2_48		(2<<20)
6569
#define  FDI_RX_TP1_TO_TP2_64		(3<<20)
6570
#define  FDI_RX_FDI_DELAY_90		(0x90<<0)
6937 serge 6571
#define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3243 Serge 6572
 
2325 Serge 6573
#define _FDI_RXA_TUSIZE1         0xf0030
6574
#define _FDI_RXA_TUSIZE2         0xf0038
6575
#define _FDI_RXB_TUSIZE1         0xf1030
6576
#define _FDI_RXB_TUSIZE2         0xf1038
6937 serge 6577
#define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6578
#define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
2325 Serge 6579
 
6580
/* FDI_RX interrupt register format */
6581
#define FDI_RX_INTER_LANE_ALIGN         (1<<10)
6582
#define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
6583
#define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
6584
#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
6585
#define FDI_RX_FS_CODE_ERR              (1<<6)
6586
#define FDI_RX_FE_CODE_ERR              (1<<5)
6587
#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
6588
#define FDI_RX_HDCP_LINK_FAIL           (1<<3)
6589
#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
6590
#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
6591
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
6592
 
6593
#define _FDI_RXA_IIR             0xf0014
6594
#define _FDI_RXA_IMR             0xf0018
6595
#define _FDI_RXB_IIR             0xf1014
6596
#define _FDI_RXB_IMR             0xf1018
6937 serge 6597
#define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6598
#define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
2325 Serge 6599
 
6937 serge 6600
#define FDI_PLL_CTL_1           _MMIO(0xfe000)
6601
#define FDI_PLL_CTL_2           _MMIO(0xfe004)
2325 Serge 6602
 
6937 serge 6603
#define PCH_LVDS	_MMIO(0xe1180)
2325 Serge 6604
#define  LVDS_DETECTED	(1 << 1)
6605
 
3031 serge 6606
/* vlv has 2 sets of panel control regs. */
6937 serge 6607
#define _PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
6608
#define _PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
6609
#define _PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
5354 serge 6610
#define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
6937 serge 6611
#define _PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
6612
#define _PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
2325 Serge 6613
 
6937 serge 6614
#define _PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
6615
#define _PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
6616
#define _PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
6617
#define _PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
6618
#define _PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
2325 Serge 6619
 
6937 serge 6620
#define VLV_PIPE_PP_STATUS(pipe)	_MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
6621
#define VLV_PIPE_PP_CONTROL(pipe)	_MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
6622
#define VLV_PIPE_PP_ON_DELAYS(pipe)	_MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
6623
#define VLV_PIPE_PP_OFF_DELAYS(pipe)	_MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
6624
#define VLV_PIPE_PP_DIVISOR(pipe)	_MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
3746 Serge 6625
 
6937 serge 6626
#define _PCH_PP_STATUS		0xc7200
6627
#define _PCH_PP_CONTROL		0xc7204
2325 Serge 6628
#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
2342 Serge 6629
#define  PANEL_UNLOCK_MASK	(0xffff << 16)
6084 serge 6630
#define  BXT_POWER_CYCLE_DELAY_MASK	(0x1f0)
6631
#define  BXT_POWER_CYCLE_DELAY_SHIFT	4
2325 Serge 6632
#define  EDP_FORCE_VDD		(1 << 3)
6633
#define  EDP_BLC_ENABLE		(1 << 2)
6634
#define  PANEL_POWER_RESET	(1 << 1)
6635
#define  PANEL_POWER_OFF	(0 << 0)
6636
#define  PANEL_POWER_ON		(1 << 0)
6937 serge 6637
#define _PCH_PP_ON_DELAYS	0xc7208
2342 Serge 6638
#define  PANEL_PORT_SELECT_MASK	(3 << 30)
6639
#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
6640
#define  PANEL_PORT_SELECT_DPA	(1 << 30)
6641
#define  PANEL_PORT_SELECT_DPC	(2 << 30)
6642
#define  PANEL_PORT_SELECT_DPD	(3 << 30)
6643
#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
6644
#define  PANEL_POWER_UP_DELAY_SHIFT	16
6645
#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
6646
#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
6647
 
6937 serge 6648
#define _PCH_PP_OFF_DELAYS		0xc720c
2342 Serge 6649
#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
6650
#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
6651
#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
6652
#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
6653
 
6937 serge 6654
#define _PCH_PP_DIVISOR			0xc7210
2342 Serge 6655
#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
6656
#define  PP_REFERENCE_DIVIDER_SHIFT	8
6657
#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
6658
#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
2325 Serge 6659
 
6937 serge 6660
#define PCH_PP_STATUS			_MMIO(_PCH_PP_STATUS)
6661
#define PCH_PP_CONTROL			_MMIO(_PCH_PP_CONTROL)
6662
#define PCH_PP_ON_DELAYS		_MMIO(_PCH_PP_ON_DELAYS)
6663
#define PCH_PP_OFF_DELAYS		_MMIO(_PCH_PP_OFF_DELAYS)
6664
#define PCH_PP_DIVISOR			_MMIO(_PCH_PP_DIVISOR)
6665
 
6084 serge 6666
/* BXT PPS changes - 2nd set of PPS registers */
6667
#define _BXT_PP_STATUS2 	0xc7300
6668
#define _BXT_PP_CONTROL2 	0xc7304
6669
#define _BXT_PP_ON_DELAYS2	0xc7308
6670
#define _BXT_PP_OFF_DELAYS2	0xc730c
6671
 
6937 serge 6672
#define BXT_PP_STATUS(n)	_MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
6673
#define BXT_PP_CONTROL(n)	_MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6674
#define BXT_PP_ON_DELAYS(n)	_MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6675
#define BXT_PP_OFF_DELAYS(n)	_MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
6084 serge 6676
 
6937 serge 6677
#define _PCH_DP_B		0xe4100
6678
#define PCH_DP_B		_MMIO(_PCH_DP_B)
6679
#define _PCH_DPB_AUX_CH_CTL	0xe4110
6680
#define _PCH_DPB_AUX_CH_DATA1	0xe4114
6681
#define _PCH_DPB_AUX_CH_DATA2	0xe4118
6682
#define _PCH_DPB_AUX_CH_DATA3	0xe411c
6683
#define _PCH_DPB_AUX_CH_DATA4	0xe4120
6684
#define _PCH_DPB_AUX_CH_DATA5	0xe4124
2325 Serge 6685
 
6937 serge 6686
#define _PCH_DP_C		0xe4200
6687
#define PCH_DP_C		_MMIO(_PCH_DP_C)
6688
#define _PCH_DPC_AUX_CH_CTL	0xe4210
6689
#define _PCH_DPC_AUX_CH_DATA1	0xe4214
6690
#define _PCH_DPC_AUX_CH_DATA2	0xe4218
6691
#define _PCH_DPC_AUX_CH_DATA3	0xe421c
6692
#define _PCH_DPC_AUX_CH_DATA4	0xe4220
6693
#define _PCH_DPC_AUX_CH_DATA5	0xe4224
2325 Serge 6694
 
6937 serge 6695
#define _PCH_DP_D		0xe4300
6696
#define PCH_DP_D		_MMIO(_PCH_DP_D)
6697
#define _PCH_DPD_AUX_CH_CTL	0xe4310
6698
#define _PCH_DPD_AUX_CH_DATA1	0xe4314
6699
#define _PCH_DPD_AUX_CH_DATA2	0xe4318
6700
#define _PCH_DPD_AUX_CH_DATA3	0xe431c
6701
#define _PCH_DPD_AUX_CH_DATA4	0xe4320
6702
#define _PCH_DPD_AUX_CH_DATA5	0xe4324
2325 Serge 6703
 
6937 serge 6704
#define PCH_DP_AUX_CH_CTL(port)		_MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6705
#define PCH_DP_AUX_CH_DATA(port, i)	_MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6706
 
2325 Serge 6707
/* CPT */
6708
#define  PORT_TRANS_A_SEL_CPT	0
6709
#define  PORT_TRANS_B_SEL_CPT	(1<<29)
6710
#define  PORT_TRANS_C_SEL_CPT	(2<<29)
6711
#define  PORT_TRANS_SEL_MASK	(3<<29)
6712
#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
3031 serge 6713
#define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
6714
#define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
5060 serge 6715
#define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
6716
#define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
2325 Serge 6717
 
6937 serge 6718
#define _TRANS_DP_CTL_A		0xe0300
6719
#define _TRANS_DP_CTL_B		0xe1300
6720
#define _TRANS_DP_CTL_C		0xe2300
6721
#define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
2325 Serge 6722
#define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
6723
#define  TRANS_DP_PORT_SEL_B	(0<<29)
6724
#define  TRANS_DP_PORT_SEL_C	(1<<29)
6725
#define  TRANS_DP_PORT_SEL_D	(2<<29)
6726
#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
6727
#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
6084 serge 6728
#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
2325 Serge 6729
#define  TRANS_DP_AUDIO_ONLY	(1<<26)
6730
#define  TRANS_DP_ENH_FRAMING	(1<<18)
6731
#define  TRANS_DP_8BPC		(0<<9)
6732
#define  TRANS_DP_10BPC		(1<<9)
6733
#define  TRANS_DP_6BPC		(2<<9)
6734
#define  TRANS_DP_12BPC		(3<<9)
6735
#define  TRANS_DP_BPC_MASK	(3<<9)
6736
#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
6737
#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
6738
#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
6739
#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
6740
#define  TRANS_DP_SYNC_MASK	(3<<3)
6741
 
6742
/* SNB eDP training params */
6743
/* SNB A-stepping */
6744
#define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
6745
#define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
6746
#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
6747
#define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
6748
/* SNB B-stepping */
6749
#define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
6750
#define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
6751
#define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
6752
#define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
6753
#define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
6754
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
6755
 
2342 Serge 6756
/* IVB */
6757
#define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
6758
#define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
6759
#define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
6760
#define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
6761
#define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
6762
#define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
4104 Serge 6763
#define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e <<22)
2342 Serge 6764
 
6765
/* legacy values */
6766
#define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
6767
#define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
6768
#define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
6769
#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
6770
#define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
6771
 
6772
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
6773
 
6937 serge 6774
#define  VLV_PMWGICZ				_MMIO(0x1300a4)
5060 serge 6775
 
6937 serge 6776
#define  FORCEWAKE				_MMIO(0xA18C)
6777
#define  FORCEWAKE_VLV				_MMIO(0x1300b0)
6778
#define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
6779
#define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
6780
#define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
6781
#define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
6782
#define  FORCEWAKE_ACK				_MMIO(0x130090)
6783
#define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
5060 serge 6784
#define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
6785
#define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
6786
#define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
6787
 
6937 serge 6788
#define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
5060 serge 6789
#define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
6790
#define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
6791
#define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
6792
#define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
6937 serge 6793
#define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
6794
#define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
6795
#define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
6796
#define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
6797
#define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
6798
#define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
6799
#define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
3243 Serge 6800
#define   FORCEWAKE_KERNEL			0x1
6801
#define   FORCEWAKE_USER			0x2
6937 serge 6802
#define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
6803
#define  ECOBUS					_MMIO(0xa180)
2342 Serge 6804
#define    FORCEWAKE_MT_ENABLE			(1<<5)
6937 serge 6805
#define  VLV_SPAREG2H				_MMIO(0xA194)
2325 Serge 6806
 
6937 serge 6807
#define  GTFIFODBG				_MMIO(0x120000)
4560 Serge 6808
#define    GT_FIFO_SBDROPERR			(1<<6)
6809
#define    GT_FIFO_BLOBDROPERR			(1<<5)
6810
#define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
6811
#define    GT_FIFO_DROPERR			(1<<3)
3031 serge 6812
#define    GT_FIFO_OVFERR			(1<<2)
6813
#define    GT_FIFO_IAWRERR			(1<<1)
6814
#define    GT_FIFO_IARDERR			(1<<0)
6815
 
6937 serge 6816
#define  GTFIFOCTL				_MMIO(0x120008)
4560 Serge 6817
#define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
2325 Serge 6818
#define    GT_FIFO_NUM_RESERVED_ENTRIES		20
6084 serge 6819
#define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
6820
#define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
2325 Serge 6821
 
6937 serge 6822
#define  HSW_IDICR				_MMIO(0x9008)
4104 Serge 6823
#define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
6937 serge 6824
#define  HSW_EDRAM_PRESENT			_MMIO(0x120010)
6084 serge 6825
#define    EDRAM_ENABLED			0x1
4104 Serge 6826
 
6937 serge 6827
#define GEN6_UCGCTL1				_MMIO(0x9400)
5060 serge 6828
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
3031 serge 6829
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
6830
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
6831
 
6937 serge 6832
#define GEN6_UCGCTL2				_MMIO(0x9404)
6084 serge 6833
# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
3031 serge 6834
# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
6835
# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
6836
# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
2342 Serge 6837
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
6838
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
6839
 
6937 serge 6840
#define GEN6_UCGCTL3				_MMIO(0x9408)
5060 serge 6841
 
6937 serge 6842
#define GEN7_UCGCTL4				_MMIO(0x940c)
3031 serge 6843
#define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
6844
 
6937 serge 6845
#define GEN6_RCGCTL1				_MMIO(0x9410)
6846
#define GEN6_RCGCTL2				_MMIO(0x9414)
6847
#define GEN6_RSTCTL				_MMIO(0x9420)
5060 serge 6848
 
6937 serge 6849
#define GEN8_UCGCTL6				_MMIO(0x9430)
6084 serge 6850
#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
5060 serge 6851
#define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
6084 serge 6852
#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
5060 serge 6853
 
6937 serge 6854
#define GEN6_GFXPAUSE				_MMIO(0xA000)
6855
#define GEN6_RPNSWREQ				_MMIO(0xA008)
2325 Serge 6856
#define   GEN6_TURBO_DISABLE			(1<<31)
6857
#define   GEN6_FREQUENCY(x)			((x)<<25)
3746 Serge 6858
#define   HSW_FREQUENCY(x)			((x)<<24)
6084 serge 6859
#define   GEN9_FREQUENCY(x)			((x)<<23)
2325 Serge 6860
#define   GEN6_OFFSET(x)			((x)<<19)
6861
#define   GEN6_AGGRESSIVE_TURBO			(0<<15)
6937 serge 6862
#define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
6863
#define GEN6_RC_CONTROL				_MMIO(0xA090)
2325 Serge 6864
#define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
6865
#define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
6866
#define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
6867
#define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
6868
#define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
4560 Serge 6869
#define   VLV_RC_CTL_CTX_RST_PARALLEL		(1<<24)
4104 Serge 6870
#define   GEN7_RC_CTL_TO_MODE			(1<<28)
2325 Serge 6871
#define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
6872
#define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
6937 serge 6873
#define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
6874
#define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
6875
#define GEN6_RPSTAT1				_MMIO(0xA01C)
2325 Serge 6876
#define   GEN6_CAGF_SHIFT			8
3480 Serge 6877
#define   HSW_CAGF_SHIFT			7
6084 serge 6878
#define   GEN9_CAGF_SHIFT			23
2325 Serge 6879
#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
3480 Serge 6880
#define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
6084 serge 6881
#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
6937 serge 6882
#define GEN6_RP_CONTROL				_MMIO(0xA024)
2325 Serge 6883
#define   GEN6_RP_MEDIA_TURBO			(1<<11)
2342 Serge 6884
#define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
6885
#define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
6886
#define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
6887
#define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
6888
#define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
2325 Serge 6889
#define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
6890
#define   GEN6_RP_ENABLE			(1<<7)
6891
#define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
6892
#define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
6893
#define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
4560 Serge 6894
#define   GEN6_RP_DOWN_IDLE_AVG			(0x2<<0)
2325 Serge 6895
#define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
6937 serge 6896
#define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
6897
#define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
6898
#define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
2325 Serge 6899
#define   GEN6_CURICONT_MASK			0xffffff
6937 serge 6900
#define GEN6_RP_CUR_UP				_MMIO(0xA054)
2325 Serge 6901
#define   GEN6_CURBSYTAVG_MASK			0xffffff
6937 serge 6902
#define GEN6_RP_PREV_UP				_MMIO(0xA058)
6903
#define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
2325 Serge 6904
#define   GEN6_CURIAVG_MASK			0xffffff
6937 serge 6905
#define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
6906
#define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
6907
#define GEN6_RP_UP_EI				_MMIO(0xA068)
6908
#define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
6909
#define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
6910
#define GEN6_RPDEUHWTC				_MMIO(0xA080)
6911
#define GEN6_RPDEUC				_MMIO(0xA084)
6912
#define GEN6_RPDEUCSW				_MMIO(0xA088)
6913
#define GEN6_RC_STATE				_MMIO(0xA094)
6914
#define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
6915
#define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
6916
#define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
6917
#define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
6918
#define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
6919
#define GEN6_RC_SLEEP				_MMIO(0xA0B0)
6920
#define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
6921
#define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
6922
#define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
6923
#define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
6924
#define VLV_RCEDATA				_MMIO(0xA0BC)
6925
#define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
6926
#define GEN6_PMINTRMSK				_MMIO(0xA168)
5060 serge 6927
#define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
6937 serge 6928
#define VLV_PWRDWNUPCTL				_MMIO(0xA294)
6929
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
6930
#define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
6931
#define GEN9_PG_ENABLE				_MMIO(0xA210)
6084 serge 6932
#define GEN9_RENDER_PG_ENABLE			(1<<0)
6933
#define GEN9_MEDIA_PG_ENABLE			(1<<1)
2325 Serge 6934
 
6937 serge 6935
#define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
6084 serge 6936
#define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
6937
#define  PIXEL_OVERLAP_CNT_SHIFT		30
6938
 
6937 serge 6939
#define GEN6_PMISR				_MMIO(0x44020)
6940
#define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
6941
#define GEN6_PMIIR				_MMIO(0x44028)
6942
#define GEN6_PMIER				_MMIO(0x4402C)
2325 Serge 6943
#define  GEN6_PM_MBOX_EVENT			(1<<25)
6944
#define  GEN6_PM_THERMAL_EVENT			(1<<24)
6945
#define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
6946
#define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
6947
#define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
6948
#define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
6949
#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
4104 Serge 6950
#define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
2325 Serge 6951
						 GEN6_PM_RP_DOWN_THRESHOLD | \
6952
						 GEN6_PM_RP_DOWN_TIMEOUT)
6953
 
6937 serge 6954
#define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
5060 serge 6955
#define GEN7_GT_SCRATCH_REG_NUM			8
6956
 
6937 serge 6957
#define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
5060 serge 6958
#define VLV_GFX_CLK_STATUS_BIT			(1<<3)
6959
#define VLV_GFX_CLK_FORCE_ON_BIT		(1<<2)
6960
 
6937 serge 6961
#define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
6962
#define VLV_COUNTER_CONTROL			_MMIO(0x138104)
4560 Serge 6963
#define   VLV_COUNT_RANGE_HIGH			(1<<15)
5060 serge 6964
#define   VLV_MEDIA_RC0_COUNT_EN		(1<<5)
6965
#define   VLV_RENDER_RC0_COUNT_EN		(1<<4)
4560 Serge 6966
#define   VLV_MEDIA_RC6_COUNT_EN		(1<<1)
6967
#define   VLV_RENDER_RC6_COUNT_EN		(1<<0)
6937 serge 6968
#define GEN6_GT_GFX_RC6				_MMIO(0x138108)
6969
#define VLV_GT_RENDER_RC6			_MMIO(0x138108)
6970
#define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
5060 serge 6971
 
6937 serge 6972
#define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
6973
#define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
6974
#define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
6975
#define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
3031 serge 6976
 
6937 serge 6977
#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
2325 Serge 6978
#define   GEN6_PCODE_READY			(1<<31)
6084 serge 6979
#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
6980
#define	  GEN6_PCODE_READ_RC6VIDS		0x5
6981
#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
6982
#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
6983
#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
6984
#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
6985
#define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
6986
#define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
6987
#define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
6988
#define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
6989
#define   SKL_PCODE_CDCLK_CONTROL		0x7
6990
#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
6991
#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
2325 Serge 6992
#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
6993
#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
6084 serge 6994
#define   GEN6_READ_OC_PARAMS			0xc
4560 Serge 6995
#define   GEN6_PCODE_READ_D_COMP		0x10
6996
#define   GEN6_PCODE_WRITE_D_COMP		0x11
6084 serge 6997
#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
4560 Serge 6998
#define   DISPLAY_IPS_CONTROL			0x19
5354 serge 6999
#define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
6937 serge 7000
#define GEN6_PCODE_DATA				_MMIO(0x138128)
2325 Serge 7001
#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
3746 Serge 7002
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
6937 serge 7003
#define GEN6_PCODE_DATA1			_MMIO(0x13812C)
2325 Serge 7004
 
6937 serge 7005
#define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
2342 Serge 7006
#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
7007
#define   GEN6_RCn_MASK			7
7008
#define   GEN6_RC0			0
7009
#define   GEN6_RC3			2
7010
#define   GEN6_RC6			3
7011
#define   GEN6_RC7			4
7012
 
6937 serge 7013
#define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
6084 serge 7014
#define   GEN8_LSLICESTAT_MASK		0x7
7015
 
6937 serge 7016
#define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
7017
#define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
6084 serge 7018
#define   CHV_SS_PG_ENABLE		(1<<1)
7019
#define   CHV_EU08_PG_ENABLE		(1<<9)
7020
#define   CHV_EU19_PG_ENABLE		(1<<17)
7021
#define   CHV_EU210_PG_ENABLE		(1<<25)
7022
 
6937 serge 7023
#define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
7024
#define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
6084 serge 7025
#define   CHV_EU311_PG_ENABLE		(1<<1)
7026
 
6937 serge 7027
#define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice)*0x4)
6084 serge 7028
#define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
7029
#define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
7030
 
6937 serge 7031
#define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice)*0x8)
7032
#define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice)*0x8)
6084 serge 7033
#define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
7034
#define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
7035
#define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
7036
#define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
7037
#define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
7038
#define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
7039
#define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
7040
#define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
7041
 
6937 serge 7042
#define GEN7_MISCCPCTL				_MMIO(0x9424)
6084 serge 7043
#define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
7044
#define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
7045
#define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
7046
#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
3031 serge 7047
 
6937 serge 7048
#define GEN8_GARBCNTL                   _MMIO(0xB004)
6084 serge 7049
#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
7050
 
3031 serge 7051
/* IVYBRIDGE DPF */
6937 serge 7052
#define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3031 serge 7053
#define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
7054
#define   GEN7_PARITY_ERROR_VALID	(1<<13)
7055
#define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
7056
#define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
7057
#define GEN7_PARITY_ERROR_ROW(reg) \
7058
		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
7059
#define GEN7_PARITY_ERROR_BANK(reg) \
7060
		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
7061
#define GEN7_PARITY_ERROR_SUBBANK(reg) \
7062
		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
7063
#define   GEN7_L3CDERRST1_ENABLE	(1<<7)
7064
 
6937 serge 7065
#define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
3031 serge 7066
#define GEN7_L3LOG_SIZE			0x80
7067
 
6937 serge 7068
#define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
7069
#define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
3243 Serge 7070
#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
4560 Serge 7071
#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
6084 serge 7072
#define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
3243 Serge 7073
#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
7074
 
6937 serge 7075
#define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
5354 serge 7076
#define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
6084 serge 7077
#define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
5354 serge 7078
 
6937 serge 7079
#define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
5060 serge 7080
#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
7081
#define   STALL_DOP_GATING_DISABLE		(1<<5)
7082
 
6937 serge 7083
#define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
7084
#define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
3243 Serge 7085
#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
7086
 
6937 serge 7087
#define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
4104 Serge 7088
#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
7089
 
6937 serge 7090
#define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
6084 serge 7091
#define   GEN8_ST_PO_DISABLE		(1<<13)
7092
 
6937 serge 7093
#define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
6084 serge 7094
#define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
4560 Serge 7095
#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
6084 serge 7096
#define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
4560 Serge 7097
#define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
7098
 
6937 serge 7099
#define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
6084 serge 7100
#define   GEN9_ENABLE_YV12_BUGFIX	(1<<4)
7101
 
5354 serge 7102
/* Audio */
6937 serge 7103
#define G4X_AUD_VID_DID			_MMIO(dev_priv->info.display_mmio_offset + 0x62020)
6084 serge 7104
#define   INTEL_AUDIO_DEVCL		0x808629FB
7105
#define   INTEL_AUDIO_DEVBLC		0x80862801
7106
#define   INTEL_AUDIO_DEVCTG		0x80862802
2342 Serge 7107
 
6937 serge 7108
#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
6084 serge 7109
#define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
7110
#define   G4X_ELDV_DEVCTG		(1 << 14)
5354 serge 7111
#define   G4X_ELD_ADDR_MASK		(0xf << 5)
6084 serge 7112
#define   G4X_ELD_ACK			(1 << 4)
6937 serge 7113
#define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
2342 Serge 7114
 
5354 serge 7115
#define _IBX_HDMIW_HDMIEDID_A		0xE2050
7116
#define _IBX_HDMIW_HDMIEDID_B		0xE2150
6937 serge 7117
#define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
5354 serge 7118
					_IBX_HDMIW_HDMIEDID_B)
7119
#define _IBX_AUD_CNTL_ST_A		0xE20B4
7120
#define _IBX_AUD_CNTL_ST_B		0xE21B4
6937 serge 7121
#define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
5354 serge 7122
					_IBX_AUD_CNTL_ST_B)
7123
#define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
7124
#define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
6084 serge 7125
#define   IBX_ELD_ACK			(1 << 4)
6937 serge 7126
#define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
5354 serge 7127
#define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
7128
#define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
2342 Serge 7129
 
5354 serge 7130
#define _CPT_HDMIW_HDMIEDID_A		0xE5050
7131
#define _CPT_HDMIW_HDMIEDID_B		0xE5150
6937 serge 7132
#define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
5354 serge 7133
#define _CPT_AUD_CNTL_ST_A		0xE50B4
7134
#define _CPT_AUD_CNTL_ST_B		0xE51B4
6937 serge 7135
#define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
7136
#define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
2342 Serge 7137
 
5354 serge 7138
#define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
7139
#define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
6937 serge 7140
#define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
5354 serge 7141
#define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
7142
#define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
6937 serge 7143
#define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
7144
#define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
4560 Serge 7145
 
2342 Serge 7146
/* These are the 4 32-bit write offset registers for each stream
7147
 * output buffer.  It determines the offset from the
7148
 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7149
 */
6937 serge 7150
#define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
2342 Serge 7151
 
5354 serge 7152
#define _IBX_AUD_CONFIG_A		0xe2000
7153
#define _IBX_AUD_CONFIG_B		0xe2100
6937 serge 7154
#define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
5354 serge 7155
#define _CPT_AUD_CONFIG_A		0xe5000
7156
#define _CPT_AUD_CONFIG_B		0xe5100
6937 serge 7157
#define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
5354 serge 7158
#define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
7159
#define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
6937 serge 7160
#define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
4560 Serge 7161
 
3031 serge 7162
#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
7163
#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
7164
#define   AUD_CONFIG_UPPER_N_SHIFT		20
5354 serge 7165
#define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
3031 serge 7166
#define   AUD_CONFIG_LOWER_N_SHIFT		4
5354 serge 7167
#define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
3031 serge 7168
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
4560 Serge 7169
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
7170
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
7171
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
7172
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
7173
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
7174
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
7175
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
7176
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
7177
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
7178
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
7179
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
3031 serge 7180
#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
7181
 
7182
/* HSW Audio */
5354 serge 7183
#define _HSW_AUD_CONFIG_A		0x65000
7184
#define _HSW_AUD_CONFIG_B		0x65100
6937 serge 7185
#define HSW_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
3031 serge 7186
 
5354 serge 7187
#define _HSW_AUD_MISC_CTRL_A		0x65010
7188
#define _HSW_AUD_MISC_CTRL_B		0x65110
6937 serge 7189
#define HSW_AUD_MISC_CTRL(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
3031 serge 7190
 
5354 serge 7191
#define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
7192
#define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
6937 serge 7193
#define HSW_AUD_DIP_ELD_CTRL(pipe)	_MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
3031 serge 7194
 
7195
/* Audio Digital Converter */
5354 serge 7196
#define _HSW_AUD_DIG_CNVT_1		0x65080
7197
#define _HSW_AUD_DIG_CNVT_2		0x65180
6937 serge 7198
#define AUD_DIG_CNVT(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
6084 serge 7199
#define DIP_PORT_SEL_MASK		0x3
3031 serge 7200
 
5354 serge 7201
#define _HSW_AUD_EDID_DATA_A		0x65050
7202
#define _HSW_AUD_EDID_DATA_B		0x65150
6937 serge 7203
#define HSW_AUD_EDID_DATA(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
3031 serge 7204
 
6937 serge 7205
#define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
7206
#define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
5354 serge 7207
#define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
7208
#define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
7209
#define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
7210
#define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
3031 serge 7211
 
6937 serge 7212
#define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
6084 serge 7213
#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
7214
 
3031 serge 7215
/* HSW Power Wells */
6937 serge 7216
#define HSW_PWR_WELL_BIOS			_MMIO(0x45400) /* CTL1 */
7217
#define HSW_PWR_WELL_DRIVER			_MMIO(0x45404) /* CTL2 */
7218
#define HSW_PWR_WELL_KVMR			_MMIO(0x45408) /* CTL3 */
7219
#define HSW_PWR_WELL_DEBUG			_MMIO(0x4540C) /* CTL4 */
4104 Serge 7220
#define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)
7221
#define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)
6937 serge 7222
#define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
3031 serge 7223
#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
7224
#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
6084 serge 7225
#define   HSW_PWR_WELL_FORCE_ON			(1<<19)
6937 serge 7226
#define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
3031 serge 7227
 
6084 serge 7228
/* SKL Fuse Status */
6937 serge 7229
#define SKL_FUSE_STATUS				_MMIO(0x42000)
6084 serge 7230
#define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
7231
#define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
7232
#define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
7233
#define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)
7234
 
3031 serge 7235
/* Per-pipe DDI Function Control */
6937 serge 7236
#define _TRANS_DDI_FUNC_CTL_A		0x60400
7237
#define _TRANS_DDI_FUNC_CTL_B		0x61400
7238
#define _TRANS_DDI_FUNC_CTL_C		0x62400
7239
#define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
7240
#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
5060 serge 7241
 
3243 Serge 7242
#define  TRANS_DDI_FUNC_ENABLE		(1<<31)
3031 serge 7243
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3243 Serge 7244
#define  TRANS_DDI_PORT_MASK		(7<<28)
5060 serge 7245
#define  TRANS_DDI_PORT_SHIFT		28
3243 Serge 7246
#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
7247
#define  TRANS_DDI_PORT_NONE		(0<<28)
7248
#define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
7249
#define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
7250
#define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
7251
#define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
7252
#define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
7253
#define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
7254
#define  TRANS_DDI_BPC_MASK		(7<<20)
7255
#define  TRANS_DDI_BPC_8		(0<<20)
7256
#define  TRANS_DDI_BPC_10		(1<<20)
7257
#define  TRANS_DDI_BPC_6		(2<<20)
7258
#define  TRANS_DDI_BPC_12		(3<<20)
7259
#define  TRANS_DDI_PVSYNC		(1<<17)
7260
#define  TRANS_DDI_PHSYNC		(1<<16)
7261
#define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
7262
#define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
7263
#define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
7264
#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
7265
#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
5060 serge 7266
#define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1<<8)
3243 Serge 7267
#define  TRANS_DDI_BFI_ENABLE		(1<<4)
3031 serge 7268
 
7269
/* DisplayPort Transport Control */
6937 serge 7270
#define _DP_TP_CTL_A			0x64040
7271
#define _DP_TP_CTL_B			0x64140
7272
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
6084 serge 7273
#define  DP_TP_CTL_ENABLE			(1<<31)
7274
#define  DP_TP_CTL_MODE_SST			(0<<27)
7275
#define  DP_TP_CTL_MODE_MST			(1<<27)
5060 serge 7276
#define  DP_TP_CTL_FORCE_ACT			(1<<25)
3031 serge 7277
#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
6084 serge 7278
#define  DP_TP_CTL_FDI_AUTOTRAIN		(1<<15)
3031 serge 7279
#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
7280
#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
7281
#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
3243 Serge 7282
#define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
7283
#define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
6084 serge 7284
#define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3<<8)
3243 Serge 7285
#define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
3031 serge 7286
 
7287
/* DisplayPort Transport Status */
6937 serge 7288
#define _DP_TP_STATUS_A			0x64044
7289
#define _DP_TP_STATUS_B			0x64144
7290
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
6084 serge 7291
#define  DP_TP_STATUS_IDLE_DONE			(1<<25)
5060 serge 7292
#define  DP_TP_STATUS_ACT_SENT			(1<<24)
7293
#define  DP_TP_STATUS_MODE_STATUS_MST		(1<<23)
6084 serge 7294
#define  DP_TP_STATUS_AUTOTRAIN_DONE		(1<<12)
5060 serge 7295
#define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
7296
#define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
7297
#define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
3031 serge 7298
 
7299
/* DDI Buffer Control */
6937 serge 7300
#define _DDI_BUF_CTL_A				0x64000
7301
#define _DDI_BUF_CTL_B				0x64100
7302
#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
6084 serge 7303
#define  DDI_BUF_CTL_ENABLE			(1<<31)
5354 serge 7304
#define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
6084 serge 7305
#define  DDI_BUF_EMP_MASK			(0xf<<24)
3480 Serge 7306
#define  DDI_BUF_PORT_REVERSAL			(1<<16)
6084 serge 7307
#define  DDI_BUF_IS_IDLE			(1<<7)
3243 Serge 7308
#define  DDI_A_4_LANES				(1<<4)
4104 Serge 7309
#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
6084 serge 7310
#define  DDI_PORT_WIDTH_MASK			(7 << 1)
7311
#define  DDI_PORT_WIDTH_SHIFT			1
3031 serge 7312
#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
7313
 
7314
/* DDI Buffer Translations */
6937 serge 7315
#define _DDI_BUF_TRANS_A		0x64E00
7316
#define _DDI_BUF_TRANS_B		0x64E60
7317
#define DDI_BUF_TRANS_LO(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
7318
#define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
3031 serge 7319
 
7320
/* Sideband Interface (SBI) is programmed indirectly, via
7321
 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7322
 * which contains the payload */
6937 serge 7323
#define SBI_ADDR			_MMIO(0xC6000)
7324
#define SBI_DATA			_MMIO(0xC6004)
7325
#define SBI_CTL_STAT			_MMIO(0xC6008)
3243 Serge 7326
#define  SBI_CTL_DEST_ICLK		(0x0<<16)
7327
#define  SBI_CTL_DEST_MPHY		(0x1<<16)
7328
#define  SBI_CTL_OP_IORD		(0x2<<8)
7329
#define  SBI_CTL_OP_IOWR		(0x3<<8)
3031 serge 7330
#define  SBI_CTL_OP_CRRD		(0x6<<8)
7331
#define  SBI_CTL_OP_CRWR		(0x7<<8)
7332
#define  SBI_RESPONSE_FAIL		(0x1<<1)
6084 serge 7333
#define  SBI_RESPONSE_SUCCESS		(0x0<<1)
7334
#define  SBI_BUSY			(0x1<<0)
7335
#define  SBI_READY			(0x0<<0)
3031 serge 7336
 
7337
/* SBI offsets */
6937 serge 7338
#define  SBI_SSCDIVINTPHASE			0x0200
6084 serge 7339
#define  SBI_SSCDIVINTPHASE6			0x0600
3031 serge 7340
#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
7341
#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
7342
#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
7343
#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
6084 serge 7344
#define   SBI_SSCDIVINTPHASE_DIR(x)		((x)<<15)
3031 serge 7345
#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
6937 serge 7346
#define  SBI_SSCDITHPHASE			0x0204
6084 serge 7347
#define  SBI_SSCCTL				0x020c
3031 serge 7348
#define  SBI_SSCCTL6				0x060C
3243 Serge 7349
#define   SBI_SSCCTL_PATHALT			(1<<3)
6084 serge 7350
#define   SBI_SSCCTL_DISABLE			(1<<0)
3031 serge 7351
#define  SBI_SSCAUXDIV6				0x0610
7352
#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
6084 serge 7353
#define  SBI_DBUFF0				0x2a00
4104 Serge 7354
#define  SBI_GEN0				0x1f00
7355
#define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)
3031 serge 7356
 
7357
/* LPT PIXCLK_GATE */
6937 serge 7358
#define PIXCLK_GATE			_MMIO(0xC6020)
3031 serge 7359
#define  PIXCLK_GATE_UNGATE		(1<<0)
7360
#define  PIXCLK_GATE_GATE		(0<<0)
7361
 
7362
/* SPLL */
6937 serge 7363
#define SPLL_CTL			_MMIO(0x46020)
3031 serge 7364
#define  SPLL_PLL_ENABLE		(1<<31)
3243 Serge 7365
#define  SPLL_PLL_SSC			(1<<28)
7366
#define  SPLL_PLL_NON_SSC		(2<<28)
5060 serge 7367
#define  SPLL_PLL_LCPLL			(3<<28)
7368
#define  SPLL_PLL_REF_MASK		(3<<28)
6084 serge 7369
#define  SPLL_PLL_FREQ_810MHz		(0<<26)
7370
#define  SPLL_PLL_FREQ_1350MHz		(1<<26)
5060 serge 7371
#define  SPLL_PLL_FREQ_2700MHz		(2<<26)
7372
#define  SPLL_PLL_FREQ_MASK		(3<<26)
3031 serge 7373
 
7374
/* WRPLL */
6937 serge 7375
#define _WRPLL_CTL1			0x46040
7376
#define _WRPLL_CTL2			0x46060
7377
#define WRPLL_CTL(pll)			_MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
6084 serge 7378
#define  WRPLL_PLL_ENABLE		(1<<31)
5060 serge 7379
#define  WRPLL_PLL_SSC			(1<<28)
7380
#define  WRPLL_PLL_NON_SSC		(2<<28)
7381
#define  WRPLL_PLL_LCPLL		(3<<28)
7382
#define  WRPLL_PLL_REF_MASK		(3<<28)
3031 serge 7383
/* WRPLL divider programming */
6084 serge 7384
#define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)
5060 serge 7385
#define  WRPLL_DIVIDER_REF_MASK		(0xff)
6084 serge 7386
#define  WRPLL_DIVIDER_POST(x)		((x)<<8)
5060 serge 7387
#define  WRPLL_DIVIDER_POST_MASK	(0x3f<<8)
7388
#define  WRPLL_DIVIDER_POST_SHIFT	8
6084 serge 7389
#define  WRPLL_DIVIDER_FEEDBACK(x)	((x)<<16)
5060 serge 7390
#define  WRPLL_DIVIDER_FB_SHIFT		16
7391
#define  WRPLL_DIVIDER_FB_MASK		(0xff<<16)
3031 serge 7392
 
7393
/* Port clock selection */
6937 serge 7394
#define _PORT_CLK_SEL_A			0x46100
7395
#define _PORT_CLK_SEL_B			0x46104
7396
#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
3031 serge 7397
#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
7398
#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
7399
#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
6084 serge 7400
#define  PORT_CLK_SEL_SPLL		(3<<29)
5060 serge 7401
#define  PORT_CLK_SEL_WRPLL(pll)	(((pll)+4)<<29)
3031 serge 7402
#define  PORT_CLK_SEL_WRPLL1		(4<<29)
7403
#define  PORT_CLK_SEL_WRPLL2		(5<<29)
3243 Serge 7404
#define  PORT_CLK_SEL_NONE		(7<<29)
5060 serge 7405
#define  PORT_CLK_SEL_MASK		(7<<29)
3031 serge 7406
 
3243 Serge 7407
/* Transcoder clock selection */
6937 serge 7408
#define _TRANS_CLK_SEL_A		0x46140
7409
#define _TRANS_CLK_SEL_B		0x46144
7410
#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
3243 Serge 7411
/* For each transcoder, we need to select the corresponding port clock */
7412
#define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
6084 serge 7413
#define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
3031 serge 7414
 
6937 serge 7415
#define CDCLK_FREQ			_MMIO(0x46200)
6660 serge 7416
 
6937 serge 7417
#define _TRANSA_MSA_MISC		0x60410
7418
#define _TRANSB_MSA_MISC		0x61410
7419
#define _TRANSC_MSA_MISC		0x62410
7420
#define _TRANS_EDP_MSA_MISC		0x6f410
7421
#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
5060 serge 7422
 
3243 Serge 7423
#define  TRANS_MSA_SYNC_CLK		(1<<0)
7424
#define  TRANS_MSA_6_BPC		(0<<5)
7425
#define  TRANS_MSA_8_BPC		(1<<5)
7426
#define  TRANS_MSA_10_BPC		(2<<5)
7427
#define  TRANS_MSA_12_BPC		(3<<5)
7428
#define  TRANS_MSA_16_BPC		(4<<5)
7429
 
3031 serge 7430
/* LCPLL Control */
6937 serge 7431
#define LCPLL_CTL			_MMIO(0x130040)
3031 serge 7432
#define  LCPLL_PLL_DISABLE		(1<<31)
7433
#define  LCPLL_PLL_LOCK			(1<<30)
3243 Serge 7434
#define  LCPLL_CLK_FREQ_MASK		(3<<26)
7435
#define  LCPLL_CLK_FREQ_450		(0<<26)
4560 Serge 7436
#define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
7437
#define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
7438
#define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
6084 serge 7439
#define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
7440
#define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
3031 serge 7441
#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
4104 Serge 7442
#define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
3243 Serge 7443
#define  LCPLL_CD_SOURCE_FCLK		(1<<21)
4104 Serge 7444
#define  LCPLL_CD_SOURCE_FCLK_DONE	(1<<19)
3031 serge 7445
 
5354 serge 7446
/*
7447
 * SKL Clocks
7448
 */
7449
 
7450
/* CDCLK_CTL */
6937 serge 7451
#define CDCLK_CTL			_MMIO(0x46000)
5354 serge 7452
#define  CDCLK_FREQ_SEL_MASK		(3<<26)
7453
#define  CDCLK_FREQ_450_432		(0<<26)
7454
#define  CDCLK_FREQ_540			(1<<26)
7455
#define  CDCLK_FREQ_337_308		(2<<26)
7456
#define  CDCLK_FREQ_675_617		(3<<26)
7457
#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
7458
 
6084 serge 7459
#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
7460
#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
7461
#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
7462
#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
7463
#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
7464
#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
7465
 
5354 serge 7466
/* LCPLL_CTL */
6937 serge 7467
#define LCPLL1_CTL		_MMIO(0x46010)
7468
#define LCPLL2_CTL		_MMIO(0x46014)
5354 serge 7469
#define  LCPLL_PLL_ENABLE	(1<<31)
7470
 
7471
/* DPLL control1 */
6937 serge 7472
#define DPLL_CTRL1		_MMIO(0x6C058)
5354 serge 7473
#define  DPLL_CTRL1_HDMI_MODE(id)		(1<<((id)*6+5))
7474
#define  DPLL_CTRL1_SSC(id)			(1<<((id)*6+4))
6084 serge 7475
#define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7<<((id)*6+1))
7476
#define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id)*6+1)
7477
#define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate)<<((id)*6+1))
5354 serge 7478
#define  DPLL_CTRL1_OVERRIDE(id)		(1<<((id)*6))
6084 serge 7479
#define  DPLL_CTRL1_LINK_RATE_2700		0
7480
#define  DPLL_CTRL1_LINK_RATE_1350		1
7481
#define  DPLL_CTRL1_LINK_RATE_810		2
7482
#define  DPLL_CTRL1_LINK_RATE_1620		3
7483
#define  DPLL_CTRL1_LINK_RATE_1080		4
7484
#define  DPLL_CTRL1_LINK_RATE_2160		5
5354 serge 7485
 
7486
/* DPLL control2 */
6937 serge 7487
#define DPLL_CTRL2				_MMIO(0x6C05C)
6084 serge 7488
#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
5354 serge 7489
#define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
7490
#define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
6084 serge 7491
#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk)<<((port)*3+1))
5354 serge 7492
#define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
7493
 
7494
/* DPLL Status */
6937 serge 7495
#define DPLL_STATUS	_MMIO(0x6C060)
5354 serge 7496
#define  DPLL_LOCK(id) (1<<((id)*8))
7497
 
7498
/* DPLL cfg */
6937 serge 7499
#define _DPLL1_CFGCR1	0x6C040
7500
#define _DPLL2_CFGCR1	0x6C048
7501
#define _DPLL3_CFGCR1	0x6C050
5354 serge 7502
#define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
7503
#define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
6084 serge 7504
#define  DPLL_CFGCR1_DCO_FRACTION(x)	((x)<<9)
5354 serge 7505
#define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
7506
 
6937 serge 7507
#define _DPLL1_CFGCR2	0x6C044
7508
#define _DPLL2_CFGCR2	0x6C04C
7509
#define _DPLL3_CFGCR2	0x6C054
5354 serge 7510
#define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
6084 serge 7511
#define  DPLL_CFGCR2_QDIV_RATIO(x)	((x)<<8)
7512
#define  DPLL_CFGCR2_QDIV_MODE(x)	((x)<<7)
5354 serge 7513
#define  DPLL_CFGCR2_KDIV_MASK		(3<<5)
6084 serge 7514
#define  DPLL_CFGCR2_KDIV(x)		((x)<<5)
5354 serge 7515
#define  DPLL_CFGCR2_KDIV_5 (0<<5)
7516
#define  DPLL_CFGCR2_KDIV_2 (1<<5)
7517
#define  DPLL_CFGCR2_KDIV_3 (2<<5)
7518
#define  DPLL_CFGCR2_KDIV_1 (3<<5)
7519
#define  DPLL_CFGCR2_PDIV_MASK		(7<<2)
6084 serge 7520
#define  DPLL_CFGCR2_PDIV(x)		((x)<<2)
5354 serge 7521
#define  DPLL_CFGCR2_PDIV_1 (0<<2)
7522
#define  DPLL_CFGCR2_PDIV_2 (1<<2)
7523
#define  DPLL_CFGCR2_PDIV_3 (2<<2)
7524
#define  DPLL_CFGCR2_PDIV_7 (4<<2)
7525
#define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
7526
 
6937 serge 7527
#define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7528
#define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
5354 serge 7529
 
6084 serge 7530
/* BXT display engine PLL */
6937 serge 7531
#define BXT_DE_PLL_CTL			_MMIO(0x6d000)
6084 serge 7532
#define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
7533
#define   BXT_DE_PLL_RATIO_MASK		0xff
7534
 
6937 serge 7535
#define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
6084 serge 7536
#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
7537
#define   BXT_DE_PLL_LOCK		(1 << 30)
7538
 
7539
/* GEN9 DC */
6937 serge 7540
#define DC_STATE_EN			_MMIO(0x45504)
7541
#define  DC_STATE_DISABLE		0
6084 serge 7542
#define  DC_STATE_EN_UPTO_DC5		(1<<0)
7543
#define  DC_STATE_EN_DC9		(1<<3)
7544
#define  DC_STATE_EN_UPTO_DC6		(2<<0)
7545
#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
7546
 
6937 serge 7547
#define  DC_STATE_DEBUG                  _MMIO(0x45520)
6084 serge 7548
#define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1<<1)
7549
 
5060 serge 7550
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7551
 * since on HSW we can't write to it using I915_WRITE. */
6937 serge 7552
#define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7553
#define D_COMP_BDW			_MMIO(0x138144)
4104 Serge 7554
#define  D_COMP_RCOMP_IN_PROGRESS	(1<<9)
7555
#define  D_COMP_COMP_FORCE		(1<<8)
7556
#define  D_COMP_COMP_DISABLE		(1<<0)
7557
 
3031 serge 7558
/* Pipe WM_LINETIME - watermark line time */
6937 serge 7559
#define _PIPE_WM_LINETIME_A		0x45270
7560
#define _PIPE_WM_LINETIME_B		0x45274
7561
#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
6084 serge 7562
#define   PIPE_WM_LINETIME_MASK			(0x1ff)
7563
#define   PIPE_WM_LINETIME_TIME(x)		((x))
3031 serge 7564
#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
6084 serge 7565
#define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
3031 serge 7566
 
7567
/* SFUSE_STRAP */
6937 serge 7568
#define SFUSE_STRAP			_MMIO(0xc2014)
5060 serge 7569
#define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
7570
#define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
6937 serge 7571
#define  SFUSE_STRAP_CRT_DISABLED	(1<<6)
3031 serge 7572
#define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
7573
#define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
7574
#define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
7575
 
6937 serge 7576
#define WM_MISC				_MMIO(0x45260)
4104 Serge 7577
#define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
7578
 
6937 serge 7579
#define WM_DBG				_MMIO(0x45280)
3031 serge 7580
#define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
7581
#define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
7582
#define  WM_DBG_DISALLOW_SPRITE		(1<<2)
7583
 
3480 Serge 7584
/* pipe CSC */
7585
#define _PIPE_A_CSC_COEFF_RY_GY	0x49010
7586
#define _PIPE_A_CSC_COEFF_BY	0x49014
7587
#define _PIPE_A_CSC_COEFF_RU_GU	0x49018
7588
#define _PIPE_A_CSC_COEFF_BU	0x4901c
7589
#define _PIPE_A_CSC_COEFF_RV_GV	0x49020
7590
#define _PIPE_A_CSC_COEFF_BV	0x49024
7591
#define _PIPE_A_CSC_MODE	0x49028
4104 Serge 7592
#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
7593
#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
7594
#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
3480 Serge 7595
#define _PIPE_A_CSC_PREOFF_HI	0x49030
7596
#define _PIPE_A_CSC_PREOFF_ME	0x49034
7597
#define _PIPE_A_CSC_PREOFF_LO	0x49038
7598
#define _PIPE_A_CSC_POSTOFF_HI	0x49040
7599
#define _PIPE_A_CSC_POSTOFF_ME	0x49044
7600
#define _PIPE_A_CSC_POSTOFF_LO	0x49048
7601
 
7602
#define _PIPE_B_CSC_COEFF_RY_GY	0x49110
7603
#define _PIPE_B_CSC_COEFF_BY	0x49114
7604
#define _PIPE_B_CSC_COEFF_RU_GU	0x49118
7605
#define _PIPE_B_CSC_COEFF_BU	0x4911c
7606
#define _PIPE_B_CSC_COEFF_RV_GV	0x49120
7607
#define _PIPE_B_CSC_COEFF_BV	0x49124
7608
#define _PIPE_B_CSC_MODE	0x49128
7609
#define _PIPE_B_CSC_PREOFF_HI	0x49130
7610
#define _PIPE_B_CSC_PREOFF_ME	0x49134
7611
#define _PIPE_B_CSC_PREOFF_LO	0x49138
7612
#define _PIPE_B_CSC_POSTOFF_HI	0x49140
7613
#define _PIPE_B_CSC_POSTOFF_ME	0x49144
7614
#define _PIPE_B_CSC_POSTOFF_LO	0x49148
7615
 
6937 serge 7616
#define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7617
#define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7618
#define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7619
#define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7620
#define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7621
#define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7622
#define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7623
#define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7624
#define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7625
#define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7626
#define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7627
#define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7628
#define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
3480 Serge 7629
 
6084 serge 7630
/* MIPI DSI registers */
4560 Serge 7631
 
6084 serge 7632
#define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
6937 serge 7633
#define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
6084 serge 7634
 
7635
/* BXT MIPI clock controls */
7636
#define BXT_MAX_VAR_OUTPUT_KHZ			39500
7637
 
6937 serge 7638
#define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
6084 serge 7639
#define  BXT_MIPI1_DIV_SHIFT			26
7640
#define  BXT_MIPI2_DIV_SHIFT			10
7641
#define  BXT_MIPI_DIV_SHIFT(port)		\
7642
			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7643
					BXT_MIPI2_DIV_SHIFT)
7644
/* Var clock divider to generate TX source. Result must be < 39.5 M */
7645
#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK		(0x3F << 26)
7646
#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK		(0x3F << 10)
7647
#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)	\
7648
			_MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
7649
						BXT_MIPI2_ESCLK_VAR_DIV_MASK)
7650
 
7651
#define  BXT_MIPI_ESCLK_VAR_DIV(port, val)	\
7652
			(val << BXT_MIPI_DIV_SHIFT(port))
7653
/* TX control divider to select actual TX clock output from (8x/var) */
7654
#define  BXT_MIPI1_TX_ESCLK_SHIFT		21
7655
#define  BXT_MIPI2_TX_ESCLK_SHIFT		5
7656
#define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
7657
			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7658
					BXT_MIPI2_TX_ESCLK_SHIFT)
7659
#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(3 << 21)
7660
#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(3 << 5)
7661
#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
7662
			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
7663
						BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7664
#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)	\
7665
		(0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7666
#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)	\
7667
		(0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7668
#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)	\
7669
		(0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7670
/* RX control divider to select actual RX clock output from 8x*/
7671
#define  BXT_MIPI1_RX_ESCLK_SHIFT		19
7672
#define  BXT_MIPI2_RX_ESCLK_SHIFT		3
7673
#define  BXT_MIPI_RX_ESCLK_SHIFT(port)		\
7674
			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
7675
					BXT_MIPI2_RX_ESCLK_SHIFT)
7676
#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK		(3 << 19)
7677
#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK		(3 << 3)
7678
#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)	\
7679
		(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7680
#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)	\
7681
		(1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7682
#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)	\
7683
		(2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7684
#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)	\
7685
		(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7686
/* BXT-A WA: Always prog DPHY dividers to 00 */
7687
#define  BXT_MIPI1_DPHY_DIV_SHIFT		16
7688
#define  BXT_MIPI2_DPHY_DIV_SHIFT		0
7689
#define  BXT_MIPI_DPHY_DIV_SHIFT(port)		\
7690
			_MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
7691
					BXT_MIPI2_DPHY_DIV_SHIFT)
7692
#define  BXT_MIPI_1_DPHY_DIVIDER_MASK		(3 << 16)
7693
#define  BXT_MIPI_2_DPHY_DIVIDER_MASK		(3 << 0)
7694
#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)	\
7695
		(3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
7696
 
7697
/* BXT MIPI mode configure */
7698
#define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
7699
#define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
6937 serge 7700
#define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
6084 serge 7701
		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7702
 
7703
#define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
7704
#define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
6937 serge 7705
#define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
6084 serge 7706
		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7707
 
7708
#define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
7709
#define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
6937 serge 7710
#define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
6084 serge 7711
		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7712
 
6937 serge 7713
#define BXT_DSI_PLL_CTL			_MMIO(0x161000)
6084 serge 7714
#define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
7715
#define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7716
#define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7717
#define  BXT_DSIC_16X_BY2		(1 << 10)
7718
#define  BXT_DSIC_16X_BY3		(2 << 10)
7719
#define  BXT_DSIC_16X_BY4		(3 << 10)
7720
#define  BXT_DSIA_16X_BY2		(1 << 8)
7721
#define  BXT_DSIA_16X_BY3		(2 << 8)
7722
#define  BXT_DSIA_16X_BY4		(3 << 8)
7723
#define  BXT_DSI_FREQ_SEL_SHIFT		8
7724
#define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
7725
 
7726
#define BXT_DSI_PLL_RATIO_MAX		0x7D
7727
#define BXT_DSI_PLL_RATIO_MIN		0x22
7728
#define BXT_DSI_PLL_RATIO_MASK		0xFF
6937 serge 7729
#define BXT_REF_CLOCK_KHZ		19200
6084 serge 7730
 
6937 serge 7731
#define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
6084 serge 7732
#define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
7733
#define  BXT_DSI_PLL_LOCKED		(1 << 30)
7734
 
4560 Serge 7735
#define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
6084 serge 7736
#define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
6937 serge 7737
#define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
6084 serge 7738
 
7739
 /* BXT port control */
7740
#define _BXT_MIPIA_PORT_CTRL				0x6B0C0
7741
#define _BXT_MIPIC_PORT_CTRL				0x6B8C0
6937 serge 7742
#define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
6084 serge 7743
 
7744
#define  DPI_ENABLE					(1 << 31) /* A + C */
4560 Serge 7745
#define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
7746
#define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
6084 serge 7747
#define  DUAL_LINK_MODE_SHIFT				26
4560 Serge 7748
#define  DUAL_LINK_MODE_MASK				(1 << 26)
7749
#define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
7750
#define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
6084 serge 7751
#define  DITHERING_ENABLE				(1 << 25) /* A + C */
4560 Serge 7752
#define  FLOPPED_HSTX					(1 << 23)
7753
#define  DE_INVERT					(1 << 19) /* XXX */
7754
#define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
7755
#define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
7756
#define  AFE_LATCHOUT					(1 << 17)
7757
#define  LP_OUTPUT_HOLD					(1 << 16)
6084 serge 7758
#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
7759
#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
7760
#define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
7761
#define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
4560 Serge 7762
#define  CSB_SHIFT					9
7763
#define  CSB_MASK					(3 << 9)
7764
#define  CSB_20MHZ					(0 << 9)
7765
#define  CSB_10MHZ					(1 << 9)
7766
#define  CSB_40MHZ					(2 << 9)
7767
#define  BANDGAP_MASK					(1 << 8)
7768
#define  BANDGAP_PNW_CIRCUIT				(0 << 8)
7769
#define  BANDGAP_LNC_CIRCUIT				(1 << 8)
6084 serge 7770
#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
7771
#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
7772
#define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
7773
#define  TEARING_EFFECT_SHIFT				2 /* A + C */
4560 Serge 7774
#define  TEARING_EFFECT_MASK				(3 << 2)
7775
#define  TEARING_EFFECT_OFF				(0 << 2)
7776
#define  TEARING_EFFECT_DSI				(1 << 2)
7777
#define  TEARING_EFFECT_GPIO				(2 << 2)
7778
#define  LANE_CONFIGURATION_SHIFT			0
7779
#define  LANE_CONFIGURATION_MASK			(3 << 0)
7780
#define  LANE_CONFIGURATION_4LANE			(0 << 0)
7781
#define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
7782
#define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
7783
 
7784
#define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
6084 serge 7785
#define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
6937 serge 7786
#define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
4560 Serge 7787
#define  TEARING_EFFECT_DELAY_SHIFT			0
7788
#define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
7789
 
7790
/* XXX: all bits reserved */
6084 serge 7791
#define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
4560 Serge 7792
 
7793
/* MIPI DSI Controller and D-PHY registers */
7794
 
5060 serge 7795
#define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
6084 serge 7796
#define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
6937 serge 7797
#define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
4560 Serge 7798
#define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
7799
#define  ULPS_STATE_MASK				(3 << 1)
7800
#define  ULPS_STATE_ENTER				(2 << 1)
7801
#define  ULPS_STATE_EXIT				(1 << 1)
7802
#define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
7803
#define  DEVICE_READY					(1 << 0)
7804
 
5060 serge 7805
#define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
6084 serge 7806
#define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
6937 serge 7807
#define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
5060 serge 7808
#define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
6084 serge 7809
#define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
6937 serge 7810
#define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
4560 Serge 7811
#define  TEARING_EFFECT					(1 << 31)
7812
#define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
7813
#define  GEN_READ_DATA_AVAIL				(1 << 29)
7814
#define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
7815
#define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
7816
#define  RX_PROT_VIOLATION				(1 << 26)
7817
#define  RX_INVALID_TX_LENGTH				(1 << 25)
7818
#define  ACK_WITH_NO_ERROR				(1 << 24)
7819
#define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
7820
#define  LP_RX_TIMEOUT					(1 << 22)
7821
#define  HS_TX_TIMEOUT					(1 << 21)
7822
#define  DPI_FIFO_UNDERRUN				(1 << 20)
7823
#define  LOW_CONTENTION					(1 << 19)
7824
#define  HIGH_CONTENTION				(1 << 18)
7825
#define  TXDSI_VC_ID_INVALID				(1 << 17)
7826
#define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
7827
#define  TXCHECKSUM_ERROR				(1 << 15)
7828
#define  TXECC_MULTIBIT_ERROR				(1 << 14)
7829
#define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
7830
#define  TXFALSE_CONTROL_ERROR				(1 << 12)
7831
#define  RXDSI_VC_ID_INVALID				(1 << 11)
7832
#define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
7833
#define  RXCHECKSUM_ERROR				(1 << 9)
7834
#define  RXECC_MULTIBIT_ERROR				(1 << 8)
7835
#define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
7836
#define  RXFALSE_CONTROL_ERROR				(1 << 6)
7837
#define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
7838
#define  RX_LP_TX_SYNC_ERROR				(1 << 4)
7839
#define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
7840
#define  RXEOT_SYNC_ERROR				(1 << 2)
7841
#define  RXSOT_SYNC_ERROR				(1 << 1)
7842
#define  RXSOT_ERROR					(1 << 0)
7843
 
5060 serge 7844
#define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
6084 serge 7845
#define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
6937 serge 7846
#define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
4560 Serge 7847
#define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
7848
#define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
7849
#define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
7850
#define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
7851
#define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
7852
#define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
7853
#define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
7854
#define  VID_MODE_FORMAT_MASK				(0xf << 7)
7855
#define  VID_MODE_NOT_SUPPORTED				(0 << 7)
7856
#define  VID_MODE_FORMAT_RGB565				(1 << 7)
7857
#define  VID_MODE_FORMAT_RGB666				(2 << 7)
7858
#define  VID_MODE_FORMAT_RGB666_LOOSE			(3 << 7)
7859
#define  VID_MODE_FORMAT_RGB888				(4 << 7)
7860
#define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
7861
#define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
7862
#define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
7863
#define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
7864
#define  DATA_LANES_PRG_REG_SHIFT			0
7865
#define  DATA_LANES_PRG_REG_MASK			(7 << 0)
7866
 
5060 serge 7867
#define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
6084 serge 7868
#define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
6937 serge 7869
#define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
4560 Serge 7870
#define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
7871
 
5060 serge 7872
#define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
6084 serge 7873
#define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
6937 serge 7874
#define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
4560 Serge 7875
#define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
7876
 
5060 serge 7877
#define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
6084 serge 7878
#define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
6937 serge 7879
#define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
4560 Serge 7880
#define  TURN_AROUND_TIMEOUT_MASK			0x3f
7881
 
5060 serge 7882
#define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
6084 serge 7883
#define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
6937 serge 7884
#define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
4560 Serge 7885
#define  DEVICE_RESET_TIMER_MASK			0xffff
7886
 
5060 serge 7887
#define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
6084 serge 7888
#define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
6937 serge 7889
#define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
4560 Serge 7890
#define  VERTICAL_ADDRESS_SHIFT				16
7891
#define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
7892
#define  HORIZONTAL_ADDRESS_SHIFT			0
7893
#define  HORIZONTAL_ADDRESS_MASK			0xffff
7894
 
5060 serge 7895
#define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
6084 serge 7896
#define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
6937 serge 7897
#define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
4560 Serge 7898
#define  DBI_FIFO_EMPTY_HALF				(0 << 0)
7899
#define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
7900
#define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
7901
 
7902
/* regs below are bits 15:0 */
5060 serge 7903
#define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
6084 serge 7904
#define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
6937 serge 7905
#define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
4560 Serge 7906
 
5060 serge 7907
#define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
6084 serge 7908
#define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
6937 serge 7909
#define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
4560 Serge 7910
 
5060 serge 7911
#define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
6084 serge 7912
#define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
6937 serge 7913
#define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
4560 Serge 7914
 
5060 serge 7915
#define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
6084 serge 7916
#define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
6937 serge 7917
#define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
4560 Serge 7918
 
5060 serge 7919
#define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
6084 serge 7920
#define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
6937 serge 7921
#define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
4560 Serge 7922
 
5060 serge 7923
#define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
6084 serge 7924
#define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
6937 serge 7925
#define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
4560 Serge 7926
 
5060 serge 7927
#define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
6084 serge 7928
#define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
6937 serge 7929
#define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
4560 Serge 7930
 
5060 serge 7931
#define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
6084 serge 7932
#define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
6937 serge 7933
#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
5060 serge 7934
 
4560 Serge 7935
/* regs above are bits 15:0 */
7936
 
5060 serge 7937
#define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
6084 serge 7938
#define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
6937 serge 7939
#define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
4560 Serge 7940
#define  DPI_LP_MODE					(1 << 6)
7941
#define  BACKLIGHT_OFF					(1 << 5)
7942
#define  BACKLIGHT_ON					(1 << 4)
7943
#define  COLOR_MODE_OFF					(1 << 3)
7944
#define  COLOR_MODE_ON					(1 << 2)
7945
#define  TURN_ON					(1 << 1)
7946
#define  SHUTDOWN					(1 << 0)
7947
 
5060 serge 7948
#define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
6084 serge 7949
#define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
6937 serge 7950
#define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
4560 Serge 7951
#define  COMMAND_BYTE_SHIFT				0
7952
#define  COMMAND_BYTE_MASK				(0x3f << 0)
7953
 
5060 serge 7954
#define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
6084 serge 7955
#define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
6937 serge 7956
#define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
4560 Serge 7957
#define  MASTER_INIT_TIMER_SHIFT			0
7958
#define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
7959
 
5060 serge 7960
#define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
6084 serge 7961
#define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
6937 serge 7962
#define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
6084 serge 7963
			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
4560 Serge 7964
#define  MAX_RETURN_PKT_SIZE_SHIFT			0
7965
#define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
7966
 
5060 serge 7967
#define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
6084 serge 7968
#define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
6937 serge 7969
#define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
4560 Serge 7970
#define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
7971
#define  DISABLE_VIDEO_BTA				(1 << 3)
7972
#define  IP_TG_CONFIG					(1 << 2)
7973
#define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
7974
#define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
7975
#define  VIDEO_MODE_BURST				(3 << 0)
7976
 
5060 serge 7977
#define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
6084 serge 7978
#define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
6937 serge 7979
#define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
4560 Serge 7980
#define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
7981
#define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
7982
#define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
7983
#define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
7984
#define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7985
#define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
7986
#define  CLOCKSTOP					(1 << 1)
7987
#define  EOT_DISABLE					(1 << 0)
7988
 
5060 serge 7989
#define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
6084 serge 7990
#define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
6937 serge 7991
#define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
4560 Serge 7992
#define  LP_BYTECLK_SHIFT				0
7993
#define  LP_BYTECLK_MASK				(0xffff << 0)
7994
 
7995
/* bits 31:0 */
5060 serge 7996
#define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
6084 serge 7997
#define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
6937 serge 7998
#define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
4560 Serge 7999
 
8000
/* bits 31:0 */
5060 serge 8001
#define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
6084 serge 8002
#define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
6937 serge 8003
#define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
4560 Serge 8004
 
5060 serge 8005
#define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
6084 serge 8006
#define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
6937 serge 8007
#define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
5060 serge 8008
#define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
6084 serge 8009
#define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
6937 serge 8010
#define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
4560 Serge 8011
#define  LONG_PACKET_WORD_COUNT_SHIFT			8
8012
#define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
8013
#define  SHORT_PACKET_PARAM_SHIFT			8
8014
#define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
8015
#define  VIRTUAL_CHANNEL_SHIFT				6
8016
#define  VIRTUAL_CHANNEL_MASK				(3 << 6)
8017
#define  DATA_TYPE_SHIFT				0
6084 serge 8018
#define  DATA_TYPE_MASK					(0x3f << 0)
4560 Serge 8019
/* data type values, see include/video/mipi_display.h */
8020
 
5060 serge 8021
#define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
6084 serge 8022
#define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
6937 serge 8023
#define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
4560 Serge 8024
#define  DPI_FIFO_EMPTY					(1 << 28)
8025
#define  DBI_FIFO_EMPTY					(1 << 27)
8026
#define  LP_CTRL_FIFO_EMPTY				(1 << 26)
8027
#define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
8028
#define  LP_CTRL_FIFO_FULL				(1 << 24)
8029
#define  HS_CTRL_FIFO_EMPTY				(1 << 18)
8030
#define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
8031
#define  HS_CTRL_FIFO_FULL				(1 << 16)
8032
#define  LP_DATA_FIFO_EMPTY				(1 << 10)
8033
#define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
8034
#define  LP_DATA_FIFO_FULL				(1 << 8)
8035
#define  HS_DATA_FIFO_EMPTY				(1 << 2)
8036
#define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
8037
#define  HS_DATA_FIFO_FULL				(1 << 0)
8038
 
5060 serge 8039
#define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
6084 serge 8040
#define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
6937 serge 8041
#define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
4560 Serge 8042
#define  DBI_HS_LP_MODE_MASK				(1 << 0)
8043
#define  DBI_LP_MODE					(1 << 0)
8044
#define  DBI_HS_MODE					(0 << 0)
8045
 
5060 serge 8046
#define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
6084 serge 8047
#define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
6937 serge 8048
#define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
4560 Serge 8049
#define  EXIT_ZERO_COUNT_SHIFT				24
8050
#define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
8051
#define  TRAIL_COUNT_SHIFT				16
8052
#define  TRAIL_COUNT_MASK				(0x1f << 16)
8053
#define  CLK_ZERO_COUNT_SHIFT				8
8054
#define  CLK_ZERO_COUNT_MASK				(0xff << 8)
8055
#define  PREPARE_COUNT_SHIFT				0
8056
#define  PREPARE_COUNT_MASK				(0x3f << 0)
8057
 
8058
/* bits 31:0 */
5060 serge 8059
#define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
6084 serge 8060
#define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
6937 serge 8061
#define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
4560 Serge 8062
 
6937 serge 8063
#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
8064
#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
8065
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
4560 Serge 8066
#define  LP_HS_SSW_CNT_SHIFT				16
8067
#define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
8068
#define  HS_LP_PWR_SW_CNT_SHIFT				0
8069
#define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
8070
 
5060 serge 8071
#define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
6084 serge 8072
#define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
6937 serge 8073
#define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
4560 Serge 8074
#define  STOP_STATE_STALL_COUNTER_SHIFT			0
8075
#define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
8076
 
5060 serge 8077
#define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
6084 serge 8078
#define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
6937 serge 8079
#define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
5060 serge 8080
#define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
6084 serge 8081
#define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
6937 serge 8082
#define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
4560 Serge 8083
#define  RX_CONTENTION_DETECTED				(1 << 0)
8084
 
8085
/* XXX: only pipe A ?!? */
5060 serge 8086
#define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
4560 Serge 8087
#define  DBI_TYPEC_ENABLE				(1 << 31)
8088
#define  DBI_TYPEC_WIP					(1 << 30)
8089
#define  DBI_TYPEC_OPTION_SHIFT				28
8090
#define  DBI_TYPEC_OPTION_MASK				(3 << 28)
8091
#define  DBI_TYPEC_FREQ_SHIFT				24
8092
#define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
8093
#define  DBI_TYPEC_OVERRIDE				(1 << 8)
8094
#define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
8095
#define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
8096
 
8097
 
8098
/* MIPI adapter registers */
8099
 
5060 serge 8100
#define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
6084 serge 8101
#define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
6937 serge 8102
#define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
4560 Serge 8103
#define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
8104
#define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
8105
#define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
8106
#define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
8107
#define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
8108
#define  READ_REQUEST_PRIORITY_SHIFT			3
8109
#define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
8110
#define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
8111
#define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
8112
#define  RGB_FLIP_TO_BGR				(1 << 2)
8113
 
6084 serge 8114
#define  BXT_PIPE_SELECT_MASK				(7 << 7)
6937 serge 8115
#define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
6084 serge 8116
 
5060 serge 8117
#define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
6084 serge 8118
#define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
6937 serge 8119
#define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
4560 Serge 8120
#define  DATA_MEM_ADDRESS_SHIFT				5
8121
#define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
8122
#define  DATA_VALID					(1 << 0)
8123
 
5060 serge 8124
#define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
6084 serge 8125
#define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
6937 serge 8126
#define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
4560 Serge 8127
#define  DATA_LENGTH_SHIFT				0
8128
#define  DATA_LENGTH_MASK				(0xfffff << 0)
8129
 
5060 serge 8130
#define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
6084 serge 8131
#define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
6937 serge 8132
#define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
4560 Serge 8133
#define  COMMAND_MEM_ADDRESS_SHIFT			5
8134
#define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
8135
#define  AUTO_PWG_ENABLE				(1 << 2)
8136
#define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
8137
#define  COMMAND_VALID					(1 << 0)
8138
 
5060 serge 8139
#define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
6084 serge 8140
#define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
6937 serge 8141
#define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
4560 Serge 8142
#define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
8143
#define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
8144
 
5060 serge 8145
#define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
6084 serge 8146
#define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
6937 serge 8147
#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
4560 Serge 8148
 
5060 serge 8149
#define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
6084 serge 8150
#define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
6937 serge 8151
#define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
4560 Serge 8152
#define  READ_DATA_VALID(n)				(1 << (n))
8153
 
5060 serge 8154
/* For UMS only (deprecated): */
8155
#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8156
#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
8157
 
6084 serge 8158
/* MOCS (Memory Object Control State) registers */
6937 serge 8159
#define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
6084 serge 8160
 
6937 serge 8161
#define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
8162
#define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
8163
#define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
8164
#define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
8165
#define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
6084 serge 8166
 
2325 Serge 8167
#endif /* _I915_REG_H_ */