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/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _I915_REG_H_

#define _I915_REG_H_

#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))

#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))

#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \

			       (pipe) == PIPE_B ? (b) : (c))

#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)

/* PCI config space */

#define HPLLCC	0xc0 /* 855 only */

#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)

#define   GC_CLOCK_133_200		(0 << 0)

#define   GC_CLOCK_100_200		(1 << 0)

#define   GC_CLOCK_100_133		(2 << 0)

#define   GC_CLOCK_166_250		(3 << 0)

#define GCFGC2	0xda

#define GCFGC	0xf0 /* 915+ only */

#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)

#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)

#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)

#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)

#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)

#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)

#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)

#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)

#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)

#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)

#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)

#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)

#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)

#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)

#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)

#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)

#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)

#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)

#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)

#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)

#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)

#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)

#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)

#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)

#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)

#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */

/* Graphics reset regs */

#define I965_GDRST 0xc0 /* PCI config register */

#define  GRDOM_FULL	(0<<2)

#define  GRDOM_RENDER	(1<<2)

#define  GRDOM_MEDIA	(3<<2)

#define  GRDOM_MASK	(3<<2)

#define  GRDOM_RESET_ENABLE (1<<0)

#define ILK_GDSR 0x2ca4 /* MCHBAR offset */

#define  ILK_GRDOM_FULL		(0<<1)

#define  ILK_GRDOM_RENDER	(1<<1)

#define  ILK_GRDOM_MEDIA	(3<<1)

#define  ILK_GRDOM_MASK		(3<<1)

#define  ILK_GRDOM_RESET_ENABLE (1<<0)

#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */

#define   GEN6_MBC_SNPCR_SHIFT	21

#define   GEN6_MBC_SNPCR_MASK	(3<<21)

#define   GEN6_MBC_SNPCR_MAX	(0<<21)

#define   GEN6_MBC_SNPCR_MED	(1<<21)

#define   GEN6_MBC_SNPCR_LOW	(2<<21)

#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */

#define VLV_G3DCTL		0x9024

#define VLV_GSCKGCTL		0x9028

#define GEN6_MBCTL		0x0907c

#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)

#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)

#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)

#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)

#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)

#define GEN6_GDRST	0x941c

#define  GEN6_GRDOM_FULL		(1 << 0)

#define  GEN6_GRDOM_RENDER		(1 << 1)

#define  GEN6_GRDOM_MEDIA		(1 << 2)

#define  GEN6_GRDOM_BLT			(1 << 3)

#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)

#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)

#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)

#define   PP_DIR_DCLV_2G		0xffffffff

#define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))

#define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)

#define GAM_ECOCHK			0x4090

#define   ECOCHK_SNB_BIT		(1<<10)

#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)

#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)

#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)

#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)

#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)

#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)

#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)

#define GAC_ECO_BITS			0x14090

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)

#define   ECOBITS_PPGTT_CACHE4B		(0<<8)

#define GAB_CTL				0x24000

#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)

/* VGA stuff */

#define VGA_ST01_MDA 0x3ba

#define VGA_ST01_CGA 0x3da

#define VGA_MSR_WRITE 0x3c2

#define VGA_MSR_READ 0x3cc

#define   VGA_MSR_MEM_EN (1<<1)

#define   VGA_MSR_CGA_MODE (1<<0)

#define VGA_SR_INDEX 0x3c4

#define SR01			1

#define VGA_SR_DATA 0x3c5

#define VGA_AR_INDEX 0x3c0

#define   VGA_AR_VID_EN (1<<5)

#define VGA_AR_DATA_WRITE 0x3c0

#define VGA_AR_DATA_READ 0x3c1

#define VGA_GR_INDEX 0x3ce

#define VGA_GR_DATA 0x3cf

/* GR05 */

#define   VGA_GR_MEM_READ_MODE_SHIFT 3

#define     VGA_GR_MEM_READ_MODE_PLANE 1

/* GR06 */

#define   VGA_GR_MEM_MODE_MASK 0xc

#define   VGA_GR_MEM_MODE_SHIFT 2

#define   VGA_GR_MEM_A0000_AFFFF 0

#define   VGA_GR_MEM_A0000_BFFFF 1

#define   VGA_GR_MEM_B0000_B7FFF 2

#define   VGA_GR_MEM_B0000_BFFFF 3

#define VGA_DACMASK 0x3c6

#define VGA_DACRX 0x3c7

#define VGA_DACWX 0x3c8

#define VGA_DACDATA 0x3c9

#define VGA_CR_INDEX_MDA 0x3b4

#define VGA_CR_DATA_MDA 0x3b5

#define VGA_CR_INDEX_CGA 0x3d4

#define VGA_CR_DATA_CGA 0x3d5

/*

 * Instruction field definitions used by the command parser

 */

#define INSTR_CLIENT_SHIFT      29

#define INSTR_CLIENT_MASK       0xE0000000

#define   INSTR_MI_CLIENT       0x0

#define   INSTR_BC_CLIENT       0x2

#define   INSTR_RC_CLIENT       0x3

#define INSTR_SUBCLIENT_SHIFT   27

#define INSTR_SUBCLIENT_MASK    0x18000000

#define   INSTR_MEDIA_SUBCLIENT 0x2

/*

 * Memory interface instructions used by the kernel

 */

#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))

/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */

#define  MI_GLOBAL_GTT    (1<<22)

#define MI_NOOP			MI_INSTR(0, 0)

#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)

#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)

#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)

#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)

#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)

#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

#define MI_FLUSH		MI_INSTR(0x04, 0)

#define   MI_READ_FLUSH		(1 << 0)

#define   MI_EXE_FLUSH		(1 << 1)

#define   MI_NO_WRITE_FLUSH	(1 << 2)

#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)

#define   MI_ARB_ENABLE			(1<<0)

#define   MI_ARB_DISABLE		(0<<0)

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)

#define   MI_SUSPEND_FLUSH_EN	(1<<0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)

#define   MI_OVERLAY_CONTINUE	(0x0<<21)

#define   MI_OVERLAY_ON		(0x1<<21)

#define   MI_OVERLAY_OFF	(0x2<<21)

#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)

#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)

#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)

#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)

/* IVB has funny definitions for which plane to flip. */

#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)

#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */

#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)

#define   MI_SEMAPHORE_UPDATE	    (1<<21)

#define   MI_SEMAPHORE_COMPARE	    (1<<20)

#define   MI_SEMAPHORE_REGISTER	    (1<<18)

#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */

#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */

#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */

#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */

#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */

#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */

#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */

#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */

#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */

#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */

#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define   MI_SEMAPHORE_SYNC_INVALID  (3<<16)

#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)

#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)

#define   MI_MM_SPACE_GTT		(1<<8)

#define   MI_MM_SPACE_PHYSICAL		(0<<8)

#define   MI_SAVE_EXT_STATE_EN		(1<<3)

#define   MI_RESTORE_EXT_STATE_EN	(1<<2)

#define   MI_FORCE_RESTORE		(1<<1)

#define   MI_RESTORE_INHIBIT		(1<<0)

#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */

#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)

#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */

#define   MI_SEMAPHORE_POLL		(1<<15)

#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)

#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)

#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */

#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)

#define   MI_STORE_DWORD_INDEX_SHIFT 2

/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:

 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw

 *   simply ignores the register load under certain conditions.

 * - One can actually load arbitrary many arbitrary registers: Simply issue x

 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!

 */

#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)

#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)

#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)

#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)

#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */

#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)

#define   MI_INVALIDATE_TLB	(1<<18)

#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)

#define   MI_FLUSH_DW_OP_MASK		(3<<14)

#define   MI_FLUSH_DW_NOTIFY		(1<<8)

#define   MI_INVALIDATE_BSD	(1<<7)

#define   MI_FLUSH_DW_USE_GTT		(1<<2)

#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)

#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)

#define   MI_BATCH_NON_SECURE	(1)

/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */

#define   MI_BATCH_NON_SECURE_I965 (1<<8)

#define   MI_BATCH_PPGTT_HSW		(1<<8)

#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)

#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)

#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */

#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)

#define MI_PREDICATE_RESULT_2	(0x2214)

#define  LOWER_SLICE_ENABLED	(1<<0)

#define  LOWER_SLICE_DISABLED	(0<<0)

/*

 * 3D instructions used by the kernel

 */

#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))

#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))

#define   SC_UPDATE_SCISSOR       (0x1<<1)

#define   SC_ENABLE_MASK          (0x1<<0)

#define   SC_ENABLE               (0x1<<0)

#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))

#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

#define   SCI_YMIN_MASK      (0xffff<<16)

#define   SCI_XMIN_MASK      (0xffff<<0)

#define   SCI_YMAX_MASK      (0xffff<<16)

#define   SCI_XMAX_MASK      (0xffff<<0)

#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))

#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))

#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)

#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)

#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)

#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)

#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)

#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)

#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)

#define   BLT_DEPTH_8			(0<<24)

#define   BLT_DEPTH_16_565		(1<<24)

#define   BLT_DEPTH_16_1555		(2<<24)

#define   BLT_DEPTH_32			(3<<24)

#define   BLT_ROP_GXCOPY		(0xcc<<16)

#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */

#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */

#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

#define   ASYNC_FLIP                (1<<22)

#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)

#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)

#define   PIPE_CONTROL_CS_STALL				(1<<20)

#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)

#define   PIPE_CONTROL_QW_WRITE	(1<<14)

#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)

#define   PIPE_CONTROL_DEPTH_STALL (1<<13)

#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)

#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */

#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_NOTIFY	(1<<8)

#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */

#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)

#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)

#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)

#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)

#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)

#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

/*

 * Commands used only by the command parser

 */

#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)

#define MI_ARB_CHECK            MI_INSTR(0x05, 0)

#define MI_RS_CONTROL           MI_INSTR(0x06, 0)

#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)

#define MI_PREDICATE            MI_INSTR(0x0C, 0)

#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)

#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)

#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)

#define MI_URB_CLEAR            MI_INSTR(0x19, 0)

#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)

#define MI_CLFLUSH              MI_INSTR(0x27, 0)

#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)

#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)

#define MI_LOAD_REGISTER_MEM    MI_INSTR(0x29, 0)

#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)

#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)

#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)

#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)

#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)

#define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))

#define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))

#define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))

#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)

#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))

#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))

#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))

#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))

#define GFX_OP_3DSTATE_SO_DECL_LIST \

	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \

	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))

#define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))

#define COLOR_BLT     ((0x2<<29)|(0x40<<22))

#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))

/*

 * Registers used only by the command parser

 */

#define BCS_SWCTRL 0x22200

#define HS_INVOCATION_COUNT 0x2300

#define DS_INVOCATION_COUNT 0x2308

#define IA_VERTICES_COUNT   0x2310

#define IA_PRIMITIVES_COUNT 0x2318

#define VS_INVOCATION_COUNT 0x2320

#define GS_INVOCATION_COUNT 0x2328

#define GS_PRIMITIVES_COUNT 0x2330

#define CL_INVOCATION_COUNT 0x2338

#define CL_PRIMITIVES_COUNT 0x2340

#define PS_INVOCATION_COUNT 0x2348

#define PS_DEPTH_COUNT      0x2350

/* There are the 4 64-bit counter registers, one for each stream output */

#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)

#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)

#define GEN7_3DPRIM_END_OFFSET          0x2420

#define GEN7_3DPRIM_START_VERTEX        0x2430

#define GEN7_3DPRIM_VERTEX_COUNT        0x2434

#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438

#define GEN7_3DPRIM_START_INSTANCE      0x243C

#define GEN7_3DPRIM_BASE_VERTEX         0x2440

#define OACONTROL 0x2360

#define _GEN7_PIPEA_DE_LOAD_SL	0x70068

#define _GEN7_PIPEB_DE_LOAD_SL	0x71068

#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \

					 _GEN7_PIPEA_DE_LOAD_SL, \

					 _GEN7_PIPEB_DE_LOAD_SL)

/*

 * Reset registers

 */

#define DEBUG_RESET_I830		0x6070

#define  DEBUG_RESET_FULL		(1<<7)

#define  DEBUG_RESET_RENDER		(1<<8)

#define  DEBUG_RESET_DISPLAY		(1<<9)

/*

 * IOSF sideband

 */

#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)

#define   IOSF_DEVFN_SHIFT			24

#define   IOSF_OPCODE_SHIFT			16

#define   IOSF_PORT_SHIFT			8

#define   IOSF_BYTE_ENABLES_SHIFT		4

#define   IOSF_BAR_SHIFT			1

#define   IOSF_SB_BUSY				(1<<0)

#define   IOSF_PORT_BUNIT			0x3

#define   IOSF_PORT_PUNIT			0x4

#define   IOSF_PORT_NC				0x11

#define   IOSF_PORT_DPIO			0x12

#define   IOSF_PORT_DPIO_2			0x1a

#define   IOSF_PORT_GPIO_NC			0x13

#define   IOSF_PORT_CCK				0x14

#define   IOSF_PORT_CCU				0xA9

#define   IOSF_PORT_GPS_CORE			0x48

#define   IOSF_PORT_FLISDSI			0x1B

#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)

#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)

/* See configdb bunit SB addr map */

#define BUNIT_REG_BISOC				0x11

#define PUNIT_REG_DSPFREQ			0x36

#define   DSPFREQSTAT_SHIFT			30

#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)

#define   DSPFREQGUAR_SHIFT			14

#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)

/* See the PUNIT HAS v0.8 for the below bits */

enum punit_power_well {

	PUNIT_POWER_WELL_RENDER			= 0,

	PUNIT_POWER_WELL_MEDIA			= 1,

	PUNIT_POWER_WELL_DISP2D			= 3,

	PUNIT_POWER_WELL_DPIO_CMN_BC		= 5,

	PUNIT_POWER_WELL_DPIO_TX_B_LANES_01	= 6,

	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,

	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,

	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,

	PUNIT_POWER_WELL_DPIO_RX0		= 10,

	PUNIT_POWER_WELL_DPIO_RX1		= 11,

	PUNIT_POWER_WELL_NUM,

};

#define PUNIT_REG_PWRGT_CTRL			0x60

#define PUNIT_REG_PWRGT_STATUS			0x61

#define   PUNIT_PWRGT_MASK(power_well)		(3 << ((power_well) * 2))

#define   PUNIT_PWRGT_PWR_ON(power_well)	(0 << ((power_well) * 2))

#define   PUNIT_PWRGT_CLK_GATE(power_well)	(1 << ((power_well) * 2))

#define   PUNIT_PWRGT_RESET(power_well)		(2 << ((power_well) * 2))

#define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))

#define PUNIT_REG_GPU_LFM			0xd3

#define PUNIT_REG_GPU_FREQ_REQ			0xd4

#define PUNIT_REG_GPU_FREQ_STS			0xd8

#define   GENFREQSTATUS				(1<<0)

#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc

#define PUNIT_REG_CZ_TIMESTAMP			0xce

#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */

#define PUNIT_GPU_STATUS_REG			0xdb

#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16

#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff

#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8

#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff

#define PUNIT_GPU_DUTYCYCLE_REG		0xdf

#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8

#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff

#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c

#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3

#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800

#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34

#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007

#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30

#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27

#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000

#define VLV_CZ_CLOCK_TO_MILLI_SEC		100000

#define VLV_RP_UP_EI_THRESHOLD			90

#define VLV_RP_DOWN_EI_THRESHOLD		70

#define VLV_INT_COUNT_FOR_DOWN_EI		5

/* vlv2 north clock has */

#define CCK_FUSE_REG				0x8

#define  CCK_FUSE_HPLL_FREQ_MASK		0x3

#define CCK_REG_DSI_PLL_FUSE			0x44

#define CCK_REG_DSI_PLL_CONTROL			0x48

#define  DSI_PLL_VCO_EN				(1 << 31)

#define  DSI_PLL_LDO_GATE			(1 << 30)

#define  DSI_PLL_P1_POST_DIV_SHIFT		17

#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)

#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)

#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)

#define  DSI_PLL_MUX_MASK			(3 << 9)

#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)

#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)

#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)

#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)

#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)

#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)

#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)

#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)

#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)

#define  DSI_PLL_LOCK				(1 << 0)

#define CCK_REG_DSI_PLL_DIVIDER			0x4c

#define  DSI_PLL_LFSR				(1 << 31)

#define  DSI_PLL_FRACTION_EN			(1 << 30)

#define  DSI_PLL_FRAC_COUNTER_SHIFT		27

#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)

#define  DSI_PLL_USYNC_CNT_SHIFT		18

#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)

#define  DSI_PLL_N1_DIV_SHIFT			16

#define  DSI_PLL_N1_DIV_MASK			(3 << 16)

#define  DSI_PLL_M1_DIV_SHIFT			0

#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)

#define CCK_DISPLAY_CLOCK_CONTROL		0x6b

#define  DISPLAY_TRUNK_FORCE_ON			(1 << 17)

#define  DISPLAY_TRUNK_FORCE_OFF		(1 << 16)

#define  DISPLAY_FREQUENCY_STATUS		(0x1f << 8)

#define  DISPLAY_FREQUENCY_STATUS_SHIFT		8

#define  DISPLAY_FREQUENCY_VALUES		(0x1f << 0)

/**

 * DOC: DPIO

 *

 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI

 * ports. DPIO is the name given to such a display PHY. These PHYs

 * don't follow the standard programming model using direct MMIO

 * registers, and instead their registers must be accessed trough IOSF

 * sideband. VLV has one such PHY for driving ports B and C, and CHV

 * adds another PHY for driving port D. Each PHY responds to specific

 * IOSF-SB port.

 *

 * Each display PHY is made up of one or two channels. Each channel

 * houses a common lane part which contains the PLL and other common

 * logic. CH0 common lane also contains the IOSF-SB logic for the

 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock

 * must be running when any DPIO registers are accessed.

 *

 * In addition to having their own registers, the PHYs are also

 * controlled through some dedicated signals from the display

 * controller. These include PLL reference clock enable, PLL enable,

 * and CRI clock selection, for example.

 *

 * Eeach channel also has two splines (also called data lanes), and

 * each spline is made up of one Physical Access Coding Sub-Layer

 * (PCS) block and two TX lanes. So each channel has two PCS blocks

 * and four TX lanes. The TX lanes are used as DP lanes or TMDS

 * data/clock pairs depending on the output type.

 *

 * Additionally the PHY also contains an AUX lane with AUX blocks

 * for each channel. This is used for DP AUX communication, but

 * this fact isn't really relevant for the driver since AUX is

 * controlled from the display controller side. No DPIO registers

 * need to be accessed during AUX communication,

 *

 * Generally the common lane corresponds to the pipe and

 * the spline (PCS/TX) correponds to the port.

 *

 * For dual channel PHY (VLV/CHV):

 *

 *  pipe A == CMN/PLL/REF CH0

 *

 *  pipe B == CMN/PLL/REF CH1

 *

 *  port B == PCS/TX CH0

 *

 *  port C == PCS/TX CH1

 *

 * This is especially important when we cross the streams

 * ie. drive port B with pipe B, or port C with pipe A.

 *

 * For single channel PHY (CHV):

 *

 *  pipe C == CMN/PLL/REF CH0

 *

 *  port D == PCS/TX CH0

 *

 * Note: digital port B is DDI0, digital port C is DDI1,

 * digital port D is DDI2

 */

/*

 * Dual channel PHY (VLV/CHV)

 * ---------------------------------

 * |      CH0      |      CH1      |

 * |  CMN/PLL/REF  |  CMN/PLL/REF  |

 * |---------------|---------------| Display PHY

 * | PCS01 | PCS23 | PCS01 | PCS23 |

 * |-------|-------|-------|-------|

 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|

 * ---------------------------------

 * |     DDI0      |     DDI1      | DP/HDMI ports

 * ---------------------------------

 *

 * Single channel PHY (CHV)

 * -----------------

 * |      CH0      |

 * |  CMN/PLL/REF  |

 * |---------------| Display PHY

 * | PCS01 | PCS23 |

 * |-------|-------|

 * |TX0|TX1|TX2|TX3|

 * -----------------

 * |     DDI2      | DP/HDMI port

 * -----------------

 */

#define DPIO_DEVFN			0

#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)

#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */

#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */

#define  DPIO_SFR_BYPASS		(1<<1)

#define  DPIO_CMNRST			(1<<0)

#define DPIO_PHY(pipe)			((pipe) >> 1)

#define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])

/*

 * Per pipe/PLL DPIO regs

 */

#define _VLV_PLL_DW3_CH0		0x800c

#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */

#define   DPIO_POST_DIV_DAC		0

#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */

#define   DPIO_POST_DIV_LVDS1		2

#define   DPIO_POST_DIV_LVDS2		3

#define   DPIO_K_SHIFT			(24) /* 4 bits */

#define   DPIO_P1_SHIFT			(21) /* 3 bits */

#define   DPIO_P2_SHIFT			(16) /* 5 bits */

#define   DPIO_N_SHIFT			(12) /* 4 bits */

#define   DPIO_ENABLE_CALIBRATION	(1<<11)

#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */

#define   DPIO_M2DIV_MASK		0xff

#define _VLV_PLL_DW3_CH1		0x802c

#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)

#define _VLV_PLL_DW5_CH0		0x8014

#define   DPIO_REFSEL_OVERRIDE		27

#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */

#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */

#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */

#define   DPIO_PLL_REFCLK_SEL_MASK	3

#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */

#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */

#define _VLV_PLL_DW5_CH1		0x8034

#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)

#define _VLV_PLL_DW7_CH0		0x801c

#define _VLV_PLL_DW7_CH1		0x803c

#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)

#define _VLV_PLL_DW8_CH0		0x8040

#define _VLV_PLL_DW8_CH1		0x8060

#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)

#define VLV_PLL_DW9_BCAST		0xc044

#define _VLV_PLL_DW9_CH0		0x8044

#define _VLV_PLL_DW9_CH1		0x8064

#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)

#define _VLV_PLL_DW10_CH0		0x8048

#define _VLV_PLL_DW10_CH1		0x8068

#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)

#define _VLV_PLL_DW11_CH0		0x804c

#define _VLV_PLL_DW11_CH1		0x806c

#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)

/* Spec for ref block start counts at DW10 */

#define VLV_REF_DW13			0x80ac

#define VLV_CMN_DW0			0x8100

/*

 * Per DDI channel DPIO regs

 */

#define _VLV_PCS_DW0_CH0		0x8200

#define _VLV_PCS_DW0_CH1		0x8400

#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)

#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)

#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)

#define _VLV_PCS01_DW0_CH0		0x200

#define _VLV_PCS23_DW0_CH0		0x400

#define _VLV_PCS01_DW0_CH1		0x2600

#define _VLV_PCS23_DW0_CH1		0x2800

#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)

#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)

#define _VLV_PCS_DW1_CH0		0x8204

#define _VLV_PCS_DW1_CH1		0x8404

#define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)

#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)

#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)

#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)

#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)

#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)

#define _VLV_PCS01_DW1_CH0		0x204

#define _VLV_PCS23_DW1_CH0		0x404

#define _VLV_PCS01_DW1_CH1		0x2604

#define _VLV_PCS23_DW1_CH1		0x2804

#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)

#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)

#define _VLV_PCS_DW8_CH0		0x8220

#define _VLV_PCS_DW8_CH1		0x8420

#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)

#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)

#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)

#define _VLV_PCS01_DW8_CH0		0x0220

#define _VLV_PCS23_DW8_CH0		0x0420

#define _VLV_PCS01_DW8_CH1		0x2620

#define _VLV_PCS23_DW8_CH1		0x2820

#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)

#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)

#define _VLV_PCS_DW9_CH0		0x8224

#define _VLV_PCS_DW9_CH1		0x8424

#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)

#define _CHV_PCS_DW10_CH0		0x8228

#define _CHV_PCS_DW10_CH1		0x8428

#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)

#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)

#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)

#define _VLV_PCS01_DW10_CH0		0x0228

#define _VLV_PCS23_DW10_CH0		0x0428

#define _VLV_PCS01_DW10_CH1		0x2628

#define _VLV_PCS23_DW10_CH1		0x2828

#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)

#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)

#define _VLV_PCS_DW11_CH0		0x822c

#define _VLV_PCS_DW11_CH1		0x842c

#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)

#define _VLV_PCS_DW12_CH0		0x8230

#define _VLV_PCS_DW12_CH1		0x8430

#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)

#define _VLV_PCS_DW14_CH0		0x8238

#define _VLV_PCS_DW14_CH1		0x8438

#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)

#define _VLV_PCS_DW23_CH0		0x825c

#define _VLV_PCS_DW23_CH1		0x845c

#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

#define _VLV_TX_DW2_CH0			0x8288

#define _VLV_TX_DW2_CH1			0x8488

#define   DPIO_SWING_MARGIN_SHIFT	16

#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)

#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8

#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)

#define _VLV_TX_DW3_CH0			0x828c

#define _VLV_TX_DW3_CH1			0x848c

/* The following bit for CHV phy */

#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)

#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)

#define _VLV_TX_DW4_CH0			0x8290

#define _VLV_TX_DW4_CH1			0x8490

#define   DPIO_SWING_DEEMPH9P5_SHIFT	24

#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)

#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)

#define _VLV_TX3_DW4_CH0		0x690

#define _VLV_TX3_DW4_CH1		0x2a90

#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)

#define _VLV_TX_DW5_CH0			0x8294

#define _VLV_TX_DW5_CH1			0x8494

#define   DPIO_TX_OCALINIT_EN		(1<<31)

#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)

#define _VLV_TX_DW11_CH0		0x82ac

#define _VLV_TX_DW11_CH1		0x84ac

#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)

#define _VLV_TX_DW14_CH0		0x82b8

#define _VLV_TX_DW14_CH1		0x84b8

#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)

/* CHV dpPhy registers */

#define _CHV_PLL_DW0_CH0		0x8000

#define _CHV_PLL_DW0_CH1		0x8180

#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)

#define _CHV_PLL_DW1_CH0		0x8004

#define _CHV_PLL_DW1_CH1		0x8184

#define   DPIO_CHV_N_DIV_SHIFT		8

#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)

#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)

#define _CHV_PLL_DW2_CH0		0x8008

#define _CHV_PLL_DW2_CH1		0x8188

#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)

#define _CHV_PLL_DW3_CH0		0x800c

#define _CHV_PLL_DW3_CH1		0x818c

#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)

#define  DPIO_CHV_FIRST_MOD		(0 << 8)

#define  DPIO_CHV_SECOND_MOD		(1 << 8)

#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0

#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)

#define _CHV_PLL_DW6_CH0		0x8018

#define _CHV_PLL_DW6_CH1		0x8198

#define   DPIO_CHV_GAIN_CTRL_SHIFT	16

#define	  DPIO_CHV_INT_COEFF_SHIFT	8

#define   DPIO_CHV_PROP_COEFF_SHIFT	0

#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)

#define _CHV_CMN_DW5_CH0               0x8114

#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)

#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)

#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)

#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)

#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)

#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)

#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)

#define   CHV_BUFLEFTENA1_MASK		(3 << 22)

#define _CHV_CMN_DW13_CH0		0x8134

#define _CHV_CMN_DW0_CH1		0x8080

#define   DPIO_CHV_S1_DIV_SHIFT		21

#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */

#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */

#define   DPIO_CHV_K_DIV_SHIFT		4

#define   DPIO_PLL_FREQLOCK		(1 << 1)

#define   DPIO_PLL_LOCK			(1 << 0)

#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)

#define _CHV_CMN_DW14_CH0		0x8138

#define _CHV_CMN_DW1_CH1		0x8084

#define   DPIO_AFC_RECAL		(1 << 14)

#define   DPIO_DCLKP_EN			(1 << 13)

#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */

#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */

#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */

#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */

#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */

#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */

#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */

#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */

#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)

#define _CHV_CMN_DW19_CH0		0x814c

#define _CHV_CMN_DW6_CH1		0x8098

#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)

#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)

#define CHV_CMN_DW30			0x8178

#define   DPIO_LRC_BYPASS		(1 << 3)

#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \

					(lane) * 0x200 + (offset))

#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)

#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)

#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)

#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)

#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)

#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)

#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)

#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)

#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)

#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)

#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)

#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)

#define   DPIO_FRC_LATENCY_SHFIT	8

#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)

#define   DPIO_UPAR_SHIFT		30

/*

 * Fence registers

 */

#define FENCE_REG_830_0			0x2000

#define FENCE_REG_945_8			0x3000

#define   I830_FENCE_START_MASK		0x07f80000

#define   I830_FENCE_TILING_Y_SHIFT	12

#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)

#define   I830_FENCE_PITCH_SHIFT	4

#define   I830_FENCE_REG_VALID		(1<<0)

#define   I915_FENCE_MAX_PITCH_VAL	4

#define   I830_FENCE_MAX_PITCH_VAL	6

#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)

#define   I915_FENCE_START_MASK		0x0ff00000

#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)

#define FENCE_REG_965_0			0x03000

#define   I965_FENCE_PITCH_SHIFT	2

#define   I965_FENCE_TILING_Y_SHIFT	1

#define   I965_FENCE_REG_VALID		(1<<0)

#define   I965_FENCE_MAX_PITCH_VAL	0x0400

#define FENCE_REG_SANDYBRIDGE_0		0x100000

#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32

#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800

/* control register for cpu gtt access */

#define TILECTL				0x101000

#define   TILECTL_SWZCTL			(1 << 0)

#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)

#define   TILECTL_BACKSNOOP_DIS		(1 << 3)

/*

 * Instruction and interrupt control regs

 */

#define PGTBL_CTL	0x02020

#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */

#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */

#define PGTBL_ER	0x02024

#define RENDER_RING_BASE	0x02000

#define BSD_RING_BASE		0x04000

#define GEN6_BSD_RING_BASE	0x12000

#define GEN8_BSD2_RING_BASE	0x1c000

#define VEBOX_RING_BASE		0x1a000

#define BLT_RING_BASE		0x22000

#define RING_TAIL(base)		((base)+0x30)

#define RING_HEAD(base)		((base)+0x34)

#define RING_START(base)	((base)+0x38)

#define RING_CTL(base)		((base)+0x3c)

#define RING_SYNC_0(base)	((base)+0x40)

#define RING_SYNC_1(base)	((base)+0x44)

#define RING_SYNC_2(base)	((base)+0x48)

#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))

#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))

#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))

#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))

#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))

#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))

#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))

#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))

#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))

#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))

#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))

#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))

#define GEN6_NOSYNC 0

#define RING_MAX_IDLE(base)	((base)+0x54)

#define RING_HWS_PGA(base)	((base)+0x80)

#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)

#define GEN7_WR_WATERMARK	0x4028

#define GEN7_GFX_PRIO_CTRL	0x402C

#define ARB_MODE		0x4030

#define   ARB_MODE_SWIZZLE_SNB	(1<<4)

#define   ARB_MODE_SWIZZLE_IVB	(1<<5)

#define GEN7_GFX_PEND_TLB0	0x4034

#define GEN7_GFX_PEND_TLB1	0x4038

/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */

#define GEN7_LRA_LIMITS_BASE	0x403C

#define GEN7_LRA_LIMITS_REG_NUM	13

#define GEN7_MEDIA_MAX_REQ_COUNT	0x4070

#define GEN7_GFX_MAX_REQ_COUNT		0x4074

#define GAMTARBMODE		0x04a08

#define   ARB_MODE_BWGTLB_DISABLE (1<<9)

#define   ARB_MODE_SWIZZLE_BDW	(1<<1)

#define RENDER_HWS_PGA_GEN7	(0x04080)

#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)

#define   RING_FAULT_GTTSEL_MASK (1<<11)

#define   RING_FAULT_SRCID(x)	((x >> 3) & 0xff)

#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)

#define   RING_FAULT_VALID	(1<<0)

#define DONE_REG		0x40b0

#define GEN8_PRIVATE_PAT	0x40e0

#define BSD_HWS_PGA_GEN7	(0x04180)

#define BLT_HWS_PGA_GEN7	(0x04280)

#define VEBOX_HWS_PGA_GEN7	(0x04380)

#define RING_ACTHD(base)	((base)+0x74)

#define RING_ACTHD_UDW(base)	((base)+0x5c)

#define RING_NOPID(base)	((base)+0x94)

#define RING_IMR(base)		((base)+0xa8)

#define RING_TIMESTAMP(base)	((base)+0x358)

#define   TAIL_ADDR		0x001FFFF8

#define   HEAD_WRAP_COUNT	0xFFE00000

#define   HEAD_WRAP_ONE		0x00200000

#define   HEAD_ADDR		0x001FFFFC

#define   RING_NR_PAGES		0x001FF000

#define   RING_REPORT_MASK	0x00000006

#define   RING_REPORT_64K	0x00000002

#define   RING_REPORT_128K	0x00000004

#define   RING_NO_REPORT	0x00000000

#define   RING_VALID_MASK	0x00000001

#define   RING_VALID		0x00000001

#define   RING_INVALID		0x00000000

#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */

#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */

#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */

#define GEN7_TLB_RD_ADDR	0x4700

#if 0

#define PRB0_TAIL	0x02030

#define PRB0_HEAD	0x02034

#define PRB0_START	0x02038

#define PRB0_CTL	0x0203c

#define PRB1_TAIL	0x02040 /* 915+ only */

#define PRB1_HEAD	0x02044 /* 915+ only */

#define PRB1_START	0x02048 /* 915+ only */

#define PRB1_CTL	0x0204c /* 915+ only */

#endif

#define IPEIR_I965	0x02064

#define IPEHR_I965	0x02068

#define INSTDONE_I965	0x0206c

#define GEN7_INSTDONE_1		0x0206c