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/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _I915_REG_H_

#define _I915_REG_H_

#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))

#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))

#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))

#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)

/* PCI config space */

#define HPLLCC	0xc0 /* 855 only */

#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)

#define   GC_CLOCK_133_200		(0 << 0)

#define   GC_CLOCK_100_200		(1 << 0)

#define   GC_CLOCK_100_133		(2 << 0)

#define   GC_CLOCK_166_250		(3 << 0)

#define GCFGC2	0xda

#define GCFGC	0xf0 /* 915+ only */

#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)

#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)

#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)

#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)

#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)

#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)

#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)

#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)

#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)

#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)

#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)

#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)

#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)

#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)

#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)

#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)

#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)

#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)

#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)

#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)

#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)

#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)

#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)

#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)

#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)

#define LBB	0xf4

/* Graphics reset regs */

#define I965_GDRST 0xc0 /* PCI config register */

#define ILK_GDSR 0x2ca4 /* MCHBAR offset */

#define  GRDOM_FULL	(0<<2)

#define  GRDOM_RENDER	(1<<2)

#define  GRDOM_MEDIA	(3<<2)

#define  GRDOM_MASK	(3<<2)

#define  GRDOM_RESET_ENABLE (1<<0)

#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */

#define   GEN6_MBC_SNPCR_SHIFT	21

#define   GEN6_MBC_SNPCR_MASK	(3<<21)

#define   GEN6_MBC_SNPCR_MAX	(0<<21)

#define   GEN6_MBC_SNPCR_MED	(1<<21)

#define   GEN6_MBC_SNPCR_LOW	(2<<21)

#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */

#define GEN6_MBCTL		0x0907c

#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)

#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)

#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)

#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)

#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)

#define GEN6_GDRST	0x941c

#define  GEN6_GRDOM_FULL		(1 << 0)

#define  GEN6_GRDOM_RENDER		(1 << 1)

#define  GEN6_GRDOM_MEDIA		(1 << 2)

#define  GEN6_GRDOM_BLT			(1 << 3)

#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)

#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)

#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)

#define   PP_DIR_DCLV_2G		0xffffffff

#define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))

#define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)

#define GAM_ECOCHK			0x4090

#define   ECOCHK_SNB_BIT		(1<<10)

#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)

#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)

#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)

#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)

#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)

#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)

#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)

#define GAC_ECO_BITS			0x14090

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)

#define   ECOBITS_PPGTT_CACHE4B		(0<<8)

#define GAB_CTL				0x24000

#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)

/* VGA stuff */

#define VGA_ST01_MDA 0x3ba

#define VGA_ST01_CGA 0x3da

#define VGA_MSR_WRITE 0x3c2

#define VGA_MSR_READ 0x3cc

#define   VGA_MSR_MEM_EN (1<<1)

#define   VGA_MSR_CGA_MODE (1<<0)

#define VGA_SR_INDEX 0x3c4

#define SR01			1

#define VGA_SR_DATA 0x3c5

#define VGA_AR_INDEX 0x3c0

#define   VGA_AR_VID_EN (1<<5)

#define VGA_AR_DATA_WRITE 0x3c0

#define VGA_AR_DATA_READ 0x3c1

#define VGA_GR_INDEX 0x3ce

#define VGA_GR_DATA 0x3cf

/* GR05 */

#define   VGA_GR_MEM_READ_MODE_SHIFT 3

#define     VGA_GR_MEM_READ_MODE_PLANE 1

/* GR06 */

#define   VGA_GR_MEM_MODE_MASK 0xc

#define   VGA_GR_MEM_MODE_SHIFT 2

#define   VGA_GR_MEM_A0000_AFFFF 0

#define   VGA_GR_MEM_A0000_BFFFF 1

#define   VGA_GR_MEM_B0000_B7FFF 2

#define   VGA_GR_MEM_B0000_BFFFF 3

#define VGA_DACMASK 0x3c6

#define VGA_DACRX 0x3c7

#define VGA_DACWX 0x3c8

#define VGA_DACDATA 0x3c9

#define VGA_CR_INDEX_MDA 0x3b4

#define VGA_CR_DATA_MDA 0x3b5

#define VGA_CR_INDEX_CGA 0x3d4

#define VGA_CR_DATA_CGA 0x3d5

/*

 * Memory interface instructions used by the kernel

 */

#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))

#define MI_NOOP			MI_INSTR(0, 0)

#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)

#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)

#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)

#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)

#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)

#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

#define MI_FLUSH		MI_INSTR(0x04, 0)

#define   MI_READ_FLUSH		(1 << 0)

#define   MI_EXE_FLUSH		(1 << 1)

#define   MI_NO_WRITE_FLUSH	(1 << 2)

#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)

#define   MI_ARB_ENABLE			(1<<0)

#define   MI_ARB_DISABLE		(0<<0)

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)

#define   MI_SUSPEND_FLUSH_EN	(1<<0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)

#define   MI_OVERLAY_CONTINUE	(0x0<<21)

#define   MI_OVERLAY_ON		(0x1<<21)

#define   MI_OVERLAY_OFF	(0x2<<21)

#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)

#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)

#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)

#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)

/* IVB has funny definitions for which plane to flip. */

#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)

#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)

#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)

#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */

#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)

#define   MI_SEMAPHORE_UPDATE	    (1<<21)

#define   MI_SEMAPHORE_COMPARE	    (1<<20)

#define   MI_SEMAPHORE_REGISTER	    (1<<18)

#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */

#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */

#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */

#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */

#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */

#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */

#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */

#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */

#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */

#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */

#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define   MI_SEMAPHORE_SYNC_INVALID  (3<<16)

#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)

#define   MI_MM_SPACE_GTT		(1<<8)

#define   MI_MM_SPACE_PHYSICAL		(0<<8)

#define   MI_SAVE_EXT_STATE_EN		(1<<3)

#define   MI_RESTORE_EXT_STATE_EN	(1<<2)

#define   MI_FORCE_RESTORE		(1<<1)

#define   MI_RESTORE_INHIBIT		(1<<0)

#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)

#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */

#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)

#define   MI_STORE_DWORD_INDEX_SHIFT 2

/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:

 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw

 *   simply ignores the register load under certain conditions.

 * - One can actually load arbitrary many arbitrary registers: Simply issue x

 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!

 */

#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)

#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)

#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)

#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */

#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)

#define   MI_INVALIDATE_TLB	(1<<18)

#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)

#define   MI_INVALIDATE_BSD	(1<<7)

#define   MI_FLUSH_DW_USE_GTT		(1<<2)

#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)

#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)

#define   MI_BATCH_NON_SECURE	(1)

/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */

#define   MI_BATCH_NON_SECURE_I965 (1<<8)

#define   MI_BATCH_PPGTT_HSW		(1<<8)

#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)

#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)

#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */

#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)

#define MI_PREDICATE_RESULT_2	(0x2214)

#define  LOWER_SLICE_ENABLED	(1<<0)

#define  LOWER_SLICE_DISABLED	(0<<0)

/*

 * 3D instructions used by the kernel

 */

#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))

#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))

#define   SC_UPDATE_SCISSOR       (0x1<<1)

#define   SC_ENABLE_MASK          (0x1<<0)

#define   SC_ENABLE               (0x1<<0)

#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))

#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

#define   SCI_YMIN_MASK      (0xffff<<16)

#define   SCI_XMIN_MASK      (0xffff<<0)

#define   SCI_YMAX_MASK      (0xffff<<16)

#define   SCI_XMAX_MASK      (0xffff<<0)

#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))

#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))

#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)

#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)

#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)

#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)

#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)

#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)

#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)

#define   BLT_DEPTH_8			(0<<24)

#define   BLT_DEPTH_16_565		(1<<24)

#define   BLT_DEPTH_16_1555		(2<<24)

#define   BLT_DEPTH_32			(3<<24)

#define   BLT_ROP_GXCOPY		(0xcc<<16)

#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */

#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */

#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

#define   ASYNC_FLIP                (1<<22)

#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

#define   PIPE_CONTROL_CS_STALL				(1<<20)

#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)

#define   PIPE_CONTROL_QW_WRITE	(1<<14)

#define   PIPE_CONTROL_DEPTH_STALL (1<<13)

#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)

#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */

#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_NOTIFY	(1<<8)

#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)

#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)

#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)

#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)

#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)

#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

/*

 * Reset registers

 */

#define DEBUG_RESET_I830		0x6070

#define  DEBUG_RESET_FULL		(1<<7)

#define  DEBUG_RESET_RENDER		(1<<8)

#define  DEBUG_RESET_DISPLAY		(1<<9)

/*

 * IOSF sideband

 */

#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)

#define   IOSF_DEVFN_SHIFT			24

#define   IOSF_OPCODE_SHIFT			16

#define   IOSF_PORT_SHIFT			8

#define   IOSF_BYTE_ENABLES_SHIFT		4

#define   IOSF_BAR_SHIFT			1

#define   IOSF_SB_BUSY				(1<<0)

#define   IOSF_PORT_BUNIT			0x3

#define   IOSF_PORT_PUNIT			0x4

#define   IOSF_PORT_NC				0x11

#define   IOSF_PORT_DPIO			0x12

#define   IOSF_PORT_GPIO_NC			0x13

#define   IOSF_PORT_CCK				0x14

#define   IOSF_PORT_CCU				0xA9

#define   IOSF_PORT_GPS_CORE			0x48

#define   IOSF_PORT_FLISDSI			0x1B

#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)

#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)

/* See configdb bunit SB addr map */

#define BUNIT_REG_BISOC				0x11

#define PUNIT_OPCODE_REG_READ			6

#define PUNIT_OPCODE_REG_WRITE			7

#define PUNIT_REG_DSPFREQ			0x36

#define   DSPFREQSTAT_SHIFT			30

#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)

#define   DSPFREQGUAR_SHIFT			14

#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)

#define PUNIT_REG_PWRGT_CTRL			0x60

#define PUNIT_REG_PWRGT_STATUS			0x61

#define	  PUNIT_CLK_GATE			1

#define	  PUNIT_PWR_RESET			2

#define	  PUNIT_PWR_GATE			3

#define	  RENDER_PWRGT				(PUNIT_PWR_GATE << 0)

#define	  MEDIA_PWRGT				(PUNIT_PWR_GATE << 2)

#define	  DISP2D_PWRGT				(PUNIT_PWR_GATE << 6)

#define PUNIT_REG_GPU_LFM			0xd3

#define PUNIT_REG_GPU_FREQ_REQ			0xd4

#define PUNIT_REG_GPU_FREQ_STS			0xd8

#define   GENFREQSTATUS				(1<<0)

#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc

#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */

#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c

#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3

#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800

#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34

#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007

#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30

#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27

#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000

/* vlv2 north clock has */

#define CCK_FUSE_REG				0x8

#define  CCK_FUSE_HPLL_FREQ_MASK		0x3

#define CCK_REG_DSI_PLL_FUSE			0x44

#define CCK_REG_DSI_PLL_CONTROL			0x48

#define  DSI_PLL_VCO_EN				(1 << 31)

#define  DSI_PLL_LDO_GATE			(1 << 30)

#define  DSI_PLL_P1_POST_DIV_SHIFT		17

#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)

#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)

#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)

#define  DSI_PLL_MUX_MASK			(3 << 9)

#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)

#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)

#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)

#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)

#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)

#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)

#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)

#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)

#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)

#define  DSI_PLL_LOCK				(1 << 0)

#define CCK_REG_DSI_PLL_DIVIDER			0x4c

#define  DSI_PLL_LFSR				(1 << 31)

#define  DSI_PLL_FRACTION_EN			(1 << 30)

#define  DSI_PLL_FRAC_COUNTER_SHIFT		27

#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)

#define  DSI_PLL_USYNC_CNT_SHIFT		18

#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)

#define  DSI_PLL_N1_DIV_SHIFT			16

#define  DSI_PLL_N1_DIV_MASK			(3 << 16)

#define  DSI_PLL_M1_DIV_SHIFT			0

#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)

#define CCK_DISPLAY_CLOCK_CONTROL		0x6b

/*

 * DPIO - a special bus for various display related registers to hide behind

 *

 * DPIO is VLV only.

 *

 * Note: digital port B is DDI0, digital pot C is DDI1

 */

#define DPIO_DEVFN			0

#define DPIO_OPCODE_REG_WRITE		1

#define DPIO_OPCODE_REG_READ		0

#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)

#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */

#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */

#define  DPIO_SFR_BYPASS		(1<<1)

#define  DPIO_CMNRST			(1<<0)

#define DPIO_PHY(pipe)			((pipe) >> 1)

#define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])

/*

 * Per pipe/PLL DPIO regs

 */

#define _VLV_PLL_DW3_CH0		0x800c

#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */

#define   DPIO_POST_DIV_DAC		0

#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */

#define   DPIO_POST_DIV_LVDS1		2

#define   DPIO_POST_DIV_LVDS2		3

#define   DPIO_K_SHIFT			(24) /* 4 bits */

#define   DPIO_P1_SHIFT			(21) /* 3 bits */

#define   DPIO_P2_SHIFT			(16) /* 5 bits */

#define   DPIO_N_SHIFT			(12) /* 4 bits */

#define   DPIO_ENABLE_CALIBRATION	(1<<11)

#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */

#define   DPIO_M2DIV_MASK		0xff

#define _VLV_PLL_DW3_CH1		0x802c

#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)

#define _VLV_PLL_DW5_CH0		0x8014

#define   DPIO_REFSEL_OVERRIDE		27

#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */

#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */

#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */

#define   DPIO_PLL_REFCLK_SEL_MASK	3

#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */

#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */

#define _VLV_PLL_DW5_CH1		0x8034

#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)

#define _VLV_PLL_DW7_CH0		0x801c

#define _VLV_PLL_DW7_CH1		0x803c

#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)

#define _VLV_PLL_DW8_CH0		0x8040

#define _VLV_PLL_DW8_CH1		0x8060

#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)

#define VLV_PLL_DW9_BCAST		0xc044

#define _VLV_PLL_DW9_CH0		0x8044

#define _VLV_PLL_DW9_CH1		0x8064

#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)

#define _VLV_PLL_DW10_CH0		0x8048

#define _VLV_PLL_DW10_CH1		0x8068

#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)

#define _VLV_PLL_DW11_CH0		0x804c

#define _VLV_PLL_DW11_CH1		0x806c

#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)

/* Spec for ref block start counts at DW10 */

#define VLV_REF_DW13			0x80ac

#define VLV_CMN_DW0			0x8100

/*

 * Per DDI channel DPIO regs

 */

#define _VLV_PCS_DW0_CH0		0x8200

#define _VLV_PCS_DW0_CH1		0x8400

#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)

#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)

#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)

#define _VLV_PCS_DW1_CH0		0x8204

#define _VLV_PCS_DW1_CH1		0x8404

#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)

#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)

#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)

#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)

#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)

#define _VLV_PCS_DW8_CH0		0x8220

#define _VLV_PCS_DW8_CH1		0x8420

#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)

#define _VLV_PCS01_DW8_CH0		0x0220

#define _VLV_PCS23_DW8_CH0		0x0420

#define _VLV_PCS01_DW8_CH1		0x2620

#define _VLV_PCS23_DW8_CH1		0x2820

#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)

#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)

#define _VLV_PCS_DW9_CH0		0x8224

#define _VLV_PCS_DW9_CH1		0x8424

#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)

#define _VLV_PCS_DW11_CH0		0x822c

#define _VLV_PCS_DW11_CH1		0x842c

#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)

#define _VLV_PCS_DW12_CH0		0x8230

#define _VLV_PCS_DW12_CH1		0x8430

#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)

#define _VLV_PCS_DW14_CH0		0x8238

#define _VLV_PCS_DW14_CH1		0x8438

#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)

#define _VLV_PCS_DW23_CH0		0x825c

#define _VLV_PCS_DW23_CH1		0x845c

#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

#define _VLV_TX_DW2_CH0			0x8288

#define _VLV_TX_DW2_CH1			0x8488

#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)

#define _VLV_TX_DW3_CH0			0x828c

#define _VLV_TX_DW3_CH1			0x848c

#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)

#define _VLV_TX_DW4_CH0			0x8290

#define _VLV_TX_DW4_CH1			0x8490

#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)

#define _VLV_TX3_DW4_CH0		0x690

#define _VLV_TX3_DW4_CH1		0x2a90

#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)

#define _VLV_TX_DW5_CH0			0x8294

#define _VLV_TX_DW5_CH1			0x8494

#define   DPIO_TX_OCALINIT_EN		(1<<31)

#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)

#define _VLV_TX_DW11_CH0		0x82ac

#define _VLV_TX_DW11_CH1		0x84ac

#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)

#define _VLV_TX_DW14_CH0		0x82b8

#define _VLV_TX_DW14_CH1		0x84b8

#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)

/*

 * Fence registers

 */

#define FENCE_REG_830_0			0x2000

#define FENCE_REG_945_8			0x3000

#define   I830_FENCE_START_MASK		0x07f80000

#define   I830_FENCE_TILING_Y_SHIFT	12

#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)

#define   I830_FENCE_PITCH_SHIFT	4

#define   I830_FENCE_REG_VALID		(1<<0)

#define   I915_FENCE_MAX_PITCH_VAL	4

#define   I830_FENCE_MAX_PITCH_VAL	6

#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)

#define   I915_FENCE_START_MASK		0x0ff00000

#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)

#define FENCE_REG_965_0			0x03000

#define   I965_FENCE_PITCH_SHIFT	2

#define   I965_FENCE_TILING_Y_SHIFT	1

#define   I965_FENCE_REG_VALID		(1<<0)

#define   I965_FENCE_MAX_PITCH_VAL	0x0400

#define FENCE_REG_SANDYBRIDGE_0		0x100000

#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32

#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800

/* control register for cpu gtt access */

#define TILECTL				0x101000

#define   TILECTL_SWZCTL			(1 << 0)

#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)

#define   TILECTL_BACKSNOOP_DIS		(1 << 3)

/*

 * Instruction and interrupt control regs

 */

#define PGTBL_ER	0x02024

#define RENDER_RING_BASE	0x02000

#define BSD_RING_BASE		0x04000

#define GEN6_BSD_RING_BASE	0x12000

#define VEBOX_RING_BASE		0x1a000

#define BLT_RING_BASE		0x22000

#define RING_TAIL(base)		((base)+0x30)

#define RING_HEAD(base)		((base)+0x34)

#define RING_START(base)	((base)+0x38)

#define RING_CTL(base)		((base)+0x3c)

#define RING_SYNC_0(base)	((base)+0x40)

#define RING_SYNC_1(base)	((base)+0x44)

#define RING_SYNC_2(base)	((base)+0x48)

#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))

#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))

#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))

#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))

#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))

#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))

#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))

#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))

#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))

#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))

#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))

#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))

#define GEN6_NOSYNC 0

#define RING_MAX_IDLE(base)	((base)+0x54)

#define RING_HWS_PGA(base)	((base)+0x80)

#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)

#define ARB_MODE		0x04030

#define   ARB_MODE_SWIZZLE_SNB	(1<<4)

#define   ARB_MODE_SWIZZLE_IVB	(1<<5)

#define GAMTARBMODE		0x04a08

#define   ARB_MODE_BWGTLB_DISABLE (1<<9)

#define   ARB_MODE_SWIZZLE_BDW	(1<<1)

#define RENDER_HWS_PGA_GEN7	(0x04080)

#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)

#define   RING_FAULT_GTTSEL_MASK (1<<11)

#define   RING_FAULT_SRCID(x)	((x >> 3) & 0xff)

#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)

#define   RING_FAULT_VALID	(1<<0)

#define DONE_REG		0x40b0

#define GEN8_PRIVATE_PAT	0x40e0

#define BSD_HWS_PGA_GEN7	(0x04180)

#define BLT_HWS_PGA_GEN7	(0x04280)

#define VEBOX_HWS_PGA_GEN7	(0x04380)

#define RING_ACTHD(base)	((base)+0x74)

#define RING_NOPID(base)	((base)+0x94)

#define RING_IMR(base)		((base)+0xa8)

#define RING_TIMESTAMP(base)	((base)+0x358)

#define   TAIL_ADDR		0x001FFFF8

#define   HEAD_WRAP_COUNT	0xFFE00000

#define   HEAD_WRAP_ONE		0x00200000

#define   HEAD_ADDR		0x001FFFFC

#define   RING_NR_PAGES		0x001FF000

#define   RING_REPORT_MASK	0x00000006

#define   RING_REPORT_64K	0x00000002

#define   RING_REPORT_128K	0x00000004

#define   RING_NO_REPORT	0x00000000

#define   RING_VALID_MASK	0x00000001

#define   RING_VALID		0x00000001

#define   RING_INVALID		0x00000000

#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */

#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */

#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */

#if 0

#define PRB0_TAIL	0x02030

#define PRB0_HEAD	0x02034

#define PRB0_START	0x02038

#define PRB0_CTL	0x0203c

#define PRB1_TAIL	0x02040 /* 915+ only */

#define PRB1_HEAD	0x02044 /* 915+ only */

#define PRB1_START	0x02048 /* 915+ only */

#define PRB1_CTL	0x0204c /* 915+ only */

#endif

#define IPEIR_I965	0x02064

#define IPEHR_I965	0x02068

#define INSTDONE_I965	0x0206c

#define GEN7_INSTDONE_1		0x0206c

#define GEN7_SC_INSTDONE	0x07100

#define GEN7_SAMPLER_INSTDONE	0x0e160

#define GEN7_ROW_INSTDONE	0x0e164

#define I915_NUM_INSTDONE_REG	4

#define RING_IPEIR(base)	((base)+0x64)

#define RING_IPEHR(base)	((base)+0x68)

#define RING_INSTDONE(base)	((base)+0x6c)

#define RING_INSTPS(base)	((base)+0x70)

#define RING_DMA_FADD(base)	((base)+0x78)

#define RING_INSTPM(base)	((base)+0xc0)

#define INSTPS		0x02070 /* 965+ only */

#define INSTDONE1	0x0207c /* 965+ only */

#define ACTHD_I965	0x02074

#define HWS_PGA		0x02080

#define HWS_ADDRESS_MASK	0xfffff000

#define HWS_START_ADDRESS_SHIFT	4

#define PWRCTXA		0x2088 /* 965GM+ only */

#define   PWRCTX_EN	(1<<0)

#define IPEIR		0x02088

#define IPEHR		0x0208c

#define INSTDONE	0x02090

#define NOPID		0x02094

#define HWSTAM		0x02098

#define DMA_FADD_I8XX	0x020d0

#define RING_BBSTATE(base)	((base)+0x110)

#define RING_BBADDR(base)	((base)+0x140)

#define RING_BBADDR_UDW(base)	((base)+0x168) /* gen8+ */

#define ERROR_GEN6	0x040a0

#define GEN7_ERR_INT	0x44040

#define   ERR_INT_POISON		(1<<31)

#define   ERR_INT_MMIO_UNCLAIMED (1<<13)

#define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)

#define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)

#define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)

#define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)

#define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)

#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + pipe*3))

#define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)

#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))

#define FPGA_DBG		0x42300

#define   FPGA_DBG_RM_NOCLAIM	(1<<31)

#define DERRMR		0x44050

/* Note that HBLANK events are reserved on bdw+ */

#define   DERRMR_PIPEA_SCANLINE		(1<<0)

#define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)

#define   DERRMR_PIPEA_SPR_FLIP_DONE	(1<<2)

#define   DERRMR_PIPEA_VBLANK		(1<<3)

#define   DERRMR_PIPEA_HBLANK		(1<<5)

#define   DERRMR_PIPEB_SCANLINE 	(1<<8)

#define   DERRMR_PIPEB_PRI_FLIP_DONE	(1<<9)

#define   DERRMR_PIPEB_SPR_FLIP_DONE	(1<<10)

#define   DERRMR_PIPEB_VBLANK		(1<<11)

#define   DERRMR_PIPEB_HBLANK		(1<<13)

/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */

#define   DERRMR_PIPEC_SCANLINE		(1<<14)

#define   DERRMR_PIPEC_PRI_FLIP_DONE	(1<<15)

#define   DERRMR_PIPEC_SPR_FLIP_DONE	(1<<20)

#define   DERRMR_PIPEC_VBLANK		(1<<21)

#define   DERRMR_PIPEC_HBLANK		(1<<22)

/* GM45+ chicken bits -- debug workaround bits that may be required

 * for various sorts of correct behavior.  The top 16 bits of each are

 * the enables for writing to the corresponding low bit.

 */

#define _3D_CHICKEN	0x02084

#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)

#define _3D_CHICKEN2	0x0208c

/* Disables pipelining of read flushes past the SF-WIZ interface.

 * Required on all Ironlake steppings according to the B-Spec, but the

 * particular danger of not doing so is not specified.

 */

# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)

#define _3D_CHICKEN3	0x02090

#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)

#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)

#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1)

#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

# define MI_FLUSH_ENABLE				(1 << 12)

# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)

#define GEN6_GT_MODE	0x20d0

#define   GEN6_GT_MODE_HI	(1 << 9)

#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)

#define GFX_MODE	0x02520

#define GFX_MODE_GEN7	0x0229c

#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)

#define   GFX_RUN_LIST_ENABLE		(1<<15)

#define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)

#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)

#define   GFX_REPLAY_MODE		(1<<11)

#define   GFX_PSMI_GRANULARITY		(1<<10)

#define   GFX_PPGTT_ENABLE		(1<<9)

#define VLV_DISPLAY_BASE 0x180000

#define SCPD0		0x0209c /* 915+ only */

#define IER		0x020a0

#define IIR		0x020a4

#define IMR		0x020a8

#define ISR		0x020ac

#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)

#define   GCFG_DIS		(1<<8)

#define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)

#define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)

#define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)

#define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)

#define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)

#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)

#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */

#define EIR		0x020b0

#define EMR		0x020b4

#define ESR		0x020b8

#define   GM45_ERROR_PAGE_TABLE				(1<<5)

#define   GM45_ERROR_MEM_PRIV				(1<<4)

#define   I915_ERROR_PAGE_TABLE				(1<<4)

#define   GM45_ERROR_CP_PRIV				(1<<3)

#define   I915_ERROR_MEMORY_REFRESH			(1<<1)

#define   I915_ERROR_INSTRUCTION			(1<<0)

#define INSTPM	        0x020c0

#define   INSTPM_SELF_EN (1<<12) /* 915GM only */

#define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts

					will not assert AGPBUSY# and will only

					be delivered when out of C3. */

#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */

#define   INSTPM_TLB_INVALIDATE	(1<<9)

#define   INSTPM_SYNC_FLUSH	(1<<5)

#define ACTHD	        0x020c8

#define FW_BLC		0x020d8

#define FW_BLC2		0x020dc

#define FW_BLC_SELF	0x020e0 /* 915+ only */

#define   FW_BLC_SELF_EN_MASK      (1<<31)

#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */

#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */

#define MM_BURST_LENGTH     0x00700000

#define MM_FIFO_WATERMARK   0x0001F000

#define LM_BURST_LENGTH     0x00000700

#define LM_FIFO_WATERMARK   0x0000001F

#define MI_ARB_STATE	0x020e4 /* 915+ only */

/* Make render/texture TLB fetches lower priorty than associated data

 *   fetches. This is not turned on by default

 */

#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)

/* Isoch request wait on GTT enable (Display A/B/C streams).

 * Make isoch requests stall on the TLB update. May cause

 * display underruns (test mode only)

 */

#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)

/* Block grant count for isoch requests when block count is

 * set to a finite value.

 */

#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)

#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */

#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */

#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */

#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */

/* Enable render writes to complete in C2/C3/C4 power states.

 * If this isn't enabled, render writes are prevented in low

 * power states. That seems bad to me.

 */

#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)

/* This acknowledges an async flip immediately instead

 * of waiting for 2TLB fetches.

 */

#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)

/* Enables non-sequential data reads through arbiter

 */

#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)

/* Disable FSB snooping of cacheable write cycles from binner/render

 * command stream

 */

#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)

/* Arbiter time slice for non-isoch streams */

#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)

#define   MI_ARB_TIME_SLICE_1			(0 << 5)

#define   MI_ARB_TIME_SLICE_2			(1 << 5)

#define   MI_ARB_TIME_SLICE_4			(2 << 5)

#define   MI_ARB_TIME_SLICE_6			(3 << 5)

#define   MI_ARB_TIME_SLICE_8			(4 << 5)

#define   MI_ARB_TIME_SLICE_10			(5 << 5)

#define   MI_ARB_TIME_SLICE_14			(6 << 5)

#define   MI_ARB_TIME_SLICE_16			(7 << 5)

/* Low priority grace period page size */

#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */

#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)

/* Disable display A/B trickle feed */

#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)

/* Set display plane priority */

#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */

#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */

#define CACHE_MODE_0	0x02120 /* 915+ only */

#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)

#define   CM0_IZ_OPT_DISABLE      (1<<6)

#define   CM0_ZR_OPT_DISABLE      (1<<5)

#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)

#define   CM0_DEPTH_EVICT_DISABLE (1<<4)

#define   CM0_COLOR_EVICT_DISABLE (1<<3)

#define   CM0_DEPTH_WRITE_DISABLE (1<<1)

#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)

#define GFX_FLSH_CNTL	0x02170 /* 915+ only */

#define GFX_FLSH_CNTL_GEN6	0x101008

#define   GFX_FLSH_CNTL_EN	(1<<0)

#define ECOSKPD		0x021d0

#define   ECO_GATING_CX_ONLY	(1<<3)

#define   ECO_FLIP_DONE		(1<<0)

#define CACHE_MODE_1		0x7004 /* IVB+ */

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)

#define GEN6_BLITTER_ECOSKPD	0x221d0

#define   GEN6_BLITTER_LOCK_SHIFT			16

#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)

#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050

#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)

#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)

#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)

#define   GEN6_BSD_GO_INDICATOR		(1 << 4)

/* On modern GEN architectures interrupt control consists of two sets

 * of registers. The first set pertains to the ring generating the

 * interrupt. The second control is for the functional block generating the

 * interrupt. These are PM, GT, DE, etc.

 *

 * Luckily *knocks on wood* all the ring interrupt bits match up with the

 * GT interrupt bits, so we don't need to duplicate the defines.

 *

 * These defines should cover us well from SNB->HSW with minor exceptions

 * it can also work on ILK.

 */

#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)

#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)

#define GT_BLT_USER_INTERRUPT			(1 << 22)

#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)

#define GT_BSD_USER_INTERRUPT			(1 << 12)

#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */

#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */

#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)

#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)

#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)

#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)

#define GT_RENDER_USER_INTERRUPT		(1 <<  0)

#define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */

#define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */

#define GT_PARITY_ERROR(dev) \

	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \

	 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))

/* These are all the "old" interrupts */

#define ILK_BSD_USER_INTERRUPT				(1<<5)

#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)

#define I915_DISPLAY_PORT_INTERRUPT			(1<<17)

#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)

#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */

#define I915_HWB_OOM_INTERRUPT				(1<<13)

#define I915_SYNC_STATUS_INTERRUPT			(1<<12)

#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)

#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)

#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)

#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)

#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)

#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)

#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)

#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)

#define I915_DEBUG_INTERRUPT				(1<<2)

#define I915_USER_INTERRUPT				(1<<1)

#define I915_ASLE_INTERRUPT				(1<<0)

#define I915_BSD_USER_INTERRUPT				(1 << 25)

#define GEN6_BSD_RNCID			0x12198

#define GEN7_FF_THREAD_MODE		0x20a0

#define   GEN7_FF_SCHED_MASK		0x0077070

#define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)

#define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)

#define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)

#define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)

#define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */

#define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)

#define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)

#define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)

#define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */

#define   GEN7_FF_VS_SCHED_HW		(0x0<<12)

#define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)

#define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)

#define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */

#define   GEN7_FF_DS_SCHED_HW		(0x0<<4)

/*

 * Framebuffer compression (915+ only)

 */

#define FBC_CFB_BASE		0x03200 /* 4k page aligned */

#define FBC_LL_BASE		0x03204 /* 4k page aligned */

#define FBC_CONTROL		0x03208

#define   FBC_CTL_EN		(1<<31)

#define   FBC_CTL_PERIODIC	(1<<30)

#define   FBC_CTL_INTERVAL_SHIFT (16)

#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)

#define   FBC_CTL_C3_IDLE	(1<<13)

#define   FBC_CTL_STRIDE_SHIFT	(5)

#define   FBC_CTL_FENCENO_SHIFT	(0)

#define FBC_COMMAND		0x0320c

#define   FBC_CMD_COMPRESS	(1<<0)

#define FBC_STATUS		0x03210

#define   FBC_STAT_COMPRESSING	(1<<31)

#define   FBC_STAT_COMPRESSED	(1<<30)

#define   FBC_STAT_MODIFIED	(1<<29)

#define   FBC_STAT_CURRENT_LINE_SHIFT	(0)

#define FBC_CONTROL2		0x03214

#define   FBC_CTL_FENCE_DBL	(0<<4)

#define   FBC_CTL_IDLE_IMM	(0<<2)

#define   FBC_CTL_IDLE_FULL	(1<<2)

#define   FBC_CTL_IDLE_LINE	(2<<2)

#define   FBC_CTL_IDLE_DEBUG	(3<<2)

#define   FBC_CTL_CPU_FENCE	(1<<1)

#define   FBC_CTL_PLANEA	(0<<0)

#define   FBC_CTL_PLANEB	(1<<0)

#define FBC_FENCE_OFF		0x0321b

#define FBC_TAG			0x03300

#define FBC_LL_SIZE		(1536)

/* Framebuffer compression for GM45+ */

#define DPFC_CB_BASE		0x3200

#define DPFC_CONTROL		0x3208

#define   DPFC_CTL_EN		(1<<31)

#define   DPFC_CTL_PLANEA	(0<<30)

#define   DPFC_CTL_PLANEB	(1<<30)

#define   IVB_DPFC_CTL_PLANE_SHIFT	(29)

#define   DPFC_CTL_FENCE_EN	(1<<29)

#define   IVB_DPFC_CTL_FENCE_EN	(1<<28)

#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)

#define   DPFC_SR_EN		(1<<10)

#define   DPFC_CTL_LIMIT_1X	(0<<6)

#define   DPFC_CTL_LIMIT_2X	(1<<6)

#define   DPFC_CTL_LIMIT_4X	(2<<6)

#define DPFC_RECOMP_CTL		0x320c

#define   DPFC_RECOMP_STALL_EN	(1<<27)

#define   DPFC_RECOMP_STALL_WM_SHIFT (16)

#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)

#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)

#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)

#define DPFC_STATUS		0x3210

#define   DPFC_INVAL_SEG_SHIFT  (16)

#define   DPFC_INVAL_SEG_MASK	(0x07ff0000)

#define   DPFC_COMP_SEG_SHIFT	(0)

#define   DPFC_COMP_SEG_MASK	(0x000003ff)

#define DPFC_STATUS2		0x3214

#define DPFC_FENCE_YOFF		0x3218

#define DPFC_CHICKEN		0x3224

#define   DPFC_HT_MODIFY	(1<<31)

/* Framebuffer compression for Ironlake */

#define ILK_DPFC_CB_BASE	0x43200

#define ILK_DPFC_CONTROL	0x43208

/* The bit 28-8 is reserved */

#define   DPFC_RESERVED		(0x1FFFFF00)

#define ILK_DPFC_RECOMP_CTL	0x4320c

#define ILK_DPFC_STATUS		0x43210

#define ILK_DPFC_FENCE_YOFF	0x43218