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2326 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
3031 | serge | 28 | #include |
29 | #include |
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30 | #include |
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31 | #include |
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2326 | Serge | 32 | #include "i915_drv.h" |
33 | |||
34 | /** @file i915_gem_tiling.c |
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35 | * |
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36 | * Support for managing tiling state of buffer objects. |
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37 | * |
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38 | * The idea behind tiling is to increase cache hit rates by rearranging |
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39 | * pixel data so that a group of pixel accesses are in the same cacheline. |
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40 | * Performance improvement from doing this on the back/depth buffer are on |
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41 | * the order of 30%. |
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42 | * |
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43 | * Intel architectures make this somewhat more complicated, though, by |
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44 | * adjustments made to addressing of data when the memory is in interleaved |
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45 | * mode (matched pairs of DIMMS) to improve memory bandwidth. |
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46 | * For interleaved memory, the CPU sends every sequential 64 bytes |
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47 | * to an alternate memory channel so it can get the bandwidth from both. |
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48 | * |
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49 | * The GPU also rearranges its accesses for increased bandwidth to interleaved |
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50 | * memory, and it matches what the CPU does for non-tiled. However, when tiled |
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51 | * it does it a little differently, since one walks addresses not just in the |
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52 | * X direction but also Y. So, along with alternating channels when bit |
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53 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 |
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54 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) |
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55 | * are common to both the 915 and 965-class hardware. |
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56 | * |
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57 | * The CPU also sometimes XORs in higher bits as well, to improve |
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58 | * bandwidth doing strided access like we do so frequently in graphics. This |
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59 | * is called "Channel XOR Randomization" in the MCH documentation. The result |
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60 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address |
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61 | * decode. |
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62 | * |
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63 | * All of this bit 6 XORing has an effect on our memory management, |
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64 | * as we need to make sure that the 3d driver can correctly address object |
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65 | * contents. |
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66 | * |
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67 | * If we don't have interleaved memory, all tiling is safe and no swizzling is |
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68 | * required. |
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69 | * |
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70 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit |
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71 | * 17 is not just a page offset, so as we page an objet out and back in, |
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72 | * individual pages in it will have different bit 17 addresses, resulting in |
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73 | * each 64 bytes being swapped with its neighbor! |
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74 | * |
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75 | * Otherwise, if interleaved, we have to tell the 3d driver what the address |
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76 | * swizzling it needs to do is, since it's writing with the CPU to the pages |
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77 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the |
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78 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
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79 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
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80 | * to match what the GPU expects. |
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81 | */ |
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82 | |||
83 | #define I915_TILING_NONE 0 |
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84 | #define I915_TILING_X 1 |
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85 | #define I915_TILING_Y 2 |
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86 | |||
87 | #define I915_BIT_6_SWIZZLE_NONE 0 |
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88 | #define I915_BIT_6_SWIZZLE_9 1 |
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89 | #define I915_BIT_6_SWIZZLE_9_10 2 |
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90 | #define I915_BIT_6_SWIZZLE_9_11 3 |
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91 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
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92 | /* Not seen by userland */ |
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93 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
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94 | /* Seen by userland. */ |
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95 | #define I915_BIT_6_SWIZZLE_9_17 6 |
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96 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
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97 | |||
98 | |||
99 | |||
100 | |||
101 | /** |
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102 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
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103 | * access through main memory. |
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104 | */ |
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105 | void |
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106 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) |
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107 | { |
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108 | drm_i915_private_t *dev_priv = dev->dev_private; |
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109 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
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110 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
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111 | |||
3031 | serge | 112 | if (IS_VALLEYVIEW(dev)) { |
2342 | Serge | 113 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
114 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
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3031 | serge | 115 | } else if (INTEL_INFO(dev)->gen >= 6) { |
116 | uint32_t dimm_c0, dimm_c1; |
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117 | dimm_c0 = I915_READ(MAD_DIMM_C0); |
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118 | dimm_c1 = I915_READ(MAD_DIMM_C1); |
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119 | dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
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120 | dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
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121 | /* Enable swizzling when the channels are populated with |
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122 | * identically sized dimms. We don't need to check the 3rd |
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123 | * channel because no cpu with gpu attached ships in that |
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124 | * configuration. Also, swizzling only makes sense for 2 |
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125 | * channels anyway. */ |
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126 | if (dimm_c0 == dimm_c1) { |
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127 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
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128 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
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129 | } else { |
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130 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
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131 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
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132 | } |
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2342 | Serge | 133 | } else if (IS_GEN5(dev)) { |
2326 | Serge | 134 | /* On Ironlake whatever DRAM config, GPU always do |
135 | * same swizzling setup. |
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136 | */ |
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137 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
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138 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
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139 | } else if (IS_GEN2(dev)) { |
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140 | /* As far as we know, the 865 doesn't have these bit 6 |
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141 | * swizzling issues. |
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142 | */ |
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143 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
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144 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
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3031 | serge | 145 | } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { |
2326 | Serge | 146 | uint32_t dcc; |
147 | |||
3031 | serge | 148 | /* On 9xx chipsets, channel interleave by the CPU is |
2326 | Serge | 149 | * determined by DCC. For single-channel, neither the CPU |
150 | * nor the GPU do swizzling. For dual channel interleaved, |
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151 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
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152 | * 9 for Y tiled. The CPU's interleave is independent, and |
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153 | * can be based on either bit 11 (haven't seen this yet) or |
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154 | * bit 17 (common). |
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155 | */ |
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156 | dcc = I915_READ(DCC); |
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157 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { |
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158 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: |
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159 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: |
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160 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
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161 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
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162 | break; |
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163 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: |
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164 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
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165 | /* This is the base swizzling by the GPU for |
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166 | * tiled buffers. |
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167 | */ |
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168 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
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169 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
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170 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
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171 | /* Bit 11 swizzling by the CPU in addition. */ |
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172 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
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173 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; |
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174 | } else { |
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175 | /* Bit 17 swizzling by the CPU in addition. */ |
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176 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
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177 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
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178 | } |
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179 | break; |
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180 | } |
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181 | if (dcc == 0xffffffff) { |
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182 | DRM_ERROR("Couldn't read from MCHBAR. " |
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183 | "Disabling tiling.\n"); |
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184 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
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185 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
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186 | } |
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187 | } else { |
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188 | /* The 965, G33, and newer, have a very flexible memory |
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189 | * configuration. It will enable dual-channel mode |
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190 | * (interleaving) on as much memory as it can, and the GPU |
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191 | * will additionally sometimes enable different bit 6 |
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192 | * swizzling for tiled objects from the CPU. |
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193 | * |
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194 | * Here's what I found on the G965: |
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195 | * slot fill memory size swizzling |
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196 | * 0A 0B 1A 1B 1-ch 2-ch |
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197 | * 512 0 0 0 512 0 O |
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198 | * 512 0 512 0 16 1008 X |
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199 | * 512 0 0 512 16 1008 X |
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200 | * 0 512 0 512 16 1008 X |
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201 | * 1024 1024 1024 0 2048 1024 O |
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202 | * |
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203 | * We could probably detect this based on either the DRB |
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204 | * matching, which was the case for the swizzling required in |
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205 | * the table above, or from the 1-ch value being less than |
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206 | * the minimum size of a rank. |
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207 | */ |
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208 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { |
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209 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
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210 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
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211 | } else { |
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212 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
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213 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
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214 | } |
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215 | } |
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216 | |||
217 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
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218 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
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219 | } |
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220 | |||
221 | #if 0 |
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222 | /* Check pitch constriants for all chips & tiling formats */ |
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223 | static bool |
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224 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
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225 | { |
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226 | int tile_width; |
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227 | |||
228 | /* Linear is always fine */ |
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229 | if (tiling_mode == I915_TILING_NONE) |
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230 | return true; |
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231 | |||
232 | if (IS_GEN2(dev) || |
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233 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
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234 | tile_width = 128; |
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235 | else |
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236 | tile_width = 512; |
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237 | |||
238 | /* check maximum stride & object size */ |
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239 | if (INTEL_INFO(dev)->gen >= 4) { |
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240 | /* i965 stores the end address of the gtt mapping in the fence |
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241 | * reg, so dont bother to check the size */ |
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242 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) |
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243 | return false; |
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244 | } else { |
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245 | if (stride > 8192) |
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246 | return false; |
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247 | |||
248 | if (IS_GEN3(dev)) { |
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249 | if (size > I830_FENCE_MAX_SIZE_VAL << 20) |
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250 | return false; |
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251 | } else { |
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252 | if (size > I830_FENCE_MAX_SIZE_VAL << 19) |
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253 | return false; |
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254 | } |
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255 | } |
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256 | |||
257 | /* 965+ just needs multiples of tile width */ |
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258 | if (INTEL_INFO(dev)->gen >= 4) { |
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259 | if (stride & (tile_width - 1)) |
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260 | return false; |
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261 | return true; |
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262 | } |
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263 | |||
264 | /* Pre-965 needs power of two tile widths */ |
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265 | if (stride < tile_width) |
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266 | return false; |
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267 | |||
268 | if (stride & (stride - 1)) |
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269 | return false; |
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270 | |||
271 | return true; |
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272 | } |
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273 | |||
274 | /* Is the current GTT allocation valid for the change in tiling? */ |
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275 | static bool |
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276 | i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) |
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277 | { |
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278 | u32 size; |
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279 | |||
280 | if (tiling_mode == I915_TILING_NONE) |
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281 | return true; |
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282 | |||
283 | if (INTEL_INFO(obj->base.dev)->gen >= 4) |
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284 | return true; |
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285 | |||
286 | if (INTEL_INFO(obj->base.dev)->gen == 3) { |
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287 | if (obj->gtt_offset & ~I915_FENCE_START_MASK) |
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288 | return false; |
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289 | } else { |
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290 | if (obj->gtt_offset & ~I830_FENCE_START_MASK) |
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291 | return false; |
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292 | } |
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293 | |||
294 | /* |
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295 | * Previous chips need to be aligned to the size of the smallest |
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296 | * fence register that can contain the object. |
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297 | */ |
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298 | if (INTEL_INFO(obj->base.dev)->gen == 3) |
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299 | size = 1024*1024; |
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300 | else |
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301 | size = 512*1024; |
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302 | |||
303 | while (size < obj->base.size) |
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304 | size <<= 1; |
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305 | |||
306 | if (obj->gtt_space->size != size) |
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307 | return false; |
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308 | |||
309 | if (obj->gtt_offset & (size - 1)) |
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310 | return false; |
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311 | |||
312 | return true; |
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313 | } |
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314 | |||
315 | /** |
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316 | * Sets the tiling mode of an object, returning the required swizzling of |
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317 | * bit 6 of addresses in the object. |
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318 | */ |
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319 | int |
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320 | i915_gem_set_tiling(struct drm_device *dev, void *data, |
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321 | struct drm_file *file) |
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322 | { |
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323 | struct drm_i915_gem_set_tiling *args = data; |
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324 | drm_i915_private_t *dev_priv = dev->dev_private; |
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325 | struct drm_i915_gem_object *obj; |
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326 | int ret = 0; |
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327 | |||
328 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
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329 | if (&obj->base == NULL) |
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330 | return -ENOENT; |
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331 | |||
332 | if (!i915_tiling_ok(dev, |
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333 | args->stride, obj->base.size, args->tiling_mode)) { |
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334 | drm_gem_object_unreference_unlocked(&obj->base); |
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335 | return -EINVAL; |
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336 | } |
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337 | |||
338 | if (obj->pin_count) { |
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339 | drm_gem_object_unreference_unlocked(&obj->base); |
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340 | return -EBUSY; |
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341 | } |
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342 | |||
343 | if (args->tiling_mode == I915_TILING_NONE) { |
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344 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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345 | args->stride = 0; |
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346 | } else { |
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347 | if (args->tiling_mode == I915_TILING_X) |
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348 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
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349 | else |
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350 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
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351 | |||
352 | /* Hide bit 17 swizzling from the user. This prevents old Mesa |
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353 | * from aborting the application on sw fallbacks to bit 17, |
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354 | * and we use the pread/pwrite bit17 paths to swizzle for it. |
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355 | * If there was a user that was relying on the swizzle |
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356 | * information for drm_intel_bo_map()ed reads/writes this would |
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357 | * break it, but we don't have any of those. |
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358 | */ |
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359 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
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360 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
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361 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
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362 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
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363 | |||
364 | /* If we can't handle the swizzling, make it untiled. */ |
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365 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { |
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366 | args->tiling_mode = I915_TILING_NONE; |
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367 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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368 | args->stride = 0; |
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369 | } |
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370 | } |
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371 | |||
372 | mutex_lock(&dev->struct_mutex); |
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373 | if (args->tiling_mode != obj->tiling_mode || |
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374 | args->stride != obj->stride) { |
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375 | /* We need to rebind the object if its current allocation |
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376 | * no longer meets the alignment restrictions for its new |
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377 | * tiling mode. Otherwise we can just leave it alone, but |
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3031 | serge | 378 | * need to ensure that any fence register is updated before |
379 | * the next fenced (either through the GTT or by the BLT unit |
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380 | * on older GPUs) access. |
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381 | * |
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382 | * After updating the tiling parameters, we then flag whether |
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383 | * we need to update an associated fence register. Note this |
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384 | * has to also include the unfenced register the GPU uses |
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385 | * whilst executing a fenced command for an untiled object. |
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2326 | Serge | 386 | */ |
387 | |||
388 | obj->map_and_fenceable = |
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389 | obj->gtt_space == NULL || |
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390 | (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && |
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391 | i915_gem_object_fence_ok(obj, args->tiling_mode)); |
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392 | |||
393 | /* Rebind if we need a change of alignment */ |
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394 | if (!obj->map_and_fenceable) { |
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395 | u32 unfenced_alignment = |
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396 | i915_gem_get_unfenced_gtt_alignment(dev, |
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397 | obj->base.size, |
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398 | args->tiling_mode); |
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399 | if (obj->gtt_offset & (unfenced_alignment - 1)) |
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400 | ret = i915_gem_object_unbind(obj); |
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401 | } |
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402 | |||
403 | if (ret == 0) { |
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3031 | serge | 404 | obj->fence_dirty = |
405 | obj->fenced_gpu_access || |
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406 | obj->fence_reg != I915_FENCE_REG_NONE; |
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407 | |||
2326 | Serge | 408 | obj->tiling_mode = args->tiling_mode; |
409 | obj->stride = args->stride; |
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3031 | serge | 410 | |
411 | /* Force the fence to be reacquired for GTT access */ |
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412 | i915_gem_release_mmap(obj); |
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2326 | Serge | 413 | } |
414 | } |
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415 | /* we have to maintain this existing ABI... */ |
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416 | args->stride = obj->stride; |
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417 | args->tiling_mode = obj->tiling_mode; |
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418 | drm_gem_object_unreference(&obj->base); |
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419 | mutex_unlock(&dev->struct_mutex); |
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420 | |||
421 | return ret; |
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422 | } |
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423 | |||
424 | /** |
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425 | * Returns the current tiling mode and required bit 6 swizzling for the object. |
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426 | */ |
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427 | int |
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428 | i915_gem_get_tiling(struct drm_device *dev, void *data, |
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429 | struct drm_file *file) |
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430 | { |
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431 | struct drm_i915_gem_get_tiling *args = data; |
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432 | drm_i915_private_t *dev_priv = dev->dev_private; |
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433 | struct drm_i915_gem_object *obj; |
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434 | |||
435 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
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436 | if (&obj->base == NULL) |
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437 | return -ENOENT; |
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438 | |||
439 | mutex_lock(&dev->struct_mutex); |
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440 | |||
441 | args->tiling_mode = obj->tiling_mode; |
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442 | switch (obj->tiling_mode) { |
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443 | case I915_TILING_X: |
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444 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
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445 | break; |
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446 | case I915_TILING_Y: |
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447 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
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448 | break; |
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449 | case I915_TILING_NONE: |
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450 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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451 | break; |
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452 | default: |
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453 | DRM_ERROR("unknown tiling mode\n"); |
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454 | } |
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455 | |||
456 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
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457 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
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458 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
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459 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
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460 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
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461 | |||
462 | drm_gem_object_unreference(&obj->base); |
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463 | mutex_unlock(&dev->struct_mutex); |
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464 | |||
465 | return 0; |
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466 | } |
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467 | |||
468 | /** |
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469 | * Swap every 64 bytes of this page around, to account for it having a new |
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470 | * bit 17 of its physical address and therefore being interpreted differently |
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471 | * by the GPU. |
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472 | */ |
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473 | static void |
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474 | i915_gem_swizzle_page(struct page *page) |
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475 | { |
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476 | char temp[64]; |
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477 | char *vaddr; |
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478 | int i; |
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479 | |||
480 | vaddr = kmap(page); |
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481 | |||
482 | for (i = 0; i < PAGE_SIZE; i += 128) { |
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483 | memcpy(temp, &vaddr[i], 64); |
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484 | memcpy(&vaddr[i], &vaddr[i + 64], 64); |
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485 | memcpy(&vaddr[i + 64], temp, 64); |
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486 | } |
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487 | |||
488 | kunmap(page); |
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489 | } |
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490 | |||
491 | void |
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492 | i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) |
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493 | { |
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3031 | serge | 494 | struct scatterlist *sg; |
2326 | Serge | 495 | int page_count = obj->base.size >> PAGE_SHIFT; |
496 | int i; |
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497 | |||
498 | if (obj->bit_17 == NULL) |
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499 | return; |
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500 | |||
3031 | serge | 501 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
502 | struct page *page = sg_page(sg); |
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503 | char new_bit_17 = page_to_phys(page) >> 17; |
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2326 | Serge | 504 | if ((new_bit_17 & 0x1) != |
505 | (test_bit(i, obj->bit_17) != 0)) { |
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3031 | serge | 506 | i915_gem_swizzle_page(page); |
507 | set_page_dirty(page); |
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2326 | Serge | 508 | } |
509 | } |
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510 | } |
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511 | |||
512 | void |
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513 | i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) |
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514 | { |
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3031 | serge | 515 | struct scatterlist *sg; |
2326 | Serge | 516 | int page_count = obj->base.size >> PAGE_SHIFT; |
517 | int i; |
||
518 | |||
519 | if (obj->bit_17 == NULL) { |
||
520 | obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * |
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521 | sizeof(long), GFP_KERNEL); |
||
522 | if (obj->bit_17 == NULL) { |
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523 | DRM_ERROR("Failed to allocate memory for bit 17 " |
||
524 | "record\n"); |
||
525 | return; |
||
526 | } |
||
527 | } |
||
528 | |||
3031 | serge | 529 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
530 | struct page *page = sg_page(sg); |
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531 | if (page_to_phys(page) & (1 << 17)) |
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2326 | Serge | 532 | __set_bit(i, obj->bit_17); |
533 | else |
||
534 | __clear_bit(i, obj->bit_17); |
||
535 | } |
||
536 | } |
||
537 | |||
538 | #endif><>>=>=><=>>>><>><> |