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| Rev | Author | Line No. | Line |
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| 5060 | serge | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Mika Kuoppala |
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| 25 | * |
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| 26 | */ |
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| 27 | |||
| 28 | #include "i915_drv.h" |
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| 29 | #include "intel_renderstate.h" |
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| 30 | |||
| 31 | static const struct intel_renderstate_rodata * |
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| 32 | render_state_get_rodata(struct drm_device *dev, const int gen) |
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| 33 | { |
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| 34 | switch (gen) { |
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| 35 | case 6: |
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| 36 | return &gen6_null_state; |
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| 37 | case 7: |
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| 38 | return &gen7_null_state; |
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| 39 | case 8: |
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| 40 | return &gen8_null_state; |
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| 5354 | serge | 41 | case 9: |
| 42 | return &gen9_null_state; |
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| 5060 | serge | 43 | } |
| 44 | |||
| 45 | return NULL; |
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| 46 | } |
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| 47 | |||
| 48 | static int render_state_init(struct render_state *so, struct drm_device *dev) |
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| 49 | { |
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| 50 | int ret; |
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| 51 | |||
| 52 | so->gen = INTEL_INFO(dev)->gen; |
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| 53 | so->rodata = render_state_get_rodata(dev, so->gen); |
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| 54 | if (so->rodata == NULL) |
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| 55 | return 0; |
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| 56 | |||
| 57 | if (so->rodata->batch_items * 4 > 4096) |
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| 58 | return -EINVAL; |
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| 59 | |||
| 60 | so->obj = i915_gem_alloc_object(dev, 4096); |
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| 61 | if (so->obj == NULL) |
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| 62 | return -ENOMEM; |
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| 63 | |||
| 64 | ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0); |
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| 65 | if (ret) |
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| 66 | goto free_gem; |
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| 67 | |||
| 68 | so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj); |
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| 69 | return 0; |
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| 70 | |||
| 71 | free_gem: |
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| 72 | drm_gem_object_unreference(&so->obj->base); |
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| 73 | return ret; |
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| 74 | } |
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| 75 | |||
| 76 | static int render_state_setup(struct render_state *so) |
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| 77 | { |
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| 78 | const struct intel_renderstate_rodata *rodata = so->rodata; |
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| 79 | unsigned int i = 0, reloc_index = 0; |
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| 80 | struct page *page; |
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| 81 | u32 *d; |
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| 82 | int ret; |
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| 83 | |||
| 84 | ret = i915_gem_object_set_to_cpu_domain(so->obj, true); |
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| 85 | if (ret) |
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| 86 | return ret; |
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| 87 | |||
| 88 | page = sg_page(so->obj->pages->sgl); |
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| 89 | d = kmap(page); |
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| 90 | |||
| 91 | while (i < rodata->batch_items) { |
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| 92 | u32 s = rodata->batch[i]; |
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| 93 | |||
| 94 | if (i * 4 == rodata->reloc[reloc_index]) { |
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| 95 | u64 r = s + so->ggtt_offset; |
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| 96 | s = lower_32_bits(r); |
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| 97 | if (so->gen >= 8) { |
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| 98 | if (i + 1 >= rodata->batch_items || |
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| 99 | rodata->batch[i + 1] != 0) |
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| 100 | return -EINVAL; |
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| 101 | |||
| 102 | d[i++] = s; |
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| 103 | s = upper_32_bits(r); |
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| 104 | } |
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| 105 | |||
| 106 | reloc_index++; |
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| 107 | } |
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| 108 | |||
| 109 | d[i++] = s; |
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| 110 | } |
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| 5354 | serge | 111 | kunmap(page); |
| 5060 | serge | 112 | |
| 113 | ret = i915_gem_object_set_to_gtt_domain(so->obj, false); |
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| 114 | if (ret) |
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| 115 | return ret; |
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| 116 | |||
| 117 | if (rodata->reloc[reloc_index] != -1) { |
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| 118 | DRM_ERROR("only %d relocs resolved\n", reloc_index); |
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| 119 | return -EINVAL; |
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| 120 | } |
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| 121 | |||
| 122 | return 0; |
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| 123 | } |
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| 124 | |||
| 5354 | serge | 125 | void i915_gem_render_state_fini(struct render_state *so) |
| 5060 | serge | 126 | { |
| 127 | i915_gem_object_ggtt_unpin(so->obj); |
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| 128 | drm_gem_object_unreference(&so->obj->base); |
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| 129 | } |
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| 130 | |||
| 5354 | serge | 131 | int i915_gem_render_state_prepare(struct intel_engine_cs *ring, |
| 132 | struct render_state *so) |
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| 5060 | serge | 133 | { |
| 134 | int ret; |
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| 135 | |||
| 136 | if (WARN_ON(ring->id != RCS)) |
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| 137 | return -ENOENT; |
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| 138 | |||
| 5354 | serge | 139 | ret = render_state_init(so, ring->dev); |
| 5060 | serge | 140 | if (ret) |
| 141 | return ret; |
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| 142 | |||
| 5354 | serge | 143 | if (so->rodata == NULL) |
| 5060 | serge | 144 | return 0; |
| 145 | |||
| 5354 | serge | 146 | ret = render_state_setup(so); |
| 147 | if (ret) { |
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| 148 | i915_gem_render_state_fini(so); |
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| 149 | return ret; |
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| 150 | } |
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| 151 | |||
| 152 | return 0; |
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| 153 | } |
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| 154 | |||
| 155 | int i915_gem_render_state_init(struct intel_engine_cs *ring) |
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| 156 | { |
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| 157 | struct render_state so; |
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| 158 | int ret; |
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| 159 | |||
| 160 | ret = i915_gem_render_state_prepare(ring, &so); |
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| 5060 | serge | 161 | if (ret) |
| 5354 | serge | 162 | return ret; |
| 5060 | serge | 163 | |
| 5354 | serge | 164 | if (so.rodata == NULL) |
| 165 | return 0; |
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| 166 | |||
| 5060 | serge | 167 | ret = ring->dispatch_execbuffer(ring, |
| 168 | so.ggtt_offset, |
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| 169 | so.rodata->batch_items * 4, |
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| 170 | I915_DISPATCH_SECURE); |
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| 171 | if (ret) |
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| 172 | goto out; |
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| 173 | |||
| 174 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); |
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| 175 | |||
| 176 | ret = __i915_add_request(ring, NULL, so.obj, NULL); |
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| 177 | /* __i915_add_request moves object to inactive if it fails */ |
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| 178 | out: |
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| 5354 | serge | 179 | i915_gem_render_state_fini(&so); |
| 5060 | serge | 180 | return ret; |
| 181 | } |