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5060 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Please try to maintain the following order within this file unless it makes |
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24 | * sense to do otherwise. From top to bottom: |
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25 | * 1. typedefs |
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26 | * 2. #defines, and macros |
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27 | * 3. structure definitions |
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28 | * 4. function prototypes |
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29 | * |
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30 | * Within each section, please try to order by generation in ascending order, |
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31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). |
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32 | */ |
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33 | |||
34 | #ifndef __I915_GEM_GTT_H__ |
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35 | #define __I915_GEM_GTT_H__ |
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36 | |||
37 | typedef uint32_t gen6_gtt_pte_t; |
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38 | typedef uint64_t gen8_gtt_pte_t; |
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39 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
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40 | |||
41 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
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42 | |||
43 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) |
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44 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
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45 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) |
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46 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
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47 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
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48 | #define GEN6_PTE_CACHE_LLC (2 << 1) |
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49 | #define GEN6_PTE_UNCACHED (1 << 1) |
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50 | #define GEN6_PTE_VALID (1 << 0) |
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51 | |||
52 | #define GEN6_PPGTT_PD_ENTRIES 512 |
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53 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) |
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54 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
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55 | #define GEN6_PDE_VALID (1 << 0) |
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56 | |||
57 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
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58 | |||
59 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) |
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60 | #define BYT_PTE_WRITEABLE (1 << 1) |
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61 | |||
62 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits |
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63 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. |
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64 | */ |
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65 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ |
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66 | (((bits) & 0x8) << (11 - 3))) |
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67 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
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68 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
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69 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
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70 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
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71 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
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72 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
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73 | #define HSW_PTE_UNCACHED (0) |
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74 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
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75 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
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76 | |||
77 | /* GEN8 legacy style address is defined as a 3 level page table: |
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78 | * 31:30 | 29:21 | 20:12 | 11:0 |
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79 | * PDPE | PDE | PTE | offset |
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80 | * The difference as compared to normal x86 3 level page table is the PDPEs are |
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81 | * programmed via register. |
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82 | */ |
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83 | #define GEN8_PDPE_SHIFT 30 |
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84 | #define GEN8_PDPE_MASK 0x3 |
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85 | #define GEN8_PDE_SHIFT 21 |
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86 | #define GEN8_PDE_MASK 0x1ff |
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87 | #define GEN8_PTE_SHIFT 12 |
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88 | #define GEN8_PTE_MASK 0x1ff |
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89 | #define GEN8_LEGACY_PDPS 4 |
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90 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
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91 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
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92 | |||
93 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
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94 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ |
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95 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ |
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96 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ |
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97 | |||
98 | #define CHV_PPAT_SNOOP (1<<6) |
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99 | #define GEN8_PPAT_AGE(x) (x<<4) |
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100 | #define GEN8_PPAT_LLCeLLC (3<<2) |
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101 | #define GEN8_PPAT_LLCELLC (2<<2) |
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102 | #define GEN8_PPAT_LLC (1<<2) |
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103 | #define GEN8_PPAT_WB (3<<0) |
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104 | #define GEN8_PPAT_WT (2<<0) |
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105 | #define GEN8_PPAT_WC (1<<0) |
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106 | #define GEN8_PPAT_UC (0<<0) |
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107 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) |
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108 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) |
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109 | |||
110 | enum i915_cache_level; |
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111 | /** |
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112 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
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113 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
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114 | * object into/from the address space. |
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115 | * |
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116 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
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117 | * will always be <= an objects lifetime. So object refcounting should cover us. |
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118 | */ |
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119 | struct i915_vma { |
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120 | struct drm_mm_node node; |
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121 | struct drm_i915_gem_object *obj; |
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122 | struct i915_address_space *vm; |
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123 | |||
124 | /** This object's place on the active/inactive lists */ |
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125 | struct list_head mm_list; |
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126 | |||
127 | struct list_head vma_link; /* Link in the object's VMA list */ |
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128 | |||
129 | /** This vma's place in the batchbuffer or on the eviction list */ |
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130 | struct list_head exec_list; |
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131 | |||
132 | /** |
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133 | * Used for performing relocations during execbuffer insertion. |
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134 | */ |
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135 | struct hlist_node exec_node; |
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136 | unsigned long exec_handle; |
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137 | struct drm_i915_gem_exec_object2 *exec_entry; |
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138 | |||
139 | /** |
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140 | * How many users have pinned this object in GTT space. The following |
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141 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
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142 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
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143 | * times for the same batchbuffer), and the framebuffer code. When |
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144 | * switching/pageflipping, the framebuffer code has at most two buffers |
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145 | * pinned per crtc. |
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146 | * |
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147 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
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148 | * bits with absolutely no headroom. So use 4 bits. */ |
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149 | unsigned int pin_count:4; |
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150 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
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151 | |||
152 | /** Unmap an object from an address space. This usually consists of |
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153 | * setting the valid PTE entries to a reserved scratch page. */ |
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154 | void (*unbind_vma)(struct i915_vma *vma); |
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155 | /* Map an object into an address space with the given cache flags. */ |
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156 | #define GLOBAL_BIND (1<<0) |
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157 | #define PTE_READ_ONLY (1<<1) |
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158 | void (*bind_vma)(struct i915_vma *vma, |
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159 | enum i915_cache_level cache_level, |
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160 | u32 flags); |
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161 | }; |
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162 | |||
163 | struct i915_address_space { |
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164 | struct drm_mm mm; |
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165 | struct drm_device *dev; |
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166 | struct list_head global_link; |
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167 | unsigned long start; /* Start offset always 0 for dri2 */ |
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168 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
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169 | |||
170 | struct { |
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171 | dma_addr_t addr; |
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172 | struct page *page; |
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173 | } scratch; |
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174 | |||
175 | /** |
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176 | * List of objects currently involved in rendering. |
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177 | * |
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178 | * Includes buffers having the contents of their GPU caches |
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179 | * flushed, not necessarily primitives. last_rendering_seqno |
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180 | * represents when the rendering involved will be completed. |
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181 | * |
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182 | * A reference is held on the buffer while on this list. |
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183 | */ |
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184 | struct list_head active_list; |
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185 | |||
186 | /** |
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187 | * LRU list of objects which are not in the ringbuffer and |
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188 | * are ready to unbind, but are still in the GTT. |
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189 | * |
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190 | * last_rendering_seqno is 0 while an object is in this list. |
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191 | * |
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192 | * A reference is not held on the buffer while on this list, |
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193 | * as merely being GTT-bound shouldn't prevent its being |
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194 | * freed, and we'll pull it off the list in the free path. |
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195 | */ |
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196 | struct list_head inactive_list; |
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197 | |||
198 | /* FIXME: Need a more generic return type */ |
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199 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
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200 | enum i915_cache_level level, |
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201 | bool valid, u32 flags); /* Create a valid PTE */ |
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202 | void (*clear_range)(struct i915_address_space *vm, |
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203 | uint64_t start, |
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204 | uint64_t length, |
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205 | bool use_scratch); |
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206 | void (*insert_entries)(struct i915_address_space *vm, |
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207 | struct sg_table *st, |
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208 | uint64_t start, |
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209 | enum i915_cache_level cache_level, u32 flags); |
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210 | void (*cleanup)(struct i915_address_space *vm); |
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211 | }; |
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212 | |||
213 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
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214 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
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215 | * collateral associated with any va->pa translations GEN hardware also has a |
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216 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
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217 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
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218 | * the spec. |
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219 | */ |
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220 | struct i915_gtt { |
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221 | struct i915_address_space base; |
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222 | size_t stolen_size; /* Total size of stolen memory */ |
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223 | |||
224 | unsigned long mappable_end; /* End offset that we can CPU map */ |
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225 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
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226 | phys_addr_t mappable_base; /* PA of our GMADR */ |
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227 | |||
228 | /** "Graphics Stolen Memory" holds the global PTEs */ |
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229 | void __iomem *gsm; |
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230 | |||
231 | bool do_idle_maps; |
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232 | |||
233 | int mtrr; |
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234 | |||
235 | /* global gtt ops */ |
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236 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
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237 | size_t *stolen, phys_addr_t *mappable_base, |
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238 | unsigned long *mappable_end); |
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239 | }; |
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240 | |||
241 | struct i915_hw_ppgtt { |
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242 | struct i915_address_space base; |
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243 | struct kref ref; |
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244 | struct drm_mm_node node; |
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245 | unsigned num_pd_entries; |
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246 | unsigned num_pd_pages; /* gen8+ */ |
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247 | union { |
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248 | struct page **pt_pages; |
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249 | struct page **gen8_pt_pages[GEN8_LEGACY_PDPS]; |
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250 | }; |
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251 | struct page *pd_pages; |
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252 | union { |
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253 | uint32_t pd_offset; |
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254 | dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS]; |
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255 | }; |
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256 | union { |
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257 | dma_addr_t *pt_dma_addr; |
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258 | dma_addr_t *gen8_pt_dma_addr[4]; |
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259 | }; |
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260 | |||
261 | struct intel_context *ctx; |
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262 | |||
263 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
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264 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
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265 | struct intel_engine_cs *ring, |
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266 | bool synchronous); |
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267 | // void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
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268 | }; |
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269 | |||
270 | int i915_gem_gtt_init(struct drm_device *dev); |
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271 | void i915_gem_init_global_gtt(struct drm_device *dev); |
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272 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
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273 | unsigned long mappable_end, unsigned long end); |
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274 | |||
275 | bool intel_enable_ppgtt(struct drm_device *dev, bool full); |
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276 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); |
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277 | |||
278 | void i915_check_and_clear_faults(struct drm_device *dev); |
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279 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
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280 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
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281 | |||
282 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
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283 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
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284 | |||
285 | #endif1) |