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3031 | serge | 1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Ben Widawsky |
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25 | * |
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26 | */ |
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27 | |||
28 | /* |
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29 | * This file implements HW context support. On gen5+ a HW context consists of an |
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30 | * opaque GPU object which is referenced at times of context saves and restores. |
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31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
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32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
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33 | * something like a context does exist for the media ring, the code only |
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34 | * supports contexts for the render ring. |
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35 | * |
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36 | * In software, there is a distinction between contexts created by the user, |
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37 | * and the default HW context. The default HW context is used by GPU clients |
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38 | * that do not request setup of their own hardware context. The default |
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39 | * context's state is never restored to help prevent programming errors. This |
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40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
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41 | * The default context only exists to give the GPU some offset to load as the |
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42 | * current to invoke a save of the context we actually care about. In fact, the |
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43 | * code could likely be constructed, albeit in a more complicated fashion, to |
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44 | * never use the default context, though that limits the driver's ability to |
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45 | * swap out, and/or destroy other contexts. |
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46 | * |
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47 | * All other contexts are created as a request by the GPU client. These contexts |
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48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
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49 | * potentially query certain state) at any time. The kernel driver makes |
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50 | * certain that the appropriate commands are inserted. |
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51 | * |
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52 | * The context life cycle is semi-complicated in that context BOs may live |
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53 | * longer than the context itself because of the way the hardware, and object |
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54 | * tracking works. Below is a very crude representation of the state machine |
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55 | * describing the context life. |
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56 | * refcount pincount active |
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57 | * S0: initial state 0 0 0 |
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58 | * S1: context created 1 0 0 |
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59 | * S2: context is currently running 2 1 X |
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60 | * S3: GPU referenced, but not current 2 0 1 |
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61 | * S4: context is current, but destroyed 1 1 0 |
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62 | * S5: like S3, but destroyed 1 0 1 |
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63 | * |
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64 | * The most common (but not all) transitions: |
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65 | * S0->S1: client creates a context |
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66 | * S1->S2: client submits execbuf with context |
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67 | * S2->S3: other clients submits execbuf with context |
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68 | * S3->S1: context object was retired |
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69 | * S3->S2: clients submits another execbuf |
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70 | * S2->S4: context destroy called with current context |
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71 | * S3->S5->S0: destroy path |
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72 | * S4->S5->S0: destroy path on current context |
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73 | * |
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74 | * There are two confusing terms used above: |
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75 | * The "current context" means the context which is currently running on the |
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4560 | Serge | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
3031 | serge | 77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
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79 | * is to do a GPU reset. |
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80 | * |
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81 | * An "active context' is one which was previously the "current context" and is |
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82 | * on the active list waiting for the next context switch to occur. Until this |
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83 | * happens, the object must remain at the same gtt offset. It is therefore |
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84 | * possible to destroy a context, but it is still active. |
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85 | * |
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86 | */ |
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87 | |||
88 | #include |
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89 | #include |
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90 | #include "i915_drv.h" |
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91 | |||
92 | /* This is a HW constraint. The value below is the largest known requirement |
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93 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
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94 | * part. It should be safe to decrease this, but it's more future proof as is. |
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95 | */ |
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5060 | serge | 96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 |
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3031 | serge | 98 | |
5060 | serge | 99 | static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
100 | { |
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101 | struct drm_device *dev = ppgtt->base.dev; |
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102 | struct drm_i915_private *dev_priv = dev->dev_private; |
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103 | struct i915_address_space *vm = &ppgtt->base; |
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3031 | serge | 104 | |
5060 | serge | 105 | if (ppgtt == dev_priv->mm.aliasing_ppgtt || |
106 | (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) { |
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107 | ppgtt->base.cleanup(&ppgtt->base); |
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108 | return; |
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109 | } |
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110 | |||
111 | /* |
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112 | * Make sure vmas are unbound before we take down the drm_mm |
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113 | * |
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114 | * FIXME: Proper refcounting should take care of this, this shouldn't be |
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115 | * needed at all. |
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116 | */ |
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117 | if (!list_empty(&vm->active_list)) { |
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118 | struct i915_vma *vma; |
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119 | |||
120 | list_for_each_entry(vma, &vm->active_list, mm_list) |
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121 | if (WARN_ON(list_empty(&vma->vma_link) || |
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122 | list_is_singular(&vma->vma_link))) |
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123 | break; |
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124 | |||
125 | i915_gem_evict_vm(&ppgtt->base, true); |
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126 | } else { |
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127 | i915_gem_retire_requests(dev); |
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128 | i915_gem_evict_vm(&ppgtt->base, false); |
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129 | } |
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130 | |||
131 | ppgtt->base.cleanup(&ppgtt->base); |
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132 | } |
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133 | |||
134 | static void ppgtt_release(struct kref *kref) |
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135 | { |
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136 | struct i915_hw_ppgtt *ppgtt = |
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137 | container_of(kref, struct i915_hw_ppgtt, ref); |
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138 | |||
139 | do_ppgtt_cleanup(ppgtt); |
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140 | kfree(ppgtt); |
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141 | } |
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142 | |||
143 | static size_t get_context_alignment(struct drm_device *dev) |
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144 | { |
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145 | if (IS_GEN6(dev)) |
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146 | return GEN6_CONTEXT_ALIGN; |
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147 | |||
148 | return GEN7_CONTEXT_ALIGN; |
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149 | } |
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150 | |||
3031 | serge | 151 | static int get_context_size(struct drm_device *dev) |
152 | { |
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153 | struct drm_i915_private *dev_priv = dev->dev_private; |
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154 | int ret; |
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155 | u32 reg; |
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156 | |||
157 | switch (INTEL_INFO(dev)->gen) { |
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158 | case 6: |
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159 | reg = I915_READ(CXT_SIZE); |
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160 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
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161 | break; |
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162 | case 7: |
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163 | reg = I915_READ(GEN7_CXT_SIZE); |
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164 | if (IS_HASWELL(dev)) |
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4104 | Serge | 165 | ret = HSW_CXT_TOTAL_SIZE; |
3031 | serge | 166 | else |
167 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
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168 | break; |
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4560 | Serge | 169 | case 8: |
170 | ret = GEN8_CXT_TOTAL_SIZE; |
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171 | break; |
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3031 | serge | 172 | default: |
173 | BUG(); |
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174 | } |
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175 | |||
176 | return ret; |
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177 | } |
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178 | |||
4104 | Serge | 179 | void i915_gem_context_free(struct kref *ctx_ref) |
3031 | serge | 180 | { |
5060 | serge | 181 | struct intel_context *ctx = container_of(ctx_ref, |
4104 | Serge | 182 | typeof(*ctx), ref); |
5060 | serge | 183 | struct i915_hw_ppgtt *ppgtt = NULL; |
3031 | serge | 184 | |
5060 | serge | 185 | if (ctx->legacy_hw_ctx.rcs_state) { |
186 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ |
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187 | if (USES_PPGTT(ctx->legacy_hw_ctx.rcs_state->base.dev)) |
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188 | ppgtt = ctx_to_ppgtt(ctx); |
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189 | } |
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190 | |||
191 | if (ppgtt) |
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192 | kref_put(&ppgtt->ref, ppgtt_release); |
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193 | if (ctx->legacy_hw_ctx.rcs_state) |
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194 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
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4560 | Serge | 195 | list_del(&ctx->link); |
3031 | serge | 196 | kfree(ctx); |
197 | } |
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198 | |||
5060 | serge | 199 | static struct drm_i915_gem_object * |
200 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
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201 | { |
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202 | struct drm_i915_gem_object *obj; |
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203 | int ret; |
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204 | |||
205 | obj = i915_gem_alloc_object(dev, size); |
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206 | if (obj == NULL) |
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207 | return ERR_PTR(-ENOMEM); |
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208 | |||
209 | /* |
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210 | * Try to make the context utilize L3 as well as LLC. |
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211 | * |
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212 | * On VLV we don't have L3 controls in the PTEs so we |
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213 | * shouldn't touch the cache level, especially as that |
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214 | * would make the object snooped which might have a |
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215 | * negative performance impact. |
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216 | */ |
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217 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
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218 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
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219 | /* Failure shouldn't ever happen this early */ |
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220 | if (WARN_ON(ret)) { |
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221 | drm_gem_object_unreference(&obj->base); |
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222 | return ERR_PTR(ret); |
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223 | } |
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224 | } |
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225 | |||
226 | return obj; |
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227 | } |
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228 | |||
229 | static struct i915_hw_ppgtt * |
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230 | create_vm_for_ctx(struct drm_device *dev, struct intel_context *ctx) |
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231 | { |
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232 | struct i915_hw_ppgtt *ppgtt; |
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233 | int ret; |
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234 | |||
235 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
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236 | if (!ppgtt) |
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237 | return ERR_PTR(-ENOMEM); |
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238 | |||
239 | ret = i915_gem_init_ppgtt(dev, ppgtt); |
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240 | if (ret) { |
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241 | kfree(ppgtt); |
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242 | return ERR_PTR(ret); |
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243 | } |
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244 | |||
245 | ppgtt->ctx = ctx; |
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246 | return ppgtt; |
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247 | } |
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248 | |||
249 | static struct intel_context * |
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250 | __create_hw_context(struct drm_device *dev, |
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3031 | serge | 251 | struct drm_i915_file_private *file_priv) |
252 | { |
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253 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 254 | struct intel_context *ctx; |
3480 | Serge | 255 | int ret; |
3031 | serge | 256 | |
3243 | Serge | 257 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
3031 | serge | 258 | if (ctx == NULL) |
259 | return ERR_PTR(-ENOMEM); |
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260 | |||
4104 | Serge | 261 | kref_init(&ctx->ref); |
5060 | serge | 262 | list_add_tail(&ctx->link, &dev_priv->context_list); |
3031 | serge | 263 | |
5060 | serge | 264 | if (dev_priv->hw_context_size) { |
265 | struct drm_i915_gem_object *obj = |
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266 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
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267 | if (IS_ERR(obj)) { |
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268 | ret = PTR_ERR(obj); |
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3746 | Serge | 269 | goto err_out; |
270 | } |
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5060 | serge | 271 | ctx->legacy_hw_ctx.rcs_state = obj; |
272 | } |
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3746 | Serge | 273 | |
3031 | serge | 274 | /* Default context will never have a file_priv */ |
5060 | serge | 275 | if (file_priv != NULL) { |
276 | ret = idr_alloc(&file_priv->context_idr, ctx, |
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277 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
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3480 | Serge | 278 | if (ret < 0) |
3031 | serge | 279 | goto err_out; |
5060 | serge | 280 | } else |
281 | ret = DEFAULT_CONTEXT_HANDLE; |
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4104 | Serge | 282 | |
283 | ctx->file_priv = file_priv; |
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5060 | serge | 284 | ctx->user_handle = ret; |
4560 | Serge | 285 | /* NB: Mark all slices as needing a remap so that when the context first |
286 | * loads it will restore whatever remap state already exists. If there |
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287 | * is no remap info, it will be a NOP. */ |
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288 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
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3031 | serge | 289 | |
290 | return ctx; |
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291 | |||
292 | err_out: |
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4104 | Serge | 293 | i915_gem_context_unreference(ctx); |
3031 | serge | 294 | return ERR_PTR(ret); |
295 | } |
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296 | |||
297 | /** |
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298 | * The default context needs to exist per ring that uses contexts. It stores the |
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299 | * context state of the GPU for applications that don't utilize HW contexts, as |
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300 | * well as an idle case. |
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301 | */ |
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5060 | serge | 302 | static struct intel_context * |
303 | i915_gem_create_context(struct drm_device *dev, |
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304 | struct drm_i915_file_private *file_priv, |
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305 | bool create_vm) |
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3031 | serge | 306 | { |
5060 | serge | 307 | const bool is_global_default_ctx = file_priv == NULL; |
308 | struct drm_i915_private *dev_priv = dev->dev_private; |
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309 | struct intel_context *ctx; |
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310 | int ret = 0; |
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3031 | serge | 311 | |
5060 | serge | 312 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
3031 | serge | 313 | |
5060 | serge | 314 | ctx = __create_hw_context(dev, file_priv); |
3031 | serge | 315 | if (IS_ERR(ctx)) |
5060 | serge | 316 | return ctx; |
3031 | serge | 317 | |
5060 | serge | 318 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
319 | /* We may need to do things with the shrinker which |
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320 | * require us to immediately switch back to the default |
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321 | * context. This can cause a problem as pinning the |
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322 | * default context also requires GTT space which may not |
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323 | * be available. To avoid this we always pin the default |
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324 | * context. |
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3031 | serge | 325 | */ |
5060 | serge | 326 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
327 | get_context_alignment(dev), 0); |
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4104 | Serge | 328 | if (ret) { |
329 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
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3031 | serge | 330 | goto err_destroy; |
4104 | Serge | 331 | } |
5060 | serge | 332 | } |
3031 | serge | 333 | |
5060 | serge | 334 | if (create_vm) { |
335 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); |
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336 | |||
337 | if (IS_ERR_OR_NULL(ppgtt)) { |
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338 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
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339 | PTR_ERR(ppgtt)); |
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340 | ret = PTR_ERR(ppgtt); |
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341 | goto err_unpin; |
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342 | } else |
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343 | ctx->vm = &ppgtt->base; |
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344 | |||
345 | /* This case is reserved for the global default context and |
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346 | * should only happen once. */ |
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347 | if (is_global_default_ctx) { |
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348 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { |
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349 | ret = -EEXIST; |
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3031 | serge | 350 | goto err_unpin; |
4104 | Serge | 351 | } |
3031 | serge | 352 | |
5060 | serge | 353 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
354 | } |
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355 | } else if (USES_PPGTT(dev)) { |
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356 | /* For platforms which only have aliasing PPGTT, we fake the |
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357 | * address space and refcounting. */ |
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358 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; |
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359 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); |
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360 | } else |
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361 | ctx->vm = &dev_priv->gtt.base; |
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4560 | Serge | 362 | |
5060 | serge | 363 | return ctx; |
3031 | serge | 364 | |
365 | err_unpin: |
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5060 | serge | 366 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
367 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
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3031 | serge | 368 | err_destroy: |
4104 | Serge | 369 | i915_gem_context_unreference(ctx); |
5060 | serge | 370 | return ERR_PTR(ret); |
3031 | serge | 371 | } |
372 | |||
5060 | serge | 373 | void i915_gem_context_reset(struct drm_device *dev) |
374 | { |
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375 | struct drm_i915_private *dev_priv = dev->dev_private; |
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376 | int i; |
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377 | |||
378 | /* Prevent the hardware from restoring the last context (which hung) on |
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379 | * the next switch */ |
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380 | for (i = 0; i < I915_NUM_RINGS; i++) { |
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381 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
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382 | struct intel_context *dctx = ring->default_context; |
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383 | struct intel_context *lctx = ring->last_context; |
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384 | |||
385 | /* Do a fake switch to the default context */ |
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386 | if (lctx == dctx) |
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387 | continue; |
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388 | |||
389 | if (!lctx) |
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390 | continue; |
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391 | |||
392 | if (dctx->legacy_hw_ctx.rcs_state && i == RCS) { |
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393 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->legacy_hw_ctx.rcs_state, |
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394 | get_context_alignment(dev), 0)); |
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395 | /* Fake a finish/inactive */ |
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396 | dctx->legacy_hw_ctx.rcs_state->base.write_domain = 0; |
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397 | dctx->legacy_hw_ctx.rcs_state->active = 0; |
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398 | } |
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399 | |||
400 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
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401 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
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402 | |||
403 | i915_gem_context_unreference(lctx); |
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404 | i915_gem_context_reference(dctx); |
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405 | ring->last_context = dctx; |
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406 | } |
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407 | } |
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408 | |||
4560 | Serge | 409 | int i915_gem_context_init(struct drm_device *dev) |
3031 | serge | 410 | { |
411 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 412 | struct intel_context *ctx; |
413 | int i; |
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3031 | serge | 414 | |
5060 | serge | 415 | /* Init should only be called once per module load. Eventually the |
416 | * restriction on the context_disabled check can be loosened. */ |
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417 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
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4560 | Serge | 418 | return 0; |
3031 | serge | 419 | |
5060 | serge | 420 | if (HAS_HW_CONTEXTS(dev)) { |
3480 | Serge | 421 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
422 | if (dev_priv->hw_context_size > (1<<20)) { |
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5060 | serge | 423 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
424 | dev_priv->hw_context_size); |
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425 | dev_priv->hw_context_size = 0; |
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426 | } |
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3031 | serge | 427 | } |
428 | |||
5060 | serge | 429 | ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev)); |
430 | if (IS_ERR(ctx)) { |
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431 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
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432 | PTR_ERR(ctx)); |
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433 | return PTR_ERR(ctx); |
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3031 | serge | 434 | } |
435 | |||
5060 | serge | 436 | /* NB: RCS will hold a ref for all rings */ |
437 | for (i = 0; i < I915_NUM_RINGS; i++) |
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438 | dev_priv->ring[i].default_context = ctx; |
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439 | |||
440 | DRM_DEBUG_DRIVER("%s context support initialized\n", dev_priv->hw_context_size ? "HW" : "fake"); |
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4560 | Serge | 441 | return 0; |
3031 | serge | 442 | } |
443 | |||
444 | void i915_gem_context_fini(struct drm_device *dev) |
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445 | { |
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446 | struct drm_i915_private *dev_priv = dev->dev_private; |
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5060 | serge | 447 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
448 | int i; |
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3031 | serge | 449 | |
5060 | serge | 450 | if (dctx->legacy_hw_ctx.rcs_state) { |
3031 | serge | 451 | /* The only known way to stop the gpu from accessing the hw context is |
452 | * to reset it. Do this as the very last operation to avoid confusing |
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453 | * other code, leading to spurious errors. */ |
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4104 | Serge | 454 | intel_gpu_reset(dev); |
3031 | serge | 455 | |
4104 | Serge | 456 | /* When default context is created and switched to, base object refcount |
457 | * will be 2 (+1 from object creation and +1 from do_switch()). |
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458 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
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459 | * to default context. So we need to unreference the base object once |
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460 | * to offset the do_switch part, so that i915_gem_context_unreference() |
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461 | * can then free the base object correctly. */ |
||
4560 | Serge | 462 | WARN_ON(!dev_priv->ring[RCS].last_context); |
463 | if (dev_priv->ring[RCS].last_context == dctx) { |
||
464 | /* Fake switch to NULL context */ |
||
5060 | serge | 465 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
466 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
||
4246 | Serge | 467 | i915_gem_context_unreference(dctx); |
5060 | serge | 468 | dev_priv->ring[RCS].last_context = NULL; |
4560 | Serge | 469 | } |
470 | |||
5060 | serge | 471 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
472 | } |
||
473 | |||
474 | for (i = 0; i < I915_NUM_RINGS; i++) { |
||
475 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
||
476 | |||
477 | if (ring->last_context) |
||
478 | i915_gem_context_unreference(ring->last_context); |
||
479 | |||
480 | ring->default_context = NULL; |
||
481 | ring->last_context = NULL; |
||
482 | } |
||
483 | |||
4560 | Serge | 484 | i915_gem_context_unreference(dctx); |
3031 | serge | 485 | } |
486 | |||
5060 | serge | 487 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
488 | { |
||
489 | struct intel_engine_cs *ring; |
||
490 | int ret, i; |
||
491 | |||
492 | /* This is the only place the aliasing PPGTT gets enabled, which means |
||
493 | * it has to happen before we bail on reset */ |
||
494 | if (dev_priv->mm.aliasing_ppgtt) { |
||
495 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
||
496 | ppgtt->enable(ppgtt); |
||
497 | } |
||
498 | |||
499 | /* FIXME: We should make this work, even in reset */ |
||
500 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
||
501 | return 0; |
||
502 | |||
503 | BUG_ON(!dev_priv->ring[RCS].default_context); |
||
504 | |||
505 | for_each_ring(ring, dev_priv, i) { |
||
506 | ret = i915_switch_context(ring, ring->default_context); |
||
507 | if (ret) |
||
508 | return ret; |
||
509 | } |
||
510 | |||
511 | return 0; |
||
512 | } |
||
513 | |||
3031 | serge | 514 | static int context_idr_cleanup(int id, void *p, void *data) |
515 | { |
||
5060 | serge | 516 | struct intel_context *ctx = p; |
3031 | serge | 517 | |
4280 | Serge | 518 | i915_gem_context_unreference(ctx); |
519 | return 0; |
||
520 | } |
||
3031 | serge | 521 | |
5060 | serge | 522 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
4280 | Serge | 523 | { |
524 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 525 | struct intel_context *ctx; |
4104 | Serge | 526 | |
5060 | serge | 527 | idr_init(&file_priv->context_idr); |
4280 | Serge | 528 | |
5060 | serge | 529 | mutex_lock(&dev->struct_mutex); |
530 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
||
531 | mutex_unlock(&dev->struct_mutex); |
||
4560 | Serge | 532 | |
5060 | serge | 533 | if (IS_ERR(ctx)) { |
534 | idr_destroy(&file_priv->context_idr); |
||
535 | return PTR_ERR(ctx); |
||
536 | } |
||
4280 | Serge | 537 | |
5060 | serge | 538 | return 0; |
3031 | serge | 539 | } |
540 | |||
541 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
||
542 | { |
||
543 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
544 | |||
4246 | Serge | 545 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
3031 | serge | 546 | idr_destroy(&file_priv->context_idr); |
547 | } |
||
548 | |||
5060 | serge | 549 | struct intel_context * |
3031 | serge | 550 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
551 | { |
||
5060 | serge | 552 | struct intel_context *ctx; |
553 | |||
554 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
||
555 | if (!ctx) |
||
556 | return ERR_PTR(-ENOENT); |
||
557 | |||
558 | return ctx; |
||
3031 | serge | 559 | } |
560 | |||
561 | static inline int |
||
5060 | serge | 562 | mi_set_context(struct intel_engine_cs *ring, |
563 | struct intel_context *new_context, |
||
3031 | serge | 564 | u32 hw_flags) |
565 | { |
||
566 | int ret; |
||
567 | |||
568 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
||
569 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
||
570 | * explicitly, so we rely on the value at ring init, stored in |
||
571 | * itlb_before_ctx_switch. |
||
572 | */ |
||
5060 | serge | 573 | if (IS_GEN6(ring->dev)) { |
3031 | serge | 574 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
575 | if (ret) |
||
576 | return ret; |
||
577 | } |
||
578 | |||
579 | ret = intel_ring_begin(ring, 6); |
||
580 | if (ret) |
||
581 | return ret; |
||
582 | |||
5060 | serge | 583 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
584 | if (INTEL_INFO(ring->dev)->gen >= 7) |
||
3031 | serge | 585 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
586 | else |
||
587 | intel_ring_emit(ring, MI_NOOP); |
||
588 | |||
589 | intel_ring_emit(ring, MI_NOOP); |
||
590 | intel_ring_emit(ring, MI_SET_CONTEXT); |
||
5060 | serge | 591 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | |
3031 | serge | 592 | MI_MM_SPACE_GTT | |
593 | MI_SAVE_EXT_STATE_EN | |
||
594 | MI_RESTORE_EXT_STATE_EN | |
||
595 | hw_flags); |
||
5060 | serge | 596 | /* |
597 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
||
598 | * WaMiSetContext_Hang:snb,ivb,vlv |
||
599 | */ |
||
3031 | serge | 600 | intel_ring_emit(ring, MI_NOOP); |
601 | |||
5060 | serge | 602 | if (INTEL_INFO(ring->dev)->gen >= 7) |
3031 | serge | 603 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
604 | else |
||
605 | intel_ring_emit(ring, MI_NOOP); |
||
606 | |||
607 | intel_ring_advance(ring); |
||
608 | |||
609 | return ret; |
||
610 | } |
||
611 | |||
5060 | serge | 612 | static int do_switch(struct intel_engine_cs *ring, |
613 | struct intel_context *to) |
||
3031 | serge | 614 | { |
5060 | serge | 615 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
616 | struct intel_context *from = ring->last_context; |
||
617 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); |
||
3031 | serge | 618 | u32 hw_flags = 0; |
5060 | serge | 619 | bool uninitialized = false; |
4560 | Serge | 620 | int ret, i; |
3031 | serge | 621 | |
5060 | serge | 622 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
623 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
||
624 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
||
625 | } |
||
3031 | serge | 626 | |
4560 | Serge | 627 | if (from == to && !to->remap_slice) |
3031 | serge | 628 | return 0; |
629 | |||
5060 | serge | 630 | /* Trying to pin first makes error handling easier. */ |
631 | if (ring == &dev_priv->ring[RCS]) { |
||
632 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
||
633 | get_context_alignment(ring->dev), 0); |
||
3031 | serge | 634 | if (ret) |
635 | return ret; |
||
5060 | serge | 636 | } |
3031 | serge | 637 | |
4539 | Serge | 638 | /* |
639 | * Pin can switch back to the default context if we end up calling into |
||
640 | * evict_everything - as a last ditch gtt defrag effort that also |
||
641 | * switches to the default context. Hence we need to reload from here. |
||
642 | */ |
||
643 | from = ring->last_context; |
||
644 | |||
5060 | serge | 645 | if (USES_FULL_PPGTT(ring->dev)) { |
646 | ret = ppgtt->switch_mm(ppgtt, ring, false); |
||
647 | if (ret) |
||
648 | goto unpin_out; |
||
649 | } |
||
650 | |||
651 | if (ring != &dev_priv->ring[RCS]) { |
||
652 | if (from) |
||
653 | i915_gem_context_unreference(from); |
||
654 | goto done; |
||
655 | } |
||
656 | |||
4539 | Serge | 657 | /* |
658 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
||
3031 | serge | 659 | * that thanks to write = false in this call and us not setting any gpu |
660 | * write domains when putting a context object onto the active list |
||
661 | * (when switching away from it), this won't block. |
||
4539 | Serge | 662 | * |
663 | * XXX: We need a real interface to do this instead of trickery. |
||
664 | */ |
||
5060 | serge | 665 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
666 | if (ret) |
||
667 | goto unpin_out; |
||
668 | |||
669 | if (!to->legacy_hw_ctx.rcs_state->has_global_gtt_mapping) { |
||
670 | struct i915_vma *vma = i915_gem_obj_to_vma(to->legacy_hw_ctx.rcs_state, |
||
671 | &dev_priv->gtt.base); |
||
672 | vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level, GLOBAL_BIND); |
||
3031 | serge | 673 | } |
674 | |||
5060 | serge | 675 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) |
3031 | serge | 676 | hw_flags |= MI_RESTORE_INHIBIT; |
677 | |||
678 | ret = mi_set_context(ring, to, hw_flags); |
||
5060 | serge | 679 | if (ret) |
680 | goto unpin_out; |
||
3031 | serge | 681 | |
4560 | Serge | 682 | for (i = 0; i < MAX_L3_SLICES; i++) { |
683 | if (!(to->remap_slice & (1< |
||
684 | continue; |
||
685 | |||
686 | ret = i915_gem_l3_remap(ring, i); |
||
687 | /* If it failed, try again next round */ |
||
688 | if (ret) |
||
689 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
||
690 | else |
||
691 | to->remap_slice &= ~(1< |
||
692 | } |
||
693 | |||
3031 | serge | 694 | /* The backing object for the context is done after switching to the |
695 | * *next* context. Therefore we cannot retire the previous context until |
||
696 | * the next context has already started running. In fact, the below code |
||
697 | * is a bit suboptimal because the retiring can occur simply after the |
||
698 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
||
699 | */ |
||
4104 | Serge | 700 | if (from != NULL) { |
5060 | serge | 701 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
702 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), ring); |
||
3031 | serge | 703 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
704 | * whole damn pipeline, we don't need to explicitly mark the |
||
705 | * object dirty. The only exception is that the context must be |
||
706 | * correct in case the object gets swapped out. Ideally we'd be |
||
707 | * able to defer doing this until we know the object would be |
||
708 | * swapped, but there is no way to do that yet. |
||
709 | */ |
||
5060 | serge | 710 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
711 | BUG_ON(from->legacy_hw_ctx.rcs_state->ring != ring); |
||
3031 | serge | 712 | |
4560 | Serge | 713 | /* obj is kept alive until the next request by its active ref */ |
5060 | serge | 714 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
4104 | Serge | 715 | i915_gem_context_unreference(from); |
3031 | serge | 716 | } |
717 | |||
5060 | serge | 718 | uninitialized = !to->legacy_hw_ctx.initialized && from == NULL; |
719 | to->legacy_hw_ctx.initialized = true; |
||
720 | |||
721 | done: |
||
4104 | Serge | 722 | i915_gem_context_reference(to); |
723 | ring->last_context = to; |
||
3031 | serge | 724 | |
5060 | serge | 725 | if (uninitialized) { |
726 | ret = i915_gem_render_state_init(ring); |
||
727 | if (ret) |
||
728 | DRM_ERROR("init render state: %d\n", ret); |
||
729 | } |
||
730 | |||
3031 | serge | 731 | return 0; |
5060 | serge | 732 | |
733 | unpin_out: |
||
734 | if (ring->id == RCS) |
||
735 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
||
736 | return ret; |
||
3031 | serge | 737 | } |
738 | |||
739 | /** |
||
740 | * i915_switch_context() - perform a GPU context switch. |
||
741 | * @ring: ring for which we'll execute the context switch |
||
5060 | serge | 742 | * @to: the context to switch to |
3031 | serge | 743 | * |
744 | * The context life cycle is simple. The context refcount is incremented and |
||
745 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
||
746 | * it will have a refoucnt > 1. This allows us to destroy the context abstract |
||
747 | * object while letting the normal object tracking destroy the backing BO. |
||
748 | */ |
||
5060 | serge | 749 | int i915_switch_context(struct intel_engine_cs *ring, |
750 | struct intel_context *to) |
||
3031 | serge | 751 | { |
752 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
||
753 | |||
4104 | Serge | 754 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
755 | |||
5060 | serge | 756 | if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
757 | if (to != ring->last_context) { |
||
758 | i915_gem_context_reference(to); |
||
759 | if (ring->last_context) |
||
760 | i915_gem_context_unreference(ring->last_context); |
||
761 | ring->last_context = to; |
||
762 | } |
||
3031 | serge | 763 | return 0; |
764 | } |
||
765 | |||
5060 | serge | 766 | return do_switch(ring, to); |
3031 | serge | 767 | } |
768 | |||
5060 | serge | 769 | static bool hw_context_enabled(struct drm_device *dev) |
770 | { |
||
771 | return to_i915(dev)->hw_context_size; |
||
772 | } |
||
773 | |||
3031 | serge | 774 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
775 | struct drm_file *file) |
||
776 | { |
||
777 | struct drm_i915_gem_context_create *args = data; |
||
778 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 779 | struct intel_context *ctx; |
3031 | serge | 780 | int ret; |
781 | |||
5060 | serge | 782 | if (!hw_context_enabled(dev)) |
3031 | serge | 783 | return -ENODEV; |
784 | |||
785 | ret = i915_mutex_lock_interruptible(dev); |
||
786 | if (ret) |
||
787 | return ret; |
||
788 | |||
5060 | serge | 789 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
3031 | serge | 790 | mutex_unlock(&dev->struct_mutex); |
791 | if (IS_ERR(ctx)) |
||
792 | return PTR_ERR(ctx); |
||
793 | |||
5060 | serge | 794 | args->ctx_id = ctx->user_handle; |
3031 | serge | 795 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
796 | |||
797 | return 0; |
||
798 | } |
||
799 | |||
800 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
||
801 | struct drm_file *file) |
||
802 | { |
||
803 | struct drm_i915_gem_context_destroy *args = data; |
||
804 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
5060 | serge | 805 | struct intel_context *ctx; |
3031 | serge | 806 | int ret; |
807 | |||
5060 | serge | 808 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
809 | return -ENOENT; |
||
3031 | serge | 810 | |
811 | ret = i915_mutex_lock_interruptible(dev); |
||
812 | if (ret) |
||
813 | return ret; |
||
814 | |||
815 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
||
5060 | serge | 816 | if (IS_ERR(ctx)) { |
3031 | serge | 817 | mutex_unlock(&dev->struct_mutex); |
5060 | serge | 818 | return PTR_ERR(ctx); |
3031 | serge | 819 | } |
820 | |||
5060 | serge | 821 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
4246 | Serge | 822 | i915_gem_context_unreference(ctx); |
3031 | serge | 823 | mutex_unlock(&dev->struct_mutex); |
824 | |||
825 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
||
826 | return 0; |
||
827 | } |