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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
3031 | serge | 28 | #include |
29 | #include |
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2326 | Serge | 30 | #include "i915_drv.h" |
2351 | Serge | 31 | #include "i915_trace.h" |
2326 | Serge | 32 | #include "intel_drv.h" |
3260 | Serge | 33 | #include |
2330 | Serge | 34 | #include |
2326 | Serge | 35 | //#include |
36 | #include |
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37 | |||
2344 | Serge | 38 | extern int x86_clflush_size; |
2332 | Serge | 39 | |
3263 | Serge | 40 | #define PROT_READ 0x1 /* page can be read */ |
41 | #define PROT_WRITE 0x2 /* page can be written */ |
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42 | #define MAP_SHARED 0x01 /* Share changes */ |
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43 | |||
2344 | Serge | 44 | #undef mb |
45 | #undef rmb |
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46 | #undef wmb |
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47 | #define mb() asm volatile("mfence") |
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48 | #define rmb() asm volatile ("lfence") |
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49 | #define wmb() asm volatile ("sfence") |
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50 | |||
3266 | Serge | 51 | struct drm_i915_gem_object *get_fb_obj(); |
52 | |||
3263 | Serge | 53 | unsigned long vm_mmap(struct file *file, unsigned long addr, |
54 | unsigned long len, unsigned long prot, |
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55 | unsigned long flag, unsigned long offset); |
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56 | |||
2344 | Serge | 57 | static inline void clflush(volatile void *__p) |
58 | { |
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59 | asm volatile("clflush %0" : "+m" (*(volatile char*)__p)); |
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60 | } |
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61 | |||
2332 | Serge | 62 | #define MAX_ERRNO 4095 |
63 | |||
64 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
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65 | |||
66 | |||
2326 | Serge | 67 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
68 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
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69 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
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70 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
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71 | |||
2332 | Serge | 72 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
73 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
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74 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
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75 | unsigned alignment, |
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3031 | serge | 76 | bool map_and_fenceable, |
77 | bool nonblocking); |
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2332 | Serge | 78 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
79 | struct drm_i915_gem_object *obj, |
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80 | struct drm_i915_gem_pwrite *args, |
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81 | struct drm_file *file); |
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2326 | Serge | 82 | |
3031 | serge | 83 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
84 | struct drm_i915_gem_object *obj); |
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85 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
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86 | struct drm_i915_fence_reg *fence, |
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87 | bool enable); |
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2332 | Serge | 88 | |
3031 | serge | 89 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
90 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
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91 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
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92 | |||
93 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
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94 | { |
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95 | if (obj->tiling_mode) |
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96 | i915_gem_release_mmap(obj); |
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97 | |||
98 | /* As we do not have an associated fence register, we will force |
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99 | * a tiling change if we ever need to acquire one. |
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100 | */ |
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101 | obj->fence_dirty = false; |
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102 | obj->fence_reg = I915_FENCE_REG_NONE; |
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103 | } |
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104 | |||
2332 | Serge | 105 | /* some bookkeeping */ |
106 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
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107 | size_t size) |
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108 | { |
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109 | dev_priv->mm.object_count++; |
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110 | dev_priv->mm.object_memory += size; |
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111 | } |
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112 | |||
113 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
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114 | size_t size) |
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115 | { |
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116 | dev_priv->mm.object_count--; |
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117 | dev_priv->mm.object_memory -= size; |
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118 | } |
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119 | |||
120 | static int |
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3480 | Serge | 121 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
2332 | Serge | 122 | { |
123 | int ret; |
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124 | |||
3480 | Serge | 125 | #define EXIT_COND (!i915_reset_in_progress(error)) |
126 | if (EXIT_COND) |
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2332 | Serge | 127 | return 0; |
3255 | Serge | 128 | #if 0 |
3031 | serge | 129 | /* |
130 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
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131 | * userspace. If it takes that long something really bad is going on and |
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132 | * we should simply try to bail out and fail as gracefully as possible. |
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133 | */ |
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3480 | Serge | 134 | ret = wait_event_interruptible_timeout(error->reset_queue, |
135 | EXIT_COND, |
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136 | 10*HZ); |
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3031 | serge | 137 | if (ret == 0) { |
138 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
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139 | return -EIO; |
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140 | } else if (ret < 0) { |
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2332 | Serge | 141 | return ret; |
3031 | serge | 142 | } |
2332 | Serge | 143 | |
3255 | Serge | 144 | #endif |
3480 | Serge | 145 | #undef EXIT_COND |
3255 | Serge | 146 | |
2332 | Serge | 147 | return 0; |
148 | } |
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149 | |||
150 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
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151 | { |
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3480 | Serge | 152 | struct drm_i915_private *dev_priv = dev->dev_private; |
2332 | Serge | 153 | int ret; |
154 | |||
3480 | Serge | 155 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
2332 | Serge | 156 | if (ret) |
157 | return ret; |
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158 | |||
3480 | Serge | 159 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
160 | if (ret) |
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161 | return ret; |
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2332 | Serge | 162 | |
163 | WARN_ON(i915_verify_lists(dev)); |
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164 | return 0; |
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165 | } |
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166 | |||
167 | static inline bool |
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168 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
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169 | { |
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3031 | serge | 170 | return obj->gtt_space && !obj->active; |
2332 | Serge | 171 | } |
172 | |||
173 | |||
174 | #if 0 |
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175 | |||
176 | int |
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177 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
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178 | struct drm_file *file) |
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179 | { |
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3480 | Serge | 180 | struct drm_i915_private *dev_priv = dev->dev_private; |
2332 | Serge | 181 | struct drm_i915_gem_init *args = data; |
182 | |||
3031 | serge | 183 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
184 | return -ENODEV; |
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185 | |||
2332 | Serge | 186 | if (args->gtt_start >= args->gtt_end || |
187 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
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188 | return -EINVAL; |
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189 | |||
3031 | serge | 190 | /* GEM with user mode setting was never supported on ilk and later. */ |
191 | if (INTEL_INFO(dev)->gen >= 5) |
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192 | return -ENODEV; |
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193 | |||
2332 | Serge | 194 | mutex_lock(&dev->struct_mutex); |
3480 | Serge | 195 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
196 | args->gtt_end); |
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197 | dev_priv->gtt.mappable_end = args->gtt_end; |
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2332 | Serge | 198 | mutex_unlock(&dev->struct_mutex); |
199 | |||
200 | return 0; |
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201 | } |
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2351 | Serge | 202 | #endif |
2332 | Serge | 203 | |
204 | int |
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205 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
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206 | struct drm_file *file) |
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207 | { |
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208 | struct drm_i915_private *dev_priv = dev->dev_private; |
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209 | struct drm_i915_gem_get_aperture *args = data; |
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210 | struct drm_i915_gem_object *obj; |
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211 | size_t pinned; |
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212 | |||
213 | pinned = 0; |
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214 | mutex_lock(&dev->struct_mutex); |
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3031 | serge | 215 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
216 | if (obj->pin_count) |
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2332 | Serge | 217 | pinned += obj->gtt_space->size; |
218 | mutex_unlock(&dev->struct_mutex); |
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219 | |||
3480 | Serge | 220 | args->aper_size = dev_priv->gtt.total; |
2342 | Serge | 221 | args->aper_available_size = args->aper_size - pinned; |
2332 | Serge | 222 | |
223 | return 0; |
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224 | } |
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225 | |||
3480 | Serge | 226 | void *i915_gem_object_alloc(struct drm_device *dev) |
227 | { |
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228 | struct drm_i915_private *dev_priv = dev->dev_private; |
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229 | return kmalloc(sizeof(struct drm_i915_gem_object), 0); |
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230 | } |
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231 | |||
232 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
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233 | { |
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234 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
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235 | kfree(obj); |
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236 | } |
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237 | |||
3031 | serge | 238 | static int |
239 | i915_gem_create(struct drm_file *file, |
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2332 | Serge | 240 | struct drm_device *dev, |
241 | uint64_t size, |
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242 | uint32_t *handle_p) |
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243 | { |
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244 | struct drm_i915_gem_object *obj; |
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245 | int ret; |
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246 | u32 handle; |
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247 | |||
248 | size = roundup(size, PAGE_SIZE); |
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2342 | Serge | 249 | if (size == 0) |
250 | return -EINVAL; |
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2332 | Serge | 251 | |
252 | /* Allocate the new object */ |
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253 | obj = i915_gem_alloc_object(dev, size); |
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254 | if (obj == NULL) |
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255 | return -ENOMEM; |
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256 | |||
257 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
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258 | if (ret) { |
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259 | drm_gem_object_release(&obj->base); |
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260 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
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261 | kfree(obj); |
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262 | return ret; |
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263 | } |
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264 | |||
265 | /* drop reference from allocate - handle holds it now */ |
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266 | drm_gem_object_unreference(&obj->base); |
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2351 | Serge | 267 | trace_i915_gem_object_create(obj); |
2332 | Serge | 268 | |
269 | *handle_p = handle; |
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270 | return 0; |
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271 | } |
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272 | |||
273 | int |
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274 | i915_gem_dumb_create(struct drm_file *file, |
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275 | struct drm_device *dev, |
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276 | struct drm_mode_create_dumb *args) |
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277 | { |
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278 | /* have to work out size/pitch and return them */ |
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279 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
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280 | args->size = args->pitch * args->height; |
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281 | return i915_gem_create(file, dev, |
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282 | args->size, &args->handle); |
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283 | } |
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284 | |||
285 | int i915_gem_dumb_destroy(struct drm_file *file, |
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286 | struct drm_device *dev, |
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287 | uint32_t handle) |
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288 | { |
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289 | return drm_gem_handle_delete(file, handle); |
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290 | } |
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291 | |||
2326 | Serge | 292 | /** |
2332 | Serge | 293 | * Creates a new mm object and returns a handle to it. |
294 | */ |
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295 | int |
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296 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
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297 | struct drm_file *file) |
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298 | { |
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299 | struct drm_i915_gem_create *args = data; |
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3031 | serge | 300 | |
2332 | Serge | 301 | return i915_gem_create(file, dev, |
302 | args->size, &args->handle); |
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303 | } |
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304 | |||
305 | |||
3260 | Serge | 306 | #if 0 |
2332 | Serge | 307 | |
3031 | serge | 308 | static inline int |
309 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
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310 | const char *gpu_vaddr, int gpu_offset, |
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2332 | Serge | 311 | int length) |
312 | { |
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3031 | serge | 313 | int ret, cpu_offset = 0; |
2332 | Serge | 314 | |
3031 | serge | 315 | while (length > 0) { |
316 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
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317 | int this_length = min(cacheline_end - gpu_offset, length); |
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318 | int swizzled_gpu_offset = gpu_offset ^ 64; |
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2332 | Serge | 319 | |
3031 | serge | 320 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
321 | gpu_vaddr + swizzled_gpu_offset, |
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322 | this_length); |
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323 | if (ret) |
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324 | return ret + length; |
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2332 | Serge | 325 | |
3031 | serge | 326 | cpu_offset += this_length; |
327 | gpu_offset += this_length; |
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328 | length -= this_length; |
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329 | } |
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330 | |||
331 | return 0; |
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2332 | Serge | 332 | } |
333 | |||
3031 | serge | 334 | static inline int |
335 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
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336 | const char __user *cpu_vaddr, |
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337 | int length) |
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2332 | Serge | 338 | { |
3031 | serge | 339 | int ret, cpu_offset = 0; |
2332 | Serge | 340 | |
341 | while (length > 0) { |
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342 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
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343 | int this_length = min(cacheline_end - gpu_offset, length); |
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344 | int swizzled_gpu_offset = gpu_offset ^ 64; |
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345 | |||
3031 | serge | 346 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
2332 | Serge | 347 | cpu_vaddr + cpu_offset, |
348 | this_length); |
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3031 | serge | 349 | if (ret) |
350 | return ret + length; |
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351 | |||
2332 | Serge | 352 | cpu_offset += this_length; |
353 | gpu_offset += this_length; |
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354 | length -= this_length; |
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355 | } |
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356 | |||
3031 | serge | 357 | return 0; |
2332 | Serge | 358 | } |
359 | |||
3031 | serge | 360 | /* Per-page copy function for the shmem pread fastpath. |
361 | * Flushes invalid cachelines before reading the target if |
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362 | * needs_clflush is set. */ |
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2332 | Serge | 363 | static int |
3031 | serge | 364 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
365 | char __user *user_data, |
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366 | bool page_do_bit17_swizzling, bool needs_clflush) |
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367 | { |
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368 | char *vaddr; |
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369 | int ret; |
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370 | |||
371 | if (unlikely(page_do_bit17_swizzling)) |
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372 | return -EINVAL; |
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373 | |||
374 | vaddr = kmap_atomic(page); |
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375 | if (needs_clflush) |
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376 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
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377 | page_length); |
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378 | ret = __copy_to_user_inatomic(user_data, |
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379 | vaddr + shmem_page_offset, |
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380 | page_length); |
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381 | kunmap_atomic(vaddr); |
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382 | |||
383 | return ret ? -EFAULT : 0; |
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384 | } |
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385 | |||
386 | static void |
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387 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
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388 | bool swizzled) |
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389 | { |
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390 | if (unlikely(swizzled)) { |
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391 | unsigned long start = (unsigned long) addr; |
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392 | unsigned long end = (unsigned long) addr + length; |
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393 | |||
394 | /* For swizzling simply ensure that we always flush both |
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395 | * channels. Lame, but simple and it works. Swizzled |
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396 | * pwrite/pread is far from a hotpath - current userspace |
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397 | * doesn't use it at all. */ |
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398 | start = round_down(start, 128); |
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399 | end = round_up(end, 128); |
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400 | |||
401 | drm_clflush_virt_range((void *)start, end - start); |
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402 | } else { |
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403 | drm_clflush_virt_range(addr, length); |
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404 | } |
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405 | |||
406 | } |
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407 | |||
408 | /* Only difference to the fast-path function is that this can handle bit17 |
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409 | * and uses non-atomic copy and kmap functions. */ |
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410 | static int |
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411 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
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412 | char __user *user_data, |
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413 | bool page_do_bit17_swizzling, bool needs_clflush) |
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414 | { |
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415 | char *vaddr; |
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416 | int ret; |
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417 | |||
418 | vaddr = kmap(page); |
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419 | if (needs_clflush) |
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420 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
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421 | page_length, |
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422 | page_do_bit17_swizzling); |
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423 | |||
424 | if (page_do_bit17_swizzling) |
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425 | ret = __copy_to_user_swizzled(user_data, |
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426 | vaddr, shmem_page_offset, |
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427 | page_length); |
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428 | else |
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429 | ret = __copy_to_user(user_data, |
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430 | vaddr + shmem_page_offset, |
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431 | page_length); |
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432 | kunmap(page); |
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433 | |||
434 | return ret ? - EFAULT : 0; |
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435 | } |
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436 | |||
437 | static int |
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438 | i915_gem_shmem_pread(struct drm_device *dev, |
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2332 | Serge | 439 | struct drm_i915_gem_object *obj, |
440 | struct drm_i915_gem_pread *args, |
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441 | struct drm_file *file) |
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442 | { |
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3031 | serge | 443 | char __user *user_data; |
2332 | Serge | 444 | ssize_t remain; |
445 | loff_t offset; |
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3031 | serge | 446 | int shmem_page_offset, page_length, ret = 0; |
447 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
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448 | int prefaulted = 0; |
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449 | int needs_clflush = 0; |
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450 | struct scatterlist *sg; |
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451 | int i; |
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2332 | Serge | 452 | |
453 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
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454 | remain = args->size; |
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455 | |||
3031 | serge | 456 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
457 | |||
458 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
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459 | /* If we're not in the cpu read domain, set ourself into the gtt |
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460 | * read domain and manually flush cachelines (if required). This |
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461 | * optimizes for the case when the gpu will dirty the data |
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462 | * anyway again before the next pread happens. */ |
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463 | if (obj->cache_level == I915_CACHE_NONE) |
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464 | needs_clflush = 1; |
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465 | if (obj->gtt_space) { |
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466 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
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467 | if (ret) |
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468 | return ret; |
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469 | } |
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470 | } |
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471 | |||
472 | ret = i915_gem_object_get_pages(obj); |
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473 | if (ret) |
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474 | return ret; |
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475 | |||
476 | i915_gem_object_pin_pages(obj); |
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477 | |||
2332 | Serge | 478 | offset = args->offset; |
479 | |||
3031 | serge | 480 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
2332 | Serge | 481 | struct page *page; |
482 | |||
3031 | serge | 483 | if (i < offset >> PAGE_SHIFT) |
484 | continue; |
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485 | |||
486 | if (remain <= 0) |
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487 | break; |
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488 | |||
2332 | Serge | 489 | /* Operation in this page |
490 | * |
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3031 | serge | 491 | * shmem_page_offset = offset within page in shmem file |
2332 | Serge | 492 | * page_length = bytes to copy for this page |
493 | */ |
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3031 | serge | 494 | shmem_page_offset = offset_in_page(offset); |
2332 | Serge | 495 | page_length = remain; |
3031 | serge | 496 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
497 | page_length = PAGE_SIZE - shmem_page_offset; |
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2332 | Serge | 498 | |
3031 | serge | 499 | page = sg_page(sg); |
500 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
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501 | (page_to_phys(page) & (1 << 17)) != 0; |
||
2332 | Serge | 502 | |
3031 | serge | 503 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
504 | user_data, page_do_bit17_swizzling, |
||
505 | needs_clflush); |
||
506 | if (ret == 0) |
||
507 | goto next_page; |
||
2332 | Serge | 508 | |
3031 | serge | 509 | mutex_unlock(&dev->struct_mutex); |
510 | |||
511 | if (!prefaulted) { |
||
512 | ret = fault_in_multipages_writeable(user_data, remain); |
||
513 | /* Userspace is tricking us, but we've already clobbered |
||
514 | * its pages with the prefault and promised to write the |
||
515 | * data up to the first fault. Hence ignore any errors |
||
516 | * and just continue. */ |
||
517 | (void)ret; |
||
518 | prefaulted = 1; |
||
519 | } |
||
520 | |||
521 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
||
522 | user_data, page_do_bit17_swizzling, |
||
523 | needs_clflush); |
||
524 | |||
525 | mutex_lock(&dev->struct_mutex); |
||
526 | |||
527 | next_page: |
||
2332 | Serge | 528 | mark_page_accessed(page); |
3031 | serge | 529 | |
2332 | Serge | 530 | if (ret) |
3031 | serge | 531 | goto out; |
2332 | Serge | 532 | |
533 | remain -= page_length; |
||
534 | user_data += page_length; |
||
535 | offset += page_length; |
||
536 | } |
||
537 | |||
3031 | serge | 538 | out: |
539 | i915_gem_object_unpin_pages(obj); |
||
540 | |||
541 | return ret; |
||
2332 | Serge | 542 | } |
543 | |||
544 | /** |
||
3031 | serge | 545 | * Reads data from the object referenced by handle. |
546 | * |
||
547 | * On error, the contents of *data are undefined. |
||
2332 | Serge | 548 | */ |
3031 | serge | 549 | int |
550 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
||
551 | struct drm_file *file) |
||
552 | { |
||
553 | struct drm_i915_gem_pread *args = data; |
||
554 | struct drm_i915_gem_object *obj; |
||
555 | int ret = 0; |
||
556 | |||
557 | if (args->size == 0) |
||
558 | return 0; |
||
559 | |||
560 | if (!access_ok(VERIFY_WRITE, |
||
561 | (char __user *)(uintptr_t)args->data_ptr, |
||
562 | args->size)) |
||
563 | return -EFAULT; |
||
564 | |||
565 | ret = i915_mutex_lock_interruptible(dev); |
||
566 | if (ret) |
||
567 | return ret; |
||
568 | |||
569 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
||
570 | if (&obj->base == NULL) { |
||
571 | ret = -ENOENT; |
||
572 | goto unlock; |
||
573 | } |
||
574 | |||
575 | /* Bounds check source. */ |
||
576 | if (args->offset > obj->base.size || |
||
577 | args->size > obj->base.size - args->offset) { |
||
578 | ret = -EINVAL; |
||
579 | goto out; |
||
580 | } |
||
581 | |||
582 | /* prime objects have no backing filp to GEM pread/pwrite |
||
583 | * pages from. |
||
584 | */ |
||
585 | if (!obj->base.filp) { |
||
586 | ret = -EINVAL; |
||
587 | goto out; |
||
588 | } |
||
589 | |||
590 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
||
591 | |||
592 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
||
593 | |||
594 | out: |
||
595 | drm_gem_object_unreference(&obj->base); |
||
596 | unlock: |
||
597 | mutex_unlock(&dev->struct_mutex); |
||
598 | return ret; |
||
599 | } |
||
600 | |||
601 | /* This is the fast write path which cannot handle |
||
602 | * page faults in the source data |
||
603 | */ |
||
604 | |||
605 | static inline int |
||
606 | fast_user_write(struct io_mapping *mapping, |
||
607 | loff_t page_base, int page_offset, |
||
608 | char __user *user_data, |
||
609 | int length) |
||
610 | { |
||
611 | void __iomem *vaddr_atomic; |
||
612 | void *vaddr; |
||
613 | unsigned long unwritten; |
||
614 | |||
615 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
||
616 | /* We can use the cpu mem copy function because this is X86. */ |
||
617 | vaddr = (void __force*)vaddr_atomic + page_offset; |
||
618 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
||
619 | user_data, length); |
||
620 | io_mapping_unmap_atomic(vaddr_atomic); |
||
621 | return unwritten; |
||
622 | } |
||
3260 | Serge | 623 | #endif |
3031 | serge | 624 | |
3260 | Serge | 625 | #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) |
3031 | serge | 626 | /** |
627 | * This is the fast pwrite path, where we copy the data directly from the |
||
628 | * user into the GTT, uncached. |
||
629 | */ |
||
2332 | Serge | 630 | static int |
3031 | serge | 631 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
632 | struct drm_i915_gem_object *obj, |
||
633 | struct drm_i915_gem_pwrite *args, |
||
634 | struct drm_file *file) |
||
2332 | Serge | 635 | { |
3031 | serge | 636 | drm_i915_private_t *dev_priv = dev->dev_private; |
2332 | Serge | 637 | ssize_t remain; |
3031 | serge | 638 | loff_t offset, page_base; |
639 | char __user *user_data; |
||
640 | int page_offset, page_length, ret; |
||
3260 | Serge | 641 | char *vaddr; |
2332 | Serge | 642 | |
3031 | serge | 643 | ret = i915_gem_object_pin(obj, 0, true, true); |
644 | if (ret) |
||
645 | goto out; |
||
646 | |||
647 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
||
648 | if (ret) |
||
649 | goto out_unpin; |
||
650 | |||
651 | ret = i915_gem_object_put_fence(obj); |
||
652 | if (ret) |
||
653 | goto out_unpin; |
||
654 | |||
3260 | Serge | 655 | vaddr = AllocKernelSpace(4096); |
656 | if(vaddr == NULL) |
||
657 | { |
||
658 | ret = -ENOSPC; |
||
659 | goto out_unpin; |
||
660 | }; |
||
661 | |||
3031 | serge | 662 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
2332 | Serge | 663 | remain = args->size; |
664 | |||
3031 | serge | 665 | offset = obj->gtt_offset + args->offset; |
2332 | Serge | 666 | |
3031 | serge | 667 | while (remain > 0) { |
668 | /* Operation in this page |
||
669 | * |
||
670 | * page_base = page offset within aperture |
||
671 | * page_offset = offset within page |
||
672 | * page_length = bytes to copy for this page |
||
673 | */ |
||
674 | page_base = offset & PAGE_MASK; |
||
675 | page_offset = offset_in_page(offset); |
||
676 | page_length = remain; |
||
677 | if ((page_offset + remain) > PAGE_SIZE) |
||
678 | page_length = PAGE_SIZE - page_offset; |
||
2332 | Serge | 679 | |
3260 | Serge | 680 | MapPage(vaddr, page_base, PG_SW|PG_NOCACHE); |
3031 | serge | 681 | |
3260 | Serge | 682 | memcpy(vaddr+page_offset, user_data, page_length); |
683 | |||
3031 | serge | 684 | remain -= page_length; |
685 | user_data += page_length; |
||
686 | offset += page_length; |
||
2332 | Serge | 687 | } |
688 | |||
3260 | Serge | 689 | FreeKernelSpace(vaddr); |
690 | |||
3031 | serge | 691 | out_unpin: |
692 | i915_gem_object_unpin(obj); |
||
693 | out: |
||
694 | return ret; |
||
695 | } |
||
696 | |||
697 | /* Per-page copy function for the shmem pwrite fastpath. |
||
698 | * Flushes invalid cachelines before writing to the target if |
||
699 | * needs_clflush_before is set and flushes out any written cachelines after |
||
700 | * writing if needs_clflush is set. */ |
||
701 | static int |
||
702 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
||
703 | char __user *user_data, |
||
704 | bool page_do_bit17_swizzling, |
||
705 | bool needs_clflush_before, |
||
706 | bool needs_clflush_after) |
||
707 | { |
||
708 | char *vaddr; |
||
3260 | Serge | 709 | int ret = 0; |
3031 | serge | 710 | |
711 | if (unlikely(page_do_bit17_swizzling)) |
||
712 | return -EINVAL; |
||
713 | |||
3260 | Serge | 714 | vaddr = (char *)MapIoMem((addr_t)page, 4096, PG_SW); |
3031 | serge | 715 | if (needs_clflush_before) |
716 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
||
717 | page_length); |
||
3260 | Serge | 718 | memcpy(vaddr + shmem_page_offset, |
3031 | serge | 719 | user_data, |
720 | page_length); |
||
721 | if (needs_clflush_after) |
||
722 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
||
723 | page_length); |
||
3260 | Serge | 724 | FreeKernelSpace(vaddr); |
3031 | serge | 725 | |
726 | return ret ? -EFAULT : 0; |
||
727 | } |
||
3260 | Serge | 728 | #if 0 |
3031 | serge | 729 | |
730 | /* Only difference to the fast-path function is that this can handle bit17 |
||
731 | * and uses non-atomic copy and kmap functions. */ |
||
732 | static int |
||
733 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
||
734 | char __user *user_data, |
||
735 | bool page_do_bit17_swizzling, |
||
736 | bool needs_clflush_before, |
||
737 | bool needs_clflush_after) |
||
738 | { |
||
739 | char *vaddr; |
||
740 | int ret; |
||
741 | |||
742 | vaddr = kmap(page); |
||
743 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
||
744 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
||
745 | page_length, |
||
746 | page_do_bit17_swizzling); |
||
747 | if (page_do_bit17_swizzling) |
||
748 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
||
749 | user_data, |
||
750 | page_length); |
||
751 | else |
||
752 | ret = __copy_from_user(vaddr + shmem_page_offset, |
||
753 | user_data, |
||
754 | page_length); |
||
755 | if (needs_clflush_after) |
||
756 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
||
757 | page_length, |
||
758 | page_do_bit17_swizzling); |
||
759 | kunmap(page); |
||
760 | |||
761 | return ret ? -EFAULT : 0; |
||
762 | } |
||
3260 | Serge | 763 | #endif |
3031 | serge | 764 | |
3260 | Serge | 765 | |
3031 | serge | 766 | static int |
767 | i915_gem_shmem_pwrite(struct drm_device *dev, |
||
768 | struct drm_i915_gem_object *obj, |
||
769 | struct drm_i915_gem_pwrite *args, |
||
770 | struct drm_file *file) |
||
771 | { |
||
772 | ssize_t remain; |
||
773 | loff_t offset; |
||
774 | char __user *user_data; |
||
775 | int shmem_page_offset, page_length, ret = 0; |
||
776 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
||
777 | int hit_slowpath = 0; |
||
778 | int needs_clflush_after = 0; |
||
779 | int needs_clflush_before = 0; |
||
780 | int i; |
||
781 | struct scatterlist *sg; |
||
782 | |||
783 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
||
784 | remain = args->size; |
||
785 | |||
786 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
||
787 | |||
788 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
||
789 | /* If we're not in the cpu write domain, set ourself into the gtt |
||
790 | * write domain and manually flush cachelines (if required). This |
||
791 | * optimizes for the case when the gpu will use the data |
||
792 | * right away and we therefore have to clflush anyway. */ |
||
793 | if (obj->cache_level == I915_CACHE_NONE) |
||
794 | needs_clflush_after = 1; |
||
795 | if (obj->gtt_space) { |
||
796 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
||
797 | if (ret) |
||
798 | return ret; |
||
799 | } |
||
800 | } |
||
801 | /* Same trick applies for invalidate partially written cachelines before |
||
802 | * writing. */ |
||
803 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
||
804 | && obj->cache_level == I915_CACHE_NONE) |
||
805 | needs_clflush_before = 1; |
||
806 | |||
807 | ret = i915_gem_object_get_pages(obj); |
||
2332 | Serge | 808 | if (ret) |
3031 | serge | 809 | return ret; |
2332 | Serge | 810 | |
3031 | serge | 811 | i915_gem_object_pin_pages(obj); |
2332 | Serge | 812 | |
813 | offset = args->offset; |
||
3031 | serge | 814 | obj->dirty = 1; |
2332 | Serge | 815 | |
3031 | serge | 816 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
2332 | Serge | 817 | struct page *page; |
3031 | serge | 818 | int partial_cacheline_write; |
2332 | Serge | 819 | |
3031 | serge | 820 | if (i < offset >> PAGE_SHIFT) |
821 | continue; |
||
822 | |||
823 | if (remain <= 0) |
||
824 | break; |
||
825 | |||
2332 | Serge | 826 | /* Operation in this page |
827 | * |
||
828 | * shmem_page_offset = offset within page in shmem file |
||
829 | * page_length = bytes to copy for this page |
||
830 | */ |
||
831 | shmem_page_offset = offset_in_page(offset); |
||
832 | |||
833 | page_length = remain; |
||
834 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
||
835 | page_length = PAGE_SIZE - shmem_page_offset; |
||
836 | |||
3031 | serge | 837 | /* If we don't overwrite a cacheline completely we need to be |
838 | * careful to have up-to-date data by first clflushing. Don't |
||
839 | * overcomplicate things and flush the entire patch. */ |
||
840 | partial_cacheline_write = needs_clflush_before && |
||
841 | ((shmem_page_offset | page_length) |
||
3260 | Serge | 842 | & (x86_clflush_size - 1)); |
2332 | Serge | 843 | |
3031 | serge | 844 | page = sg_page(sg); |
845 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
||
846 | (page_to_phys(page) & (1 << 17)) != 0; |
||
2332 | Serge | 847 | |
3031 | serge | 848 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
849 | user_data, page_do_bit17_swizzling, |
||
850 | partial_cacheline_write, |
||
851 | needs_clflush_after); |
||
852 | if (ret == 0) |
||
853 | goto next_page; |
||
854 | |||
855 | hit_slowpath = 1; |
||
856 | mutex_unlock(&dev->struct_mutex); |
||
3260 | Serge | 857 | dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__); |
3031 | serge | 858 | |
3260 | Serge | 859 | // ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
860 | // user_data, page_do_bit17_swizzling, |
||
861 | // partial_cacheline_write, |
||
862 | // needs_clflush_after); |
||
863 | |||
3031 | serge | 864 | mutex_lock(&dev->struct_mutex); |
865 | |||
866 | next_page: |
||
2332 | Serge | 867 | |
3031 | serge | 868 | if (ret) |
869 | goto out; |
||
870 | |||
2332 | Serge | 871 | remain -= page_length; |
3031 | serge | 872 | user_data += page_length; |
2332 | Serge | 873 | offset += page_length; |
874 | } |
||
875 | |||
876 | out: |
||
3031 | serge | 877 | i915_gem_object_unpin_pages(obj); |
878 | |||
879 | if (hit_slowpath) { |
||
3480 | Serge | 880 | /* |
881 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
||
882 | * cachelines in-line while writing and the object moved |
||
883 | * out of the cpu write domain while we've dropped the lock. |
||
884 | */ |
||
885 | if (!needs_clflush_after && |
||
886 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
||
3031 | serge | 887 | i915_gem_clflush_object(obj); |
3243 | Serge | 888 | i915_gem_chipset_flush(dev); |
3031 | serge | 889 | } |
2332 | Serge | 890 | } |
891 | |||
3031 | serge | 892 | if (needs_clflush_after) |
3243 | Serge | 893 | i915_gem_chipset_flush(dev); |
3031 | serge | 894 | |
2332 | Serge | 895 | return ret; |
896 | } |
||
3031 | serge | 897 | |
898 | /** |
||
899 | * Writes data to the object referenced by handle. |
||
900 | * |
||
901 | * On error, the contents of the buffer that were to be modified are undefined. |
||
902 | */ |
||
903 | int |
||
904 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
||
905 | struct drm_file *file) |
||
906 | { |
||
907 | struct drm_i915_gem_pwrite *args = data; |
||
908 | struct drm_i915_gem_object *obj; |
||
909 | int ret; |
||
910 | |||
3480 | Serge | 911 | if(args->handle == -2) |
912 | { |
||
913 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
914 | return 0; |
||
915 | } |
||
916 | |||
3031 | serge | 917 | if (args->size == 0) |
918 | return 0; |
||
919 | |||
920 | ret = i915_mutex_lock_interruptible(dev); |
||
921 | if (ret) |
||
922 | return ret; |
||
923 | |||
924 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
||
925 | if (&obj->base == NULL) { |
||
926 | ret = -ENOENT; |
||
927 | goto unlock; |
||
928 | } |
||
929 | |||
930 | /* Bounds check destination. */ |
||
931 | if (args->offset > obj->base.size || |
||
932 | args->size > obj->base.size - args->offset) { |
||
933 | ret = -EINVAL; |
||
934 | goto out; |
||
935 | } |
||
936 | |||
937 | /* prime objects have no backing filp to GEM pread/pwrite |
||
938 | * pages from. |
||
939 | */ |
||
940 | if (!obj->base.filp) { |
||
941 | ret = -EINVAL; |
||
942 | goto out; |
||
943 | } |
||
944 | |||
945 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
||
946 | |||
947 | ret = -EFAULT; |
||
948 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
||
949 | * it would end up going through the fenced access, and we'll get |
||
950 | * different detiling behavior between reading and writing. |
||
951 | * pread/pwrite currently are reading and writing from the CPU |
||
952 | * perspective, requiring manual detiling by the client. |
||
953 | */ |
||
3260 | Serge | 954 | // if (obj->phys_obj) { |
955 | // ret = i915_gem_phys_pwrite(dev, obj, args, file); |
||
956 | // goto out; |
||
957 | // } |
||
3031 | serge | 958 | |
959 | if (obj->cache_level == I915_CACHE_NONE && |
||
960 | obj->tiling_mode == I915_TILING_NONE && |
||
961 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
||
962 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
||
963 | /* Note that the gtt paths might fail with non-page-backed user |
||
964 | * pointers (e.g. gtt mappings when moving data between |
||
965 | * textures). Fallback to the shmem path in that case. */ |
||
966 | } |
||
967 | |||
968 | if (ret == -EFAULT || ret == -ENOSPC) |
||
3260 | Serge | 969 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
3031 | serge | 970 | |
971 | out: |
||
972 | drm_gem_object_unreference(&obj->base); |
||
973 | unlock: |
||
974 | mutex_unlock(&dev->struct_mutex); |
||
975 | return ret; |
||
976 | } |
||
977 | |||
978 | int |
||
3480 | Serge | 979 | i915_gem_check_wedge(struct i915_gpu_error *error, |
3031 | serge | 980 | bool interruptible) |
981 | { |
||
3480 | Serge | 982 | if (i915_reset_in_progress(error)) { |
3031 | serge | 983 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
984 | * -EIO unconditionally for these. */ |
||
985 | if (!interruptible) |
||
986 | return -EIO; |
||
2332 | Serge | 987 | |
3480 | Serge | 988 | /* Recovery complete, but the reset failed ... */ |
989 | if (i915_terminally_wedged(error)) |
||
3031 | serge | 990 | return -EIO; |
2332 | Serge | 991 | |
3031 | serge | 992 | return -EAGAIN; |
993 | } |
||
2332 | Serge | 994 | |
3031 | serge | 995 | return 0; |
996 | } |
||
2332 | Serge | 997 | |
3031 | serge | 998 | /* |
999 | * Compare seqno against outstanding lazy request. Emit a request if they are |
||
1000 | * equal. |
||
1001 | */ |
||
1002 | static int |
||
1003 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
||
1004 | { |
||
1005 | int ret; |
||
2332 | Serge | 1006 | |
3031 | serge | 1007 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
2332 | Serge | 1008 | |
3031 | serge | 1009 | ret = 0; |
1010 | if (seqno == ring->outstanding_lazy_request) |
||
1011 | ret = i915_add_request(ring, NULL, NULL); |
||
2332 | Serge | 1012 | |
3031 | serge | 1013 | return ret; |
1014 | } |
||
2332 | Serge | 1015 | |
3031 | serge | 1016 | /** |
1017 | * __wait_seqno - wait until execution of seqno has finished |
||
1018 | * @ring: the ring expected to report seqno |
||
1019 | * @seqno: duh! |
||
3480 | Serge | 1020 | * @reset_counter: reset sequence associated with the given seqno |
3031 | serge | 1021 | * @interruptible: do an interruptible wait (normally yes) |
1022 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
||
1023 | * |
||
3480 | Serge | 1024 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1025 | * values have been read by the caller in an smp safe manner. Where read-side |
||
1026 | * locks are involved, it is sufficient to read the reset_counter before |
||
1027 | * unlocking the lock that protects the seqno. For lockless tricks, the |
||
1028 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
||
1029 | * inserted. |
||
1030 | * |
||
3031 | serge | 1031 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1032 | * errno with remaining time filled in timeout argument. |
||
1033 | */ |
||
1034 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
||
3480 | Serge | 1035 | unsigned reset_counter, |
3031 | serge | 1036 | bool interruptible, struct timespec *timeout) |
1037 | { |
||
1038 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
||
1039 | struct timespec before, now, wait_time={1,0}; |
||
1040 | unsigned long timeout_jiffies; |
||
1041 | long end; |
||
1042 | bool wait_forever = true; |
||
1043 | int ret; |
||
2332 | Serge | 1044 | |
3031 | serge | 1045 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1046 | return 0; |
||
2332 | Serge | 1047 | |
3031 | serge | 1048 | trace_i915_gem_request_wait_begin(ring, seqno); |
2332 | Serge | 1049 | |
3031 | serge | 1050 | if (timeout != NULL) { |
1051 | wait_time = *timeout; |
||
1052 | wait_forever = false; |
||
1053 | } |
||
2332 | Serge | 1054 | |
3266 | Serge | 1055 | timeout_jiffies = timespec_to_jiffies(&wait_time); |
2332 | Serge | 1056 | |
3031 | serge | 1057 | if (WARN_ON(!ring->irq_get(ring))) |
1058 | return -ENODEV; |
||
2332 | Serge | 1059 | |
3031 | serge | 1060 | /* Record current time in case interrupted by signal, or wedged * */ |
1061 | getrawmonotonic(&before); |
||
2332 | Serge | 1062 | |
3031 | serge | 1063 | #define EXIT_COND \ |
1064 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
||
3480 | Serge | 1065 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1066 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
||
3031 | serge | 1067 | do { |
3266 | Serge | 1068 | if (interruptible) |
1069 | end = wait_event_interruptible_timeout(ring->irq_queue, |
||
1070 | EXIT_COND, |
||
1071 | timeout_jiffies); |
||
1072 | else |
||
3031 | serge | 1073 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
1074 | timeout_jiffies); |
||
2332 | Serge | 1075 | |
3480 | Serge | 1076 | /* We need to check whether any gpu reset happened in between |
1077 | * the caller grabbing the seqno and now ... */ |
||
1078 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
||
1079 | end = -EAGAIN; |
||
1080 | |||
1081 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
||
1082 | * gone. */ |
||
1083 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
||
3031 | serge | 1084 | if (ret) |
1085 | end = ret; |
||
1086 | } while (end == 0 && wait_forever); |
||
2332 | Serge | 1087 | |
3031 | serge | 1088 | getrawmonotonic(&now); |
2332 | Serge | 1089 | |
3031 | serge | 1090 | ring->irq_put(ring); |
1091 | trace_i915_gem_request_wait_end(ring, seqno); |
||
1092 | #undef EXIT_COND |
||
2332 | Serge | 1093 | |
3031 | serge | 1094 | if (timeout) { |
1095 | // struct timespec sleep_time = timespec_sub(now, before); |
||
1096 | // *timeout = timespec_sub(*timeout, sleep_time); |
||
1097 | } |
||
2332 | Serge | 1098 | |
3031 | serge | 1099 | switch (end) { |
1100 | case -EIO: |
||
1101 | case -EAGAIN: /* Wedged */ |
||
1102 | case -ERESTARTSYS: /* Signal */ |
||
1103 | return (int)end; |
||
1104 | case 0: /* Timeout */ |
||
3266 | Serge | 1105 | if (timeout) |
1106 | set_normalized_timespec(timeout, 0, 0); |
||
3031 | serge | 1107 | return -ETIME; |
1108 | default: /* Completed */ |
||
1109 | WARN_ON(end < 0); /* We're not aware of other errors */ |
||
1110 | return 0; |
||
1111 | } |
||
1112 | } |
||
2332 | Serge | 1113 | |
3031 | serge | 1114 | /** |
1115 | * Waits for a sequence number to be signaled, and cleans up the |
||
1116 | * request and object lists appropriately for that event. |
||
1117 | */ |
||
1118 | int |
||
1119 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
||
1120 | { |
||
1121 | struct drm_device *dev = ring->dev; |
||
1122 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1123 | bool interruptible = dev_priv->mm.interruptible; |
||
1124 | int ret; |
||
2332 | Serge | 1125 | |
3031 | serge | 1126 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1127 | BUG_ON(seqno == 0); |
||
2332 | Serge | 1128 | |
3480 | Serge | 1129 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
3031 | serge | 1130 | if (ret) |
1131 | return ret; |
||
2332 | Serge | 1132 | |
3031 | serge | 1133 | ret = i915_gem_check_olr(ring, seqno); |
1134 | if (ret) |
||
1135 | return ret; |
||
2332 | Serge | 1136 | |
3480 | Serge | 1137 | return __wait_seqno(ring, seqno, |
1138 | atomic_read(&dev_priv->gpu_error.reset_counter), |
||
1139 | interruptible, NULL); |
||
3031 | serge | 1140 | } |
2332 | Serge | 1141 | |
3031 | serge | 1142 | /** |
1143 | * Ensures that all rendering to the object has completed and the object is |
||
1144 | * safe to unbind from the GTT or access from the CPU. |
||
1145 | */ |
||
1146 | static __must_check int |
||
1147 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
||
1148 | bool readonly) |
||
1149 | { |
||
1150 | struct intel_ring_buffer *ring = obj->ring; |
||
1151 | u32 seqno; |
||
1152 | int ret; |
||
2332 | Serge | 1153 | |
3031 | serge | 1154 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1155 | if (seqno == 0) |
||
1156 | return 0; |
||
2332 | Serge | 1157 | |
3031 | serge | 1158 | ret = i915_wait_seqno(ring, seqno); |
1159 | if (ret) |
||
1160 | return ret; |
||
2332 | Serge | 1161 | |
3031 | serge | 1162 | i915_gem_retire_requests_ring(ring); |
2332 | Serge | 1163 | |
3031 | serge | 1164 | /* Manually manage the write flush as we may have not yet |
1165 | * retired the buffer. |
||
1166 | */ |
||
1167 | if (obj->last_write_seqno && |
||
1168 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
||
1169 | obj->last_write_seqno = 0; |
||
1170 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
||
1171 | } |
||
2332 | Serge | 1172 | |
3031 | serge | 1173 | return 0; |
1174 | } |
||
2332 | Serge | 1175 | |
3260 | Serge | 1176 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1177 | * as the object state may change during this call. |
||
1178 | */ |
||
1179 | static __must_check int |
||
1180 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
||
1181 | bool readonly) |
||
1182 | { |
||
1183 | struct drm_device *dev = obj->base.dev; |
||
1184 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1185 | struct intel_ring_buffer *ring = obj->ring; |
||
3480 | Serge | 1186 | unsigned reset_counter; |
3260 | Serge | 1187 | u32 seqno; |
1188 | int ret; |
||
2332 | Serge | 1189 | |
3260 | Serge | 1190 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1191 | BUG_ON(!dev_priv->mm.interruptible); |
||
2332 | Serge | 1192 | |
3260 | Serge | 1193 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1194 | if (seqno == 0) |
||
1195 | return 0; |
||
2332 | Serge | 1196 | |
3480 | Serge | 1197 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3260 | Serge | 1198 | if (ret) |
1199 | return ret; |
||
2332 | Serge | 1200 | |
3260 | Serge | 1201 | ret = i915_gem_check_olr(ring, seqno); |
1202 | if (ret) |
||
1203 | return ret; |
||
2332 | Serge | 1204 | |
3480 | Serge | 1205 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3260 | Serge | 1206 | mutex_unlock(&dev->struct_mutex); |
3480 | Serge | 1207 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3260 | Serge | 1208 | mutex_lock(&dev->struct_mutex); |
2332 | Serge | 1209 | |
3260 | Serge | 1210 | i915_gem_retire_requests_ring(ring); |
2332 | Serge | 1211 | |
3260 | Serge | 1212 | /* Manually manage the write flush as we may have not yet |
1213 | * retired the buffer. |
||
1214 | */ |
||
1215 | if (obj->last_write_seqno && |
||
1216 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
||
1217 | obj->last_write_seqno = 0; |
||
1218 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
||
1219 | } |
||
2332 | Serge | 1220 | |
3260 | Serge | 1221 | return ret; |
1222 | } |
||
2332 | Serge | 1223 | |
3260 | Serge | 1224 | /** |
1225 | * Called when user space prepares to use an object with the CPU, either |
||
1226 | * through the mmap ioctl's mapping or a GTT mapping. |
||
1227 | */ |
||
1228 | int |
||
1229 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
||
1230 | struct drm_file *file) |
||
1231 | { |
||
1232 | struct drm_i915_gem_set_domain *args = data; |
||
1233 | struct drm_i915_gem_object *obj; |
||
1234 | uint32_t read_domains = args->read_domains; |
||
1235 | uint32_t write_domain = args->write_domain; |
||
1236 | int ret; |
||
2332 | Serge | 1237 | |
3480 | Serge | 1238 | |
1239 | if(args->handle == -2) |
||
1240 | { |
||
1241 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
1242 | return 0; |
||
1243 | } |
||
1244 | |||
3260 | Serge | 1245 | /* Only handle setting domains to types used by the CPU. */ |
1246 | if (write_domain & I915_GEM_GPU_DOMAINS) |
||
1247 | return -EINVAL; |
||
2332 | Serge | 1248 | |
3260 | Serge | 1249 | if (read_domains & I915_GEM_GPU_DOMAINS) |
1250 | return -EINVAL; |
||
2332 | Serge | 1251 | |
3260 | Serge | 1252 | /* Having something in the write domain implies it's in the read |
1253 | * domain, and only that read domain. Enforce that in the request. |
||
1254 | */ |
||
1255 | if (write_domain != 0 && read_domains != write_domain) |
||
1256 | return -EINVAL; |
||
2332 | Serge | 1257 | |
3260 | Serge | 1258 | ret = i915_mutex_lock_interruptible(dev); |
1259 | if (ret) |
||
1260 | return ret; |
||
2332 | Serge | 1261 | |
3260 | Serge | 1262 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1263 | if (&obj->base == NULL) { |
||
1264 | ret = -ENOENT; |
||
1265 | goto unlock; |
||
1266 | } |
||
2332 | Serge | 1267 | |
3260 | Serge | 1268 | /* Try to flush the object off the GPU without holding the lock. |
1269 | * We will repeat the flush holding the lock in the normal manner |
||
1270 | * to catch cases where we are gazumped. |
||
1271 | */ |
||
1272 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
||
1273 | if (ret) |
||
1274 | goto unref; |
||
2332 | Serge | 1275 | |
3260 | Serge | 1276 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1277 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
||
2332 | Serge | 1278 | |
3260 | Serge | 1279 | /* Silently promote "you're not bound, there was nothing to do" |
1280 | * to success, since the client was just asking us to |
||
1281 | * make sure everything was done. |
||
1282 | */ |
||
1283 | if (ret == -EINVAL) |
||
1284 | ret = 0; |
||
1285 | } else { |
||
1286 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
||
1287 | } |
||
2332 | Serge | 1288 | |
3260 | Serge | 1289 | unref: |
1290 | drm_gem_object_unreference(&obj->base); |
||
1291 | unlock: |
||
1292 | mutex_unlock(&dev->struct_mutex); |
||
1293 | return ret; |
||
1294 | } |
||
2332 | Serge | 1295 | |
1296 | |||
1297 | |||
1298 | |||
1299 | |||
1300 | |||
3260 | Serge | 1301 | /** |
1302 | * Maps the contents of an object, returning the address it is mapped |
||
1303 | * into. |
||
1304 | * |
||
1305 | * While the mapping holds a reference on the contents of the object, it doesn't |
||
1306 | * imply a ref on the object itself. |
||
1307 | */ |
||
1308 | int |
||
1309 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
||
1310 | struct drm_file *file) |
||
1311 | { |
||
1312 | struct drm_i915_gem_mmap *args = data; |
||
1313 | struct drm_gem_object *obj; |
||
1314 | unsigned long addr = 0; |
||
2332 | Serge | 1315 | |
3480 | Serge | 1316 | if(args->handle == -2) |
1317 | { |
||
1318 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
1319 | return 0; |
||
1320 | } |
||
1321 | |||
3260 | Serge | 1322 | obj = drm_gem_object_lookup(dev, file, args->handle); |
1323 | if (obj == NULL) |
||
1324 | return -ENOENT; |
||
1325 | |||
3298 | Serge | 1326 | //dbgprintf("%s offset %lld size %lld\n", |
1327 | // __FUNCTION__, args->offset, args->size); |
||
3260 | Serge | 1328 | /* prime objects have no backing filp to GEM mmap |
1329 | * pages from. |
||
1330 | */ |
||
1331 | if (!obj->filp) { |
||
1332 | drm_gem_object_unreference_unlocked(obj); |
||
1333 | return -EINVAL; |
||
1334 | } |
||
2332 | Serge | 1335 | |
3263 | Serge | 1336 | addr = vm_mmap(obj->filp, 0, args->size, |
1337 | PROT_READ | PROT_WRITE, MAP_SHARED, |
||
1338 | args->offset); |
||
3260 | Serge | 1339 | drm_gem_object_unreference_unlocked(obj); |
3263 | Serge | 1340 | if (IS_ERR((void *)addr)) |
1341 | return addr; |
||
2332 | Serge | 1342 | |
3260 | Serge | 1343 | args->addr_ptr = (uint64_t) addr; |
2332 | Serge | 1344 | |
3263 | Serge | 1345 | return 0; |
3260 | Serge | 1346 | } |
2332 | Serge | 1347 | |
1348 | |||
1349 | |||
1350 | |||
1351 | |||
1352 | |||
1353 | |||
1354 | |||
3031 | serge | 1355 | |
1356 | |||
1357 | |||
1358 | |||
1359 | |||
1360 | /** |
||
1361 | * i915_gem_release_mmap - remove physical page mappings |
||
1362 | * @obj: obj in question |
||
1363 | * |
||
1364 | * Preserve the reservation of the mmapping with the DRM core code, but |
||
1365 | * relinquish ownership of the pages back to the system. |
||
1366 | * |
||
1367 | * It is vital that we remove the page mapping if we have mapped a tiled |
||
1368 | * object through the GTT and then lose the fence register due to |
||
1369 | * resource pressure. Similarly if the object has been moved out of the |
||
1370 | * aperture, than pages mapped into userspace must be revoked. Removing the |
||
1371 | * mapping will then trigger a page fault on the next user access, allowing |
||
1372 | * fixup by i915_gem_fault(). |
||
1373 | */ |
||
1374 | void |
||
1375 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
||
1376 | { |
||
1377 | if (!obj->fault_mappable) |
||
1378 | return; |
||
1379 | |||
1380 | if (obj->base.dev->dev_mapping) |
||
1381 | // unmap_mapping_range(obj->base.dev->dev_mapping, |
||
1382 | // (loff_t)obj->base.map_list.hash.key< |
||
1383 | // obj->base.size, 1); |
||
1384 | |||
1385 | obj->fault_mappable = false; |
||
1386 | } |
||
1387 | |||
3480 | Serge | 1388 | uint32_t |
2332 | Serge | 1389 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
1390 | { |
||
1391 | uint32_t gtt_size; |
||
1392 | |||
1393 | if (INTEL_INFO(dev)->gen >= 4 || |
||
1394 | tiling_mode == I915_TILING_NONE) |
||
1395 | return size; |
||
1396 | |||
1397 | /* Previous chips need a power-of-two fence region when tiling */ |
||
1398 | if (INTEL_INFO(dev)->gen == 3) |
||
1399 | gtt_size = 1024*1024; |
||
1400 | else |
||
1401 | gtt_size = 512*1024; |
||
1402 | |||
1403 | while (gtt_size < size) |
||
1404 | gtt_size <<= 1; |
||
1405 | |||
1406 | return gtt_size; |
||
1407 | } |
||
1408 | |||
1409 | /** |
||
1410 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
||
1411 | * @obj: object to check |
||
1412 | * |
||
1413 | * Return the required GTT alignment for an object, taking into account |
||
1414 | * potential fence register mapping. |
||
1415 | */ |
||
3480 | Serge | 1416 | uint32_t |
1417 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
||
1418 | int tiling_mode, bool fenced) |
||
2332 | Serge | 1419 | { |
1420 | /* |
||
1421 | * Minimum alignment is 4k (GTT page size), but might be greater |
||
1422 | * if a fence register is needed for the object. |
||
1423 | */ |
||
3480 | Serge | 1424 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
2332 | Serge | 1425 | tiling_mode == I915_TILING_NONE) |
1426 | return 4096; |
||
1427 | |||
1428 | /* |
||
1429 | * Previous chips need to be aligned to the size of the smallest |
||
1430 | * fence register that can contain the object. |
||
1431 | */ |
||
1432 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
||
1433 | } |
||
1434 | |||
1435 | /** |
||
1436 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
||
1437 | * unfenced object |
||
1438 | * @dev: the device |
||
1439 | * @size: size of the object |
||
1440 | * @tiling_mode: tiling mode of the object |
||
1441 | * |
||
1442 | * Return the required GTT alignment for an object, only taking into account |
||
1443 | * unfenced tiled surface requirements. |
||
1444 | */ |
||
1445 | uint32_t |
||
1446 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
||
1447 | uint32_t size, |
||
1448 | int tiling_mode) |
||
1449 | { |
||
1450 | /* |
||
1451 | * Minimum alignment is 4k (GTT page size) for sane hw. |
||
1452 | */ |
||
1453 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
||
1454 | tiling_mode == I915_TILING_NONE) |
||
1455 | return 4096; |
||
1456 | |||
1457 | /* Previous hardware however needs to be aligned to a power-of-two |
||
1458 | * tile height. The simplest method for determining this is to reuse |
||
1459 | * the power-of-tile object size. |
||
1460 | */ |
||
1461 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
||
1462 | } |
||
1463 | |||
3480 | Serge | 1464 | int |
1465 | i915_gem_mmap_gtt(struct drm_file *file, |
||
1466 | struct drm_device *dev, |
||
1467 | uint32_t handle, |
||
1468 | uint64_t *offset) |
||
1469 | { |
||
1470 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1471 | struct drm_i915_gem_object *obj; |
||
1472 | unsigned long pfn; |
||
1473 | char *mem, *ptr; |
||
1474 | int ret; |
||
1475 | |||
1476 | ret = i915_mutex_lock_interruptible(dev); |
||
1477 | if (ret) |
||
1478 | return ret; |
||
1479 | |||
1480 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
||
1481 | if (&obj->base == NULL) { |
||
1482 | ret = -ENOENT; |
||
1483 | goto unlock; |
||
1484 | } |
||
1485 | |||
1486 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
||
1487 | ret = -E2BIG; |
||
1488 | goto out; |
||
1489 | } |
||
1490 | |||
1491 | if (obj->madv != I915_MADV_WILLNEED) { |
||
1492 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
||
1493 | ret = -EINVAL; |
||
1494 | goto out; |
||
1495 | } |
||
1496 | /* Now bind it into the GTT if needed */ |
||
1497 | ret = i915_gem_object_pin(obj, 0, true, false); |
||
1498 | if (ret) |
||
1499 | goto out; |
||
1500 | |||
1501 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
||
1502 | if (ret) |
||
1503 | goto unpin; |
||
1504 | |||
1505 | ret = i915_gem_object_get_fence(obj); |
||
1506 | if (ret) |
||
1507 | goto unpin; |
||
1508 | |||
1509 | obj->fault_mappable = true; |
||
1510 | |||
1511 | pfn = dev_priv->gtt.mappable_base + obj->gtt_offset; |
||
1512 | |||
1513 | /* Finally, remap it using the new GTT offset */ |
||
1514 | |||
1515 | mem = UserAlloc(obj->base.size); |
||
1516 | if(unlikely(mem == NULL)) |
||
1517 | { |
||
1518 | ret = -ENOMEM; |
||
1519 | goto unpin; |
||
1520 | } |
||
1521 | |||
1522 | for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096) |
||
1523 | MapPage(ptr, pfn, PG_SHARED|PG_UW); |
||
1524 | |||
1525 | unpin: |
||
1526 | i915_gem_object_unpin(obj); |
||
1527 | |||
1528 | |||
1529 | *offset = (u64)mem; |
||
1530 | |||
1531 | out: |
||
1532 | drm_gem_object_unreference(&obj->base); |
||
1533 | unlock: |
||
1534 | mutex_unlock(&dev->struct_mutex); |
||
1535 | return ret; |
||
1536 | } |
||
1537 | |||
1538 | /** |
||
1539 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
||
1540 | * @dev: DRM device |
||
1541 | * @data: GTT mapping ioctl data |
||
1542 | * @file: GEM object info |
||
1543 | * |
||
1544 | * Simply returns the fake offset to userspace so it can mmap it. |
||
1545 | * The mmap call will end up in drm_gem_mmap(), which will set things |
||
1546 | * up so we can get faults in the handler above. |
||
1547 | * |
||
1548 | * The fault handler will take care of binding the object into the GTT |
||
1549 | * (since it may have been evicted to make room for something), allocating |
||
1550 | * a fence register, and mapping the appropriate aperture address into |
||
1551 | * userspace. |
||
1552 | */ |
||
1553 | int |
||
1554 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
||
1555 | struct drm_file *file) |
||
1556 | { |
||
1557 | struct drm_i915_gem_mmap_gtt *args = data; |
||
1558 | |||
1559 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
||
1560 | } |
||
1561 | |||
3031 | serge | 1562 | /* Immediately discard the backing storage */ |
1563 | static void |
||
1564 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
||
1565 | { |
||
1566 | // struct inode *inode; |
||
2332 | Serge | 1567 | |
3031 | serge | 1568 | // i915_gem_object_free_mmap_offset(obj); |
2332 | Serge | 1569 | |
3263 | Serge | 1570 | if (obj->base.filp == NULL) |
1571 | return; |
||
2332 | Serge | 1572 | |
3031 | serge | 1573 | /* Our goal here is to return as much of the memory as |
1574 | * is possible back to the system as we are called from OOM. |
||
1575 | * To do this we must instruct the shmfs to drop all of its |
||
1576 | * backing pages, *now*. |
||
1577 | */ |
||
1578 | // inode = obj->base.filp->f_path.dentry->d_inode; |
||
1579 | // shmem_truncate_range(inode, 0, (loff_t)-1); |
||
2332 | Serge | 1580 | |
3031 | serge | 1581 | obj->madv = __I915_MADV_PURGED; |
1582 | } |
||
2332 | Serge | 1583 | |
3031 | serge | 1584 | static inline int |
1585 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
||
1586 | { |
||
1587 | return obj->madv == I915_MADV_DONTNEED; |
||
1588 | } |
||
2332 | Serge | 1589 | |
3031 | serge | 1590 | static void |
1591 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
||
1592 | { |
||
3243 | Serge | 1593 | int page_count = obj->base.size / PAGE_SIZE; |
1594 | struct scatterlist *sg; |
||
3031 | serge | 1595 | int ret, i; |
2332 | Serge | 1596 | |
3031 | serge | 1597 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
2332 | Serge | 1598 | |
3031 | serge | 1599 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1600 | if (ret) { |
||
1601 | /* In the event of a disaster, abandon all caches and |
||
1602 | * hope for the best. |
||
1603 | */ |
||
1604 | WARN_ON(ret != -EIO); |
||
1605 | i915_gem_clflush_object(obj); |
||
1606 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
1607 | } |
||
2332 | Serge | 1608 | |
3031 | serge | 1609 | if (obj->madv == I915_MADV_DONTNEED) |
1610 | obj->dirty = 0; |
||
2332 | Serge | 1611 | |
3243 | Serge | 1612 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1613 | struct page *page = sg_page(sg); |
||
2332 | Serge | 1614 | |
3290 | Serge | 1615 | page_cache_release(page); |
3243 | Serge | 1616 | } |
1617 | //DRM_DEBUG_KMS("%s release %d pages\n", __FUNCTION__, page_count); |
||
3290 | Serge | 1618 | |
3031 | serge | 1619 | obj->dirty = 0; |
3243 | Serge | 1620 | |
1621 | sg_free_table(obj->pages); |
||
1622 | kfree(obj->pages); |
||
3031 | serge | 1623 | } |
2332 | Serge | 1624 | |
3480 | Serge | 1625 | int |
3031 | serge | 1626 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1627 | { |
||
1628 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
||
2332 | Serge | 1629 | |
3243 | Serge | 1630 | if (obj->pages == NULL) |
3031 | serge | 1631 | return 0; |
2332 | Serge | 1632 | |
3031 | serge | 1633 | BUG_ON(obj->gtt_space); |
1634 | |||
1635 | if (obj->pages_pin_count) |
||
1636 | return -EBUSY; |
||
1637 | |||
3243 | Serge | 1638 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1639 | * array, hence protect them from being reaped by removing them from gtt |
||
1640 | * lists early. */ |
||
1641 | list_del(&obj->gtt_list); |
||
1642 | |||
3031 | serge | 1643 | ops->put_pages(obj); |
3243 | Serge | 1644 | obj->pages = NULL; |
3031 | serge | 1645 | |
1646 | if (i915_gem_object_is_purgeable(obj)) |
||
1647 | i915_gem_object_truncate(obj); |
||
1648 | |||
1649 | return 0; |
||
1650 | } |
||
1651 | |||
1652 | |||
1653 | |||
1654 | |||
1655 | |||
1656 | |||
1657 | |||
1658 | |||
2332 | Serge | 1659 | static int |
3031 | serge | 1660 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
2332 | Serge | 1661 | { |
3260 | Serge | 1662 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3243 | Serge | 1663 | int page_count, i; |
3260 | Serge | 1664 | struct address_space *mapping; |
3243 | Serge | 1665 | struct sg_table *st; |
1666 | struct scatterlist *sg; |
||
1667 | struct page *page; |
||
1668 | gfp_t gfp; |
||
2332 | Serge | 1669 | |
3243 | Serge | 1670 | /* Assert that the object is not currently in any GPU domain. As it |
1671 | * wasn't in the GTT, there shouldn't be any way it could have been in |
||
1672 | * a GPU cache |
||
2332 | Serge | 1673 | */ |
3243 | Serge | 1674 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
1675 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
||
1676 | |||
1677 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
||
1678 | if (st == NULL) |
||
1679 | return -ENOMEM; |
||
1680 | |||
2332 | Serge | 1681 | page_count = obj->base.size / PAGE_SIZE; |
3243 | Serge | 1682 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1683 | sg_free_table(st); |
||
1684 | kfree(st); |
||
2332 | Serge | 1685 | return -ENOMEM; |
3243 | Serge | 1686 | } |
2332 | Serge | 1687 | |
3243 | Serge | 1688 | /* Get the list of pages out of our struct file. They'll be pinned |
1689 | * at this point until we release them. |
||
1690 | * |
||
1691 | * Fail silently without starting the shrinker |
||
1692 | */ |
||
1693 | for_each_sg(st->sgl, sg, page_count, i) { |
||
3260 | Serge | 1694 | page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp); |
1695 | if (IS_ERR(page)) { |
||
1696 | dbgprintf("%s invalid page %p\n", __FUNCTION__, page); |
||
2332 | Serge | 1697 | goto err_pages; |
1698 | |||
3260 | Serge | 1699 | } |
3243 | Serge | 1700 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1701 | } |
||
3031 | serge | 1702 | |
3243 | Serge | 1703 | obj->pages = st; |
3031 | serge | 1704 | |
3298 | Serge | 1705 | // DRM_DEBUG_KMS("%s alloc %d pages\n", __FUNCTION__, page_count); |
2332 | Serge | 1706 | |
1707 | return 0; |
||
1708 | |||
1709 | err_pages: |
||
3243 | Serge | 1710 | for_each_sg(st->sgl, sg, i, page_count) |
1711 | page_cache_release(sg_page(sg)); |
||
1712 | sg_free_table(st); |
||
1713 | kfree(st); |
||
1714 | return PTR_ERR(page); |
||
2332 | Serge | 1715 | } |
1716 | |||
3031 | serge | 1717 | /* Ensure that the associated pages are gathered from the backing storage |
1718 | * and pinned into our object. i915_gem_object_get_pages() may be called |
||
1719 | * multiple times before they are released by a single call to |
||
1720 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
||
1721 | * either as a result of memory pressure (reaping pages under the shrinker) |
||
1722 | * or as the object is itself released. |
||
1723 | */ |
||
1724 | int |
||
1725 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
||
2332 | Serge | 1726 | { |
3031 | serge | 1727 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1728 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
||
1729 | int ret; |
||
2332 | Serge | 1730 | |
3243 | Serge | 1731 | if (obj->pages) |
3031 | serge | 1732 | return 0; |
2332 | Serge | 1733 | |
3031 | serge | 1734 | BUG_ON(obj->pages_pin_count); |
2332 | Serge | 1735 | |
3031 | serge | 1736 | ret = ops->get_pages(obj); |
1737 | if (ret) |
||
1738 | return ret; |
||
2344 | Serge | 1739 | |
3031 | serge | 1740 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
3243 | Serge | 1741 | return 0; |
2332 | Serge | 1742 | } |
1743 | |||
1744 | void |
||
1745 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
||
3243 | Serge | 1746 | struct intel_ring_buffer *ring) |
2332 | Serge | 1747 | { |
1748 | struct drm_device *dev = obj->base.dev; |
||
1749 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 1750 | u32 seqno = intel_ring_get_seqno(ring); |
2332 | Serge | 1751 | |
1752 | BUG_ON(ring == NULL); |
||
1753 | obj->ring = ring; |
||
1754 | |||
1755 | /* Add a reference if we're newly entering the active list. */ |
||
1756 | if (!obj->active) { |
||
2344 | Serge | 1757 | drm_gem_object_reference(&obj->base); |
2332 | Serge | 1758 | obj->active = 1; |
1759 | } |
||
1760 | |||
1761 | /* Move from whatever list we were on to the tail of execution. */ |
||
1762 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
||
1763 | list_move_tail(&obj->ring_list, &ring->active_list); |
||
1764 | |||
3031 | serge | 1765 | obj->last_read_seqno = seqno; |
1766 | |||
2332 | Serge | 1767 | if (obj->fenced_gpu_access) { |
3031 | serge | 1768 | obj->last_fenced_seqno = seqno; |
1769 | |||
1770 | /* Bump MRU to take account of the delayed flush */ |
||
1771 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
||
2332 | Serge | 1772 | struct drm_i915_fence_reg *reg; |
1773 | |||
1774 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
||
3031 | serge | 1775 | list_move_tail(®->lru_list, |
1776 | &dev_priv->mm.fence_list); |
||
1777 | } |
||
2332 | Serge | 1778 | } |
1779 | } |
||
1780 | |||
2344 | Serge | 1781 | static void |
3031 | serge | 1782 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
2344 | Serge | 1783 | { |
1784 | struct drm_device *dev = obj->base.dev; |
||
3031 | serge | 1785 | struct drm_i915_private *dev_priv = dev->dev_private; |
2332 | Serge | 1786 | |
3031 | serge | 1787 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
2344 | Serge | 1788 | BUG_ON(!obj->active); |
2332 | Serge | 1789 | |
2352 | Serge | 1790 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
2344 | Serge | 1791 | |
3031 | serge | 1792 | list_del_init(&obj->ring_list); |
2352 | Serge | 1793 | obj->ring = NULL; |
2344 | Serge | 1794 | |
3031 | serge | 1795 | obj->last_read_seqno = 0; |
1796 | obj->last_write_seqno = 0; |
||
1797 | obj->base.write_domain = 0; |
||
1798 | |||
1799 | obj->last_fenced_seqno = 0; |
||
2352 | Serge | 1800 | obj->fenced_gpu_access = false; |
2344 | Serge | 1801 | |
2352 | Serge | 1802 | obj->active = 0; |
1803 | drm_gem_object_unreference(&obj->base); |
||
1804 | |||
1805 | WARN_ON(i915_verify_lists(dev)); |
||
1806 | } |
||
1807 | |||
3243 | Serge | 1808 | static int |
3480 | Serge | 1809 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
2344 | Serge | 1810 | { |
3243 | Serge | 1811 | struct drm_i915_private *dev_priv = dev->dev_private; |
1812 | struct intel_ring_buffer *ring; |
||
1813 | int ret, i, j; |
||
2344 | Serge | 1814 | |
3480 | Serge | 1815 | /* Carefully retire all requests without writing to the rings */ |
3243 | Serge | 1816 | for_each_ring(ring, dev_priv, i) { |
3480 | Serge | 1817 | ret = intel_ring_idle(ring); |
3243 | Serge | 1818 | if (ret) |
1819 | return ret; |
||
3480 | Serge | 1820 | } |
1821 | i915_gem_retire_requests(dev); |
||
3243 | Serge | 1822 | |
3480 | Serge | 1823 | /* Finally reset hw state */ |
3243 | Serge | 1824 | for_each_ring(ring, dev_priv, i) { |
3480 | Serge | 1825 | intel_ring_init_seqno(ring, seqno); |
1826 | |||
3243 | Serge | 1827 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1828 | ring->sync_seqno[j] = 0; |
||
1829 | } |
||
1830 | |||
1831 | return 0; |
||
2344 | Serge | 1832 | } |
1833 | |||
3480 | Serge | 1834 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1835 | { |
||
1836 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1837 | int ret; |
||
1838 | |||
1839 | if (seqno == 0) |
||
1840 | return -EINVAL; |
||
1841 | |||
1842 | /* HWS page needs to be set less than what we |
||
1843 | * will inject to ring |
||
1844 | */ |
||
1845 | ret = i915_gem_init_seqno(dev, seqno - 1); |
||
1846 | if (ret) |
||
1847 | return ret; |
||
1848 | |||
1849 | /* Carefully set the last_seqno value so that wrap |
||
1850 | * detection still works |
||
1851 | */ |
||
1852 | dev_priv->next_seqno = seqno; |
||
1853 | dev_priv->last_seqno = seqno - 1; |
||
1854 | if (dev_priv->last_seqno == 0) |
||
1855 | dev_priv->last_seqno--; |
||
1856 | |||
1857 | return 0; |
||
1858 | } |
||
1859 | |||
3243 | Serge | 1860 | int |
1861 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
||
2344 | Serge | 1862 | { |
3243 | Serge | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
2344 | Serge | 1864 | |
3243 | Serge | 1865 | /* reserve 0 for non-seqno */ |
1866 | if (dev_priv->next_seqno == 0) { |
||
3480 | Serge | 1867 | int ret = i915_gem_init_seqno(dev, 0); |
3243 | Serge | 1868 | if (ret) |
1869 | return ret; |
||
1870 | |||
1871 | dev_priv->next_seqno = 1; |
||
1872 | } |
||
1873 | |||
3480 | Serge | 1874 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
3243 | Serge | 1875 | return 0; |
2332 | Serge | 1876 | } |
1877 | |||
2352 | Serge | 1878 | int |
1879 | i915_add_request(struct intel_ring_buffer *ring, |
||
1880 | struct drm_file *file, |
||
3031 | serge | 1881 | u32 *out_seqno) |
2352 | Serge | 1882 | { |
1883 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
||
3031 | serge | 1884 | struct drm_i915_gem_request *request; |
1885 | u32 request_ring_position; |
||
2352 | Serge | 1886 | int was_empty; |
1887 | int ret; |
||
2332 | Serge | 1888 | |
3031 | serge | 1889 | /* |
1890 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
||
1891 | * after having emitted the batchbuffer command. Hence we need to fix |
||
1892 | * things up similar to emitting the lazy request. The difference here |
||
1893 | * is that the flush _must_ happen before the next request, no matter |
||
1894 | * what. |
||
1895 | */ |
||
1896 | ret = intel_ring_flush_all_caches(ring); |
||
1897 | if (ret) |
||
1898 | return ret; |
||
2332 | Serge | 1899 | |
3031 | serge | 1900 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1901 | if (request == NULL) |
||
1902 | return -ENOMEM; |
||
1903 | |||
1904 | |||
1905 | /* Record the position of the start of the request so that |
||
1906 | * should we detect the updated seqno part-way through the |
||
1907 | * GPU processing the request, we never over-estimate the |
||
1908 | * position of the head. |
||
1909 | */ |
||
1910 | request_ring_position = intel_ring_get_tail(ring); |
||
1911 | |||
3243 | Serge | 1912 | ret = ring->add_request(ring); |
3031 | serge | 1913 | if (ret) { |
1914 | kfree(request); |
||
2352 | Serge | 1915 | return ret; |
3031 | serge | 1916 | } |
2332 | Serge | 1917 | |
3243 | Serge | 1918 | request->seqno = intel_ring_get_seqno(ring); |
2352 | Serge | 1919 | request->ring = ring; |
3031 | serge | 1920 | request->tail = request_ring_position; |
1921 | request->emitted_jiffies = GetTimerTicks(); |
||
2352 | Serge | 1922 | was_empty = list_empty(&ring->request_list); |
1923 | list_add_tail(&request->list, &ring->request_list); |
||
3031 | serge | 1924 | request->file_priv = NULL; |
2332 | Serge | 1925 | |
3263 | Serge | 1926 | if (file) { |
1927 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
2332 | Serge | 1928 | |
3263 | Serge | 1929 | spin_lock(&file_priv->mm.lock); |
1930 | request->file_priv = file_priv; |
||
1931 | list_add_tail(&request->client_list, |
||
1932 | &file_priv->mm.request_list); |
||
1933 | spin_unlock(&file_priv->mm.lock); |
||
1934 | } |
||
1935 | |||
1936 | trace_i915_gem_request_add(ring, request->seqno); |
||
3031 | serge | 1937 | ring->outstanding_lazy_request = 0; |
2332 | Serge | 1938 | |
2360 | Serge | 1939 | if (!dev_priv->mm.suspended) { |
1940 | if (i915_enable_hangcheck) { |
||
2352 | Serge | 1941 | // mod_timer(&dev_priv->hangcheck_timer, |
1942 | // jiffies + |
||
1943 | // msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
||
2360 | Serge | 1944 | } |
3031 | serge | 1945 | if (was_empty) { |
2360 | Serge | 1946 | queue_delayed_work(dev_priv->wq, |
3482 | Serge | 1947 | &dev_priv->mm.retire_work, |
1948 | round_jiffies_up_relative(HZ)); |
||
3031 | serge | 1949 | intel_mark_busy(dev_priv->dev); |
1950 | } |
||
2360 | Serge | 1951 | } |
3031 | serge | 1952 | |
1953 | if (out_seqno) |
||
3243 | Serge | 1954 | *out_seqno = request->seqno; |
2352 | Serge | 1955 | return 0; |
1956 | } |
||
2332 | Serge | 1957 | |
3263 | Serge | 1958 | static inline void |
1959 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
||
1960 | { |
||
1961 | struct drm_i915_file_private *file_priv = request->file_priv; |
||
2332 | Serge | 1962 | |
3263 | Serge | 1963 | if (!file_priv) |
1964 | return; |
||
2332 | Serge | 1965 | |
3263 | Serge | 1966 | spin_lock(&file_priv->mm.lock); |
1967 | if (request->file_priv) { |
||
1968 | list_del(&request->client_list); |
||
1969 | request->file_priv = NULL; |
||
1970 | } |
||
1971 | spin_unlock(&file_priv->mm.lock); |
||
1972 | } |
||
2332 | Serge | 1973 | |
3031 | serge | 1974 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1975 | struct intel_ring_buffer *ring) |
||
1976 | { |
||
1977 | while (!list_empty(&ring->request_list)) { |
||
1978 | struct drm_i915_gem_request *request; |
||
2332 | Serge | 1979 | |
3031 | serge | 1980 | request = list_first_entry(&ring->request_list, |
1981 | struct drm_i915_gem_request, |
||
1982 | list); |
||
2332 | Serge | 1983 | |
3031 | serge | 1984 | list_del(&request->list); |
3263 | Serge | 1985 | i915_gem_request_remove_from_client(request); |
3031 | serge | 1986 | kfree(request); |
1987 | } |
||
2332 | Serge | 1988 | |
3031 | serge | 1989 | while (!list_empty(&ring->active_list)) { |
1990 | struct drm_i915_gem_object *obj; |
||
2332 | Serge | 1991 | |
3031 | serge | 1992 | obj = list_first_entry(&ring->active_list, |
1993 | struct drm_i915_gem_object, |
||
1994 | ring_list); |
||
2332 | Serge | 1995 | |
3031 | serge | 1996 | i915_gem_object_move_to_inactive(obj); |
1997 | } |
||
1998 | } |
||
2332 | Serge | 1999 | |
3031 | serge | 2000 | static void i915_gem_reset_fences(struct drm_device *dev) |
2001 | { |
||
2002 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2003 | int i; |
||
2332 | Serge | 2004 | |
3031 | serge | 2005 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
2006 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
||
2332 | Serge | 2007 | |
3031 | serge | 2008 | i915_gem_write_fence(dev, i, NULL); |
2360 | Serge | 2009 | |
3031 | serge | 2010 | if (reg->obj) |
2011 | i915_gem_object_fence_lost(reg->obj); |
||
2360 | Serge | 2012 | |
3031 | serge | 2013 | reg->pin_count = 0; |
2014 | reg->obj = NULL; |
||
2015 | INIT_LIST_HEAD(®->lru_list); |
||
2016 | } |
||
2360 | Serge | 2017 | |
3031 | serge | 2018 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
2019 | } |
||
2360 | Serge | 2020 | |
3031 | serge | 2021 | void i915_gem_reset(struct drm_device *dev) |
2022 | { |
||
2023 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2024 | struct drm_i915_gem_object *obj; |
||
2025 | struct intel_ring_buffer *ring; |
||
2026 | int i; |
||
2360 | Serge | 2027 | |
3031 | serge | 2028 | for_each_ring(ring, dev_priv, i) |
2029 | i915_gem_reset_ring_lists(dev_priv, ring); |
||
2360 | Serge | 2030 | |
3031 | serge | 2031 | /* Move everything out of the GPU domains to ensure we do any |
2032 | * necessary invalidation upon reuse. |
||
2033 | */ |
||
2034 | list_for_each_entry(obj, |
||
2035 | &dev_priv->mm.inactive_list, |
||
2036 | mm_list) |
||
2037 | { |
||
2038 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
||
2039 | } |
||
2360 | Serge | 2040 | |
3031 | serge | 2041 | /* The fence registers are invalidated so clear them out */ |
2042 | i915_gem_reset_fences(dev); |
||
2043 | } |
||
2360 | Serge | 2044 | |
2352 | Serge | 2045 | /** |
2046 | * This function clears the request list as sequence numbers are passed. |
||
2047 | */ |
||
3031 | serge | 2048 | void |
2352 | Serge | 2049 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
2050 | { |
||
2051 | uint32_t seqno; |
||
2332 | Serge | 2052 | |
2352 | Serge | 2053 | if (list_empty(&ring->request_list)) |
2054 | return; |
||
2332 | Serge | 2055 | |
2352 | Serge | 2056 | WARN_ON(i915_verify_lists(ring->dev)); |
2332 | Serge | 2057 | |
3031 | serge | 2058 | seqno = ring->get_seqno(ring, true); |
2332 | Serge | 2059 | |
2352 | Serge | 2060 | while (!list_empty(&ring->request_list)) { |
2061 | struct drm_i915_gem_request *request; |
||
2332 | Serge | 2062 | |
2352 | Serge | 2063 | request = list_first_entry(&ring->request_list, |
2064 | struct drm_i915_gem_request, |
||
2065 | list); |
||
2332 | Serge | 2066 | |
2352 | Serge | 2067 | if (!i915_seqno_passed(seqno, request->seqno)) |
2068 | break; |
||
2332 | Serge | 2069 | |
2352 | Serge | 2070 | trace_i915_gem_request_retire(ring, request->seqno); |
3031 | serge | 2071 | /* We know the GPU must have read the request to have |
2072 | * sent us the seqno + interrupt, so use the position |
||
2073 | * of tail of the request to update the last known position |
||
2074 | * of the GPU head. |
||
2075 | */ |
||
2076 | ring->last_retired_head = request->tail; |
||
2332 | Serge | 2077 | |
2352 | Serge | 2078 | list_del(&request->list); |
3263 | Serge | 2079 | i915_gem_request_remove_from_client(request); |
2352 | Serge | 2080 | kfree(request); |
2081 | } |
||
2332 | Serge | 2082 | |
2352 | Serge | 2083 | /* Move any buffers on the active list that are no longer referenced |
2084 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
||
2085 | */ |
||
2086 | while (!list_empty(&ring->active_list)) { |
||
2087 | struct drm_i915_gem_object *obj; |
||
2332 | Serge | 2088 | |
2352 | Serge | 2089 | obj = list_first_entry(&ring->active_list, |
2090 | struct drm_i915_gem_object, |
||
2091 | ring_list); |
||
2332 | Serge | 2092 | |
3031 | serge | 2093 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
2352 | Serge | 2094 | break; |
2332 | Serge | 2095 | |
2352 | Serge | 2096 | i915_gem_object_move_to_inactive(obj); |
2097 | } |
||
2332 | Serge | 2098 | |
2352 | Serge | 2099 | if (unlikely(ring->trace_irq_seqno && |
2100 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
||
2101 | ring->irq_put(ring); |
||
2102 | ring->trace_irq_seqno = 0; |
||
2103 | } |
||
2332 | Serge | 2104 | |
2352 | Serge | 2105 | WARN_ON(i915_verify_lists(ring->dev)); |
2106 | } |
||
2332 | Serge | 2107 | |
2352 | Serge | 2108 | void |
2109 | i915_gem_retire_requests(struct drm_device *dev) |
||
2110 | { |
||
2111 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3031 | serge | 2112 | struct intel_ring_buffer *ring; |
2352 | Serge | 2113 | int i; |
2332 | Serge | 2114 | |
3031 | serge | 2115 | for_each_ring(ring, dev_priv, i) |
2116 | i915_gem_retire_requests_ring(ring); |
||
2352 | Serge | 2117 | } |
2118 | |||
2360 | Serge | 2119 | static void |
2120 | i915_gem_retire_work_handler(struct work_struct *work) |
||
2121 | { |
||
2122 | drm_i915_private_t *dev_priv; |
||
2123 | struct drm_device *dev; |
||
3031 | serge | 2124 | struct intel_ring_buffer *ring; |
2360 | Serge | 2125 | bool idle; |
2126 | int i; |
||
2352 | Serge | 2127 | |
2360 | Serge | 2128 | dev_priv = container_of(work, drm_i915_private_t, |
2129 | mm.retire_work.work); |
||
2130 | dev = dev_priv->dev; |
||
2352 | Serge | 2131 | |
2360 | Serge | 2132 | /* Come back later if the device is busy... */ |
2133 | if (!mutex_trylock(&dev->struct_mutex)) { |
||
3482 | Serge | 2134 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2135 | round_jiffies_up_relative(HZ)); |
||
3243 | Serge | 2136 | return; |
2360 | Serge | 2137 | } |
2352 | Serge | 2138 | |
2360 | Serge | 2139 | i915_gem_retire_requests(dev); |
2352 | Serge | 2140 | |
2360 | Serge | 2141 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2142 | * objects indefinitely. |
||
2143 | */ |
||
2144 | idle = true; |
||
3031 | serge | 2145 | for_each_ring(ring, dev_priv, i) { |
2146 | if (ring->gpu_caches_dirty) |
||
2147 | i915_add_request(ring, NULL, NULL); |
||
2352 | Serge | 2148 | |
2360 | Serge | 2149 | idle &= list_empty(&ring->request_list); |
2150 | } |
||
2352 | Serge | 2151 | |
2360 | Serge | 2152 | if (!dev_priv->mm.suspended && !idle) |
3482 | Serge | 2153 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2154 | round_jiffies_up_relative(HZ)); |
||
3031 | serge | 2155 | if (idle) |
2156 | intel_mark_idle(dev); |
||
2360 | Serge | 2157 | |
2158 | mutex_unlock(&dev->struct_mutex); |
||
2159 | } |
||
2160 | |||
2344 | Serge | 2161 | /** |
3031 | serge | 2162 | * Ensures that an object will eventually get non-busy by flushing any required |
2163 | * write domains, emitting any outstanding lazy request and retiring and |
||
2164 | * completed requests. |
||
2352 | Serge | 2165 | */ |
3031 | serge | 2166 | static int |
2167 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
||
2352 | Serge | 2168 | { |
3031 | serge | 2169 | int ret; |
2352 | Serge | 2170 | |
3031 | serge | 2171 | if (obj->active) { |
2172 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
||
2173 | if (ret) |
||
2174 | return ret; |
||
2352 | Serge | 2175 | |
3031 | serge | 2176 | i915_gem_retire_requests_ring(obj->ring); |
2177 | } |
||
2352 | Serge | 2178 | |
3031 | serge | 2179 | return 0; |
2180 | } |
||
2352 | Serge | 2181 | |
3243 | Serge | 2182 | /** |
2183 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
||
2184 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
||
2185 | * |
||
2186 | * Returns 0 if successful, else an error is returned with the remaining time in |
||
2187 | * the timeout parameter. |
||
2188 | * -ETIME: object is still busy after timeout |
||
2189 | * -ERESTARTSYS: signal interrupted the wait |
||
2190 | * -ENONENT: object doesn't exist |
||
2191 | * Also possible, but rare: |
||
2192 | * -EAGAIN: GPU wedged |
||
2193 | * -ENOMEM: damn |
||
2194 | * -ENODEV: Internal IRQ fail |
||
2195 | * -E?: The add request failed |
||
2196 | * |
||
2197 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
||
2198 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
||
2199 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
||
2200 | * without holding struct_mutex the object may become re-busied before this |
||
2201 | * function completes. A similar but shorter * race condition exists in the busy |
||
2202 | * ioctl |
||
2203 | */ |
||
2352 | Serge | 2204 | |
2205 | |||
2206 | |||
2207 | |||
2208 | |||
2209 | |||
2210 | |||
2211 | |||
2212 | |||
3243 | Serge | 2213 | |
2214 | |||
2215 | |||
2352 | Serge | 2216 | /** |
3031 | serge | 2217 | * i915_gem_object_sync - sync an object to a ring. |
2218 | * |
||
2219 | * @obj: object which may be in use on another ring. |
||
2220 | * @to: ring we wish to use the object on. May be NULL. |
||
2221 | * |
||
2222 | * This code is meant to abstract object synchronization with the GPU. |
||
2223 | * Calling with NULL implies synchronizing the object with the CPU |
||
2224 | * rather than a particular GPU ring. |
||
2225 | * |
||
2226 | * Returns 0 if successful, else propagates up the lower layer error. |
||
2344 | Serge | 2227 | */ |
2228 | int |
||
3031 | serge | 2229 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2230 | struct intel_ring_buffer *to) |
||
2344 | Serge | 2231 | { |
3031 | serge | 2232 | struct intel_ring_buffer *from = obj->ring; |
2233 | u32 seqno; |
||
2234 | int ret, idx; |
||
2332 | Serge | 2235 | |
3031 | serge | 2236 | if (from == NULL || to == from) |
2237 | return 0; |
||
2332 | Serge | 2238 | |
3031 | serge | 2239 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2240 | return i915_gem_object_wait_rendering(obj, false); |
||
2332 | Serge | 2241 | |
3031 | serge | 2242 | idx = intel_ring_sync_index(from, to); |
2243 | |||
2244 | seqno = obj->last_read_seqno; |
||
2245 | if (seqno <= from->sync_seqno[idx]) |
||
2246 | return 0; |
||
2247 | |||
2248 | ret = i915_gem_check_olr(obj->ring, seqno); |
||
2249 | if (ret) |
||
2250 | return ret; |
||
2251 | |||
2252 | ret = to->sync_to(to, from, seqno); |
||
2253 | if (!ret) |
||
3243 | Serge | 2254 | /* We use last_read_seqno because sync_to() |
2255 | * might have just caused seqno wrap under |
||
2256 | * the radar. |
||
2257 | */ |
||
2258 | from->sync_seqno[idx] = obj->last_read_seqno; |
||
3031 | serge | 2259 | |
2260 | return ret; |
||
2344 | Serge | 2261 | } |
2332 | Serge | 2262 | |
2344 | Serge | 2263 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2264 | { |
||
2265 | u32 old_write_domain, old_read_domains; |
||
2332 | Serge | 2266 | |
2344 | Serge | 2267 | /* Force a pagefault for domain tracking on next user access */ |
2268 | // i915_gem_release_mmap(obj); |
||
2332 | Serge | 2269 | |
2344 | Serge | 2270 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2271 | return; |
||
2332 | Serge | 2272 | |
3480 | Serge | 2273 | /* Wait for any direct GTT access to complete */ |
2274 | mb(); |
||
2275 | |||
2344 | Serge | 2276 | old_read_domains = obj->base.read_domains; |
2277 | old_write_domain = obj->base.write_domain; |
||
2351 | Serge | 2278 | |
2344 | Serge | 2279 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
2280 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
||
2332 | Serge | 2281 | |
2351 | Serge | 2282 | trace_i915_gem_object_change_domain(obj, |
2283 | old_read_domains, |
||
2284 | old_write_domain); |
||
2344 | Serge | 2285 | } |
2332 | Serge | 2286 | |
2344 | Serge | 2287 | /** |
2288 | * Unbinds an object from the GTT aperture. |
||
2289 | */ |
||
2290 | int |
||
2291 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
||
2292 | { |
||
3031 | serge | 2293 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
3480 | Serge | 2294 | int ret; |
2332 | Serge | 2295 | |
3263 | Serge | 2296 | if(obj == get_fb_obj()) |
2297 | return 0; |
||
2298 | |||
2344 | Serge | 2299 | if (obj->gtt_space == NULL) |
2300 | return 0; |
||
2332 | Serge | 2301 | |
3031 | serge | 2302 | if (obj->pin_count) |
2303 | return -EBUSY; |
||
2332 | Serge | 2304 | |
3243 | Serge | 2305 | BUG_ON(obj->pages == NULL); |
3031 | serge | 2306 | |
2344 | Serge | 2307 | ret = i915_gem_object_finish_gpu(obj); |
3031 | serge | 2308 | if (ret) |
2344 | Serge | 2309 | return ret; |
2310 | /* Continue on if we fail due to EIO, the GPU is hung so we |
||
2311 | * should be safe and we need to cleanup or else we might |
||
2312 | * cause memory corruption through use-after-free. |
||
2313 | */ |
||
2332 | Serge | 2314 | |
2344 | Serge | 2315 | i915_gem_object_finish_gtt(obj); |
2332 | Serge | 2316 | |
2344 | Serge | 2317 | /* release the fence reg _after_ flushing */ |
2318 | ret = i915_gem_object_put_fence(obj); |
||
3031 | serge | 2319 | if (ret) |
2344 | Serge | 2320 | return ret; |
2332 | Serge | 2321 | |
2351 | Serge | 2322 | trace_i915_gem_object_unbind(obj); |
2332 | Serge | 2323 | |
3031 | serge | 2324 | if (obj->has_global_gtt_mapping) |
3243 | Serge | 2325 | i915_gem_gtt_unbind_object(obj); |
3031 | serge | 2326 | if (obj->has_aliasing_ppgtt_mapping) { |
2327 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
||
2328 | obj->has_aliasing_ppgtt_mapping = 0; |
||
2329 | } |
||
2330 | i915_gem_gtt_finish_object(obj); |
||
2332 | Serge | 2331 | |
3031 | serge | 2332 | list_del(&obj->mm_list); |
2333 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
||
2344 | Serge | 2334 | /* Avoid an unnecessary call to unbind on rebind. */ |
2335 | obj->map_and_fenceable = true; |
||
2332 | Serge | 2336 | |
2344 | Serge | 2337 | drm_mm_put_block(obj->gtt_space); |
2338 | obj->gtt_space = NULL; |
||
2339 | obj->gtt_offset = 0; |
||
2332 | Serge | 2340 | |
2344 | Serge | 2341 | return 0; |
2342 | } |
||
2332 | Serge | 2343 | |
3031 | serge | 2344 | int i915_gpu_idle(struct drm_device *dev) |
2344 | Serge | 2345 | { |
2346 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3031 | serge | 2347 | struct intel_ring_buffer *ring; |
2344 | Serge | 2348 | int ret, i; |
2332 | Serge | 2349 | |
2344 | Serge | 2350 | /* Flush everything onto the inactive list. */ |
3031 | serge | 2351 | for_each_ring(ring, dev_priv, i) { |
2352 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
||
2344 | Serge | 2353 | if (ret) |
2354 | return ret; |
||
3031 | serge | 2355 | |
3243 | Serge | 2356 | ret = intel_ring_idle(ring); |
3031 | serge | 2357 | if (ret) |
2358 | return ret; |
||
2344 | Serge | 2359 | } |
2332 | Serge | 2360 | |
2344 | Serge | 2361 | return 0; |
2362 | } |
||
2332 | Serge | 2363 | |
3480 | Serge | 2364 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3031 | serge | 2365 | struct drm_i915_gem_object *obj) |
2366 | { |
||
2367 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3480 | Serge | 2368 | int fence_reg; |
2369 | int fence_pitch_shift; |
||
3031 | serge | 2370 | uint64_t val; |
2332 | Serge | 2371 | |
3480 | Serge | 2372 | if (INTEL_INFO(dev)->gen >= 6) { |
2373 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
||
2374 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
||
2375 | } else { |
||
2376 | fence_reg = FENCE_REG_965_0; |
||
2377 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
||
2378 | } |
||
2332 | Serge | 2379 | |
3031 | serge | 2380 | if (obj) { |
2381 | u32 size = obj->gtt_space->size; |
||
2332 | Serge | 2382 | |
3031 | serge | 2383 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2384 | 0xfffff000) << 32; |
||
2385 | val |= obj->gtt_offset & 0xfffff000; |
||
3480 | Serge | 2386 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
3031 | serge | 2387 | if (obj->tiling_mode == I915_TILING_Y) |
2388 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
||
2389 | val |= I965_FENCE_REG_VALID; |
||
2390 | } else |
||
2391 | val = 0; |
||
2332 | Serge | 2392 | |
3480 | Serge | 2393 | fence_reg += reg * 8; |
2394 | I915_WRITE64(fence_reg, val); |
||
2395 | POSTING_READ(fence_reg); |
||
3031 | serge | 2396 | } |
2332 | Serge | 2397 | |
3031 | serge | 2398 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2399 | struct drm_i915_gem_object *obj) |
||
2400 | { |
||
2401 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
2402 | u32 val; |
||
2332 | Serge | 2403 | |
3031 | serge | 2404 | if (obj) { |
2405 | u32 size = obj->gtt_space->size; |
||
2406 | int pitch_val; |
||
2407 | int tile_width; |
||
2332 | Serge | 2408 | |
3031 | serge | 2409 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2410 | (size & -size) != size || |
||
2411 | (obj->gtt_offset & (size - 1)), |
||
2412 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
||
2413 | obj->gtt_offset, obj->map_and_fenceable, size); |
||
2332 | Serge | 2414 | |
3031 | serge | 2415 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2416 | tile_width = 128; |
||
2417 | else |
||
2418 | tile_width = 512; |
||
2332 | Serge | 2419 | |
3031 | serge | 2420 | /* Note: pitch better be a power of two tile widths */ |
2421 | pitch_val = obj->stride / tile_width; |
||
2422 | pitch_val = ffs(pitch_val) - 1; |
||
2332 | Serge | 2423 | |
3031 | serge | 2424 | val = obj->gtt_offset; |
2425 | if (obj->tiling_mode == I915_TILING_Y) |
||
2426 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
||
2427 | val |= I915_FENCE_SIZE_BITS(size); |
||
2428 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
||
2429 | val |= I830_FENCE_REG_VALID; |
||
2430 | } else |
||
2431 | val = 0; |
||
2332 | Serge | 2432 | |
3031 | serge | 2433 | if (reg < 8) |
2434 | reg = FENCE_REG_830_0 + reg * 4; |
||
2435 | else |
||
2436 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
||
2332 | Serge | 2437 | |
3031 | serge | 2438 | I915_WRITE(reg, val); |
2439 | POSTING_READ(reg); |
||
2440 | } |
||
2332 | Serge | 2441 | |
3031 | serge | 2442 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2443 | struct drm_i915_gem_object *obj) |
||
2444 | { |
||
2445 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
2446 | uint32_t val; |
||
2344 | Serge | 2447 | |
3031 | serge | 2448 | if (obj) { |
2449 | u32 size = obj->gtt_space->size; |
||
2450 | uint32_t pitch_val; |
||
2344 | Serge | 2451 | |
3031 | serge | 2452 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2453 | (size & -size) != size || |
||
2454 | (obj->gtt_offset & (size - 1)), |
||
2455 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
||
2456 | obj->gtt_offset, size); |
||
2344 | Serge | 2457 | |
3031 | serge | 2458 | pitch_val = obj->stride / 128; |
2459 | pitch_val = ffs(pitch_val) - 1; |
||
2344 | Serge | 2460 | |
3031 | serge | 2461 | val = obj->gtt_offset; |
2462 | if (obj->tiling_mode == I915_TILING_Y) |
||
2463 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
||
2464 | val |= I830_FENCE_SIZE_BITS(size); |
||
2465 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
||
2466 | val |= I830_FENCE_REG_VALID; |
||
2467 | } else |
||
2468 | val = 0; |
||
2469 | |||
2470 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
||
2471 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
||
2472 | } |
||
2473 | |||
3480 | Serge | 2474 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2475 | { |
||
2476 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
||
2477 | } |
||
2478 | |||
3031 | serge | 2479 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2480 | struct drm_i915_gem_object *obj) |
||
2332 | Serge | 2481 | { |
3480 | Serge | 2482 | struct drm_i915_private *dev_priv = dev->dev_private; |
2483 | |||
2484 | /* Ensure that all CPU reads are completed before installing a fence |
||
2485 | * and all writes before removing the fence. |
||
2486 | */ |
||
2487 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
||
2488 | mb(); |
||
2489 | |||
3031 | serge | 2490 | switch (INTEL_INFO(dev)->gen) { |
2491 | case 7: |
||
3480 | Serge | 2492 | case 6: |
3031 | serge | 2493 | case 5: |
2494 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
||
2495 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
||
2496 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
||
3480 | Serge | 2497 | default: BUG(); |
3031 | serge | 2498 | } |
3480 | Serge | 2499 | |
2500 | /* And similarly be paranoid that no direct access to this region |
||
2501 | * is reordered to before the fence is installed. |
||
2502 | */ |
||
2503 | if (i915_gem_object_needs_mb(obj)) |
||
2504 | mb(); |
||
2344 | Serge | 2505 | } |
2506 | |||
3031 | serge | 2507 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2508 | struct drm_i915_fence_reg *fence) |
||
2344 | Serge | 2509 | { |
3031 | serge | 2510 | return fence - dev_priv->fence_regs; |
2511 | } |
||
2332 | Serge | 2512 | |
3031 | serge | 2513 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2514 | struct drm_i915_fence_reg *fence, |
||
2515 | bool enable) |
||
2516 | { |
||
2517 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
2518 | int reg = fence_number(dev_priv, fence); |
||
2332 | Serge | 2519 | |
3031 | serge | 2520 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
2521 | |||
2522 | if (enable) { |
||
2523 | obj->fence_reg = reg; |
||
2524 | fence->obj = obj; |
||
2525 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
||
2526 | } else { |
||
2527 | obj->fence_reg = I915_FENCE_REG_NONE; |
||
2528 | fence->obj = NULL; |
||
2529 | list_del_init(&fence->lru_list); |
||
2344 | Serge | 2530 | } |
3031 | serge | 2531 | } |
2344 | Serge | 2532 | |
3031 | serge | 2533 | static int |
3480 | Serge | 2534 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
3031 | serge | 2535 | { |
2536 | if (obj->last_fenced_seqno) { |
||
2537 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
||
2352 | Serge | 2538 | if (ret) |
2539 | return ret; |
||
2344 | Serge | 2540 | |
2541 | obj->last_fenced_seqno = 0; |
||
2542 | } |
||
2543 | |||
3031 | serge | 2544 | obj->fenced_gpu_access = false; |
2332 | Serge | 2545 | return 0; |
2546 | } |
||
2547 | |||
2548 | int |
||
2344 | Serge | 2549 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
2332 | Serge | 2550 | { |
3031 | serge | 2551 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2332 | Serge | 2552 | int ret; |
2553 | |||
3480 | Serge | 2554 | ret = i915_gem_object_wait_fence(obj); |
2332 | Serge | 2555 | if (ret) |
2556 | return ret; |
||
2557 | |||
3031 | serge | 2558 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2559 | return 0; |
||
2332 | Serge | 2560 | |
3031 | serge | 2561 | i915_gem_object_update_fence(obj, |
2562 | &dev_priv->fence_regs[obj->fence_reg], |
||
2563 | false); |
||
2564 | i915_gem_object_fence_lost(obj); |
||
2344 | Serge | 2565 | |
2332 | Serge | 2566 | return 0; |
2567 | } |
||
2568 | |||
3031 | serge | 2569 | static struct drm_i915_fence_reg * |
2570 | i915_find_fence_reg(struct drm_device *dev) |
||
2571 | { |
||
2572 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2573 | struct drm_i915_fence_reg *reg, *avail; |
||
2574 | int i; |
||
2332 | Serge | 2575 | |
3031 | serge | 2576 | /* First try to find a free reg */ |
2577 | avail = NULL; |
||
2578 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
||
2579 | reg = &dev_priv->fence_regs[i]; |
||
2580 | if (!reg->obj) |
||
2581 | return reg; |
||
2332 | Serge | 2582 | |
3031 | serge | 2583 | if (!reg->pin_count) |
2584 | avail = reg; |
||
2585 | } |
||
2332 | Serge | 2586 | |
3031 | serge | 2587 | if (avail == NULL) |
2588 | return NULL; |
||
2332 | Serge | 2589 | |
3031 | serge | 2590 | /* None available, try to steal one or wait for a user to finish */ |
2591 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
||
2592 | if (reg->pin_count) |
||
2593 | continue; |
||
2332 | Serge | 2594 | |
3031 | serge | 2595 | return reg; |
2596 | } |
||
2332 | Serge | 2597 | |
3031 | serge | 2598 | return NULL; |
2599 | } |
||
2332 | Serge | 2600 | |
3031 | serge | 2601 | /** |
2602 | * i915_gem_object_get_fence - set up fencing for an object |
||
2603 | * @obj: object to map through a fence reg |
||
2604 | * |
||
2605 | * When mapping objects through the GTT, userspace wants to be able to write |
||
2606 | * to them without having to worry about swizzling if the object is tiled. |
||
2607 | * This function walks the fence regs looking for a free one for @obj, |
||
2608 | * stealing one if it can't find any. |
||
2609 | * |
||
2610 | * It then sets up the reg based on the object's properties: address, pitch |
||
2611 | * and tiling format. |
||
2612 | * |
||
2613 | * For an untiled surface, this removes any existing fence. |
||
2614 | */ |
||
2615 | int |
||
2616 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
||
2617 | { |
||
2618 | struct drm_device *dev = obj->base.dev; |
||
2619 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2620 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
||
2621 | struct drm_i915_fence_reg *reg; |
||
2622 | int ret; |
||
2332 | Serge | 2623 | |
3031 | serge | 2624 | /* Have we updated the tiling parameters upon the object and so |
2625 | * will need to serialise the write to the associated fence register? |
||
2626 | */ |
||
2627 | if (obj->fence_dirty) { |
||
3480 | Serge | 2628 | ret = i915_gem_object_wait_fence(obj); |
3031 | serge | 2629 | if (ret) |
2630 | return ret; |
||
2631 | } |
||
2332 | Serge | 2632 | |
3031 | serge | 2633 | /* Just update our place in the LRU if our fence is getting reused. */ |
2634 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
||
2635 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
||
2636 | if (!obj->fence_dirty) { |
||
2637 | list_move_tail(®->lru_list, |
||
2638 | &dev_priv->mm.fence_list); |
||
2639 | return 0; |
||
2640 | } |
||
2641 | } else if (enable) { |
||
2642 | reg = i915_find_fence_reg(dev); |
||
2643 | if (reg == NULL) |
||
2644 | return -EDEADLK; |
||
2332 | Serge | 2645 | |
3031 | serge | 2646 | if (reg->obj) { |
2647 | struct drm_i915_gem_object *old = reg->obj; |
||
2332 | Serge | 2648 | |
3480 | Serge | 2649 | ret = i915_gem_object_wait_fence(old); |
3031 | serge | 2650 | if (ret) |
2651 | return ret; |
||
2332 | Serge | 2652 | |
3031 | serge | 2653 | i915_gem_object_fence_lost(old); |
2654 | } |
||
2655 | } else |
||
2656 | return 0; |
||
2332 | Serge | 2657 | |
3031 | serge | 2658 | i915_gem_object_update_fence(obj, reg, enable); |
2659 | obj->fence_dirty = false; |
||
2332 | Serge | 2660 | |
3031 | serge | 2661 | return 0; |
2662 | } |
||
2332 | Serge | 2663 | |
3031 | serge | 2664 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2665 | struct drm_mm_node *gtt_space, |
||
2666 | unsigned long cache_level) |
||
2667 | { |
||
2668 | struct drm_mm_node *other; |
||
2332 | Serge | 2669 | |
3031 | serge | 2670 | /* On non-LLC machines we have to be careful when putting differing |
2671 | * types of snoopable memory together to avoid the prefetcher |
||
3480 | Serge | 2672 | * crossing memory domains and dying. |
3031 | serge | 2673 | */ |
2674 | if (HAS_LLC(dev)) |
||
2675 | return true; |
||
2332 | Serge | 2676 | |
3031 | serge | 2677 | if (gtt_space == NULL) |
2678 | return true; |
||
2332 | Serge | 2679 | |
3031 | serge | 2680 | if (list_empty(>t_space->node_list)) |
2681 | return true; |
||
2332 | Serge | 2682 | |
3031 | serge | 2683 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
2684 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
||
2685 | return false; |
||
2344 | Serge | 2686 | |
3031 | serge | 2687 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
2688 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
||
2689 | return false; |
||
2344 | Serge | 2690 | |
3031 | serge | 2691 | return true; |
2692 | } |
||
2344 | Serge | 2693 | |
3031 | serge | 2694 | static void i915_gem_verify_gtt(struct drm_device *dev) |
2695 | { |
||
2696 | #if WATCH_GTT |
||
2697 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2698 | struct drm_i915_gem_object *obj; |
||
2699 | int err = 0; |
||
2344 | Serge | 2700 | |
3031 | serge | 2701 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { |
2702 | if (obj->gtt_space == NULL) { |
||
2703 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
||
2704 | err++; |
||
2705 | continue; |
||
2706 | } |
||
2344 | Serge | 2707 | |
3031 | serge | 2708 | if (obj->cache_level != obj->gtt_space->color) { |
2709 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
||
2710 | obj->gtt_space->start, |
||
2711 | obj->gtt_space->start + obj->gtt_space->size, |
||
2712 | obj->cache_level, |
||
2713 | obj->gtt_space->color); |
||
2714 | err++; |
||
2715 | continue; |
||
2716 | } |
||
2344 | Serge | 2717 | |
3031 | serge | 2718 | if (!i915_gem_valid_gtt_space(dev, |
2719 | obj->gtt_space, |
||
2720 | obj->cache_level)) { |
||
2721 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
||
2722 | obj->gtt_space->start, |
||
2723 | obj->gtt_space->start + obj->gtt_space->size, |
||
2724 | obj->cache_level); |
||
2725 | err++; |
||
2726 | continue; |
||
2727 | } |
||
2728 | } |
||
2344 | Serge | 2729 | |
3031 | serge | 2730 | WARN_ON(err); |
2731 | #endif |
||
2326 | Serge | 2732 | } |
2733 | |||
2332 | Serge | 2734 | /** |
2735 | * Finds free space in the GTT aperture and binds the object there. |
||
2736 | */ |
||
2737 | static int |
||
2738 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
||
2739 | unsigned alignment, |
||
3031 | serge | 2740 | bool map_and_fenceable, |
2741 | bool nonblocking) |
||
2332 | Serge | 2742 | { |
2743 | struct drm_device *dev = obj->base.dev; |
||
2744 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3243 | Serge | 2745 | struct drm_mm_node *node; |
2332 | Serge | 2746 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
2747 | bool mappable, fenceable; |
||
2748 | int ret; |
||
2326 | Serge | 2749 | |
2332 | Serge | 2750 | fence_size = i915_gem_get_gtt_size(dev, |
2751 | obj->base.size, |
||
2752 | obj->tiling_mode); |
||
2753 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
||
2754 | obj->base.size, |
||
3480 | Serge | 2755 | obj->tiling_mode, true); |
2332 | Serge | 2756 | unfenced_alignment = |
3480 | Serge | 2757 | i915_gem_get_gtt_alignment(dev, |
2332 | Serge | 2758 | obj->base.size, |
3480 | Serge | 2759 | obj->tiling_mode, false); |
2332 | Serge | 2760 | |
2761 | if (alignment == 0) |
||
2762 | alignment = map_and_fenceable ? fence_alignment : |
||
2763 | unfenced_alignment; |
||
2764 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
||
2765 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
||
2766 | return -EINVAL; |
||
2767 | } |
||
2768 | |||
2769 | size = map_and_fenceable ? fence_size : obj->base.size; |
||
2770 | |||
2771 | /* If the object is bigger than the entire aperture, reject it early |
||
2772 | * before evicting everything in a vain attempt to find space. |
||
2773 | */ |
||
2774 | if (obj->base.size > |
||
3480 | Serge | 2775 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
2332 | Serge | 2776 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2777 | return -E2BIG; |
||
2778 | } |
||
2779 | |||
3031 | serge | 2780 | ret = i915_gem_object_get_pages(obj); |
2781 | if (ret) |
||
2782 | return ret; |
||
2783 | |||
3243 | Serge | 2784 | i915_gem_object_pin_pages(obj); |
2785 | |||
2786 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
||
2787 | if (node == NULL) { |
||
2788 | i915_gem_object_unpin_pages(obj); |
||
2789 | return -ENOMEM; |
||
2790 | } |
||
2791 | |||
2332 | Serge | 2792 | search_free: |
2793 | if (map_and_fenceable) |
||
3243 | Serge | 2794 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
3031 | serge | 2795 | size, alignment, obj->cache_level, |
3480 | Serge | 2796 | 0, dev_priv->gtt.mappable_end); |
2332 | Serge | 2797 | else |
3243 | Serge | 2798 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2799 | size, alignment, obj->cache_level); |
||
2800 | if (ret) { |
||
2332 | Serge | 2801 | |
3243 | Serge | 2802 | i915_gem_object_unpin_pages(obj); |
2803 | kfree(node); |
||
2332 | Serge | 2804 | return ret; |
2805 | } |
||
3243 | Serge | 2806 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
2807 | i915_gem_object_unpin_pages(obj); |
||
2808 | drm_mm_put_block(node); |
||
3031 | serge | 2809 | return -EINVAL; |
2810 | } |
||
2332 | Serge | 2811 | |
3031 | serge | 2812 | ret = i915_gem_gtt_prepare_object(obj); |
2332 | Serge | 2813 | if (ret) { |
3243 | Serge | 2814 | i915_gem_object_unpin_pages(obj); |
2815 | drm_mm_put_block(node); |
||
2332 | Serge | 2816 | return ret; |
2817 | } |
||
2818 | |||
3031 | serge | 2819 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
2332 | Serge | 2820 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
2821 | |||
3243 | Serge | 2822 | obj->gtt_space = node; |
2823 | obj->gtt_offset = node->start; |
||
2332 | Serge | 2824 | |
2825 | fenceable = |
||
3243 | Serge | 2826 | node->size == fence_size && |
2827 | (node->start & (fence_alignment - 1)) == 0; |
||
2332 | Serge | 2828 | |
2829 | mappable = |
||
3480 | Serge | 2830 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
2332 | Serge | 2831 | |
2832 | obj->map_and_fenceable = mappable && fenceable; |
||
2833 | |||
3243 | Serge | 2834 | i915_gem_object_unpin_pages(obj); |
2351 | Serge | 2835 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
3031 | serge | 2836 | i915_gem_verify_gtt(dev); |
2332 | Serge | 2837 | return 0; |
2838 | } |
||
2839 | |||
2840 | void |
||
2841 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
||
2842 | { |
||
2843 | /* If we don't have a page list set up, then we're not pinned |
||
2844 | * to GPU, and we can ignore the cache flush because it'll happen |
||
2845 | * again at bind time. |
||
2846 | */ |
||
3243 | Serge | 2847 | if (obj->pages == NULL) |
2332 | Serge | 2848 | return; |
2849 | |||
3480 | Serge | 2850 | /* |
2851 | * Stolen memory is always coherent with the GPU as it is explicitly |
||
2852 | * marked as wc by the system, or the system is cache-coherent. |
||
2853 | */ |
||
2854 | if (obj->stolen) |
||
2855 | return; |
||
2856 | |||
2332 | Serge | 2857 | /* If the GPU is snooping the contents of the CPU cache, |
2858 | * we do not need to manually clear the CPU cache lines. However, |
||
2859 | * the caches are only snooped when the render cache is |
||
2860 | * flushed/invalidated. As we always have to emit invalidations |
||
2861 | * and flushes when moving into and out of the RENDER domain, correct |
||
2862 | * snooping behaviour occurs naturally as the result of our domain |
||
2863 | * tracking. |
||
2864 | */ |
||
2865 | if (obj->cache_level != I915_CACHE_NONE) |
||
2866 | return; |
||
3243 | Serge | 2867 | #if 0 |
2344 | Serge | 2868 | if(obj->mapped != NULL) |
2869 | { |
||
2870 | uint8_t *page_virtual; |
||
2871 | unsigned int i; |
||
2332 | Serge | 2872 | |
2344 | Serge | 2873 | page_virtual = obj->mapped; |
2874 | asm volatile("mfence"); |
||
2875 | for (i = 0; i < obj->base.size; i += x86_clflush_size) |
||
2876 | clflush(page_virtual + i); |
||
2877 | asm volatile("mfence"); |
||
2878 | } |
||
2879 | else |
||
2880 | { |
||
2881 | uint8_t *page_virtual; |
||
2882 | unsigned int i; |
||
2883 | page_virtual = AllocKernelSpace(obj->base.size); |
||
2884 | if(page_virtual != NULL) |
||
2885 | { |
||
3031 | serge | 2886 | dma_addr_t *src, *dst; |
2344 | Serge | 2887 | u32 count; |
2888 | |||
2889 | #define page_tabs 0xFDC00000 /* really dirty hack */ |
||
2890 | |||
3031 | serge | 2891 | src = obj->pages.page; |
2892 | dst = &((dma_addr_t*)page_tabs)[(u32_t)page_virtual >> 12]; |
||
2344 | Serge | 2893 | count = obj->base.size/4096; |
2894 | |||
2895 | while(count--) |
||
2896 | { |
||
2897 | *dst++ = (0xFFFFF000 & *src++) | 0x001 ; |
||
2898 | }; |
||
2899 | |||
2900 | asm volatile("mfence"); |
||
2901 | for (i = 0; i < obj->base.size; i += x86_clflush_size) |
||
2902 | clflush(page_virtual + i); |
||
2903 | asm volatile("mfence"); |
||
2904 | FreeKernelSpace(page_virtual); |
||
2905 | } |
||
2906 | else |
||
2907 | { |
||
2908 | asm volatile ( |
||
2909 | "mfence \n" |
||
2910 | "wbinvd \n" /* this is really ugly */ |
||
2911 | "mfence"); |
||
2912 | } |
||
2913 | } |
||
3243 | Serge | 2914 | #endif |
2915 | |||
2332 | Serge | 2916 | } |
2917 | |||
2344 | Serge | 2918 | /** Flushes the GTT write domain for the object if it's dirty. */ |
2919 | static void |
||
2920 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
||
2921 | { |
||
2922 | uint32_t old_write_domain; |
||
2332 | Serge | 2923 | |
2344 | Serge | 2924 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
2925 | return; |
||
2332 | Serge | 2926 | |
2344 | Serge | 2927 | /* No actual flushing is required for the GTT write domain. Writes |
2928 | * to it immediately go to main memory as far as we know, so there's |
||
2929 | * no chipset flush. It also doesn't land in render cache. |
||
2930 | * |
||
2931 | * However, we do have to enforce the order so that all writes through |
||
2932 | * the GTT land before any writes to the device, such as updates to |
||
2933 | * the GATT itself. |
||
2934 | */ |
||
2935 | wmb(); |
||
2332 | Serge | 2936 | |
2344 | Serge | 2937 | old_write_domain = obj->base.write_domain; |
2938 | obj->base.write_domain = 0; |
||
2332 | Serge | 2939 | |
2351 | Serge | 2940 | trace_i915_gem_object_change_domain(obj, |
2941 | obj->base.read_domains, |
||
2942 | old_write_domain); |
||
2344 | Serge | 2943 | } |
2332 | Serge | 2944 | |
2945 | /** Flushes the CPU write domain for the object if it's dirty. */ |
||
2326 | Serge | 2946 | static void |
2332 | Serge | 2947 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
2948 | { |
||
2949 | uint32_t old_write_domain; |
||
2950 | |||
2951 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
||
2952 | return; |
||
2953 | |||
2954 | i915_gem_clflush_object(obj); |
||
3243 | Serge | 2955 | i915_gem_chipset_flush(obj->base.dev); |
2332 | Serge | 2956 | old_write_domain = obj->base.write_domain; |
2957 | obj->base.write_domain = 0; |
||
2958 | |||
2351 | Serge | 2959 | trace_i915_gem_object_change_domain(obj, |
2960 | obj->base.read_domains, |
||
2961 | old_write_domain); |
||
2332 | Serge | 2962 | } |
2963 | |||
2964 | /** |
||
2965 | * Moves a single object to the GTT read, and possibly write domain. |
||
2966 | * |
||
2967 | * This function returns when the move is complete, including waiting on |
||
2968 | * flushes to occur. |
||
2969 | */ |
||
2970 | int |
||
2971 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
||
2972 | { |
||
3031 | serge | 2973 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
2332 | Serge | 2974 | uint32_t old_write_domain, old_read_domains; |
2975 | int ret; |
||
2976 | |||
2977 | /* Not valid to be called on unbound objects. */ |
||
2978 | if (obj->gtt_space == NULL) |
||
2979 | return -EINVAL; |
||
2980 | |||
2981 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
||
2982 | return 0; |
||
2983 | |||
3031 | serge | 2984 | ret = i915_gem_object_wait_rendering(obj, !write); |
2332 | Serge | 2985 | if (ret) |
2986 | return ret; |
||
2987 | |||
2988 | i915_gem_object_flush_cpu_write_domain(obj); |
||
2989 | |||
3480 | Serge | 2990 | /* Serialise direct access to this object with the barriers for |
2991 | * coherent writes from the GPU, by effectively invalidating the |
||
2992 | * GTT domain upon first access. |
||
2993 | */ |
||
2994 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
||
2995 | mb(); |
||
2996 | |||
2332 | Serge | 2997 | old_write_domain = obj->base.write_domain; |
2998 | old_read_domains = obj->base.read_domains; |
||
2999 | |||
3000 | /* It should now be out of any other write domains, and we can update |
||
3001 | * the domain values for our changes. |
||
3002 | */ |
||
3003 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
||
3004 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
||
3005 | if (write) { |
||
3006 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
||
3007 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
||
3008 | obj->dirty = 1; |
||
3009 | } |
||
3010 | |||
2351 | Serge | 3011 | trace_i915_gem_object_change_domain(obj, |
3012 | old_read_domains, |
||
3013 | old_write_domain); |
||
3014 | |||
3031 | serge | 3015 | /* And bump the LRU for this access */ |
3016 | if (i915_gem_object_is_inactive(obj)) |
||
3017 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
||
3018 | |||
2332 | Serge | 3019 | return 0; |
3020 | } |
||
3021 | |||
2335 | Serge | 3022 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3023 | enum i915_cache_level cache_level) |
||
3024 | { |
||
3031 | serge | 3025 | struct drm_device *dev = obj->base.dev; |
3026 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
2335 | Serge | 3027 | int ret; |
2332 | Serge | 3028 | |
2335 | Serge | 3029 | if (obj->cache_level == cache_level) |
3030 | return 0; |
||
2332 | Serge | 3031 | |
2335 | Serge | 3032 | if (obj->pin_count) { |
3033 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
||
3034 | return -EBUSY; |
||
3035 | } |
||
2332 | Serge | 3036 | |
3031 | serge | 3037 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3038 | ret = i915_gem_object_unbind(obj); |
||
3039 | if (ret) |
||
3040 | return ret; |
||
3041 | } |
||
3042 | |||
2335 | Serge | 3043 | if (obj->gtt_space) { |
3044 | ret = i915_gem_object_finish_gpu(obj); |
||
3045 | if (ret) |
||
3046 | return ret; |
||
2332 | Serge | 3047 | |
2335 | Serge | 3048 | i915_gem_object_finish_gtt(obj); |
2332 | Serge | 3049 | |
2335 | Serge | 3050 | /* Before SandyBridge, you could not use tiling or fence |
3051 | * registers with snooped memory, so relinquish any fences |
||
3052 | * currently pointing to our region in the aperture. |
||
3053 | */ |
||
3031 | serge | 3054 | if (INTEL_INFO(dev)->gen < 6) { |
2335 | Serge | 3055 | ret = i915_gem_object_put_fence(obj); |
3056 | if (ret) |
||
3057 | return ret; |
||
3058 | } |
||
2332 | Serge | 3059 | |
3031 | serge | 3060 | if (obj->has_global_gtt_mapping) |
3061 | i915_gem_gtt_bind_object(obj, cache_level); |
||
3062 | if (obj->has_aliasing_ppgtt_mapping) |
||
3063 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
||
3064 | obj, cache_level); |
||
3065 | |||
3066 | obj->gtt_space->color = cache_level; |
||
2335 | Serge | 3067 | } |
2332 | Serge | 3068 | |
2335 | Serge | 3069 | if (cache_level == I915_CACHE_NONE) { |
3070 | u32 old_read_domains, old_write_domain; |
||
2332 | Serge | 3071 | |
2335 | Serge | 3072 | /* If we're coming from LLC cached, then we haven't |
3073 | * actually been tracking whether the data is in the |
||
3074 | * CPU cache or not, since we only allow one bit set |
||
3075 | * in obj->write_domain and have been skipping the clflushes. |
||
3076 | * Just set it to the CPU cache for now. |
||
3077 | */ |
||
3078 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
||
3079 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
||
2332 | Serge | 3080 | |
2335 | Serge | 3081 | old_read_domains = obj->base.read_domains; |
3082 | old_write_domain = obj->base.write_domain; |
||
2332 | Serge | 3083 | |
2335 | Serge | 3084 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3085 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
2332 | Serge | 3086 | |
2351 | Serge | 3087 | trace_i915_gem_object_change_domain(obj, |
3088 | old_read_domains, |
||
3089 | old_write_domain); |
||
2344 | Serge | 3090 | } |
2332 | Serge | 3091 | |
2335 | Serge | 3092 | obj->cache_level = cache_level; |
3031 | serge | 3093 | i915_gem_verify_gtt(dev); |
2335 | Serge | 3094 | return 0; |
3095 | } |
||
2332 | Serge | 3096 | |
3260 | Serge | 3097 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3098 | struct drm_file *file) |
||
3099 | { |
||
3100 | struct drm_i915_gem_caching *args = data; |
||
3101 | struct drm_i915_gem_object *obj; |
||
3102 | int ret; |
||
3103 | |||
3480 | Serge | 3104 | if(args->handle == -2) |
3105 | { |
||
3106 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
3107 | return 0; |
||
3108 | } |
||
3109 | |||
3260 | Serge | 3110 | ret = i915_mutex_lock_interruptible(dev); |
3111 | if (ret) |
||
3112 | return ret; |
||
3113 | |||
3114 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
||
3115 | if (&obj->base == NULL) { |
||
3116 | ret = -ENOENT; |
||
3117 | goto unlock; |
||
3118 | } |
||
3119 | |||
3120 | args->caching = obj->cache_level != I915_CACHE_NONE; |
||
3121 | |||
3122 | drm_gem_object_unreference(&obj->base); |
||
3123 | unlock: |
||
3124 | mutex_unlock(&dev->struct_mutex); |
||
3125 | return ret; |
||
3126 | } |
||
3127 | |||
3128 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
||
3129 | struct drm_file *file) |
||
3130 | { |
||
3131 | struct drm_i915_gem_caching *args = data; |
||
3132 | struct drm_i915_gem_object *obj; |
||
3133 | enum i915_cache_level level; |
||
3134 | int ret; |
||
3135 | |||
3480 | Serge | 3136 | if(args->handle == -2) |
3137 | { |
||
3138 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
3139 | return 0; |
||
3140 | } |
||
3141 | |||
3260 | Serge | 3142 | switch (args->caching) { |
3143 | case I915_CACHING_NONE: |
||
3144 | level = I915_CACHE_NONE; |
||
3145 | break; |
||
3146 | case I915_CACHING_CACHED: |
||
3147 | level = I915_CACHE_LLC; |
||
3148 | break; |
||
3149 | default: |
||
3150 | return -EINVAL; |
||
3151 | } |
||
3152 | |||
3153 | ret = i915_mutex_lock_interruptible(dev); |
||
3154 | if (ret) |
||
3155 | return ret; |
||
3156 | |||
3157 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
||
3158 | if (&obj->base == NULL) { |
||
3159 | ret = -ENOENT; |
||
3160 | goto unlock; |
||
3161 | } |
||
3162 | |||
3163 | ret = i915_gem_object_set_cache_level(obj, level); |
||
3164 | |||
3165 | drm_gem_object_unreference(&obj->base); |
||
3166 | unlock: |
||
3167 | mutex_unlock(&dev->struct_mutex); |
||
3168 | return ret; |
||
3169 | } |
||
3170 | |||
2335 | Serge | 3171 | /* |
3172 | * Prepare buffer for display plane (scanout, cursors, etc). |
||
3173 | * Can be called from an uninterruptible phase (modesetting) and allows |
||
3174 | * any flushes to be pipelined (for pageflips). |
||
3175 | */ |
||
3176 | int |
||
3177 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
||
3178 | u32 alignment, |
||
3179 | struct intel_ring_buffer *pipelined) |
||
3180 | { |
||
3181 | u32 old_read_domains, old_write_domain; |
||
3182 | int ret; |
||
2332 | Serge | 3183 | |
3031 | serge | 3184 | if (pipelined != obj->ring) { |
3185 | ret = i915_gem_object_sync(obj, pipelined); |
||
2335 | Serge | 3186 | if (ret) |
3187 | return ret; |
||
3188 | } |
||
2332 | Serge | 3189 | |
2335 | Serge | 3190 | /* The display engine is not coherent with the LLC cache on gen6. As |
3191 | * a result, we make sure that the pinning that is about to occur is |
||
3192 | * done with uncached PTEs. This is lowest common denominator for all |
||
3193 | * chipsets. |
||
3194 | * |
||
3195 | * However for gen6+, we could do better by using the GFDT bit instead |
||
3196 | * of uncaching, which would allow us to flush all the LLC-cached data |
||
3197 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
||
3198 | */ |
||
2360 | Serge | 3199 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
3200 | if (ret) |
||
3201 | return ret; |
||
2332 | Serge | 3202 | |
2335 | Serge | 3203 | /* As the user may map the buffer once pinned in the display plane |
3204 | * (e.g. libkms for the bootup splash), we have to ensure that we |
||
3205 | * always use map_and_fenceable for all scanout buffers. |
||
3206 | */ |
||
3031 | serge | 3207 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2335 | Serge | 3208 | if (ret) |
3209 | return ret; |
||
2332 | Serge | 3210 | |
2335 | Serge | 3211 | i915_gem_object_flush_cpu_write_domain(obj); |
2332 | Serge | 3212 | |
2335 | Serge | 3213 | old_write_domain = obj->base.write_domain; |
3214 | old_read_domains = obj->base.read_domains; |
||
2332 | Serge | 3215 | |
2335 | Serge | 3216 | /* It should now be out of any other write domains, and we can update |
3217 | * the domain values for our changes. |
||
3218 | */ |
||
3031 | serge | 3219 | obj->base.write_domain = 0; |
2335 | Serge | 3220 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
2332 | Serge | 3221 | |
2351 | Serge | 3222 | trace_i915_gem_object_change_domain(obj, |
3223 | old_read_domains, |
||
3224 | old_write_domain); |
||
2332 | Serge | 3225 | |
2335 | Serge | 3226 | return 0; |
3227 | } |
||
2332 | Serge | 3228 | |
2344 | Serge | 3229 | int |
3230 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
||
3231 | { |
||
3232 | int ret; |
||
2332 | Serge | 3233 | |
2344 | Serge | 3234 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
3235 | return 0; |
||
2332 | Serge | 3236 | |
3031 | serge | 3237 | ret = i915_gem_object_wait_rendering(obj, false); |
3243 | Serge | 3238 | if (ret) |
3239 | return ret; |
||
2332 | Serge | 3240 | |
2344 | Serge | 3241 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3242 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
||
3031 | serge | 3243 | return 0; |
2344 | Serge | 3244 | } |
2332 | Serge | 3245 | |
2344 | Serge | 3246 | /** |
3247 | * Moves a single object to the CPU read, and possibly write domain. |
||
3248 | * |
||
3249 | * This function returns when the move is complete, including waiting on |
||
3250 | * flushes to occur. |
||
3251 | */ |
||
3031 | serge | 3252 | int |
2344 | Serge | 3253 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
3254 | { |
||
3255 | uint32_t old_write_domain, old_read_domains; |
||
3256 | int ret; |
||
2332 | Serge | 3257 | |
2344 | Serge | 3258 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3259 | return 0; |
||
2332 | Serge | 3260 | |
3031 | serge | 3261 | ret = i915_gem_object_wait_rendering(obj, !write); |
2344 | Serge | 3262 | if (ret) |
3263 | return ret; |
||
2332 | Serge | 3264 | |
2344 | Serge | 3265 | i915_gem_object_flush_gtt_write_domain(obj); |
2332 | Serge | 3266 | |
2344 | Serge | 3267 | old_write_domain = obj->base.write_domain; |
3268 | old_read_domains = obj->base.read_domains; |
||
2332 | Serge | 3269 | |
2344 | Serge | 3270 | /* Flush the CPU cache if it's still invalid. */ |
3271 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
||
3272 | i915_gem_clflush_object(obj); |
||
2332 | Serge | 3273 | |
2344 | Serge | 3274 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
3275 | } |
||
2332 | Serge | 3276 | |
2344 | Serge | 3277 | /* It should now be out of any other write domains, and we can update |
3278 | * the domain values for our changes. |
||
3279 | */ |
||
3280 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
||
2332 | Serge | 3281 | |
2344 | Serge | 3282 | /* If we're writing through the CPU, then the GPU read domains will |
3283 | * need to be invalidated at next use. |
||
3284 | */ |
||
3285 | if (write) { |
||
3286 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
||
3287 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
3288 | } |
||
2332 | Serge | 3289 | |
2351 | Serge | 3290 | trace_i915_gem_object_change_domain(obj, |
3291 | old_read_domains, |
||
3292 | old_write_domain); |
||
2332 | Serge | 3293 | |
2344 | Serge | 3294 | return 0; |
3295 | } |
||
2332 | Serge | 3296 | |
3031 | serge | 3297 | /* Throttle our rendering by waiting until the ring has completed our requests |
3298 | * emitted over 20 msec ago. |
||
2344 | Serge | 3299 | * |
3031 | serge | 3300 | * Note that if we were to use the current jiffies each time around the loop, |
3301 | * we wouldn't escape the function with any frames outstanding if the time to |
||
3302 | * render a frame was over 20ms. |
||
3303 | * |
||
3304 | * This should get us reasonable parallelism between CPU and GPU but also |
||
3305 | * relatively low latency when blocking on a particular request to finish. |
||
2344 | Serge | 3306 | */ |
3031 | serge | 3307 | static int |
3308 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
||
2344 | Serge | 3309 | { |
3031 | serge | 3310 | struct drm_i915_private *dev_priv = dev->dev_private; |
3311 | struct drm_i915_file_private *file_priv = file->driver_priv; |
||
3263 | Serge | 3312 | unsigned long recent_enough = GetTimerTicks() - msecs_to_jiffies(20); |
3031 | serge | 3313 | struct drm_i915_gem_request *request; |
3314 | struct intel_ring_buffer *ring = NULL; |
||
3480 | Serge | 3315 | unsigned reset_counter; |
3031 | serge | 3316 | u32 seqno = 0; |
3317 | int ret; |
||
2332 | Serge | 3318 | |
3480 | Serge | 3319 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3320 | if (ret) |
||
3321 | return ret; |
||
2332 | Serge | 3322 | |
3480 | Serge | 3323 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
3324 | if (ret) |
||
3325 | return ret; |
||
3326 | |||
3031 | serge | 3327 | spin_lock(&file_priv->mm.lock); |
3328 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
||
3329 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
||
3330 | break; |
||
2332 | Serge | 3331 | |
3031 | serge | 3332 | ring = request->ring; |
3333 | seqno = request->seqno; |
||
3334 | } |
||
3480 | Serge | 3335 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3031 | serge | 3336 | spin_unlock(&file_priv->mm.lock); |
2332 | Serge | 3337 | |
3031 | serge | 3338 | if (seqno == 0) |
3339 | return 0; |
||
2332 | Serge | 3340 | |
3480 | Serge | 3341 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3031 | serge | 3342 | if (ret == 0) |
3343 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
||
2332 | Serge | 3344 | |
3031 | serge | 3345 | return ret; |
2352 | Serge | 3346 | } |
2332 | Serge | 3347 | |
3348 | int |
||
3349 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
||
3350 | uint32_t alignment, |
||
3031 | serge | 3351 | bool map_and_fenceable, |
3352 | bool nonblocking) |
||
2332 | Serge | 3353 | { |
3354 | int ret; |
||
3355 | |||
3031 | serge | 3356 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3357 | return -EBUSY; |
||
2332 | Serge | 3358 | |
3359 | if (obj->gtt_space != NULL) { |
||
3360 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
||
3361 | (map_and_fenceable && !obj->map_and_fenceable)) { |
||
3362 | WARN(obj->pin_count, |
||
3363 | "bo is already pinned with incorrect alignment:" |
||
3364 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
||
3365 | " obj->map_and_fenceable=%d\n", |
||
3366 | obj->gtt_offset, alignment, |
||
3367 | map_and_fenceable, |
||
3368 | obj->map_and_fenceable); |
||
3369 | ret = i915_gem_object_unbind(obj); |
||
3370 | if (ret) |
||
3371 | return ret; |
||
3372 | } |
||
3373 | } |
||
3374 | |||
3375 | if (obj->gtt_space == NULL) { |
||
3243 | Serge | 3376 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3377 | |||
2332 | Serge | 3378 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
3031 | serge | 3379 | map_and_fenceable, |
3380 | nonblocking); |
||
2332 | Serge | 3381 | if (ret) |
3382 | return ret; |
||
3243 | Serge | 3383 | |
3384 | if (!dev_priv->mm.aliasing_ppgtt) |
||
3385 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
||
2332 | Serge | 3386 | } |
3387 | |||
3031 | serge | 3388 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3389 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
||
3390 | |||
3391 | obj->pin_count++; |
||
2332 | Serge | 3392 | obj->pin_mappable |= map_and_fenceable; |
3393 | |||
3394 | return 0; |
||
3395 | } |
||
3396 | |||
2344 | Serge | 3397 | void |
3398 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
||
3399 | { |
||
3400 | BUG_ON(obj->pin_count == 0); |
||
3401 | BUG_ON(obj->gtt_space == NULL); |
||
2332 | Serge | 3402 | |
3031 | serge | 3403 | if (--obj->pin_count == 0) |
2344 | Serge | 3404 | obj->pin_mappable = false; |
3405 | } |
||
2332 | Serge | 3406 | |
3031 | serge | 3407 | int |
3408 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
||
3409 | struct drm_file *file) |
||
3410 | { |
||
3411 | struct drm_i915_gem_pin *args = data; |
||
3412 | struct drm_i915_gem_object *obj; |
||
3413 | int ret; |
||
2332 | Serge | 3414 | |
3480 | Serge | 3415 | if(args->handle == -2) |
3416 | { |
||
3417 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
||
3418 | return 0; |
||
3419 | } |
||
3420 | |||
3031 | serge | 3421 | ret = i915_mutex_lock_interruptible(dev); |
3422 | if (ret) |
||
3423 | return ret; |
||
2332 | Serge | 3424 | |
3031 | serge | 3425 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3426 | if (&obj->base == NULL) { |
||
3427 | ret = -ENOENT; |
||
3428 | goto unlock; |
||
3429 | } |
||
2332 | Serge | 3430 | |
3031 | serge | 3431 | if (obj->madv != I915_MADV_WILLNEED) { |
3432 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
||
3433 | ret = -EINVAL; |
||
3434 | goto out; |
||
3435 | } |
||
2332 | Serge | 3436 | |
3031 | serge | 3437 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
3438 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
||
3439 | args->handle); |
||
3440 | ret = -EINVAL; |
||
3441 | goto out; |
||
3442 | } |
||
2332 | Serge | 3443 | |
3243 | Serge | 3444 | if (obj->user_pin_count == 0) { |
3031 | serge | 3445 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
3446 | if (ret) |
||
3447 | goto out; |
||
3448 | } |
||
2332 | Serge | 3449 | |
3243 | Serge | 3450 | obj->user_pin_count++; |
3451 | obj->pin_filp = file; |
||
3452 | |||
3031 | serge | 3453 | /* XXX - flush the CPU caches for pinned objects |
3454 | * as the X server doesn't manage domains yet |
||
3455 | */ |
||
3456 | i915_gem_object_flush_cpu_write_domain(obj); |
||
3457 | args->offset = obj->gtt_offset; |
||
3458 | out: |
||
3459 | drm_gem_object_unreference(&obj->base); |
||
3460 | unlock: |
||
3461 | mutex_unlock(&dev->struct_mutex); |
||
3462 | return ret; |
||
3463 | } |
||
2332 | Serge | 3464 | |
3255 | Serge | 3465 | #if 0 |
3466 | |||
3031 | serge | 3467 | int |
3468 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
||
3469 | struct drm_file *file) |
||
3470 | { |
||
3471 | struct drm_i915_gem_pin *args = data; |
||
3472 | struct drm_i915_gem_object *obj; |
||
3473 | int ret; |
||
2332 | Serge | 3474 | |
3031 | serge | 3475 | ret = i915_mutex_lock_interruptible(dev); |
3476 | if (ret) |
||
3477 | return ret; |
||
2332 | Serge | 3478 | |
3031 | serge | 3479 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3480 | if (&obj->base == NULL) { |
||
3481 | ret = -ENOENT; |
||
3482 | goto unlock; |
||
3483 | } |
||
2332 | Serge | 3484 | |
3031 | serge | 3485 | if (obj->pin_filp != file) { |
3486 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
||
3487 | args->handle); |
||
3488 | ret = -EINVAL; |
||
3489 | goto out; |
||
3490 | } |
||
3491 | obj->user_pin_count--; |
||
3492 | if (obj->user_pin_count == 0) { |
||
3493 | obj->pin_filp = NULL; |
||
3494 | i915_gem_object_unpin(obj); |
||
3495 | } |
||
2332 | Serge | 3496 | |
3031 | serge | 3497 | out: |
3498 | drm_gem_object_unreference(&obj->base); |
||
3499 | unlock: |
||
3500 | mutex_unlock(&dev->struct_mutex); |
||
3501 | return ret; |
||
3502 | } |
||
2332 | Serge | 3503 | |
3260 | Serge | 3504 | #endif |
3505 | |||
3031 | serge | 3506 | int |
3507 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
||
3508 | struct drm_file *file) |
||
3509 | { |
||
3510 | struct drm_i915_gem_busy *args = data; |
||
3511 | struct drm_i915_gem_object *obj; |
||
3512 | int ret; |
||
2332 | Serge | 3513 | |
3031 | serge | 3514 | ret = i915_mutex_lock_interruptible(dev); |
3515 | if (ret) |
||
3516 | return ret; |
||
2332 | Serge | 3517 | |
3480 | Serge | 3518 | if(args->handle == -2) |
3519 | { |
||
3520 | obj = get_fb_obj(); |
||
3521 | drm_gem_object_reference(&obj->base); |
||
3522 | } |
||
3523 | else |
||
3031 | serge | 3524 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3525 | if (&obj->base == NULL) { |
||
3526 | ret = -ENOENT; |
||
3527 | goto unlock; |
||
3528 | } |
||
2332 | Serge | 3529 | |
3031 | serge | 3530 | /* Count all active objects as busy, even if they are currently not used |
3531 | * by the gpu. Users of this interface expect objects to eventually |
||
3532 | * become non-busy without any further actions, therefore emit any |
||
3533 | * necessary flushes here. |
||
3534 | */ |
||
3535 | ret = i915_gem_object_flush_active(obj); |
||
2332 | Serge | 3536 | |
3031 | serge | 3537 | args->busy = obj->active; |
3538 | if (obj->ring) { |
||
3539 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
||
3540 | args->busy |= intel_ring_flag(obj->ring) << 16; |
||
3541 | } |
||
2332 | Serge | 3542 | |
3031 | serge | 3543 | drm_gem_object_unreference(&obj->base); |
3544 | unlock: |
||
3545 | mutex_unlock(&dev->struct_mutex); |
||
3546 | return ret; |
||
3547 | } |
||
2332 | Serge | 3548 | |
3031 | serge | 3549 | int |
3550 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
||
3551 | struct drm_file *file_priv) |
||
3552 | { |
||
3553 | return i915_gem_ring_throttle(dev, file_priv); |
||
3554 | } |
||
2332 | Serge | 3555 | |
3263 | Serge | 3556 | #if 0 |
3557 | |||
3031 | serge | 3558 | int |
3559 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
||
3560 | struct drm_file *file_priv) |
||
3561 | { |
||
3562 | struct drm_i915_gem_madvise *args = data; |
||
3563 | struct drm_i915_gem_object *obj; |
||
3564 | int ret; |
||
2332 | Serge | 3565 | |
3031 | serge | 3566 | switch (args->madv) { |
3567 | case I915_MADV_DONTNEED: |
||
3568 | case I915_MADV_WILLNEED: |
||
3569 | break; |
||
3570 | default: |
||
3571 | return -EINVAL; |
||
3572 | } |
||
2332 | Serge | 3573 | |
3031 | serge | 3574 | ret = i915_mutex_lock_interruptible(dev); |
3575 | if (ret) |
||
3576 | return ret; |
||
2332 | Serge | 3577 | |
3031 | serge | 3578 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3579 | if (&obj->base == NULL) { |
||
3580 | ret = -ENOENT; |
||
3581 | goto unlock; |
||
3582 | } |
||
2332 | Serge | 3583 | |
3031 | serge | 3584 | if (obj->pin_count) { |
3585 | ret = -EINVAL; |
||
3586 | goto out; |
||
3587 | } |
||
2332 | Serge | 3588 | |
3031 | serge | 3589 | if (obj->madv != __I915_MADV_PURGED) |
3590 | obj->madv = args->madv; |
||
2332 | Serge | 3591 | |
3031 | serge | 3592 | /* if the object is no longer attached, discard its backing storage */ |
3593 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
||
3594 | i915_gem_object_truncate(obj); |
||
2332 | Serge | 3595 | |
3031 | serge | 3596 | args->retained = obj->madv != __I915_MADV_PURGED; |
2332 | Serge | 3597 | |
3031 | serge | 3598 | out: |
3599 | drm_gem_object_unreference(&obj->base); |
||
3600 | unlock: |
||
3601 | mutex_unlock(&dev->struct_mutex); |
||
3602 | return ret; |
||
3603 | } |
||
3604 | #endif |
||
2332 | Serge | 3605 | |
3031 | serge | 3606 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3607 | const struct drm_i915_gem_object_ops *ops) |
||
3608 | { |
||
3609 | INIT_LIST_HEAD(&obj->mm_list); |
||
3610 | INIT_LIST_HEAD(&obj->gtt_list); |
||
3611 | INIT_LIST_HEAD(&obj->ring_list); |
||
3612 | INIT_LIST_HEAD(&obj->exec_list); |
||
2332 | Serge | 3613 | |
3031 | serge | 3614 | obj->ops = ops; |
3615 | |||
3616 | obj->fence_reg = I915_FENCE_REG_NONE; |
||
3617 | obj->madv = I915_MADV_WILLNEED; |
||
3618 | /* Avoid an unnecessary call to unbind on the first bind. */ |
||
3619 | obj->map_and_fenceable = true; |
||
3620 | |||
3621 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
||
3622 | } |
||
3623 | |||
3624 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
||
3625 | .get_pages = i915_gem_object_get_pages_gtt, |
||
3626 | .put_pages = i915_gem_object_put_pages_gtt, |
||
3627 | }; |
||
3628 | |||
2332 | Serge | 3629 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3630 | size_t size) |
||
3631 | { |
||
3632 | struct drm_i915_gem_object *obj; |
||
3031 | serge | 3633 | struct address_space *mapping; |
3480 | Serge | 3634 | gfp_t mask; |
2340 | Serge | 3635 | |
2332 | Serge | 3636 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3637 | if (obj == NULL) |
||
3638 | return NULL; |
||
3639 | |||
3640 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
||
3641 | kfree(obj); |
||
3642 | return NULL; |
||
3643 | } |
||
3644 | |||
3645 | |||
3031 | serge | 3646 | i915_gem_object_init(obj, &i915_gem_object_ops); |
2332 | Serge | 3647 | |
3648 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
||
3649 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
||
3650 | |||
3031 | serge | 3651 | if (HAS_LLC(dev)) { |
3652 | /* On some devices, we can have the GPU use the LLC (the CPU |
||
2332 | Serge | 3653 | * cache) for about a 10% performance improvement |
3654 | * compared to uncached. Graphics requests other than |
||
3655 | * display scanout are coherent with the CPU in |
||
3656 | * accessing this cache. This means in this mode we |
||
3657 | * don't need to clflush on the CPU side, and on the |
||
3658 | * GPU side we only need to flush internal caches to |
||
3659 | * get data visible to the CPU. |
||
3660 | * |
||
3661 | * However, we maintain the display planes as UC, and so |
||
3662 | * need to rebind when first used as such. |
||
3663 | */ |
||
3664 | obj->cache_level = I915_CACHE_LLC; |
||
3665 | } else |
||
3666 | obj->cache_level = I915_CACHE_NONE; |
||
3667 | |||
3668 | return obj; |
||
3669 | } |
||
3670 | |||
2344 | Serge | 3671 | int i915_gem_init_object(struct drm_gem_object *obj) |
3672 | { |
||
3673 | BUG(); |
||
2332 | Serge | 3674 | |
2344 | Serge | 3675 | return 0; |
3676 | } |
||
2332 | Serge | 3677 | |
3031 | serge | 3678 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
2344 | Serge | 3679 | { |
3031 | serge | 3680 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
2344 | Serge | 3681 | struct drm_device *dev = obj->base.dev; |
3682 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
2332 | Serge | 3683 | |
3031 | serge | 3684 | trace_i915_gem_object_destroy(obj); |
3685 | |||
3686 | // if (obj->phys_obj) |
||
3687 | // i915_gem_detach_phys_object(dev, obj); |
||
3298 | Serge | 3688 | // printf("%s obj %p\n", __FUNCTION__, obj); |
3031 | serge | 3689 | |
3690 | obj->pin_count = 0; |
||
3691 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
||
3692 | bool was_interruptible; |
||
3693 | |||
3694 | was_interruptible = dev_priv->mm.interruptible; |
||
3695 | dev_priv->mm.interruptible = false; |
||
3696 | |||
3697 | WARN_ON(i915_gem_object_unbind(obj)); |
||
3698 | |||
3699 | dev_priv->mm.interruptible = was_interruptible; |
||
2344 | Serge | 3700 | } |
2332 | Serge | 3701 | |
3031 | serge | 3702 | obj->pages_pin_count = 0; |
3703 | i915_gem_object_put_pages(obj); |
||
3704 | // i915_gem_object_free_mmap_offset(obj); |
||
2332 | Serge | 3705 | |
3243 | Serge | 3706 | BUG_ON(obj->pages); |
2332 | Serge | 3707 | |
3031 | serge | 3708 | // if (obj->base.import_attach) |
3709 | // drm_prime_gem_destroy(&obj->base, NULL); |
||
3710 | |||
3290 | Serge | 3711 | if(obj->base.filp != NULL) |
3712 | { |
||
3298 | Serge | 3713 | // printf("filp %p\n", obj->base.filp); |
3290 | Serge | 3714 | shmem_file_delete(obj->base.filp); |
3715 | } |
||
3716 | |||
2344 | Serge | 3717 | drm_gem_object_release(&obj->base); |
3718 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
||
2332 | Serge | 3719 | |
2344 | Serge | 3720 | kfree(obj->bit_17); |
3721 | kfree(obj); |
||
3722 | } |
||
2332 | Serge | 3723 | |
3031 | serge | 3724 | #if 0 |
3725 | int |
||
3726 | i915_gem_idle(struct drm_device *dev) |
||
2344 | Serge | 3727 | { |
3031 | serge | 3728 | drm_i915_private_t *dev_priv = dev->dev_private; |
3729 | int ret; |
||
2332 | Serge | 3730 | |
3031 | serge | 3731 | mutex_lock(&dev->struct_mutex); |
2332 | Serge | 3732 | |
3031 | serge | 3733 | if (dev_priv->mm.suspended) { |
3734 | mutex_unlock(&dev->struct_mutex); |
||
3735 | return 0; |
||
3736 | } |
||
2332 | Serge | 3737 | |
3031 | serge | 3738 | ret = i915_gpu_idle(dev); |
3739 | if (ret) { |
||
3740 | mutex_unlock(&dev->struct_mutex); |
||
3741 | return ret; |
||
3742 | } |
||
3743 | i915_gem_retire_requests(dev); |
||
3744 | |||
3480 | Serge | 3745 | /* Under UMS, be paranoid and evict. */ |
3746 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
||
3747 | i915_gem_evict_everything(dev); |
||
3748 | |||
3031 | serge | 3749 | i915_gem_reset_fences(dev); |
3750 | |||
3751 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
||
3752 | * We need to replace this with a semaphore, or something. |
||
3753 | * And not confound mm.suspended! |
||
3754 | */ |
||
3755 | dev_priv->mm.suspended = 1; |
||
3480 | Serge | 3756 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
3031 | serge | 3757 | |
3758 | i915_kernel_lost_context(dev); |
||
3759 | i915_gem_cleanup_ringbuffer(dev); |
||
3760 | |||
3761 | mutex_unlock(&dev->struct_mutex); |
||
3762 | |||
3763 | /* Cancel the retire work handler, which should be idle now. */ |
||
3263 | Serge | 3764 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
3031 | serge | 3765 | |
3766 | return 0; |
||
2344 | Serge | 3767 | } |
3031 | serge | 3768 | #endif |
2332 | Serge | 3769 | |
3031 | serge | 3770 | void i915_gem_l3_remap(struct drm_device *dev) |
3771 | { |
||
3772 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3773 | u32 misccpctl; |
||
3774 | int i; |
||
2332 | Serge | 3775 | |
3480 | Serge | 3776 | if (!HAS_L3_GPU_CACHE(dev)) |
3031 | serge | 3777 | return; |
2332 | Serge | 3778 | |
3243 | Serge | 3779 | if (!dev_priv->l3_parity.remap_info) |
3031 | serge | 3780 | return; |
2332 | Serge | 3781 | |
3031 | serge | 3782 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
3783 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
||
3784 | POSTING_READ(GEN7_MISCCPCTL); |
||
2332 | Serge | 3785 | |
3031 | serge | 3786 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
3787 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
||
3243 | Serge | 3788 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
3031 | serge | 3789 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3790 | GEN7_L3LOG_BASE + i, remap); |
||
3243 | Serge | 3791 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
3031 | serge | 3792 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
3243 | Serge | 3793 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
3031 | serge | 3794 | } |
2332 | Serge | 3795 | |
3031 | serge | 3796 | /* Make sure all the writes land before disabling dop clock gating */ |
3797 | POSTING_READ(GEN7_L3LOG_BASE); |
||
2332 | Serge | 3798 | |
3031 | serge | 3799 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
3800 | } |
||
2332 | Serge | 3801 | |
3031 | serge | 3802 | void i915_gem_init_swizzling(struct drm_device *dev) |
3803 | { |
||
3804 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
2332 | Serge | 3805 | |
3031 | serge | 3806 | if (INTEL_INFO(dev)->gen < 5 || |
3807 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
||
3808 | return; |
||
2332 | Serge | 3809 | |
3031 | serge | 3810 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
3811 | DISP_TILE_SURFACE_SWIZZLING); |
||
2332 | Serge | 3812 | |
3031 | serge | 3813 | if (IS_GEN5(dev)) |
3814 | return; |
||
2344 | Serge | 3815 | |
3031 | serge | 3816 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3817 | if (IS_GEN6(dev)) |
||
3818 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
||
3480 | Serge | 3819 | else if (IS_GEN7(dev)) |
3820 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
||
3031 | serge | 3821 | else |
3480 | Serge | 3822 | BUG(); |
3031 | serge | 3823 | } |
3824 | |||
3825 | static bool |
||
3826 | intel_enable_blt(struct drm_device *dev) |
||
3827 | { |
||
3828 | if (!HAS_BLT(dev)) |
||
3829 | return false; |
||
3830 | |||
3831 | /* The blitter was dysfunctional on early prototypes */ |
||
3832 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
||
3833 | DRM_INFO("BLT not supported on this pre-production hardware;" |
||
3834 | " graphics performance will be degraded.\n"); |
||
3835 | return false; |
||
3836 | } |
||
3837 | |||
3838 | return true; |
||
3839 | } |
||
3840 | |||
3480 | Serge | 3841 | static int i915_gem_init_rings(struct drm_device *dev) |
2332 | Serge | 3842 | { |
3480 | Serge | 3843 | struct drm_i915_private *dev_priv = dev->dev_private; |
2332 | Serge | 3844 | int ret; |
2351 | Serge | 3845 | |
2332 | Serge | 3846 | ret = intel_init_render_ring_buffer(dev); |
3847 | if (ret) |
||
3848 | return ret; |
||
3849 | |||
3850 | if (HAS_BSD(dev)) { |
||
3851 | ret = intel_init_bsd_ring_buffer(dev); |
||
3852 | if (ret) |
||
3853 | goto cleanup_render_ring; |
||
3854 | } |
||
3855 | |||
3031 | serge | 3856 | if (intel_enable_blt(dev)) { |
2332 | Serge | 3857 | ret = intel_init_blt_ring_buffer(dev); |
3858 | if (ret) |
||
3859 | goto cleanup_bsd_ring; |
||
3860 | } |
||
3861 | |||
3480 | Serge | 3862 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
3863 | if (ret) |
||
3864 | goto cleanup_blt_ring; |
||
2351 | Serge | 3865 | |
2332 | Serge | 3866 | return 0; |
3867 | |||
3480 | Serge | 3868 | cleanup_blt_ring: |
3869 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
||
2332 | Serge | 3870 | cleanup_bsd_ring: |
3871 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
||
3872 | cleanup_render_ring: |
||
3873 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
||
3480 | Serge | 3874 | |
2332 | Serge | 3875 | return ret; |
3876 | } |
||
3877 | |||
3480 | Serge | 3878 | int |
3879 | i915_gem_init_hw(struct drm_device *dev) |
||
3031 | serge | 3880 | { |
3480 | Serge | 3881 | drm_i915_private_t *dev_priv = dev->dev_private; |
3882 | int ret; |
||
3031 | serge | 3883 | |
3480 | Serge | 3884 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
3885 | return -EIO; |
||
3031 | serge | 3886 | |
3480 | Serge | 3887 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3888 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); |
||
3889 | |||
3890 | i915_gem_l3_remap(dev); |
||
3891 | |||
3892 | i915_gem_init_swizzling(dev); |
||
3893 | |||
3894 | ret = i915_gem_init_rings(dev); |
||
3895 | if (ret) |
||
3896 | return ret; |
||
3897 | |||
3898 | /* |
||
3899 | * XXX: There was some w/a described somewhere suggesting loading |
||
3900 | * contexts before PPGTT. |
||
3901 | */ |
||
3902 | i915_gem_context_init(dev); |
||
3903 | i915_gem_init_ppgtt(dev); |
||
3904 | |||
3905 | return 0; |
||
3031 | serge | 3906 | } |
3907 | |||
3908 | #define LFB_SIZE 0xC00000 |
||
3909 | |||
3910 | int i915_gem_init(struct drm_device *dev) |
||
3911 | { |
||
3912 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3913 | int ret; |
||
3914 | |||
3915 | mutex_lock(&dev->struct_mutex); |
||
3480 | Serge | 3916 | i915_gem_init_global_gtt(dev); |
3031 | serge | 3917 | ret = i915_gem_init_hw(dev); |
3918 | mutex_unlock(&dev->struct_mutex); |
||
3919 | if (ret) { |
||
3920 | i915_gem_cleanup_aliasing_ppgtt(dev); |
||
3921 | return ret; |
||
3922 | } |
||
3923 | |||
3924 | return 0; |
||
3925 | } |
||
3926 | |||
2332 | Serge | 3927 | void |
3928 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
||
3929 | { |
||
3930 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3031 | serge | 3931 | struct intel_ring_buffer *ring; |
2332 | Serge | 3932 | int i; |
3933 | |||
3031 | serge | 3934 | for_each_ring(ring, dev_priv, i) |
3935 | intel_cleanup_ring_buffer(ring); |
||
2332 | Serge | 3936 | } |
3937 | |||
3031 | serge | 3938 | #if 0 |
3939 | |||
2332 | Serge | 3940 | int |
3941 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
||
3942 | struct drm_file *file_priv) |
||
3943 | { |
||
3944 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
3031 | serge | 3945 | int ret; |
2332 | Serge | 3946 | |
3947 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
3948 | return 0; |
||
3949 | |||
3480 | Serge | 3950 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
2332 | Serge | 3951 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
3480 | Serge | 3952 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
2332 | Serge | 3953 | } |
3954 | |||
3955 | mutex_lock(&dev->struct_mutex); |
||
3956 | dev_priv->mm.suspended = 0; |
||
3957 | |||
3031 | serge | 3958 | ret = i915_gem_init_hw(dev); |
2332 | Serge | 3959 | if (ret != 0) { |
3960 | mutex_unlock(&dev->struct_mutex); |
||
3961 | return ret; |
||
3962 | } |
||
3963 | |||
3964 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
||
3965 | mutex_unlock(&dev->struct_mutex); |
||
3966 | |||
3967 | ret = drm_irq_install(dev); |
||
3968 | if (ret) |
||
3969 | goto cleanup_ringbuffer; |
||
3970 | |||
3971 | return 0; |
||
3972 | |||
3973 | cleanup_ringbuffer: |
||
3974 | mutex_lock(&dev->struct_mutex); |
||
3975 | i915_gem_cleanup_ringbuffer(dev); |
||
3976 | dev_priv->mm.suspended = 1; |
||
3977 | mutex_unlock(&dev->struct_mutex); |
||
3978 | |||
3979 | return ret; |
||
3980 | } |
||
3981 | |||
3982 | int |
||
3983 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
||
3984 | struct drm_file *file_priv) |
||
3985 | { |
||
3986 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
3987 | return 0; |
||
3988 | |||
3989 | drm_irq_uninstall(dev); |
||
3990 | return i915_gem_idle(dev); |
||
3991 | } |
||
3992 | |||
3993 | void |
||
3994 | i915_gem_lastclose(struct drm_device *dev) |
||
3995 | { |
||
3996 | int ret; |
||
3997 | |||
3998 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
3999 | return; |
||
4000 | |||
4001 | ret = i915_gem_idle(dev); |
||
4002 | if (ret) |
||
4003 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
||
4004 | } |
||
4005 | #endif |
||
4006 | |||
4007 | static void |
||
2326 | Serge | 4008 | init_ring_lists(struct intel_ring_buffer *ring) |
4009 | { |
||
4010 | INIT_LIST_HEAD(&ring->active_list); |
||
4011 | INIT_LIST_HEAD(&ring->request_list); |
||
4012 | } |
||
4013 | |||
4014 | void |
||
4015 | i915_gem_load(struct drm_device *dev) |
||
4016 | { |
||
3480 | Serge | 4017 | drm_i915_private_t *dev_priv = dev->dev_private; |
2326 | Serge | 4018 | int i; |
4019 | |||
4020 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
||
4021 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
||
3031 | serge | 4022 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4023 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
||
2326 | Serge | 4024 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4025 | for (i = 0; i < I915_NUM_RINGS; i++) |
||
4026 | init_ring_lists(&dev_priv->ring[i]); |
||
2342 | Serge | 4027 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
2326 | Serge | 4028 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
2360 | Serge | 4029 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4030 | i915_gem_retire_work_handler); |
||
3480 | Serge | 4031 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
2326 | Serge | 4032 | |
4033 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
||
4034 | if (IS_GEN3(dev)) { |
||
3031 | serge | 4035 | I915_WRITE(MI_ARB_STATE, |
4036 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
||
2326 | Serge | 4037 | } |
4038 | |||
4039 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
||
4040 | |||
4041 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
||
4042 | dev_priv->num_fence_regs = 16; |
||
4043 | else |
||
4044 | dev_priv->num_fence_regs = 8; |
||
4045 | |||
4046 | /* Initialize fence registers to zero */ |
||
3031 | serge | 4047 | i915_gem_reset_fences(dev); |
2326 | Serge | 4048 | |
4049 | i915_gem_detect_bit_6_swizzle(dev); |
||
4050 | |||
4051 | dev_priv->mm.interruptible = true; |
||
4052 | |||
4053 | // dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
||
4054 | // dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
||
4055 | // register_shrinker(&dev_priv->mm.inactive_shrinker); |
||
4056 | }>>>>>>><>>>>=>>><>><>>><>><>><>><>><>=>>>>=><=>> |
||
4057 | |||
4058 |