WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/i915_drv.h

Rev	Author	Line No.	Line
2325	Serge	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
		2	*/
		3	/*
		4	*
		5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
		6	* All Rights Reserved.
		7	*
		8	* Permission is hereby granted, free of charge, to any person obtaining a
		9	* copy of this software and associated documentation files (the
		10	* "Software"), to deal in the Software without restriction, including
		11	* without limitation the rights to use, copy, modify, merge, publish,
		12	* distribute, sub license, and/or sell copies of the Software, and to
		13	* permit persons to whom the Software is furnished to do so, subject to
		14	* the following conditions:
		15	*
		16	* The above copyright notice and this permission notice (including the
		17	* next paragraph) shall be included in all copies or substantial portions
		18	* of the Software.
		19	*
		20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
		23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
		24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		27	*
		28	*/
		29
		30	#ifndef _I915_DRV_H_
		31	#define _I915_DRV_H_
		32
3480	Serge	33	#include
6084	serge	34	#include
3480	Serge	35
6937	serge	36	#include
2325	Serge	37	#include "i915_reg.h"
2327	Serge	38	#include "intel_bios.h"
2326	Serge	39	#include "intel_ringbuffer.h"
5354	serge	40	#include "intel_lrc.h"
5060	serge	41	#include "i915_gem_gtt.h"
5354	serge	42	#include "i915_gem_render_state.h"
6084	serge	43	#include
2330	Serge	44	#include
3031	serge	45	#include
2332	Serge	46	#include
5354	serge	47	#include /* for struct drm_dma_handle */
		48	#include
6937	serge	49	#include
5060	serge	50	#include
6084	serge	51	#include
		52	#include "intel_guc.h"
2325	Serge	53
		54	#include
		55
		56	/* General customization:
		57	*/
		58
		59	#define DRIVER_NAME "i915"
		60	#define DRIVER_DESC "Intel Graphics"
6937	serge	61	#define DRIVER_DATE "20151218"
2325	Serge	62
5354	serge	63	#undef WARN_ON
6084	serge	64	/* Many gcc seem to no see through this and fall over :( */
		65	#if 0
		66	#define WARN_ON(x) ({ \
		67	bool __i915_warn_cond = (x); \
		68	if (__builtin_constant_p(__i915_warn_cond)) \
		69	BUILD_BUG_ON(__i915_warn_cond); \
		70	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
		71	#else
		72	#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
		73	#endif
5354	serge	74
6084	serge	75	#undef WARN_ON_ONCE
		76	#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
		77
		78	#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
		79	(long) (x), __func__);
		80
		81	/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
		82	* WARN_ON()) for hw state sanity checks to check for unexpected conditions
		83	* which may not necessarily be a user visible problem. This will either
		84	* WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
		85	* enable distros and users to tailor their preferred amount of i915 abrt
		86	* spam.
		87	*/
		88	#define I915_STATE_WARN(condition, format...) ({ \
		89	int __ret_warn_on = !!(condition); \
		90	if (unlikely(__ret_warn_on)) { \
		91	if (i915.verbose_state_checks) \
		92	WARN(1, format); \
		93	else \
		94	DRM_ERROR(format); \
		95	} \
		96	unlikely(__ret_warn_on); \
		97	})
		98
		99	#define I915_STATE_WARN_ON(condition) ({ \
		100	int __ret_warn_on = !!(condition); \
		101	if (unlikely(__ret_warn_on)) { \
		102	if (i915.verbose_state_checks) \
		103	WARN(1, "WARN_ON(" #condition ")\n"); \
		104	else \
		105	DRM_ERROR("WARN_ON(" #condition ")\n"); \
		106	} \
		107	unlikely(__ret_warn_on); \
		108	})
		109
		110	static inline const char *yesno(bool v)
		111	{
		112	return v ? "yes" : "no";
		113	}
		114
2325	Serge	115	enum pipe {
4560	Serge	116	INVALID_PIPE = -1,
2325	Serge	117	PIPE_A = 0,
		118	PIPE_B,
		119	PIPE_C,
5060	serge	120	_PIPE_EDP,
		121	I915_MAX_PIPES = _PIPE_EDP
2325	Serge	122	};
		123	#define pipe_name(p) ((p) + 'A')
		124
3243	Serge	125	enum transcoder {
		126	TRANSCODER_A = 0,
		127	TRANSCODER_B,
		128	TRANSCODER_C,
5060	serge	129	TRANSCODER_EDP,
		130	I915_MAX_TRANSCODERS
3243	Serge	131	};
		132	#define transcoder_name(t) ((t) + 'A')
		133
5354	serge	134	/*
6084	serge	135	* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
		136	* number of planes per CRTC. Not all platforms really have this many planes,
		137	* which means some arrays of size I915_MAX_PLANES may have unused entries
		138	* between the topmost sprite plane and the cursor plane.
5354	serge	139	*/
2325	Serge	140	enum plane {
		141	PLANE_A = 0,
		142	PLANE_B,
		143	PLANE_C,
6084	serge	144	PLANE_CURSOR,
		145	I915_MAX_PLANES,
2325	Serge	146	};
		147	#define plane_name(p) ((p) + 'A')
		148
5060	serge	149	#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
4104	Serge	150
3031	serge	151	enum port {
		152	PORT_A = 0,
		153	PORT_B,
		154	PORT_C,
		155	PORT_D,
		156	PORT_E,
		157	I915_MAX_PORTS
		158	};
		159	#define port_name(p) ((p) + 'A')
		160
5060	serge	161	#define I915_NUM_PHYS_VLV 2
4560	Serge	162
		163	enum dpio_channel {
		164	DPIO_CH0,
		165	DPIO_CH1
		166	};
		167
		168	enum dpio_phy {
		169	DPIO_PHY0,
		170	DPIO_PHY1
		171	};
		172
4104	Serge	173	enum intel_display_power_domain {
		174	POWER_DOMAIN_PIPE_A,
		175	POWER_DOMAIN_PIPE_B,
		176	POWER_DOMAIN_PIPE_C,
		177	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
		178	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
		179	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
		180	POWER_DOMAIN_TRANSCODER_A,
		181	POWER_DOMAIN_TRANSCODER_B,
		182	POWER_DOMAIN_TRANSCODER_C,
4560	Serge	183	POWER_DOMAIN_TRANSCODER_EDP,
6937	serge	184	POWER_DOMAIN_PORT_DDI_A_LANES,
		185	POWER_DOMAIN_PORT_DDI_B_LANES,
		186	POWER_DOMAIN_PORT_DDI_C_LANES,
		187	POWER_DOMAIN_PORT_DDI_D_LANES,
		188	POWER_DOMAIN_PORT_DDI_E_LANES,
5060	serge	189	POWER_DOMAIN_PORT_DSI,
		190	POWER_DOMAIN_PORT_CRT,
		191	POWER_DOMAIN_PORT_OTHER,
4560	Serge	192	POWER_DOMAIN_VGA,
		193	POWER_DOMAIN_AUDIO,
5060	serge	194	POWER_DOMAIN_PLLS,
6084	serge	195	POWER_DOMAIN_AUX_A,
		196	POWER_DOMAIN_AUX_B,
		197	POWER_DOMAIN_AUX_C,
		198	POWER_DOMAIN_AUX_D,
		199	POWER_DOMAIN_GMBUS,
6937	serge	200	POWER_DOMAIN_MODESET,
4560	Serge	201	POWER_DOMAIN_INIT,
		202
		203	POWER_DOMAIN_NUM,
4104	Serge	204	};
		205
		206	#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
		207	#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		208	((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
4560	Serge	209	#define POWER_DOMAIN_TRANSCODER(tran) \
		210	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
		211	(tran) + POWER_DOMAIN_TRANSCODER_A)
4104	Serge	212
3746	Serge	213	enum hpd_pin {
		214	HPD_NONE = 0,
		215	HPD_TV = HPD_NONE, /* TV is known to be unreliable */
		216	HPD_CRT,
		217	HPD_SDVO_B,
		218	HPD_SDVO_C,
6084	serge	219	HPD_PORT_A,
3746	Serge	220	HPD_PORT_B,
		221	HPD_PORT_C,
		222	HPD_PORT_D,
6084	serge	223	HPD_PORT_E,
3746	Serge	224	HPD_NUM_PINS
		225	};
		226
6084	serge	227	#define for_each_hpd_pin(__pin) \
		228	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
		229
		230	struct i915_hotplug {
		231	struct work_struct hotplug_work;
		232
		233	struct {
		234	unsigned long last_jiffies;
		235	int count;
		236	enum {
		237	HPD_ENABLED = 0,
		238	HPD_DISABLED = 1,
		239	HPD_MARK_DISABLED = 2
		240	} state;
		241	} stats[HPD_NUM_PINS];
		242	u32 event_bits;
		243	struct delayed_work reenable_work;
		244
		245	struct intel_digital_port *irq_port[I915_MAX_PORTS];
		246	u32 long_port_mask;
		247	u32 short_port_mask;
		248	struct work_struct dig_port_work;
		249
		250	/*
		251	* if we get a HPD irq from DP and a HPD irq from non-DP
		252	* the non-DP HPD could block the workqueue on a mode config
		253	* mutex getting, that userspace may have taken. However
		254	* userspace is waiting on the DP workqueue to run which is
		255	* blocked behind the non-DP one.
		256	*/
		257	struct workqueue_struct *dp_wq;
		258	};
		259
3480	Serge	260	#define I915_GEM_GPU_DOMAINS \
		261	(I915_GEM_DOMAIN_RENDER \| \
		262	I915_GEM_DOMAIN_SAMPLER \| \
		263	I915_GEM_DOMAIN_COMMAND \| \
		264	I915_GEM_DOMAIN_INSTRUCTION \| \
		265	I915_GEM_DOMAIN_VERTEX)
2325	Serge	266
5354	serge	267	#define for_each_pipe(__dev_priv, __p) \
		268	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
6084	serge	269	#define for_each_plane(__dev_priv, __pipe, __p) \
		270	for ((__p) = 0; \
		271	(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
		272	(__p)++)
		273	#define for_each_sprite(__dev_priv, __p, __s) \
		274	for ((__s) = 0; \
		275	(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
		276	(__s)++)
2325	Serge	277
5060	serge	278	#define for_each_crtc(dev, crtc) \
		279	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		280
6084	serge	281	#define for_each_intel_plane(dev, intel_plane) \
		282	list_for_each_entry(intel_plane, \
		283	&dev->mode_config.plane_list, \
		284	base.head)
		285
		286	#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
		287	list_for_each_entry(intel_plane, \
		288	&(dev)->mode_config.plane_list, \
		289	base.head) \
6937	serge	290	for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
6084	serge	291
5060	serge	292	#define for_each_intel_crtc(dev, intel_crtc) \
		293	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
		294
5354	serge	295	#define for_each_intel_encoder(dev, intel_encoder) \
		296	list_for_each_entry(intel_encoder, \
		297	&(dev)->mode_config.encoder_list, \
		298	base.head)
		299
6084	serge	300	#define for_each_intel_connector(dev, intel_connector) \
		301	list_for_each_entry(intel_connector, \
		302	&dev->mode_config.connector_list, \
		303	base.head)
		304
3031	serge	305	#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
		306	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
6937	serge	307	for_each_if ((intel_encoder)->base.crtc == (__crtc))
3031	serge	308
5060	serge	309	#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
		310	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
6937	serge	311	for_each_if ((intel_connector)->base.encoder == (__encoder))
5060	serge	312
		313	#define for_each_power_domain(domain, mask) \
		314	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6937	serge	315	for_each_if ((1 << (domain)) & (mask))
5060	serge	316
4104	Serge	317	struct drm_i915_private;
5128	serge	318	struct i915_mm_struct;
5060	serge	319	struct i915_mmu_object;
4104	Serge	320
6084	serge	321	struct drm_i915_file_private {
		322	struct drm_i915_private *dev_priv;
		323	struct drm_file *file;
		324
		325	struct {
		326	spinlock_t lock;
		327	struct list_head request_list;
		328	/* 20ms is a fairly arbitrary limit (greater than the average frame time)
		329	* chosen to prevent the CPU getting more than a frame ahead of the GPU
		330	* (when using lax throttling for the frontbuffer). We also use it to
		331	* offer free GPU waitboosts for severely congested workloads.
		332	*/
		333	#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
		334	} mm;
		335	struct idr context_idr;
		336
		337	struct intel_rps_client {
		338	struct list_head link;
		339	unsigned boosts;
		340	} rps;
		341
		342	struct intel_engine_cs *bsd_ring;
		343	};
		344
4104	Serge	345	enum intel_dpll_id {
		346	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
		347	/* real shared dpll ids must be >= 0 */
5060	serge	348	DPLL_ID_PCH_PLL_A = 0,
		349	DPLL_ID_PCH_PLL_B = 1,
5354	serge	350	/* hsw/bdw */
5060	serge	351	DPLL_ID_WRPLL1 = 0,
		352	DPLL_ID_WRPLL2 = 1,
6084	serge	353	DPLL_ID_SPLL = 2,
		354
5354	serge	355	/* skl */
		356	DPLL_ID_SKL_DPLL1 = 0,
		357	DPLL_ID_SKL_DPLL2 = 1,
		358	DPLL_ID_SKL_DPLL3 = 2,
4104	Serge	359	};
5354	serge	360	#define I915_NUM_PLLS 3
4104	Serge	361
		362	struct intel_dpll_hw_state {
5354	serge	363	/* i9xx, pch plls */
4104	Serge	364	uint32_t dpll;
		365	uint32_t dpll_md;
		366	uint32_t fp0;
		367	uint32_t fp1;
5354	serge	368
		369	/* hsw, bdw */
5060	serge	370	uint32_t wrpll;
6084	serge	371	uint32_t spll;
5354	serge	372
		373	/* skl */
		374	/*
		375	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
6084	serge	376	* lower part of ctrl1 and they get shifted into position when writing
5354	serge	377	* the register. This allows us to easily compare the state to share
		378	* the DPLL.
		379	*/
		380	uint32_t ctrl1;
		381	/* HDMI only, 0 when used for DP */
		382	uint32_t cfgcr1, cfgcr2;
6084	serge	383
		384	/* bxt */
		385	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		386	pcsdw12;
4104	Serge	387	};
		388
5354	serge	389	struct intel_shared_dpll_config {
		390	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
		391	struct intel_dpll_hw_state hw_state;
		392	};
		393
4104	Serge	394	struct intel_shared_dpll {
5354	serge	395	struct intel_shared_dpll_config config;
		396
3031	serge	397	int active; /* count of number of active CRTCs (i.e. DPMS on) */
		398	bool on; /* is the PLL actually active? Disabled during modeset */
4104	Serge	399	const char *name;
		400	/* should match the index in the dev_priv->shared_dplls array */
		401	enum intel_dpll_id id;
5060	serge	402	/* The mode_set hook is optional and should be used together with the
		403	* intel_prepare_shared_dpll function. */
4104	Serge	404	void (mode_set)(struct drm_i915_private dev_priv,
		405	struct intel_shared_dpll *pll);
		406	void (enable)(struct drm_i915_private dev_priv,
		407	struct intel_shared_dpll *pll);
		408	void (disable)(struct drm_i915_private dev_priv,
		409	struct intel_shared_dpll *pll);
		410	bool (get_hw_state)(struct drm_i915_private dev_priv,
		411	struct intel_shared_dpll *pll,
		412	struct intel_dpll_hw_state *hw_state);
3031	serge	413	};
		414
5354	serge	415	#define SKL_DPLL0 0
		416	#define SKL_DPLL1 1
		417	#define SKL_DPLL2 2
		418	#define SKL_DPLL3 3
		419
3480	Serge	420	/* Used by dp and fdi links */
		421	struct intel_link_m_n {
		422	uint32_t tu;
		423	uint32_t gmch_m;
		424	uint32_t gmch_n;
		425	uint32_t link_m;
		426	uint32_t link_n;
		427	};
		428
		429	void intel_link_compute_m_n(int bpp, int nlanes,
		430	int pixel_clock, int link_clock,
		431	struct intel_link_m_n *m_n);
		432
2325	Serge	433	/* Interface history:
		434	*
		435	* 1.1: Original.
		436	* 1.2: Add Power Management
		437	* 1.3: Add vblank support
		438	* 1.4: Fix cmdbuffer path, add heap destroy
		439	* 1.5: Add vblank pipe configuration
		440	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
		441	* - Support vertical blank on secondary display pipe
		442	*/
		443	#define DRIVER_MAJOR 1
		444	#define DRIVER_MINOR 6
		445	#define DRIVER_PATCHLEVEL 0
		446
		447	#define WATCH_LISTS 0
		448
		449	struct opregion_header;
		450	struct opregion_acpi;
		451	struct opregion_swsci;
		452	struct opregion_asle;
		453
		454	struct intel_opregion {
6084	serge	455	struct opregion_header *header;
		456	struct opregion_acpi *acpi;
		457	struct opregion_swsci *swsci;
4560	Serge	458	u32 swsci_gbda_sub_functions;
		459	u32 swsci_sbcb_sub_functions;
6084	serge	460	struct opregion_asle *asle;
6937	serge	461	void *rvda;
		462	const void *vbt;
		463	u32 vbt_size;
6084	serge	464	u32 *lid_state;
4560	Serge	465	struct work_struct asle_work;
2325	Serge	466	};
		467	#define OPREGION_SIZE (8*1024)
		468
		469	struct intel_overlay;
		470	struct intel_overlay_error_state;
		471
		472	#define I915_FENCE_REG_NONE -1
3746	Serge	473	#define I915_MAX_NUM_FENCES 32
		474	/* 32 fences + sign bit for FENCE_REG_NONE */
		475	#define I915_MAX_NUM_FENCE_BITS 6
2325	Serge	476
		477	struct drm_i915_fence_reg {
		478	struct list_head lru_list;
		479	struct drm_i915_gem_object *obj;
3031	serge	480	int pin_count;
2325	Serge	481	};
		482
		483	struct sdvo_device_mapping {
		484	u8 initialized;
		485	u8 dvo_port;
		486	u8 slave_addr;
		487	u8 dvo_wiring;
		488	u8 i2c_pin;
		489	u8 ddc_pin;
		490	};
		491
		492	struct intel_display_error_state;
		493
		494	struct drm_i915_error_state {
3243	Serge	495	struct kref ref;
5060	serge	496	struct timeval time;
		497
		498	char error_msg[128];
6084	serge	499	int iommu;
5060	serge	500	u32 reset_count;
		501	u32 suspend_count;
		502
		503	/* Generic register state */
2325	Serge	504	u32 eir;
		505	u32 pgtbl_er;
3031	serge	506	u32 ier;
5060	serge	507	u32 gtier[4];
3031	serge	508	u32 ccid;
3243	Serge	509	u32 derrmr;
		510	u32 forcewake;
2325	Serge	511	u32 error; /* gen6+ */
3031	serge	512	u32 err_int; /* gen7 */
6084	serge	513	u32 fault_data0; /* gen8, gen9 */
		514	u32 fault_data1; /* gen8, gen9 */
5060	serge	515	u32 done_reg;
		516	u32 gac_eco;
		517	u32 gam_ecochk;
		518	u32 gab_ctl;
		519	u32 gfx_mode;
3031	serge	520	u32 extra_instdone[I915_NUM_INSTDONE_REG];
2342	Serge	521	u64 fence[I915_MAX_NUM_FENCES];
5060	serge	522	struct intel_overlay_error_state *overlay;
		523	struct intel_display_error_state *display;
6084	serge	524	struct drm_i915_error_object *semaphore_obj;
5060	serge	525
3031	serge	526	struct drm_i915_error_ring {
4560	Serge	527	bool valid;
5060	serge	528	/* Software tracked state */
		529	bool waiting;
		530	int hangcheck_score;
		531	enum intel_ring_hangcheck_action hangcheck_action;
		532	int num_requests;
		533
		534	/* our own tracking of ring head and tail */
		535	u32 cpu_ring_head;
		536	u32 cpu_ring_tail;
		537
		538	u32 semaphore_seqno[I915_NUM_RINGS - 1];
		539
		540	/* Register state */
6084	serge	541	u32 start;
5060	serge	542	u32 tail;
		543	u32 head;
		544	u32 ctl;
		545	u32 hws;
		546	u32 ipeir;
		547	u32 ipehr;
		548	u32 instdone;
		549	u32 bbstate;
		550	u32 instpm;
		551	u32 instps;
		552	u32 seqno;
		553	u64 bbaddr;
		554	u64 acthd;
		555	u32 fault_reg;
		556	u64 faddr;
		557	u32 rc_psmi; /* sleep state */
		558	u32 semaphore_mboxes[I915_NUM_RINGS - 1];
		559
6084	serge	560	struct drm_i915_error_object {
		561	int page_count;
		562	u64 gtt_offset;
		563	u32 *pages[0];
5060	serge	564	} ringbuffer, batchbuffer, wa_batchbuffer, ctx, *hws_page;
		565
3031	serge	566	struct drm_i915_error_request {
		567	long jiffies;
		568	u32 seqno;
		569	u32 tail;
		570	} *requests;
5060	serge	571
		572	struct {
		573	u32 gfx_mode;
		574	union {
		575	u64 pdp[4];
		576	u32 pp_dir_base;
		577	};
		578	} vm_info;
		579
		580	pid_t pid;
		581	char comm[TASK_COMM_LEN];
3031	serge	582	} ring[I915_NUM_RINGS];
5354	serge	583
2325	Serge	584	struct drm_i915_error_buffer {
		585	u32 size;
		586	u32 name;
6084	serge	587	u32 rseqno[I915_NUM_RINGS], wseqno;
		588	u64 gtt_offset;
2325	Serge	589	u32 read_domains;
		590	u32 write_domain;
2342	Serge	591	s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
2325	Serge	592	s32 pinned:2;
		593	u32 tiling:2;
		594	u32 dirty:1;
		595	u32 purgeable:1;
5060	serge	596	u32 userptr:1;
3031	serge	597	s32 ring:4;
4560	Serge	598	u32 cache_level:3;
4104	Serge	599	} active_bo, pinned_bo;
5060	serge	600
4104	Serge	601	u32 active_bo_count, pinned_bo_count;
5354	serge	602	u32 vm_count;
2325	Serge	603	};
		604
4560	Serge	605	struct intel_connector;
5354	serge	606	struct intel_encoder;
6084	serge	607	struct intel_crtc_state;
		608	struct intel_initial_plane_config;
3746	Serge	609	struct intel_crtc;
4104	Serge	610	struct intel_limit;
		611	struct dpll;
3746	Serge	612
2325	Serge	613	struct drm_i915_display_funcs {
		614	int (get_display_clock_speed)(struct drm_device dev);
		615	int (get_fifo_size)(struct drm_device dev, int plane);
4104	Serge	616	/**
		617	* find_dpll() - Find the best values for the PLL
		618	* @limit: limits for the PLL
		619	* @crtc: current CRTC
		620	* @target: target frequency in kHz
		621	* @refclk: reference clock frequency in kHz
		622	* @match_clock: if provided, @best_clock P divider must
		623	* match the P divider from @match_clock
		624	* used for LVDS downclocking
		625	* @best_clock: best PLL values found
		626	*
		627	* Returns true on success, false on failure.
		628	*/
		629	bool (find_dpll)(const struct intel_limit limit,
6084	serge	630	struct intel_crtc_state *crtc_state,
4104	Serge	631	int target, int refclk,
		632	struct dpll *match_clock,
		633	struct dpll *best_clock);
6937	serge	634	int (compute_pipe_wm)(struct intel_crtc crtc,
		635	struct drm_atomic_state *state);
4560	Serge	636	void (update_wm)(struct drm_crtc crtc);
6084	serge	637	int (modeset_calc_cdclk)(struct drm_atomic_state state);
		638	void (modeset_commit_cdclk)(struct drm_atomic_state state);
3746	Serge	639	/* Returns the active state of the crtc, and if the crtc is active,
		640	* fills out the pipe-config with the hw state. */
		641	bool (get_pipe_config)(struct intel_crtc ,
6084	serge	642	struct intel_crtc_state *);
		643	void (get_initial_plane_config)(struct intel_crtc ,
		644	struct intel_initial_plane_config *);
		645	int (crtc_compute_clock)(struct intel_crtc crtc,
		646	struct intel_crtc_state *crtc_state);
3031	serge	647	void (crtc_enable)(struct drm_crtc crtc);
		648	void (crtc_disable)(struct drm_crtc crtc);
5354	serge	649	void (audio_codec_enable)(struct drm_connector connector,
		650	struct intel_encoder *encoder,
6084	serge	651	const struct drm_display_mode *adjusted_mode);
5354	serge	652	void (audio_codec_disable)(struct intel_encoder encoder);
2325	Serge	653	void (fdi_link_train)(struct drm_crtc crtc);
		654	void (init_clock_gating)(struct drm_device dev);
		655	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,
		656	struct drm_framebuffer *fb,
4104	Serge	657	struct drm_i915_gem_object *obj,
6084	serge	658	struct drm_i915_gem_request *req,
4104	Serge	659	uint32_t flags);
5060	serge	660	void (update_primary_plane)(struct drm_crtc crtc,
6084	serge	661	struct drm_framebuffer *fb,
		662	int x, int y);
3480	Serge	663	void (hpd_irq_setup)(struct drm_device dev);
2325	Serge	664	/* clock updates for mode set */
		665	/* cursor updates */
		666	/* render clock increase/decrease */
		667	/* display clock increase/decrease */
		668	/* pll clock increase/decrease */
6084	serge	669	};
4560	Serge	670
6084	serge	671	enum forcewake_domain_id {
		672	FW_DOMAIN_ID_RENDER = 0,
		673	FW_DOMAIN_ID_BLITTER,
		674	FW_DOMAIN_ID_MEDIA,
		675
		676	FW_DOMAIN_ID_COUNT
2325	Serge	677	};
		678
6084	serge	679	enum forcewake_domains {
		680	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
		681	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
		682	FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
		683	FORCEWAKE_ALL = (FORCEWAKE_RENDER \|
		684	FORCEWAKE_BLITTER \|
		685	FORCEWAKE_MEDIA)
		686	};
		687
4104	Serge	688	struct intel_uncore_funcs {
4560	Serge	689	void (force_wake_get)(struct drm_i915_private dev_priv,
6084	serge	690	enum forcewake_domains domains);
4560	Serge	691	void (force_wake_put)(struct drm_i915_private dev_priv,
6084	serge	692	enum forcewake_domains domains);
4560	Serge	693
6937	serge	694	uint8_t (mmio_readb)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		695	uint16_t (mmio_readw)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		696	uint32_t (mmio_readl)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
		697	uint64_t (mmio_readq)(struct drm_i915_private dev_priv, i915_reg_t r, bool trace);
4560	Serge	698
6937	serge	699	void (mmio_writeb)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	700	uint8_t val, bool trace);
6937	serge	701	void (mmio_writew)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	702	uint16_t val, bool trace);
6937	serge	703	void (mmio_writel)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	704	uint32_t val, bool trace);
6937	serge	705	void (mmio_writeq)(struct drm_i915_private dev_priv, i915_reg_t r,
4560	Serge	706	uint64_t val, bool trace);
3031	serge	707	};
		708
4104	Serge	709	struct intel_uncore {
		710	spinlock_t lock; /** lock is also taken in irq contexts. */
3031	serge	711
4104	Serge	712	struct intel_uncore_funcs funcs;
		713
		714	unsigned fifo_count;
6084	serge	715	enum forcewake_domains fw_domains;
4560	Serge	716
6084	serge	717	struct intel_uncore_forcewake_domain {
		718	struct drm_i915_private *i915;
		719	enum forcewake_domain_id id;
		720	unsigned wake_count;
		721	struct timer_list timer;
6937	serge	722	i915_reg_t reg_set;
6084	serge	723	u32 val_set;
		724	u32 val_clear;
6937	serge	725	i915_reg_t reg_ack;
		726	i915_reg_t reg_post;
6084	serge	727	u32 val_reset;
		728	} fw_domain[FW_DOMAIN_ID_COUNT];
		729	};
4560	Serge	730
6084	serge	731	/* Iterate over initialised fw domains */
		732	#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
		733	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
		734	(i__) < FW_DOMAIN_ID_COUNT; \
		735	(i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
6937	serge	736	for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
6084	serge	737
		738	#define for_each_fw_domain(domain__, dev_priv__, i__) \
		739	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
		740
6937	serge	741	#define CSR_VERSION(major, minor) ((major) << 16 \| (minor))
		742	#define CSR_VERSION_MAJOR(version) ((version) >> 16)
		743	#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
4104	Serge	744
6084	serge	745	struct intel_csr {
6937	serge	746	struct work_struct work;
6084	serge	747	const char *fw_path;
		748	uint32_t *dmc_payload;
		749	uint32_t dmc_fw_size;
6937	serge	750	uint32_t version;
6084	serge	751	uint32_t mmio_count;
6937	serge	752	i915_reg_t mmioaddr[8];
6084	serge	753	uint32_t mmiodata[8];
6937	serge	754	uint32_t dc_state;
6084	serge	755	};
		756
4104	Serge	757	#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
		758	func(is_mobile) sep \
		759	func(is_i85x) sep \
		760	func(is_i915g) sep \
		761	func(is_i945gm) sep \
		762	func(is_g33) sep \
		763	func(need_gfx_hws) sep \
		764	func(is_g4x) sep \
		765	func(is_pineview) sep \
		766	func(is_broadwater) sep \
		767	func(is_crestline) sep \
		768	func(is_ivybridge) sep \
		769	func(is_valleyview) sep \
6937	serge	770	func(is_cherryview) sep \
4104	Serge	771	func(is_haswell) sep \
5354	serge	772	func(is_skylake) sep \
6937	serge	773	func(is_broxton) sep \
		774	func(is_kabylake) sep \
4560	Serge	775	func(is_preliminary) sep \
4104	Serge	776	func(has_fbc) sep \
		777	func(has_pipe_cxsr) sep \
		778	func(has_hotplug) sep \
		779	func(cursor_needs_physical) sep \
		780	func(has_overlay) sep \
		781	func(overlay_needs_physical) sep \
		782	func(supports_tv) sep \
		783	func(has_llc) sep \
		784	func(has_ddi) sep \
		785	func(has_fpga_dbg)
		786
		787	#define DEFINE_FLAG(name) u8 name:1
		788	#define SEP_SEMICOLON ;
		789
2325	Serge	790	struct intel_device_info {
3480	Serge	791	u32 display_mmio_offset;
5354	serge	792	u16 device_id;
3746	Serge	793	u8 num_pipes:3;
5060	serge	794	u8 num_sprites[I915_MAX_PIPES];
2325	Serge	795	u8 gen;
4560	Serge	796	u8 ring_mask; /* Rings supported by the HW */
4104	Serge	797	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
5060	serge	798	/* Register offsets for the various display pipes and transcoders */
		799	int pipe_offsets[I915_MAX_TRANSCODERS];
		800	int trans_offsets[I915_MAX_TRANSCODERS];
		801	int palette_offsets[I915_MAX_PIPES];
		802	int cursor_offsets[I915_MAX_PIPES];
6084	serge	803
		804	/* Slice/subslice/EU info */
		805	u8 slice_total;
		806	u8 subslice_total;
		807	u8 subslice_per_slice;
		808	u8 eu_total;
		809	u8 eu_per_subslice;
		810	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
		811	u8 subslice_7eu[3];
		812	u8 has_slice_pg:1;
		813	u8 has_subslice_pg:1;
		814	u8 has_eu_pg:1;
2325	Serge	815	};
		816
4104	Serge	817	#undef DEFINE_FLAG
		818	#undef SEP_SEMICOLON
		819
3480	Serge	820	enum i915_cache_level {
		821	I915_CACHE_NONE = 0,
4104	Serge	822	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
		823	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
		824	caches, eg sampler/render caches, and the
		825	large Last-Level-Cache. LLC is coherent with
		826	the CPU, but L3 is only visible to the GPU. */
		827	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
3480	Serge	828	};
		829
4104	Serge	830	struct i915_ctx_hang_stats {
		831	/* This context had batch pending when hang was declared */
		832	unsigned batch_pending;
		833
		834	/* This context had batch active when hang was declared */
		835	unsigned batch_active;
4560	Serge	836
		837	/* Time when this context was last blamed for a GPU reset */
		838	unsigned long guilty_ts;
		839
6084	serge	840	/* If the contexts causes a second GPU hang within this time,
		841	* it is permanently banned from submitting any more work.
		842	*/
		843	unsigned long ban_period_seconds;
		844
4560	Serge	845	/* This context is banned to submit more work */
		846	bool banned;
4104	Serge	847	};
		848
3031	serge	849	/* This must match up with the value previously used for execbuf2.rsvd1. */
5060	serge	850	#define DEFAULT_CONTEXT_HANDLE 0
6084	serge	851
		852	#define CONTEXT_NO_ZEROMAP (1<<0)
5060	serge	853	/**
		854	* struct intel_context - as the name implies, represents a context.
		855	* @ref: reference count.
		856	* @user_handle: userspace tracking identity for this context.
		857	* @remap_slice: l3 row remapping information.
6084	serge	858	* @flags: context specific flags:
		859	* CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
5060	serge	860	* @file_priv: filp associated with this context (NULL for global default
		861	* context).
		862	* @hang_stats: information about the role of this context in possible GPU
		863	* hangs.
6084	serge	864	* @ppgtt: virtual memory space used by this context.
5060	serge	865	* @legacy_hw_ctx: render context backing object and whether it is correctly
		866	* initialized (legacy ring submission mechanism only).
		867	* @link: link in the global list of contexts.
		868	*
		869	* Contexts are memory images used by the hardware to store copies of their
		870	* internal state.
		871	*/
		872	struct intel_context {
4104	Serge	873	struct kref ref;
5060	serge	874	int user_handle;
4560	Serge	875	uint8_t remap_slice;
6084	serge	876	struct drm_i915_private *i915;
		877	int flags;
3031	serge	878	struct drm_i915_file_private *file_priv;
4104	Serge	879	struct i915_ctx_hang_stats hang_stats;
5354	serge	880	struct i915_hw_ppgtt *ppgtt;
4560	Serge	881
5354	serge	882	/* Legacy ring buffer submission */
5060	serge	883	struct {
		884	struct drm_i915_gem_object *rcs_state;
		885	bool initialized;
		886	} legacy_hw_ctx;
		887
5354	serge	888	/* Execlists */
		889	struct {
		890	struct drm_i915_gem_object *state;
		891	struct intel_ringbuffer *ringbuf;
6084	serge	892	int pin_count;
5354	serge	893	} engine[I915_NUM_RINGS];
		894
4560	Serge	895	struct list_head link;
3031	serge	896	};
		897
6084	serge	898	enum fb_op_origin {
		899	ORIGIN_GTT,
		900	ORIGIN_CPU,
		901	ORIGIN_CS,
		902	ORIGIN_FLIP,
		903	ORIGIN_DIRTYFB,
		904	};
		905
4104	Serge	906	struct i915_fbc {
6084	serge	907	/* This is always the inner lock when overlapping with struct_mutex and
		908	* it's the outer lock when overlapping with stolen_lock. */
		909	struct mutex lock;
5060	serge	910	unsigned threshold;
4104	Serge	911	unsigned int fb_id;
6084	serge	912	unsigned int possible_framebuffer_bits;
		913	unsigned int busy_bits;
		914	struct intel_crtc *crtc;
4104	Serge	915	int y;
		916
5060	serge	917	struct drm_mm_node compressed_fb;
4104	Serge	918	struct drm_mm_node *compressed_llb;
		919
5354	serge	920	bool false_color;
		921
		922	bool enabled;
6937	serge	923	bool active;
5354	serge	924
4104	Serge	925	struct intel_fbc_work {
6937	serge	926	bool scheduled;
		927	struct work_struct work;
4104	Serge	928	struct drm_framebuffer *fb;
6937	serge	929	unsigned long enable_jiffies;
		930	} work;
4104	Serge	931
6937	serge	932	const char *no_fbc_reason;
6084	serge	933
6937	serge	934	bool (is_active)(struct drm_i915_private dev_priv);
		935	void (activate)(struct intel_crtc crtc);
		936	void (deactivate)(struct drm_i915_private dev_priv);
2325	Serge	937	};
		938
6084	serge	939	/**
		940	* HIGH_RR is the highest eDP panel refresh rate read from EDID
		941	* LOW_RR is the lowest eDP panel refresh rate found from EDID
		942	* parsing for same resolution.
		943	*/
		944	enum drrs_refresh_rate_type {
		945	DRRS_HIGH_RR,
		946	DRRS_LOW_RR,
		947	DRRS_MAX_RR, /* RR count */
		948	};
		949
		950	enum drrs_support_type {
		951	DRRS_NOT_SUPPORTED = 0,
		952	STATIC_DRRS_SUPPORT = 1,
		953	SEAMLESS_DRRS_SUPPORT = 2
		954	};
		955
		956	struct intel_dp;
5060	serge	957	struct i915_drrs {
6084	serge	958	struct mutex mutex;
		959	struct delayed_work work;
		960	struct intel_dp *dp;
		961	unsigned busy_frontbuffer_bits;
		962	enum drrs_refresh_rate_type refresh_rate_type;
		963	enum drrs_support_type type;
5060	serge	964	};
		965
4560	Serge	966	struct i915_psr {
5060	serge	967	struct mutex lock;
4560	Serge	968	bool sink_support;
		969	bool source_ok;
5060	serge	970	struct intel_dp *enabled;
		971	bool active;
		972	struct delayed_work work;
		973	unsigned busy_frontbuffer_bits;
6084	serge	974	bool psr2_support;
		975	bool aux_frame_sync;
4104	Serge	976	};
		977
2325	Serge	978	enum intel_pch {
3031	serge	979	PCH_NONE = 0, /* No PCH present */
2325	Serge	980	PCH_IBX, /* Ibexpeak PCH */
		981	PCH_CPT, /* Cougarpoint PCH */
3031	serge	982	PCH_LPT, /* Lynxpoint PCH */
5354	serge	983	PCH_SPT, /* Sunrisepoint PCH */
3746	Serge	984	PCH_NOP,
2325	Serge	985	};
		986
3243	Serge	987	enum intel_sbi_destination {
		988	SBI_ICLK,
		989	SBI_MPHY,
		990	};
		991
2325	Serge	992	#define QUIRK_PIPEA_FORCE (1<<0)
		993	#define QUIRK_LVDS_SSC_DISABLE (1<<1)
3031	serge	994	#define QUIRK_INVERT_BRIGHTNESS (1<<2)
5060	serge	995	#define QUIRK_BACKLIGHT_PRESENT (1<<3)
5354	serge	996	#define QUIRK_PIPEB_FORCE (1<<4)
		997	#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
2325	Serge	998
		999	struct intel_fbdev;
		1000	struct intel_fbc_work;
		1001
3031	serge	1002	struct intel_gmbus {
		1003	struct i2c_adapter adapter;
3243	Serge	1004	u32 force_bit;
3031	serge	1005	u32 reg0;
6937	serge	1006	i915_reg_t gpio_reg;
3031	serge	1007	struct i2c_algo_bit_data bit_algo;
		1008	struct drm_i915_private *dev_priv;
		1009	};
		1010
3243	Serge	1011	struct i915_suspend_saved_registers {
2325	Serge	1012	u32 saveDSPARB;
		1013	u32 saveLVDS;
		1014	u32 savePP_ON_DELAYS;
		1015	u32 savePP_OFF_DELAYS;
		1016	u32 savePP_ON;
		1017	u32 savePP_OFF;
		1018	u32 savePP_CONTROL;
		1019	u32 savePP_DIVISOR;
		1020	u32 saveFBC_CONTROL;
		1021	u32 saveCACHE_MODE_0;
		1022	u32 saveMI_ARB_STATE;
		1023	u32 saveSWF0[16];
		1024	u32 saveSWF1[16];
6084	serge	1025	u32 saveSWF3[3];
2342	Serge	1026	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
2325	Serge	1027	u32 savePCH_PORT_HOTPLUG;
5354	serge	1028	u16 saveGCDGMBUS;
3243	Serge	1029	};
2325	Serge	1030
5060	serge	1031	struct vlv_s0ix_state {
		1032	/* GAM */
		1033	u32 wr_watermark;
		1034	u32 gfx_prio_ctrl;
		1035	u32 arb_mode;
		1036	u32 gfx_pend_tlb0;
		1037	u32 gfx_pend_tlb1;
		1038	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
		1039	u32 media_max_req_count;
		1040	u32 gfx_max_req_count;
		1041	u32 render_hwsp;
		1042	u32 ecochk;
		1043	u32 bsd_hwsp;
		1044	u32 blt_hwsp;
		1045	u32 tlb_rd_addr;
		1046
		1047	/* MBC */
		1048	u32 g3dctl;
		1049	u32 gsckgctl;
		1050	u32 mbctl;
		1051
		1052	/* GCP */
		1053	u32 ucgctl1;
		1054	u32 ucgctl3;
		1055	u32 rcgctl1;
		1056	u32 rcgctl2;
		1057	u32 rstctl;
		1058	u32 misccpctl;
		1059
		1060	/* GPM */
		1061	u32 gfxpause;
		1062	u32 rpdeuhwtc;
		1063	u32 rpdeuc;
		1064	u32 ecobus;
		1065	u32 pwrdwnupctl;
		1066	u32 rp_down_timeout;
		1067	u32 rp_deucsw;
		1068	u32 rcubmabdtmr;
		1069	u32 rcedata;
		1070	u32 spare2gh;
		1071
		1072	/* Display 1 CZ domain */
		1073	u32 gt_imr;
		1074	u32 gt_ier;
		1075	u32 pm_imr;
		1076	u32 pm_ier;
		1077	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
		1078
		1079	/* GT SA CZ domain */
		1080	u32 tilectl;
		1081	u32 gt_fifoctl;
		1082	u32 gtlc_wake_ctrl;
		1083	u32 gtlc_survive;
		1084	u32 pmwgicz;
		1085
		1086	/* Display 2 CZ domain */
		1087	u32 gu_ctl0;
		1088	u32 gu_ctl1;
6084	serge	1089	u32 pcbr;
5060	serge	1090	u32 clock_gate_dis2;
		1091	};
		1092
		1093	struct intel_rps_ei {
		1094	u32 cz_clock;
		1095	u32 render_c0;
		1096	u32 media_c0;
		1097	};
		1098
3243	Serge	1099	struct intel_gen6_power_mgmt {
5354	serge	1100	/*
		1101	* work, interrupts_enabled and pm_iir are protected by
		1102	* dev_priv->irq_lock
		1103	*/
3243	Serge	1104	struct work_struct work;
5354	serge	1105	bool interrupts_enabled;
3243	Serge	1106	u32 pm_iir;
		1107
5060	serge	1108	/* Frequencies are stored in potentially platform dependent multiples.
		1109	* In other words, *_freq needs to be multiplied by X to be interesting.
		1110	* Soft limits are those which are used for the dynamic reclocking done
		1111	* by the driver (raise frequencies under heavy loads, and lower for
		1112	* lighter loads). Hard limits are those imposed by the hardware.
		1113	*
		1114	* A distinction is made for overclocking, which is never enabled by
		1115	* default, and is considered to be above the hard limit if it's
		1116	* possible at all.
		1117	*/
		1118	u8 cur_freq; /* Current frequency (cached, may not == HW) */
		1119	u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
		1120	u8 max_freq_softlimit; /* Max frequency permitted by the driver */
		1121	u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
		1122	u8 min_freq; /* AKA RPn. Minimum frequency */
6084	serge	1123	u8 idle_freq; /* Frequency to request when we are idle */
5060	serge	1124	u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
		1125	u8 rp1_freq; /* "less than" RP0 power/freqency */
		1126	u8 rp0_freq; /* Non-overclocked max frequency. */
3243	Serge	1127
6084	serge	1128	u8 up_threshold; /* Current %busy required to uplock */
		1129	u8 down_threshold; /* Current %busy required to downclock */
5060	serge	1130
4560	Serge	1131	int last_adj;
		1132	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
		1133
6084	serge	1134	spinlock_t client_lock;
		1135	struct list_head clients;
		1136	bool client_boost;
		1137
4560	Serge	1138	bool enabled;
3243	Serge	1139	struct delayed_work delayed_resume_work;
6084	serge	1140	unsigned boosts;
3243	Serge	1141
6084	serge	1142	struct intel_rps_client semaphores, mmioflips;
		1143
5060	serge	1144	/* manual wa residency calculations */
6937	serge	1145	struct intel_rps_ei up_ei, down_ei;
5060	serge	1146
3243	Serge	1147	/*
		1148	* Protects RPS/RC6 register access and PCU communication.
6084	serge	1149	* Must be taken after struct_mutex if nested. Note that
		1150	* this lock may be held for long periods of time when
		1151	* talking to hw - so only take it when talking to hw!
3243	Serge	1152	*/
		1153	struct mutex hw_lock;
		1154	};
		1155
3480	Serge	1156	/* defined intel_pm.c */
		1157	extern spinlock_t mchdev_lock;
		1158
3243	Serge	1159	struct intel_ilk_power_mgmt {
		1160	u8 cur_delay;
		1161	u8 min_delay;
		1162	u8 max_delay;
		1163	u8 fmax;
		1164	u8 fstart;
		1165
		1166	u64 last_count1;
		1167	unsigned long last_time1;
		1168	unsigned long chipset_power;
		1169	u64 last_count2;
5060	serge	1170	u64 last_time2;
3243	Serge	1171	unsigned long gfx_power;
		1172	u8 corr;
		1173
		1174	int c_m;
		1175	int r_t;
		1176	};
		1177
5060	serge	1178	struct drm_i915_private;
		1179	struct i915_power_well;
		1180
		1181	struct i915_power_well_ops {
		1182	/*
		1183	* Synchronize the well's hw state to match the current sw state, for
		1184	* example enable/disable it based on the current refcount. Called
		1185	* during driver init and resume time, possibly after first calling
		1186	* the enable/disable handlers.
		1187	*/
		1188	void (sync_hw)(struct drm_i915_private dev_priv,
		1189	struct i915_power_well *power_well);
		1190	/*
		1191	* Enable the well and resources that depend on it (for example
		1192	* interrupts located on the well). Called after the 0->1 refcount
		1193	* transition.
		1194	*/
		1195	void (enable)(struct drm_i915_private dev_priv,
		1196	struct i915_power_well *power_well);
		1197	/*
		1198	* Disable the well and resources that depend on it. Called after
		1199	* the 1->0 refcount transition.
		1200	*/
		1201	void (disable)(struct drm_i915_private dev_priv,
		1202	struct i915_power_well *power_well);
		1203	/* Returns the hw enabled state. */
		1204	bool (is_enabled)(struct drm_i915_private dev_priv,
		1205	struct i915_power_well *power_well);
		1206	};
		1207
4104	Serge	1208	/* Power well structure for haswell */
		1209	struct i915_power_well {
4560	Serge	1210	const char *name;
		1211	bool always_on;
4104	Serge	1212	/* power well enable/disable usage count */
		1213	int count;
5060	serge	1214	/* cached hw enabled state */
		1215	bool hw_enabled;
4560	Serge	1216	unsigned long domains;
5060	serge	1217	unsigned long data;
		1218	const struct i915_power_well_ops *ops;
4104	Serge	1219	};
		1220
4560	Serge	1221	struct i915_power_domains {
		1222	/*
		1223	* Power wells needed for initialization at driver init and suspend
		1224	* time are on. They are kept on until after the first modeset.
		1225	*/
		1226	bool init_power_on;
5060	serge	1227	bool initializing;
4560	Serge	1228	int power_well_count;
		1229
		1230	struct mutex lock;
		1231	int domain_use_count[POWER_DOMAIN_NUM];
		1232	struct i915_power_well *power_wells;
		1233	};
		1234
		1235	#define MAX_L3_SLICES 2
3243	Serge	1236	struct intel_l3_parity {
4560	Serge	1237	u32 *remap_info[MAX_L3_SLICES];
3243	Serge	1238	struct work_struct error_work;
4560	Serge	1239	int which_slice;
3243	Serge	1240	};
		1241
3480	Serge	1242	struct i915_gem_mm {
		1243	/** Memory allocator for GTT stolen memory */
		1244	struct drm_mm stolen;
6084	serge	1245	/** Protects the usage of the GTT stolen memory allocator. This is
		1246	* always the inner lock when overlapping with struct_mutex. */
		1247	struct mutex stolen_lock;
		1248
3480	Serge	1249	/** List of all objects in gtt_space. Used to restore gtt
		1250	* mappings on resume */
		1251	struct list_head bound_list;
		1252	/**
		1253	* List of objects which are not bound to the GTT (thus
		1254	* are idle and not used by the GPU) but still have
		1255	* (presumably uncached) pages still attached.
		1256	*/
		1257	struct list_head unbound_list;
		1258
		1259	/** Usable portion of the GTT for GEM */
		1260	unsigned long stolen_base; /* limited to low memory (32-bit) */
		1261
		1262	/** PPGTT used for aliasing the PPGTT with the GTT */
		1263	struct i915_hw_ppgtt *aliasing_ppgtt;
		1264
6937	serge	1265	struct notifier_block oom_notifier;
3480	Serge	1266	/** LRU list of objects with fence regs on them. */
		1267	struct list_head fence_list;
		1268
		1269	/**
		1270	* We leave the user IRQ off as much as possible,
		1271	* but this means that requests will finish and never
		1272	* be retired once the system goes idle. Set a timer to
		1273	* fire periodically while the ring is running. When it
		1274	* fires, go retire requests.
		1275	*/
		1276	struct delayed_work retire_work;
		1277
		1278	/**
4560	Serge	1279	* When we detect an idle GPU, we want to turn on
		1280	* powersaving features. So once we see that there
		1281	* are no more requests outstanding and no more
		1282	* arrive within a small period of time, we fire
		1283	* off the idle_work.
		1284	*/
		1285	struct delayed_work idle_work;
		1286
		1287	/**
3480	Serge	1288	* Are we in a non-interruptible section of code like
		1289	* modesetting?
		1290	*/
		1291	bool interruptible;
		1292
5060	serge	1293	/**
		1294	* Is the GPU currently considered idle, or busy executing userspace
		1295	* requests? Whilst idle, we attempt to power down the hardware and
		1296	* display clocks. In order to reduce the effect on performance, there
		1297	* is a slight delay before we do so.
		1298	*/
		1299	bool busy;
		1300
		1301	/* the indicator for dispatch video commands on two BSD rings */
		1302	int bsd_ring_dispatch_index;
		1303
3480	Serge	1304	/** Bit 6 swizzling required for X tiling */
		1305	uint32_t bit_6_swizzle_x;
		1306	/** Bit 6 swizzling required for Y tiling */
		1307	uint32_t bit_6_swizzle_y;
		1308
		1309	/* accounting, useful for userland debugging */
4104	Serge	1310	spinlock_t object_stat_lock;
3480	Serge	1311	size_t object_memory;
		1312	u32 object_count;
		1313	};
		1314
4104	Serge	1315	struct drm_i915_error_state_buf {
5354	serge	1316	struct drm_i915_private *i915;
4104	Serge	1317	unsigned bytes;
		1318	unsigned size;
		1319	int err;
		1320	u8 *buf;
		1321	loff_t start;
		1322	loff_t pos;
		1323	};
		1324
		1325	struct i915_error_state_file_priv {
		1326	struct drm_device *dev;
		1327	struct drm_i915_error_state *error;
		1328	};
		1329
3480	Serge	1330	struct i915_gpu_error {
		1331	/* For hangcheck timer */
		1332	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
		1333	#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
4560	Serge	1334	/* Hang gpu twice in this window and your context gets banned */
		1335	#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
		1336
6084	serge	1337	struct workqueue_struct *hangcheck_wq;
		1338	struct delayed_work hangcheck_work;
3480	Serge	1339
		1340	/* For reset and error_state handling. */
		1341	spinlock_t lock;
		1342	/* Protected by the above dev->gpu_error.lock. */
		1343	struct drm_i915_error_state *first_error;
		1344
4560	Serge	1345	unsigned long missed_irq_rings;
		1346
3480	Serge	1347	/**
4560	Serge	1348	* State variable controlling the reset flow and count
3480	Serge	1349	*
4560	Serge	1350	* This is a counter which gets incremented when reset is triggered,
		1351	* and again when reset has been handled. So odd values (lowest bit set)
		1352	* means that reset is in progress and even values that
		1353	* (reset_counter >> 1):th reset was successfully completed.
3480	Serge	1354	*
4560	Serge	1355	* If reset is not completed succesfully, the I915_WEDGE bit is
		1356	* set meaning that hardware is terminally sour and there is no
		1357	* recovery. All waiters on the reset_queue will be woken when
		1358	* that happens.
		1359	*
		1360	* This counter is used by the wait_seqno code to notice that reset
		1361	* event happened and it needs to restart the entire ioctl (since most
		1362	* likely the seqno it waited for won't ever signal anytime soon).
		1363	*
3480	Serge	1364	* This is important for lock-free wait paths, where no contended lock
		1365	* naturally enforces the correct ordering between the bail-out of the
		1366	* waiter and the gpu reset work code.
		1367	*/
		1368	atomic_t reset_counter;
		1369
		1370	#define I915_RESET_IN_PROGRESS_FLAG 1
4560	Serge	1371	#define I915_WEDGED (1 << 31)
3480	Serge	1372
		1373	/**
		1374	* Waitqueue to signal when the reset has completed. Used by clients
		1375	* that wait for dev_priv->mm.wedged to settle.
		1376	*/
		1377	wait_queue_head_t reset_queue;
		1378
5060	serge	1379	/* Userspace knobs for gpu hang simulation;
		1380	* combines both a ring mask, and extra flags
		1381	*/
		1382	u32 stop_rings;
		1383	#define I915_STOP_RING_ALLOW_BAN (1 << 31)
		1384	#define I915_STOP_RING_ALLOW_WARN (1 << 30)
4560	Serge	1385
		1386	/* For missed irq/seqno simulation. */
		1387	unsigned int test_irq_rings;
5354	serge	1388
		1389	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
		1390	bool reload_in_reset;
3480	Serge	1391	};
		1392
		1393	enum modeset_restore {
		1394	MODESET_ON_LID_OPEN,
		1395	MODESET_DONE,
		1396	MODESET_SUSPENDED,
		1397	};
		1398
6084	serge	1399	#define DP_AUX_A 0x40
		1400	#define DP_AUX_B 0x10
		1401	#define DP_AUX_C 0x20
		1402	#define DP_AUX_D 0x30
		1403
		1404	#define DDC_PIN_B 0x05
		1405	#define DDC_PIN_C 0x04
		1406	#define DDC_PIN_D 0x06
		1407
4560	Serge	1408	struct ddi_vbt_port_info {
5354	serge	1409	/*
		1410	* This is an index in the HDMI/DVI DDI buffer translation table.
		1411	* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
		1412	* populate this field.
		1413	*/
		1414	#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
4560	Serge	1415	uint8_t hdmi_level_shift;
		1416
		1417	uint8_t supports_dvi:1;
		1418	uint8_t supports_hdmi:1;
		1419	uint8_t supports_dp:1;
6084	serge	1420
		1421	uint8_t alternate_aux_channel;
		1422	uint8_t alternate_ddc_pin;
		1423
		1424	uint8_t dp_boost_level;
		1425	uint8_t hdmi_boost_level;
4560	Serge	1426	};
		1427
6084	serge	1428	enum psr_lines_to_wait {
		1429	PSR_0_LINES_TO_WAIT = 0,
		1430	PSR_1_LINE_TO_WAIT,
		1431	PSR_4_LINES_TO_WAIT,
		1432	PSR_8_LINES_TO_WAIT
5060	serge	1433	};
		1434
4104	Serge	1435	struct intel_vbt_data {
		1436	struct drm_display_mode lfp_lvds_vbt_mode; / if any */
		1437	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */
		1438
		1439	/* Feature bits */
		1440	unsigned int int_tv_support:1;
		1441	unsigned int lvds_dither:1;
		1442	unsigned int lvds_vbt:1;
		1443	unsigned int int_crt_support:1;
		1444	unsigned int lvds_use_ssc:1;
		1445	unsigned int display_clock_mode:1;
		1446	unsigned int fdi_rx_polarity_inverted:1;
5060	serge	1447	unsigned int has_mipi:1;
4104	Serge	1448	int lvds_ssc_freq;
		1449	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
		1450
5060	serge	1451	enum drrs_support_type drrs_type;
		1452
4104	Serge	1453	/* eDP */
		1454	int edp_rate;
		1455	int edp_lanes;
		1456	int edp_preemphasis;
		1457	int edp_vswing;
		1458	bool edp_initialized;
		1459	bool edp_support;
		1460	int edp_bpp;
		1461	struct edp_power_seq edp_pps;
		1462
4560	Serge	1463	struct {
6084	serge	1464	bool full_link;
		1465	bool require_aux_wakeup;
		1466	int idle_frames;
		1467	enum psr_lines_to_wait lines_to_wait;
		1468	int tp1_wakeup_time;
		1469	int tp2_tp3_wakeup_time;
		1470	} psr;
		1471
		1472	struct {
4560	Serge	1473	u16 pwm_freq_hz;
5060	serge	1474	bool present;
4560	Serge	1475	bool active_low_pwm;
5060	serge	1476	u8 min_brightness; /* min_brightness/255 of max */
4560	Serge	1477	} backlight;
		1478
		1479	/* MIPI DSI */
		1480	struct {
5060	serge	1481	u16 port;
4560	Serge	1482	u16 panel_id;
5060	serge	1483	struct mipi_config *config;
		1484	struct mipi_pps_data *pps;
		1485	u8 seq_version;
		1486	u32 size;
		1487	u8 *data;
		1488	u8 *sequence[MIPI_SEQ_MAX];
4560	Serge	1489	} dsi;
		1490
4104	Serge	1491	int crt_ddc_pin;
		1492
		1493	int child_dev_num;
4560	Serge	1494	union child_device_config *child_dev;
		1495
		1496	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
4104	Serge	1497	};
		1498
		1499	enum intel_ddb_partitioning {
		1500	INTEL_DDB_PART_1_2,
		1501	INTEL_DDB_PART_5_6, /* IVB+ */
		1502	};
		1503
		1504	struct intel_wm_level {
		1505	bool enable;
		1506	uint32_t pri_val;
		1507	uint32_t spr_val;
		1508	uint32_t cur_val;
		1509	uint32_t fbc_val;
		1510	};
		1511
4560	Serge	1512	struct ilk_wm_values {
		1513	uint32_t wm_pipe[3];
		1514	uint32_t wm_lp[3];
		1515	uint32_t wm_lp_spr[3];
		1516	uint32_t wm_linetime[3];
		1517	bool enable_fbc_wm;
		1518	enum intel_ddb_partitioning partitioning;
		1519	};
		1520
6084	serge	1521	struct vlv_pipe_wm {
		1522	uint16_t primary;
		1523	uint16_t sprite[2];
		1524	uint8_t cursor;
		1525	};
		1526
		1527	struct vlv_sr_wm {
		1528	uint16_t plane;
		1529	uint8_t cursor;
		1530	};
		1531
		1532	struct vlv_wm_values {
		1533	struct vlv_pipe_wm pipe[3];
		1534	struct vlv_sr_wm sr;
		1535	struct {
		1536	uint8_t cursor;
		1537	uint8_t sprite[2];
		1538	uint8_t primary;
		1539	} ddl[3];
		1540	uint8_t level;
		1541	bool cxsr;
		1542	};
		1543
5354	serge	1544	struct skl_ddb_entry {
		1545	uint16_t start, end; /* in number of blocks, 'end' is exclusive */
		1546	};
		1547
		1548	static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
		1549	{
		1550	return entry->end - entry->start;
		1551	}
		1552
		1553	static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
		1554	const struct skl_ddb_entry *e2)
		1555	{
		1556	if (e1->start == e2->start && e1->end == e2->end)
		1557	return true;
		1558
		1559	return false;
		1560	}
		1561
		1562	struct skl_ddb_allocation {
		1563	struct skl_ddb_entry pipe[I915_MAX_PIPES];
6084	serge	1564	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
		1565	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
5354	serge	1566	};
		1567
		1568	struct skl_wm_values {
		1569	bool dirty[I915_MAX_PIPES];
		1570	struct skl_ddb_allocation ddb;
		1571	uint32_t wm_linetime[I915_MAX_PIPES];
		1572	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
		1573	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
		1574	};
		1575
		1576	struct skl_wm_level {
		1577	bool plane_en[I915_MAX_PLANES];
		1578	uint16_t plane_res_b[I915_MAX_PLANES];
		1579	uint8_t plane_res_l[I915_MAX_PLANES];
		1580	};
		1581
4104	Serge	1582	/*
5060	serge	1583	* This struct helps tracking the state needed for runtime PM, which puts the
		1584	* device in PCI D3 state. Notice that when this happens, nothing on the
		1585	* graphics device works, even register access, so we don't get interrupts nor
		1586	* anything else.
4104	Serge	1587	*
5060	serge	1588	* Every piece of our code that needs to actually touch the hardware needs to
		1589	* either call intel_runtime_pm_get or call intel_display_power_get with the
		1590	* appropriate power domain.
4104	Serge	1591	*
5060	serge	1592	* Our driver uses the autosuspend delay feature, which means we'll only really
		1593	* suspend if we stay with zero refcount for a certain amount of time. The
5354	serge	1594	* default value is currently very conservative (see intel_runtime_pm_enable), but
5060	serge	1595	* it can be changed with the standard runtime PM files from sysfs.
4104	Serge	1596	*
		1597	* The irqs_disabled variable becomes true exactly after we disable the IRQs and
		1598	* goes back to false exactly before we reenable the IRQs. We use this variable
		1599	* to check if someone is trying to enable/disable IRQs while they're supposed
		1600	* to be disabled. This shouldn't happen and we'll print some error messages in
5060	serge	1601	* case it happens.
4104	Serge	1602	*
5060	serge	1603	* For more, read the Documentation/power/runtime_pm.txt.
4104	Serge	1604	*/
4560	Serge	1605	struct i915_runtime_pm {
6937	serge	1606	atomic_t wakeref_count;
		1607	atomic_t atomic_seq;
4560	Serge	1608	bool suspended;
5354	serge	1609	bool irqs_enabled;
4560	Serge	1610	};
		1611
		1612	enum intel_pipe_crc_source {
		1613	INTEL_PIPE_CRC_SOURCE_NONE,
		1614	INTEL_PIPE_CRC_SOURCE_PLANE1,
		1615	INTEL_PIPE_CRC_SOURCE_PLANE2,
		1616	INTEL_PIPE_CRC_SOURCE_PF,
		1617	INTEL_PIPE_CRC_SOURCE_PIPE,
		1618	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
		1619	INTEL_PIPE_CRC_SOURCE_TV,
		1620	INTEL_PIPE_CRC_SOURCE_DP_B,
		1621	INTEL_PIPE_CRC_SOURCE_DP_C,
		1622	INTEL_PIPE_CRC_SOURCE_DP_D,
		1623	INTEL_PIPE_CRC_SOURCE_AUTO,
		1624	INTEL_PIPE_CRC_SOURCE_MAX,
		1625	};
		1626
		1627	struct intel_pipe_crc_entry {
		1628	uint32_t frame;
		1629	uint32_t crc[5];
		1630	};
		1631
		1632	#define INTEL_PIPE_CRC_ENTRIES_NR 128
		1633	struct intel_pipe_crc {
		1634	spinlock_t lock;
		1635	bool opened; /* exclusive access to the result file */
		1636	struct intel_pipe_crc_entry *entries;
		1637	enum intel_pipe_crc_source source;
		1638	int head, tail;
		1639	wait_queue_head_t wq;
		1640	};
		1641
5060	serge	1642	struct i915_frontbuffer_tracking {
		1643	struct mutex lock;
		1644
		1645	/*
		1646	* Tracking bits for delayed frontbuffer flushing du to gpu activity or
		1647	* scheduled flips.
		1648	*/
		1649	unsigned busy_bits;
		1650	unsigned flip_bits;
		1651	};
		1652
5354	serge	1653	struct i915_wa_reg {
6937	serge	1654	i915_reg_t addr;
5354	serge	1655	u32 value;
		1656	/* bitmask representing WA bits */
		1657	u32 mask;
		1658	};
		1659
		1660	#define I915_MAX_WA_REGS 16
		1661
		1662	struct i915_workarounds {
		1663	struct i915_wa_reg reg[I915_MAX_WA_REGS];
		1664	u32 count;
		1665	};
		1666
6084	serge	1667	struct i915_virtual_gpu {
		1668	bool active;
		1669	};
		1670
		1671	struct i915_execbuffer_params {
		1672	struct drm_device *dev;
		1673	struct drm_file *file;
		1674	uint32_t dispatch_flags;
		1675	uint32_t args_batch_start_offset;
		1676	uint64_t batch_obj_vm_offset;
		1677	struct intel_engine_cs *ring;
		1678	struct drm_i915_gem_object *batch_obj;
		1679	struct intel_context *ctx;
		1680	struct drm_i915_gem_request *request;
		1681	};
		1682
6937	serge	1683	/* used in computing the new watermarks state */
		1684	struct intel_wm_config {
		1685	unsigned int num_pipes_active;
		1686	bool sprites_enabled;
		1687	bool sprites_scaled;
		1688	};
		1689
5060	serge	1690	struct drm_i915_private {
3243	Serge	1691	struct drm_device *dev;
6084	serge	1692	struct kmem_cache *objects;
		1693	struct kmem_cache *vmas;
		1694	struct kmem_cache *requests;
3243	Serge	1695
5060	serge	1696	const struct intel_device_info info;
3243	Serge	1697
		1698	int relative_constants_mode;
		1699
		1700	void __iomem *regs;
		1701
4104	Serge	1702	struct intel_uncore uncore;
3243	Serge	1703
6084	serge	1704	struct i915_virtual_gpu vgpu;
3243	Serge	1705
6084	serge	1706	struct intel_guc guc;
3480	Serge	1707
6084	serge	1708	struct intel_csr csr;
		1709
		1710	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
		1711
3243	Serge	1712	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
		1713	* controller on different i2c buses. */
		1714	struct mutex gmbus_mutex;
		1715
		1716	/**
		1717	* Base address of the gmbus and gpio block.
		1718	*/
		1719	uint32_t gpio_mmio_base;
		1720
5060	serge	1721	/* MMIO base address for MIPI regs */
		1722	uint32_t mipi_mmio_base;
		1723
6937	serge	1724	uint32_t psr_mmio_base;
		1725
3480	Serge	1726	wait_queue_head_t gmbus_wait_queue;
		1727
3243	Serge	1728	struct pci_dev *bridge_dev;
5060	serge	1729	struct intel_engine_cs ring[I915_NUM_RINGS];
		1730	struct drm_i915_gem_object *semaphore_obj;
3480	Serge	1731	uint32_t last_seqno, next_seqno;
3243	Serge	1732
5354	serge	1733	struct drm_dma_handle *status_page_dmah;
3243	Serge	1734	struct resource mch_res;
		1735
		1736	/* protects the irq masks */
		1737	spinlock_t irq_lock;
		1738
5060	serge	1739	/* protects the mmio flip data */
		1740	spinlock_t mmio_flip_lock;
		1741
		1742	bool display_irqs_enabled;
		1743
3480	Serge	1744
6084	serge	1745	/* Sideband mailbox protection */
		1746	struct mutex sb_lock;
3243	Serge	1747
		1748	/** Cached value of IMR to avoid reads in updating the bitfield */
4560	Serge	1749	union {
6084	serge	1750	u32 irq_mask;
4560	Serge	1751	u32 de_irq_mask[I915_MAX_PIPES];
		1752	};
3243	Serge	1753	u32 gt_irq_mask;
4104	Serge	1754	u32 pm_irq_mask;
5060	serge	1755	u32 pm_rps_events;
		1756	u32 pipestat_irq_mask[I915_MAX_PIPES];
3243	Serge	1757
6084	serge	1758	struct i915_hotplug hotplug;
4104	Serge	1759	struct i915_fbc fbc;
5060	serge	1760	struct i915_drrs drrs;
3243	Serge	1761	struct intel_opregion opregion;
4104	Serge	1762	struct intel_vbt_data vbt;
3243	Serge	1763
5354	serge	1764	bool preserve_bios_swizzle;
		1765
3243	Serge	1766	/* overlay */
		1767	struct intel_overlay *overlay;
		1768
4560	Serge	1769	/* backlight registers and fields in struct intel_panel */
5354	serge	1770	struct mutex backlight_lock;
3746	Serge	1771
3243	Serge	1772	/* LVDS info */
		1773	bool no_aux_handshake;
		1774
5354	serge	1775	/* protects panel power sequencer state */
		1776	struct mutex pps_mutex;
		1777
3243	Serge	1778	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
		1779	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
		1780
		1781	unsigned int fsb_freq, mem_freq, is_ddr3;
6084	serge	1782	unsigned int skl_boot_cdclk;
		1783	unsigned int cdclk_freq, max_cdclk_freq;
		1784	unsigned int max_dotclk_freq;
5354	serge	1785	unsigned int hpll_freq;
6084	serge	1786	unsigned int czclk_freq;
3243	Serge	1787
4104	Serge	1788	/**
		1789	* wq - Driver workqueue for GEM.
		1790	*
		1791	* NOTE: Work items scheduled here are not allowed to grab any modeset
		1792	* locks, for otherwise the flushing done in the pageflip code will
		1793	* result in deadlocks.
		1794	*/
3243	Serge	1795	struct workqueue_struct *wq;
		1796
		1797	/* Display functions */
		1798	struct drm_i915_display_funcs display;
		1799
		1800	/* PCH chipset type */
		1801	enum intel_pch pch_type;
		1802	unsigned short pch_id;
		1803
		1804	unsigned long quirks;
		1805
3480	Serge	1806	enum modeset_restore modeset_restore;
		1807	struct mutex modeset_restore_lock;
3243	Serge	1808
4104	Serge	1809	struct list_head vm_list; /* Global list of all address spaces */
5060	serge	1810	struct i915_gtt gtt; /* VM representing the global address space */
2325	Serge	1811
3480	Serge	1812	struct i915_gem_mm mm;
5128	serge	1813	DECLARE_HASHTABLE(mm_structs, 7);
		1814	struct mutex mm_lock;
2325	Serge	1815
3031	serge	1816	/* Kernel Modesetting */
		1817
6084	serge	1818	struct sdvo_device_mapping sdvo_mappings[2];
2325	Serge	1819
5060	serge	1820	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
		1821	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2352	Serge	1822	wait_queue_head_t pending_flip_queue;
2325	Serge	1823
4560	Serge	1824	#ifdef CONFIG_DEBUG_FS
		1825	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
		1826	#endif
		1827
4104	Serge	1828	int num_shared_dpll;
		1829	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
4560	Serge	1830	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
3031	serge	1831
5354	serge	1832	struct i915_workarounds workarounds;
		1833
2325	Serge	1834	/* Reclocking support */
		1835	bool render_reclock_avail;
5060	serge	1836
		1837	struct i915_frontbuffer_tracking fb_tracking;
		1838
2325	Serge	1839	u16 orig_clock;
		1840
		1841	bool mchbar_need_disable;
		1842
3243	Serge	1843	struct intel_l3_parity l3_parity;
		1844
4104	Serge	1845	/* Cannot be determined by PCIID. You must always read a register. */
		1846	size_t ellc_size;
		1847
3031	serge	1848	/* gen6+ rps state */
3243	Serge	1849	struct intel_gen6_power_mgmt rps;
2325	Serge	1850
3031	serge	1851	/* ilk-only ips/rps state. Everything in here is protected by the global
		1852	* mchdev_lock in intel_pm.c */
3243	Serge	1853	struct intel_ilk_power_mgmt ips;
2325	Serge	1854
4560	Serge	1855	struct i915_power_domains power_domains;
2325	Serge	1856
4560	Serge	1857	struct i915_psr psr;
2325	Serge	1858
3480	Serge	1859	struct i915_gpu_error gpu_error;
2325	Serge	1860
4104	Serge	1861	struct drm_i915_gem_object *vlv_pctx;
		1862
6084	serge	1863	#ifdef CONFIG_DRM_FBDEV_EMULATION
2325	Serge	1864	/* list of fbdev register on this device */
6084	serge	1865	struct intel_fbdev *fbdev;
5354	serge	1866	struct work_struct fbdev_suspend_work;
4560	Serge	1867	#endif
2325	Serge	1868
3031	serge	1869	struct drm_property *broadcast_rgb_property;
		1870	struct drm_property *force_audio_property;
		1871
6084	serge	1872	/* hda/i915 audio component */
		1873	struct i915_audio_component *audio_component;
		1874	bool audio_component_registered;
		1875	/**
		1876	* av_mutex - mutex for audio/video sync
		1877	*
		1878	*/
		1879	struct mutex av_mutex;
		1880
3031	serge	1881	uint32_t hw_context_size;
4560	Serge	1882	struct list_head context_list;
3243	Serge	1883
3480	Serge	1884	u32 fdi_rx_config;
3243	Serge	1885
6084	serge	1886	u32 chv_phy_control;
		1887
5060	serge	1888	u32 suspend_count;
6937	serge	1889	bool suspended_to_idle;
3243	Serge	1890	struct i915_suspend_saved_registers regfile;
5060	serge	1891	struct vlv_s0ix_state vlv_s0ix_state;
3243	Serge	1892
4104	Serge	1893	struct {
		1894	/*
		1895	* Raw watermark latency values:
		1896	* in 0.1us units for WM0,
		1897	* in 0.5us units for WM1+.
		1898	*/
		1899	/* primary */
		1900	uint16_t pri_latency[5];
		1901	/* sprite */
		1902	uint16_t spr_latency[5];
		1903	/* cursor */
		1904	uint16_t cur_latency[5];
5354	serge	1905	/*
		1906	* Raw watermark memory latency values
		1907	* for SKL for all 8 levels
		1908	* in 1us units.
		1909	*/
		1910	uint16_t skl_latency[8];
4560	Serge	1911
6937	serge	1912	/* Committed wm config */
		1913	struct intel_wm_config config;
		1914
5354	serge	1915	/*
		1916	* The skl_wm_values structure is a bit too big for stack
		1917	* allocation, so we keep the staging struct where we store
		1918	* intermediate results here instead.
		1919	*/
		1920	struct skl_wm_values skl_results;
		1921
4560	Serge	1922	/* current hardware state */
5354	serge	1923	union {
6084	serge	1924	struct ilk_wm_values hw;
5354	serge	1925	struct skl_wm_values skl_hw;
6084	serge	1926	struct vlv_wm_values vlv;
5354	serge	1927	};
6084	serge	1928
		1929	uint8_t max_level;
4104	Serge	1930	} wm;
		1931
4560	Serge	1932	struct i915_runtime_pm pm;
		1933
5354	serge	1934	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
		1935	struct {
6084	serge	1936	int (execbuf_submit)(struct i915_execbuffer_params params,
		1937	struct drm_i915_gem_execbuffer2 *args,
		1938	struct list_head *vmas);
5354	serge	1939	int (init_rings)(struct drm_device dev);
		1940	void (cleanup_ring)(struct intel_engine_cs ring);
		1941	void (stop_ring)(struct intel_engine_cs ring);
		1942	} gt;
		1943
6084	serge	1944	bool edp_low_vswing;
		1945
		1946	/* perform PHY state sanity checks? */
		1947	bool chv_phy_assert[2];
		1948
6937	serge	1949	struct intel_encoder *dig_port_map[I915_MAX_PORTS];
		1950
5060	serge	1951	/*
		1952	* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
		1953	* will be rejected. Instead look for a better place.
		1954	*/
		1955	};
		1956
4104	Serge	1957	static inline struct drm_i915_private to_i915(const struct drm_device dev)
		1958	{
		1959	return dev->dev_private;
		1960	}
		1961
6084	serge	1962	static inline struct drm_i915_private dev_to_i915(struct device dev)
		1963	{
		1964	return to_i915(dev_get_drvdata(dev));
		1965	}
		1966
		1967	static inline struct drm_i915_private guc_to_i915(struct intel_guc guc)
		1968	{
		1969	return container_of(guc, struct drm_i915_private, guc);
		1970	}
		1971
3031	serge	1972	/* Iterate over initialised rings */
		1973	#define for_each_ring(ring__, dev_priv__, i__) \
		1974	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
6937	serge	1975	for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
3031	serge	1976
		1977	enum hdmi_force_audio {
		1978	HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
		1979	HDMI_AUDIO_OFF, /* force turn off HDMI audio */
		1980	HDMI_AUDIO_AUTO, /* trust EDID */
		1981	HDMI_AUDIO_ON, /* force turn on HDMI audio */
		1982	};
		1983
4104	Serge	1984	#define I915_GTT_OFFSET_NONE ((u32)-1)
2325	Serge	1985
3031	serge	1986	struct drm_i915_gem_object_ops {
6937	serge	1987	unsigned int flags;
		1988	#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
		1989
3031	serge	1990	/* Interface between the GEM object and its backing storage.
		1991	* get_pages() is called once prior to the use of the associated set
		1992	* of pages before to binding them into the GTT, and put_pages() is
		1993	* called after we no longer need them. As we expect there to be
		1994	* associated cost with migrating pages between the backing storage
		1995	* and making them available for the GPU (e.g. clflush), we may hold
		1996	* onto the pages after they are no longer referenced by the GPU
		1997	* in case they may be used again shortly (for example migrating the
		1998	* pages to a different memory domain within the GTT). put_pages()
		1999	* will therefore most likely be called when the object itself is
		2000	* being released or under memory pressure (where we attempt to
		2001	* reap pages for the shrinker).
		2002	*/
		2003	int (get_pages)(struct drm_i915_gem_object );
		2004	void (put_pages)(struct drm_i915_gem_object );
6937	serge	2005
5060	serge	2006	int (dmabuf_export)(struct drm_i915_gem_object );
		2007	void (release)(struct drm_i915_gem_object );
3031	serge	2008	};
		2009
5060	serge	2010	/*
		2011	* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
6084	serge	2012	* considered to be the frontbuffer for the given plane interface-wise. This
5060	serge	2013	* doesn't mean that the hw necessarily already scans it out, but that any
		2014	* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
		2015	*
		2016	* We have one bit per pipe and per scanout plane type.
		2017	*/
6084	serge	2018	#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
		2019	#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
5060	serge	2020	#define INTEL_FRONTBUFFER_BITS \
		2021	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
		2022	#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
		2023	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
		2024	#define INTEL_FRONTBUFFER_CURSOR(pipe) \
6084	serge	2025	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
		2026	#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
		2027	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2028	#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
6084	serge	2029	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
5060	serge	2030	#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
6084	serge	2031	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
5060	serge	2032
2327	Serge	2033	struct drm_i915_gem_object {
6084	serge	2034	struct drm_gem_object base;
2325	Serge	2035
3031	serge	2036	const struct drm_i915_gem_object_ops *ops;
		2037
4104	Serge	2038	/** List of VMAs backed by this object */
		2039	struct list_head vma_list;
		2040
3480	Serge	2041	/** Stolen memory for this object, instead of being backed by shmem. */
		2042	struct drm_mm_node *stolen;
4104	Serge	2043	struct list_head global_list;
2327	Serge	2044
6084	serge	2045	struct list_head ring_list[I915_NUM_RINGS];
4104	Serge	2046	/** Used in execbuf to temporarily hold a ref */
		2047	struct list_head obj_exec_link;
2327	Serge	2048
6084	serge	2049	struct list_head batch_pool_link;
		2050
		2051	/**
3031	serge	2052	* This is set if the object is on the active lists (has pending
		2053	* rendering and so a non-zero seqno), and is not set if it i s on
		2054	* inactive (ready to be unbound) list.
6084	serge	2055	*/
		2056	unsigned int active:I915_NUM_RINGS;
2327	Serge	2057
6084	serge	2058	/**
		2059	* This is set if the object has been written to since last bound
		2060	* to the GTT
		2061	*/
2342	Serge	2062	unsigned int dirty:1;
2327	Serge	2063
6084	serge	2064	/**
		2065	* Fence register bits (if any) for this object. Will be set
		2066	* as needed when mapped into the GTT.
		2067	* Protected by dev->struct_mutex.
		2068	*/
2342	Serge	2069	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2327	Serge	2070
6084	serge	2071	/**
		2072	* Advice: are the backing pages purgeable?
		2073	*/
2342	Serge	2074	unsigned int madv:2;
2327	Serge	2075
6084	serge	2076	/**
		2077	* Current tiling mode for the object.
		2078	*/
2342	Serge	2079	unsigned int tiling_mode:2;
3031	serge	2080	/**
		2081	* Whether the tiling parameters for the currently associated fence
		2082	* register have changed. Note that for the purposes of tracking
		2083	* tiling changes we also treat the unfenced register, the register
		2084	* slot that the object occupies whilst it executes a fenced
		2085	* command (such as BLT on gen2/3), as a "fence".
		2086	*/
		2087	unsigned int fence_dirty:1;
2327	Serge	2088
6084	serge	2089	/**
		2090	* Is the object at the current location in the gtt mappable and
		2091	* fenceable? Used to avoid costly recalculations.
		2092	*/
2342	Serge	2093	unsigned int map_and_fenceable:1;
2327	Serge	2094
6084	serge	2095	/**
		2096	* Whether the current gtt mapping needs to be mappable (and isn't just
		2097	* mappable by accident). Track pin and fault separate for a more
		2098	* accurate mappable working set.
		2099	*/
2342	Serge	2100	unsigned int fault_mappable:1;
2327	Serge	2101
6084	serge	2102	/*
5060	serge	2103	* Is the object to be mapped as read-only to the GPU
		2104	* Only honoured if hardware has relevant pte bit
		2105	*/
		2106	unsigned long gt_ro:1;
4104	Serge	2107	unsigned int cache_level:3;
6084	serge	2108	unsigned int cache_dirty:1;
2327	Serge	2109
5060	serge	2110	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
		2111
6084	serge	2112	unsigned int pin_display;
		2113
3243	Serge	2114	struct sg_table *pages;
3031	serge	2115	int pages_pin_count;
6084	serge	2116	struct get_page {
		2117	struct scatterlist *sg;
		2118	int last;
		2119	} get_page;
2327	Serge	2120
3031	serge	2121	/* prime dma-buf support */
		2122	void *dma_buf_vmapping;
		2123	int vmapping_count;
		2124
6084	serge	2125	/** Breadcrumb of last rendering to the buffer.
		2126	* There can only be one writer, but we allow for multiple readers.
		2127	* If there is a writer that necessarily implies that all other
		2128	* read requests are complete - but we may only be lazily clearing
		2129	* the read requests. A read request is naturally the most recent
		2130	* request on a ring, so we may have two different write and read
		2131	* requests on one ring where the write request is older than the
		2132	* read request. This allows for the CPU to read from an active
		2133	* buffer by only waiting for the write to complete.
		2134	* */
		2135	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
		2136	struct drm_i915_gem_request *last_write_req;
		2137	/** Breadcrumb of last fenced GPU access to the buffer. */
		2138	struct drm_i915_gem_request *last_fenced_req;
3031	serge	2139
6084	serge	2140	/** Current tiling stride for the object, if it's tiled. */
		2141	uint32_t stride;
2327	Serge	2142
4560	Serge	2143	/** References from framebuffers, locks out tiling changes. */
		2144	unsigned long framebuffer_references;
		2145
6084	serge	2146	/** Record of address bit 17 of each page at last unbind. */
		2147	unsigned long *bit_17;
2327	Serge	2148
6937	serge	2149	union {
		2150	/** for phy allocated objects */
		2151	struct drm_dma_handle *phys_handle;
		2152
5060	serge	2153	struct i915_gem_userptr {
		2154	uintptr_t ptr;
		2155	unsigned read_only :1;
		2156	unsigned workers :4;
		2157	#define I915_GEM_USERPTR_MAX_WORKERS 15
		2158
5128	serge	2159	struct i915_mm_struct *mm;
		2160	struct i915_mmu_object *mmu_object;
5060	serge	2161	struct work_struct *work;
		2162	} userptr;
6937	serge	2163	};
2327	Serge	2164	};
2325	Serge	2165	#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
		2166
5060	serge	2167	void i915_gem_track_fb(struct drm_i915_gem_object *old,
		2168	struct drm_i915_gem_object *new,
		2169	unsigned frontbuffer_bits);
		2170
2325	Serge	2171	/**
		2172	* Request queue structure.
		2173	*
		2174	* The request queue allows us to note sequence numbers that have been emitted
		2175	* and may be associated with active buffers to be retired.
		2176	*
6084	serge	2177	* By keeping this list, we can avoid having to do questionable sequence
		2178	* number comparisons on buffer last_read\|write_seqno. It also allows an
		2179	* emission time to be associated with the request for tracking how far ahead
		2180	* of the GPU the submission is.
		2181	*
		2182	* The requests are reference counted, so upon creation they should have an
		2183	* initial reference taken using kref_init
2325	Serge	2184	*/
		2185	struct drm_i915_gem_request {
6084	serge	2186	struct kref ref;
		2187
2325	Serge	2188	/** On Which ring this request was generated */
6084	serge	2189	struct drm_i915_private *i915;
5060	serge	2190	struct intel_engine_cs *ring;
2325	Serge	2191
6084	serge	2192	/** GEM sequence number associated with the previous request,
		2193	* when the HWS breadcrumb is equal to this the GPU is processing
		2194	* this request.
		2195	*/
		2196	u32 previous_seqno;
2325	Serge	2197
6084	serge	2198	/** GEM sequence number associated with this request,
		2199	* when the HWS breadcrumb is equal or greater than this the GPU
		2200	* has finished processing this request.
		2201	*/
		2202	u32 seqno;
		2203
4104	Serge	2204	/** Position in the ringbuffer of the start of the request */
		2205	u32 head;
		2206
6084	serge	2207	/**
		2208	* Position in the ringbuffer of the start of the postfix.
		2209	* This is required to calculate the maximum available ringbuffer
		2210	* space without overwriting the postfix.
		2211	*/
		2212	u32 postfix;
		2213
		2214	/** Position in the ringbuffer of the end of the whole request */
3031	serge	2215	u32 tail;
		2216
6084	serge	2217	/**
		2218	* Context and ring buffer related to this request
		2219	* Contexts are refcounted, so when this request is associated with a
		2220	* context, we must increment the context's refcount, to guarantee that
		2221	* it persists while any request is linked to it. Requests themselves
		2222	* are also refcounted, so the request will only be freed when the last
		2223	* reference to it is dismissed, and the code in
		2224	* i915_gem_request_free() will then decrement the refcount on the
		2225	* context.
		2226	*/
5060	serge	2227	struct intel_context *ctx;
6084	serge	2228	struct intel_ringbuffer *ringbuf;
4104	Serge	2229
6084	serge	2230	/** Batch buffer related to this request if any (used for
		2231	error state dump only) */
4104	Serge	2232	struct drm_i915_gem_object *batch_obj;
		2233
2325	Serge	2234	/** Time at which this request was emitted, in jiffies. */
		2235	unsigned long emitted_jiffies;
		2236
		2237	/** global list entry for this request */
		2238	struct list_head list;
		2239
		2240	struct drm_i915_file_private *file_priv;
		2241	/** file_priv list entry for this request */
		2242	struct list_head client_list;
		2243
6084	serge	2244	/** process identifier submitting this request */
		2245	struct pid *pid;
4560	Serge	2246
6084	serge	2247	/**
		2248	* The ELSP only accepts two elements at a time, so we queue
		2249	* context/tail pairs on a given queue (ring->execlist_queue) until the
		2250	* hardware is available. The queue serves a double purpose: we also use
		2251	* it to keep track of the up to 2 contexts currently in the hardware
		2252	* (usually one in execution and the other queued up by the GPU): We
		2253	* only remove elements from the head of the queue when the hardware
		2254	* informs us that an element has been completed.
		2255	*
		2256	* All accesses to the queue are mediated by a spinlock
		2257	* (ring->execlist_lock).
		2258	*/
4104	Serge	2259
6084	serge	2260	/** Execlist link in the submission queue.*/
		2261	struct list_head execlist_link;
		2262
		2263	/** Execlists no. of times this request has been sent to the ELSP */
		2264	int elsp_submitted;
		2265
2325	Serge	2266	};
		2267
6084	serge	2268	int i915_gem_request_alloc(struct intel_engine_cs *ring,
		2269	struct intel_context *ctx,
		2270	struct drm_i915_gem_request **req_out);
		2271	void i915_gem_request_cancel(struct drm_i915_gem_request *req);
		2272	void i915_gem_request_free(struct kref *req_ref);
		2273	int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
		2274	struct drm_file *file);
		2275
		2276	static inline uint32_t
		2277	i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
		2278	{
		2279	return req ? req->seqno : 0;
		2280	}
		2281
		2282	static inline struct intel_engine_cs *
		2283	i915_gem_request_get_ring(struct drm_i915_gem_request *req)
		2284	{
		2285	return req ? req->ring : NULL;
		2286	}
		2287
		2288	static inline struct drm_i915_gem_request *
		2289	i915_gem_request_reference(struct drm_i915_gem_request *req)
		2290	{
		2291	if (req)
		2292	kref_get(&req->ref);
		2293	return req;
		2294	}
		2295
		2296	static inline void
		2297	i915_gem_request_unreference(struct drm_i915_gem_request *req)
		2298	{
		2299	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
		2300	kref_put(&req->ref, i915_gem_request_free);
		2301	}
		2302
		2303	static inline void
		2304	i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
		2305	{
		2306	struct drm_device *dev;
		2307
		2308	if (!req)
		2309	return;
		2310
		2311	dev = req->ring->dev;
		2312	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
		2313	mutex_unlock(&dev->struct_mutex);
		2314	}
		2315
		2316	static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
		2317	struct drm_i915_gem_request *src)
		2318	{
		2319	if (src)
		2320	i915_gem_request_reference(src);
		2321
		2322	if (*pdst)
		2323	i915_gem_request_unreference(*pdst);
		2324
		2325	*pdst = src;
		2326	}
		2327
5060	serge	2328	/*
6084	serge	2329	* XXX: i915_gem_request_completed should be here but currently needs the
		2330	* definition of i915_seqno_passed() which is below. It will be moved in
		2331	* a later patch when the call to i915_seqno_passed() is obsoleted...
		2332	*/
		2333
		2334	/*
5060	serge	2335	* A command that requires special handling by the command parser.
		2336	*/
		2337	struct drm_i915_cmd_descriptor {
		2338	/*
		2339	* Flags describing how the command parser processes the command.
		2340	*
		2341	* CMD_DESC_FIXED: The command has a fixed length if this is set,
		2342	* a length mask if not set
		2343	* CMD_DESC_SKIP: The command is allowed but does not follow the
		2344	* standard length encoding for the opcode range in
		2345	* which it falls
		2346	* CMD_DESC_REJECT: The command is never allowed
		2347	* CMD_DESC_REGISTER: The command should be checked against the
		2348	* register whitelist for the appropriate ring
		2349	* CMD_DESC_MASTER: The command is allowed if the submitting process
		2350	* is the DRM master
		2351	*/
		2352	u32 flags;
		2353	#define CMD_DESC_FIXED (1<<0)
		2354	#define CMD_DESC_SKIP (1<<1)
		2355	#define CMD_DESC_REJECT (1<<2)
		2356	#define CMD_DESC_REGISTER (1<<3)
		2357	#define CMD_DESC_BITMASK (1<<4)
		2358	#define CMD_DESC_MASTER (1<<5)
2325	Serge	2359
5060	serge	2360	/*
		2361	* The command's unique identification bits and the bitmask to get them.
		2362	* This isn't strictly the opcode field as defined in the spec and may
		2363	* also include type, subtype, and/or subop fields.
		2364	*/
		2365	struct {
		2366	u32 value;
		2367	u32 mask;
		2368	} cmd;
		2369
		2370	/*
		2371	* The command's length. The command is either fixed length (i.e. does
		2372	* not include a length field) or has a length field mask. The flag
		2373	* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		2374	* a length mask. All command entries in a command table must include
		2375	* length information.
		2376	*/
		2377	union {
		2378	u32 fixed;
		2379	u32 mask;
		2380	} length;
		2381
		2382	/*
		2383	* Describes where to find a register address in the command to check
		2384	* against the ring's register whitelist. Only valid if flags has the
		2385	* CMD_DESC_REGISTER bit set.
6084	serge	2386	*
		2387	* A non-zero step value implies that the command may access multiple
		2388	* registers in sequence (e.g. LRI), in that case step gives the
		2389	* distance in dwords between individual offset fields.
5060	serge	2390	*/
		2391	struct {
		2392	u32 offset;
		2393	u32 mask;
6084	serge	2394	u32 step;
5060	serge	2395	} reg;
		2396
		2397	#define MAX_CMD_DESC_BITMASKS 3
		2398	/*
		2399	* Describes command checks where a particular dword is masked and
		2400	* compared against an expected value. If the command does not match
		2401	* the expected value, the parser rejects it. Only valid if flags has
		2402	* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		2403	* are valid.
		2404	*
		2405	* If the check specifies a non-zero condition_mask then the parser
		2406	* only performs the check when the bits specified by condition_mask
		2407	* are non-zero.
		2408	*/
		2409	struct {
		2410	u32 offset;
		2411	u32 mask;
		2412	u32 expected;
		2413	u32 condition_offset;
		2414	u32 condition_mask;
		2415	} bits[MAX_CMD_DESC_BITMASKS];
		2416	};
		2417
		2418	/*
		2419	* A table of commands requiring special handling by the command parser.
		2420	*
		2421	* Each ring has an array of tables. Each table consists of an array of command
		2422	* descriptors, which must be sorted with command opcodes in ascending order.
		2423	*/
		2424	struct drm_i915_cmd_table {
		2425	const struct drm_i915_cmd_descriptor *table;
		2426	int count;
		2427	};
		2428
5354	serge	2429	/* Note that the (struct drm_i915_private ) cast is just to shut up gcc. /
		2430	#define __I915__(p) ({ \
		2431	struct drm_i915_private *__p; \
		2432	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		2433	__p = (struct drm_i915_private *)p; \
		2434	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		2435	__p = to_i915((struct drm_device *)p); \
		2436	else \
		2437	BUILD_BUG(); \
		2438	__p; \
		2439	})
		2440	#define INTEL_INFO(p) (&__I915__(p)->info)
		2441	#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
6084	serge	2442	#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
5060	serge	2443
6937	serge	2444	#define REVID_FOREVER 0xff
		2445	/*
		2446	* Return true if revision is in range [since,until] inclusive.
		2447	*
		2448	* Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
		2449	*/
		2450	#define IS_REVID(p, since, until) \
		2451	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
		2452
5354	serge	2453	#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
		2454	#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2325	Serge	2455	#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
5354	serge	2456	#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2325	Serge	2457	#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
5354	serge	2458	#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
		2459	#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2325	Serge	2460	#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
		2461	#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
		2462	#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
5354	serge	2463	#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2325	Serge	2464	#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
5354	serge	2465	#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
		2466	#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2325	Serge	2467	#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
		2468	#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
5354	serge	2469	#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2325	Serge	2470	#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
5354	serge	2471	#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 \|\| \
		2472	INTEL_DEVID(dev) == 0x0152 \|\| \
		2473	INTEL_DEVID(dev) == 0x015a)
3031	serge	2474	#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6937	serge	2475	#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
3031	serge	2476	#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
6937	serge	2477	#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
5354	serge	2478	#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
6937	serge	2479	#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
		2480	#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2325	Serge	2481	#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
4104	Serge	2482	#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
5354	serge	2483	(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
4560	Serge	2484	#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
6084	serge	2485	((INTEL_DEVID(dev) & 0xf) == 0x6 \|\| \
		2486	(INTEL_DEVID(dev) & 0xf) == 0xb \|\| \
5354	serge	2487	(INTEL_DEVID(dev) & 0xf) == 0xe))
6084	serge	2488	/* ULX machines are also considered ULT. */
		2489	#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
		2490	(INTEL_DEVID(dev) & 0xf) == 0xe)
5354	serge	2491	#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
		2492	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
4560	Serge	2493	#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
5354	serge	2494	(INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
4560	Serge	2495	#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
5354	serge	2496	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5060	serge	2497	/* ULX machines are also considered ULT. */
5354	serge	2498	#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E \|\| \
		2499	INTEL_DEVID(dev) == 0x0A1E)
6084	serge	2500	#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 \|\| \
		2501	INTEL_DEVID(dev) == 0x1913 \|\| \
		2502	INTEL_DEVID(dev) == 0x1916 \|\| \
		2503	INTEL_DEVID(dev) == 0x1921 \|\| \
		2504	INTEL_DEVID(dev) == 0x1926)
		2505	#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E \|\| \
		2506	INTEL_DEVID(dev) == 0x1915 \|\| \
		2507	INTEL_DEVID(dev) == 0x191E)
6937	serge	2508	#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 \|\| \
		2509	INTEL_DEVID(dev) == 0x5913 \|\| \
		2510	INTEL_DEVID(dev) == 0x5916 \|\| \
		2511	INTEL_DEVID(dev) == 0x5921 \|\| \
		2512	INTEL_DEVID(dev) == 0x5926)
		2513	#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E \|\| \
		2514	INTEL_DEVID(dev) == 0x5915 \|\| \
		2515	INTEL_DEVID(dev) == 0x591E)
6084	serge	2516	#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
		2517	(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
		2518	#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
		2519	(INTEL_DEVID(dev) & 0x00F0) == 0x0030)
		2520
4560	Serge	2521	#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2325	Serge	2522
6937	serge	2523	#define SKL_REVID_A0 0x0
		2524	#define SKL_REVID_B0 0x1
		2525	#define SKL_REVID_C0 0x2
		2526	#define SKL_REVID_D0 0x3
		2527	#define SKL_REVID_E0 0x4
		2528	#define SKL_REVID_F0 0x5
6084	serge	2529
6937	serge	2530	#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
6084	serge	2531
6937	serge	2532	#define BXT_REVID_A0 0x0
		2533	#define BXT_REVID_A1 0x1
		2534	#define BXT_REVID_B0 0x3
		2535	#define BXT_REVID_C0 0x9
		2536
		2537	#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
		2538
2325	Serge	2539	/*
		2540	* The genX designation typically refers to the render engine, so render
		2541	* capability related checks should use IS_GEN, while display and other checks
		2542	* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
		2543	* chips, etc.).
		2544	*/
		2545	#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
		2546	#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
		2547	#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
		2548	#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
		2549	#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
		2550	#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
4560	Serge	2551	#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
5354	serge	2552	#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2325	Serge	2553
4560	Serge	2554	#define RENDER_RING (1<
		2555	#define BSD_RING (1<
		2556	#define BLT_RING (1<
		2557	#define VEBOX_RING (1<
5060	serge	2558	#define BSD2_RING (1<
6084	serge	2559	#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
5060	serge	2560	#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
6084	serge	2561	#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
		2562	#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
		2563	#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
5060	serge	2564	#define HAS_WT(dev) ((IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) && \
5354	serge	2565	__I915__(dev)->ellc_size)
2325	Serge	2566	#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
		2567
3031	serge	2568	#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
5354	serge	2569	#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
		2570	#define USES_PPGTT(dev) (i915.enable_ppgtt)
6084	serge	2571	#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
		2572	#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
3031	serge	2573
2325	Serge	2574	#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
		2575	#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
		2576
3243	Serge	2577	/* Early gen2 have a totally busted CS tlb and require pinned batches. */
		2578	#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) \|\| IS_845G(dev))
5060	serge	2579	/*
		2580	* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
		2581	* even when in MSI mode. This results in spurious interrupt warnings if the
		2582	* legacy irq no. is shared with another device. The kernel then disables that
		2583	* interrupt source and so prevents the other device from working properly.
		2584	*/
		2585	#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
		2586	#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
3243	Serge	2587
2325	Serge	2588	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
		2589	* rows, which changed the alignment requirements and fence programming.
		2590	*/
		2591	#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) \|\| \
		2592	IS_I915GM(dev)))
		2593	#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
		2594	#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
		2595
		2596	#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
		2597	#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
4560	Serge	2598	#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2325	Serge	2599
5354	serge	2600	#define HAS_IPS(dev) (IS_HSW_ULT(dev) \|\| IS_BROADWELL(dev))
2325	Serge	2601
6084	serge	2602	#define HAS_DP_MST(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2603	INTEL_INFO(dev)->gen >= 9)
		2604
4104	Serge	2605	#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
		2606	#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
6084	serge	2607	#define HAS_PSR(dev) (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| \
		2608	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev) \|\| \
6937	serge	2609	IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
5060	serge	2610	#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) \|\| IS_HASWELL(dev) \|\| \
6084	serge	2611	IS_BROADWELL(dev) \|\| IS_VALLEYVIEW(dev) \|\| \
6937	serge	2612	IS_CHERRYVIEW(dev) \|\| IS_SKYLAKE(dev) \|\| \
		2613	IS_KABYLAKE(dev))
5354	serge	2614	#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
		2615	#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 \|\| IS_IVYBRIDGE(dev))
3480	Serge	2616
6084	serge	2617	#define HAS_CSR(dev) (IS_GEN9(dev))
		2618
6937	serge	2619	#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
		2620	#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
6084	serge	2621
		2622	#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) \|\| \
		2623	INTEL_INFO(dev)->gen >= 8)
		2624
		2625	#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
6937	serge	2626	!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
		2627	!IS_BROXTON(dev))
6084	serge	2628
3243	Serge	2629	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
		2630	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
		2631	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
		2632	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
		2633	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
		2634	#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
5354	serge	2635	#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
		2636	#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
6084	serge	2637	#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
6320	serge	2638	#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3243	Serge	2639
5354	serge	2640	#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
		2641	#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
3031	serge	2642	#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
6084	serge	2643	#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6937	serge	2644	#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2325	Serge	2645	#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
		2646	#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
3746	Serge	2647	#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
3031	serge	2648	#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2325	Serge	2649
6937	serge	2650	#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 \|\| \
		2651	IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
5060	serge	2652
4560	Serge	2653	/* DPF == dynamic parity feature */
		2654	#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) \|\| IS_HASWELL(dev))
		2655	#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2325	Serge	2656
3031	serge	2657	#define GT_FREQUENCY_MULTIPLIER 50
6084	serge	2658	#define GEN9_FREQ_SCALER 3
3031	serge	2659
		2660	#include "i915_trace.h"
		2661
6084	serge	2662	extern const struct drm_ioctl_desc i915_ioctls[];
		2663	extern int i915_max_ioctl;
3031	serge	2664
6660	serge	2665	extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
6084	serge	2666	extern int i915_resume_switcheroo(struct drm_device *dev);
2325	Serge	2667
5060	serge	2668	/* i915_params.c */
		2669	struct i915_params {
		2670	int modeset;
		2671	int panel_ignore_lid;
		2672	int semaphores;
		2673	int lvds_channel_mode;
		2674	int panel_use_ssc;
		2675	int vbt_sdvo_panel_type;
		2676	int enable_rc6;
6937	serge	2677	int enable_dc;
5060	serge	2678	int enable_fbc;
		2679	int enable_ppgtt;
5354	serge	2680	int enable_execlists;
5060	serge	2681	int enable_psr;
		2682	unsigned int preliminary_hw_support;
		2683	int disable_power_well;
		2684	int enable_ips;
		2685	int invert_brightness;
		2686	int enable_cmd_parser;
		2687	/* leave bools at the end to not create holes */
		2688	bool enable_hangcheck;
		2689	bool fastboot;
		2690	bool prefault_disable;
6084	serge	2691	bool load_detect_test;
5060	serge	2692	bool reset;
		2693	bool disable_display;
		2694	bool disable_vtd_wa;
6084	serge	2695	bool enable_guc_submission;
		2696	int guc_log_level;
5060	serge	2697	int use_mmio_flip;
6084	serge	2698	int mmio_debug;
		2699	bool verbose_state_checks;
		2700	bool nuclear_pageflip;
		2701	int edp_vswing;
6103	serge	2702	/* Kolibri related */
		2703	char *log_file;
		2704	char *cmdline_mode;
5060	serge	2705	};
		2706	extern struct i915_params i915 __read_mostly;
		2707
2325	Serge	2708	/* i915_dma.c */
		2709	extern int i915_driver_load(struct drm_device *, unsigned long flags);
		2710	extern int i915_driver_unload(struct drm_device *);
5060	serge	2711	extern int i915_driver_open(struct drm_device dev, struct drm_file file);
2325	Serge	2712	extern void i915_driver_lastclose(struct drm_device * dev);
		2713	extern void i915_driver_preclose(struct drm_device *dev,
5060	serge	2714	struct drm_file *file);
2325	Serge	2715	extern void i915_driver_postclose(struct drm_device *dev,
5060	serge	2716	struct drm_file *file);
3031	serge	2717	#ifdef CONFIG_COMPAT
2325	Serge	2718	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
		2719	unsigned long arg);
3031	serge	2720	#endif
		2721	extern int intel_gpu_reset(struct drm_device *dev);
6084	serge	2722	extern bool intel_has_gpu_reset(struct drm_device *dev);
3031	serge	2723	extern int i915_reset(struct drm_device *dev);
2325	Serge	2724	extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
		2725	extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
		2726	extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
		2727	extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
5060	serge	2728	int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
6084	serge	2729
		2730	/* intel_hotplug.c */
		2731	void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
		2732	void intel_hpd_init(struct drm_i915_private *dev_priv);
		2733	void intel_hpd_init_work(struct drm_i915_private *dev_priv);
5060	serge	2734	void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
6084	serge	2735	bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2325	Serge	2736
		2737	/* i915_irq.c */
4104	Serge	2738	void i915_queue_hangcheck(struct drm_device *dev);
5060	serge	2739	__printf(3, 4)
		2740	void i915_handle_error(struct drm_device *dev, bool wedged,
		2741	const char *fmt, ...);
2325	Serge	2742
5354	serge	2743	extern void intel_irq_init(struct drm_i915_private *dev_priv);
		2744	int intel_irq_install(struct drm_i915_private *dev_priv);
		2745	void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2325	Serge	2746
4104	Serge	2747	extern void intel_uncore_sanitize(struct drm_device *dev);
5060	serge	2748	extern void intel_uncore_early_sanitize(struct drm_device *dev,
		2749	bool restore_forcewake);
4104	Serge	2750	extern void intel_uncore_init(struct drm_device *dev);
		2751	extern void intel_uncore_check_errors(struct drm_device *dev);
4560	Serge	2752	extern void intel_uncore_fini(struct drm_device *dev);
5060	serge	2753	extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
6084	serge	2754	const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
		2755	void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
		2756	enum forcewake_domains domains);
		2757	void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
		2758	enum forcewake_domains domains);
		2759	/* Like above but the caller must manage the uncore.lock itself.
		2760	* Must be used with I915_READ_FW and friends.
		2761	*/
		2762	void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
		2763	enum forcewake_domains domains);
		2764	void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
		2765	enum forcewake_domains domains);
		2766	void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
		2767	static inline bool intel_vgpu_active(struct drm_device *dev)
		2768	{
		2769	return to_i915(dev)->vgpu.active;
		2770	}
2325	Serge	2771
		2772	void
5060	serge	2773	i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2774	u32 status_mask);
2325	Serge	2775
		2776	void
5060	serge	2777	i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		2778	u32 status_mask);
2325	Serge	2779
5060	serge	2780	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
		2781	void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
6084	serge	2782	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
		2783	uint32_t mask,
		2784	uint32_t bits);
6937	serge	2785	void ilk_update_display_irq(struct drm_i915_private *dev_priv,
		2786	uint32_t interrupt_mask,
		2787	uint32_t enabled_irq_mask);
		2788	static inline void
		2789	ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
		2790	{
		2791	ilk_update_display_irq(dev_priv, bits, bits);
		2792	}
		2793	static inline void
		2794	ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
		2795	{
		2796	ilk_update_display_irq(dev_priv, bits, 0);
		2797	}
		2798	void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
		2799	enum pipe pipe,
		2800	uint32_t interrupt_mask,
		2801	uint32_t enabled_irq_mask);
		2802	static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
		2803	enum pipe pipe, uint32_t bits)
		2804	{
		2805	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
		2806	}
		2807	static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
		2808	enum pipe pipe, uint32_t bits)
		2809	{
		2810	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
		2811	}
5354	serge	2812	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
		2813	uint32_t interrupt_mask,
		2814	uint32_t enabled_irq_mask);
6937	serge	2815	static inline void
		2816	ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
		2817	{
		2818	ibx_display_interrupt_update(dev_priv, bits, bits);
		2819	}
		2820	static inline void
		2821	ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
		2822	{
		2823	ibx_display_interrupt_update(dev_priv, bits, 0);
		2824	}
5060	serge	2825
6937	serge	2826
2325	Serge	2827	/* i915_gem.c */
		2828	int i915_gem_create_ioctl(struct drm_device dev, void data,
		2829	struct drm_file *file_priv);
		2830	int i915_gem_pread_ioctl(struct drm_device dev, void data,
		2831	struct drm_file *file_priv);
		2832	int i915_gem_pwrite_ioctl(struct drm_device dev, void data,
		2833	struct drm_file *file_priv);
		2834	int i915_gem_mmap_ioctl(struct drm_device dev, void data,
		2835	struct drm_file *file_priv);
		2836	int i915_gem_mmap_gtt_ioctl(struct drm_device dev, void data,
		2837	struct drm_file *file_priv);
		2838	int i915_gem_set_domain_ioctl(struct drm_device dev, void data,
		2839	struct drm_file *file_priv);
		2840	int i915_gem_sw_finish_ioctl(struct drm_device dev, void data,
		2841	struct drm_file *file_priv);
5354	serge	2842	void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
6084	serge	2843	struct drm_i915_gem_request *req);
		2844	void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
		2845	int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
5354	serge	2846	struct drm_i915_gem_execbuffer2 *args,
6084	serge	2847	struct list_head *vmas);
2325	Serge	2848	int i915_gem_execbuffer(struct drm_device dev, void data,
		2849	struct drm_file *file_priv);
		2850	int i915_gem_execbuffer2(struct drm_device dev, void data,
		2851	struct drm_file *file_priv);
		2852	int i915_gem_busy_ioctl(struct drm_device dev, void data,
		2853	struct drm_file *file_priv);
3031	serge	2854	int i915_gem_get_caching_ioctl(struct drm_device dev, void data,
		2855	struct drm_file *file);
		2856	int i915_gem_set_caching_ioctl(struct drm_device dev, void data,
		2857	struct drm_file *file);
2325	Serge	2858	int i915_gem_throttle_ioctl(struct drm_device dev, void data,
		2859	struct drm_file *file_priv);
		2860	int i915_gem_madvise_ioctl(struct drm_device dev, void data,
		2861	struct drm_file *file_priv);
		2862	int i915_gem_set_tiling(struct drm_device dev, void data,
		2863	struct drm_file *file_priv);
		2864	int i915_gem_get_tiling(struct drm_device dev, void data,
		2865	struct drm_file *file_priv);
5060	serge	2866	int i915_gem_init_userptr(struct drm_device *dev);
		2867	int i915_gem_userptr_ioctl(struct drm_device dev, void data,
		2868	struct drm_file *file);
2325	Serge	2869	int i915_gem_get_aperture_ioctl(struct drm_device dev, void data,
		2870	struct drm_file *file_priv);
3031	serge	2871	int i915_gem_wait_ioctl(struct drm_device dev, void data,
		2872	struct drm_file *file_priv);
2325	Serge	2873	void i915_gem_load(struct drm_device *dev);
3480	Serge	2874	void i915_gem_object_alloc(struct drm_device dev);
		2875	void i915_gem_object_free(struct drm_i915_gem_object *obj);
3031	serge	2876	void i915_gem_object_init(struct drm_i915_gem_object *obj,
		2877	const struct drm_i915_gem_object_ops *ops);
2325	Serge	2878	struct drm_i915_gem_object i915_gem_alloc_object(struct drm_device dev,
		2879	size_t size);
6084	serge	2880	struct drm_i915_gem_object *i915_gem_object_create_from_data(
		2881	struct drm_device dev, const void data, size_t size);
2325	Serge	2882	void i915_gem_free_object(struct drm_gem_object *obj);
4104	Serge	2883	void i915_gem_vma_destroy(struct i915_vma *vma);
3480	Serge	2884
6084	serge	2885	/* Flags used by pin/bind&friends. */
		2886	#define PIN_MAPPABLE (1<<0)
		2887	#define PIN_NONBLOCK (1<<1)
		2888	#define PIN_GLOBAL (1<<2)
		2889	#define PIN_OFFSET_BIAS (1<<3)
		2890	#define PIN_USER (1<<4)
		2891	#define PIN_UPDATE (1<<5)
		2892	#define PIN_ZONE_4G (1<<6)
		2893	#define PIN_HIGH (1<<7)
6937	serge	2894	#define PIN_OFFSET_FIXED (1<<8)
5060	serge	2895	#define PIN_OFFSET_MASK (~4095)
6084	serge	2896	int __must_check
		2897	i915_gem_object_pin(struct drm_i915_gem_object *obj,
		2898	struct i915_address_space *vm,
		2899	uint32_t alignment,
		2900	uint64_t flags);
		2901	int __must_check
		2902	i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
		2903	const struct i915_ggtt_view *view,
		2904	uint32_t alignment,
		2905	uint64_t flags);
		2906
		2907	int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		2908	u32 flags);
		2909	void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
4104	Serge	2910	int __must_check i915_vma_unbind(struct i915_vma *vma);
6084	serge	2911	/*
		2912	* BEWARE: Do not use the function below unless you can _absolutely_
		2913	* _guarantee_ VMA in question is _not in use_ anywhere.
		2914	*/
		2915	int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3480	Serge	2916	int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
4560	Serge	2917	void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2325	Serge	2918	void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
		2919
5060	serge	2920	int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
		2921	int *needs_clflush);
		2922
3031	serge	2923	int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
6084	serge	2924
		2925	static inline int __sg_page_count(struct scatterlist *sg)
3031	serge	2926	{
6084	serge	2927	return sg->length >> PAGE_SHIFT;
		2928	}
3031	serge	2929
6937	serge	2930	struct page *
		2931	i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
		2932
6084	serge	2933	static inline struct page *
		2934	i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
		2935	{
		2936	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		2937	return NULL;
3746	Serge	2938
6084	serge	2939	if (n < obj->get_page.last) {
		2940	obj->get_page.sg = obj->pages->sgl;
		2941	obj->get_page.last = 0;
		2942	}
		2943
		2944	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		2945	obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		2946	if (unlikely(sg_is_chain(obj->get_page.sg)))
		2947	obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
		2948	}
		2949
		2950	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3243	Serge	2951	}
6084	serge	2952
3031	serge	2953	static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
		2954	{
3243	Serge	2955	BUG_ON(obj->pages == NULL);
3031	serge	2956	obj->pages_pin_count++;
		2957	}
		2958	static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
		2959	{
		2960	BUG_ON(obj->pages_pin_count == 0);
		2961	obj->pages_pin_count--;
		2962	}
		2963
2325	Serge	2964	int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3031	serge	2965	int i915_gem_object_sync(struct drm_i915_gem_object *obj,
6084	serge	2966	struct intel_engine_cs *to,
		2967	struct drm_i915_gem_request **to_req);
4560	Serge	2968	void i915_vma_move_to_active(struct i915_vma *vma,
6084	serge	2969	struct drm_i915_gem_request *req);
2325	Serge	2970	int i915_gem_dumb_create(struct drm_file *file_priv,
		2971	struct drm_device *dev,
		2972	struct drm_mode_create_dumb *args);
		2973	int i915_gem_mmap_gtt(struct drm_file file_priv, struct drm_device dev,
		2974	uint32_t handle, uint64_t *offset);
		2975	/**
		2976	* Returns true if seq1 is later than seq2.
		2977	*/
2340	Serge	2978	static inline bool
		2979	i915_seqno_passed(uint32_t seq1, uint32_t seq2)
		2980	{
		2981	return (int32_t)(seq1 - seq2) >= 0;
		2982	}
2325	Serge	2983
6084	serge	2984	static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
		2985	bool lazy_coherency)
		2986	{
		2987	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2988	return i915_seqno_passed(seqno, req->previous_seqno);
		2989	}
		2990
		2991	static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
		2992	bool lazy_coherency)
		2993	{
		2994	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
		2995	return i915_seqno_passed(seqno, req->seqno);
		2996	}
		2997
3480	Serge	2998	int __must_check i915_gem_get_seqno(struct drm_device dev, u32 seqno);
		2999	int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3031	serge	3000
5060	serge	3001	struct drm_i915_gem_request *
		3002	i915_gem_find_active_request(struct intel_engine_cs *ring);
2332	Serge	3003
4560	Serge	3004	bool i915_gem_retire_requests(struct drm_device *dev);
5060	serge	3005	void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3480	Serge	3006	int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3031	serge	3007	bool interruptible);
5060	serge	3008
3480	Serge	3009	static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
		3010	{
		3011	return unlikely(atomic_read(&error->reset_counter)
4560	Serge	3012	& (I915_RESET_IN_PROGRESS_FLAG \| I915_WEDGED));
3480	Serge	3013	}
3031	serge	3014
3480	Serge	3015	static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
		3016	{
4560	Serge	3017	return atomic_read(&error->reset_counter) & I915_WEDGED;
3480	Serge	3018	}
		3019
4560	Serge	3020	static inline u32 i915_reset_count(struct i915_gpu_error *error)
		3021	{
		3022	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
		3023	}
		3024
5060	serge	3025	static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
		3026	{
		3027	return dev_priv->gpu_error.stop_rings == 0 \|\|
		3028	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
		3029	}
		3030
		3031	static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
		3032	{
		3033	return dev_priv->gpu_error.stop_rings == 0 \|\|
		3034	dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
		3035	}
		3036
2325	Serge	3037	void i915_gem_reset(struct drm_device *dev);
4104	Serge	3038	bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3031	serge	3039	int __must_check i915_gem_init(struct drm_device *dev);
5354	serge	3040	int i915_gem_init_rings(struct drm_device *dev);
3031	serge	3041	int __must_check i915_gem_init_hw(struct drm_device *dev);
6084	serge	3042	int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3031	serge	3043	void i915_gem_init_swizzling(struct drm_device *dev);
2325	Serge	3044	void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
		3045	int __must_check i915_gpu_idle(struct drm_device *dev);
4560	Serge	3046	int __must_check i915_gem_suspend(struct drm_device *dev);
6084	serge	3047	void __i915_add_request(struct drm_i915_gem_request *req,
		3048	struct drm_i915_gem_object *batch_obj,
		3049	bool flush_caches);
		3050	#define i915_add_request(req) \
		3051	__i915_add_request(req, NULL, true)
		3052	#define i915_add_request_no_flush(req) \
		3053	__i915_add_request(req, NULL, false)
		3054	int __i915_wait_request(struct drm_i915_gem_request *req,
5354	serge	3055	unsigned reset_counter,
		3056	bool interruptible,
		3057	s64 *timeout,
6084	serge	3058	struct intel_rps_client *rps);
		3059	int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2325	Serge	3060	int i915_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
		3061	int __must_check
6084	serge	3062	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
		3063	bool readonly);
		3064	int __must_check
2325	Serge	3065	i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
		3066	bool write);
		3067	int __must_check
3031	serge	3068	i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
		3069	int __must_check
2325	Serge	3070	i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
		3071	u32 alignment,
6084	serge	3072	const struct i915_ggtt_view *view);
		3073	void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
		3074	const struct i915_ggtt_view *view);
5060	serge	3075	int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2325	Serge	3076	int align);
4560	Serge	3077	int i915_gem_open(struct drm_device dev, struct drm_file file);
2325	Serge	3078	void i915_gem_release(struct drm_device dev, struct drm_file file);
		3079
		3080	uint32_t
3480	Serge	3081	i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
		3082	uint32_t
		3083	i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
		3084	int tiling_mode, bool fenced);
2325	Serge	3085
		3086	int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
		3087	enum i915_cache_level cache_level);
		3088
4104	Serge	3089	struct drm_gem_object i915_gem_prime_import(struct drm_device dev,
		3090	struct dma_buf *dma_buf);
3031	serge	3091
		3092	struct dma_buf i915_gem_prime_export(struct drm_device dev,
		3093	struct drm_gem_object *gem_obj, int flags);
		3094
6084	serge	3095	u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
		3096	const struct i915_ggtt_view *view);
		3097	u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
		3098	struct i915_address_space *vm);
		3099	static inline u64
		3100	i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
		3101	{
		3102	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
		3103	}
3746	Serge	3104
4104	Serge	3105	bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
6084	serge	3106	bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
		3107	const struct i915_ggtt_view *view);
4104	Serge	3108	bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
		3109	struct i915_address_space *vm);
6084	serge	3110
4104	Serge	3111	unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
		3112	struct i915_address_space *vm);
		3113	struct i915_vma *
6084	serge	3114	i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		3115	struct i915_address_space *vm);
		3116	struct i915_vma *
		3117	i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
		3118	const struct i915_ggtt_view *view);
		3119
		3120	struct i915_vma *
4104	Serge	3121	i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
		3122	struct i915_address_space *vm);
6084	serge	3123	struct i915_vma *
		3124	i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
		3125	const struct i915_ggtt_view *view);
4560	Serge	3126
6084	serge	3127	static inline struct i915_vma *
		3128	i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
		3129	{
		3130	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
5060	serge	3131	}
6084	serge	3132	bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
4560	Serge	3133
4104	Serge	3134	/* Some GGTT VM helpers */
5354	serge	3135	#define i915_obj_to_ggtt(obj) \
4104	Serge	3136	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
		3137	static inline bool i915_is_ggtt(struct i915_address_space *vm)
		3138	{
		3139	struct i915_address_space *ggtt =
		3140	&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
		3141	return vm == ggtt;
		3142	}
		3143
5354	serge	3144	static inline struct i915_hw_ppgtt *
		3145	i915_vm_to_ppgtt(struct i915_address_space *vm)
		3146	{
		3147	WARN_ON(i915_is_ggtt(vm));
		3148
		3149	return container_of(vm, struct i915_hw_ppgtt, base);
		3150	}
		3151
		3152
4104	Serge	3153	static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
		3154	{
6084	serge	3155	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
4104	Serge	3156	}
		3157
		3158	static inline unsigned long
		3159	i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
		3160	{
5354	serge	3161	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
4104	Serge	3162	}
		3163
		3164	static inline int __must_check
		3165	i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		3166	uint32_t alignment,
5060	serge	3167	unsigned flags)
4104	Serge	3168	{
5354	serge	3169	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
		3170	alignment, flags \| PIN_GLOBAL);
4104	Serge	3171	}
		3172
5060	serge	3173	static inline int
		3174	i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
		3175	{
		3176	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
		3177	}
		3178
6084	serge	3179	void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
		3180	const struct i915_ggtt_view *view);
		3181	static inline void
		3182	i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
		3183	{
		3184	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
		3185	}
5060	serge	3186
6084	serge	3187	/* i915_gem_fence.c */
		3188	int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
		3189	int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
		3190
		3191	bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
		3192	void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
		3193
		3194	void i915_gem_restore_fences(struct drm_device *dev);
		3195
		3196	void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
		3197	void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3198	void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
		3199
3031	serge	3200	/* i915_gem_context.c */
4560	Serge	3201	int __must_check i915_gem_context_init(struct drm_device *dev);
3031	serge	3202	void i915_gem_context_fini(struct drm_device *dev);
5060	serge	3203	void i915_gem_context_reset(struct drm_device *dev);
		3204	int i915_gem_context_open(struct drm_device dev, struct drm_file file);
6084	serge	3205	int i915_gem_context_enable(struct drm_i915_gem_request *req);
3031	serge	3206	void i915_gem_context_close(struct drm_device dev, struct drm_file file);
6084	serge	3207	int i915_switch_context(struct drm_i915_gem_request *req);
5060	serge	3208	struct intel_context *
		3209	i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
4104	Serge	3210	void i915_gem_context_free(struct kref *ctx_ref);
5354	serge	3211	struct drm_i915_gem_object *
		3212	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
5060	serge	3213	static inline void i915_gem_context_reference(struct intel_context *ctx)
4104	Serge	3214	{
		3215	kref_get(&ctx->ref);
		3216	}
		3217
5060	serge	3218	static inline void i915_gem_context_unreference(struct intel_context *ctx)
4104	Serge	3219	{
		3220	kref_put(&ctx->ref, i915_gem_context_free);
		3221	}
		3222
5060	serge	3223	static inline bool i915_gem_context_is_default(const struct intel_context *c)
		3224	{
		3225	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
		3226	}
		3227
3031	serge	3228	int i915_gem_context_create_ioctl(struct drm_device dev, void data,
		3229	struct drm_file *file);
		3230	int i915_gem_context_destroy_ioctl(struct drm_device dev, void data,
		3231	struct drm_file *file);
6084	serge	3232	int i915_gem_context_getparam_ioctl(struct drm_device dev, void data,
		3233	struct drm_file *file_priv);
		3234	int i915_gem_context_setparam_ioctl(struct drm_device dev, void data,
		3235	struct drm_file *file_priv);
3031	serge	3236
2325	Serge	3237	/* i915_gem_evict.c */
4104	Serge	3238	int __must_check i915_gem_evict_something(struct drm_device *dev,
		3239	struct i915_address_space *vm,
		3240	int min_size,
3031	serge	3241	unsigned alignment,
		3242	unsigned cache_level,
5060	serge	3243	unsigned long start,
		3244	unsigned long end,
		3245	unsigned flags);
6937	serge	3246	int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
4560	Serge	3247	int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2325	Serge	3248
5060	serge	3249	/* belongs in i915_gem_gtt.h */
		3250	static inline void i915_gem_chipset_flush(struct drm_device *dev)
		3251	{
		3252	if (INTEL_INFO(dev)->gen < 6)
		3253	intel_gtt_chipset_flush();
		3254	}
		3255
3031	serge	3256	/* i915_gem_stolen.c */
6084	serge	3257	int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
		3258	struct drm_mm_node *node, u64 size,
		3259	unsigned alignment);
		3260	int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
		3261	struct drm_mm_node *node, u64 size,
		3262	unsigned alignment, u64 start,
		3263	u64 end);
		3264	void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
		3265	struct drm_mm_node *node);
3031	serge	3266	int i915_gem_init_stolen(struct drm_device *dev);
		3267	void i915_gem_cleanup_stolen(struct drm_device *dev);
3480	Serge	3268	struct drm_i915_gem_object *
		3269	i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3746	Serge	3270	struct drm_i915_gem_object *
		3271	i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
		3272	u32 stolen_offset,
		3273	u32 gtt_offset,
		3274	u32 size);
3031	serge	3275
6084	serge	3276	/* i915_gem_shrinker.c */
		3277	unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
		3278	unsigned long target,
		3279	unsigned flags);
		3280	#define I915_SHRINK_PURGEABLE 0x1
		3281	#define I915_SHRINK_UNBOUND 0x2
		3282	#define I915_SHRINK_BOUND 0x4
		3283	#define I915_SHRINK_ACTIVE 0x8
		3284	unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
		3285	void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
		3286
		3287
2325	Serge	3288	/* i915_gem_tiling.c */
4104	Serge	3289	static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3480	Serge	3290	{
5060	serge	3291	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3480	Serge	3292
		3293	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		3294	obj->tiling_mode != I915_TILING_NONE;
		3295	}
		3296
2325	Serge	3297	/* i915_gem_debug.c */
		3298	#if WATCH_LISTS
		3299	int i915_verify_lists(struct drm_device *dev);
		3300	#else
		3301	#define i915_verify_lists(dev) 0
		3302	#endif
		3303
		3304	/* i915_debugfs.c */
		3305	int i915_debugfs_init(struct drm_minor *minor);
		3306	void i915_debugfs_cleanup(struct drm_minor *minor);
4560	Serge	3307	#ifdef CONFIG_DEBUG_FS
6084	serge	3308	int i915_debugfs_connector_add(struct drm_connector *connector);
4560	Serge	3309	void intel_display_crc_init(struct drm_device *dev);
		3310	#else
6084	serge	3311	static inline int i915_debugfs_connector_add(struct drm_connector *connector)
		3312	{ return 0; }
4560	Serge	3313	static inline void intel_display_crc_init(struct drm_device *dev) {}
		3314	#endif
2325	Serge	3315
4104	Serge	3316	/* i915_gpu_error.c */
		3317	__printf(2, 3)
		3318	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...);
		3319	int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
		3320	const struct i915_error_state_file_priv *error);
		3321	int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
5354	serge	3322	struct drm_i915_private *i915,
4104	Serge	3323	size_t count, loff_t pos);
		3324	static inline void i915_error_state_buf_release(
		3325	struct drm_i915_error_state_buf *eb)
		3326	{
		3327	kfree(eb->buf);
		3328	}
5060	serge	3329	void i915_capture_error_state(struct drm_device *dev, bool wedge,
		3330	const char *error_msg);
4104	Serge	3331	void i915_error_state_get(struct drm_device *dev,
		3332	struct i915_error_state_file_priv *error_priv);
		3333	void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
		3334	void i915_destroy_error_state(struct drm_device *dev);
		3335
		3336	void i915_get_extra_instdone(struct drm_device dev, uint32_t instdone);
5354	serge	3337	const char i915_cache_level_str(struct drm_i915_private i915, int type);
4104	Serge	3338
5060	serge	3339	/* i915_cmd_parser.c */
		3340	int i915_cmd_parser_get_version(void);
		3341	int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
		3342	void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
		3343	bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
		3344	int i915_parse_cmds(struct intel_engine_cs *ring,
		3345	struct drm_i915_gem_object *batch_obj,
6084	serge	3346	struct drm_i915_gem_object *shadow_batch_obj,
5060	serge	3347	u32 batch_start_offset,
6084	serge	3348	u32 batch_len,
5060	serge	3349	bool is_master);
		3350
2325	Serge	3351	/* i915_suspend.c */
		3352	extern int i915_save_state(struct drm_device *dev);
		3353	extern int i915_restore_state(struct drm_device *dev);
		3354
3031	serge	3355	/* i915_sysfs.c */
		3356	void i915_setup_sysfs(struct drm_device *dev_priv);
		3357	void i915_teardown_sysfs(struct drm_device *dev_priv);
		3358
2325	Serge	3359	/* intel_i2c.c */
		3360	extern int intel_setup_gmbus(struct drm_device *dev);
		3361	extern void intel_teardown_gmbus(struct drm_device *dev);
6084	serge	3362	extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
		3363	unsigned int pin);
3031	serge	3364
6084	serge	3365	extern struct i2c_adapter *
		3366	intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
2325	Serge	3367	extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
		3368	extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4104	Serge	3369	static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2342	Serge	3370	{
		3371	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
		3372	}
2325	Serge	3373	extern void intel_i2c_reset(struct drm_device *dev);
		3374
6935	serge	3375	/* intel_bios.c */
6937	serge	3376	int intel_bios_init(struct drm_i915_private *dev_priv);
		3377	bool intel_bios_is_valid_vbt(const void *buf, size_t size);
6935	serge	3378
2325	Serge	3379	/* intel_opregion.c */
4560	Serge	3380	#ifdef CONFIG_ACPI
2325	Serge	3381	extern int intel_opregion_setup(struct drm_device *dev);
		3382	extern void intel_opregion_init(struct drm_device *dev);
		3383	extern void intel_opregion_fini(struct drm_device *dev);
		3384	extern void intel_opregion_asle_intr(struct drm_device *dev);
4560	Serge	3385	extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
		3386	bool enable);
		3387	extern int intel_opregion_notify_adapter(struct drm_device *dev,
		3388	pci_power_t state);
2325	Serge	3389	#else
4560	Serge	3390	static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2325	Serge	3391	static inline void intel_opregion_init(struct drm_device *dev) { return; }
		3392	static inline void intel_opregion_fini(struct drm_device *dev) { return; }
		3393	static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
4560	Serge	3394	static inline int
		3395	intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
		3396	{
		3397	return 0;
		3398	}
		3399	static inline int
		3400	intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
		3401	{
		3402	return 0;
		3403	}
2325	Serge	3404	#endif
		3405
		3406	/* intel_acpi.c */
		3407	#ifdef CONFIG_ACPI
		3408	extern void intel_register_dsm_handler(void);
		3409	extern void intel_unregister_dsm_handler(void);
		3410	#else
		3411	static inline void intel_register_dsm_handler(void) { return; }
		3412	static inline void intel_unregister_dsm_handler(void) { return; }
		3413	#endif /* CONFIG_ACPI */
		3414
		3415	/* modesetting */
3031	serge	3416	extern void intel_modeset_init_hw(struct drm_device *dev);
2325	Serge	3417	extern void intel_modeset_init(struct drm_device *dev);
		3418	extern void intel_modeset_gem_init(struct drm_device *dev);
		3419	extern void intel_modeset_cleanup(struct drm_device *dev);
5060	serge	3420	extern void intel_connector_unregister(struct intel_connector *);
2325	Serge	3421	extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
6084	serge	3422	extern void intel_display_resume(struct drm_device *dev);
3480	Serge	3423	extern void i915_redisable_vga(struct drm_device *dev);
5060	serge	3424	extern void i915_redisable_vga_power_on(struct drm_device *dev);
2325	Serge	3425	extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3243	Serge	3426	extern void intel_init_pch_refclk(struct drm_device *dev);
6084	serge	3427	extern void intel_set_rps(struct drm_device *dev, u8 val);
5060	serge	3428	extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
		3429	bool enable);
2342	Serge	3430	extern void intel_detect_pch(struct drm_device *dev);
3031	serge	3431	extern int intel_enable_rc6(const struct drm_device *dev);
2325	Serge	3432
3031	serge	3433	extern bool i915_semaphore_is_enabled(struct drm_device *dev);
		3434	int i915_reg_read_ioctl(struct drm_device dev, void data,
		3435	struct drm_file *file);
4560	Serge	3436	int i915_get_reset_stats_ioctl(struct drm_device dev, void data,
		3437	struct drm_file *file);
2342	Serge	3438
2325	Serge	3439	/* overlay */
		3440	extern struct intel_overlay_error_state intel_overlay_capture_error_state(struct drm_device dev);
4104	Serge	3441	extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
		3442	struct intel_overlay_error_state *error);
2325	Serge	3443
		3444	extern struct intel_display_error_state intel_display_capture_error_state(struct drm_device dev);
4104	Serge	3445	extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2325	Serge	3446	struct drm_device *dev,
		3447	struct intel_display_error_state *error);
		3448
5354	serge	3449	int sandybridge_pcode_read(struct drm_i915_private dev_priv, u32 mbox, u32 val);
		3450	int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3243	Serge	3451
4104	Serge	3452	/* intel_sideband.c */
6084	serge	3453	u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
		3454	void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
4104	Serge	3455	u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
4560	Serge	3456	u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
		3457	void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3458	u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
		3459	void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3460	u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
		3461	void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3462	u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
		3463	void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3464	u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
		3465	void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
		3466	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
		3467	void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
4104	Serge	3468	u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		3469	enum intel_sbi_destination destination);
		3470	void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		3471	enum intel_sbi_destination destination);
4560	Serge	3472	u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
		3473	void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2325	Serge	3474
6084	serge	3475	int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
		3476	int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
4104	Serge	3477
4560	Serge	3478	#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
		3479	#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2325	Serge	3480
4560	Serge	3481	#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
		3482	#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
		3483	#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
		3484	#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
		3485
		3486	#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
		3487	#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
		3488	#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
		3489	#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
		3490
5060	serge	3491	/* Be very careful with read/write 64-bit values. On 32-bit machines, they
		3492	* will be implemented using 2 32-bit writes in an arbitrary order with
		3493	* an arbitrary delay between them. This can cause the hardware to
		3494	* act upon the intermediate value, possibly leading to corruption and
		3495	* machine death. You have been warned.
		3496	*/
4560	Serge	3497	#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
		3498	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
		3499
5060	serge	3500	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
6084	serge	3501	u32 upper, lower, old_upper, loop = 0; \
		3502	upper = I915_READ(upper_reg); \
		3503	do { \
		3504	old_upper = upper; \
		3505	lower = I915_READ(lower_reg); \
		3506	upper = I915_READ(upper_reg); \
		3507	} while (upper != old_upper && loop++ < 2); \
		3508	(u64)upper << 32 \| lower; })
5060	serge	3509
2325	Serge	3510	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
		3511	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
		3512
6937	serge	3513	#define __raw_read(x, s) \
		3514	static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
		3515	i915_reg_t reg) \
		3516	{ \
		3517	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
		3518	}
		3519
		3520	#define __raw_write(x, s) \
		3521	static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
		3522	i915_reg_t reg, uint##x##_t val) \
		3523	{ \
		3524	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
		3525	}
		3526	__raw_read(8, b)
		3527	__raw_read(16, w)
		3528	__raw_read(32, l)
		3529	__raw_read(64, q)
		3530
		3531	__raw_write(8, b)
		3532	__raw_write(16, w)
		3533	__raw_write(32, l)
		3534	__raw_write(64, q)
		3535
		3536	#undef __raw_read
		3537	#undef __raw_write
		3538
6084	serge	3539	/* These are untraced mmio-accessors that are only valid to be used inside
		3540	* criticial sections inside IRQ handlers where forcewake is explicitly
		3541	* controlled.
		3542	* Think twice, and think again, before using these.
		3543	* Note: Should only be used between intel_uncore_forcewake_irqlock() and
		3544	* intel_uncore_forcewake_irqunlock().
		3545	*/
6937	serge	3546	#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
		3547	#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
6084	serge	3548	#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
		3549
3480	Serge	3550	/* "Broadcast RGB" property */
		3551	#define INTEL_BROADCAST_RGB_AUTO 0
		3552	#define INTEL_BROADCAST_RGB_FULL 1
		3553	#define INTEL_BROADCAST_RGB_LIMITED 2
		3554
6937	serge	3555	static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3480	Serge	3556	{
6937	serge	3557	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
5060	serge	3558	return VLV_VGACNTRL;
		3559	else if (INTEL_INFO(dev)->gen >= 5)
3480	Serge	3560	return CPU_VGACNTRL;
		3561	else
		3562	return VGACNTRL;
		3563	}
		3564
3746	Serge	3565	static inline void __user *to_user_ptr(u64 address)
		3566	{
		3567	return (void __user *)(uintptr_t)address;
		3568	}
		3569
		3570	static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
		3571	{
		3572	unsigned long j = msecs_to_jiffies(m);
		3573
		3574	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3575	}
		3576
5354	serge	3577	static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
		3578	{
		3579	return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
		3580	}
		3581
3746	Serge	3582	static inline unsigned long
		3583	timespec_to_jiffies_timeout(const struct timespec *value)
		3584	{
		3585	unsigned long j = timespec_to_jiffies(value);
		3586
		3587	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
		3588	}
		3589
5060	serge	3590	/*
		3591	* If you need to wait X milliseconds between events A and B, but event B
		3592	* doesn't happen exactly after event A, you record the timestamp (jiffies) of
		3593	* when event A happened, then just before event B you call this function and
		3594	* pass the timestamp as the first argument, and X as the second argument.
		3595	*/
		3596	static inline void
		3597	wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4280	Serge	3598	{
5060	serge	3599	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
		3600
		3601	/*
		3602	* Don't re-read the value of "jiffies" every time since it may change
		3603	* behind our back and break the math.
		3604	*/
		3605	tmp_jiffies = jiffies;
		3606	target_jiffies = timestamp_jiffies +
		3607	msecs_to_jiffies_timeout(to_wait_ms);
		3608
		3609	if (time_after(target_jiffies, tmp_jiffies)) {
		3610	remaining_jiffies = target_jiffies - tmp_jiffies;
6103	serge	3611	delay(remaining_jiffies);
5060	serge	3612	}
4280	Serge	3613	}
3746	Serge	3614
6084	serge	3615	static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
		3616	struct drm_i915_gem_request *req)
2338	Serge	3617	{
6084	serge	3618	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		3619	i915_gem_request_assign(&ring->trace_irq_req, req);
5354	serge	3620	}
		3621
6937	serge	3622	#include "intel_drv.h"
		3623
2325	Serge	3624	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 6937