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2325 | Serge | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * |
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5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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6 | * All Rights Reserved. |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the |
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10 | * "Software"), to deal in the Software without restriction, including |
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11 | * without limitation the rights to use, copy, modify, merge, publish, |
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12 | * distribute, sub license, and/or sell copies of the Software, and to |
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13 | * permit persons to whom the Software is furnished to do so, subject to |
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14 | * the following conditions: |
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15 | * |
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16 | * The above copyright notice and this permission notice (including the |
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17 | * next paragraph) shall be included in all copies or substantial portions |
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18 | * of the Software. |
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19 | * |
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20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | * |
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28 | */ |
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29 | |||
30 | #ifndef _I915_DRV_H_ |
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31 | #define _I915_DRV_H_ |
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32 | |||
3480 | Serge | 33 | #include |
34 | |||
2325 | Serge | 35 | #include "i915_reg.h" |
2327 | Serge | 36 | #include "intel_bios.h" |
2326 | Serge | 37 | #include "intel_ringbuffer.h" |
3243 | Serge | 38 | #include |
2325 | Serge | 39 | //#include |
2330 | Serge | 40 | #include |
3031 | serge | 41 | #include |
2332 | Serge | 42 | #include |
2325 | Serge | 43 | //#include |
44 | |||
45 | #include |
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3243 | Serge | 46 | #include |
2325 | Serge | 47 | |
2360 | Serge | 48 | |
2325 | Serge | 49 | /* General customization: |
50 | */ |
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51 | |||
3031 | serge | 52 | #define I915_TILING_NONE 0 |
2327 | Serge | 53 | |
3031 | serge | 54 | #define VGA_RSRC_NONE 0x00 |
55 | #define VGA_RSRC_LEGACY_IO 0x01 |
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56 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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57 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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58 | /* Non-legacy access */ |
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59 | #define VGA_RSRC_NORMAL_IO 0x04 |
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60 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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2327 | Serge | 61 | |
2325 | Serge | 62 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
63 | |||
64 | #define DRIVER_NAME "i915" |
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65 | #define DRIVER_DESC "Intel Graphics" |
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66 | #define DRIVER_DATE "20080730" |
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67 | |||
68 | enum pipe { |
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69 | PIPE_A = 0, |
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70 | PIPE_B, |
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71 | PIPE_C, |
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72 | I915_MAX_PIPES |
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73 | }; |
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74 | #define pipe_name(p) ((p) + 'A') |
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75 | |||
3243 | Serge | 76 | enum transcoder { |
77 | TRANSCODER_A = 0, |
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78 | TRANSCODER_B, |
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79 | TRANSCODER_C, |
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80 | TRANSCODER_EDP = 0xF, |
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81 | }; |
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82 | #define transcoder_name(t) ((t) + 'A') |
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83 | |||
2325 | Serge | 84 | enum plane { |
85 | PLANE_A = 0, |
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86 | PLANE_B, |
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87 | PLANE_C, |
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88 | }; |
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89 | #define plane_name(p) ((p) + 'A') |
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90 | |||
3031 | serge | 91 | enum port { |
92 | PORT_A = 0, |
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93 | PORT_B, |
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94 | PORT_C, |
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95 | PORT_D, |
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96 | PORT_E, |
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97 | I915_MAX_PORTS |
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98 | }; |
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99 | #define port_name(p) ((p) + 'A') |
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100 | |||
3746 | Serge | 101 | enum hpd_pin { |
102 | HPD_NONE = 0, |
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103 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
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104 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
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105 | HPD_CRT, |
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106 | HPD_SDVO_B, |
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107 | HPD_SDVO_C, |
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108 | HPD_PORT_B, |
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109 | HPD_PORT_C, |
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110 | HPD_PORT_D, |
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111 | HPD_NUM_PINS |
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112 | }; |
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113 | |||
3480 | Serge | 114 | #define I915_GEM_GPU_DOMAINS \ |
115 | (I915_GEM_DOMAIN_RENDER | \ |
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116 | I915_GEM_DOMAIN_SAMPLER | \ |
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117 | I915_GEM_DOMAIN_COMMAND | \ |
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118 | I915_GEM_DOMAIN_INSTRUCTION | \ |
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119 | I915_GEM_DOMAIN_VERTEX) |
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2325 | Serge | 120 | |
3746 | Serge | 121 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
2325 | Serge | 122 | |
3031 | serge | 123 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
124 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
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125 | if ((intel_encoder)->base.crtc == (__crtc)) |
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126 | |||
127 | struct intel_pch_pll { |
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128 | int refcount; /* count of number of CRTCs sharing this PLL */ |
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129 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
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130 | bool on; /* is the PLL actually active? Disabled during modeset */ |
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131 | int pll_reg; |
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132 | int fp0_reg; |
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133 | int fp1_reg; |
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134 | }; |
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135 | #define I915_NUM_PLLS 2 |
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136 | |||
3480 | Serge | 137 | /* Used by dp and fdi links */ |
138 | struct intel_link_m_n { |
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139 | uint32_t tu; |
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140 | uint32_t gmch_m; |
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141 | uint32_t gmch_n; |
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142 | uint32_t link_m; |
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143 | uint32_t link_n; |
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144 | }; |
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145 | |||
146 | void intel_link_compute_m_n(int bpp, int nlanes, |
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147 | int pixel_clock, int link_clock, |
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148 | struct intel_link_m_n *m_n); |
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149 | |||
3243 | Serge | 150 | struct intel_ddi_plls { |
151 | int spll_refcount; |
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152 | int wrpll1_refcount; |
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153 | int wrpll2_refcount; |
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154 | }; |
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155 | |||
2325 | Serge | 156 | /* Interface history: |
157 | * |
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158 | * 1.1: Original. |
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159 | * 1.2: Add Power Management |
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160 | * 1.3: Add vblank support |
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161 | * 1.4: Fix cmdbuffer path, add heap destroy |
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162 | * 1.5: Add vblank pipe configuration |
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163 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
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164 | * - Support vertical blank on secondary display pipe |
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165 | */ |
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166 | #define DRIVER_MAJOR 1 |
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167 | #define DRIVER_MINOR 6 |
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168 | #define DRIVER_PATCHLEVEL 0 |
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169 | |||
170 | #define WATCH_COHERENCY 0 |
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171 | #define WATCH_LISTS 0 |
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3031 | serge | 172 | #define WATCH_GTT 0 |
2325 | Serge | 173 | |
174 | #define I915_GEM_PHYS_CURSOR_0 1 |
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175 | #define I915_GEM_PHYS_CURSOR_1 2 |
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176 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
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177 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
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178 | |||
3480 | Serge | 179 | struct drm_i915_gem_phys_object { |
180 | int id; |
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181 | struct page **page_list; |
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182 | drm_dma_handle_t *handle; |
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183 | struct drm_i915_gem_object *cur_obj; |
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184 | }; |
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2325 | Serge | 185 | |
186 | struct opregion_header; |
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187 | struct opregion_acpi; |
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188 | struct opregion_swsci; |
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189 | struct opregion_asle; |
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2342 | Serge | 190 | struct drm_i915_private; |
2325 | Serge | 191 | |
192 | struct intel_opregion { |
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3031 | serge | 193 | struct opregion_header __iomem *header; |
194 | struct opregion_acpi __iomem *acpi; |
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195 | struct opregion_swsci __iomem *swsci; |
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196 | struct opregion_asle __iomem *asle; |
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197 | void __iomem *vbt; |
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2325 | Serge | 198 | u32 __iomem *lid_state; |
199 | }; |
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200 | #define OPREGION_SIZE (8*1024) |
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201 | |||
202 | struct intel_overlay; |
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203 | struct intel_overlay_error_state; |
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204 | |||
2330 | Serge | 205 | struct drm_i915_master_private { |
206 | drm_local_map_t *sarea; |
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207 | struct _drm_i915_sarea *sarea_priv; |
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208 | }; |
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2325 | Serge | 209 | #define I915_FENCE_REG_NONE -1 |
3746 | Serge | 210 | #define I915_MAX_NUM_FENCES 32 |
211 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
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212 | #define I915_MAX_NUM_FENCE_BITS 6 |
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2325 | Serge | 213 | |
214 | struct drm_i915_fence_reg { |
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215 | struct list_head lru_list; |
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216 | struct drm_i915_gem_object *obj; |
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3031 | serge | 217 | int pin_count; |
2325 | Serge | 218 | }; |
219 | |||
220 | struct sdvo_device_mapping { |
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221 | u8 initialized; |
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222 | u8 dvo_port; |
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223 | u8 slave_addr; |
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224 | u8 dvo_wiring; |
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225 | u8 i2c_pin; |
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226 | u8 ddc_pin; |
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227 | }; |
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228 | |||
229 | struct intel_display_error_state; |
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230 | |||
231 | struct drm_i915_error_state { |
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3243 | Serge | 232 | struct kref ref; |
2325 | Serge | 233 | u32 eir; |
234 | u32 pgtbl_er; |
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3031 | serge | 235 | u32 ier; |
236 | u32 ccid; |
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3243 | Serge | 237 | u32 derrmr; |
238 | u32 forcewake; |
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3031 | serge | 239 | bool waiting[I915_NUM_RINGS]; |
2325 | Serge | 240 | u32 pipestat[I915_MAX_PIPES]; |
3031 | serge | 241 | u32 tail[I915_NUM_RINGS]; |
242 | u32 head[I915_NUM_RINGS]; |
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3243 | Serge | 243 | u32 ctl[I915_NUM_RINGS]; |
3031 | serge | 244 | u32 ipeir[I915_NUM_RINGS]; |
245 | u32 ipehr[I915_NUM_RINGS]; |
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246 | u32 instdone[I915_NUM_RINGS]; |
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247 | u32 acthd[I915_NUM_RINGS]; |
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248 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
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3243 | Serge | 249 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
3031 | serge | 250 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
251 | /* our own tracking of ring head and tail */ |
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252 | u32 cpu_ring_head[I915_NUM_RINGS]; |
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253 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
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2325 | Serge | 254 | u32 error; /* gen6+ */ |
3031 | serge | 255 | u32 err_int; /* gen7 */ |
256 | u32 instpm[I915_NUM_RINGS]; |
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257 | u32 instps[I915_NUM_RINGS]; |
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258 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
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259 | u32 seqno[I915_NUM_RINGS]; |
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2325 | Serge | 260 | u64 bbaddr; |
3031 | serge | 261 | u32 fault_reg[I915_NUM_RINGS]; |
262 | u32 done_reg; |
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263 | u32 faddr[I915_NUM_RINGS]; |
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2342 | Serge | 264 | u64 fence[I915_MAX_NUM_FENCES]; |
2325 | Serge | 265 | struct timeval time; |
3031 | serge | 266 | struct drm_i915_error_ring { |
2325 | Serge | 267 | struct drm_i915_error_object { |
268 | int page_count; |
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269 | u32 gtt_offset; |
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270 | u32 *pages[0]; |
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3746 | Serge | 271 | } *ringbuffer, *batchbuffer, *ctx; |
3031 | serge | 272 | struct drm_i915_error_request { |
273 | long jiffies; |
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274 | u32 seqno; |
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275 | u32 tail; |
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276 | } *requests; |
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277 | int num_requests; |
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278 | } ring[I915_NUM_RINGS]; |
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2325 | Serge | 279 | struct drm_i915_error_buffer { |
280 | u32 size; |
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281 | u32 name; |
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3031 | serge | 282 | u32 rseqno, wseqno; |
2325 | Serge | 283 | u32 gtt_offset; |
284 | u32 read_domains; |
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285 | u32 write_domain; |
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2342 | Serge | 286 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
2325 | Serge | 287 | s32 pinned:2; |
288 | u32 tiling:2; |
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289 | u32 dirty:1; |
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290 | u32 purgeable:1; |
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3031 | serge | 291 | s32 ring:4; |
2325 | Serge | 292 | u32 cache_level:2; |
293 | } *active_bo, *pinned_bo; |
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294 | u32 active_bo_count, pinned_bo_count; |
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295 | struct intel_overlay_error_state *overlay; |
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296 | struct intel_display_error_state *display; |
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297 | }; |
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298 | |||
3746 | Serge | 299 | struct intel_crtc_config; |
300 | struct intel_crtc; |
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301 | |||
2325 | Serge | 302 | struct drm_i915_display_funcs { |
303 | bool (*fbc_enabled)(struct drm_device *dev); |
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304 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
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305 | void (*disable_fbc)(struct drm_device *dev); |
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306 | int (*get_display_clock_speed)(struct drm_device *dev); |
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307 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
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308 | void (*update_wm)(struct drm_device *dev); |
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2342 | Serge | 309 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
310 | uint32_t sprite_width, int pixel_size); |
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3031 | serge | 311 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
312 | struct drm_display_mode *mode); |
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3243 | Serge | 313 | void (*modeset_global_resources)(struct drm_device *dev); |
3746 | Serge | 314 | /* Returns the active state of the crtc, and if the crtc is active, |
315 | * fills out the pipe-config with the hw state. */ |
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316 | bool (*get_pipe_config)(struct intel_crtc *, |
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317 | struct intel_crtc_config *); |
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2325 | Serge | 318 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
319 | int x, int y, |
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320 | struct drm_framebuffer *old_fb); |
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3031 | serge | 321 | void (*crtc_enable)(struct drm_crtc *crtc); |
322 | void (*crtc_disable)(struct drm_crtc *crtc); |
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323 | void (*off)(struct drm_crtc *crtc); |
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2342 | Serge | 324 | void (*write_eld)(struct drm_connector *connector, |
325 | struct drm_crtc *crtc); |
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2325 | Serge | 326 | void (*fdi_link_train)(struct drm_crtc *crtc); |
327 | void (*init_clock_gating)(struct drm_device *dev); |
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328 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
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329 | struct drm_framebuffer *fb, |
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330 | struct drm_i915_gem_object *obj); |
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331 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
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332 | int x, int y); |
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3480 | Serge | 333 | void (*hpd_irq_setup)(struct drm_device *dev); |
2325 | Serge | 334 | /* clock updates for mode set */ |
335 | /* cursor updates */ |
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336 | /* render clock increase/decrease */ |
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337 | /* display clock increase/decrease */ |
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338 | /* pll clock increase/decrease */ |
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339 | }; |
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340 | |||
3031 | serge | 341 | struct drm_i915_gt_funcs { |
342 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
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343 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
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344 | }; |
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345 | |||
346 | #define DEV_INFO_FLAGS \ |
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347 | DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ |
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348 | DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ |
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349 | DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ |
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350 | DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ |
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351 | DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ |
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352 | DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ |
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353 | DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ |
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354 | DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ |
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355 | DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ |
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356 | DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ |
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357 | DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ |
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358 | DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ |
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359 | DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ |
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360 | DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ |
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361 | DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ |
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362 | DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ |
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363 | DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ |
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364 | DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ |
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365 | DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ |
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366 | DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ |
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367 | DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ |
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368 | DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ |
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369 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ |
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370 | DEV_INFO_FLAG(has_llc) |
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371 | |||
2325 | Serge | 372 | struct intel_device_info { |
3480 | Serge | 373 | u32 display_mmio_offset; |
3746 | Serge | 374 | u8 num_pipes:3; |
2325 | Serge | 375 | u8 gen; |
2342 | Serge | 376 | u8 is_mobile:1; |
377 | u8 is_i85x:1; |
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378 | u8 is_i915g:1; |
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379 | u8 is_i945gm:1; |
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380 | u8 is_g33:1; |
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381 | u8 need_gfx_hws:1; |
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382 | u8 is_g4x:1; |
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383 | u8 is_pineview:1; |
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384 | u8 is_broadwater:1; |
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385 | u8 is_crestline:1; |
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386 | u8 is_ivybridge:1; |
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3031 | serge | 387 | u8 is_valleyview:1; |
388 | u8 has_force_wake:1; |
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389 | u8 is_haswell:1; |
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2342 | Serge | 390 | u8 has_fbc:1; |
391 | u8 has_pipe_cxsr:1; |
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392 | u8 has_hotplug:1; |
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393 | u8 cursor_needs_physical:1; |
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394 | u8 has_overlay:1; |
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395 | u8 overlay_needs_physical:1; |
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396 | u8 supports_tv:1; |
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397 | u8 has_bsd_ring:1; |
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398 | u8 has_blt_ring:1; |
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3031 | serge | 399 | u8 has_llc:1; |
2325 | Serge | 400 | }; |
401 | |||
3480 | Serge | 402 | enum i915_cache_level { |
403 | I915_CACHE_NONE = 0, |
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404 | I915_CACHE_LLC, |
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405 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ |
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406 | }; |
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407 | |||
408 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
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409 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
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410 | * collateral associated with any va->pa translations GEN hardware also has a |
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411 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
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412 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
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413 | * the spec. |
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414 | */ |
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415 | struct i915_gtt { |
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416 | unsigned long start; /* Start offset of used GTT */ |
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417 | size_t total; /* Total size GTT can map */ |
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418 | size_t stolen_size; /* Total size of stolen memory */ |
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419 | |||
420 | unsigned long mappable_end; /* End offset that we can CPU map */ |
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421 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
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422 | phys_addr_t mappable_base; /* PA of our GMADR */ |
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423 | |||
424 | /** "Graphics Stolen Memory" holds the global PTEs */ |
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425 | void __iomem *gsm; |
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426 | |||
427 | bool do_idle_maps; |
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428 | dma_addr_t scratch_page_dma; |
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429 | struct page *scratch_page; |
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430 | |||
431 | /* global gtt ops */ |
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432 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
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433 | size_t *stolen, phys_addr_t *mappable_base, |
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434 | unsigned long *mappable_end); |
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435 | void (*gtt_remove)(struct drm_device *dev); |
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436 | void (*gtt_clear_range)(struct drm_device *dev, |
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437 | unsigned int first_entry, |
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438 | unsigned int num_entries); |
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439 | void (*gtt_insert_entries)(struct drm_device *dev, |
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440 | struct sg_table *st, |
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441 | unsigned int pg_start, |
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442 | enum i915_cache_level cache_level); |
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443 | }; |
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444 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
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445 | |||
3031 | serge | 446 | #define I915_PPGTT_PD_ENTRIES 512 |
447 | #define I915_PPGTT_PT_ENTRIES 1024 |
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448 | struct i915_hw_ppgtt { |
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3243 | Serge | 449 | struct drm_device *dev; |
3031 | serge | 450 | unsigned num_pd_entries; |
3243 | Serge | 451 | struct page **pt_pages; |
3031 | serge | 452 | uint32_t pd_offset; |
453 | dma_addr_t *pt_dma_addr; |
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454 | dma_addr_t scratch_page_dma_addr; |
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3480 | Serge | 455 | |
456 | /* pte functions, mirroring the interface of the global gtt. */ |
||
457 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, |
||
458 | unsigned int first_entry, |
||
459 | unsigned int num_entries); |
||
460 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, |
||
461 | struct sg_table *st, |
||
462 | unsigned int pg_start, |
||
463 | enum i915_cache_level cache_level); |
||
3746 | Serge | 464 | int (*enable)(struct drm_device *dev); |
3480 | Serge | 465 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
3031 | serge | 466 | }; |
467 | |||
468 | |||
469 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
||
470 | #define DEFAULT_CONTEXT_ID 0 |
||
471 | struct i915_hw_context { |
||
472 | int id; |
||
473 | bool is_initialized; |
||
474 | struct drm_i915_file_private *file_priv; |
||
475 | struct intel_ring_buffer *ring; |
||
476 | struct drm_i915_gem_object *obj; |
||
477 | }; |
||
478 | |||
2325 | Serge | 479 | enum no_fbc_reason { |
480 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
||
481 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
||
482 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
||
483 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
||
484 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
||
485 | FBC_NOT_TILED, /* buffer not tiled */ |
||
486 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
||
487 | FBC_MODULE_PARAM, |
||
488 | }; |
||
489 | |||
490 | enum intel_pch { |
||
3031 | serge | 491 | PCH_NONE = 0, /* No PCH present */ |
2325 | Serge | 492 | PCH_IBX, /* Ibexpeak PCH */ |
493 | PCH_CPT, /* Cougarpoint PCH */ |
||
3031 | serge | 494 | PCH_LPT, /* Lynxpoint PCH */ |
3746 | Serge | 495 | PCH_NOP, |
2325 | Serge | 496 | }; |
497 | |||
3243 | Serge | 498 | enum intel_sbi_destination { |
499 | SBI_ICLK, |
||
500 | SBI_MPHY, |
||
501 | }; |
||
502 | |||
2325 | Serge | 503 | #define QUIRK_PIPEA_FORCE (1<<0) |
504 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
||
3031 | serge | 505 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
2325 | Serge | 506 | |
507 | struct intel_fbdev; |
||
508 | struct intel_fbc_work; |
||
509 | |||
3031 | serge | 510 | struct intel_gmbus { |
511 | struct i2c_adapter adapter; |
||
3243 | Serge | 512 | u32 force_bit; |
3031 | serge | 513 | u32 reg0; |
514 | u32 gpio_reg; |
||
515 | struct i2c_algo_bit_data bit_algo; |
||
516 | struct drm_i915_private *dev_priv; |
||
517 | }; |
||
518 | |||
3243 | Serge | 519 | struct i915_suspend_saved_registers { |
2325 | Serge | 520 | u8 saveLBB; |
521 | u32 saveDSPACNTR; |
||
522 | u32 saveDSPBCNTR; |
||
523 | u32 saveDSPARB; |
||
524 | u32 savePIPEACONF; |
||
525 | u32 savePIPEBCONF; |
||
526 | u32 savePIPEASRC; |
||
527 | u32 savePIPEBSRC; |
||
528 | u32 saveFPA0; |
||
529 | u32 saveFPA1; |
||
530 | u32 saveDPLL_A; |
||
531 | u32 saveDPLL_A_MD; |
||
532 | u32 saveHTOTAL_A; |
||
533 | u32 saveHBLANK_A; |
||
534 | u32 saveHSYNC_A; |
||
535 | u32 saveVTOTAL_A; |
||
536 | u32 saveVBLANK_A; |
||
537 | u32 saveVSYNC_A; |
||
538 | u32 saveBCLRPAT_A; |
||
539 | u32 saveTRANSACONF; |
||
540 | u32 saveTRANS_HTOTAL_A; |
||
541 | u32 saveTRANS_HBLANK_A; |
||
542 | u32 saveTRANS_HSYNC_A; |
||
543 | u32 saveTRANS_VTOTAL_A; |
||
544 | u32 saveTRANS_VBLANK_A; |
||
545 | u32 saveTRANS_VSYNC_A; |
||
546 | u32 savePIPEASTAT; |
||
547 | u32 saveDSPASTRIDE; |
||
548 | u32 saveDSPASIZE; |
||
549 | u32 saveDSPAPOS; |
||
550 | u32 saveDSPAADDR; |
||
551 | u32 saveDSPASURF; |
||
552 | u32 saveDSPATILEOFF; |
||
553 | u32 savePFIT_PGM_RATIOS; |
||
554 | u32 saveBLC_HIST_CTL; |
||
555 | u32 saveBLC_PWM_CTL; |
||
556 | u32 saveBLC_PWM_CTL2; |
||
557 | u32 saveBLC_CPU_PWM_CTL; |
||
558 | u32 saveBLC_CPU_PWM_CTL2; |
||
559 | u32 saveFPB0; |
||
560 | u32 saveFPB1; |
||
561 | u32 saveDPLL_B; |
||
562 | u32 saveDPLL_B_MD; |
||
563 | u32 saveHTOTAL_B; |
||
564 | u32 saveHBLANK_B; |
||
565 | u32 saveHSYNC_B; |
||
566 | u32 saveVTOTAL_B; |
||
567 | u32 saveVBLANK_B; |
||
568 | u32 saveVSYNC_B; |
||
569 | u32 saveBCLRPAT_B; |
||
570 | u32 saveTRANSBCONF; |
||
571 | u32 saveTRANS_HTOTAL_B; |
||
572 | u32 saveTRANS_HBLANK_B; |
||
573 | u32 saveTRANS_HSYNC_B; |
||
574 | u32 saveTRANS_VTOTAL_B; |
||
575 | u32 saveTRANS_VBLANK_B; |
||
576 | u32 saveTRANS_VSYNC_B; |
||
577 | u32 savePIPEBSTAT; |
||
578 | u32 saveDSPBSTRIDE; |
||
579 | u32 saveDSPBSIZE; |
||
580 | u32 saveDSPBPOS; |
||
581 | u32 saveDSPBADDR; |
||
582 | u32 saveDSPBSURF; |
||
583 | u32 saveDSPBTILEOFF; |
||
584 | u32 saveVGA0; |
||
585 | u32 saveVGA1; |
||
586 | u32 saveVGA_PD; |
||
587 | u32 saveVGACNTRL; |
||
588 | u32 saveADPA; |
||
589 | u32 saveLVDS; |
||
590 | u32 savePP_ON_DELAYS; |
||
591 | u32 savePP_OFF_DELAYS; |
||
592 | u32 saveDVOA; |
||
593 | u32 saveDVOB; |
||
594 | u32 saveDVOC; |
||
595 | u32 savePP_ON; |
||
596 | u32 savePP_OFF; |
||
597 | u32 savePP_CONTROL; |
||
598 | u32 savePP_DIVISOR; |
||
599 | u32 savePFIT_CONTROL; |
||
600 | u32 save_palette_a[256]; |
||
601 | u32 save_palette_b[256]; |
||
602 | u32 saveDPFC_CB_BASE; |
||
603 | u32 saveFBC_CFB_BASE; |
||
604 | u32 saveFBC_LL_BASE; |
||
605 | u32 saveFBC_CONTROL; |
||
606 | u32 saveFBC_CONTROL2; |
||
607 | u32 saveIER; |
||
608 | u32 saveIIR; |
||
609 | u32 saveIMR; |
||
610 | u32 saveDEIER; |
||
611 | u32 saveDEIMR; |
||
612 | u32 saveGTIER; |
||
613 | u32 saveGTIMR; |
||
614 | u32 saveFDI_RXA_IMR; |
||
615 | u32 saveFDI_RXB_IMR; |
||
616 | u32 saveCACHE_MODE_0; |
||
617 | u32 saveMI_ARB_STATE; |
||
618 | u32 saveSWF0[16]; |
||
619 | u32 saveSWF1[16]; |
||
620 | u32 saveSWF2[3]; |
||
621 | u8 saveMSR; |
||
622 | u8 saveSR[8]; |
||
623 | u8 saveGR[25]; |
||
624 | u8 saveAR_INDEX; |
||
625 | u8 saveAR[21]; |
||
626 | u8 saveDACMASK; |
||
627 | u8 saveCR[37]; |
||
2342 | Serge | 628 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
2325 | Serge | 629 | u32 saveCURACNTR; |
630 | u32 saveCURAPOS; |
||
631 | u32 saveCURABASE; |
||
632 | u32 saveCURBCNTR; |
||
633 | u32 saveCURBPOS; |
||
634 | u32 saveCURBBASE; |
||
635 | u32 saveCURSIZE; |
||
636 | u32 saveDP_B; |
||
637 | u32 saveDP_C; |
||
638 | u32 saveDP_D; |
||
639 | u32 savePIPEA_GMCH_DATA_M; |
||
640 | u32 savePIPEB_GMCH_DATA_M; |
||
641 | u32 savePIPEA_GMCH_DATA_N; |
||
642 | u32 savePIPEB_GMCH_DATA_N; |
||
643 | u32 savePIPEA_DP_LINK_M; |
||
644 | u32 savePIPEB_DP_LINK_M; |
||
645 | u32 savePIPEA_DP_LINK_N; |
||
646 | u32 savePIPEB_DP_LINK_N; |
||
647 | u32 saveFDI_RXA_CTL; |
||
648 | u32 saveFDI_TXA_CTL; |
||
649 | u32 saveFDI_RXB_CTL; |
||
650 | u32 saveFDI_TXB_CTL; |
||
651 | u32 savePFA_CTL_1; |
||
652 | u32 savePFB_CTL_1; |
||
653 | u32 savePFA_WIN_SZ; |
||
654 | u32 savePFB_WIN_SZ; |
||
655 | u32 savePFA_WIN_POS; |
||
656 | u32 savePFB_WIN_POS; |
||
657 | u32 savePCH_DREF_CONTROL; |
||
658 | u32 saveDISP_ARB_CTL; |
||
659 | u32 savePIPEA_DATA_M1; |
||
660 | u32 savePIPEA_DATA_N1; |
||
661 | u32 savePIPEA_LINK_M1; |
||
662 | u32 savePIPEA_LINK_N1; |
||
663 | u32 savePIPEB_DATA_M1; |
||
664 | u32 savePIPEB_DATA_N1; |
||
665 | u32 savePIPEB_LINK_M1; |
||
666 | u32 savePIPEB_LINK_N1; |
||
667 | u32 saveMCHBAR_RENDER_STANDBY; |
||
668 | u32 savePCH_PORT_HOTPLUG; |
||
3243 | Serge | 669 | }; |
2325 | Serge | 670 | |
3243 | Serge | 671 | struct intel_gen6_power_mgmt { |
672 | struct work_struct work; |
||
673 | u32 pm_iir; |
||
674 | /* lock - irqsave spinlock that protectects the work_struct and |
||
675 | * pm_iir. */ |
||
676 | spinlock_t lock; |
||
677 | |||
678 | /* The below variables an all the rps hw state are protected by |
||
679 | * dev->struct mutext. */ |
||
680 | u8 cur_delay; |
||
681 | u8 min_delay; |
||
682 | u8 max_delay; |
||
3746 | Serge | 683 | u8 hw_max; |
3243 | Serge | 684 | |
685 | struct delayed_work delayed_resume_work; |
||
686 | |||
687 | /* |
||
688 | * Protects RPS/RC6 register access and PCU communication. |
||
689 | * Must be taken after struct_mutex if nested. |
||
690 | */ |
||
691 | struct mutex hw_lock; |
||
692 | }; |
||
693 | |||
3480 | Serge | 694 | /* defined intel_pm.c */ |
695 | extern spinlock_t mchdev_lock; |
||
696 | |||
3243 | Serge | 697 | struct intel_ilk_power_mgmt { |
698 | u8 cur_delay; |
||
699 | u8 min_delay; |
||
700 | u8 max_delay; |
||
701 | u8 fmax; |
||
702 | u8 fstart; |
||
703 | |||
704 | u64 last_count1; |
||
705 | unsigned long last_time1; |
||
706 | unsigned long chipset_power; |
||
707 | u64 last_count2; |
||
708 | struct timespec last_time2; |
||
709 | unsigned long gfx_power; |
||
710 | u8 corr; |
||
711 | |||
712 | int c_m; |
||
713 | int r_t; |
||
714 | |||
715 | struct drm_i915_gem_object *pwrctx; |
||
716 | struct drm_i915_gem_object *renderctx; |
||
717 | }; |
||
718 | |||
719 | struct i915_dri1_state { |
||
720 | unsigned allow_batchbuffer : 1; |
||
721 | u32 __iomem *gfx_hws_cpu_addr; |
||
722 | |||
723 | unsigned int cpp; |
||
724 | int back_offset; |
||
725 | int front_offset; |
||
726 | int current_page; |
||
727 | int page_flipping; |
||
728 | |||
729 | uint32_t counter; |
||
730 | }; |
||
731 | |||
732 | struct intel_l3_parity { |
||
733 | u32 *remap_info; |
||
734 | struct work_struct error_work; |
||
735 | }; |
||
736 | |||
3480 | Serge | 737 | struct i915_gem_mm { |
738 | /** Memory allocator for GTT stolen memory */ |
||
739 | struct drm_mm stolen; |
||
740 | /** Memory allocator for GTT */ |
||
741 | struct drm_mm gtt_space; |
||
742 | /** List of all objects in gtt_space. Used to restore gtt |
||
743 | * mappings on resume */ |
||
744 | struct list_head bound_list; |
||
745 | /** |
||
746 | * List of objects which are not bound to the GTT (thus |
||
747 | * are idle and not used by the GPU) but still have |
||
748 | * (presumably uncached) pages still attached. |
||
749 | */ |
||
750 | struct list_head unbound_list; |
||
751 | |||
752 | /** Usable portion of the GTT for GEM */ |
||
753 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
||
754 | |||
755 | int gtt_mtrr; |
||
756 | |||
757 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
||
758 | struct i915_hw_ppgtt *aliasing_ppgtt; |
||
759 | |||
760 | bool shrinker_no_lock_stealing; |
||
761 | |||
762 | /** |
||
763 | * List of objects currently involved in rendering. |
||
764 | * |
||
765 | * Includes buffers having the contents of their GPU caches |
||
766 | * flushed, not necessarily primitives. last_rendering_seqno |
||
767 | * represents when the rendering involved will be completed. |
||
768 | * |
||
769 | * A reference is held on the buffer while on this list. |
||
770 | */ |
||
771 | struct list_head active_list; |
||
772 | |||
773 | /** |
||
774 | * LRU list of objects which are not in the ringbuffer and |
||
775 | * are ready to unbind, but are still in the GTT. |
||
776 | * |
||
777 | * last_rendering_seqno is 0 while an object is in this list. |
||
778 | * |
||
779 | * A reference is not held on the buffer while on this list, |
||
780 | * as merely being GTT-bound shouldn't prevent its being |
||
781 | * freed, and we'll pull it off the list in the free path. |
||
782 | */ |
||
783 | struct list_head inactive_list; |
||
784 | |||
785 | /** LRU list of objects with fence regs on them. */ |
||
786 | struct list_head fence_list; |
||
787 | |||
788 | /** |
||
789 | * We leave the user IRQ off as much as possible, |
||
790 | * but this means that requests will finish and never |
||
791 | * be retired once the system goes idle. Set a timer to |
||
792 | * fire periodically while the ring is running. When it |
||
793 | * fires, go retire requests. |
||
794 | */ |
||
795 | struct delayed_work retire_work; |
||
796 | |||
797 | /** |
||
798 | * Are we in a non-interruptible section of code like |
||
799 | * modesetting? |
||
800 | */ |
||
801 | bool interruptible; |
||
802 | |||
803 | /** |
||
804 | * Flag if the X Server, and thus DRM, is not currently in |
||
805 | * control of the device. |
||
806 | * |
||
807 | * This is set between LeaveVT and EnterVT. It needs to be |
||
808 | * replaced with a semaphore. It also needs to be |
||
809 | * transitioned away from for kernel modesetting. |
||
810 | */ |
||
811 | int suspended; |
||
812 | |||
813 | /** Bit 6 swizzling required for X tiling */ |
||
814 | uint32_t bit_6_swizzle_x; |
||
815 | /** Bit 6 swizzling required for Y tiling */ |
||
816 | uint32_t bit_6_swizzle_y; |
||
817 | |||
818 | /* storage for physical objects */ |
||
819 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
||
820 | |||
821 | /* accounting, useful for userland debugging */ |
||
822 | size_t object_memory; |
||
823 | u32 object_count; |
||
824 | }; |
||
825 | |||
826 | struct i915_gpu_error { |
||
827 | /* For hangcheck timer */ |
||
828 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
||
829 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
||
830 | struct timer_list hangcheck_timer; |
||
831 | int hangcheck_count; |
||
832 | uint32_t last_acthd[I915_NUM_RINGS]; |
||
833 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; |
||
834 | |||
835 | /* For reset and error_state handling. */ |
||
836 | spinlock_t lock; |
||
837 | /* Protected by the above dev->gpu_error.lock. */ |
||
838 | struct drm_i915_error_state *first_error; |
||
839 | struct work_struct work; |
||
840 | |||
841 | unsigned long last_reset; |
||
842 | |||
843 | /** |
||
844 | * State variable and reset counter controlling the reset flow |
||
845 | * |
||
846 | * Upper bits are for the reset counter. This counter is used by the |
||
847 | * wait_seqno code to race-free noticed that a reset event happened and |
||
848 | * that it needs to restart the entire ioctl (since most likely the |
||
849 | * seqno it waited for won't ever signal anytime soon). |
||
850 | * |
||
851 | * This is important for lock-free wait paths, where no contended lock |
||
852 | * naturally enforces the correct ordering between the bail-out of the |
||
853 | * waiter and the gpu reset work code. |
||
854 | * |
||
855 | * Lowest bit controls the reset state machine: Set means a reset is in |
||
856 | * progress. This state will (presuming we don't have any bugs) decay |
||
857 | * into either unset (successful reset) or the special WEDGED value (hw |
||
858 | * terminally sour). All waiters on the reset_queue will be woken when |
||
859 | * that happens. |
||
860 | */ |
||
861 | atomic_t reset_counter; |
||
862 | |||
863 | /** |
||
864 | * Special values/flags for reset_counter |
||
865 | * |
||
866 | * Note that the code relies on |
||
867 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG |
||
868 | * being true. |
||
869 | */ |
||
870 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
||
871 | #define I915_WEDGED 0xffffffff |
||
872 | |||
873 | /** |
||
874 | * Waitqueue to signal when the reset has completed. Used by clients |
||
875 | * that wait for dev_priv->mm.wedged to settle. |
||
876 | */ |
||
877 | wait_queue_head_t reset_queue; |
||
878 | |||
879 | /* For gpu hang simulation. */ |
||
880 | unsigned int stop_rings; |
||
881 | }; |
||
882 | |||
883 | enum modeset_restore { |
||
884 | MODESET_ON_LID_OPEN, |
||
885 | MODESET_DONE, |
||
886 | MODESET_SUSPENDED, |
||
887 | }; |
||
888 | |||
3243 | Serge | 889 | typedef struct drm_i915_private { |
890 | struct drm_device *dev; |
||
891 | |||
892 | const struct intel_device_info *info; |
||
893 | |||
894 | int relative_constants_mode; |
||
895 | |||
896 | void __iomem *regs; |
||
897 | |||
898 | struct drm_i915_gt_funcs gt; |
||
899 | /** gt_fifo_count and the subsequent register write are synchronized |
||
900 | * with dev->struct_mutex. */ |
||
901 | unsigned gt_fifo_count; |
||
902 | /** forcewake_count is protected by gt_lock */ |
||
903 | unsigned forcewake_count; |
||
904 | /** gt_lock is also taken in irq contexts. */ |
||
3480 | Serge | 905 | spinlock_t gt_lock; |
3243 | Serge | 906 | |
907 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
||
908 | |||
3480 | Serge | 909 | |
3243 | Serge | 910 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
911 | * controller on different i2c buses. */ |
||
912 | struct mutex gmbus_mutex; |
||
913 | |||
914 | /** |
||
915 | * Base address of the gmbus and gpio block. |
||
916 | */ |
||
917 | uint32_t gpio_mmio_base; |
||
918 | |||
3480 | Serge | 919 | wait_queue_head_t gmbus_wait_queue; |
920 | |||
3243 | Serge | 921 | struct pci_dev *bridge_dev; |
922 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
||
3480 | Serge | 923 | uint32_t last_seqno, next_seqno; |
3243 | Serge | 924 | |
925 | drm_dma_handle_t *status_page_dmah; |
||
926 | struct resource mch_res; |
||
927 | |||
928 | atomic_t irq_received; |
||
929 | |||
930 | /* protects the irq masks */ |
||
931 | spinlock_t irq_lock; |
||
932 | |||
3480 | Serge | 933 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
934 | // struct pm_qos_request pm_qos; |
||
935 | |||
3243 | Serge | 936 | /* DPIO indirect register protection */ |
3480 | Serge | 937 | struct mutex dpio_lock; |
3243 | Serge | 938 | |
939 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
||
940 | u32 irq_mask; |
||
941 | u32 gt_irq_mask; |
||
942 | |||
943 | struct work_struct hotplug_work; |
||
3480 | Serge | 944 | bool enable_hotplug_processing; |
3746 | Serge | 945 | struct { |
946 | unsigned long hpd_last_jiffies; |
||
947 | int hpd_cnt; |
||
948 | enum { |
||
949 | HPD_ENABLED = 0, |
||
950 | HPD_DISABLED = 1, |
||
951 | HPD_MARK_DISABLED = 2 |
||
952 | } hpd_mark; |
||
953 | } hpd_stats[HPD_NUM_PINS]; |
||
3243 | Serge | 954 | |
955 | int num_pch_pll; |
||
3746 | Serge | 956 | int num_plane; |
3243 | Serge | 957 | |
958 | unsigned long cfb_size; |
||
959 | unsigned int cfb_fb; |
||
960 | enum plane cfb_plane; |
||
961 | int cfb_y; |
||
962 | struct intel_fbc_work *fbc_work; |
||
963 | |||
964 | struct intel_opregion opregion; |
||
965 | |||
966 | /* overlay */ |
||
967 | struct intel_overlay *overlay; |
||
3480 | Serge | 968 | unsigned int sprite_scaling_enabled; |
3243 | Serge | 969 | |
3746 | Serge | 970 | /* backlight */ |
971 | struct { |
||
972 | int level; |
||
973 | bool enabled; |
||
974 | struct backlight_device *device; |
||
975 | } backlight; |
||
976 | |||
3243 | Serge | 977 | /* LVDS info */ |
978 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
||
979 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
||
980 | |||
981 | /* Feature bits from the VBIOS */ |
||
982 | unsigned int int_tv_support:1; |
||
983 | unsigned int lvds_dither:1; |
||
984 | unsigned int lvds_vbt:1; |
||
985 | unsigned int int_crt_support:1; |
||
986 | unsigned int lvds_use_ssc:1; |
||
987 | unsigned int display_clock_mode:1; |
||
3746 | Serge | 988 | unsigned int fdi_rx_polarity_inverted:1; |
3243 | Serge | 989 | int lvds_ssc_freq; |
990 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
||
2325 | Serge | 991 | struct { |
3243 | Serge | 992 | int rate; |
993 | int lanes; |
||
994 | int preemphasis; |
||
995 | int vswing; |
||
996 | |||
997 | bool initialized; |
||
998 | bool support; |
||
999 | int bpp; |
||
1000 | struct edp_power_seq pps; |
||
1001 | } edp; |
||
1002 | bool no_aux_handshake; |
||
1003 | |||
1004 | int crt_ddc_pin; |
||
1005 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
||
1006 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
||
1007 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
||
1008 | |||
1009 | unsigned int fsb_freq, mem_freq, is_ddr3; |
||
1010 | |||
1011 | struct workqueue_struct *wq; |
||
1012 | |||
1013 | /* Display functions */ |
||
1014 | struct drm_i915_display_funcs display; |
||
1015 | |||
1016 | /* PCH chipset type */ |
||
1017 | enum intel_pch pch_type; |
||
1018 | unsigned short pch_id; |
||
1019 | |||
1020 | unsigned long quirks; |
||
1021 | |||
3480 | Serge | 1022 | enum modeset_restore modeset_restore; |
1023 | struct mutex modeset_restore_lock; |
||
3243 | Serge | 1024 | |
3480 | Serge | 1025 | struct i915_gtt gtt; |
2325 | Serge | 1026 | |
3480 | Serge | 1027 | struct i915_gem_mm mm; |
2325 | Serge | 1028 | |
3031 | serge | 1029 | /* Kernel Modesetting */ |
1030 | |||
2327 | Serge | 1031 | struct sdvo_device_mapping sdvo_mappings[2]; |
2325 | Serge | 1032 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
1033 | unsigned int lvds_border_bits; |
||
1034 | /* Panel fitter placement and size for Ironlake+ */ |
||
1035 | u32 pch_pf_pos, pch_pf_size; |
||
1036 | |||
2342 | Serge | 1037 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1038 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
||
2352 | Serge | 1039 | wait_queue_head_t pending_flip_queue; |
2325 | Serge | 1040 | |
3031 | serge | 1041 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
3243 | Serge | 1042 | struct intel_ddi_plls ddi_plls; |
3031 | serge | 1043 | |
2325 | Serge | 1044 | /* Reclocking support */ |
1045 | bool render_reclock_avail; |
||
1046 | bool lvds_downclock_avail; |
||
1047 | /* indicates the reduced downclock for LVDS*/ |
||
1048 | int lvds_downclock; |
||
1049 | u16 orig_clock; |
||
1050 | int child_dev_num; |
||
2327 | Serge | 1051 | struct child_device_config *child_dev; |
2325 | Serge | 1052 | |
1053 | bool mchbar_need_disable; |
||
1054 | |||
3243 | Serge | 1055 | struct intel_l3_parity l3_parity; |
1056 | |||
3031 | serge | 1057 | /* gen6+ rps state */ |
3243 | Serge | 1058 | struct intel_gen6_power_mgmt rps; |
2325 | Serge | 1059 | |
3031 | serge | 1060 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1061 | * mchdev_lock in intel_pm.c */ |
||
3243 | Serge | 1062 | struct intel_ilk_power_mgmt ips; |
2325 | Serge | 1063 | |
2336 | Serge | 1064 | enum no_fbc_reason no_fbc_reason; |
2325 | Serge | 1065 | |
3031 | serge | 1066 | struct drm_mm_node *compressed_fb; |
1067 | struct drm_mm_node *compressed_llb; |
||
2325 | Serge | 1068 | |
3480 | Serge | 1069 | struct i915_gpu_error gpu_error; |
2325 | Serge | 1070 | |
1071 | /* list of fbdev register on this device */ |
||
2332 | Serge | 1072 | struct intel_fbdev *fbdev; |
2325 | Serge | 1073 | |
3243 | Serge | 1074 | /* |
1075 | * The console may be contended at resume, but we don't |
||
1076 | * want it to block on it. |
||
1077 | */ |
||
1078 | struct work_struct console_resume_work; |
||
1079 | |||
3031 | serge | 1080 | struct drm_property *broadcast_rgb_property; |
1081 | struct drm_property *force_audio_property; |
||
1082 | |||
1083 | bool hw_contexts_disabled; |
||
1084 | uint32_t hw_context_size; |
||
3243 | Serge | 1085 | |
3480 | Serge | 1086 | u32 fdi_rx_config; |
3243 | Serge | 1087 | |
1088 | struct i915_suspend_saved_registers regfile; |
||
1089 | |||
1090 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
||
1091 | * here! */ |
||
1092 | struct i915_dri1_state dri1; |
||
2325 | Serge | 1093 | } drm_i915_private_t; |
1094 | |||
3031 | serge | 1095 | /* Iterate over initialised rings */ |
1096 | #define for_each_ring(ring__, dev_priv__, i__) \ |
||
1097 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
||
1098 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
||
1099 | |||
1100 | enum hdmi_force_audio { |
||
1101 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
||
1102 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
||
1103 | HDMI_AUDIO_AUTO, /* trust EDID */ |
||
1104 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
||
1105 | }; |
||
1106 | |||
3480 | Serge | 1107 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
2325 | Serge | 1108 | |
3031 | serge | 1109 | struct drm_i915_gem_object_ops { |
1110 | /* Interface between the GEM object and its backing storage. |
||
1111 | * get_pages() is called once prior to the use of the associated set |
||
1112 | * of pages before to binding them into the GTT, and put_pages() is |
||
1113 | * called after we no longer need them. As we expect there to be |
||
1114 | * associated cost with migrating pages between the backing storage |
||
1115 | * and making them available for the GPU (e.g. clflush), we may hold |
||
1116 | * onto the pages after they are no longer referenced by the GPU |
||
1117 | * in case they may be used again shortly (for example migrating the |
||
1118 | * pages to a different memory domain within the GTT). put_pages() |
||
1119 | * will therefore most likely be called when the object itself is |
||
1120 | * being released or under memory pressure (where we attempt to |
||
1121 | * reap pages for the shrinker). |
||
1122 | */ |
||
1123 | int (*get_pages)(struct drm_i915_gem_object *); |
||
1124 | void (*put_pages)(struct drm_i915_gem_object *); |
||
1125 | }; |
||
1126 | |||
2327 | Serge | 1127 | struct drm_i915_gem_object { |
1128 | struct drm_gem_object base; |
||
2325 | Serge | 1129 | |
3031 | serge | 1130 | const struct drm_i915_gem_object_ops *ops; |
1131 | |||
2327 | Serge | 1132 | /** Current space allocated to this object in the GTT, if any. */ |
1133 | struct drm_mm_node *gtt_space; |
||
3480 | Serge | 1134 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1135 | struct drm_mm_node *stolen; |
||
2327 | Serge | 1136 | struct list_head gtt_list; |
1137 | |||
3031 | serge | 1138 | /** This object's place on the active/inactive lists */ |
2327 | Serge | 1139 | struct list_head ring_list; |
1140 | struct list_head mm_list; |
||
1141 | /** This object's place in the batchbuffer or on the eviction list */ |
||
1142 | struct list_head exec_list; |
||
1143 | |||
1144 | /** |
||
3031 | serge | 1145 | * This is set if the object is on the active lists (has pending |
1146 | * rendering and so a non-zero seqno), and is not set if it i s on |
||
1147 | * inactive (ready to be unbound) list. |
||
2327 | Serge | 1148 | */ |
2342 | Serge | 1149 | unsigned int active:1; |
2327 | Serge | 1150 | |
1151 | /** |
||
1152 | * This is set if the object has been written to since last bound |
||
1153 | * to the GTT |
||
1154 | */ |
||
2342 | Serge | 1155 | unsigned int dirty:1; |
2327 | Serge | 1156 | |
1157 | /** |
||
1158 | * Fence register bits (if any) for this object. Will be set |
||
1159 | * as needed when mapped into the GTT. |
||
1160 | * Protected by dev->struct_mutex. |
||
1161 | */ |
||
2342 | Serge | 1162 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
2327 | Serge | 1163 | |
1164 | /** |
||
1165 | * Advice: are the backing pages purgeable? |
||
1166 | */ |
||
2342 | Serge | 1167 | unsigned int madv:2; |
2327 | Serge | 1168 | |
1169 | /** |
||
1170 | * Current tiling mode for the object. |
||
1171 | */ |
||
2342 | Serge | 1172 | unsigned int tiling_mode:2; |
3031 | serge | 1173 | /** |
1174 | * Whether the tiling parameters for the currently associated fence |
||
1175 | * register have changed. Note that for the purposes of tracking |
||
1176 | * tiling changes we also treat the unfenced register, the register |
||
1177 | * slot that the object occupies whilst it executes a fenced |
||
1178 | * command (such as BLT on gen2/3), as a "fence". |
||
1179 | */ |
||
1180 | unsigned int fence_dirty:1; |
||
2327 | Serge | 1181 | |
1182 | /** How many users have pinned this object in GTT space. The following |
||
1183 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
||
1184 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
||
1185 | * times for the same batchbuffer), and the framebuffer code. When |
||
1186 | * switching/pageflipping, the framebuffer code has at most two buffers |
||
1187 | * pinned per crtc. |
||
1188 | * |
||
1189 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
||
1190 | * bits with absolutely no headroom. So use 4 bits. */ |
||
2342 | Serge | 1191 | unsigned int pin_count:4; |
2327 | Serge | 1192 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
1193 | |||
1194 | /** |
||
1195 | * Is the object at the current location in the gtt mappable and |
||
1196 | * fenceable? Used to avoid costly recalculations. |
||
1197 | */ |
||
2342 | Serge | 1198 | unsigned int map_and_fenceable:1; |
2327 | Serge | 1199 | |
1200 | /** |
||
1201 | * Whether the current gtt mapping needs to be mappable (and isn't just |
||
1202 | * mappable by accident). Track pin and fault separate for a more |
||
1203 | * accurate mappable working set. |
||
1204 | */ |
||
2342 | Serge | 1205 | unsigned int fault_mappable:1; |
1206 | unsigned int pin_mappable:1; |
||
2327 | Serge | 1207 | |
1208 | /* |
||
1209 | * Is the GPU currently using a fence to access this buffer, |
||
1210 | */ |
||
1211 | unsigned int pending_fenced_gpu_access:1; |
||
1212 | unsigned int fenced_gpu_access:1; |
||
1213 | |||
1214 | unsigned int cache_level:2; |
||
1215 | |||
3031 | serge | 1216 | unsigned int has_aliasing_ppgtt_mapping:1; |
1217 | unsigned int has_global_gtt_mapping:1; |
||
1218 | unsigned int has_dma_mapping:1; |
||
2327 | Serge | 1219 | |
3243 | Serge | 1220 | struct sg_table *pages; |
3031 | serge | 1221 | int pages_pin_count; |
2327 | Serge | 1222 | |
3031 | serge | 1223 | /* prime dma-buf support */ |
1224 | void *dma_buf_vmapping; |
||
1225 | int vmapping_count; |
||
1226 | |||
2327 | Serge | 1227 | /** |
1228 | * Used for performing relocations during execbuffer insertion. |
||
1229 | */ |
||
1230 | struct hlist_node exec_node; |
||
1231 | unsigned long exec_handle; |
||
1232 | struct drm_i915_gem_exec_object2 *exec_entry; |
||
1233 | |||
1234 | /** |
||
1235 | * Current offset of the object in GTT space. |
||
1236 | * |
||
1237 | * This is the same as gtt_space->start |
||
1238 | */ |
||
1239 | uint32_t gtt_offset; |
||
1240 | |||
3031 | serge | 1241 | struct intel_ring_buffer *ring; |
1242 | |||
2327 | Serge | 1243 | /** Breadcrumb of last rendering to the buffer. */ |
3031 | serge | 1244 | uint32_t last_read_seqno; |
1245 | uint32_t last_write_seqno; |
||
2327 | Serge | 1246 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1247 | uint32_t last_fenced_seqno; |
||
1248 | |||
1249 | /** Current tiling stride for the object, if it's tiled. */ |
||
1250 | uint32_t stride; |
||
1251 | |||
1252 | /** Record of address bit 17 of each page at last unbind. */ |
||
1253 | unsigned long *bit_17; |
||
1254 | |||
1255 | /** User space pin count and filp owning the pin */ |
||
1256 | uint32_t user_pin_count; |
||
1257 | struct drm_file *pin_filp; |
||
1258 | |||
1259 | /** for phy allocated objects */ |
||
1260 | struct drm_i915_gem_phys_object *phys_obj; |
||
1261 | }; |
||
3243 | Serge | 1262 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
2327 | Serge | 1263 | |
2325 | Serge | 1264 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
1265 | |||
1266 | /** |
||
1267 | * Request queue structure. |
||
1268 | * |
||
1269 | * The request queue allows us to note sequence numbers that have been emitted |
||
1270 | * and may be associated with active buffers to be retired. |
||
1271 | * |
||
1272 | * By keeping this list, we can avoid having to do questionable |
||
1273 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
||
1274 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
||
1275 | */ |
||
1276 | struct drm_i915_gem_request { |
||
1277 | /** On Which ring this request was generated */ |
||
1278 | struct intel_ring_buffer *ring; |
||
1279 | |||
1280 | /** GEM sequence number associated with this request. */ |
||
1281 | uint32_t seqno; |
||
1282 | |||
3031 | serge | 1283 | /** Postion in the ringbuffer of the end of the request */ |
1284 | u32 tail; |
||
1285 | |||
2325 | Serge | 1286 | /** Time at which this request was emitted, in jiffies. */ |
1287 | unsigned long emitted_jiffies; |
||
1288 | |||
1289 | /** global list entry for this request */ |
||
1290 | struct list_head list; |
||
1291 | |||
1292 | struct drm_i915_file_private *file_priv; |
||
1293 | /** file_priv list entry for this request */ |
||
1294 | struct list_head client_list; |
||
1295 | }; |
||
1296 | |||
1297 | struct drm_i915_file_private { |
||
1298 | struct { |
||
3480 | Serge | 1299 | spinlock_t lock; |
2325 | Serge | 1300 | struct list_head request_list; |
1301 | } mm; |
||
3031 | serge | 1302 | struct idr context_idr; |
2325 | Serge | 1303 | }; |
1304 | |||
1305 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
||
1306 | |||
1307 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
||
1308 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
||
1309 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
||
1310 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
||
1311 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
||
1312 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
||
1313 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
||
1314 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
||
1315 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
||
1316 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
||
1317 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
||
1318 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
||
1319 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
||
1320 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
||
1321 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
||
1322 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
||
1323 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
||
1324 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
||
1325 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
||
3243 | Serge | 1326 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1327 | (dev)->pci_device == 0x0152 || \ |
||
1328 | (dev)->pci_device == 0x015a) |
||
1329 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
||
1330 | (dev)->pci_device == 0x0106 || \ |
||
1331 | (dev)->pci_device == 0x010A) |
||
3031 | serge | 1332 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
1333 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
||
2325 | Serge | 1334 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
3243 | Serge | 1335 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1336 | ((dev)->pci_device & 0xFF00) == 0x0A00) |
||
2325 | Serge | 1337 | |
1338 | /* |
||
1339 | * The genX designation typically refers to the render engine, so render |
||
1340 | * capability related checks should use IS_GEN, while display and other checks |
||
1341 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
||
1342 | * chips, etc.). |
||
1343 | */ |
||
1344 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
||
1345 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
||
1346 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
||
1347 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
||
1348 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
||
1349 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
||
1350 | |||
1351 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
||
1352 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
||
3031 | serge | 1353 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
2325 | Serge | 1354 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1355 | |||
3031 | serge | 1356 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
1357 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
||
1358 | |||
2325 | Serge | 1359 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
1360 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
||
1361 | |||
3243 | Serge | 1362 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1363 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
||
1364 | |||
2325 | Serge | 1365 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1366 | * rows, which changed the alignment requirements and fence programming. |
||
1367 | */ |
||
1368 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
||
1369 | IS_I915GM(dev))) |
||
1370 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
||
1371 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1372 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
||
1373 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
||
1374 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
||
1375 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
||
1376 | /* dsparb controlled by hw only */ |
||
1377 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
||
1378 | |||
1379 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
||
1380 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
||
1381 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
||
1382 | |||
1383 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
||
1384 | |||
3480 | Serge | 1385 | #define HAS_DDI(dev) (IS_HASWELL(dev)) |
3746 | Serge | 1386 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
3480 | Serge | 1387 | |
3243 | Serge | 1388 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1389 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
||
1390 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
||
1391 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
||
1392 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
||
1393 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
||
1394 | |||
2325 | Serge | 1395 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
3031 | serge | 1396 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2325 | Serge | 1397 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1398 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
||
3746 | Serge | 1399 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
3031 | serge | 1400 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2325 | Serge | 1401 | |
3031 | serge | 1402 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
2325 | Serge | 1403 | |
3031 | serge | 1404 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
2325 | Serge | 1405 | |
3031 | serge | 1406 | #define GT_FREQUENCY_MULTIPLIER 50 |
1407 | |||
1408 | #include "i915_trace.h" |
||
1409 | |||
1410 | /** |
||
1411 | * RC6 is a special power stage which allows the GPU to enter an very |
||
1412 | * low-voltage mode when idle, using down to 0V while at this stage. This |
||
1413 | * stage is entered automatically when the GPU is idle when RC6 support is |
||
1414 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
||
1415 | * |
||
1416 | * There are different RC6 modes available in Intel GPU, which differentiate |
||
1417 | * among each other with the latency required to enter and leave RC6 and |
||
1418 | * voltage consumed by the GPU in different states. |
||
1419 | * |
||
1420 | * The combination of the following flags define which states GPU is allowed |
||
1421 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
||
1422 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
||
1423 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
||
1424 | * which brings the most power savings; deeper states save more power, but |
||
1425 | * require higher latency to switch to and wake up. |
||
1426 | */ |
||
1427 | #define INTEL_RC6_ENABLE (1<<0) |
||
1428 | #define INTEL_RC6p_ENABLE (1<<1) |
||
1429 | #define INTEL_RC6pp_ENABLE (1<<2) |
||
1430 | |||
1431 | extern unsigned int i915_fbpercrtc __always_unused; |
||
1432 | extern int i915_panel_ignore_lid __read_mostly; |
||
1433 | extern unsigned int i915_powersave __read_mostly; |
||
1434 | extern int i915_semaphores __read_mostly; |
||
1435 | extern unsigned int i915_lvds_downclock __read_mostly; |
||
1436 | extern int i915_lvds_channel_mode __read_mostly; |
||
1437 | extern int i915_panel_use_ssc __read_mostly; |
||
1438 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
||
1439 | extern int i915_enable_rc6 __read_mostly; |
||
1440 | extern int i915_enable_fbc __read_mostly; |
||
1441 | extern bool i915_enable_hangcheck __read_mostly; |
||
1442 | extern int i915_enable_ppgtt __read_mostly; |
||
1443 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
||
3480 | Serge | 1444 | extern int i915_disable_power_well __read_mostly; |
3031 | serge | 1445 | |
2325 | Serge | 1446 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1447 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
||
1448 | |||
1449 | /* i915_dma.c */ |
||
3031 | serge | 1450 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
2325 | Serge | 1451 | extern void i915_kernel_lost_context(struct drm_device * dev); |
1452 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
||
1453 | extern int i915_driver_unload(struct drm_device *); |
||
1454 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
||
1455 | extern void i915_driver_lastclose(struct drm_device * dev); |
||
1456 | extern void i915_driver_preclose(struct drm_device *dev, |
||
1457 | struct drm_file *file_priv); |
||
1458 | extern void i915_driver_postclose(struct drm_device *dev, |
||
1459 | struct drm_file *file_priv); |
||
1460 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
||
3031 | serge | 1461 | #ifdef CONFIG_COMPAT |
2325 | Serge | 1462 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1463 | unsigned long arg); |
||
3031 | serge | 1464 | #endif |
2325 | Serge | 1465 | extern int i915_emit_box(struct drm_device *dev, |
1466 | struct drm_clip_rect *box, |
||
1467 | int DR1, int DR4); |
||
3031 | serge | 1468 | extern int intel_gpu_reset(struct drm_device *dev); |
1469 | extern int i915_reset(struct drm_device *dev); |
||
2325 | Serge | 1470 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1471 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
||
1472 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
||
1473 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
||
1474 | |||
1475 | |||
1476 | /* i915_irq.c */ |
||
1477 | void i915_hangcheck_elapsed(unsigned long data); |
||
1478 | void i915_handle_error(struct drm_device *dev, bool wedged); |
||
1479 | |||
1480 | extern void intel_irq_init(struct drm_device *dev); |
||
3480 | Serge | 1481 | extern void intel_hpd_init(struct drm_device *dev); |
3031 | serge | 1482 | extern void intel_gt_init(struct drm_device *dev); |
3243 | Serge | 1483 | extern void intel_gt_reset(struct drm_device *dev); |
2325 | Serge | 1484 | |
3031 | serge | 1485 | void i915_error_state_free(struct kref *error_ref); |
2325 | Serge | 1486 | |
1487 | void |
||
1488 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
||
1489 | |||
1490 | void |
||
1491 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
||
1492 | |||
2342 | Serge | 1493 | void intel_enable_asle(struct drm_device *dev); |
2325 | Serge | 1494 | |
1495 | #ifdef CONFIG_DEBUG_FS |
||
1496 | extern void i915_destroy_error_state(struct drm_device *dev); |
||
1497 | #else |
||
1498 | #define i915_destroy_error_state(x) |
||
1499 | #endif |
||
1500 | |||
1501 | |||
1502 | /* i915_gem.c */ |
||
1503 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
||
1504 | struct drm_file *file_priv); |
||
1505 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
||
1506 | struct drm_file *file_priv); |
||
1507 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
||
1508 | struct drm_file *file_priv); |
||
1509 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
||
1510 | struct drm_file *file_priv); |
||
1511 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
||
1512 | struct drm_file *file_priv); |
||
1513 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
||
1514 | struct drm_file *file_priv); |
||
1515 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
||
1516 | struct drm_file *file_priv); |
||
1517 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
||
1518 | struct drm_file *file_priv); |
||
1519 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
||
1520 | struct drm_file *file_priv); |
||
1521 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
||
1522 | struct drm_file *file_priv); |
||
1523 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
||
1524 | struct drm_file *file_priv); |
||
1525 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
||
1526 | struct drm_file *file_priv); |
||
1527 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
||
1528 | struct drm_file *file_priv); |
||
3031 | serge | 1529 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1530 | struct drm_file *file); |
||
1531 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
||
1532 | struct drm_file *file); |
||
2325 | Serge | 1533 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1534 | struct drm_file *file_priv); |
||
1535 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
||
1536 | struct drm_file *file_priv); |
||
1537 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
||
1538 | struct drm_file *file_priv); |
||
1539 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
||
1540 | struct drm_file *file_priv); |
||
1541 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
||
1542 | struct drm_file *file_priv); |
||
1543 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
||
1544 | struct drm_file *file_priv); |
||
1545 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
||
1546 | struct drm_file *file_priv); |
||
3031 | serge | 1547 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1548 | struct drm_file *file_priv); |
||
2325 | Serge | 1549 | void i915_gem_load(struct drm_device *dev); |
3480 | Serge | 1550 | void *i915_gem_object_alloc(struct drm_device *dev); |
1551 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
||
2325 | Serge | 1552 | int i915_gem_init_object(struct drm_gem_object *obj); |
3031 | serge | 1553 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1554 | const struct drm_i915_gem_object_ops *ops); |
||
2325 | Serge | 1555 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1556 | size_t size); |
||
1557 | void i915_gem_free_object(struct drm_gem_object *obj); |
||
3480 | Serge | 1558 | |
2325 | Serge | 1559 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1560 | uint32_t alignment, |
||
3031 | serge | 1561 | bool map_and_fenceable, |
1562 | bool nonblocking); |
||
2325 | Serge | 1563 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
1564 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
||
3480 | Serge | 1565 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
2325 | Serge | 1566 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
1567 | void i915_gem_lastclose(struct drm_device *dev); |
||
1568 | |||
3031 | serge | 1569 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3243 | Serge | 1570 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
3031 | serge | 1571 | { |
3746 | Serge | 1572 | struct sg_page_iter sg_iter; |
3031 | serge | 1573 | |
3746 | Serge | 1574 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
1575 | return sg_page_iter_page(&sg_iter); |
||
1576 | |||
1577 | return NULL; |
||
3243 | Serge | 1578 | } |
3031 | serge | 1579 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1580 | { |
||
3243 | Serge | 1581 | BUG_ON(obj->pages == NULL); |
3031 | serge | 1582 | obj->pages_pin_count++; |
1583 | } |
||
1584 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
||
1585 | { |
||
1586 | BUG_ON(obj->pages_pin_count == 0); |
||
1587 | obj->pages_pin_count--; |
||
1588 | } |
||
1589 | |||
2325 | Serge | 1590 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
3031 | serge | 1591 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1592 | struct intel_ring_buffer *to); |
||
2325 | Serge | 1593 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
3243 | Serge | 1594 | struct intel_ring_buffer *ring); |
2325 | Serge | 1595 | |
1596 | int i915_gem_dumb_create(struct drm_file *file_priv, |
||
1597 | struct drm_device *dev, |
||
1598 | struct drm_mode_create_dumb *args); |
||
1599 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
||
1600 | uint32_t handle, uint64_t *offset); |
||
1601 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
||
1602 | uint32_t handle); |
||
1603 | /** |
||
1604 | * Returns true if seq1 is later than seq2. |
||
1605 | */ |
||
2340 | Serge | 1606 | static inline bool |
1607 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
||
1608 | { |
||
1609 | return (int32_t)(seq1 - seq2) >= 0; |
||
1610 | } |
||
2325 | Serge | 1611 | |
3480 | Serge | 1612 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1613 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
||
3031 | serge | 1614 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
1615 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
||
1616 | |||
1617 | static inline bool |
||
1618 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
||
2332 | Serge | 1619 | { |
3031 | serge | 1620 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
1621 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
1622 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
||
1623 | return true; |
||
1624 | } else |
||
1625 | return false; |
||
2332 | Serge | 1626 | } |
2325 | Serge | 1627 | |
3031 | serge | 1628 | static inline void |
1629 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
||
1630 | { |
||
1631 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
||
1632 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
||
1633 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
||
1634 | } |
||
1635 | } |
||
2332 | Serge | 1636 | |
2325 | Serge | 1637 | void i915_gem_retire_requests(struct drm_device *dev); |
3031 | serge | 1638 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
3480 | Serge | 1639 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
3031 | serge | 1640 | bool interruptible); |
3480 | Serge | 1641 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1642 | { |
||
1643 | return unlikely(atomic_read(&error->reset_counter) |
||
1644 | & I915_RESET_IN_PROGRESS_FLAG); |
||
1645 | } |
||
3031 | serge | 1646 | |
3480 | Serge | 1647 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
1648 | { |
||
1649 | return atomic_read(&error->reset_counter) == I915_WEDGED; |
||
1650 | } |
||
1651 | |||
2325 | Serge | 1652 | void i915_gem_reset(struct drm_device *dev); |
1653 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
||
1654 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
||
1655 | uint32_t read_domains, |
||
1656 | uint32_t write_domain); |
||
1657 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
||
3031 | serge | 1658 | int __must_check i915_gem_init(struct drm_device *dev); |
1659 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
||
1660 | void i915_gem_l3_remap(struct drm_device *dev); |
||
1661 | void i915_gem_init_swizzling(struct drm_device *dev); |
||
2325 | Serge | 1662 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1663 | int __must_check i915_gpu_idle(struct drm_device *dev); |
||
1664 | int __must_check i915_gem_idle(struct drm_device *dev); |
||
3031 | serge | 1665 | int i915_add_request(struct intel_ring_buffer *ring, |
2325 | Serge | 1666 | struct drm_file *file, |
3031 | serge | 1667 | u32 *seqno); |
1668 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
||
2325 | Serge | 1669 | uint32_t seqno); |
1670 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
||
1671 | int __must_check |
||
1672 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
||
1673 | bool write); |
||
1674 | int __must_check |
||
3031 | serge | 1675 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1676 | int __must_check |
||
2325 | Serge | 1677 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1678 | u32 alignment, |
||
1679 | struct intel_ring_buffer *pipelined); |
||
1680 | int i915_gem_attach_phys_object(struct drm_device *dev, |
||
1681 | struct drm_i915_gem_object *obj, |
||
1682 | int id, |
||
1683 | int align); |
||
1684 | void i915_gem_detach_phys_object(struct drm_device *dev, |
||
1685 | struct drm_i915_gem_object *obj); |
||
1686 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
||
1687 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
||
1688 | |||
1689 | uint32_t |
||
3480 | Serge | 1690 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
1691 | uint32_t |
||
1692 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
||
1693 | int tiling_mode, bool fenced); |
||
2325 | Serge | 1694 | |
1695 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
||
1696 | enum i915_cache_level cache_level); |
||
1697 | |||
3031 | serge | 1698 | |
1699 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
||
1700 | struct drm_gem_object *gem_obj, int flags); |
||
1701 | |||
3746 | Serge | 1702 | void i915_gem_restore_fences(struct drm_device *dev); |
1703 | |||
3031 | serge | 1704 | /* i915_gem_context.c */ |
1705 | void i915_gem_context_init(struct drm_device *dev); |
||
1706 | void i915_gem_context_fini(struct drm_device *dev); |
||
1707 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
||
1708 | int i915_switch_context(struct intel_ring_buffer *ring, |
||
1709 | struct drm_file *file, int to_id); |
||
1710 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
||
1711 | struct drm_file *file); |
||
1712 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
||
1713 | struct drm_file *file); |
||
1714 | |||
2325 | Serge | 1715 | /* i915_gem_gtt.c */ |
3031 | serge | 1716 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
1717 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
||
1718 | struct drm_i915_gem_object *obj, |
||
1719 | enum i915_cache_level cache_level); |
||
1720 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
||
1721 | struct drm_i915_gem_object *obj); |
||
1722 | |||
2325 | Serge | 1723 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
3031 | serge | 1724 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1725 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
||
2325 | Serge | 1726 | enum i915_cache_level cache_level); |
1727 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
||
3031 | serge | 1728 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
3480 | Serge | 1729 | void i915_gem_init_global_gtt(struct drm_device *dev); |
1730 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
||
1731 | unsigned long mappable_end, unsigned long end); |
||
3243 | Serge | 1732 | int i915_gem_gtt_init(struct drm_device *dev); |
1733 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
||
1734 | { |
||
1735 | if (INTEL_INFO(dev)->gen < 6) |
||
1736 | intel_gtt_chipset_flush(); |
||
1737 | } |
||
2325 | Serge | 1738 | |
3243 | Serge | 1739 | |
2325 | Serge | 1740 | /* i915_gem_evict.c */ |
1741 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
||
3031 | serge | 1742 | unsigned alignment, |
1743 | unsigned cache_level, |
||
1744 | bool mappable, |
||
1745 | bool nonblock); |
||
1746 | int i915_gem_evict_everything(struct drm_device *dev); |
||
2325 | Serge | 1747 | |
3031 | serge | 1748 | /* i915_gem_stolen.c */ |
1749 | int i915_gem_init_stolen(struct drm_device *dev); |
||
3480 | Serge | 1750 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1751 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
||
3031 | serge | 1752 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
3480 | Serge | 1753 | struct drm_i915_gem_object * |
1754 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
||
3746 | Serge | 1755 | struct drm_i915_gem_object * |
1756 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
||
1757 | u32 stolen_offset, |
||
1758 | u32 gtt_offset, |
||
1759 | u32 size); |
||
3480 | Serge | 1760 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
3031 | serge | 1761 | |
2325 | Serge | 1762 | /* i915_gem_tiling.c */ |
3480 | Serge | 1763 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1764 | { |
||
1765 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
||
1766 | |||
1767 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
||
1768 | obj->tiling_mode != I915_TILING_NONE; |
||
1769 | } |
||
1770 | |||
2325 | Serge | 1771 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
1772 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
1773 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
||
1774 | |||
1775 | /* i915_gem_debug.c */ |
||
1776 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
||
1777 | const char *where, uint32_t mark); |
||
1778 | #if WATCH_LISTS |
||
1779 | int i915_verify_lists(struct drm_device *dev); |
||
1780 | #else |
||
1781 | #define i915_verify_lists(dev) 0 |
||
1782 | #endif |
||
1783 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
||
1784 | int handle); |
||
1785 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
||
1786 | const char *where, uint32_t mark); |
||
1787 | |||
1788 | /* i915_debugfs.c */ |
||
1789 | int i915_debugfs_init(struct drm_minor *minor); |
||
1790 | void i915_debugfs_cleanup(struct drm_minor *minor); |
||
1791 | |||
1792 | /* i915_suspend.c */ |
||
1793 | extern int i915_save_state(struct drm_device *dev); |
||
1794 | extern int i915_restore_state(struct drm_device *dev); |
||
1795 | |||
3480 | Serge | 1796 | /* i915_ums.c */ |
1797 | void i915_save_display_reg(struct drm_device *dev); |
||
1798 | void i915_restore_display_reg(struct drm_device *dev); |
||
2325 | Serge | 1799 | |
3031 | serge | 1800 | /* i915_sysfs.c */ |
1801 | void i915_setup_sysfs(struct drm_device *dev_priv); |
||
1802 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
||
1803 | |||
2325 | Serge | 1804 | /* intel_i2c.c */ |
1805 | extern int intel_setup_gmbus(struct drm_device *dev); |
||
1806 | extern void intel_teardown_gmbus(struct drm_device *dev); |
||
3031 | serge | 1807 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1808 | { |
||
1809 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
||
1810 | } |
||
1811 | |||
1812 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
||
1813 | struct drm_i915_private *dev_priv, unsigned port); |
||
2325 | Serge | 1814 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1815 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
||
2342 | Serge | 1816 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1817 | { |
||
1818 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
||
1819 | } |
||
2325 | Serge | 1820 | extern void intel_i2c_reset(struct drm_device *dev); |
1821 | |||
1822 | /* intel_opregion.c */ |
||
1823 | extern int intel_opregion_setup(struct drm_device *dev); |
||
1824 | #ifdef CONFIG_ACPI |
||
1825 | extern void intel_opregion_init(struct drm_device *dev); |
||
1826 | extern void intel_opregion_fini(struct drm_device *dev); |
||
1827 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
||
1828 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
||
1829 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
||
1830 | #else |
||
1831 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
||
1832 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
||
1833 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
||
1834 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
||
1835 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
||
1836 | #endif |
||
1837 | |||
1838 | /* intel_acpi.c */ |
||
1839 | #ifdef CONFIG_ACPI |
||
1840 | extern void intel_register_dsm_handler(void); |
||
1841 | extern void intel_unregister_dsm_handler(void); |
||
1842 | #else |
||
1843 | static inline void intel_register_dsm_handler(void) { return; } |
||
1844 | static inline void intel_unregister_dsm_handler(void) { return; } |
||
1845 | #endif /* CONFIG_ACPI */ |
||
1846 | |||
1847 | /* modesetting */ |
||
3031 | serge | 1848 | extern void intel_modeset_init_hw(struct drm_device *dev); |
2325 | Serge | 1849 | extern void intel_modeset_init(struct drm_device *dev); |
1850 | extern void intel_modeset_gem_init(struct drm_device *dev); |
||
1851 | extern void intel_modeset_cleanup(struct drm_device *dev); |
||
1852 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
||
3243 | Serge | 1853 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
1854 | bool force_restore); |
||
3480 | Serge | 1855 | extern void i915_redisable_vga(struct drm_device *dev); |
2325 | Serge | 1856 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1857 | extern void intel_disable_fbc(struct drm_device *dev); |
||
1858 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
||
3243 | Serge | 1859 | extern void intel_init_pch_refclk(struct drm_device *dev); |
2325 | Serge | 1860 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
2342 | Serge | 1861 | extern void intel_detect_pch(struct drm_device *dev); |
1862 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
||
3031 | serge | 1863 | extern int intel_enable_rc6(const struct drm_device *dev); |
2325 | Serge | 1864 | |
3031 | serge | 1865 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
1866 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
||
1867 | struct drm_file *file); |
||
2342 | Serge | 1868 | |
2325 | Serge | 1869 | /* overlay */ |
1870 | #ifdef CONFIG_DEBUG_FS |
||
1871 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
||
1872 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
||
1873 | |||
1874 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
||
1875 | extern void intel_display_print_error_state(struct seq_file *m, |
||
1876 | struct drm_device *dev, |
||
1877 | struct intel_display_error_state *error); |
||
1878 | #endif |
||
1879 | |||
1880 | /* On SNB platform, before reading ring registers forcewake bit |
||
1881 | * must be set to prevent GT core from power down and stale values being |
||
1882 | * returned. |
||
1883 | */ |
||
1884 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
||
1885 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
||
3031 | serge | 1886 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
2325 | Serge | 1887 | |
3243 | Serge | 1888 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1889 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
||
3746 | Serge | 1890 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
1891 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
||
3243 | Serge | 1892 | |
2325 | Serge | 1893 | #define __i915_read(x, y) \ |
2342 | Serge | 1894 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
2325 | Serge | 1895 | |
1896 | __i915_read(8, b) |
||
1897 | __i915_read(16, w) |
||
1898 | __i915_read(32, l) |
||
1899 | __i915_read(64, q) |
||
1900 | #undef __i915_read |
||
1901 | |||
1902 | #define __i915_write(x, y) \ |
||
2342 | Serge | 1903 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1904 | |||
2325 | Serge | 1905 | __i915_write(8, b) |
1906 | __i915_write(16, w) |
||
1907 | __i915_write(32, l) |
||
1908 | __i915_write(64, q) |
||
1909 | #undef __i915_write |
||
1910 | |||
1911 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
||
1912 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
||
1913 | |||
1914 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
||
1915 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
||
1916 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
||
1917 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
||
1918 | |||
1919 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
||
1920 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
||
1921 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
||
1922 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
||
1923 | |||
1924 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
||
1925 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
||
1926 | |||
1927 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
||
1928 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
||
1929 | |||
3480 | Serge | 1930 | /* "Broadcast RGB" property */ |
1931 | #define INTEL_BROADCAST_RGB_AUTO 0 |
||
1932 | #define INTEL_BROADCAST_RGB_FULL 1 |
||
1933 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
||
1934 | |||
1935 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
||
1936 | { |
||
1937 | if (HAS_PCH_SPLIT(dev)) |
||
1938 | return CPU_VGACNTRL; |
||
1939 | else if (IS_VALLEYVIEW(dev)) |
||
1940 | return VLV_VGACNTRL; |
||
1941 | else |
||
1942 | return VGACNTRL; |
||
1943 | } |
||
1944 | |||
3746 | Serge | 1945 | static inline void __user *to_user_ptr(u64 address) |
1946 | { |
||
1947 | return (void __user *)(uintptr_t)address; |
||
1948 | } |
||
1949 | |||
1950 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
||
1951 | { |
||
1952 | unsigned long j = msecs_to_jiffies(m); |
||
1953 | |||
1954 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
1955 | } |
||
1956 | |||
1957 | static inline unsigned long |
||
1958 | timespec_to_jiffies_timeout(const struct timespec *value) |
||
1959 | { |
||
1960 | unsigned long j = timespec_to_jiffies(value); |
||
1961 | |||
1962 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
||
1963 | } |
||
1964 | |||
1965 | |||
2338 | Serge | 1966 | typedef struct |
1967 | { |
||
1968 | int width; |
||
1969 | int height; |
||
1970 | int bpp; |
||
1971 | int freq; |
||
1972 | }videomode_t; |
||
2325 | Serge | 1973 | |
2360 | Serge | 1974 | |
1975 | static inline int mutex_trylock(struct mutex *lock) |
||
1976 | { |
||
1977 | if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1)) |
||
1978 | return 1; |
||
1979 | return 0; |
||
1980 | } |
||
1981 | |||
1982 | |||
3031 | serge | 1983 | #define ioread32(addr) readl(addr) |
2360 | Serge | 1984 | |
1985 | |||
1986 | |||
1987 | |||
1988 | |||
2325 | Serge | 1989 | #endif=>>2) |