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2325 | Serge | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * |
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5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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6 | * All Rights Reserved. |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the |
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10 | * "Software"), to deal in the Software without restriction, including |
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11 | * without limitation the rights to use, copy, modify, merge, publish, |
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12 | * distribute, sub license, and/or sell copies of the Software, and to |
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13 | * permit persons to whom the Software is furnished to do so, subject to |
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14 | * the following conditions: |
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15 | * |
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16 | * The above copyright notice and this permission notice (including the |
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17 | * next paragraph) shall be included in all copies or substantial portions |
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18 | * of the Software. |
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19 | * |
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20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | * |
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28 | */ |
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29 | |||
2330 | Serge | 30 | //#include |
3031 | serge | 31 | #include |
32 | #include |
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2330 | Serge | 33 | #include "i915_drv.h" |
34 | #include "intel_drv.h" |
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2325 | Serge | 35 | |
36 | #include |
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37 | #include |
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38 | #include |
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39 | #include |
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40 | #include |
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41 | |||
3031 | serge | 42 | #include |
43 | |||
2325 | Serge | 44 | #include |
45 | |||
2330 | Serge | 46 | #define __read_mostly |
2327 | Serge | 47 | |
2338 | Serge | 48 | int init_display_kms(struct drm_device *dev); |
2330 | Serge | 49 | |
2340 | Serge | 50 | struct drm_device *main_device; |
2338 | Serge | 51 | |
3255 | Serge | 52 | struct drm_file *drm_file_handlers[256]; |
53 | |||
3031 | serge | 54 | static int i915_modeset __read_mostly = 1; |
3480 | Serge | 55 | module_param_named(modeset, i915_modeset, int, 0400); |
3031 | serge | 56 | MODULE_PARM_DESC(modeset, |
57 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
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58 | "1=on, -1=force vga console preference [default])"); |
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59 | |||
60 | |||
3480 | Serge | 61 | int i915_panel_ignore_lid __read_mostly = 1; |
62 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
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3031 | serge | 63 | MODULE_PARM_DESC(panel_ignore_lid, |
3480 | Serge | 64 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
65 | "-1=force lid closed, -2=force lid open)"); |
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2330 | Serge | 66 | |
3482 | Serge | 67 | unsigned int i915_powersave __read_mostly = 1; |
3480 | Serge | 68 | module_param_named(powersave, i915_powersave, int, 0600); |
3031 | serge | 69 | MODULE_PARM_DESC(powersave, |
70 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
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2330 | Serge | 71 | |
3031 | serge | 72 | int i915_semaphores __read_mostly = -1; |
3480 | Serge | 73 | module_param_named(semaphores, i915_semaphores, int, 0600); |
3031 | serge | 74 | MODULE_PARM_DESC(semaphores, |
75 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
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2330 | Serge | 76 | |
3482 | Serge | 77 | int i915_enable_rc6 __read_mostly = -1; |
3480 | Serge | 78 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
3031 | serge | 79 | MODULE_PARM_DESC(i915_enable_rc6, |
80 | "Enable power-saving render C-state 6. " |
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81 | "Different stages can be selected via bitmask values " |
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82 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " |
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83 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " |
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84 | "default: -1 (use per-chip default)"); |
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85 | |||
3482 | Serge | 86 | int i915_enable_fbc __read_mostly = -1; |
3480 | Serge | 87 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
3031 | serge | 88 | MODULE_PARM_DESC(i915_enable_fbc, |
89 | "Enable frame buffer compression for power savings " |
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90 | "(default: -1 (use per-chip default))"); |
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91 | |||
2330 | Serge | 92 | unsigned int i915_lvds_downclock __read_mostly = 0; |
3480 | Serge | 93 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
3031 | serge | 94 | MODULE_PARM_DESC(lvds_downclock, |
95 | "Use panel (LVDS/eDP) downclocking for power savings " |
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96 | "(default: false)"); |
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2330 | Serge | 97 | |
3031 | serge | 98 | int i915_lvds_channel_mode __read_mostly; |
3480 | Serge | 99 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); |
3031 | serge | 100 | MODULE_PARM_DESC(lvds_channel_mode, |
101 | "Specify LVDS channel mode " |
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102 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
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2330 | Serge | 103 | |
3031 | serge | 104 | int i915_panel_use_ssc __read_mostly = -1; |
3480 | Serge | 105 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
3031 | serge | 106 | MODULE_PARM_DESC(lvds_use_ssc, |
107 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
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108 | "(default: auto from VBT)"); |
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109 | |||
2332 | Serge | 110 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
3480 | Serge | 111 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
3031 | serge | 112 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
113 | "Override/Ignore selection of SDVO panel mode in the VBT " |
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114 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
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2330 | Serge | 115 | |
3031 | serge | 116 | static bool i915_try_reset __read_mostly = true; |
3480 | Serge | 117 | module_param_named(reset, i915_try_reset, bool, 0600); |
3031 | serge | 118 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
119 | |||
120 | bool i915_enable_hangcheck __read_mostly = false; |
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3480 | Serge | 121 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
3031 | serge | 122 | MODULE_PARM_DESC(enable_hangcheck, |
123 | "Periodically check GPU activity for detecting hangs. " |
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124 | "WARNING: Disabling this can cause system wide hangs. " |
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125 | "(default: true)"); |
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126 | |||
127 | int i915_enable_ppgtt __read_mostly = false; |
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3480 | Serge | 128 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
3031 | serge | 129 | MODULE_PARM_DESC(i915_enable_ppgtt, |
130 | "Enable PPGTT (default: true)"); |
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131 | |||
132 | unsigned int i915_preliminary_hw_support __read_mostly = true; |
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3480 | Serge | 133 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
3031 | serge | 134 | MODULE_PARM_DESC(preliminary_hw_support, |
135 | "Enable preliminary hardware support. " |
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136 | "Enable Haswell and ValleyView Support. " |
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137 | "(default: false)"); |
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138 | |||
3482 | Serge | 139 | int i915_disable_power_well __read_mostly = 0; |
140 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
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141 | MODULE_PARM_DESC(disable_power_well, |
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142 | "Disable the power well when possible (default: false)"); |
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3031 | serge | 143 | |
2326 | Serge | 144 | #define PCI_VENDOR_ID_INTEL 0x8086 |
145 | |||
2325 | Serge | 146 | #define INTEL_VGA_DEVICE(id, info) { \ |
2342 | Serge | 147 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
2325 | Serge | 148 | .class_mask = 0xff0000, \ |
149 | .vendor = 0x8086, \ |
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150 | .device = id, \ |
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151 | .subvendor = PCI_ANY_ID, \ |
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152 | .subdevice = PCI_ANY_ID, \ |
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153 | .driver_data = (unsigned long) info } |
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154 | |||
2339 | Serge | 155 | |
156 | static const struct intel_device_info intel_i915g_info = { |
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157 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
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158 | .has_overlay = 1, .overlay_needs_physical = 1, |
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159 | }; |
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160 | static const struct intel_device_info intel_i915gm_info = { |
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161 | .gen = 3, .is_mobile = 1, |
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162 | .cursor_needs_physical = 1, |
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163 | .has_overlay = 1, .overlay_needs_physical = 1, |
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164 | .supports_tv = 1, |
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165 | }; |
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166 | static const struct intel_device_info intel_i945g_info = { |
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167 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
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168 | .has_overlay = 1, .overlay_needs_physical = 1, |
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169 | }; |
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170 | static const struct intel_device_info intel_i945gm_info = { |
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171 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
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172 | .has_hotplug = 1, .cursor_needs_physical = 1, |
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173 | .has_overlay = 1, .overlay_needs_physical = 1, |
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174 | .supports_tv = 1, |
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175 | }; |
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176 | |||
177 | static const struct intel_device_info intel_i965g_info = { |
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178 | .gen = 4, .is_broadwater = 1, |
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179 | .has_hotplug = 1, |
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180 | .has_overlay = 1, |
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181 | }; |
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182 | |||
183 | static const struct intel_device_info intel_i965gm_info = { |
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184 | .gen = 4, .is_crestline = 1, |
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185 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
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186 | .has_overlay = 1, |
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187 | .supports_tv = 1, |
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188 | }; |
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189 | |||
190 | static const struct intel_device_info intel_g33_info = { |
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191 | .gen = 3, .is_g33 = 1, |
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192 | .need_gfx_hws = 1, .has_hotplug = 1, |
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193 | .has_overlay = 1, |
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194 | }; |
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195 | |||
196 | static const struct intel_device_info intel_g45_info = { |
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197 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
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198 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
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199 | .has_bsd_ring = 1, |
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200 | }; |
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201 | |||
202 | static const struct intel_device_info intel_gm45_info = { |
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203 | .gen = 4, .is_g4x = 1, |
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204 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
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205 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
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206 | .supports_tv = 1, |
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207 | .has_bsd_ring = 1, |
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208 | }; |
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209 | |||
210 | static const struct intel_device_info intel_pineview_info = { |
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211 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
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212 | .need_gfx_hws = 1, .has_hotplug = 1, |
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213 | .has_overlay = 1, |
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214 | }; |
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215 | |||
216 | static const struct intel_device_info intel_ironlake_d_info = { |
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217 | .gen = 5, |
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3031 | serge | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
2339 | Serge | 219 | .has_bsd_ring = 1, |
220 | }; |
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221 | |||
222 | static const struct intel_device_info intel_ironlake_m_info = { |
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223 | .gen = 5, .is_mobile = 1, |
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224 | .need_gfx_hws = 1, .has_hotplug = 1, |
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225 | .has_fbc = 1, |
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226 | .has_bsd_ring = 1, |
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227 | }; |
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228 | |||
2325 | Serge | 229 | static const struct intel_device_info intel_sandybridge_d_info = { |
230 | .gen = 6, |
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2330 | Serge | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
2325 | Serge | 232 | .has_bsd_ring = 1, |
233 | .has_blt_ring = 1, |
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3031 | serge | 234 | .has_llc = 1, |
235 | .has_force_wake = 1, |
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2325 | Serge | 236 | }; |
237 | |||
238 | static const struct intel_device_info intel_sandybridge_m_info = { |
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2330 | Serge | 239 | .gen = 6, .is_mobile = 1, |
240 | .need_gfx_hws = 1, .has_hotplug = 1, |
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2325 | Serge | 241 | .has_fbc = 1, |
242 | .has_bsd_ring = 1, |
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243 | .has_blt_ring = 1, |
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3031 | serge | 244 | .has_llc = 1, |
245 | .has_force_wake = 1, |
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2325 | Serge | 246 | }; |
247 | |||
2339 | Serge | 248 | static const struct intel_device_info intel_ivybridge_d_info = { |
249 | .is_ivybridge = 1, .gen = 7, |
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250 | .need_gfx_hws = 1, .has_hotplug = 1, |
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251 | .has_bsd_ring = 1, |
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252 | .has_blt_ring = 1, |
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3031 | serge | 253 | .has_llc = 1, |
254 | .has_force_wake = 1, |
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2339 | Serge | 255 | }; |
2325 | Serge | 256 | |
2339 | Serge | 257 | static const struct intel_device_info intel_ivybridge_m_info = { |
258 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
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259 | .need_gfx_hws = 1, .has_hotplug = 1, |
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260 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
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261 | .has_bsd_ring = 1, |
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262 | .has_blt_ring = 1, |
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3031 | serge | 263 | .has_llc = 1, |
264 | .has_force_wake = 1, |
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2339 | Serge | 265 | }; |
266 | |||
3031 | serge | 267 | static const struct intel_device_info intel_valleyview_m_info = { |
268 | .gen = 7, .is_mobile = 1, |
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269 | .need_gfx_hws = 1, .has_hotplug = 1, |
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270 | .has_fbc = 0, |
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271 | .has_bsd_ring = 1, |
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272 | .has_blt_ring = 1, |
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273 | .is_valleyview = 1, |
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3480 | Serge | 274 | .display_mmio_offset = VLV_DISPLAY_BASE, |
3031 | serge | 275 | }; |
276 | |||
277 | static const struct intel_device_info intel_valleyview_d_info = { |
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278 | .gen = 7, |
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279 | .need_gfx_hws = 1, .has_hotplug = 1, |
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280 | .has_fbc = 0, |
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281 | .has_bsd_ring = 1, |
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282 | .has_blt_ring = 1, |
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283 | .is_valleyview = 1, |
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3480 | Serge | 284 | .display_mmio_offset = VLV_DISPLAY_BASE, |
3031 | serge | 285 | }; |
286 | |||
287 | static const struct intel_device_info intel_haswell_d_info = { |
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288 | .is_haswell = 1, .gen = 7, |
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289 | .need_gfx_hws = 1, .has_hotplug = 1, |
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290 | .has_bsd_ring = 1, |
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291 | .has_blt_ring = 1, |
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292 | .has_llc = 1, |
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293 | .has_force_wake = 1, |
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294 | }; |
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295 | |||
296 | static const struct intel_device_info intel_haswell_m_info = { |
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297 | .is_haswell = 1, .gen = 7, .is_mobile = 1, |
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298 | .need_gfx_hws = 1, .has_hotplug = 1, |
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299 | .has_bsd_ring = 1, |
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300 | .has_blt_ring = 1, |
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301 | .has_llc = 1, |
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302 | .has_force_wake = 1, |
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303 | }; |
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304 | |||
2325 | Serge | 305 | static const struct pci_device_id pciidlist[] = { /* aka */ |
2339 | Serge | 306 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
307 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
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308 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
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309 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
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310 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
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311 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
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312 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
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313 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
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314 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
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315 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
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316 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
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317 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
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318 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
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319 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
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320 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
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321 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
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322 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
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323 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
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324 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
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325 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
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326 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
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327 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
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328 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
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329 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
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330 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
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331 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
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2325 | Serge | 332 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
333 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
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334 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
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335 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
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336 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
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337 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
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338 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
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2339 | Serge | 339 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
340 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
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341 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
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342 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
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343 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
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3031 | serge | 344 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
345 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
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346 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
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347 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
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348 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
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349 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
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350 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
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351 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
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352 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
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353 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
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354 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
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355 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
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356 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
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357 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
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358 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
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359 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
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360 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
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361 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
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362 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
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363 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
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364 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
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365 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
||
366 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
||
367 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
||
368 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
||
369 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
||
370 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
||
371 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
||
3480 | Serge | 372 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
373 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ |
||
3031 | serge | 374 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
3480 | Serge | 375 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
376 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ |
||
3031 | serge | 377 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
3480 | Serge | 378 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
379 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ |
||
3031 | serge | 380 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
381 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
||
382 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
||
383 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
||
2325 | Serge | 384 | {0, 0, 0} |
385 | }; |
||
386 | |||
2326 | Serge | 387 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
388 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
||
389 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
||
390 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
||
3031 | serge | 391 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
2325 | Serge | 392 | |
2342 | Serge | 393 | void intel_detect_pch(struct drm_device *dev) |
2326 | Serge | 394 | { |
395 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
396 | struct pci_dev *pch; |
||
397 | |||
398 | /* |
||
399 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
||
400 | * make graphics device passthrough work easy for VMM, that only |
||
401 | * need to expose ISA bridge to let driver know the real hardware |
||
402 | * underneath. This is a requirement from virtualization team. |
||
403 | */ |
||
404 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
||
405 | if (pch) { |
||
406 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
||
3243 | Serge | 407 | unsigned short id; |
2326 | Serge | 408 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
3243 | Serge | 409 | dev_priv->pch_id = id; |
2326 | Serge | 410 | |
411 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
||
412 | dev_priv->pch_type = PCH_IBX; |
||
3031 | serge | 413 | dev_priv->num_pch_pll = 2; |
2326 | Serge | 414 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
3243 | Serge | 415 | WARN_ON(!IS_GEN5(dev)); |
2326 | Serge | 416 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
417 | dev_priv->pch_type = PCH_CPT; |
||
3031 | serge | 418 | dev_priv->num_pch_pll = 2; |
2326 | Serge | 419 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
3243 | Serge | 420 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
2326 | Serge | 421 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
422 | /* PantherPoint is CPT compatible */ |
||
423 | dev_priv->pch_type = PCH_CPT; |
||
3031 | serge | 424 | dev_priv->num_pch_pll = 2; |
2326 | Serge | 425 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
3243 | Serge | 426 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
3031 | serge | 427 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
428 | dev_priv->pch_type = PCH_LPT; |
||
429 | dev_priv->num_pch_pll = 0; |
||
430 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
||
3243 | Serge | 431 | WARN_ON(!IS_HASWELL(dev)); |
432 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
||
433 | dev_priv->pch_type = PCH_LPT; |
||
434 | dev_priv->num_pch_pll = 0; |
||
435 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
||
436 | WARN_ON(!IS_HASWELL(dev)); |
||
2326 | Serge | 437 | } |
3031 | serge | 438 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
2326 | Serge | 439 | } |
440 | } |
||
441 | } |
||
442 | |||
3031 | serge | 443 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
2326 | Serge | 444 | { |
3031 | serge | 445 | if (INTEL_INFO(dev)->gen < 6) |
446 | return 0; |
||
2326 | Serge | 447 | |
3031 | serge | 448 | if (i915_semaphores >= 0) |
449 | return i915_semaphores; |
||
2326 | Serge | 450 | |
3031 | serge | 451 | #ifdef CONFIG_INTEL_IOMMU |
452 | /* Enable semaphores on SNB when IO remapping is off */ |
||
453 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
||
454 | return false; |
||
455 | #endif |
||
2326 | Serge | 456 | |
3031 | serge | 457 | return 1; |
2326 | Serge | 458 | } |
459 | |||
2342 | Serge | 460 | |
461 | |||
462 | |||
463 | |||
2325 | Serge | 464 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent); |
465 | |||
466 | int i915_init(void) |
||
467 | { |
||
468 | static pci_dev_t device; |
||
469 | const struct pci_device_id *ent; |
||
470 | int err; |
||
471 | |||
472 | ent = find_pci_device(&device, pciidlist); |
||
473 | if( unlikely(ent == NULL) ) |
||
474 | { |
||
475 | dbgprintf("device not found\n"); |
||
3480 | Serge | 476 | return -ENODEV; |
2325 | Serge | 477 | }; |
478 | |||
3031 | serge | 479 | struct intel_device_info *intel_info = |
480 | (struct intel_device_info *) ent->driver_data; |
||
481 | |||
3243 | Serge | 482 | if (intel_info->is_valleyview) |
3031 | serge | 483 | if(!i915_preliminary_hw_support) { |
484 | DRM_ERROR("Preliminary hardware support disabled\n"); |
||
485 | return -ENODEV; |
||
486 | } |
||
487 | |||
3037 | serge | 488 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
2325 | Serge | 489 | device.pci_dev.device); |
490 | |||
3031 | serge | 491 | if (intel_info->gen != 3) { |
492 | |||
493 | } else if (init_agp() != 0) { |
||
494 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
||
495 | return -ENODEV; |
||
496 | } |
||
497 | |||
2325 | Serge | 498 | err = drm_get_dev(&device.pci_dev, ent); |
499 | |||
500 | return err; |
||
501 | } |
||
502 | |||
3260 | Serge | 503 | |
504 | |||
505 | static struct drm_driver driver = { |
||
506 | /* Don't use MTRRs here; the Xserver or userspace app should |
||
507 | * deal with them for Intel hardware. |
||
508 | */ |
||
3482 | Serge | 509 | .driver_features = |
510 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ |
||
511 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_MODESET, |
||
3260 | Serge | 512 | // .load = i915_driver_load, |
513 | // .unload = i915_driver_unload, |
||
3263 | Serge | 514 | .open = i915_driver_open, |
3260 | Serge | 515 | // .lastclose = i915_driver_lastclose, |
516 | // .preclose = i915_driver_preclose, |
||
517 | // .postclose = i915_driver_postclose, |
||
518 | |||
519 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
||
520 | // .suspend = i915_suspend, |
||
521 | // .resume = i915_resume, |
||
522 | |||
523 | // .device_is_agp = i915_driver_device_is_agp, |
||
524 | // .master_create = i915_master_create, |
||
525 | // .master_destroy = i915_master_destroy, |
||
526 | .gem_init_object = i915_gem_init_object, |
||
527 | .gem_free_object = i915_gem_free_object, |
||
528 | // .gem_vm_ops = &i915_gem_vm_ops, |
||
529 | |||
530 | // .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
||
531 | // .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
||
532 | // .gem_prime_export = i915_gem_prime_export, |
||
533 | // .gem_prime_import = i915_gem_prime_import, |
||
534 | |||
535 | // .dumb_create = i915_gem_dumb_create, |
||
536 | // .dumb_map_offset = i915_gem_mmap_gtt, |
||
537 | // .dumb_destroy = i915_gem_dumb_destroy, |
||
538 | // .ioctls = i915_ioctls, |
||
539 | // .fops = &i915_driver_fops, |
||
540 | // .name = DRIVER_NAME, |
||
541 | // .desc = DRIVER_DESC, |
||
542 | // .date = DRIVER_DATE, |
||
543 | // .major = DRIVER_MAJOR, |
||
544 | // .minor = DRIVER_MINOR, |
||
545 | // .patchlevel = DRIVER_PATCHLEVEL, |
||
546 | }; |
||
547 | |||
548 | |||
2325 | Serge | 549 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
550 | { |
||
3255 | Serge | 551 | static struct drm_device drm_dev; |
552 | static struct drm_file drm_file; |
||
3243 | Serge | 553 | |
3255 | Serge | 554 | struct drm_device *dev; |
555 | struct drm_file *priv; |
||
556 | |||
2325 | Serge | 557 | int ret; |
558 | |||
3255 | Serge | 559 | dev = &drm_dev; |
560 | priv = &drm_file; |
||
2325 | Serge | 561 | |
3255 | Serge | 562 | drm_file_handlers[0] = priv; |
563 | |||
2325 | Serge | 564 | // ret = pci_enable_device(pdev); |
565 | // if (ret) |
||
566 | // goto err_g1; |
||
567 | |||
3031 | serge | 568 | pci_set_master(pdev); |
2325 | Serge | 569 | |
570 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
571 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
572 | // goto err_g2; |
||
573 | // } |
||
574 | |||
575 | dev->pdev = pdev; |
||
576 | dev->pci_device = pdev->device; |
||
577 | dev->pci_vendor = pdev->vendor; |
||
578 | |||
579 | INIT_LIST_HEAD(&dev->filelist); |
||
580 | INIT_LIST_HEAD(&dev->ctxlist); |
||
581 | INIT_LIST_HEAD(&dev->vmalist); |
||
582 | INIT_LIST_HEAD(&dev->maplist); |
||
583 | |||
584 | spin_lock_init(&dev->count_lock); |
||
585 | mutex_init(&dev->struct_mutex); |
||
586 | mutex_init(&dev->ctxlist_mutex); |
||
587 | |||
3255 | Serge | 588 | INIT_LIST_HEAD(&priv->lhead); |
589 | INIT_LIST_HEAD(&priv->fbs); |
||
590 | INIT_LIST_HEAD(&priv->event_list); |
||
591 | init_waitqueue_head(&priv->event_wait); |
||
592 | priv->event_space = 4096; /* set aside 4k for event buffer */ |
||
593 | |||
594 | idr_init(&priv->object_idr); |
||
595 | spin_lock_init(&priv->table_lock); |
||
596 | |||
3243 | Serge | 597 | dev->driver = &driver; |
598 | |||
3263 | Serge | 599 | if (dev->driver->open) { |
600 | ret = dev->driver->open(dev, priv); |
||
601 | if (ret < 0) |
||
602 | goto err_g4; |
||
603 | } |
||
604 | |||
2336 | Serge | 605 | ret = i915_driver_load(dev, ent->driver_data ); |
2325 | Serge | 606 | |
2338 | Serge | 607 | if (ret) |
608 | goto err_g4; |
||
2330 | Serge | 609 | |
2338 | Serge | 610 | ret = init_display_kms(dev); |
2336 | Serge | 611 | |
2338 | Serge | 612 | if (ret) |
613 | goto err_g4; |
||
2336 | Serge | 614 | |
2325 | Serge | 615 | return 0; |
616 | |||
617 | err_g4: |
||
618 | //err_g3: |
||
619 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
620 | // drm_put_minor(&dev->control); |
||
621 | //err_g2: |
||
622 | // pci_disable_device(pdev); |
||
623 | //err_g1: |
||
624 | |||
625 | return ret; |
||
626 | } |
||
627 | |||
3031 | serge | 628 | /* We give fast paths for the really cool registers */ |
629 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
||
630 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
||
631 | ((reg) < 0x40000) && \ |
||
632 | ((reg) != FORCEWAKE)) |
||
2325 | Serge | 633 | |
3031 | serge | 634 | static bool IS_DISPLAYREG(u32 reg) |
635 | { |
||
636 | /* |
||
637 | * This should make it easier to transition modules over to the |
||
638 | * new register block scheme, since we can do it incrementally. |
||
639 | */ |
||
640 | if (reg >= VLV_DISPLAY_BASE) |
||
641 | return false; |
||
642 | |||
643 | if (reg >= RENDER_RING_BASE && |
||
644 | reg < RENDER_RING_BASE + 0xff) |
||
645 | return false; |
||
646 | if (reg >= GEN6_BSD_RING_BASE && |
||
647 | reg < GEN6_BSD_RING_BASE + 0xff) |
||
648 | return false; |
||
649 | if (reg >= BLT_RING_BASE && |
||
650 | reg < BLT_RING_BASE + 0xff) |
||
651 | return false; |
||
652 | |||
653 | if (reg == PGTBL_ER) |
||
654 | return false; |
||
655 | |||
656 | if (reg >= IPEIR_I965 && |
||
657 | reg < HWSTAM) |
||
658 | return false; |
||
659 | |||
660 | if (reg == MI_MODE) |
||
661 | return false; |
||
662 | |||
663 | if (reg == GFX_MODE_GEN7) |
||
664 | return false; |
||
665 | |||
666 | if (reg == RENDER_HWS_PGA_GEN7 || |
||
667 | reg == BSD_HWS_PGA_GEN7 || |
||
668 | reg == BLT_HWS_PGA_GEN7) |
||
669 | return false; |
||
670 | |||
671 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
||
672 | reg == GEN6_BSD_RNCID) |
||
673 | return false; |
||
674 | |||
675 | if (reg == GEN6_BLITTER_ECOSKPD) |
||
676 | return false; |
||
677 | |||
678 | if (reg >= 0x4000c && |
||
679 | reg <= 0x4002c) |
||
680 | return false; |
||
681 | |||
682 | if (reg >= 0x4f000 && |
||
683 | reg <= 0x4f08f) |
||
684 | return false; |
||
685 | |||
686 | if (reg >= 0x4f100 && |
||
687 | reg <= 0x4f11f) |
||
688 | return false; |
||
689 | |||
690 | if (reg >= VLV_MASTER_IER && |
||
691 | reg <= GEN6_PMIER) |
||
692 | return false; |
||
693 | |||
694 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
||
695 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
||
696 | return false; |
||
697 | |||
698 | if (reg >= VLV_IIR_RW && |
||
699 | reg <= VLV_ISR) |
||
700 | return false; |
||
701 | |||
702 | if (reg == FORCEWAKE_VLV || |
||
703 | reg == FORCEWAKE_ACK_VLV) |
||
704 | return false; |
||
705 | |||
706 | if (reg == GEN6_GDRST) |
||
707 | return false; |
||
708 | |||
3243 | Serge | 709 | switch (reg) { |
710 | case _3D_CHICKEN3: |
||
711 | case IVB_CHICKEN3: |
||
712 | case GEN7_COMMON_SLICE_CHICKEN1: |
||
713 | case GEN7_L3CNTLREG1: |
||
714 | case GEN7_L3_CHICKEN_MODE_REGISTER: |
||
715 | case GEN7_ROW_CHICKEN2: |
||
716 | case GEN7_L3SQCREG4: |
||
717 | case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: |
||
718 | case GEN7_HALF_SLICE_CHICKEN1: |
||
719 | case GEN6_MBCTL: |
||
720 | case GEN6_UCGCTL2: |
||
721 | return false; |
||
722 | default: |
||
723 | break; |
||
724 | } |
||
725 | |||
3031 | serge | 726 | return true; |
727 | } |
||
728 | |||
3243 | Serge | 729 | static void |
730 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
||
731 | { |
||
732 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the |
||
733 | * chip from rc6 before touching it for real. MI_MODE is masked, hence |
||
734 | * harmless to write 0 into. */ |
||
735 | I915_WRITE_NOTRACE(MI_MODE, 0); |
||
736 | } |
||
737 | |||
2342 | Serge | 738 | #define __i915_read(x, y) \ |
739 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
||
740 | u##x val = 0; \ |
||
3243 | Serge | 741 | if (IS_GEN5(dev_priv->dev)) \ |
742 | ilk_dummy_write(dev_priv); \ |
||
2342 | Serge | 743 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
744 | unsigned long irqflags; \ |
||
745 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
||
746 | if (dev_priv->forcewake_count == 0) \ |
||
3031 | serge | 747 | dev_priv->gt.force_wake_get(dev_priv); \ |
2342 | Serge | 748 | val = read##y(dev_priv->regs + reg); \ |
749 | if (dev_priv->forcewake_count == 0) \ |
||
3031 | serge | 750 | dev_priv->gt.force_wake_put(dev_priv); \ |
2342 | Serge | 751 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
752 | } else { \ |
||
753 | val = read##y(dev_priv->regs + reg); \ |
||
754 | } \ |
||
755 | return val; \ |
||
756 | } |
||
757 | |||
758 | __i915_read(8, b) |
||
759 | __i915_read(16, w) |
||
760 | __i915_read(32, l) |
||
761 | __i915_read(64, q) |
||
762 | #undef __i915_read |
||
763 | |||
764 | #define __i915_write(x, y) \ |
||
765 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
||
3120 | serge | 766 | u32 __fifo_ret = 0; \ |
767 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
||
2342 | Serge | 768 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
3120 | serge | 769 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
2342 | Serge | 770 | } \ |
3243 | Serge | 771 | if (IS_GEN5(dev_priv->dev)) \ |
772 | ilk_dummy_write(dev_priv); \ |
||
773 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
||
774 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ |
||
775 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ |
||
776 | } \ |
||
2342 | Serge | 777 | write##y(val, dev_priv->regs + reg); \ |
3120 | serge | 778 | if (unlikely(__fifo_ret)) { \ |
779 | gen6_gt_check_fifodbg(dev_priv); \ |
||
780 | } \ |
||
781 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
||
782 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
||
783 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
||
784 | } \ |
||
2342 | Serge | 785 | } |
786 | __i915_write(8, b) |
||
787 | __i915_write(16, w) |
||
788 | __i915_write(32, l) |
||
789 | __i915_write(64, q) |
||
790 | #undef __i915_write=>>=>=>=>=>>>>>>>>><>><> |