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Rev | Author | Line No. | Line |
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2325 | Serge | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * |
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5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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6 | * All Rights Reserved. |
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7 | * |
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8 | * Permission is hereby granted, free of charge, to any person obtaining a |
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9 | * copy of this software and associated documentation files (the |
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10 | * "Software"), to deal in the Software without restriction, including |
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11 | * without limitation the rights to use, copy, modify, merge, publish, |
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12 | * distribute, sub license, and/or sell copies of the Software, and to |
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13 | * permit persons to whom the Software is furnished to do so, subject to |
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14 | * the following conditions: |
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15 | * |
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16 | * The above copyright notice and this permission notice (including the |
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17 | * next paragraph) shall be included in all copies or substantial portions |
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18 | * of the Software. |
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19 | * |
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20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | * |
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28 | */ |
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29 | |||
2330 | Serge | 30 | //#include |
31 | #include "drmP.h" |
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32 | #include "drm.h" |
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33 | #include "i915_drm.h" |
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34 | #include "i915_drv.h" |
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35 | #include "intel_drv.h" |
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2325 | Serge | 36 | |
2330 | Serge | 37 | |
2325 | Serge | 38 | #include |
39 | #include |
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40 | #include |
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41 | #include |
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42 | #include |
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43 | |||
44 | #include |
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45 | |||
2330 | Serge | 46 | #define __read_mostly |
2327 | Serge | 47 | |
2338 | Serge | 48 | int init_display_kms(struct drm_device *dev); |
2330 | Serge | 49 | |
2340 | Serge | 50 | struct drm_device *main_device; |
2338 | Serge | 51 | |
2332 | Serge | 52 | int i915_panel_ignore_lid __read_mostly = 0; |
2330 | Serge | 53 | |
2332 | Serge | 54 | unsigned int i915_powersave __read_mostly = 0; |
2330 | Serge | 55 | |
2342 | Serge | 56 | unsigned int i915_enable_rc6 __read_mostly = -1; |
2330 | Serge | 57 | |
2336 | Serge | 58 | unsigned int i915_enable_fbc __read_mostly = 0; |
2330 | Serge | 59 | |
60 | unsigned int i915_lvds_downclock __read_mostly = 0; |
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61 | |||
2332 | Serge | 62 | unsigned int i915_panel_use_ssc __read_mostly = 1; |
2330 | Serge | 63 | |
2332 | Serge | 64 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
2330 | Serge | 65 | |
2326 | Serge | 66 | #define PCI_VENDOR_ID_INTEL 0x8086 |
67 | |||
2325 | Serge | 68 | #define INTEL_VGA_DEVICE(id, info) { \ |
2342 | Serge | 69 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
2325 | Serge | 70 | .class_mask = 0xff0000, \ |
71 | .vendor = 0x8086, \ |
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72 | .device = id, \ |
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73 | .subvendor = PCI_ANY_ID, \ |
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74 | .subdevice = PCI_ANY_ID, \ |
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75 | .driver_data = (unsigned long) info } |
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76 | |||
2339 | Serge | 77 | |
78 | static const struct intel_device_info intel_i915g_info = { |
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79 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
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80 | .has_overlay = 1, .overlay_needs_physical = 1, |
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81 | }; |
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82 | static const struct intel_device_info intel_i915gm_info = { |
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83 | .gen = 3, .is_mobile = 1, |
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84 | .cursor_needs_physical = 1, |
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85 | .has_overlay = 1, .overlay_needs_physical = 1, |
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86 | .supports_tv = 1, |
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87 | }; |
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88 | static const struct intel_device_info intel_i945g_info = { |
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89 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
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90 | .has_overlay = 1, .overlay_needs_physical = 1, |
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91 | }; |
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92 | static const struct intel_device_info intel_i945gm_info = { |
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93 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
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94 | .has_hotplug = 1, .cursor_needs_physical = 1, |
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95 | .has_overlay = 1, .overlay_needs_physical = 1, |
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96 | .supports_tv = 1, |
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97 | }; |
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98 | |||
99 | static const struct intel_device_info intel_i965g_info = { |
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100 | .gen = 4, .is_broadwater = 1, |
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101 | .has_hotplug = 1, |
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102 | .has_overlay = 1, |
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103 | }; |
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104 | |||
105 | static const struct intel_device_info intel_i965gm_info = { |
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106 | .gen = 4, .is_crestline = 1, |
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107 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
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108 | .has_overlay = 1, |
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109 | .supports_tv = 1, |
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110 | }; |
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111 | |||
112 | static const struct intel_device_info intel_g33_info = { |
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113 | .gen = 3, .is_g33 = 1, |
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114 | .need_gfx_hws = 1, .has_hotplug = 1, |
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115 | .has_overlay = 1, |
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116 | }; |
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117 | |||
118 | static const struct intel_device_info intel_g45_info = { |
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119 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
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120 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
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121 | .has_bsd_ring = 1, |
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122 | }; |
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123 | |||
124 | static const struct intel_device_info intel_gm45_info = { |
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125 | .gen = 4, .is_g4x = 1, |
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126 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
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127 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
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128 | .supports_tv = 1, |
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129 | .has_bsd_ring = 1, |
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130 | }; |
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131 | |||
132 | static const struct intel_device_info intel_pineview_info = { |
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133 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
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134 | .need_gfx_hws = 1, .has_hotplug = 1, |
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135 | .has_overlay = 1, |
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136 | }; |
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137 | |||
138 | static const struct intel_device_info intel_ironlake_d_info = { |
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139 | .gen = 5, |
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140 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
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141 | .has_bsd_ring = 1, |
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142 | }; |
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143 | |||
144 | static const struct intel_device_info intel_ironlake_m_info = { |
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145 | .gen = 5, .is_mobile = 1, |
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146 | .need_gfx_hws = 1, .has_hotplug = 1, |
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147 | .has_fbc = 1, |
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148 | .has_bsd_ring = 1, |
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149 | }; |
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150 | |||
2325 | Serge | 151 | static const struct intel_device_info intel_sandybridge_d_info = { |
152 | .gen = 6, |
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2330 | Serge | 153 | .need_gfx_hws = 1, .has_hotplug = 1, |
2325 | Serge | 154 | .has_bsd_ring = 1, |
155 | .has_blt_ring = 1, |
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156 | }; |
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157 | |||
158 | static const struct intel_device_info intel_sandybridge_m_info = { |
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2330 | Serge | 159 | .gen = 6, .is_mobile = 1, |
160 | .need_gfx_hws = 1, .has_hotplug = 1, |
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2325 | Serge | 161 | .has_fbc = 1, |
162 | .has_bsd_ring = 1, |
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163 | .has_blt_ring = 1, |
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164 | }; |
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165 | |||
2339 | Serge | 166 | static const struct intel_device_info intel_ivybridge_d_info = { |
167 | .is_ivybridge = 1, .gen = 7, |
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168 | .need_gfx_hws = 1, .has_hotplug = 1, |
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169 | .has_bsd_ring = 1, |
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170 | .has_blt_ring = 1, |
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171 | }; |
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2325 | Serge | 172 | |
2339 | Serge | 173 | static const struct intel_device_info intel_ivybridge_m_info = { |
174 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
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175 | .need_gfx_hws = 1, .has_hotplug = 1, |
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176 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
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177 | .has_bsd_ring = 1, |
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178 | .has_blt_ring = 1, |
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179 | }; |
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180 | |||
2325 | Serge | 181 | static const struct pci_device_id pciidlist[] = { /* aka */ |
2339 | Serge | 182 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
183 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
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184 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
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185 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
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186 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
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187 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
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188 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
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189 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
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190 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
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191 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
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192 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
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193 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
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194 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
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195 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
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196 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
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197 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
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198 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
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199 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
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200 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
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201 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
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202 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
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203 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
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204 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
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205 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
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206 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
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207 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
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2325 | Serge | 208 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
209 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
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210 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
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211 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
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212 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
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213 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
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214 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
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2339 | Serge | 215 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
216 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
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217 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
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218 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
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219 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
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2325 | Serge | 220 | {0, 0, 0} |
221 | }; |
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222 | |||
2326 | Serge | 223 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
224 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
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225 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
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226 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
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2325 | Serge | 227 | |
2342 | Serge | 228 | void intel_detect_pch(struct drm_device *dev) |
2326 | Serge | 229 | { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; |
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231 | struct pci_dev *pch; |
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232 | |||
233 | /* |
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234 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
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235 | * make graphics device passthrough work easy for VMM, that only |
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236 | * need to expose ISA bridge to let driver know the real hardware |
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237 | * underneath. This is a requirement from virtualization team. |
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238 | */ |
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239 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
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240 | if (pch) { |
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241 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
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242 | int id; |
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243 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
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244 | |||
245 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
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246 | dev_priv->pch_type = PCH_IBX; |
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247 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
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248 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
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249 | dev_priv->pch_type = PCH_CPT; |
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250 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
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251 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
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252 | /* PantherPoint is CPT compatible */ |
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253 | dev_priv->pch_type = PCH_CPT; |
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254 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
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255 | } |
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256 | } |
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257 | } |
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258 | } |
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259 | |||
2342 | Serge | 260 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
2326 | Serge | 261 | { |
262 | int count; |
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263 | |||
264 | count = 0; |
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265 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
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266 | udelay(10); |
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267 | |||
268 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
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269 | POSTING_READ(FORCEWAKE); |
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270 | |||
271 | count = 0; |
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272 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) |
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273 | udelay(10); |
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274 | } |
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275 | |||
2342 | Serge | 276 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
277 | { |
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278 | int count; |
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279 | |||
280 | count = 0; |
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281 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) |
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282 | udelay(10); |
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283 | |||
284 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); |
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285 | POSTING_READ(FORCEWAKE_MT); |
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286 | |||
287 | count = 0; |
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288 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) |
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289 | udelay(10); |
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290 | } |
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291 | |||
2326 | Serge | 292 | /* |
293 | * Generally this is called implicitly by the register read function. However, |
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294 | * if some sequence requires the GT to not power down then this function should |
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295 | * be called at the beginning of the sequence followed by a call to |
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296 | * gen6_gt_force_wake_put() at the end of the sequence. |
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297 | */ |
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298 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
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299 | { |
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2342 | Serge | 300 | unsigned long irqflags; |
2326 | Serge | 301 | |
2342 | Serge | 302 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
303 | if (dev_priv->forcewake_count++ == 0) |
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304 | dev_priv->display.force_wake_get(dev_priv); |
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305 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
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2326 | Serge | 306 | } |
307 | |||
2342 | Serge | 308 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
2326 | Serge | 309 | { |
310 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
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311 | POSTING_READ(FORCEWAKE); |
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312 | } |
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313 | |||
2342 | Serge | 314 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
315 | { |
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316 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); |
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317 | POSTING_READ(FORCEWAKE_MT); |
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318 | } |
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319 | |||
2326 | Serge | 320 | /* |
321 | * see gen6_gt_force_wake_get() |
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322 | */ |
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323 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
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324 | { |
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2342 | Serge | 325 | unsigned long irqflags; |
2326 | Serge | 326 | |
2342 | Serge | 327 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
328 | if (--dev_priv->forcewake_count == 0) |
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329 | dev_priv->display.force_wake_put(dev_priv); |
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330 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
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2326 | Serge | 331 | } |
332 | |||
333 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
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334 | { |
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2342 | Serge | 335 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
2326 | Serge | 336 | int loop = 500; |
337 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
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338 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
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339 | udelay(10); |
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340 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
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341 | } |
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342 | // WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES); |
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343 | dev_priv->gt_fifo_count = fifo; |
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344 | } |
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345 | dev_priv->gt_fifo_count--; |
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346 | } |
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347 | |||
348 | |||
349 | |||
350 | |||
351 | |||
2325 | Serge | 352 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent); |
353 | |||
354 | int i915_init(void) |
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355 | { |
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356 | static pci_dev_t device; |
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357 | const struct pci_device_id *ent; |
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358 | int err; |
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359 | |||
360 | if( init_agp() != 0) |
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361 | { |
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362 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
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363 | return 0; |
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364 | }; |
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365 | |||
366 | ent = find_pci_device(&device, pciidlist); |
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367 | |||
368 | if( unlikely(ent == NULL) ) |
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369 | { |
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370 | dbgprintf("device not found\n"); |
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371 | return 0; |
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372 | }; |
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373 | |||
374 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
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375 | device.pci_dev.device); |
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376 | |||
377 | err = drm_get_dev(&device.pci_dev, ent); |
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378 | |||
379 | return err; |
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380 | } |
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381 | |||
382 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
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383 | { |
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2340 | Serge | 384 | struct drm_device *dev; |
2325 | Serge | 385 | int ret; |
386 | |||
387 | ENTER(); |
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388 | |||
389 | dev = kzalloc(sizeof(*dev), 0); |
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390 | if (!dev) |
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391 | return -ENOMEM; |
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392 | |||
393 | // ret = pci_enable_device(pdev); |
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394 | // if (ret) |
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395 | // goto err_g1; |
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396 | |||
397 | // pci_set_master(pdev); |
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398 | |||
399 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
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400 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
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401 | // goto err_g2; |
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402 | // } |
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403 | |||
404 | dev->pdev = pdev; |
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405 | dev->pci_device = pdev->device; |
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406 | dev->pci_vendor = pdev->vendor; |
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407 | |||
408 | INIT_LIST_HEAD(&dev->filelist); |
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409 | INIT_LIST_HEAD(&dev->ctxlist); |
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410 | INIT_LIST_HEAD(&dev->vmalist); |
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411 | INIT_LIST_HEAD(&dev->maplist); |
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412 | |||
413 | spin_lock_init(&dev->count_lock); |
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414 | mutex_init(&dev->struct_mutex); |
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415 | mutex_init(&dev->ctxlist_mutex); |
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416 | |||
2336 | Serge | 417 | ret = i915_driver_load(dev, ent->driver_data ); |
2325 | Serge | 418 | |
2338 | Serge | 419 | if (ret) |
420 | goto err_g4; |
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2330 | Serge | 421 | |
2338 | Serge | 422 | ret = init_display_kms(dev); |
2336 | Serge | 423 | |
2338 | Serge | 424 | if (ret) |
425 | goto err_g4; |
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2336 | Serge | 426 | |
2325 | Serge | 427 | LEAVE(); |
428 | |||
429 | return 0; |
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430 | |||
431 | err_g4: |
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432 | // drm_put_minor(&dev->primary); |
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433 | //err_g3: |
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434 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
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435 | // drm_put_minor(&dev->control); |
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436 | //err_g2: |
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437 | // pci_disable_device(pdev); |
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438 | //err_g1: |
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439 | free(dev); |
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440 | |||
441 | LEAVE(); |
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442 | |||
443 | return ret; |
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444 | } |
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445 | |||
446 | |||
2342 | Serge | 447 | #define __i915_read(x, y) \ |
448 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
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449 | u##x val = 0; \ |
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450 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
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451 | unsigned long irqflags; \ |
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452 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
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453 | if (dev_priv->forcewake_count == 0) \ |
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454 | dev_priv->display.force_wake_get(dev_priv); \ |
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455 | val = read##y(dev_priv->regs + reg); \ |
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456 | if (dev_priv->forcewake_count == 0) \ |
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457 | dev_priv->display.force_wake_put(dev_priv); \ |
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458 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
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459 | } else { \ |
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460 | val = read##y(dev_priv->regs + reg); \ |
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461 | } \ |
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462 | return val; \ |
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463 | } |
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464 | |||
465 | __i915_read(8, b) |
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466 | __i915_read(16, w) |
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467 | __i915_read(32, l) |
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468 | __i915_read(64, q) |
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469 | #undef __i915_read |
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470 | |||
471 | #define __i915_write(x, y) \ |
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472 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
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473 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
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474 | __gen6_gt_wait_for_fifo(dev_priv); \ |
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475 | } \ |
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476 | write##y(val, dev_priv->regs + reg); \ |
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477 | } |
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478 | __i915_write(8, b) |
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479 | __i915_write(16, w) |
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480 | __i915_write(32, l) |
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481 | __i915_write(64, q) |
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482 | #undef __i915_write=>>=>>16)><16)>>16)><16)>>>>><>><> |