Subversion Repositories Kolibri OS

/*

 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sub license, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial portions

 * of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef _I915_DRM_H_

#define _I915_DRM_H_

#include "drm.h"

/* Please note that modifications to all structs defined here are

 * subject to backwards-compatibility constraints.

 */

#ifdef __KERNEL__

/* For use by IPS driver */

extern unsigned long i915_read_mch_val(void);

extern bool i915_gpu_raise(void);

extern bool i915_gpu_lower(void);

extern bool i915_gpu_busy(void);

extern bool i915_gpu_turbo_disable(void);

#endif

/* Each region is a minimum of 16k, and there are at most 255 of them.

 */

#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use

				 * of chars for next/prev indices */

#define I915_LOG_MIN_TEX_REGION_SIZE 14

typedef struct _drm_i915_init {

	enum {

		I915_INIT_DMA = 0x01,

		I915_CLEANUP_DMA = 0x02,

		I915_RESUME_DMA = 0x03

	} func;

	unsigned int mmio_offset;

	int sarea_priv_offset;

	unsigned int ring_start;

	unsigned int ring_end;

	unsigned int ring_size;

	unsigned int front_offset;

	unsigned int back_offset;

	unsigned int depth_offset;

	unsigned int w;

	unsigned int h;

	unsigned int pitch;

	unsigned int pitch_bits;

	unsigned int back_pitch;

	unsigned int depth_pitch;

	unsigned int cpp;

	unsigned int chipset;

} drm_i915_init_t;

typedef struct _drm_i915_sarea {

	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];

	int last_upload;	/* last time texture was uploaded */

	int last_enqueue;	/* last time a buffer was enqueued */

	int last_dispatch;	/* age of the most recently dispatched buffer */

	int ctxOwner;		/* last context to upload state */

	int texAge;

	int pf_enabled;		/* is pageflipping allowed? */

	int pf_active;

	int pf_current_page;	/* which buffer is being displayed? */

	int perf_boxes;		/* performance boxes to be displayed */

	int width, height;      /* screen size in pixels */

	drm_handle_t front_handle;

	int front_offset;

	int front_size;

	drm_handle_t back_handle;

	int back_offset;

	int back_size;

	drm_handle_t depth_handle;

	int depth_offset;

	int depth_size;

	drm_handle_t tex_handle;

	int tex_offset;

	int tex_size;

	int log_tex_granularity;

	int pitch;

	int rotation;           /* 0, 90, 180 or 270 */

	int rotated_offset;

	int rotated_size;

	int rotated_pitch;

	int virtualX, virtualY;

	unsigned int front_tiled;

	unsigned int back_tiled;

	unsigned int depth_tiled;

	unsigned int rotated_tiled;

	unsigned int rotated2_tiled;

	int pipeA_x;

	int pipeA_y;

	int pipeA_w;

	int pipeA_h;

	int pipeB_x;

	int pipeB_y;

	int pipeB_w;

	int pipeB_h;

	/* fill out some space for old userspace triple buffer */

	drm_handle_t unused_handle;

	__u32 unused1, unused2, unused3;

	/* buffer object handles for static buffers. May change

	 * over the lifetime of the client.

	 */

	__u32 front_bo_handle;

	__u32 back_bo_handle;

	__u32 unused_bo_handle;

	__u32 depth_bo_handle;

} drm_i915_sarea_t;

/* due to userspace building against these headers we need some compat here */

#define planeA_x pipeA_x

#define planeA_y pipeA_y

#define planeA_w pipeA_w

#define planeA_h pipeA_h

#define planeB_x pipeB_x

#define planeB_y pipeB_y

#define planeB_w pipeB_w

#define planeB_h pipeB_h

/* Flags for perf_boxes

 */

#define I915_BOX_RING_EMPTY    0x1

#define I915_BOX_FLIP          0x2

#define I915_BOX_WAIT          0x4

#define I915_BOX_TEXTURE_LOAD  0x8

#define I915_BOX_LOST_CONTEXT  0x10

/* I915 specific ioctls

 * The device specific ioctl range is 0x40 to 0x79.

 */

#define DRM_I915_INIT		0x00

#define DRM_I915_FLUSH		0x01

#define DRM_I915_FLIP		0x02

#define DRM_I915_BATCHBUFFER	0x03

#define DRM_I915_IRQ_EMIT	0x04

#define DRM_I915_IRQ_WAIT	0x05

#define DRM_I915_GETPARAM	0x06

#define DRM_I915_SETPARAM	0x07

#define DRM_I915_ALLOC		0x08

#define DRM_I915_FREE		0x09

#define DRM_I915_INIT_HEAP	0x0a

#define DRM_I915_CMDBUFFER	0x0b

#define DRM_I915_DESTROY_HEAP	0x0c

#define DRM_I915_SET_VBLANK_PIPE	0x0d

#define DRM_I915_GET_VBLANK_PIPE	0x0e

#define DRM_I915_VBLANK_SWAP	0x0f

#define DRM_I915_HWS_ADDR	0x11

#define DRM_I915_GEM_INIT	0x13

#define DRM_I915_GEM_EXECBUFFER	0x14

#define DRM_I915_GEM_PIN	0x15

#define DRM_I915_GEM_UNPIN	0x16

#define DRM_I915_GEM_BUSY	0x17

#define DRM_I915_GEM_THROTTLE	0x18

#define DRM_I915_GEM_ENTERVT	0x19

#define DRM_I915_GEM_LEAVEVT	0x1a

#define DRM_I915_GEM_CREATE	0x1b

#define DRM_I915_GEM_PREAD	0x1c

#define DRM_I915_GEM_PWRITE	0x1d

#define DRM_I915_GEM_MMAP	0x1e

#define DRM_I915_GEM_SET_DOMAIN	0x1f

#define DRM_I915_GEM_SW_FINISH	0x20

#define DRM_I915_GEM_SET_TILING	0x21

#define DRM_I915_GEM_GET_TILING	0x22

#define DRM_I915_GEM_GET_APERTURE 0x23

#define DRM_I915_GEM_MMAP_GTT	0x24

#define DRM_I915_GET_PIPE_FROM_CRTC_ID	0x25

#define DRM_I915_GEM_MADVISE	0x26

#define DRM_I915_OVERLAY_PUT_IMAGE	0x27

#define DRM_I915_OVERLAY_ATTRS	0x28

#define DRM_I915_GEM_EXECBUFFER2	0x29

#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)

#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)

#define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)

#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)

#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)

#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)

#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)

#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)

#define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)

#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)

#define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)

#define DRM_IOCTL_I915_DESTROY_HEAP	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)

#define DRM_IOCTL_I915_SET_VBLANK_PIPE	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

#define DRM_IOCTL_I915_GET_VBLANK_PIPE	DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

#define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)

#define DRM_IOCTL_I915_HWS_ADDR		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)

#define DRM_IOCTL_I915_GEM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)

#define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)

#define DRM_IOCTL_I915_GEM_EXECBUFFER2	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)

#define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)

#define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)

#define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)

#define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)

#define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)

#define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)

#define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)

#define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)

#define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)

#define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)

#define DRM_IOCTL_I915_GEM_MMAP_GTT	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)

#define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)

#define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)

#define DRM_IOCTL_I915_GEM_SET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)

#define DRM_IOCTL_I915_GEM_GET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)

#define DRM_IOCTL_I915_GEM_GET_APERTURE	DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)

#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)

#define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)

#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)

#define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)

/* Allow drivers to submit batchbuffers directly to hardware, relying

 * on the security mechanisms provided by hardware.

 */

typedef struct drm_i915_batchbuffer {

	int start;		/* agp offset */

	int used;		/* nr bytes in use */

	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */

	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */

	int num_cliprects;	/* mulitpass with multiple cliprects? */

	struct drm_clip_rect __user *cliprects;	/* pointer to userspace cliprects */

} drm_i915_batchbuffer_t;

/* As above, but pass a pointer to userspace buffer which can be

 * validated by the kernel prior to sending to hardware.