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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ |
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3 | /* |
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4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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5 | * All Rights Reserved. |
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6 | * |
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7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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8 | * copy of this software and associated documentation files (the |
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9 | * "Software"), to deal in the Software without restriction, including |
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10 | * without limitation the rights to use, copy, modify, merge, publish, |
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11 | * distribute, sub license, and/or sell copies of the Software, and to |
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12 | * permit persons to whom the Software is furnished to do so, subject to |
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13 | * the following conditions: |
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14 | * |
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15 | * The above copyright notice and this permission notice (including the |
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16 | * next paragraph) shall be included in all copies or substantial portions |
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17 | * of the Software. |
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18 | * |
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19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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26 | * |
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27 | */ |
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28 | |||
29 | #include "drmP.h" |
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30 | #include "drm.h" |
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31 | #include "drm_crtc_helper.h" |
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32 | #include "drm_fb_helper.h" |
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33 | #include "intel_drv.h" |
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2330 | Serge | 34 | #include "i915_drm.h" |
2326 | Serge | 35 | #include "i915_drv.h" |
36 | #include |
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2351 | Serge | 37 | #include "i915_trace.h" |
2326 | Serge | 38 | //#include "../../../platform/x86/intel_ips.h" |
39 | #include |
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40 | //#include |
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41 | //#include |
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42 | //#include |
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43 | //#include |
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2330 | Serge | 44 | #include |
2326 | Serge | 45 | //#include |
46 | |||
47 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); |
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48 | |||
2330 | Serge | 49 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
50 | u32 *val) |
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51 | { |
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52 | *val = PciRead32(dev->busnr, dev->devfn, where); |
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53 | return 1; |
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54 | } |
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55 | |||
56 | |||
57 | |||
2326 | Serge | 58 | static void i915_write_hws_pga(struct drm_device *dev) |
59 | { |
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60 | drm_i915_private_t *dev_priv = dev->dev_private; |
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61 | u32 addr; |
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62 | |||
63 | addr = dev_priv->status_page_dmah->busaddr; |
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64 | if (INTEL_INFO(dev)->gen >= 4) |
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65 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
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66 | I915_WRITE(HWS_PGA, addr); |
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67 | } |
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68 | |||
69 | /** |
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70 | * Sets up the hardware status page for devices that need a physical address |
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71 | * in the register. |
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72 | */ |
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73 | static int i915_init_phys_hws(struct drm_device *dev) |
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74 | { |
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75 | drm_i915_private_t *dev_priv = dev->dev_private; |
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76 | |||
77 | /* Program Hardware Status Page */ |
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78 | dev_priv->status_page_dmah = |
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2352 | Serge | 79 | (void*)drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
2326 | Serge | 80 | |
81 | if (!dev_priv->status_page_dmah) { |
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82 | DRM_ERROR("Can not allocate hardware status page\n"); |
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83 | return -ENOMEM; |
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84 | } |
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85 | |||
86 | i915_write_hws_pga(dev); |
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87 | |||
88 | dbgprintf("Enabled hardware status page\n"); |
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89 | return 0; |
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90 | } |
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91 | |||
2330 | Serge | 92 | |
93 | |||
94 | |||
95 | |||
96 | |||
97 | |||
98 | |||
99 | |||
100 | |||
101 | #define MCHBAR_I915 0x44 |
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102 | #define MCHBAR_I965 0x48 |
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103 | #define MCHBAR_SIZE (4*4096) |
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104 | |||
105 | #define DEVEN_REG 0x54 |
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106 | #define DEVEN_MCHBAR_EN (1 << 28) |
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107 | |||
108 | |||
109 | |||
110 | |||
111 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
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112 | static void |
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113 | intel_setup_mchbar(struct drm_device *dev) |
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114 | { |
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115 | drm_i915_private_t *dev_priv = dev->dev_private; |
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116 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
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117 | u32 temp; |
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118 | bool enabled; |
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119 | |||
120 | dev_priv->mchbar_need_disable = false; |
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121 | |||
122 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
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123 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
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124 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
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125 | } else { |
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126 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
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127 | enabled = temp & 1; |
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128 | } |
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129 | |||
130 | /* If it's already enabled, don't have to do anything */ |
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131 | if (enabled) |
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132 | return; |
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133 | |||
134 | dbgprintf("Epic fail\n"); |
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135 | |||
136 | #if 0 |
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137 | if (intel_alloc_mchbar_resource(dev)) |
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138 | return; |
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139 | |||
140 | dev_priv->mchbar_need_disable = true; |
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141 | |||
142 | /* Space is allocated or reserved, so enable it. */ |
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143 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
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144 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
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145 | temp | DEVEN_MCHBAR_EN); |
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146 | } else { |
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147 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
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148 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
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149 | } |
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150 | #endif |
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151 | } |
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152 | |||
153 | |||
154 | |||
155 | |||
156 | |||
157 | |||
158 | |||
159 | |||
160 | |||
161 | |||
162 | |||
163 | |||
164 | |||
165 | |||
166 | |||
2332 | Serge | 167 | #define LFB_SIZE 0xC00000 |
2330 | Serge | 168 | |
169 | static int i915_load_gem_init(struct drm_device *dev) |
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170 | { |
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171 | struct drm_i915_private *dev_priv = dev->dev_private; |
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172 | unsigned long prealloc_size, gtt_size, mappable_size; |
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173 | int ret; |
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174 | |||
175 | prealloc_size = dev_priv->mm.gtt->stolen_size; |
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176 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
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177 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
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178 | |||
179 | dbgprintf("%s prealloc: %x gtt: %x mappable: %x\n",__FUNCTION__, |
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180 | prealloc_size, gtt_size, mappable_size); |
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181 | |||
182 | /* Basic memrange allocator for stolen space */ |
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183 | drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); |
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184 | |||
185 | /* Let GEM Manage all of the aperture. |
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186 | * |
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187 | * However, leave one page at the end still bound to the scratch page. |
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188 | * There are a number of places where the hardware apparently |
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189 | * prefetches past the end of the object, and we've seen multiple |
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190 | * hangs with the GPU head pointer stuck in a batchbuffer bound |
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191 | * at the last page of the aperture. One page should be enough to |
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192 | * keep any prefetching inside of the aperture. |
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193 | */ |
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2332 | Serge | 194 | i915_gem_do_init(dev, LFB_SIZE, mappable_size, gtt_size - PAGE_SIZE - LFB_SIZE); |
2330 | Serge | 195 | |
2332 | Serge | 196 | mutex_lock(&dev->struct_mutex); |
197 | ret = i915_gem_init_ringbuffer(dev); |
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198 | mutex_unlock(&dev->struct_mutex); |
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199 | if (ret) |
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200 | return ret; |
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2330 | Serge | 201 | |
202 | /* Try to set up FBC with a reasonable compressed buffer size */ |
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203 | // if (I915_HAS_FBC(dev) && i915_powersave) { |
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204 | // int cfb_size; |
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205 | |||
206 | /* Leave 1M for line length buffer & misc. */ |
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207 | |||
208 | /* Try to get a 32M buffer... */ |
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209 | // if (prealloc_size > (36*1024*1024)) |
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210 | // cfb_size = 32*1024*1024; |
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211 | // else /* fall back to 7/8 of the stolen space */ |
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212 | // cfb_size = prealloc_size * 7 / 8; |
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213 | // i915_setup_compression(dev, cfb_size); |
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214 | // } |
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215 | |||
216 | /* Allow hardware batchbuffers unless told otherwise. */ |
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217 | dev_priv->allow_batchbuffer = 1; |
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218 | return 0; |
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219 | } |
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220 | |||
2327 | Serge | 221 | static int i915_load_modeset_init(struct drm_device *dev) |
222 | { |
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223 | struct drm_i915_private *dev_priv = dev->dev_private; |
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224 | int ret; |
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225 | |||
226 | ret = intel_parse_bios(dev); |
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227 | if (ret) |
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228 | DRM_INFO("failed to find VBIOS tables\n"); |
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229 | |||
230 | // intel_register_dsm_handler(); |
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231 | |||
232 | /* IIR "flip pending" bit means done if this bit is set */ |
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233 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) |
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234 | dev_priv->flip_pending_is_done = true; |
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235 | |||
236 | intel_modeset_init(dev); |
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237 | |||
238 | ret = i915_load_gem_init(dev); |
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239 | if (ret) |
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240 | goto cleanup_vga_switcheroo; |
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241 | |||
242 | intel_modeset_gem_init(dev); |
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243 | |||
2351 | Serge | 244 | ret = drm_irq_install(dev); |
245 | if (ret) |
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246 | goto cleanup_gem; |
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2327 | Serge | 247 | |
248 | /* Always safe in the mode setting case. */ |
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249 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
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250 | dev->vblank_disable_allowed = 1; |
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251 | |||
252 | ret = intel_fbdev_init(dev); |
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253 | if (ret) |
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254 | goto cleanup_irq; |
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255 | |||
2332 | Serge | 256 | // drm_kms_helper_poll_init(dev); |
2327 | Serge | 257 | |
258 | /* We're off and running w/KMS */ |
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259 | dev_priv->mm.suspended = 0; |
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260 | |||
261 | return 0; |
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262 | |||
263 | cleanup_irq: |
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264 | // drm_irq_uninstall(dev); |
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265 | cleanup_gem: |
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266 | // mutex_lock(&dev->struct_mutex); |
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267 | // i915_gem_cleanup_ringbuffer(dev); |
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268 | // mutex_unlock(&dev->struct_mutex); |
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269 | cleanup_vga_switcheroo: |
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270 | // vga_switcheroo_unregister_client(dev->pdev); |
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271 | cleanup_vga_client: |
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272 | // vga_client_register(dev->pdev, NULL, NULL, NULL); |
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273 | out: |
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274 | return ret; |
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275 | } |
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276 | |||
277 | |||
278 | |||
2326 | Serge | 279 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
280 | { |
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281 | drm_i915_private_t *dev_priv = dev->dev_private; |
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282 | u32 tmp; |
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283 | |||
284 | tmp = I915_READ(CLKCFG); |
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285 | |||
286 | switch (tmp & CLKCFG_FSB_MASK) { |
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287 | case CLKCFG_FSB_533: |
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288 | dev_priv->fsb_freq = 533; /* 133*4 */ |
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289 | break; |
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290 | case CLKCFG_FSB_800: |
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291 | dev_priv->fsb_freq = 800; /* 200*4 */ |
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292 | break; |
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293 | case CLKCFG_FSB_667: |
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294 | dev_priv->fsb_freq = 667; /* 167*4 */ |
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295 | break; |
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296 | case CLKCFG_FSB_400: |
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297 | dev_priv->fsb_freq = 400; /* 100*4 */ |
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298 | break; |
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299 | } |
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300 | |||
301 | switch (tmp & CLKCFG_MEM_MASK) { |
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302 | case CLKCFG_MEM_533: |
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303 | dev_priv->mem_freq = 533; |
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304 | break; |
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305 | case CLKCFG_MEM_667: |
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306 | dev_priv->mem_freq = 667; |
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307 | break; |
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308 | case CLKCFG_MEM_800: |
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309 | dev_priv->mem_freq = 800; |
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310 | break; |
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311 | } |
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312 | |||
313 | /* detect pineview DDR3 setting */ |
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314 | tmp = I915_READ(CSHRDDR3CTL); |
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315 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
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316 | } |
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317 | |||
318 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
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319 | { |
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320 | drm_i915_private_t *dev_priv = dev->dev_private; |
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321 | u16 ddrpll, csipll; |
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322 | |||
323 | ddrpll = I915_READ16(DDRMPLL1); |
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324 | csipll = I915_READ16(CSIPLL0); |
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325 | |||
326 | switch (ddrpll & 0xff) { |
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327 | case 0xc: |
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328 | dev_priv->mem_freq = 800; |
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329 | break; |
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330 | case 0x10: |
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331 | dev_priv->mem_freq = 1066; |
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332 | break; |
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333 | case 0x14: |
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334 | dev_priv->mem_freq = 1333; |
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335 | break; |
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336 | case 0x18: |
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337 | dev_priv->mem_freq = 1600; |
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338 | break; |
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339 | default: |
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340 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
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341 | ddrpll & 0xff); |
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342 | dev_priv->mem_freq = 0; |
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343 | break; |
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344 | } |
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345 | |||
346 | dev_priv->r_t = dev_priv->mem_freq; |
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347 | |||
348 | switch (csipll & 0x3ff) { |
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349 | case 0x00c: |
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350 | dev_priv->fsb_freq = 3200; |
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351 | break; |
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352 | case 0x00e: |
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353 | dev_priv->fsb_freq = 3733; |
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354 | break; |
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355 | case 0x010: |
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356 | dev_priv->fsb_freq = 4266; |
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357 | break; |
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358 | case 0x012: |
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359 | dev_priv->fsb_freq = 4800; |
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360 | break; |
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361 | case 0x014: |
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362 | dev_priv->fsb_freq = 5333; |
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363 | break; |
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364 | case 0x016: |
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365 | dev_priv->fsb_freq = 5866; |
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366 | break; |
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367 | case 0x018: |
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368 | dev_priv->fsb_freq = 6400; |
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369 | break; |
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370 | default: |
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371 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
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372 | csipll & 0x3ff); |
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373 | dev_priv->fsb_freq = 0; |
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374 | break; |
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375 | } |
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376 | |||
377 | if (dev_priv->fsb_freq == 3200) { |
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378 | dev_priv->c_m = 0; |
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379 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
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380 | dev_priv->c_m = 1; |
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381 | } else { |
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382 | dev_priv->c_m = 2; |
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383 | } |
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384 | } |
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385 | |||
386 | static int i915_get_bridge_dev(struct drm_device *dev) |
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387 | { |
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388 | struct drm_i915_private *dev_priv = dev->dev_private; |
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389 | |||
390 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
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391 | if (!dev_priv->bridge_dev) { |
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392 | DRM_ERROR("bridge device not found\n"); |
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393 | return -1; |
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394 | } |
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395 | return 0; |
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396 | } |
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397 | |||
398 | |||
399 | /* Global for IPS driver to get at the current i915 device */ |
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400 | static struct drm_i915_private *i915_mch_dev; |
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401 | /* |
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402 | * Lock protecting IPS related data structures |
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403 | * - i915_mch_dev |
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404 | * - dev_priv->max_delay |
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405 | * - dev_priv->min_delay |
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406 | * - dev_priv->fmax |
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407 | * - dev_priv->gpu_busy |
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408 | */ |
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409 | static DEFINE_SPINLOCK(mchdev_lock); |
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410 | |||
411 | |||
412 | /** |
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413 | * i915_driver_load - setup chip and create an initial config |
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414 | * @dev: DRM device |
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415 | * @flags: startup flags |
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416 | * |
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417 | * The driver load routine has to do several things: |
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418 | * - drive output discovery via intel_modeset_init() |
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419 | * - initialize the memory manager |
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420 | * - allocate initial config memory |
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421 | * - setup the DRM framebuffer with the allocated memory |
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422 | */ |
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423 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
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424 | { |
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425 | struct drm_i915_private *dev_priv; |
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426 | int ret = 0, mmio_bar; |
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427 | uint32_t agp_size; |
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428 | |||
429 | ENTER(); |
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430 | |||
431 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
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432 | if (dev_priv == NULL) |
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433 | return -ENOMEM; |
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434 | |||
435 | dev->dev_private = (void *)dev_priv; |
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436 | dev_priv->dev = dev; |
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437 | dev_priv->info = (struct intel_device_info *) flags; |
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438 | |||
439 | if (i915_get_bridge_dev(dev)) { |
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440 | ret = -EIO; |
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441 | goto free_priv; |
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442 | } |
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443 | |||
444 | /* overlay on gen2 is broken and can't address above 1G */ |
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445 | // if (IS_GEN2(dev)) |
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446 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
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447 | |||
448 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
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449 | * using 32bit addressing, overwriting memory if HWS is located |
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450 | * above 4GB. |
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451 | * |
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452 | * The documentation also mentions an issue with undefined |
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453 | * behaviour if any general state is accessed within a page above 4GB, |
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454 | * which also needs to be handled carefully. |
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455 | */ |
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456 | // if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
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457 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
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458 | |||
459 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
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460 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); |
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461 | if (!dev_priv->regs) { |
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462 | DRM_ERROR("failed to map registers\n"); |
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463 | ret = -EIO; |
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464 | goto put_bridge; |
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465 | } |
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466 | |||
467 | dev_priv->mm.gtt = intel_gtt_get(); |
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468 | if (!dev_priv->mm.gtt) { |
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469 | DRM_ERROR("Failed to initialize GTT\n"); |
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470 | ret = -ENODEV; |
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471 | goto out_rmmap; |
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472 | } |
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473 | |||
474 | // agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
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475 | |||
476 | /* agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; */ |
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477 | |||
478 | // dev_priv->mm.gtt_mapping = |
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479 | // io_mapping_create_wc(dev->agp->base, agp_size); |
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480 | // if (dev_priv->mm.gtt_mapping == NULL) { |
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481 | // ret = -EIO; |
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482 | // goto out_rmmap; |
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483 | // } |
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484 | |||
485 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
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486 | * one would think, because the kernel disables PAT on first |
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487 | * generation Core chips because WC PAT gets overridden by a UC |
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488 | * MTRR if present. Even if a UC MTRR isn't present. |
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489 | */ |
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490 | // dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, |
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491 | // agp_size, |
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492 | // MTRR_TYPE_WRCOMB, 1); |
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493 | // if (dev_priv->mm.gtt_mtrr < 0) { |
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494 | // DRM_INFO("MTRR allocation failed. Graphics " |
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495 | // "performance may suffer.\n"); |
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496 | // } |
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497 | |||
498 | /* The i915 workqueue is primarily used for batched retirement of |
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499 | * requests (and thus managing bo) once the task has been completed |
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500 | * by the GPU. i915_gem_retire_requests() is called directly when we |
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501 | * need high-priority retirement, such as waiting for an explicit |
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502 | * bo. |
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503 | * |
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504 | * It is also used for periodic low-priority events, such as |
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505 | * idle-timers and recording error state. |
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506 | * |
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507 | * All tasks on the workqueue are expected to acquire the dev mutex |
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508 | * so there is no point in running more than one instance of the |
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509 | * workqueue at any time: max_active = 1 and NON_REENTRANT. |
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510 | */ |
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2360 | Serge | 511 | dev_priv->wq = alloc_workqueue("i915", |
512 | WQ_UNBOUND | WQ_NON_REENTRANT, |
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513 | 1); |
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514 | if (dev_priv->wq == NULL) { |
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515 | DRM_ERROR("Failed to create our workqueue.\n"); |
||
516 | ret = -ENOMEM; |
||
517 | goto out_mtrrfree; |
||
518 | } |
||
2326 | Serge | 519 | |
520 | /* enable GEM by default */ |
||
521 | dev_priv->has_gem = 1; |
||
522 | |||
2351 | Serge | 523 | intel_irq_init(dev); |
2326 | Serge | 524 | |
525 | /* Try to make sure MCHBAR is enabled before poking at it */ |
||
2330 | Serge | 526 | intel_setup_mchbar(dev); |
2326 | Serge | 527 | intel_setup_gmbus(dev); |
2327 | Serge | 528 | intel_opregion_setup(dev); |
2326 | Serge | 529 | |
530 | /* Make sure the bios did its job and set up vital registers */ |
||
2330 | Serge | 531 | intel_setup_bios(dev); |
2326 | Serge | 532 | |
533 | i915_gem_load(dev); |
||
534 | |||
535 | /* Init HWS */ |
||
536 | if (!I915_NEED_GFX_HWS(dev)) { |
||
537 | ret = i915_init_phys_hws(dev); |
||
538 | if (ret) |
||
539 | goto out_gem_unload; |
||
540 | } |
||
541 | |||
542 | if (IS_PINEVIEW(dev)) |
||
543 | i915_pineview_get_mem_freq(dev); |
||
544 | else if (IS_GEN5(dev)) |
||
545 | i915_ironlake_get_mem_freq(dev); |
||
546 | |||
547 | /* On the 945G/GM, the chipset reports the MSI capability on the |
||
548 | * integrated graphics even though the support isn't actually there |
||
549 | * according to the published specs. It doesn't appear to function |
||
550 | * correctly in testing on 945G. |
||
551 | * This may be a side effect of MSI having been made available for PEG |
||
552 | * and the registers being closely associated. |
||
553 | * |
||
554 | * According to chipset errata, on the 965GM, MSI interrupts may |
||
555 | * be lost or delayed, but we use them anyways to avoid |
||
556 | * stuck interrupts on some machines. |
||
557 | */ |
||
558 | // if (!IS_I945G(dev) && !IS_I945GM(dev)) |
||
559 | // pci_enable_msi(dev->pdev); |
||
560 | |||
2342 | Serge | 561 | spin_lock_init(&dev_priv->gt_lock); |
2326 | Serge | 562 | spin_lock_init(&dev_priv->irq_lock); |
563 | spin_lock_init(&dev_priv->error_lock); |
||
564 | spin_lock_init(&dev_priv->rps_lock); |
||
565 | |||
2342 | Serge | 566 | if (IS_IVYBRIDGE(dev)) |
567 | dev_priv->num_pipe = 3; |
||
568 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
||
2326 | Serge | 569 | dev_priv->num_pipe = 2; |
570 | else |
||
571 | dev_priv->num_pipe = 1; |
||
572 | |||
573 | // ret = drm_vblank_init(dev, dev_priv->num_pipe); |
||
574 | // if (ret) |
||
575 | // goto out_gem_unload; |
||
576 | |||
577 | /* Start out suspended */ |
||
578 | dev_priv->mm.suspended = 1; |
||
579 | |||
580 | intel_detect_pch(dev); |
||
581 | |||
2327 | Serge | 582 | ret = i915_load_modeset_init(dev); |
583 | if (ret < 0) { |
||
584 | DRM_ERROR("failed to init modeset\n"); |
||
585 | goto out_gem_unload; |
||
586 | } |
||
2326 | Serge | 587 | |
588 | /* Must be done after probing outputs */ |
||
589 | // intel_opregion_init(dev); |
||
590 | // acpi_video_register(); |
||
591 | |||
592 | // setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
||
593 | // (unsigned long) dev); |
||
594 | |||
595 | spin_lock(&mchdev_lock); |
||
596 | i915_mch_dev = dev_priv; |
||
597 | dev_priv->mchdev_lock = &mchdev_lock; |
||
598 | spin_unlock(&mchdev_lock); |
||
599 | |||
600 | // ips_ping_for_i915_load(); |
||
601 | |||
602 | LEAVE(); |
||
603 | |||
604 | return 0; |
||
605 | |||
606 | out_gem_unload: |
||
607 | // if (dev_priv->mm.inactive_shrinker.shrink) |
||
608 | // unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
||
609 | |||
610 | // if (dev->pdev->msi_enabled) |
||
611 | // pci_disable_msi(dev->pdev); |
||
612 | |||
613 | // intel_teardown_gmbus(dev); |
||
614 | // intel_teardown_mchbar(dev); |
||
615 | // destroy_workqueue(dev_priv->wq); |
||
616 | out_mtrrfree: |
||
617 | // if (dev_priv->mm.gtt_mtrr >= 0) { |
||
618 | // mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, |
||
619 | // dev->agp->agp_info.aper_size * 1024 * 1024); |
||
620 | // dev_priv->mm.gtt_mtrr = -1; |
||
621 | // } |
||
622 | // io_mapping_free(dev_priv->mm.gtt_mapping); |
||
623 | |||
624 | out_rmmap: |
||
625 | pci_iounmap(dev->pdev, dev_priv->regs); |
||
626 | put_bridge: |
||
627 | // pci_dev_put(dev_priv->bridge_dev); |
||
628 | free_priv: |
||
629 | kfree(dev_priv); |
||
630 | return ret; |
||
631 | }>>><>=>><>><>><> |
||
632 |