Rev 2326 | Rev 2330 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
2326 | Serge | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ |
||
3 | /* |
||
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
||
5 | * All Rights Reserved. |
||
6 | * |
||
7 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
8 | * copy of this software and associated documentation files (the |
||
9 | * "Software"), to deal in the Software without restriction, including |
||
10 | * without limitation the rights to use, copy, modify, merge, publish, |
||
11 | * distribute, sub license, and/or sell copies of the Software, and to |
||
12 | * permit persons to whom the Software is furnished to do so, subject to |
||
13 | * the following conditions: |
||
14 | * |
||
15 | * The above copyright notice and this permission notice (including the |
||
16 | * next paragraph) shall be included in all copies or substantial portions |
||
17 | * of the Software. |
||
18 | * |
||
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
||
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
||
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
||
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
||
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
||
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
||
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
||
26 | * |
||
27 | */ |
||
28 | |||
29 | #include "drmP.h" |
||
30 | #include "drm.h" |
||
31 | #include "drm_crtc_helper.h" |
||
32 | #include "drm_fb_helper.h" |
||
33 | #include "intel_drv.h" |
||
34 | //#include "i915_drm.h" |
||
35 | #include "i915_drv.h" |
||
36 | #include |
||
37 | //#include "i915_trace.h" |
||
38 | //#include "../../../platform/x86/intel_ips.h" |
||
39 | #include |
||
40 | //#include |
||
41 | //#include |
||
42 | //#include |
||
43 | //#include |
||
44 | //#include |
||
45 | //#include |
||
46 | |||
47 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); |
||
48 | |||
49 | static void i915_write_hws_pga(struct drm_device *dev) |
||
50 | { |
||
51 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
52 | u32 addr; |
||
53 | |||
54 | addr = dev_priv->status_page_dmah->busaddr; |
||
55 | if (INTEL_INFO(dev)->gen >= 4) |
||
56 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
||
57 | I915_WRITE(HWS_PGA, addr); |
||
58 | } |
||
59 | |||
60 | |||
61 | /** |
||
62 | * Sets up the hardware status page for devices that need a physical address |
||
63 | * in the register. |
||
64 | */ |
||
65 | static int i915_init_phys_hws(struct drm_device *dev) |
||
66 | { |
||
67 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
68 | |||
69 | /* Program Hardware Status Page */ |
||
70 | dev_priv->status_page_dmah = |
||
71 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
||
72 | |||
73 | if (!dev_priv->status_page_dmah) { |
||
74 | DRM_ERROR("Can not allocate hardware status page\n"); |
||
75 | return -ENOMEM; |
||
76 | } |
||
77 | |||
78 | i915_write_hws_pga(dev); |
||
79 | |||
80 | dbgprintf("Enabled hardware status page\n"); |
||
81 | return 0; |
||
82 | } |
||
83 | |||
2327 | Serge | 84 | static int i915_load_modeset_init(struct drm_device *dev) |
85 | { |
||
86 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
87 | int ret; |
||
88 | |||
89 | ret = intel_parse_bios(dev); |
||
90 | if (ret) |
||
91 | DRM_INFO("failed to find VBIOS tables\n"); |
||
92 | |||
93 | // intel_register_dsm_handler(); |
||
94 | |||
95 | /* IIR "flip pending" bit means done if this bit is set */ |
||
96 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) |
||
97 | dev_priv->flip_pending_is_done = true; |
||
98 | |||
99 | intel_modeset_init(dev); |
||
100 | |||
101 | #if 0 |
||
102 | |||
103 | ret = i915_load_gem_init(dev); |
||
104 | if (ret) |
||
105 | goto cleanup_vga_switcheroo; |
||
106 | |||
107 | intel_modeset_gem_init(dev); |
||
108 | |||
109 | ret = drm_irq_install(dev); |
||
110 | if (ret) |
||
111 | goto cleanup_gem; |
||
112 | |||
113 | /* Always safe in the mode setting case. */ |
||
114 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
||
115 | dev->vblank_disable_allowed = 1; |
||
116 | |||
117 | ret = intel_fbdev_init(dev); |
||
118 | if (ret) |
||
119 | goto cleanup_irq; |
||
120 | |||
121 | drm_kms_helper_poll_init(dev); |
||
122 | |||
123 | /* We're off and running w/KMS */ |
||
124 | dev_priv->mm.suspended = 0; |
||
125 | |||
126 | #endif |
||
127 | |||
128 | return 0; |
||
129 | |||
130 | cleanup_irq: |
||
131 | // drm_irq_uninstall(dev); |
||
132 | cleanup_gem: |
||
133 | // mutex_lock(&dev->struct_mutex); |
||
134 | // i915_gem_cleanup_ringbuffer(dev); |
||
135 | // mutex_unlock(&dev->struct_mutex); |
||
136 | cleanup_vga_switcheroo: |
||
137 | // vga_switcheroo_unregister_client(dev->pdev); |
||
138 | cleanup_vga_client: |
||
139 | // vga_client_register(dev->pdev, NULL, NULL, NULL); |
||
140 | out: |
||
141 | return ret; |
||
142 | } |
||
143 | |||
144 | |||
145 | |||
2326 | Serge | 146 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
147 | { |
||
148 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
149 | u32 tmp; |
||
150 | |||
151 | tmp = I915_READ(CLKCFG); |
||
152 | |||
153 | switch (tmp & CLKCFG_FSB_MASK) { |
||
154 | case CLKCFG_FSB_533: |
||
155 | dev_priv->fsb_freq = 533; /* 133*4 */ |
||
156 | break; |
||
157 | case CLKCFG_FSB_800: |
||
158 | dev_priv->fsb_freq = 800; /* 200*4 */ |
||
159 | break; |
||
160 | case CLKCFG_FSB_667: |
||
161 | dev_priv->fsb_freq = 667; /* 167*4 */ |
||
162 | break; |
||
163 | case CLKCFG_FSB_400: |
||
164 | dev_priv->fsb_freq = 400; /* 100*4 */ |
||
165 | break; |
||
166 | } |
||
167 | |||
168 | switch (tmp & CLKCFG_MEM_MASK) { |
||
169 | case CLKCFG_MEM_533: |
||
170 | dev_priv->mem_freq = 533; |
||
171 | break; |
||
172 | case CLKCFG_MEM_667: |
||
173 | dev_priv->mem_freq = 667; |
||
174 | break; |
||
175 | case CLKCFG_MEM_800: |
||
176 | dev_priv->mem_freq = 800; |
||
177 | break; |
||
178 | } |
||
179 | |||
180 | /* detect pineview DDR3 setting */ |
||
181 | tmp = I915_READ(CSHRDDR3CTL); |
||
182 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
||
183 | } |
||
184 | |||
185 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
||
186 | { |
||
187 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
188 | u16 ddrpll, csipll; |
||
189 | |||
190 | ddrpll = I915_READ16(DDRMPLL1); |
||
191 | csipll = I915_READ16(CSIPLL0); |
||
192 | |||
193 | switch (ddrpll & 0xff) { |
||
194 | case 0xc: |
||
195 | dev_priv->mem_freq = 800; |
||
196 | break; |
||
197 | case 0x10: |
||
198 | dev_priv->mem_freq = 1066; |
||
199 | break; |
||
200 | case 0x14: |
||
201 | dev_priv->mem_freq = 1333; |
||
202 | break; |
||
203 | case 0x18: |
||
204 | dev_priv->mem_freq = 1600; |
||
205 | break; |
||
206 | default: |
||
207 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
||
208 | ddrpll & 0xff); |
||
209 | dev_priv->mem_freq = 0; |
||
210 | break; |
||
211 | } |
||
212 | |||
213 | dev_priv->r_t = dev_priv->mem_freq; |
||
214 | |||
215 | switch (csipll & 0x3ff) { |
||
216 | case 0x00c: |
||
217 | dev_priv->fsb_freq = 3200; |
||
218 | break; |
||
219 | case 0x00e: |
||
220 | dev_priv->fsb_freq = 3733; |
||
221 | break; |
||
222 | case 0x010: |
||
223 | dev_priv->fsb_freq = 4266; |
||
224 | break; |
||
225 | case 0x012: |
||
226 | dev_priv->fsb_freq = 4800; |
||
227 | break; |
||
228 | case 0x014: |
||
229 | dev_priv->fsb_freq = 5333; |
||
230 | break; |
||
231 | case 0x016: |
||
232 | dev_priv->fsb_freq = 5866; |
||
233 | break; |
||
234 | case 0x018: |
||
235 | dev_priv->fsb_freq = 6400; |
||
236 | break; |
||
237 | default: |
||
238 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
||
239 | csipll & 0x3ff); |
||
240 | dev_priv->fsb_freq = 0; |
||
241 | break; |
||
242 | } |
||
243 | |||
244 | if (dev_priv->fsb_freq == 3200) { |
||
245 | dev_priv->c_m = 0; |
||
246 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
||
247 | dev_priv->c_m = 1; |
||
248 | } else { |
||
249 | dev_priv->c_m = 2; |
||
250 | } |
||
251 | } |
||
252 | |||
253 | static int i915_get_bridge_dev(struct drm_device *dev) |
||
254 | { |
||
255 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
256 | |||
257 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
||
258 | if (!dev_priv->bridge_dev) { |
||
259 | DRM_ERROR("bridge device not found\n"); |
||
260 | return -1; |
||
261 | } |
||
262 | return 0; |
||
263 | } |
||
264 | |||
265 | |||
266 | /* Global for IPS driver to get at the current i915 device */ |
||
267 | static struct drm_i915_private *i915_mch_dev; |
||
268 | /* |
||
269 | * Lock protecting IPS related data structures |
||
270 | * - i915_mch_dev |
||
271 | * - dev_priv->max_delay |
||
272 | * - dev_priv->min_delay |
||
273 | * - dev_priv->fmax |
||
274 | * - dev_priv->gpu_busy |
||
275 | */ |
||
276 | static DEFINE_SPINLOCK(mchdev_lock); |
||
277 | |||
278 | |||
279 | /** |
||
280 | * i915_driver_load - setup chip and create an initial config |
||
281 | * @dev: DRM device |
||
282 | * @flags: startup flags |
||
283 | * |
||
284 | * The driver load routine has to do several things: |
||
285 | * - drive output discovery via intel_modeset_init() |
||
286 | * - initialize the memory manager |
||
287 | * - allocate initial config memory |
||
288 | * - setup the DRM framebuffer with the allocated memory |
||
289 | */ |
||
290 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
||
291 | { |
||
292 | struct drm_i915_private *dev_priv; |
||
293 | int ret = 0, mmio_bar; |
||
294 | uint32_t agp_size; |
||
295 | |||
296 | ENTER(); |
||
297 | |||
298 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
||
299 | if (dev_priv == NULL) |
||
300 | return -ENOMEM; |
||
301 | |||
302 | dev->dev_private = (void *)dev_priv; |
||
303 | dev_priv->dev = dev; |
||
304 | dev_priv->info = (struct intel_device_info *) flags; |
||
305 | |||
306 | if (i915_get_bridge_dev(dev)) { |
||
307 | ret = -EIO; |
||
308 | goto free_priv; |
||
309 | } |
||
310 | |||
311 | /* overlay on gen2 is broken and can't address above 1G */ |
||
312 | // if (IS_GEN2(dev)) |
||
313 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
||
314 | |||
315 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
||
316 | * using 32bit addressing, overwriting memory if HWS is located |
||
317 | * above 4GB. |
||
318 | * |
||
319 | * The documentation also mentions an issue with undefined |
||
320 | * behaviour if any general state is accessed within a page above 4GB, |
||
321 | * which also needs to be handled carefully. |
||
322 | */ |
||
323 | // if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
||
324 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
||
325 | |||
326 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
||
327 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); |
||
328 | if (!dev_priv->regs) { |
||
329 | DRM_ERROR("failed to map registers\n"); |
||
330 | ret = -EIO; |
||
331 | goto put_bridge; |
||
332 | } |
||
333 | |||
334 | dev_priv->mm.gtt = intel_gtt_get(); |
||
335 | if (!dev_priv->mm.gtt) { |
||
336 | DRM_ERROR("Failed to initialize GTT\n"); |
||
337 | ret = -ENODEV; |
||
338 | goto out_rmmap; |
||
339 | } |
||
340 | |||
341 | // agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
||
342 | |||
343 | /* agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; */ |
||
344 | |||
345 | // dev_priv->mm.gtt_mapping = |
||
346 | // io_mapping_create_wc(dev->agp->base, agp_size); |
||
347 | // if (dev_priv->mm.gtt_mapping == NULL) { |
||
348 | // ret = -EIO; |
||
349 | // goto out_rmmap; |
||
350 | // } |
||
351 | |||
352 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
||
353 | * one would think, because the kernel disables PAT on first |
||
354 | * generation Core chips because WC PAT gets overridden by a UC |
||
355 | * MTRR if present. Even if a UC MTRR isn't present. |
||
356 | */ |
||
357 | // dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, |
||
358 | // agp_size, |
||
359 | // MTRR_TYPE_WRCOMB, 1); |
||
360 | // if (dev_priv->mm.gtt_mtrr < 0) { |
||
361 | // DRM_INFO("MTRR allocation failed. Graphics " |
||
362 | // "performance may suffer.\n"); |
||
363 | // } |
||
364 | |||
365 | /* The i915 workqueue is primarily used for batched retirement of |
||
366 | * requests (and thus managing bo) once the task has been completed |
||
367 | * by the GPU. i915_gem_retire_requests() is called directly when we |
||
368 | * need high-priority retirement, such as waiting for an explicit |
||
369 | * bo. |
||
370 | * |
||
371 | * It is also used for periodic low-priority events, such as |
||
372 | * idle-timers and recording error state. |
||
373 | * |
||
374 | * All tasks on the workqueue are expected to acquire the dev mutex |
||
375 | * so there is no point in running more than one instance of the |
||
376 | * workqueue at any time: max_active = 1 and NON_REENTRANT. |
||
377 | */ |
||
378 | |||
379 | // dev_priv->wq = alloc_workqueue("i915", |
||
380 | // WQ_UNBOUND | WQ_NON_REENTRANT, |
||
381 | // 1); |
||
382 | // if (dev_priv->wq == NULL) { |
||
383 | // DRM_ERROR("Failed to create our workqueue.\n"); |
||
384 | // ret = -ENOMEM; |
||
385 | // goto out_mtrrfree; |
||
386 | // } |
||
387 | |||
388 | /* enable GEM by default */ |
||
389 | dev_priv->has_gem = 1; |
||
390 | |||
391 | |||
392 | // intel_irq_init(dev); |
||
393 | |||
394 | /* Try to make sure MCHBAR is enabled before poking at it */ |
||
395 | // intel_setup_mchbar(dev); |
||
396 | intel_setup_gmbus(dev); |
||
397 | |||
2327 | Serge | 398 | intel_opregion_setup(dev); |
2326 | Serge | 399 | |
400 | /* Make sure the bios did its job and set up vital registers */ |
||
401 | // intel_setup_bios(dev); |
||
402 | |||
403 | i915_gem_load(dev); |
||
404 | |||
405 | /* Init HWS */ |
||
406 | if (!I915_NEED_GFX_HWS(dev)) { |
||
407 | ret = i915_init_phys_hws(dev); |
||
408 | if (ret) |
||
409 | goto out_gem_unload; |
||
410 | } |
||
411 | |||
412 | if (IS_PINEVIEW(dev)) |
||
413 | i915_pineview_get_mem_freq(dev); |
||
414 | else if (IS_GEN5(dev)) |
||
415 | i915_ironlake_get_mem_freq(dev); |
||
416 | |||
417 | /* On the 945G/GM, the chipset reports the MSI capability on the |
||
418 | * integrated graphics even though the support isn't actually there |
||
419 | * according to the published specs. It doesn't appear to function |
||
420 | * correctly in testing on 945G. |
||
421 | * This may be a side effect of MSI having been made available for PEG |
||
422 | * and the registers being closely associated. |
||
423 | * |
||
424 | * According to chipset errata, on the 965GM, MSI interrupts may |
||
425 | * be lost or delayed, but we use them anyways to avoid |
||
426 | * stuck interrupts on some machines. |
||
427 | */ |
||
428 | // if (!IS_I945G(dev) && !IS_I945GM(dev)) |
||
429 | // pci_enable_msi(dev->pdev); |
||
430 | |||
431 | spin_lock_init(&dev_priv->irq_lock); |
||
432 | spin_lock_init(&dev_priv->error_lock); |
||
433 | spin_lock_init(&dev_priv->rps_lock); |
||
434 | |||
435 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
||
436 | dev_priv->num_pipe = 2; |
||
437 | else |
||
438 | dev_priv->num_pipe = 1; |
||
439 | |||
440 | // ret = drm_vblank_init(dev, dev_priv->num_pipe); |
||
441 | // if (ret) |
||
442 | // goto out_gem_unload; |
||
443 | |||
444 | /* Start out suspended */ |
||
445 | dev_priv->mm.suspended = 1; |
||
446 | |||
447 | intel_detect_pch(dev); |
||
448 | |||
2327 | Serge | 449 | ret = i915_load_modeset_init(dev); |
450 | if (ret < 0) { |
||
451 | DRM_ERROR("failed to init modeset\n"); |
||
452 | goto out_gem_unload; |
||
453 | } |
||
2326 | Serge | 454 | |
455 | /* Must be done after probing outputs */ |
||
456 | // intel_opregion_init(dev); |
||
457 | // acpi_video_register(); |
||
458 | |||
459 | // setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
||
460 | // (unsigned long) dev); |
||
461 | |||
462 | spin_lock(&mchdev_lock); |
||
463 | i915_mch_dev = dev_priv; |
||
464 | dev_priv->mchdev_lock = &mchdev_lock; |
||
465 | spin_unlock(&mchdev_lock); |
||
466 | |||
467 | // ips_ping_for_i915_load(); |
||
468 | |||
469 | LEAVE(); |
||
470 | |||
471 | return 0; |
||
472 | |||
473 | out_gem_unload: |
||
474 | // if (dev_priv->mm.inactive_shrinker.shrink) |
||
475 | // unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
||
476 | |||
477 | // if (dev->pdev->msi_enabled) |
||
478 | // pci_disable_msi(dev->pdev); |
||
479 | |||
480 | // intel_teardown_gmbus(dev); |
||
481 | // intel_teardown_mchbar(dev); |
||
482 | // destroy_workqueue(dev_priv->wq); |
||
483 | out_mtrrfree: |
||
484 | // if (dev_priv->mm.gtt_mtrr >= 0) { |
||
485 | // mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, |
||
486 | // dev->agp->agp_info.aper_size * 1024 * 1024); |
||
487 | // dev_priv->mm.gtt_mtrr = -1; |
||
488 | // } |
||
489 | // io_mapping_free(dev_priv->mm.gtt_mapping); |
||
490 | |||
491 | out_rmmap: |
||
492 | pci_iounmap(dev->pdev, dev_priv->regs); |
||
493 | |||
494 | put_bridge: |
||
495 | // pci_dev_put(dev_priv->bridge_dev); |
||
496 | free_priv: |
||
497 | kfree(dev_priv); |
||
498 | return ret; |
||
499 | }>>><>=> |
||
500 |