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5060 | serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Brad Volkin |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "i915_drv.h" |
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29 | |||
30 | /** |
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31 | * DOC: batch buffer command parser |
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32 | * |
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33 | * Motivation: |
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34 | * Certain OpenGL features (e.g. transform feedback, performance monitoring) |
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35 | * require userspace code to submit batches containing commands such as |
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36 | * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some |
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37 | * generations of the hardware will noop these commands in "unsecure" batches |
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38 | * (which includes all userspace batches submitted via i915) even though the |
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39 | * commands may be safe and represent the intended programming model of the |
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40 | * device. |
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41 | * |
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42 | * The software command parser is similar in operation to the command parsing |
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43 | * done in hardware for unsecure batches. However, the software parser allows |
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44 | * some operations that would be noop'd by hardware, if the parser determines |
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45 | * the operation is safe, and submits the batch as "secure" to prevent hardware |
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46 | * parsing. |
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47 | * |
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48 | * Threats: |
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49 | * At a high level, the hardware (and software) checks attempt to prevent |
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50 | * granting userspace undue privileges. There are three categories of privilege. |
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51 | * |
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52 | * First, commands which are explicitly defined as privileged or which should |
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53 | * only be used by the kernel driver. The parser generally rejects such |
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54 | * commands, though it may allow some from the drm master process. |
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55 | * |
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56 | * Second, commands which access registers. To support correct/enhanced |
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57 | * userspace functionality, particularly certain OpenGL extensions, the parser |
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58 | * provides a whitelist of registers which userspace may safely access (for both |
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59 | * normal and drm master processes). |
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60 | * |
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61 | * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). |
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62 | * The parser always rejects such commands. |
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63 | * |
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64 | * The majority of the problematic commands fall in the MI_* range, with only a |
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65 | * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). |
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66 | * |
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67 | * Implementation: |
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68 | * Each ring maintains tables of commands and registers which the parser uses in |
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69 | * scanning batch buffers submitted to that ring. |
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70 | * |
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71 | * Since the set of commands that the parser must check for is significantly |
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72 | * smaller than the number of commands supported, the parser tables contain only |
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73 | * those commands required by the parser. This generally works because command |
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74 | * opcode ranges have standard command length encodings. So for commands that |
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75 | * the parser does not need to check, it can easily skip them. This is |
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5354 | serge | 76 | * implemented via a per-ring length decoding vfunc. |
5060 | serge | 77 | * |
78 | * Unfortunately, there are a number of commands that do not follow the standard |
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79 | * length encoding for their opcode range, primarily amongst the MI_* commands. |
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80 | * To handle this, the parser provides a way to define explicit "skip" entries |
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81 | * in the per-ring command tables. |
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82 | * |
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83 | * Other command table entries map fairly directly to high level categories |
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84 | * mentioned above: rejected, master-only, register whitelist. The parser |
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85 | * implements a number of checks, including the privileged memory checks, via a |
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86 | * general bitmasking mechanism. |
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87 | */ |
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88 | |||
89 | #define STD_MI_OPCODE_MASK 0xFF800000 |
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90 | #define STD_3D_OPCODE_MASK 0xFFFF0000 |
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91 | #define STD_2D_OPCODE_MASK 0xFFC00000 |
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92 | #define STD_MFX_OPCODE_MASK 0xFFFF0000 |
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93 | |||
94 | #define CMD(op, opm, f, lm, fl, ...) \ |
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95 | { \ |
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96 | .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ |
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97 | .cmd = { (op), (opm) }, \ |
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98 | .length = { (lm) }, \ |
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99 | __VA_ARGS__ \ |
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100 | } |
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101 | |||
102 | /* Convenience macros to compress the tables */ |
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103 | #define SMI STD_MI_OPCODE_MASK |
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104 | #define S3D STD_3D_OPCODE_MASK |
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105 | #define S2D STD_2D_OPCODE_MASK |
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106 | #define SMFX STD_MFX_OPCODE_MASK |
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107 | #define F true |
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108 | #define S CMD_DESC_SKIP |
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109 | #define R CMD_DESC_REJECT |
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110 | #define W CMD_DESC_REGISTER |
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111 | #define B CMD_DESC_BITMASK |
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112 | #define M CMD_DESC_MASTER |
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113 | |||
114 | /* Command Mask Fixed Len Action |
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115 | ---------------------------------------------------------- */ |
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116 | static const struct drm_i915_cmd_descriptor common_cmds[] = { |
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117 | CMD( MI_NOOP, SMI, F, 1, S ), |
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118 | CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), |
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119 | CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), |
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120 | CMD( MI_ARB_CHECK, SMI, F, 1, S ), |
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121 | CMD( MI_REPORT_HEAD, SMI, F, 1, S ), |
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122 | CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), |
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123 | CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), |
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124 | CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), |
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125 | CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, |
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126 | .reg = { .offset = 1, .mask = 0x007FFFFC } ), |
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127 | CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B, |
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128 | .reg = { .offset = 1, .mask = 0x007FFFFC }, |
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129 | .bits = {{ |
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130 | .offset = 0, |
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131 | .mask = MI_GLOBAL_GTT, |
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132 | .expected = 0, |
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133 | }}, ), |
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134 | CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B, |
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135 | .reg = { .offset = 1, .mask = 0x007FFFFC }, |
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136 | .bits = {{ |
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137 | .offset = 0, |
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138 | .mask = MI_GLOBAL_GTT, |
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139 | .expected = 0, |
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140 | }}, ), |
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5354 | serge | 141 | /* |
142 | * MI_BATCH_BUFFER_START requires some special handling. It's not |
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143 | * really a 'skip' action but it doesn't seem like it's worth adding |
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144 | * a new action. See i915_parse_cmds(). |
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145 | */ |
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5060 | serge | 146 | CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), |
147 | }; |
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148 | |||
149 | static const struct drm_i915_cmd_descriptor render_cmds[] = { |
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150 | CMD( MI_FLUSH, SMI, F, 1, S ), |
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151 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
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152 | CMD( MI_PREDICATE, SMI, F, 1, S ), |
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153 | CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), |
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154 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
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155 | CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), |
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156 | CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), |
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157 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, |
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158 | .bits = {{ |
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159 | .offset = 0, |
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160 | .mask = MI_GLOBAL_GTT, |
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161 | .expected = 0, |
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162 | }}, ), |
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163 | CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), |
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164 | CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, |
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165 | .bits = {{ |
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166 | .offset = 0, |
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167 | .mask = MI_GLOBAL_GTT, |
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168 | .expected = 0, |
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169 | }}, ), |
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170 | CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, |
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171 | .bits = {{ |
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172 | .offset = 1, |
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173 | .mask = MI_REPORT_PERF_COUNT_GGTT, |
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174 | .expected = 0, |
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175 | }}, ), |
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176 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, |
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177 | .bits = {{ |
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178 | .offset = 0, |
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179 | .mask = MI_GLOBAL_GTT, |
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180 | .expected = 0, |
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181 | }}, ), |
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182 | CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), |
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183 | CMD( PIPELINE_SELECT, S3D, F, 1, S ), |
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184 | CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, |
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185 | .bits = {{ |
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186 | .offset = 2, |
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187 | .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, |
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188 | .expected = 0, |
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189 | }}, ), |
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190 | CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), |
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191 | CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), |
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192 | CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), |
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193 | CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, |
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194 | .bits = {{ |
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195 | .offset = 1, |
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196 | .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), |
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197 | .expected = 0, |
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198 | }, |
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199 | { |
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200 | .offset = 1, |
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201 | .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | |
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202 | PIPE_CONTROL_STORE_DATA_INDEX), |
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203 | .expected = 0, |
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204 | .condition_offset = 1, |
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205 | .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, |
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206 | }}, ), |
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207 | }; |
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208 | |||
209 | static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { |
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210 | CMD( MI_SET_PREDICATE, SMI, F, 1, S ), |
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211 | CMD( MI_RS_CONTROL, SMI, F, 1, S ), |
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212 | CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), |
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213 | CMD( MI_RS_CONTEXT, SMI, F, 1, S ), |
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214 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
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215 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
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216 | CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), |
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217 | CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), |
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218 | CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), |
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219 | CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), |
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220 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), |
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221 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), |
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222 | |||
223 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), |
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224 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), |
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225 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), |
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226 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), |
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227 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), |
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228 | }; |
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229 | |||
230 | static const struct drm_i915_cmd_descriptor video_cmds[] = { |
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231 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
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232 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
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233 | .bits = {{ |
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234 | .offset = 0, |
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235 | .mask = MI_GLOBAL_GTT, |
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236 | .expected = 0, |
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237 | }}, ), |
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238 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
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239 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
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240 | .bits = {{ |
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241 | .offset = 0, |
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242 | .mask = MI_FLUSH_DW_NOTIFY, |
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243 | .expected = 0, |
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244 | }, |
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245 | { |
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246 | .offset = 1, |
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247 | .mask = MI_FLUSH_DW_USE_GTT, |
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248 | .expected = 0, |
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249 | .condition_offset = 0, |
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250 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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251 | }, |
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252 | { |
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253 | .offset = 0, |
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254 | .mask = MI_FLUSH_DW_STORE_INDEX, |
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255 | .expected = 0, |
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256 | .condition_offset = 0, |
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257 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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258 | }}, ), |
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259 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, |
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260 | .bits = {{ |
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261 | .offset = 0, |
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262 | .mask = MI_GLOBAL_GTT, |
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263 | .expected = 0, |
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264 | }}, ), |
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265 | /* |
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266 | * MFX_WAIT doesn't fit the way we handle length for most commands. |
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267 | * It has a length field but it uses a non-standard length bias. |
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268 | * It is always 1 dword though, so just treat it as fixed length. |
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269 | */ |
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270 | CMD( MFX_WAIT, SMFX, F, 1, S ), |
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271 | }; |
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272 | |||
273 | static const struct drm_i915_cmd_descriptor vecs_cmds[] = { |
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274 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
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275 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
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276 | .bits = {{ |
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277 | .offset = 0, |
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278 | .mask = MI_GLOBAL_GTT, |
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279 | .expected = 0, |
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280 | }}, ), |
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281 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
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282 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
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283 | .bits = {{ |
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284 | .offset = 0, |
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285 | .mask = MI_FLUSH_DW_NOTIFY, |
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286 | .expected = 0, |
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287 | }, |
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288 | { |
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289 | .offset = 1, |
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290 | .mask = MI_FLUSH_DW_USE_GTT, |
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291 | .expected = 0, |
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292 | .condition_offset = 0, |
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293 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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294 | }, |
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295 | { |
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296 | .offset = 0, |
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297 | .mask = MI_FLUSH_DW_STORE_INDEX, |
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298 | .expected = 0, |
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299 | .condition_offset = 0, |
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300 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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301 | }}, ), |
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302 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, |
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303 | .bits = {{ |
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304 | .offset = 0, |
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305 | .mask = MI_GLOBAL_GTT, |
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306 | .expected = 0, |
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307 | }}, ), |
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308 | }; |
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309 | |||
310 | static const struct drm_i915_cmd_descriptor blt_cmds[] = { |
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311 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
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312 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, |
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313 | .bits = {{ |
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314 | .offset = 0, |
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315 | .mask = MI_GLOBAL_GTT, |
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316 | .expected = 0, |
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317 | }}, ), |
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318 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
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319 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
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320 | .bits = {{ |
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321 | .offset = 0, |
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322 | .mask = MI_FLUSH_DW_NOTIFY, |
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323 | .expected = 0, |
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324 | }, |
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325 | { |
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326 | .offset = 1, |
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327 | .mask = MI_FLUSH_DW_USE_GTT, |
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328 | .expected = 0, |
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329 | .condition_offset = 0, |
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330 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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331 | }, |
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332 | { |
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333 | .offset = 0, |
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334 | .mask = MI_FLUSH_DW_STORE_INDEX, |
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335 | .expected = 0, |
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336 | .condition_offset = 0, |
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337 | .condition_mask = MI_FLUSH_DW_OP_MASK, |
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338 | }}, ), |
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339 | CMD( COLOR_BLT, S2D, !F, 0x3F, S ), |
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340 | CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), |
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341 | }; |
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342 | |||
343 | static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { |
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344 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
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345 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
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346 | }; |
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347 | |||
348 | #undef CMD |
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349 | #undef SMI |
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350 | #undef S3D |
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351 | #undef S2D |
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352 | #undef SMFX |
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353 | #undef F |
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354 | #undef S |
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355 | #undef R |
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356 | #undef W |
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357 | #undef B |
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358 | #undef M |
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359 | |||
360 | static const struct drm_i915_cmd_table gen7_render_cmds[] = { |
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361 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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362 | { render_cmds, ARRAY_SIZE(render_cmds) }, |
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363 | }; |
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364 | |||
365 | static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { |
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366 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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367 | { render_cmds, ARRAY_SIZE(render_cmds) }, |
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368 | { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, |
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369 | }; |
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370 | |||
371 | static const struct drm_i915_cmd_table gen7_video_cmds[] = { |
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372 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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373 | { video_cmds, ARRAY_SIZE(video_cmds) }, |
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374 | }; |
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375 | |||
376 | static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { |
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377 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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378 | { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, |
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379 | }; |
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380 | |||
381 | static const struct drm_i915_cmd_table gen7_blt_cmds[] = { |
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382 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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383 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, |
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384 | }; |
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385 | |||
386 | static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { |
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387 | { common_cmds, ARRAY_SIZE(common_cmds) }, |
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388 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, |
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389 | { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, |
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390 | }; |
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391 | |||
392 | /* |
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393 | * Register whitelists, sorted by increasing register offset. |
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394 | * |
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395 | * Some registers that userspace accesses are 64 bits. The register |
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396 | * access commands only allow 32-bit accesses. Hence, we have to include |
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397 | * entries for both halves of the 64-bit registers. |
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398 | */ |
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399 | |||
400 | /* Convenience macro for adding 64-bit registers */ |
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401 | #define REG64(addr) (addr), (addr + sizeof(u32)) |
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402 | |||
403 | static const u32 gen7_render_regs[] = { |
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404 | REG64(HS_INVOCATION_COUNT), |
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405 | REG64(DS_INVOCATION_COUNT), |
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406 | REG64(IA_VERTICES_COUNT), |
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407 | REG64(IA_PRIMITIVES_COUNT), |
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408 | REG64(VS_INVOCATION_COUNT), |
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409 | REG64(GS_INVOCATION_COUNT), |
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410 | REG64(GS_PRIMITIVES_COUNT), |
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411 | REG64(CL_INVOCATION_COUNT), |
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412 | REG64(CL_PRIMITIVES_COUNT), |
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413 | REG64(PS_INVOCATION_COUNT), |
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414 | REG64(PS_DEPTH_COUNT), |
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415 | OACONTROL, /* Only allowed for LRI and SRM. See below. */ |
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5354 | serge | 416 | REG64(MI_PREDICATE_SRC0), |
417 | REG64(MI_PREDICATE_SRC1), |
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5060 | serge | 418 | GEN7_3DPRIM_END_OFFSET, |
419 | GEN7_3DPRIM_START_VERTEX, |
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420 | GEN7_3DPRIM_VERTEX_COUNT, |
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421 | GEN7_3DPRIM_INSTANCE_COUNT, |
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422 | GEN7_3DPRIM_START_INSTANCE, |
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423 | GEN7_3DPRIM_BASE_VERTEX, |
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424 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), |
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425 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), |
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426 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), |
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427 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), |
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428 | REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), |
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429 | REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), |
||
430 | REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), |
||
431 | REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), |
||
432 | GEN7_SO_WRITE_OFFSET(0), |
||
433 | GEN7_SO_WRITE_OFFSET(1), |
||
434 | GEN7_SO_WRITE_OFFSET(2), |
||
435 | GEN7_SO_WRITE_OFFSET(3), |
||
436 | GEN7_L3SQCREG1, |
||
437 | GEN7_L3CNTLREG2, |
||
438 | GEN7_L3CNTLREG3, |
||
439 | }; |
||
440 | |||
441 | static const u32 gen7_blt_regs[] = { |
||
442 | BCS_SWCTRL, |
||
443 | }; |
||
444 | |||
445 | static const u32 ivb_master_regs[] = { |
||
446 | FORCEWAKE_MT, |
||
447 | DERRMR, |
||
448 | GEN7_PIPE_DE_LOAD_SL(PIPE_A), |
||
449 | GEN7_PIPE_DE_LOAD_SL(PIPE_B), |
||
450 | GEN7_PIPE_DE_LOAD_SL(PIPE_C), |
||
451 | }; |
||
452 | |||
453 | static const u32 hsw_master_regs[] = { |
||
454 | FORCEWAKE_MT, |
||
455 | DERRMR, |
||
456 | }; |
||
457 | |||
458 | #undef REG64 |
||
459 | |||
460 | static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) |
||
461 | { |
||
462 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; |
||
463 | u32 subclient = |
||
464 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; |
||
465 | |||
466 | if (client == INSTR_MI_CLIENT) |
||
467 | return 0x3F; |
||
468 | else if (client == INSTR_RC_CLIENT) { |
||
469 | if (subclient == INSTR_MEDIA_SUBCLIENT) |
||
470 | return 0xFFFF; |
||
471 | else |
||
472 | return 0xFF; |
||
473 | } |
||
474 | |||
475 | DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); |
||
476 | return 0; |
||
477 | } |
||
478 | |||
479 | static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) |
||
480 | { |
||
481 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; |
||
482 | u32 subclient = |
||
483 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; |
||
484 | |||
485 | if (client == INSTR_MI_CLIENT) |
||
486 | return 0x3F; |
||
487 | else if (client == INSTR_RC_CLIENT) { |
||
488 | if (subclient == INSTR_MEDIA_SUBCLIENT) |
||
489 | return 0xFFF; |
||
490 | else |
||
491 | return 0xFF; |
||
492 | } |
||
493 | |||
494 | DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); |
||
495 | return 0; |
||
496 | } |
||
497 | |||
498 | static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) |
||
499 | { |
||
500 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; |
||
501 | |||
502 | if (client == INSTR_MI_CLIENT) |
||
503 | return 0x3F; |
||
504 | else if (client == INSTR_BC_CLIENT) |
||
505 | return 0xFF; |
||
506 | |||
507 | DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); |
||
508 | return 0; |
||
509 | } |
||
510 | |||
511 | static bool validate_cmds_sorted(struct intel_engine_cs *ring, |
||
512 | const struct drm_i915_cmd_table *cmd_tables, |
||
513 | int cmd_table_count) |
||
514 | { |
||
515 | int i; |
||
516 | bool ret = true; |
||
517 | |||
518 | if (!cmd_tables || cmd_table_count == 0) |
||
519 | return true; |
||
520 | |||
521 | for (i = 0; i < cmd_table_count; i++) { |
||
522 | const struct drm_i915_cmd_table *table = &cmd_tables[i]; |
||
523 | u32 previous = 0; |
||
524 | int j; |
||
525 | |||
526 | for (j = 0; j < table->count; j++) { |
||
527 | const struct drm_i915_cmd_descriptor *desc = |
||
528 | &table->table[i]; |
||
529 | u32 curr = desc->cmd.value & desc->cmd.mask; |
||
530 | |||
531 | if (curr < previous) { |
||
532 | DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", |
||
533 | ring->id, i, j, curr, previous); |
||
534 | ret = false; |
||
535 | } |
||
536 | |||
537 | previous = curr; |
||
538 | } |
||
539 | } |
||
540 | |||
541 | return ret; |
||
542 | } |
||
543 | |||
544 | static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count) |
||
545 | { |
||
546 | int i; |
||
547 | u32 previous = 0; |
||
548 | bool ret = true; |
||
549 | |||
550 | for (i = 0; i < reg_count; i++) { |
||
551 | u32 curr = reg_table[i]; |
||
552 | |||
553 | if (curr < previous) { |
||
554 | DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", |
||
555 | ring_id, i, curr, previous); |
||
556 | ret = false; |
||
557 | } |
||
558 | |||
559 | previous = curr; |
||
560 | } |
||
561 | |||
562 | return ret; |
||
563 | } |
||
564 | |||
565 | static bool validate_regs_sorted(struct intel_engine_cs *ring) |
||
566 | { |
||
567 | return check_sorted(ring->id, ring->reg_table, ring->reg_count) && |
||
568 | check_sorted(ring->id, ring->master_reg_table, |
||
569 | ring->master_reg_count); |
||
570 | } |
||
571 | |||
572 | struct cmd_node { |
||
573 | const struct drm_i915_cmd_descriptor *desc; |
||
574 | struct hlist_node node; |
||
575 | }; |
||
576 | |||
577 | /* |
||
578 | * Different command ranges have different numbers of bits for the opcode. For |
||
579 | * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The |
||
580 | * problem is that, for example, MI commands use bits 22:16 for other fields |
||
581 | * such as GGTT vs PPGTT bits. If we include those bits in the mask then when |
||
582 | * we mask a command from a batch it could hash to the wrong bucket due to |
||
583 | * non-opcode bits being set. But if we don't include those bits, some 3D |
||
584 | * commands may hash to the same bucket due to not including opcode bits that |
||
585 | * make the command unique. For now, we will risk hashing to the same bucket. |
||
586 | * |
||
587 | * If we attempt to generate a perfect hash, we should be able to look at bits |
||
588 | * 31:29 of a command from a batch buffer and use the full mask for that |
||
589 | * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. |
||
590 | */ |
||
591 | #define CMD_HASH_MASK STD_MI_OPCODE_MASK |
||
592 | |||
593 | static int init_hash_table(struct intel_engine_cs *ring, |
||
594 | const struct drm_i915_cmd_table *cmd_tables, |
||
595 | int cmd_table_count) |
||
596 | { |
||
597 | int i, j; |
||
598 | |||
599 | hash_init(ring->cmd_hash); |
||
600 | |||
601 | for (i = 0; i < cmd_table_count; i++) { |
||
602 | const struct drm_i915_cmd_table *table = &cmd_tables[i]; |
||
603 | |||
604 | for (j = 0; j < table->count; j++) { |
||
605 | const struct drm_i915_cmd_descriptor *desc = |
||
606 | &table->table[j]; |
||
607 | struct cmd_node *desc_node = |
||
608 | kmalloc(sizeof(*desc_node), GFP_KERNEL); |
||
609 | |||
610 | if (!desc_node) |
||
611 | return -ENOMEM; |
||
612 | |||
613 | desc_node->desc = desc; |
||
614 | hash_add(ring->cmd_hash, &desc_node->node, |
||
615 | desc->cmd.value & CMD_HASH_MASK); |
||
616 | } |
||
617 | } |
||
618 | |||
619 | return 0; |
||
620 | } |
||
621 | |||
622 | static void fini_hash_table(struct intel_engine_cs *ring) |
||
623 | { |
||
624 | struct hlist_node *tmp; |
||
625 | struct cmd_node *desc_node; |
||
626 | int i; |
||
627 | |||
628 | hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) { |
||
629 | hash_del(&desc_node->node); |
||
630 | kfree(desc_node); |
||
631 | } |
||
632 | } |
||
633 | |||
634 | /** |
||
635 | * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer |
||
636 | * @ring: the ringbuffer to initialize |
||
637 | * |
||
638 | * Optionally initializes fields related to batch buffer command parsing in the |
||
639 | * struct intel_engine_cs based on whether the platform requires software |
||
640 | * command parsing. |
||
641 | * |
||
642 | * Return: non-zero if initialization fails |
||
643 | */ |
||
644 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring) |
||
645 | { |
||
646 | const struct drm_i915_cmd_table *cmd_tables; |
||
647 | int cmd_table_count; |
||
648 | int ret; |
||
649 | |||
650 | if (!IS_GEN7(ring->dev)) |
||
651 | return 0; |
||
652 | |||
653 | switch (ring->id) { |
||
654 | case RCS: |
||
655 | if (IS_HASWELL(ring->dev)) { |
||
656 | cmd_tables = hsw_render_ring_cmds; |
||
657 | cmd_table_count = |
||
658 | ARRAY_SIZE(hsw_render_ring_cmds); |
||
659 | } else { |
||
660 | cmd_tables = gen7_render_cmds; |
||
661 | cmd_table_count = ARRAY_SIZE(gen7_render_cmds); |
||
662 | } |
||
663 | |||
664 | ring->reg_table = gen7_render_regs; |
||
665 | ring->reg_count = ARRAY_SIZE(gen7_render_regs); |
||
666 | |||
667 | if (IS_HASWELL(ring->dev)) { |
||
668 | ring->master_reg_table = hsw_master_regs; |
||
669 | ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); |
||
670 | } else { |
||
671 | ring->master_reg_table = ivb_master_regs; |
||
672 | ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); |
||
673 | } |
||
674 | |||
675 | ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; |
||
676 | break; |
||
677 | case VCS: |
||
678 | cmd_tables = gen7_video_cmds; |
||
679 | cmd_table_count = ARRAY_SIZE(gen7_video_cmds); |
||
680 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
||
681 | break; |
||
682 | case BCS: |
||
683 | if (IS_HASWELL(ring->dev)) { |
||
684 | cmd_tables = hsw_blt_ring_cmds; |
||
685 | cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); |
||
686 | } else { |
||
687 | cmd_tables = gen7_blt_cmds; |
||
688 | cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); |
||
689 | } |
||
690 | |||
691 | ring->reg_table = gen7_blt_regs; |
||
692 | ring->reg_count = ARRAY_SIZE(gen7_blt_regs); |
||
693 | |||
694 | if (IS_HASWELL(ring->dev)) { |
||
695 | ring->master_reg_table = hsw_master_regs; |
||
696 | ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); |
||
697 | } else { |
||
698 | ring->master_reg_table = ivb_master_regs; |
||
699 | ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); |
||
700 | } |
||
701 | |||
702 | ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; |
||
703 | break; |
||
704 | case VECS: |
||
705 | cmd_tables = hsw_vebox_cmds; |
||
706 | cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); |
||
707 | /* VECS can use the same length_mask function as VCS */ |
||
708 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
||
709 | break; |
||
710 | default: |
||
711 | DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", |
||
712 | ring->id); |
||
713 | BUG(); |
||
714 | } |
||
715 | |||
716 | BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count)); |
||
717 | BUG_ON(!validate_regs_sorted(ring)); |
||
718 | |||
5354 | serge | 719 | if (hash_empty(ring->cmd_hash)) { |
5060 | serge | 720 | ret = init_hash_table(ring, cmd_tables, cmd_table_count); |
721 | if (ret) { |
||
722 | DRM_ERROR("CMD: cmd_parser_init failed!\n"); |
||
723 | fini_hash_table(ring); |
||
724 | return ret; |
||
725 | } |
||
5354 | serge | 726 | } |
5060 | serge | 727 | |
728 | ring->needs_cmd_parser = true; |
||
729 | |||
730 | return 0; |
||
731 | } |
||
732 | |||
733 | /** |
||
734 | * i915_cmd_parser_fini_ring() - clean up cmd parser related fields |
||
735 | * @ring: the ringbuffer to clean up |
||
736 | * |
||
737 | * Releases any resources related to command parsing that may have been |
||
738 | * initialized for the specified ring. |
||
739 | */ |
||
740 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring) |
||
741 | { |
||
742 | if (!ring->needs_cmd_parser) |
||
743 | return; |
||
744 | |||
745 | fini_hash_table(ring); |
||
746 | } |
||
747 | |||
748 | static const struct drm_i915_cmd_descriptor* |
||
749 | find_cmd_in_table(struct intel_engine_cs *ring, |
||
750 | u32 cmd_header) |
||
751 | { |
||
752 | struct cmd_node *desc_node; |
||
753 | |||
754 | hash_for_each_possible(ring->cmd_hash, desc_node, node, |
||
755 | cmd_header & CMD_HASH_MASK) { |
||
756 | const struct drm_i915_cmd_descriptor *desc = desc_node->desc; |
||
757 | u32 masked_cmd = desc->cmd.mask & cmd_header; |
||
758 | u32 masked_value = desc->cmd.value & desc->cmd.mask; |
||
759 | |||
760 | if (masked_cmd == masked_value) |
||
761 | return desc; |
||
762 | } |
||
763 | |||
764 | return NULL; |
||
765 | } |
||
766 | |||
767 | /* |
||
768 | * Returns a pointer to a descriptor for the command specified by cmd_header. |
||
769 | * |
||
770 | * The caller must supply space for a default descriptor via the default_desc |
||
771 | * parameter. If no descriptor for the specified command exists in the ring's |
||
772 | * command parser tables, this function fills in default_desc based on the |
||
773 | * ring's default length encoding and returns default_desc. |
||
774 | */ |
||
775 | static const struct drm_i915_cmd_descriptor* |
||
776 | find_cmd(struct intel_engine_cs *ring, |
||
777 | u32 cmd_header, |
||
778 | struct drm_i915_cmd_descriptor *default_desc) |
||
779 | { |
||
780 | const struct drm_i915_cmd_descriptor *desc; |
||
781 | u32 mask; |
||
782 | |||
783 | desc = find_cmd_in_table(ring, cmd_header); |
||
784 | if (desc) |
||
785 | return desc; |
||
786 | |||
787 | mask = ring->get_cmd_length_mask(cmd_header); |
||
788 | if (!mask) |
||
789 | return NULL; |
||
790 | |||
791 | BUG_ON(!default_desc); |
||
792 | default_desc->flags = CMD_DESC_SKIP; |
||
793 | default_desc->length.mask = mask; |
||
794 | |||
795 | return default_desc; |
||
796 | } |
||
797 | |||
798 | static bool valid_reg(const u32 *table, int count, u32 addr) |
||
799 | { |
||
800 | if (table && count != 0) { |
||
801 | int i; |
||
802 | |||
803 | for (i = 0; i < count; i++) { |
||
804 | if (table[i] == addr) |
||
805 | return true; |
||
806 | } |
||
807 | } |
||
808 | |||
809 | return false; |
||
810 | } |
||
811 | |||
812 | static u32 *vmap_batch(struct drm_i915_gem_object *obj) |
||
813 | { |
||
814 | int i; |
||
815 | void *addr = NULL; |
||
816 | struct sg_page_iter sg_iter; |
||
817 | struct page **pages; |
||
818 | |||
819 | pages = kmalloc(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); |
||
820 | if (pages == NULL) { |
||
821 | DRM_DEBUG_DRIVER("Failed to get space for pages\n"); |
||
822 | goto finish; |
||
823 | } |
||
824 | |||
825 | i = 0; |
||
826 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
||
827 | pages[i] = sg_page_iter_page(&sg_iter); |
||
828 | i++; |
||
829 | } |
||
830 | |||
831 | // addr = vmap(pages, i, 0, PAGE_KERNEL); |
||
832 | if (addr == NULL) { |
||
833 | DRM_DEBUG_DRIVER("Failed to vmap pages\n"); |
||
834 | goto finish; |
||
835 | } |
||
836 | |||
837 | finish: |
||
838 | if (pages) |
||
839 | free(pages); |
||
840 | return (u32*)addr; |
||
841 | } |
||
842 | |||
843 | /** |
||
844 | * i915_needs_cmd_parser() - should a given ring use software command parsing? |
||
845 | * @ring: the ring in question |
||
846 | * |
||
847 | * Only certain platforms require software batch buffer command parsing, and |
||
5354 | serge | 848 | * only when enabled via module parameter. |
5060 | serge | 849 | * |
850 | * Return: true if the ring requires software command parsing |
||
851 | */ |
||
852 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring) |
||
853 | { |
||
854 | if (!ring->needs_cmd_parser) |
||
855 | return false; |
||
856 | |||
5354 | serge | 857 | if (!USES_PPGTT(ring->dev)) |
5060 | serge | 858 | return false; |
859 | |||
860 | return (i915.enable_cmd_parser == 1); |
||
861 | } |
||
862 | |||
863 | static bool check_cmd(const struct intel_engine_cs *ring, |
||
864 | const struct drm_i915_cmd_descriptor *desc, |
||
865 | const u32 *cmd, |
||
866 | const bool is_master, |
||
867 | bool *oacontrol_set) |
||
868 | { |
||
869 | if (desc->flags & CMD_DESC_REJECT) { |
||
870 | DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); |
||
871 | return false; |
||
872 | } |
||
873 | |||
874 | if ((desc->flags & CMD_DESC_MASTER) && !is_master) { |
||
875 | DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", |
||
876 | *cmd); |
||
877 | return false; |
||
878 | } |
||
879 | |||
880 | if (desc->flags & CMD_DESC_REGISTER) { |
||
881 | u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask; |
||
882 | |||
883 | /* |
||
884 | * OACONTROL requires some special handling for writes. We |
||
885 | * want to make sure that any batch which enables OA also |
||
886 | * disables it before the end of the batch. The goal is to |
||
887 | * prevent one process from snooping on the perf data from |
||
888 | * another process. To do that, we need to check the value |
||
889 | * that will be written to the register. Hence, limit |
||
890 | * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands. |
||
891 | */ |
||
892 | if (reg_addr == OACONTROL) { |
||
5354 | serge | 893 | if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { |
894 | DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); |
||
5060 | serge | 895 | return false; |
5354 | serge | 896 | } |
5060 | serge | 897 | |
898 | if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) |
||
899 | *oacontrol_set = (cmd[2] != 0); |
||
900 | } |
||
901 | |||
902 | if (!valid_reg(ring->reg_table, |
||
903 | ring->reg_count, reg_addr)) { |
||
904 | if (!is_master || |
||
905 | !valid_reg(ring->master_reg_table, |
||
906 | ring->master_reg_count, |
||
907 | reg_addr)) { |
||
908 | DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", |
||
909 | reg_addr, |
||
910 | *cmd, |
||
911 | ring->id); |
||
912 | return false; |
||
913 | } |
||
914 | } |
||
915 | } |
||
916 | |||
917 | if (desc->flags & CMD_DESC_BITMASK) { |
||
918 | int i; |
||
919 | |||
920 | for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { |
||
921 | u32 dword; |
||
922 | |||
923 | if (desc->bits[i].mask == 0) |
||
924 | break; |
||
925 | |||
926 | if (desc->bits[i].condition_mask != 0) { |
||
927 | u32 offset = |
||
928 | desc->bits[i].condition_offset; |
||
929 | u32 condition = cmd[offset] & |
||
930 | desc->bits[i].condition_mask; |
||
931 | |||
932 | if (condition == 0) |
||
933 | continue; |
||
934 | } |
||
935 | |||
936 | dword = cmd[desc->bits[i].offset] & |
||
937 | desc->bits[i].mask; |
||
938 | |||
939 | if (dword != desc->bits[i].expected) { |
||
940 | DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", |
||
941 | *cmd, |
||
942 | desc->bits[i].mask, |
||
943 | desc->bits[i].expected, |
||
944 | dword, ring->id); |
||
945 | return false; |
||
946 | } |
||
947 | } |
||
948 | } |
||
949 | |||
950 | return true; |
||
951 | } |
||
952 | |||
953 | #define LENGTH_BIAS 2 |
||
954 | |||
955 | #if 0 |
||
956 | /** |
||
957 | * i915_parse_cmds() - parse a submitted batch buffer for privilege violations |
||
958 | * @ring: the ring on which the batch is to execute |
||
959 | * @batch_obj: the batch buffer in question |
||
960 | * @batch_start_offset: byte offset in the batch at which execution starts |
||
961 | * @is_master: is the submitting process the drm master? |
||
962 | * |
||
963 | * Parses the specified batch buffer looking for privilege violations as |
||
964 | * described in the overview. |
||
965 | * |
||
5354 | serge | 966 | * Return: non-zero if the parser finds violations or otherwise fails; -EACCES |
967 | * if the batch appears legal but should use hardware parsing |
||
5060 | serge | 968 | */ |
969 | int i915_parse_cmds(struct intel_engine_cs *ring, |
||
970 | struct drm_i915_gem_object *batch_obj, |
||
971 | u32 batch_start_offset, |
||
972 | bool is_master) |
||
973 | { |
||
974 | int ret = 0; |
||
975 | u32 *cmd, *batch_base, *batch_end; |
||
976 | struct drm_i915_cmd_descriptor default_desc = { 0 }; |
||
977 | int needs_clflush = 0; |
||
978 | bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ |
||
979 | |||
980 | ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush); |
||
981 | if (ret) { |
||
982 | DRM_DEBUG_DRIVER("CMD: failed to prep read\n"); |
||
983 | return ret; |
||
984 | } |
||
985 | |||
986 | batch_base = vmap_batch(batch_obj); |
||
987 | if (!batch_base) { |
||
988 | DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); |
||
989 | i915_gem_object_unpin_pages(batch_obj); |
||
990 | return -ENOMEM; |
||
991 | } |
||
992 | |||
993 | if (needs_clflush) |
||
994 | drm_clflush_virt_range((char *)batch_base, batch_obj->base.size); |
||
995 | |||
996 | cmd = batch_base + (batch_start_offset / sizeof(*cmd)); |
||
997 | batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end)); |
||
998 | |||
999 | while (cmd < batch_end) { |
||
1000 | const struct drm_i915_cmd_descriptor *desc; |
||
1001 | u32 length; |
||
1002 | |||
1003 | if (*cmd == MI_BATCH_BUFFER_END) |
||
1004 | break; |
||
1005 | |||
1006 | desc = find_cmd(ring, *cmd, &default_desc); |
||
1007 | if (!desc) { |
||
1008 | DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", |
||
1009 | *cmd); |
||
1010 | ret = -EINVAL; |
||
1011 | break; |
||
1012 | } |
||
1013 | |||
5354 | serge | 1014 | /* |
1015 | * If the batch buffer contains a chained batch, return an |
||
1016 | * error that tells the caller to abort and dispatch the |
||
1017 | * workload as a non-secure batch. |
||
1018 | */ |
||
1019 | if (desc->cmd.value == MI_BATCH_BUFFER_START) { |
||
1020 | ret = -EACCES; |
||
1021 | break; |
||
1022 | } |
||
1023 | |||
5060 | serge | 1024 | if (desc->flags & CMD_DESC_FIXED) |
1025 | length = desc->length.fixed; |
||
1026 | else |
||
1027 | length = ((*cmd & desc->length.mask) + LENGTH_BIAS); |
||
1028 | |||
1029 | if ((batch_end - cmd) < length) { |
||
1030 | DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", |
||
1031 | *cmd, |
||
1032 | length, |
||
1033 | batch_end - cmd); |
||
1034 | ret = -EINVAL; |
||
1035 | break; |
||
1036 | } |
||
1037 | |||
1038 | if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) { |
||
1039 | ret = -EINVAL; |
||
1040 | break; |
||
1041 | } |
||
1042 | |||
1043 | cmd += length; |
||
1044 | } |
||
1045 | |||
1046 | if (oacontrol_set) { |
||
1047 | DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); |
||
1048 | ret = -EINVAL; |
||
1049 | } |
||
1050 | |||
1051 | if (cmd >= batch_end) { |
||
1052 | DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); |
||
1053 | ret = -EINVAL; |
||
1054 | } |
||
1055 | |||
1056 | // vunmap(batch_base); |
||
1057 | |||
1058 | i915_gem_object_unpin_pages(batch_obj); |
||
1059 | |||
1060 | return ret; |
||
1061 | } |
||
1062 | #endif |
||
1063 | |||
1064 | /** |
||
1065 | * i915_cmd_parser_get_version() - get the cmd parser version number |
||
1066 | * |
||
1067 | * The cmd parser maintains a simple increasing integer version number suitable |
||
1068 | * for passing to userspace clients to determine what operations are permitted. |
||
1069 | * |
||
1070 | * Return: the current version number of the cmd parser |
||
1071 | */ |
||
1072 | int i915_cmd_parser_get_version(void) |
||
1073 | { |
||
1074 | /* |
||
1075 | * Command parser version history |
||
1076 | * |
||
1077 | * 1. Initial version. Checks batches and reports violations, but leaves |
||
1078 | * hardware parsing enabled (so does not allow new use cases). |
||
5354 | serge | 1079 | * 2. Allow access to the MI_PREDICATE_SRC0 and |
1080 | * MI_PREDICATE_SRC1 registers. |
||
5060 | serge | 1081 | */ |
5354 | serge | 1082 | return 2; |
5060 | serge | 1083 | }>>>>>>>>>>> |