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2330 | Serge | 1 | /* |
2 | * Copyright © 2006 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "dvo.h" |
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29 | |||
30 | #define CH7017_TV_DISPLAY_MODE 0x00 |
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31 | #define CH7017_FLICKER_FILTER 0x01 |
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32 | #define CH7017_VIDEO_BANDWIDTH 0x02 |
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33 | #define CH7017_TEXT_ENHANCEMENT 0x03 |
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34 | #define CH7017_START_ACTIVE_VIDEO 0x04 |
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35 | #define CH7017_HORIZONTAL_POSITION 0x05 |
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36 | #define CH7017_VERTICAL_POSITION 0x06 |
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37 | #define CH7017_BLACK_LEVEL 0x07 |
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38 | #define CH7017_CONTRAST_ENHANCEMENT 0x08 |
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39 | #define CH7017_TV_PLL 0x09 |
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40 | #define CH7017_TV_PLL_M 0x0a |
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41 | #define CH7017_TV_PLL_N 0x0b |
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42 | #define CH7017_SUB_CARRIER_0 0x0c |
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43 | #define CH7017_CIV_CONTROL 0x10 |
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44 | #define CH7017_CIV_0 0x11 |
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45 | #define CH7017_CHROMA_BOOST 0x14 |
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46 | #define CH7017_CLOCK_MODE 0x1c |
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47 | #define CH7017_INPUT_CLOCK 0x1d |
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48 | #define CH7017_GPIO_CONTROL 0x1e |
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49 | #define CH7017_INPUT_DATA_FORMAT 0x1f |
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50 | #define CH7017_CONNECTION_DETECT 0x20 |
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51 | #define CH7017_DAC_CONTROL 0x21 |
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52 | #define CH7017_BUFFERED_CLOCK_OUTPUT 0x22 |
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53 | #define CH7017_DEFEAT_VSYNC 0x47 |
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54 | #define CH7017_TEST_PATTERN 0x48 |
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55 | |||
56 | #define CH7017_POWER_MANAGEMENT 0x49 |
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57 | /** Enables the TV output path. */ |
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58 | #define CH7017_TV_EN (1 << 0) |
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59 | #define CH7017_DAC0_POWER_DOWN (1 << 1) |
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60 | #define CH7017_DAC1_POWER_DOWN (1 << 2) |
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61 | #define CH7017_DAC2_POWER_DOWN (1 << 3) |
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62 | #define CH7017_DAC3_POWER_DOWN (1 << 4) |
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63 | /** Powers down the TV out block, and DAC0-3 */ |
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64 | #define CH7017_TV_POWER_DOWN_EN (1 << 5) |
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65 | |||
66 | #define CH7017_VERSION_ID 0x4a |
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67 | |||
68 | #define CH7017_DEVICE_ID 0x4b |
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69 | #define CH7017_DEVICE_ID_VALUE 0x1b |
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70 | #define CH7018_DEVICE_ID_VALUE 0x1a |
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71 | #define CH7019_DEVICE_ID_VALUE 0x19 |
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72 | |||
73 | #define CH7017_XCLK_D2_ADJUST 0x53 |
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74 | #define CH7017_UP_SCALER_COEFF_0 0x55 |
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75 | #define CH7017_UP_SCALER_COEFF_1 0x56 |
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76 | #define CH7017_UP_SCALER_COEFF_2 0x57 |
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77 | #define CH7017_UP_SCALER_COEFF_3 0x58 |
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78 | #define CH7017_UP_SCALER_COEFF_4 0x59 |
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79 | #define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a |
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80 | #define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b |
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81 | #define CH7017_GPIO_INVERT 0x5c |
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82 | #define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d |
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83 | #define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e |
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84 | |||
85 | #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f |
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86 | /**< Low bits of horizontal active pixel input */ |
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87 | |||
88 | #define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60 |
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89 | /** High bits of horizontal active pixel input */ |
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90 | #define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0) |
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91 | /** High bits of vertical active line output */ |
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92 | #define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3) |
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93 | |||
94 | #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61 |
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95 | /**< Low bits of vertical active line output */ |
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96 | |||
97 | #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62 |
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98 | /**< Low bits of horizontal active pixel output */ |
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99 | |||
100 | #define CH7017_LVDS_POWER_DOWN 0x63 |
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101 | /** High bits of horizontal active pixel output */ |
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102 | #define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0) |
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103 | /** Enables the LVDS power down state transition */ |
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104 | #define CH7017_LVDS_POWER_DOWN_EN (1 << 6) |
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105 | /** Enables the LVDS upscaler */ |
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106 | #define CH7017_LVDS_UPSCALER_EN (1 << 7) |
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107 | #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08 |
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108 | |||
109 | #define CH7017_LVDS_ENCODING 0x64 |
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110 | #define CH7017_LVDS_DITHER_2D (1 << 2) |
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111 | #define CH7017_LVDS_DITHER_DIS (1 << 3) |
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112 | #define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4) |
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113 | #define CH7017_LVDS_24_BIT (1 << 5) |
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114 | |||
115 | #define CH7017_LVDS_ENCODING_2 0x65 |
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116 | |||
117 | #define CH7017_LVDS_PLL_CONTROL 0x66 |
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118 | /** Enables the LVDS panel output path */ |
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119 | #define CH7017_LVDS_PANEN (1 << 0) |
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120 | /** Enables the LVDS panel backlight */ |
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121 | #define CH7017_LVDS_BKLEN (1 << 3) |
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122 | |||
123 | #define CH7017_POWER_SEQUENCING_T1 0x67 |
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124 | #define CH7017_POWER_SEQUENCING_T2 0x68 |
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125 | #define CH7017_POWER_SEQUENCING_T3 0x69 |
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126 | #define CH7017_POWER_SEQUENCING_T4 0x6a |
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127 | #define CH7017_POWER_SEQUENCING_T5 0x6b |
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128 | #define CH7017_GPIO_DRIVER_TYPE 0x6c |
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129 | #define CH7017_GPIO_DATA 0x6d |
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130 | #define CH7017_GPIO_DIRECTION_CONTROL 0x6e |
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131 | |||
132 | #define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71 |
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133 | # define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4 |
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134 | # define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0 |
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135 | # define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80 |
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136 | |||
137 | #define CH7017_LVDS_PLL_VCO_CONTROL 0x72 |
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138 | # define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80 |
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139 | # define CH7017_LVDS_PLL_VCO_SHIFT 4 |
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140 | # define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0 |
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141 | |||
142 | #define CH7017_OUTPUTS_ENABLE 0x73 |
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143 | # define CH7017_CHARGE_PUMP_LOW 0x0 |
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144 | # define CH7017_CHARGE_PUMP_HIGH 0x3 |
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145 | # define CH7017_LVDS_CHANNEL_A (1 << 3) |
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146 | # define CH7017_LVDS_CHANNEL_B (1 << 4) |
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147 | # define CH7017_TV_DAC_A (1 << 5) |
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148 | # define CH7017_TV_DAC_B (1 << 6) |
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149 | # define CH7017_DDC_SELECT_DC2 (1 << 7) |
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150 | |||
151 | #define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74 |
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152 | #define CH7017_LVDS_PLL_EMI_REDUCTION 0x75 |
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153 | #define CH7017_LVDS_POWER_DOWN_FLICKER 0x76 |
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154 | |||
155 | #define CH7017_LVDS_CONTROL_2 0x78 |
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156 | # define CH7017_LOOP_FILTER_SHIFT 5 |
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157 | # define CH7017_PHASE_DETECTOR_SHIFT 0 |
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158 | |||
159 | #define CH7017_BANG_LIMIT_CONTROL 0x7f |
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160 | |||
161 | struct ch7017_priv { |
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162 | uint8_t dummy; |
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163 | }; |
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164 | |||
165 | static void ch7017_dump_regs(struct intel_dvo_device *dvo); |
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166 | static void ch7017_dpms(struct intel_dvo_device *dvo, int mode); |
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167 | |||
168 | static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val) |
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169 | { |
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170 | struct i2c_msg msgs[] = { |
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171 | { |
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172 | .addr = dvo->slave_addr, |
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173 | .flags = 0, |
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174 | .len = 1, |
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175 | .buf = &addr, |
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176 | }, |
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177 | { |
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178 | .addr = dvo->slave_addr, |
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179 | .flags = I2C_M_RD, |
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180 | .len = 1, |
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181 | .buf = val, |
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182 | } |
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183 | }; |
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184 | return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2; |
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185 | } |
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186 | |||
187 | static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val) |
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188 | { |
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189 | uint8_t buf[2] = { addr, val }; |
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190 | struct i2c_msg msg = { |
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191 | .addr = dvo->slave_addr, |
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192 | .flags = 0, |
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193 | .len = 2, |
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194 | .buf = buf, |
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195 | }; |
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196 | return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1; |
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197 | } |
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198 | |||
199 | /** Probes for a CH7017 on the given bus and slave address. */ |
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200 | static bool ch7017_init(struct intel_dvo_device *dvo, |
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201 | struct i2c_adapter *adapter) |
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202 | { |
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203 | struct ch7017_priv *priv; |
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204 | const char *str; |
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205 | u8 val; |
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206 | |||
207 | priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL); |
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208 | if (priv == NULL) |
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209 | return false; |
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210 | |||
211 | dvo->i2c_bus = adapter; |
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212 | dvo->dev_priv = priv; |
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213 | |||
214 | if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) |
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215 | goto fail; |
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216 | |||
217 | switch (val) { |
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218 | case CH7017_DEVICE_ID_VALUE: |
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219 | str = "ch7017"; |
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220 | break; |
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221 | case CH7018_DEVICE_ID_VALUE: |
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222 | str = "ch7018"; |
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223 | break; |
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224 | case CH7019_DEVICE_ID_VALUE: |
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225 | str = "ch7019"; |
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226 | break; |
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227 | default: |
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228 | DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " |
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229 | "slave %d.\n", |
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230 | val, adapter->name,dvo->slave_addr); |
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231 | goto fail; |
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232 | } |
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233 | |||
234 | DRM_DEBUG_KMS("%s detected on %s, addr %d\n", |
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235 | str, adapter->name, dvo->slave_addr); |
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236 | return true; |
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237 | |||
238 | fail: |
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239 | kfree(priv); |
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240 | return false; |
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241 | } |
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242 | |||
243 | static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo) |
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244 | { |
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245 | return connector_status_connected; |
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246 | } |
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247 | |||
248 | static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo, |
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249 | struct drm_display_mode *mode) |
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250 | { |
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251 | if (mode->clock > 160000) |
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252 | return MODE_CLOCK_HIGH; |
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253 | |||
254 | return MODE_OK; |
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255 | } |
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256 | |||
257 | static void ch7017_mode_set(struct intel_dvo_device *dvo, |
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258 | struct drm_display_mode *mode, |
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259 | struct drm_display_mode *adjusted_mode) |
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260 | { |
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261 | uint8_t lvds_pll_feedback_div, lvds_pll_vco_control; |
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262 | uint8_t outputs_enable, lvds_control_2, lvds_power_down; |
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263 | uint8_t horizontal_active_pixel_input; |
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264 | uint8_t horizontal_active_pixel_output, vertical_active_line_output; |
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265 | uint8_t active_input_line_output; |
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266 | |||
267 | DRM_DEBUG_KMS("Registers before mode setting\n"); |
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268 | ch7017_dump_regs(dvo); |
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269 | |||
270 | /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ |
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271 | if (mode->clock < 100000) { |
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272 | outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW; |
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273 | lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | |
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274 | (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | |
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275 | (13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); |
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276 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | |
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277 | (2 << CH7017_LVDS_PLL_VCO_SHIFT) | |
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278 | (3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); |
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279 | lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) | |
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280 | (0 << CH7017_PHASE_DETECTOR_SHIFT); |
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281 | } else { |
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282 | outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH; |
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283 | lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | |
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284 | (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | |
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285 | (3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); |
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286 | lvds_pll_feedback_div = 35; |
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287 | lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) | |
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288 | (0 << CH7017_PHASE_DETECTOR_SHIFT); |
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289 | if (1) { /* XXX: dual channel panel detection. Assume yes for now. */ |
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290 | outputs_enable |= CH7017_LVDS_CHANNEL_B; |
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291 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | |
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292 | (2 << CH7017_LVDS_PLL_VCO_SHIFT) | |
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293 | (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); |
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294 | } else { |
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295 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | |
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296 | (1 << CH7017_LVDS_PLL_VCO_SHIFT) | |
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297 | (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); |
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298 | } |
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299 | } |
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300 | |||
301 | horizontal_active_pixel_input = mode->hdisplay & 0x00ff; |
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302 | |||
303 | vertical_active_line_output = mode->vdisplay & 0x00ff; |
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304 | horizontal_active_pixel_output = mode->hdisplay & 0x00ff; |
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305 | |||
306 | active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) | |
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307 | (((mode->vdisplay & 0x0700) >> 8) << 3); |
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308 | |||
309 | lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED | |
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310 | (mode->hdisplay & 0x0700) >> 8; |
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311 | |||
312 | ch7017_dpms(dvo, DRM_MODE_DPMS_OFF); |
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313 | ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, |
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314 | horizontal_active_pixel_input); |
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315 | ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT, |
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316 | horizontal_active_pixel_output); |
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317 | ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, |
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318 | vertical_active_line_output); |
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319 | ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, |
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320 | active_input_line_output); |
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321 | ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control); |
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322 | ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div); |
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323 | ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2); |
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324 | ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable); |
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325 | |||
326 | /* Turn the LVDS back on with new settings. */ |
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327 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); |
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328 | |||
329 | DRM_DEBUG_KMS("Registers after mode setting\n"); |
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330 | ch7017_dump_regs(dvo); |
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331 | } |
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332 | |||
333 | /* set the CH7017 power state */ |
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334 | static void ch7017_dpms(struct intel_dvo_device *dvo, int mode) |
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335 | { |
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336 | uint8_t val; |
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337 | |||
338 | ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); |
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339 | |||
340 | /* Turn off TV/VGA, and never turn it on since we don't support it. */ |
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341 | ch7017_write(dvo, CH7017_POWER_MANAGEMENT, |
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342 | CH7017_DAC0_POWER_DOWN | |
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343 | CH7017_DAC1_POWER_DOWN | |
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344 | CH7017_DAC2_POWER_DOWN | |
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345 | CH7017_DAC3_POWER_DOWN | |
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346 | CH7017_TV_POWER_DOWN_EN); |
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347 | |||
348 | if (mode == DRM_MODE_DPMS_ON) { |
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349 | /* Turn on the LVDS */ |
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350 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, |
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351 | val & ~CH7017_LVDS_POWER_DOWN_EN); |
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352 | } else { |
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353 | /* Turn off the LVDS */ |
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354 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, |
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355 | val | CH7017_LVDS_POWER_DOWN_EN); |
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356 | } |
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357 | |||
358 | /* XXX: Should actually wait for update power status somehow */ |
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359 | msleep(20); |
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360 | } |
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361 | |||
362 | static void ch7017_dump_regs(struct intel_dvo_device *dvo) |
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363 | { |
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364 | uint8_t val; |
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365 | |||
366 | #define DUMP(reg) \ |
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367 | do { \ |
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368 | ch7017_read(dvo, reg, &val); \ |
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369 | DRM_DEBUG_KMS(#reg ": %02x\n", val); \ |
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370 | } while (0) |
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371 | |||
372 | DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); |
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373 | DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT); |
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374 | DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT); |
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375 | DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT); |
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376 | DUMP(CH7017_LVDS_PLL_VCO_CONTROL); |
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377 | DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV); |
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378 | DUMP(CH7017_LVDS_CONTROL_2); |
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379 | DUMP(CH7017_OUTPUTS_ENABLE); |
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380 | DUMP(CH7017_LVDS_POWER_DOWN); |
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381 | } |
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382 | |||
383 | static void ch7017_destroy(struct intel_dvo_device *dvo) |
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384 | { |
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385 | struct ch7017_priv *priv = dvo->dev_priv; |
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386 | |||
387 | if (priv) { |
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388 | kfree(priv); |
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389 | dvo->dev_priv = NULL; |
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390 | } |
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391 | } |
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392 | |||
393 | struct intel_dvo_dev_ops ch7017_ops = { |
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394 | .init = ch7017_init, |
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395 | .detect = ch7017_detect, |
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396 | .mode_valid = ch7017_mode_valid, |
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397 | .mode_set = ch7017_mode_set, |
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398 | .dpms = ch7017_dpms, |
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399 | .dump_regs = ch7017_dump_regs, |
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400 | .destroy = ch7017_destroy, |
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401 | };><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>>><>><>><>><>><>><> |