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4104 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | /* |
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28 | * Authors: Thomas Hellström |
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29 | */ |
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30 | |||
31 | #include |
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32 | #include |
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33 | |||
34 | extern int x86_clflush_size; |
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35 | |||
4293 | Serge | 36 | |
4104 | Serge | 37 | #if 0 |
38 | static void |
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39 | drm_clflush_page(struct page *page) |
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40 | { |
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41 | uint8_t *page_virtual; |
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42 | unsigned int i; |
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43 | const int size = boot_cpu_data.x86_clflush_size; |
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44 | |||
45 | if (unlikely(page == NULL)) |
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46 | return; |
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47 | |||
48 | page_virtual = kmap_atomic(page); |
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49 | for (i = 0; i < PAGE_SIZE; i += size) |
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50 | clflush(page_virtual + i); |
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51 | kunmap_atomic(page_virtual); |
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52 | } |
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53 | |||
54 | static void drm_cache_flush_clflush(struct page *pages[], |
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55 | unsigned long num_pages) |
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56 | { |
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57 | unsigned long i; |
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58 | |||
59 | mb(); |
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60 | for (i = 0; i < num_pages; i++) |
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61 | drm_clflush_page(*pages++); |
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62 | mb(); |
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63 | } |
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64 | #endif |
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65 | |||
66 | void |
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67 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) |
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68 | { |
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4293 | Serge | 69 | uint8_t *pva; |
4104 | Serge | 70 | unsigned int i, j; |
71 | |||
4293 | Serge | 72 | pva = AllocKernelSpace(4096); |
4104 | Serge | 73 | |
4293 | Serge | 74 | if(pva != NULL) |
4104 | Serge | 75 | { |
76 | dma_addr_t *src, *dst; |
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77 | u32 count; |
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78 | |||
79 | for (i = 0; i < num_pages; i++) |
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80 | { |
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81 | mb(); |
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4293 | Serge | 82 | MapPage(pva, page_to_phys(pages[i]), 0x001); |
4104 | Serge | 83 | for (j = 0; j < PAGE_SIZE; j += x86_clflush_size) |
4293 | Serge | 84 | clflush(pva + j); |
4104 | Serge | 85 | } |
4293 | Serge | 86 | FreeKernelSpace(pva); |
4104 | Serge | 87 | } |
4293 | Serge | 88 | mb(); |
4104 | Serge | 89 | } |
90 | EXPORT_SYMBOL(drm_clflush_pages); |
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91 | |||
92 | void |
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93 | drm_clflush_sg(struct sg_table *st) |
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94 | { |
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4539 | Serge | 95 | struct sg_page_iter sg_iter; |
4293 | Serge | 96 | struct page *page; |
4104 | Serge | 97 | |
4293 | Serge | 98 | uint8_t *pva; |
99 | unsigned int i; |
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100 | |||
101 | pva = AllocKernelSpace(4096); |
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102 | if( pva != NULL) |
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103 | { |
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4539 | Serge | 104 | mb(); |
105 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
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4293 | Serge | 106 | { |
107 | page = sg_page_iter_page(&sg_iter); |
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4104 | Serge | 108 | |
4293 | Serge | 109 | MapPage(pva,page_to_phys(page), 0x001); |
4104 | Serge | 110 | |
4293 | Serge | 111 | for (i = 0; i < PAGE_SIZE; i += x86_clflush_size) |
112 | clflush(pva + i); |
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113 | }; |
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114 | FreeKernelSpace(pva); |
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115 | }; |
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116 | mb(); |
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4104 | Serge | 117 | } |
118 | EXPORT_SYMBOL(drm_clflush_sg); |
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119 | |||
4293 | Serge | 120 | #if 0 |
4104 | Serge | 121 | void |
6084 | serge | 122 | drm_clflush_virt_range(void *addr, unsigned long length) |
4104 | Serge | 123 | { |
124 | #if defined(CONFIG_X86) |
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125 | if (cpu_has_clflush) { |
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6084 | serge | 126 | const int size = boot_cpu_data.x86_clflush_size; |
127 | void *end = addr + length; |
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128 | addr = (void *)(((unsigned long)addr) & -size); |
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4104 | Serge | 129 | mb(); |
6084 | serge | 130 | for (; addr < end; addr += size) |
131 | clflushopt(addr); |
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4104 | Serge | 132 | mb(); |
133 | return; |
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134 | } |
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135 | |||
6084 | serge | 136 | if (wbinvd_on_all_cpus()) |
4104 | Serge | 137 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
138 | #else |
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139 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
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140 | WARN_ON_ONCE(1); |
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141 | #endif |
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142 | } |
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143 | EXPORT_SYMBOL(drm_clflush_virt_range); |
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144 | |||
145 | #endif>>>>>> |