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4104 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | /* |
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28 | * Authors: Thomas Hellström |
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29 | */ |
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30 | |||
31 | #include |
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32 | #include |
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33 | |||
34 | extern int x86_clflush_size; |
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35 | |||
36 | static inline void clflush(volatile void *__p) |
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37 | { |
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38 | asm volatile("clflush %0" : "+m" (*(volatile char*)__p)); |
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39 | } |
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40 | #if 0 |
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41 | static void |
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42 | drm_clflush_page(struct page *page) |
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43 | { |
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44 | uint8_t *page_virtual; |
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45 | unsigned int i; |
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46 | const int size = boot_cpu_data.x86_clflush_size; |
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47 | |||
48 | if (unlikely(page == NULL)) |
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49 | return; |
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50 | |||
51 | page_virtual = kmap_atomic(page); |
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52 | for (i = 0; i < PAGE_SIZE; i += size) |
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53 | clflush(page_virtual + i); |
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54 | kunmap_atomic(page_virtual); |
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55 | } |
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56 | |||
57 | static void drm_cache_flush_clflush(struct page *pages[], |
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58 | unsigned long num_pages) |
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59 | { |
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60 | unsigned long i; |
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61 | |||
62 | mb(); |
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63 | for (i = 0; i < num_pages; i++) |
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64 | drm_clflush_page(*pages++); |
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65 | mb(); |
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66 | } |
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67 | |||
68 | static void |
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69 | drm_clflush_ipi_handler(void *null) |
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70 | { |
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71 | wbinvd(); |
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72 | } |
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73 | #endif |
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74 | |||
75 | void |
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76 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) |
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77 | { |
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78 | uint8_t *page_virtual; |
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79 | unsigned int i, j; |
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80 | |||
81 | page_virtual = AllocKernelSpace(4096); |
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82 | |||
83 | if(page_virtual != NULL) |
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84 | { |
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85 | dma_addr_t *src, *dst; |
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86 | u32 count; |
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87 | |||
88 | for (i = 0; i < num_pages; i++) |
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89 | { |
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90 | mb(); |
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91 | // asm volatile("mfence"); |
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92 | |||
93 | MapPage(page_virtual,*pages++, 0x001); |
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94 | for (j = 0; j < PAGE_SIZE; j += x86_clflush_size) |
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95 | clflush(page_virtual + j); |
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96 | mb(); |
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97 | } |
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98 | FreeKernelSpace(page_virtual); |
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99 | } |
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100 | |||
101 | } |
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102 | EXPORT_SYMBOL(drm_clflush_pages); |
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103 | |||
104 | #if 0 |
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105 | void |
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106 | drm_clflush_sg(struct sg_table *st) |
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107 | { |
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108 | #if defined(CONFIG_X86) |
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109 | if (cpu_has_clflush) { |
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110 | struct sg_page_iter sg_iter; |
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111 | |||
112 | mb(); |
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113 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
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114 | drm_clflush_page(sg_page_iter_page(&sg_iter)); |
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115 | mb(); |
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116 | |||
117 | return; |
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118 | } |
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119 | |||
120 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
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121 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
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122 | #else |
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123 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
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124 | WARN_ON_ONCE(1); |
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125 | #endif |
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126 | } |
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127 | EXPORT_SYMBOL(drm_clflush_sg); |
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128 | |||
129 | void |
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130 | drm_clflush_virt_range(char *addr, unsigned long length) |
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131 | { |
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132 | #if defined(CONFIG_X86) |
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133 | if (cpu_has_clflush) { |
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134 | char *end = addr + length; |
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135 | mb(); |
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136 | for (; addr < end; addr += boot_cpu_data.x86_clflush_size) |
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137 | clflush(addr); |
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138 | clflush(end - 1); |
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139 | mb(); |
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140 | return; |
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141 | } |
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142 | |||
143 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
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144 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
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145 | #else |
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146 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
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147 | WARN_ON_ONCE(1); |
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148 | #endif |
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149 | } |
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150 | EXPORT_SYMBOL(drm_clflush_virt_range); |
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151 | |||
152 | #endif>>>>> |