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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | #define RADEON_SCRATCH_REG0 0x15e0 |
| 2 | #define RADEON_SCRATCH_REG1 0x15e4 |
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| 3 | #define RADEON_SCRATCH_REG2 0x15e8 |
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| 4 | #define RADEON_SCRATCH_REG3 0x15ec |
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| 5 | #define RADEON_SCRATCH_REG4 0x15f0 |
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| 6 | #define RADEON_SCRATCH_REG5 0x15f4 |
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| 7 | #define RADEON_SCRATCH_UMSK 0x0770 |
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| 8 | #define RADEON_SCRATCH_ADDR 0x0774 |
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| 9 | |||
| 10 | # define RS400_BUS_MASTER_DIS (1 << 14) |
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| 11 | //# define RADEON_BUS_MASTER_DIS (1 << 6) |
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| 12 | |||
| 13 | #define RADEON_ISYNC_CNTL 0x1724 |
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| 14 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
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| 15 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
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| 16 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
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| 17 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
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| 18 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
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| 19 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
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| 20 | |||
| 21 | |||
| 22 | void RADEONEngineFlush(RHDPtr info) |
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| 23 | { |
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| 24 | int i; |
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| 25 | |||
| 26 | if (info->ChipFamily <= CHIP_FAMILY_RV280) |
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| 27 | { |
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| 28 | MASKREG(RADEON_RB3D_DSTCACHE_CTLSTAT,RADEON_RB3D_DC_FLUSH_ALL, |
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| 29 | ~RADEON_RB3D_DC_FLUSH_ALL); |
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| 30 | for (i = 0; i < RADEON_TIMEOUT; i++) { |
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| 31 | if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) |
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| 32 | break; |
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| 33 | } |
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| 34 | if (i == RADEON_TIMEOUT) { |
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| 35 | dbgprintf("DC flush timeout: %x\n", |
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| 36 | (u32_t)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); |
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| 37 | } |
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| 38 | } |
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| 39 | else |
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| 40 | { |
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| 41 | // MASKREG(R300_DSTCACHE_CTLSTAT,R300_RB2D_DC_FLUSH_ALL, |
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| 42 | // ~R300_RB2D_DC_FLUSH_ALL); |
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| 43 | // for (i = 0; i < RADEON_TIMEOUT; i++) { |
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| 44 | // if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) |
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| 45 | // break; |
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| 46 | // } |
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| 47 | // if (i == RADEON_TIMEOUT) { |
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| 48 | // dbgprintf("DC flush timeout: %x\n", |
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| 49 | // (u32_t)INREG(R300_DSTCACHE_CTLSTAT)); |
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| 50 | // } |
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| 51 | } |
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| 52 | } |
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| 53 | |||
| 54 | |||
| 55 | static int radeon_do_wait_for_idle() |
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| 56 | { |
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| 57 | int i, ret; |
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| 58 | |||
| 59 | ret = R5xxFIFOWaitLocal(64); |
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| 60 | if (ret) |
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| 61 | return ret; |
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| 62 | |||
| 63 | for (i = 0; i < RADEON_TIMEOUT; i++) |
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| 64 | { |
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| 65 | if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { |
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| 66 | RADEONEngineFlush(&rhd); |
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| 67 | return 0; |
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| 68 | } |
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| 69 | usleep(1); |
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| 70 | } |
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| 71 | dbgprintf("wait idle failed status : 0x%08X 0x%08X\n", |
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| 72 | INREG(RADEON_RBBM_STATUS), |
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| 73 | INREG(R300_VAP_CNTL_STATUS)); |
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| 74 | |||
| 75 | return 1; |
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| 76 | } |
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| 77 | |||
| 78 | |||
| 79 | |||
| 80 | /* ================================================================ |
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| 81 | * CP control, initialization |
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| 82 | */ |
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| 83 | |||
| 84 | /* Load the microcode for the CP */ |
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| 85 | |||
| 86 | #include "radeon_microcode.h" |
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| 87 | |||
| 88 | static void load_microcode(RHDPtr info) |
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| 89 | { |
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| 90 | int i; |
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| 91 | const u32_t (*microcode)[2]; |
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| 92 | |||
| 93 | OUTREG(RADEON_CP_ME_RAM_ADDR, 0); |
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| 94 | |||
| 95 | if ( (info->ChipFamily == CHIP_FAMILY_LEGACY ) || |
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| 96 | (info->ChipFamily == CHIP_FAMILY_RADEON ) || |
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| 97 | (info->ChipFamily == CHIP_FAMILY_RV100 ) || |
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| 98 | (info->ChipFamily == CHIP_FAMILY_RV200 ) || |
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| 99 | (info->ChipFamily == CHIP_FAMILY_RS100 ) || |
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| 100 | (info->ChipFamily == CHIP_FAMILY_RS200 )) |
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| 101 | { |
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| 102 | microcode = R100_cp_microcode; |
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| 103 | dbgprintf("Loading R100 Microcode\n"); |
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| 104 | } |
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| 105 | else if ((info->ChipFamily == CHIP_FAMILY_R200 ) || |
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| 106 | (info->ChipFamily == CHIP_FAMILY_RV250) || |
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| 107 | (info->ChipFamily == CHIP_FAMILY_RV280) || |
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| 108 | (info->ChipFamily == CHIP_FAMILY_RS300)) |
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| 109 | { |
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| 110 | microcode = R200_cp_microcode; |
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| 111 | dbgprintf("Loading R200 Microcode\n"); |
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| 112 | } |
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| 113 | else if ((info->ChipFamily == CHIP_FAMILY_R300) || |
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| 114 | (info->ChipFamily == CHIP_FAMILY_R350) || |
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| 115 | (info->ChipFamily == CHIP_FAMILY_RV350) || |
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| 116 | (info->ChipFamily == CHIP_FAMILY_RV380) || |
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| 117 | (info->ChipFamily == CHIP_FAMILY_RS400) || |
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| 118 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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| 119 | { |
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| 120 | dbgprintf("Loading R300 Microcode\n"); |
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| 121 | microcode = R300_cp_microcode; |
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| 122 | } |
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| 123 | else if ((info->ChipFamily == CHIP_FAMILY_R420) || |
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| 124 | (info->ChipFamily == CHIP_FAMILY_RV410)) |
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| 125 | { |
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| 126 | dbgprintf("Loading R400 Microcode\n"); |
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| 127 | microcode = R420_cp_microcode; |
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| 128 | |||
| 129 | } |
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| 130 | else if ((info->ChipFamily == CHIP_FAMILY_RS600) || |
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| 131 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 132 | (info->ChipFamily == CHIP_FAMILY_RS740)) |
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| 133 | { |
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| 134 | dbgprintf("Loading RS690/RS740 Microcode\n"); |
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| 135 | microcode = RS690_cp_microcode; |
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| 136 | } |
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| 137 | else if ((info->ChipFamily == CHIP_FAMILY_RV515) || |
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| 138 | (info->ChipFamily == CHIP_FAMILY_R520) || |
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| 139 | (info->ChipFamily == CHIP_FAMILY_RV530) || |
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| 140 | (info->ChipFamily == CHIP_FAMILY_R580) || |
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| 141 | (info->ChipFamily == CHIP_FAMILY_RV560) || |
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| 142 | (info->ChipFamily == CHIP_FAMILY_RV570)) |
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| 143 | { |
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| 144 | dbgprintf("Loading R500 Microcode\n"); |
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| 145 | microcode = R520_cp_microcode; |
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| 146 | } |
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| 147 | |||
| 148 | for (i = 0; i < 256; i++) { |
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| 149 | OUTREG(RADEON_CP_ME_RAM_DATAH, microcode[i][1]); |
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| 150 | OUTREG(RADEON_CP_ME_RAM_DATAL, microcode[i][0]); |
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| 151 | } |
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| 152 | } |
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| 153 | |||
| 154 | |||
| 155 | void init_ring_buffer(RHDPtr info) |
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| 156 | { |
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| 157 | u32_t ring_base; |
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| 158 | u32_t tmp; |
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| 159 | |||
| 160 | info->ringBase = CreateRingBuffer( 64*1024, PG_SW); |
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| 161 | |||
| 162 | dbgprintf("create cp ring buffer %x\n", rhd.ringBase); |
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| 163 | ring_base = GetPgAddr(rhd.ringBase); |
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| 164 | dbgprintf("ring base %x\n", ring_base); |
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| 165 | |||
| 166 | OUTREG(RADEON_CP_RB_BASE, ring_base); |
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| 167 | |||
| 168 | info->ring_avail = 64*1024/4 ; |
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| 169 | |||
| 170 | /* Set the write pointer delay */ |
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| 171 | OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); |
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| 172 | |||
| 173 | /* Initialize the ring buffer's read and write pointers */ |
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| 174 | rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
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| 175 | rhd.host_rp = rhd.ring_rp; |
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| 176 | |||
| 177 | OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
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| 178 | |||
| 179 | tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr((void*)&rhd.host_rp); |
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| 180 | |||
| 181 | OUTREG(RADEON_CP_RB_RPTR_ADDR, tmp); // ring buffer read pointer |
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| 182 | |||
| 183 | /* Set ring buffer size */ |
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| 184 | OUTREG(RADEON_CP_RB_CNTL, (1<<27)|(0<<18)|(10<<8)|13); |
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| 185 | |||
| 186 | /* Initialize the scratch register pointer. This will cause |
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| 187 | * the scratch register values to be written out to memory |
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| 188 | * whenever they are updated. |
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| 189 | * |
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| 190 | * We simply put this behind the ring read pointer, this works |
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| 191 | * with PCI GART as well as (whatever kind of) AGP GART |
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| 192 | */ |
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| 193 | |||
| 194 | tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr((void*)&rhd.scratch0); |
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| 195 | OUTREG(RADEON_SCRATCH_ADDR, tmp); |
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| 196 | |||
| 197 | OUTREG(RADEON_SCRATCH_UMSK, 0x0); |
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| 198 | //OUTREG(0x778, 1); |
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| 199 | |||
| 200 | /* Turn on bus mastering */ |
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| 201 | if ( (info->ChipFamily == CHIP_FAMILY_RS400) || |
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| 202 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 203 | (info->ChipFamily == CHIP_FAMILY_RS740) ) |
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| 204 | { |
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| 205 | /* rs400, rs690/rs740 */ |
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| 206 | tmp = INREG(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; |
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| 207 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 208 | } |
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| 209 | else if (!((info->ChipFamily == CHIP_FAMILY_RV380) || |
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| 210 | (info->ChipFamily >= CHIP_FAMILY_R420))) |
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| 211 | { |
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| 212 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ |
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| 213 | tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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| 214 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 215 | } /* PCIE cards appears to not need this */ |
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| 216 | |||
| 217 | tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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| 218 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 219 | |||
| 220 | radeon_do_wait_for_idle(); |
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| 221 | |||
| 222 | /* Sync everything up */ |
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| 223 | OUTREG(RADEON_ISYNC_CNTL, |
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| 224 | (RADEON_ISYNC_ANY2D_IDLE3D | |
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| 225 | RADEON_ISYNC_ANY3D_IDLE2D | |
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| 226 | RADEON_ISYNC_WAIT_IDLEGUI | |
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| 227 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); |
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| 228 | } |
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| 229 | |||
| 230 | |||
| 231 | |||
| 232 | #define RADEON_WAIT_UNTIL_IDLE() do { \ |
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| 233 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 1 ) ); \ |
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| 234 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ |
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| 235 | RADEON_WAIT_3D_IDLECLEAN | \ |
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| 236 | RADEON_WAIT_HOST_IDLECLEAN) ); \ |
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| 237 | } while (0) |
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| 238 | |||
| 239 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
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| 240 | # define RADEON_RB3D_ZC_FLUSH (1 << 0) |
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| 241 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
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| 242 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
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| 243 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
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| 244 | # define R300_ZC_FLUSH (1 << 0) |
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| 245 | # define R300_ZC_FREE (1 << 1) |
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| 246 | # define R300_ZC_BUSY (1 << 31) |
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| 247 | # define RADEON_RB3D_DC_FLUSH (3 << 0) |
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| 248 | # define RADEON_RB3D_DC_FREE (3 << 2) |
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| 249 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
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| 250 | # define RADEON_RB3D_DC_BUSY (1 << 31) |
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| 251 | # define R300_RB3D_DC_FLUSH (2 << 0) |
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| 252 | # define R300_RB3D_DC_FREE (2 << 2) |
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| 253 | # |
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| 254 | #define RADEON_PURGE_CACHE() do { \ |
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| 255 | if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 256 | OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
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| 257 | OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ |
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| 258 | } else { \ |
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| 259 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
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| 260 | OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ |
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| 261 | } \ |
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| 262 | } while (0) |
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| 263 | |||
| 264 | #define RADEON_FLUSH_ZCACHE() do { \ |
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| 265 | if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 266 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 1 ) ); \ |
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| 267 | OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ |
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| 268 | } else { \ |
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| 269 | OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 1 ) ); \ |
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| 270 | OUT_RING( R300_ZC_FLUSH ); \ |
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| 271 | } \ |
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| 272 | } while (0) |
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| 273 | #define RADEON_PURGE_ZCACHE() do { \ |
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| 274 | if (rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 275 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 1)); \ |
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| 276 | OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ |
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| 277 | } else { \ |
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| 278 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 1)); \ |
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| 279 | OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ |
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| 280 | } \ |
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| 281 | } while (0) |
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| 282 | |||
| 283 | static int radeon_cp_start(RHDPtr info) |
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| 284 | { |
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| 285 | u32_t *ring, write; |
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| 286 | u32_t ifl; |
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| 287 | radeon_do_wait_for_idle(64); |
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| 288 | |||
| 289 | OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
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| 290 | |||
| 291 | ifl = safe_cli(); |
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| 292 | |||
| 293 | BEGIN_RING(8); |
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| 294 | /* isync can only be written through cp on r5xx write it here */ |
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| 295 | OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 1)); |
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| 296 | OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | |
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| 297 | RADEON_ISYNC_ANY3D_IDLE2D | |
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| 298 | RADEON_ISYNC_WAIT_IDLEGUI | |
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| 299 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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| 300 | RADEON_PURGE_CACHE(); |
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| 301 | RADEON_PURGE_ZCACHE(); |
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| 302 | RADEON_WAIT_UNTIL_IDLE(); |
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| 303 | ADVANCE_RING(); |
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| 304 | COMMIT_RING(); |
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| 305 | |||
| 306 | safe_sti(ifl); |
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| 307 | |||
| 308 | radeon_do_wait_for_idle(); |
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| 309 | }; |
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| 310 | |||
| 311 | |||
| 312 | Bool init_cp(RHDPtr info) |
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| 313 | { |
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| 314 | load_microcode(&rhd); |
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| 315 | |||
| 316 | init_ring_buffer(&rhd); |
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| 317 | |||
| 318 | radeon_engine_reset(&rhd); |
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| 319 | |||
| 320 | rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
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| 321 | OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp); |
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| 322 | |||
| 323 | radeon_cp_start(&rhd); |
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| 324 | |||
| 325 | return TRUE; |
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| 326 | }; |
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| 327 | |||
| 328 |